./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/transmitter.03.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 3a877d22 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/transmitter.03.cil.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 4edad7c083448b81b05575191757512095bfff0f094103ddb1a592d0cd702494 --- Real Ultimate output --- This is Ultimate 0.2.2-3a877d227dc491413fd706022d0c47cd97beb353-3a877d2 [2021-12-15 17:21:27,447 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-12-15 17:21:27,450 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-12-15 17:21:27,501 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-12-15 17:21:27,501 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-12-15 17:21:27,502 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-12-15 17:21:27,503 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-12-15 17:21:27,505 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-12-15 17:21:27,506 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-12-15 17:21:27,507 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-12-15 17:21:27,508 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-12-15 17:21:27,510 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-12-15 17:21:27,510 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-12-15 17:21:27,513 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-12-15 17:21:27,515 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-12-15 17:21:27,519 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-12-15 17:21:27,521 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-12-15 17:21:27,526 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-12-15 17:21:27,527 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-12-15 17:21:27,528 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-12-15 17:21:27,529 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-12-15 17:21:27,534 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-12-15 17:21:27,535 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-12-15 17:21:27,536 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-12-15 17:21:27,538 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-12-15 17:21:27,542 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-12-15 17:21:27,543 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-12-15 17:21:27,543 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-12-15 17:21:27,544 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-12-15 17:21:27,545 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-12-15 17:21:27,545 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-12-15 17:21:27,545 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-12-15 17:21:27,546 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-12-15 17:21:27,549 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-12-15 17:21:27,550 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-12-15 17:21:27,550 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-12-15 17:21:27,551 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-12-15 17:21:27,551 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-12-15 17:21:27,551 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-12-15 17:21:27,552 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-12-15 17:21:27,553 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-12-15 17:21:27,554 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2021-12-15 17:21:27,585 INFO L113 SettingsManager]: Loading preferences was successful [2021-12-15 17:21:27,585 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-12-15 17:21:27,586 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2021-12-15 17:21:27,586 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2021-12-15 17:21:27,587 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-12-15 17:21:27,587 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-12-15 17:21:27,588 INFO L138 SettingsManager]: * Use SBE=true [2021-12-15 17:21:27,588 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2021-12-15 17:21:27,588 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2021-12-15 17:21:27,588 INFO L138 SettingsManager]: * Use old map elimination=false [2021-12-15 17:21:27,589 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2021-12-15 17:21:27,589 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2021-12-15 17:21:27,589 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2021-12-15 17:21:27,589 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-12-15 17:21:27,590 INFO L138 SettingsManager]: * sizeof long=4 [2021-12-15 17:21:27,590 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2021-12-15 17:21:27,590 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-12-15 17:21:27,590 INFO L138 SettingsManager]: * sizeof POINTER=4 [2021-12-15 17:21:27,590 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-12-15 17:21:27,590 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2021-12-15 17:21:27,591 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2021-12-15 17:21:27,591 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2021-12-15 17:21:27,591 INFO L138 SettingsManager]: * sizeof long double=12 [2021-12-15 17:21:27,591 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-12-15 17:21:27,591 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2021-12-15 17:21:27,591 INFO L138 SettingsManager]: * Use constant arrays=true [2021-12-15 17:21:27,592 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2021-12-15 17:21:27,592 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-12-15 17:21:27,592 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-12-15 17:21:27,592 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-12-15 17:21:27,592 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-12-15 17:21:27,593 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2021-12-15 17:21:27,593 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2021-12-15 17:21:27,594 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 4edad7c083448b81b05575191757512095bfff0f094103ddb1a592d0cd702494 [2021-12-15 17:21:27,773 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-12-15 17:21:27,794 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-12-15 17:21:27,797 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-12-15 17:21:27,798 INFO L271 PluginConnector]: Initializing CDTParser... [2021-12-15 17:21:27,799 INFO L275 PluginConnector]: CDTParser initialized [2021-12-15 17:21:27,800 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/transmitter.03.cil.c [2021-12-15 17:21:27,853 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/efe936ec5/5459e3dc007f438fa2657255d4a44565/FLAG2a24fc32f [2021-12-15 17:21:28,210 INFO L306 CDTParser]: Found 1 translation units. [2021-12-15 17:21:28,211 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.03.cil.c [2021-12-15 17:21:28,223 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/efe936ec5/5459e3dc007f438fa2657255d4a44565/FLAG2a24fc32f [2021-12-15 17:21:28,613 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/efe936ec5/5459e3dc007f438fa2657255d4a44565 [2021-12-15 17:21:28,616 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-12-15 17:21:28,617 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-12-15 17:21:28,618 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-12-15 17:21:28,618 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-12-15 17:21:28,621 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-12-15 17:21:28,622 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 15.12 05:21:28" (1/1) ... [2021-12-15 17:21:28,622 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@474768f and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:21:28, skipping insertion in model container [2021-12-15 17:21:28,623 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 15.12 05:21:28" (1/1) ... [2021-12-15 17:21:28,628 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-12-15 17:21:28,651 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-12-15 17:21:28,765 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.03.cil.c[706,719] [2021-12-15 17:21:28,814 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-15 17:21:28,822 INFO L203 MainTranslator]: Completed pre-run [2021-12-15 17:21:28,831 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.03.cil.c[706,719] [2021-12-15 17:21:28,854 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-15 17:21:28,868 INFO L208 MainTranslator]: Completed translation [2021-12-15 17:21:28,868 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:21:28 WrapperNode [2021-12-15 17:21:28,868 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-12-15 17:21:28,869 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-12-15 17:21:28,870 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-12-15 17:21:28,870 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-12-15 17:21:28,875 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:21:28" (1/1) ... [2021-12-15 17:21:28,882 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:21:28" (1/1) ... [2021-12-15 17:21:28,916 INFO L137 Inliner]: procedures = 34, calls = 39, calls flagged for inlining = 34, calls inlined = 56, statements flattened = 733 [2021-12-15 17:21:28,916 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-12-15 17:21:28,917 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-12-15 17:21:28,917 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-12-15 17:21:28,917 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-12-15 17:21:28,924 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:21:28" (1/1) ... [2021-12-15 17:21:28,924 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:21:28" (1/1) ... [2021-12-15 17:21:28,928 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:21:28" (1/1) ... [2021-12-15 17:21:28,928 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:21:28" (1/1) ... [2021-12-15 17:21:28,936 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:21:28" (1/1) ... [2021-12-15 17:21:28,944 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:21:28" (1/1) ... [2021-12-15 17:21:28,947 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:21:28" (1/1) ... [2021-12-15 17:21:28,951 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-12-15 17:21:28,952 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-12-15 17:21:28,952 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-12-15 17:21:28,952 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-12-15 17:21:28,953 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:21:28" (1/1) ... [2021-12-15 17:21:28,967 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-15 17:21:28,977 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-15 17:21:28,992 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-15 17:21:28,997 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2021-12-15 17:21:29,022 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2021-12-15 17:21:29,023 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2021-12-15 17:21:29,023 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-12-15 17:21:29,023 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-12-15 17:21:29,086 INFO L236 CfgBuilder]: Building ICFG [2021-12-15 17:21:29,087 INFO L262 CfgBuilder]: Building CFG for each procedure with an implementation [2021-12-15 17:21:29,608 INFO L277 CfgBuilder]: Performing block encoding [2021-12-15 17:21:29,621 INFO L296 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-12-15 17:21:29,621 INFO L301 CfgBuilder]: Removed 7 assume(true) statements. [2021-12-15 17:21:29,623 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 15.12 05:21:29 BoogieIcfgContainer [2021-12-15 17:21:29,623 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-12-15 17:21:29,624 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2021-12-15 17:21:29,624 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2021-12-15 17:21:29,630 INFO L275 PluginConnector]: BuchiAutomizer initialized [2021-12-15 17:21:29,630 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-15 17:21:29,630 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 15.12 05:21:28" (1/3) ... [2021-12-15 17:21:29,631 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@6a795fb9 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 15.12 05:21:29, skipping insertion in model container [2021-12-15 17:21:29,632 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-15 17:21:29,632 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:21:28" (2/3) ... [2021-12-15 17:21:29,632 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@6a795fb9 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 15.12 05:21:29, skipping insertion in model container [2021-12-15 17:21:29,632 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-15 17:21:29,632 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 15.12 05:21:29" (3/3) ... [2021-12-15 17:21:29,634 INFO L388 chiAutomizerObserver]: Analyzing ICFG transmitter.03.cil.c [2021-12-15 17:21:29,668 INFO L359 BuchiCegarLoop]: Interprodecural is true [2021-12-15 17:21:29,668 INFO L360 BuchiCegarLoop]: Hoare is false [2021-12-15 17:21:29,669 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2021-12-15 17:21:29,669 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2021-12-15 17:21:29,669 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2021-12-15 17:21:29,669 INFO L364 BuchiCegarLoop]: Difference is false [2021-12-15 17:21:29,669 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2021-12-15 17:21:29,669 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2021-12-15 17:21:29,698 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 291 states, 290 states have (on average 1.5413793103448277) internal successors, (447), 290 states have internal predecessors, (447), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:29,750 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 234 [2021-12-15 17:21:29,752 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:21:29,752 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:21:29,762 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:29,763 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:29,763 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2021-12-15 17:21:29,764 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 291 states, 290 states have (on average 1.5413793103448277) internal successors, (447), 290 states have internal predecessors, (447), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:29,773 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 234 [2021-12-15 17:21:29,774 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:21:29,774 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:21:29,780 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:29,780 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:29,787 INFO L791 eck$LassoCheckResult]: Stem: 282#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 193#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 161#L615true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 113#L274true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 169#L281true assume !(1 == ~m_i~0);~m_st~0 := 2; 227#L281-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 34#L286-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 206#L291-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 221#L296-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 15#L418true assume !(0 == ~M_E~0); 168#L418-2true assume !(0 == ~T1_E~0); 214#L423-1true assume 0 == ~T2_E~0;~T2_E~0 := 1; 224#L428-1true assume !(0 == ~T3_E~0); 211#L433-1true assume !(0 == ~E_1~0); 197#L438-1true assume !(0 == ~E_2~0); 127#L443-1true assume !(0 == ~E_3~0); 123#L448-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 92#L197true assume !(1 == ~m_pc~0); 259#L197-2true is_master_triggered_~__retres1~0#1 := 0; 263#L208true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 271#L209true activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 233#L510true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 7#L510-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 260#L216true assume 1 == ~t1_pc~0; 26#L217true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 118#L227true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 110#L228true activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 8#L518true assume !(0 != activate_threads_~tmp___0~0#1); 135#L518-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 274#L235true assume !(1 == ~t2_pc~0); 203#L235-2true is_transmit2_triggered_~__retres1~2#1 := 0; 81#L246true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 132#L247true activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 245#L526true assume !(0 != activate_threads_~tmp___1~0#1); 255#L526-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 72#L254true assume 1 == ~t3_pc~0; 19#L255true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 88#L265true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13#L266true activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 111#L534true assume !(0 != activate_threads_~tmp___2~0#1); 77#L534-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3#L461true assume !(1 == ~M_E~0); 35#L461-2true assume !(1 == ~T1_E~0); 222#L466-1true assume !(1 == ~T2_E~0); 267#L471-1true assume 1 == ~T3_E~0;~T3_E~0 := 2; 47#L476-1true assume !(1 == ~E_1~0); 272#L481-1true assume !(1 == ~E_2~0); 147#L486-1true assume !(1 == ~E_3~0); 55#L491-1true assume { :end_inline_reset_delta_events } true; 11#L652-2true [2021-12-15 17:21:29,794 INFO L793 eck$LassoCheckResult]: Loop: 11#L652-2true assume !false; 63#L653true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 172#L393true assume false; 264#L408true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 231#L274-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 290#L418-3true assume 0 == ~M_E~0;~M_E~0 := 1; 134#L418-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 155#L423-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 130#L428-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 91#L433-3true assume 0 == ~E_1~0;~E_1~0 := 1; 177#L438-3true assume !(0 == ~E_2~0); 184#L443-3true assume 0 == ~E_3~0;~E_3~0 := 1; 4#L448-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 186#L197-12true assume !(1 == ~m_pc~0); 229#L197-14true is_master_triggered_~__retres1~0#1 := 0; 69#L208-4true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 269#L209-4true activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 10#L510-12true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 106#L510-14true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 68#L216-12true assume 1 == ~t1_pc~0; 284#L217-4true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 103#L227-4true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 45#L228-4true activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 74#L518-12true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 33#L518-14true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 278#L235-12true assume 1 == ~t2_pc~0; 195#L236-4true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 246#L246-4true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 241#L247-4true activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 286#L526-12true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 124#L526-14true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 236#L254-12true assume !(1 == ~t3_pc~0); 242#L254-14true is_transmit3_triggered_~__retres1~3#1 := 0; 126#L265-4true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 133#L266-4true activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 108#L534-12true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 148#L534-14true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 70#L461-3true assume 1 == ~M_E~0;~M_E~0 := 2; 291#L461-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 139#L466-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 232#L471-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 65#L476-3true assume 1 == ~E_1~0;~E_1~0 := 2; 131#L481-3true assume 1 == ~E_2~0;~E_2~0 := 2; 87#L486-3true assume !(1 == ~E_3~0); 252#L491-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 21#L309-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 36#L331-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 49#L332-1true start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 140#L671true assume !(0 == start_simulation_~tmp~3#1); 174#L671-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 292#L309-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 146#L331-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 112#L332-2true stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 219#L626true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 150#L633true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 244#L634true start_simulation_#t~ret15#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 159#L684true assume !(0 != start_simulation_~tmp___0~1#1); 11#L652-2true [2021-12-15 17:21:29,800 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:29,800 INFO L85 PathProgramCache]: Analyzing trace with hash -1773697160, now seen corresponding path program 1 times [2021-12-15 17:21:29,809 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:29,810 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [15018286] [2021-12-15 17:21:29,810 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:29,811 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:29,913 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:30,005 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:30,006 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:30,007 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [15018286] [2021-12-15 17:21:30,008 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [15018286] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:30,009 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:30,010 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:30,012 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [434264783] [2021-12-15 17:21:30,012 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:30,016 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:21:30,018 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:30,019 INFO L85 PathProgramCache]: Analyzing trace with hash -1061159640, now seen corresponding path program 1 times [2021-12-15 17:21:30,019 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:30,019 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1967866870] [2021-12-15 17:21:30,019 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:30,019 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:30,035 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:30,055 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:30,056 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:30,056 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1967866870] [2021-12-15 17:21:30,056 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1967866870] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:30,056 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:30,057 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-15 17:21:30,057 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1427590013] [2021-12-15 17:21:30,057 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:30,059 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:21:30,060 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:21:30,094 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:21:30,094 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:21:30,097 INFO L87 Difference]: Start difference. First operand has 291 states, 290 states have (on average 1.5413793103448277) internal successors, (447), 290 states have internal predecessors, (447), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 16.333333333333332) internal successors, (49), 3 states have internal predecessors, (49), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:30,146 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:21:30,148 INFO L93 Difference]: Finished difference Result 290 states and 430 transitions. [2021-12-15 17:21:30,149 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:21:30,155 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 290 states and 430 transitions. [2021-12-15 17:21:30,158 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 231 [2021-12-15 17:21:30,165 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 290 states to 284 states and 424 transitions. [2021-12-15 17:21:30,166 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 284 [2021-12-15 17:21:30,167 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 284 [2021-12-15 17:21:30,168 INFO L73 IsDeterministic]: Start isDeterministic. Operand 284 states and 424 transitions. [2021-12-15 17:21:30,173 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:21:30,173 INFO L681 BuchiCegarLoop]: Abstraction has 284 states and 424 transitions. [2021-12-15 17:21:30,188 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 284 states and 424 transitions. [2021-12-15 17:21:30,233 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 284 to 284. [2021-12-15 17:21:30,235 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 284 states, 284 states have (on average 1.4929577464788732) internal successors, (424), 283 states have internal predecessors, (424), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:30,235 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 284 states to 284 states and 424 transitions. [2021-12-15 17:21:30,236 INFO L704 BuchiCegarLoop]: Abstraction has 284 states and 424 transitions. [2021-12-15 17:21:30,236 INFO L587 BuchiCegarLoop]: Abstraction has 284 states and 424 transitions. [2021-12-15 17:21:30,236 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2021-12-15 17:21:30,236 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 284 states and 424 transitions. [2021-12-15 17:21:30,238 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 231 [2021-12-15 17:21:30,238 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:21:30,238 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:21:30,239 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:30,239 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:30,239 INFO L791 eck$LassoCheckResult]: Stem: 873#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 840#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 810#L615 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 771#L274 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 772#L281 assume 1 == ~m_i~0;~m_st~0 := 0; 818#L281-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 657#L286-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 658#L291-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 850#L296-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 614#L418 assume !(0 == ~M_E~0); 615#L418-2 assume !(0 == ~T1_E~0); 817#L423-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 853#L428-1 assume !(0 == ~T3_E~0); 851#L433-1 assume !(0 == ~E_1~0); 843#L438-1 assume !(0 == ~E_2~0); 784#L443-1 assume !(0 == ~E_3~0); 779#L448-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 745#L197 assume !(1 == ~m_pc~0); 742#L197-2 is_master_triggered_~__retres1~0#1 := 0; 741#L208 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 868#L209 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 861#L510 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 598#L510-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 599#L216 assume 1 == ~t1_pc~0; 642#L217 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 643#L227 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 768#L228 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 600#L518 assume !(0 != activate_threads_~tmp___0~0#1); 601#L518-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 790#L235 assume !(1 == ~t2_pc~0); 847#L235-2 is_transmit2_triggered_~__retres1~2#1 := 0; 731#L246 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 732#L247 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 786#L526 assume !(0 != activate_threads_~tmp___1~0#1); 864#L526-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 720#L254 assume 1 == ~t3_pc~0; 624#L255 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 625#L265 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 610#L266 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 611#L534 assume !(0 != activate_threads_~tmp___2~0#1); 726#L534-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 590#L461 assume !(1 == ~M_E~0); 591#L461-2 assume !(1 == ~T1_E~0); 659#L466-1 assume !(1 == ~T2_E~0); 856#L471-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 680#L476-1 assume !(1 == ~E_1~0); 681#L481-1 assume !(1 == ~E_2~0); 803#L486-1 assume !(1 == ~E_3~0); 694#L491-1 assume { :end_inline_reset_delta_events } true; 608#L652-2 [2021-12-15 17:21:30,240 INFO L793 eck$LassoCheckResult]: Loop: 608#L652-2 assume !false; 609#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 707#L393 assume !false; 674#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 675#L309 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 653#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 813#L332 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 697#L346 assume !(0 != eval_~tmp~0#1); 698#L408 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 859#L274-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 860#L418-3 assume 0 == ~M_E~0;~M_E~0 := 1; 787#L418-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 788#L423-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 785#L428-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 743#L433-3 assume 0 == ~E_1~0;~E_1~0 := 1; 744#L438-3 assume !(0 == ~E_2~0); 825#L443-3 assume 0 == ~E_3~0;~E_3~0 := 1; 592#L448-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 593#L197-12 assume !(1 == ~m_pc~0); 833#L197-14 is_master_triggered_~__retres1~0#1 := 0; 714#L208-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 715#L209-4 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 604#L510-12 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 605#L510-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 711#L216-12 assume 1 == ~t1_pc~0; 712#L217-4 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 759#L227-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 676#L228-4 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 677#L518-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 655#L518-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 656#L235-12 assume !(1 == ~t2_pc~0); 729#L235-14 is_transmit2_triggered_~__retres1~2#1 := 0; 730#L246-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 862#L247-4 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 863#L526-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 781#L526-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 782#L254-12 assume 1 == ~t3_pc~0; 633#L255-4 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 634#L265-4 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 783#L266-4 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 763#L534-12 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 764#L534-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 716#L461-3 assume 1 == ~M_E~0;~M_E~0 := 2; 717#L461-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 794#L466-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 795#L471-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 708#L476-3 assume 1 == ~E_1~0;~E_1~0 := 2; 709#L481-3 assume 1 == ~E_2~0;~E_2~0 := 2; 736#L486-3 assume !(1 == ~E_3~0); 737#L491-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 627#L309-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 628#L331-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 660#L332-1 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 685#L671 assume !(0 == start_simulation_~tmp~3#1); 613#L671-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 820#L309-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 705#L331-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 769#L332-2 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 770#L626 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 804#L633 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 805#L634 start_simulation_#t~ret15#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 808#L684 assume !(0 != start_simulation_~tmp___0~1#1); 608#L652-2 [2021-12-15 17:21:30,240 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:30,240 INFO L85 PathProgramCache]: Analyzing trace with hash 1627783798, now seen corresponding path program 1 times [2021-12-15 17:21:30,241 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:30,241 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1745398917] [2021-12-15 17:21:30,241 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:30,241 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:30,261 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:30,284 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:30,285 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:30,285 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1745398917] [2021-12-15 17:21:30,286 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1745398917] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:30,287 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:30,287 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:30,287 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [552157882] [2021-12-15 17:21:30,288 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:30,288 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:21:30,288 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:30,288 INFO L85 PathProgramCache]: Analyzing trace with hash 1668488769, now seen corresponding path program 1 times [2021-12-15 17:21:30,288 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:30,289 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [444817894] [2021-12-15 17:21:30,289 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:30,289 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:30,306 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:30,337 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:30,337 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:30,337 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [444817894] [2021-12-15 17:21:30,338 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [444817894] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:30,338 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:30,338 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:30,338 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1669757640] [2021-12-15 17:21:30,338 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:30,339 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:21:30,339 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:21:30,339 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:21:30,339 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:21:30,340 INFO L87 Difference]: Start difference. First operand 284 states and 424 transitions. cyclomatic complexity: 141 Second operand has 3 states, 3 states have (on average 16.333333333333332) internal successors, (49), 3 states have internal predecessors, (49), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:30,349 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:21:30,349 INFO L93 Difference]: Finished difference Result 284 states and 423 transitions. [2021-12-15 17:21:30,350 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:21:30,350 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 284 states and 423 transitions. [2021-12-15 17:21:30,353 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 231 [2021-12-15 17:21:30,354 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 284 states to 284 states and 423 transitions. [2021-12-15 17:21:30,355 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 284 [2021-12-15 17:21:30,355 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 284 [2021-12-15 17:21:30,355 INFO L73 IsDeterministic]: Start isDeterministic. Operand 284 states and 423 transitions. [2021-12-15 17:21:30,356 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:21:30,356 INFO L681 BuchiCegarLoop]: Abstraction has 284 states and 423 transitions. [2021-12-15 17:21:30,356 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 284 states and 423 transitions. [2021-12-15 17:21:30,360 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 284 to 284. [2021-12-15 17:21:30,360 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 284 states, 284 states have (on average 1.4894366197183098) internal successors, (423), 283 states have internal predecessors, (423), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:30,361 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 284 states to 284 states and 423 transitions. [2021-12-15 17:21:30,361 INFO L704 BuchiCegarLoop]: Abstraction has 284 states and 423 transitions. [2021-12-15 17:21:30,361 INFO L587 BuchiCegarLoop]: Abstraction has 284 states and 423 transitions. [2021-12-15 17:21:30,361 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2021-12-15 17:21:30,362 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 284 states and 423 transitions. [2021-12-15 17:21:30,363 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 231 [2021-12-15 17:21:30,363 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:21:30,363 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:21:30,364 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:30,365 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:30,365 INFO L791 eck$LassoCheckResult]: Stem: 1448#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 1415#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 1385#L615 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1346#L274 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1347#L281 assume 1 == ~m_i~0;~m_st~0 := 0; 1393#L281-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1232#L286-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1233#L291-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1425#L296-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1192#L418 assume !(0 == ~M_E~0); 1193#L418-2 assume !(0 == ~T1_E~0); 1392#L423-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1428#L428-1 assume !(0 == ~T3_E~0); 1426#L433-1 assume !(0 == ~E_1~0); 1418#L438-1 assume !(0 == ~E_2~0); 1359#L443-1 assume !(0 == ~E_3~0); 1354#L448-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1320#L197 assume !(1 == ~m_pc~0); 1317#L197-2 is_master_triggered_~__retres1~0#1 := 0; 1316#L208 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1443#L209 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 1436#L510 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1173#L510-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1174#L216 assume 1 == ~t1_pc~0; 1217#L217 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1218#L227 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1343#L228 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1175#L518 assume !(0 != activate_threads_~tmp___0~0#1); 1176#L518-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1365#L235 assume !(1 == ~t2_pc~0); 1424#L235-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1306#L246 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1307#L247 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1361#L526 assume !(0 != activate_threads_~tmp___1~0#1); 1439#L526-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1295#L254 assume 1 == ~t3_pc~0; 1199#L255 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1200#L265 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1185#L266 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1186#L534 assume !(0 != activate_threads_~tmp___2~0#1); 1301#L534-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1165#L461 assume !(1 == ~M_E~0); 1166#L461-2 assume !(1 == ~T1_E~0); 1234#L466-1 assume !(1 == ~T2_E~0); 1431#L471-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1255#L476-1 assume !(1 == ~E_1~0); 1256#L481-1 assume !(1 == ~E_2~0); 1378#L486-1 assume !(1 == ~E_3~0); 1271#L491-1 assume { :end_inline_reset_delta_events } true; 1183#L652-2 [2021-12-15 17:21:30,365 INFO L793 eck$LassoCheckResult]: Loop: 1183#L652-2 assume !false; 1184#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1282#L393 assume !false; 1249#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 1250#L309 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 1228#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 1388#L332 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1272#L346 assume !(0 != eval_~tmp~0#1); 1273#L408 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1434#L274-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1435#L418-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1362#L418-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1363#L423-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1360#L428-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1318#L433-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1319#L438-3 assume !(0 == ~E_2~0); 1401#L443-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1167#L448-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1168#L197-12 assume !(1 == ~m_pc~0); 1408#L197-14 is_master_triggered_~__retres1~0#1 := 0; 1289#L208-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1290#L209-4 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 1179#L510-12 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1180#L510-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1286#L216-12 assume 1 == ~t1_pc~0; 1287#L217-4 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1334#L227-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1251#L228-4 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1252#L518-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1230#L518-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1231#L235-12 assume !(1 == ~t2_pc~0); 1304#L235-14 is_transmit2_triggered_~__retres1~2#1 := 0; 1305#L246-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1437#L247-4 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1438#L526-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1355#L526-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1356#L254-12 assume 1 == ~t3_pc~0; 1208#L255-4 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1209#L265-4 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1358#L266-4 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1338#L534-12 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1339#L534-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1291#L461-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1292#L461-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1369#L466-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1370#L471-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1283#L476-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1284#L481-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1311#L486-3 assume !(1 == ~E_3~0); 1312#L491-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 1202#L309-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 1203#L331-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 1235#L332-1 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 1260#L671 assume !(0 == start_simulation_~tmp~3#1); 1188#L671-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 1395#L309-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 1280#L331-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 1344#L332-2 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 1345#L626 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1379#L633 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1380#L634 start_simulation_#t~ret15#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 1383#L684 assume !(0 != start_simulation_~tmp___0~1#1); 1183#L652-2 [2021-12-15 17:21:30,365 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:30,365 INFO L85 PathProgramCache]: Analyzing trace with hash -1769790220, now seen corresponding path program 1 times [2021-12-15 17:21:30,366 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:30,366 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [209507136] [2021-12-15 17:21:30,366 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:30,366 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:30,375 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:30,393 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:30,393 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:30,393 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [209507136] [2021-12-15 17:21:30,393 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [209507136] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:30,394 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:30,394 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:30,394 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1597784804] [2021-12-15 17:21:30,394 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:30,394 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:21:30,395 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:30,395 INFO L85 PathProgramCache]: Analyzing trace with hash 1668488769, now seen corresponding path program 2 times [2021-12-15 17:21:30,395 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:30,395 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [716762817] [2021-12-15 17:21:30,395 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:30,396 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:30,412 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:30,453 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:30,453 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:30,454 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [716762817] [2021-12-15 17:21:30,454 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [716762817] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:30,454 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:30,454 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:30,454 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [529650057] [2021-12-15 17:21:30,454 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:30,455 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:21:30,455 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:21:30,455 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:21:30,455 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:21:30,456 INFO L87 Difference]: Start difference. First operand 284 states and 423 transitions. cyclomatic complexity: 140 Second operand has 3 states, 3 states have (on average 16.333333333333332) internal successors, (49), 3 states have internal predecessors, (49), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:30,470 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:21:30,470 INFO L93 Difference]: Finished difference Result 284 states and 422 transitions. [2021-12-15 17:21:30,473 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:21:30,474 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 284 states and 422 transitions. [2021-12-15 17:21:30,477 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 231 [2021-12-15 17:21:30,478 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 284 states to 284 states and 422 transitions. [2021-12-15 17:21:30,478 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 284 [2021-12-15 17:21:30,479 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 284 [2021-12-15 17:21:30,479 INFO L73 IsDeterministic]: Start isDeterministic. Operand 284 states and 422 transitions. [2021-12-15 17:21:30,479 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:21:30,479 INFO L681 BuchiCegarLoop]: Abstraction has 284 states and 422 transitions. [2021-12-15 17:21:30,480 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 284 states and 422 transitions. [2021-12-15 17:21:30,482 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 284 to 284. [2021-12-15 17:21:30,483 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 284 states, 284 states have (on average 1.4859154929577465) internal successors, (422), 283 states have internal predecessors, (422), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:30,484 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 284 states to 284 states and 422 transitions. [2021-12-15 17:21:30,484 INFO L704 BuchiCegarLoop]: Abstraction has 284 states and 422 transitions. [2021-12-15 17:21:30,484 INFO L587 BuchiCegarLoop]: Abstraction has 284 states and 422 transitions. [2021-12-15 17:21:30,484 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2021-12-15 17:21:30,484 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 284 states and 422 transitions. [2021-12-15 17:21:30,486 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 231 [2021-12-15 17:21:30,486 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:21:30,486 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:21:30,488 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:30,488 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:30,490 INFO L791 eck$LassoCheckResult]: Stem: 2023#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 1990#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 1960#L615 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1921#L274 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1922#L281 assume 1 == ~m_i~0;~m_st~0 := 0; 1968#L281-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1807#L286-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1808#L291-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2000#L296-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1769#L418 assume !(0 == ~M_E~0); 1770#L418-2 assume !(0 == ~T1_E~0); 1967#L423-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2003#L428-1 assume !(0 == ~T3_E~0); 2001#L433-1 assume !(0 == ~E_1~0); 1993#L438-1 assume !(0 == ~E_2~0); 1934#L443-1 assume !(0 == ~E_3~0); 1929#L448-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1895#L197 assume !(1 == ~m_pc~0); 1892#L197-2 is_master_triggered_~__retres1~0#1 := 0; 1891#L208 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2019#L209 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 2011#L510 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1748#L510-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1749#L216 assume 1 == ~t1_pc~0; 1792#L217 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1793#L227 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1918#L228 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1750#L518 assume !(0 != activate_threads_~tmp___0~0#1); 1751#L518-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1941#L235 assume !(1 == ~t2_pc~0); 1999#L235-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1882#L246 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1883#L247 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1936#L526 assume !(0 != activate_threads_~tmp___1~0#1); 2014#L526-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1873#L254 assume 1 == ~t3_pc~0; 1774#L255 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1775#L265 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1760#L266 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1761#L534 assume !(0 != activate_threads_~tmp___2~0#1); 1876#L534-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1740#L461 assume !(1 == ~M_E~0); 1741#L461-2 assume !(1 == ~T1_E~0); 1809#L466-1 assume !(1 == ~T2_E~0); 2006#L471-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1830#L476-1 assume !(1 == ~E_1~0); 1831#L481-1 assume !(1 == ~E_2~0); 1953#L486-1 assume !(1 == ~E_3~0); 1846#L491-1 assume { :end_inline_reset_delta_events } true; 1758#L652-2 [2021-12-15 17:21:30,490 INFO L793 eck$LassoCheckResult]: Loop: 1758#L652-2 assume !false; 1759#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1857#L393 assume !false; 1824#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 1825#L309 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 1803#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 1963#L332 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1847#L346 assume !(0 != eval_~tmp~0#1); 1848#L408 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2009#L274-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2010#L418-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1937#L418-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1938#L423-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1935#L428-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1893#L433-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1894#L438-3 assume !(0 == ~E_2~0); 1975#L443-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1742#L448-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1743#L197-12 assume 1 == ~m_pc~0; 1984#L198-4 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1864#L208-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1865#L209-4 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 1754#L510-12 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1755#L510-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1861#L216-12 assume 1 == ~t1_pc~0; 1862#L217-4 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1909#L227-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1826#L228-4 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1827#L518-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1805#L518-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1806#L235-12 assume !(1 == ~t2_pc~0); 1879#L235-14 is_transmit2_triggered_~__retres1~2#1 := 0; 1880#L246-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2012#L247-4 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 2013#L526-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1930#L526-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1931#L254-12 assume 1 == ~t3_pc~0; 1783#L255-4 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1784#L265-4 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1933#L266-4 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1913#L534-12 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1914#L534-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1866#L461-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1867#L461-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1944#L466-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1945#L471-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1858#L476-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1859#L481-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1886#L486-3 assume !(1 == ~E_3~0); 1887#L491-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 1780#L309-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 1781#L331-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 1810#L332-1 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 1835#L671 assume !(0 == start_simulation_~tmp~3#1); 1763#L671-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 1970#L309-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 1855#L331-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 1919#L332-2 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 1920#L626 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1954#L633 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1955#L634 start_simulation_#t~ret15#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 1958#L684 assume !(0 != start_simulation_~tmp___0~1#1); 1758#L652-2 [2021-12-15 17:21:30,490 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:30,490 INFO L85 PathProgramCache]: Analyzing trace with hash -2017936714, now seen corresponding path program 1 times [2021-12-15 17:21:30,491 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:30,491 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1428481673] [2021-12-15 17:21:30,492 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:30,492 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:30,518 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:30,564 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:30,564 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:30,565 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1428481673] [2021-12-15 17:21:30,565 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1428481673] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:30,565 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:30,565 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:30,565 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [758434007] [2021-12-15 17:21:30,565 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:30,566 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:21:30,566 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:30,566 INFO L85 PathProgramCache]: Analyzing trace with hash -1351375838, now seen corresponding path program 1 times [2021-12-15 17:21:30,566 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:30,566 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [566439136] [2021-12-15 17:21:30,566 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:30,567 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:30,587 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:30,618 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:30,619 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:30,619 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [566439136] [2021-12-15 17:21:30,619 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [566439136] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:30,620 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:30,620 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:30,620 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1384526834] [2021-12-15 17:21:30,620 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:30,621 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:21:30,622 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:21:30,623 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-15 17:21:30,623 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-15 17:21:30,624 INFO L87 Difference]: Start difference. First operand 284 states and 422 transitions. cyclomatic complexity: 139 Second operand has 4 states, 4 states have (on average 12.25) internal successors, (49), 3 states have internal predecessors, (49), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:30,720 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:21:30,720 INFO L93 Difference]: Finished difference Result 485 states and 716 transitions. [2021-12-15 17:21:30,720 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-15 17:21:30,721 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 485 states and 716 transitions. [2021-12-15 17:21:30,725 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 425 [2021-12-15 17:21:30,727 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 485 states to 485 states and 716 transitions. [2021-12-15 17:21:30,727 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 485 [2021-12-15 17:21:30,728 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 485 [2021-12-15 17:21:30,728 INFO L73 IsDeterministic]: Start isDeterministic. Operand 485 states and 716 transitions. [2021-12-15 17:21:30,729 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:21:30,729 INFO L681 BuchiCegarLoop]: Abstraction has 485 states and 716 transitions. [2021-12-15 17:21:30,730 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 485 states and 716 transitions. [2021-12-15 17:21:30,737 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 485 to 485. [2021-12-15 17:21:30,738 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 485 states, 485 states have (on average 1.4762886597938145) internal successors, (716), 484 states have internal predecessors, (716), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:30,740 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 485 states to 485 states and 716 transitions. [2021-12-15 17:21:30,740 INFO L704 BuchiCegarLoop]: Abstraction has 485 states and 716 transitions. [2021-12-15 17:21:30,740 INFO L587 BuchiCegarLoop]: Abstraction has 485 states and 716 transitions. [2021-12-15 17:21:30,740 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2021-12-15 17:21:30,741 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 485 states and 716 transitions. [2021-12-15 17:21:30,744 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 425 [2021-12-15 17:21:30,744 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:21:30,744 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:21:30,748 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:30,748 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:30,748 INFO L791 eck$LassoCheckResult]: Stem: 2818#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 2779#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 2745#L615 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2704#L274 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2705#L281 assume 1 == ~m_i~0;~m_st~0 := 0; 2754#L281-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2587#L286-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2588#L291-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2791#L296-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2549#L418 assume !(0 == ~M_E~0); 2550#L418-2 assume !(0 == ~T1_E~0); 2753#L423-1 assume !(0 == ~T2_E~0); 2794#L428-1 assume !(0 == ~T3_E~0); 2792#L433-1 assume !(0 == ~E_1~0); 2782#L438-1 assume !(0 == ~E_2~0); 2719#L443-1 assume !(0 == ~E_3~0); 2714#L448-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2678#L197 assume !(1 == ~m_pc~0); 2675#L197-2 is_master_triggered_~__retres1~0#1 := 0; 2674#L208 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2812#L209 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 2803#L510 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2528#L510-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2529#L216 assume 1 == ~t1_pc~0; 2572#L217 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2573#L227 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2701#L228 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 2530#L518 assume !(0 != activate_threads_~tmp___0~0#1); 2531#L518-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2724#L235 assume !(1 == ~t2_pc~0); 2788#L235-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2663#L246 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2664#L247 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 2721#L526 assume !(0 != activate_threads_~tmp___1~0#1); 2808#L526-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2652#L254 assume 1 == ~t3_pc~0; 2554#L255 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2555#L265 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2540#L266 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2541#L534 assume !(0 != activate_threads_~tmp___2~0#1); 2658#L534-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2519#L461 assume 1 == ~M_E~0;~M_E~0 := 2; 2520#L461-2 assume !(1 == ~T1_E~0); 2946#L466-1 assume !(1 == ~T2_E~0); 2797#L471-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2943#L476-1 assume !(1 == ~E_1~0); 2942#L481-1 assume !(1 == ~E_2~0); 2941#L486-1 assume !(1 == ~E_3~0); 2940#L491-1 assume { :end_inline_reset_delta_events } true; 2536#L652-2 [2021-12-15 17:21:30,749 INFO L793 eck$LassoCheckResult]: Loop: 2536#L652-2 assume !false; 2537#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2636#L393 assume !false; 2604#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 2605#L309 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 2583#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 2749#L332 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 2824#L346 assume !(0 != eval_~tmp~0#1); 2823#L408 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2822#L274-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2821#L418-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2722#L418-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2723#L423-3 assume !(0 == ~T2_E~0); 2720#L428-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2676#L433-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2677#L438-3 assume !(0 == ~E_2~0); 2762#L443-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2522#L448-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2523#L197-12 assume !(1 == ~m_pc~0); 2772#L197-14 is_master_triggered_~__retres1~0#1 := 0; 2646#L208-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2647#L209-4 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 2534#L510-12 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2535#L510-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2643#L216-12 assume 1 == ~t1_pc~0; 2644#L217-4 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2692#L227-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2606#L228-4 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 2607#L518-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2585#L518-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2586#L235-12 assume !(1 == ~t2_pc~0); 2661#L235-14 is_transmit2_triggered_~__retres1~2#1 := 0; 2662#L246-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2804#L247-4 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 2805#L526-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2715#L526-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2716#L254-12 assume 1 == ~t3_pc~0; 2563#L255-4 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2564#L265-4 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2718#L266-4 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2696#L534-12 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2697#L534-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2648#L461-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2649#L461-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2729#L466-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2730#L471-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2640#L476-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2641#L481-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2670#L486-3 assume !(1 == ~E_3~0); 2671#L491-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 2560#L309-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 2561#L331-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 2590#L332-1 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 2615#L671 assume !(0 == start_simulation_~tmp~3#1); 2543#L671-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 2756#L309-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 2638#L331-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 2702#L332-2 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 2703#L626 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2739#L633 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2740#L634 start_simulation_#t~ret15#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 2807#L684 assume !(0 != start_simulation_~tmp___0~1#1); 2536#L652-2 [2021-12-15 17:21:30,749 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:30,750 INFO L85 PathProgramCache]: Analyzing trace with hash 2057017910, now seen corresponding path program 1 times [2021-12-15 17:21:30,750 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:30,750 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [924595939] [2021-12-15 17:21:30,750 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:30,751 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:30,769 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:30,799 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:30,799 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:30,800 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [924595939] [2021-12-15 17:21:30,800 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [924595939] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:30,800 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:30,800 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-15 17:21:30,800 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [428760597] [2021-12-15 17:21:30,801 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:30,801 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:21:30,801 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:30,802 INFO L85 PathProgramCache]: Analyzing trace with hash 1187408511, now seen corresponding path program 1 times [2021-12-15 17:21:30,802 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:30,802 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1223008997] [2021-12-15 17:21:30,803 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:30,803 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:30,821 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:30,842 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:30,842 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:30,843 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1223008997] [2021-12-15 17:21:30,843 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1223008997] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:30,843 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:30,843 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:30,843 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [859925400] [2021-12-15 17:21:30,844 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:30,844 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:21:30,845 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:21:30,845 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-15 17:21:30,845 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-15 17:21:30,845 INFO L87 Difference]: Start difference. First operand 485 states and 716 transitions. cyclomatic complexity: 233 Second operand has 5 states, 5 states have (on average 9.8) internal successors, (49), 5 states have internal predecessors, (49), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:30,966 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:21:30,966 INFO L93 Difference]: Finished difference Result 1331 states and 1952 transitions. [2021-12-15 17:21:30,967 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-15 17:21:30,969 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1331 states and 1952 transitions. [2021-12-15 17:21:30,977 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1194 [2021-12-15 17:21:30,984 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1331 states to 1331 states and 1952 transitions. [2021-12-15 17:21:30,984 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1331 [2021-12-15 17:21:30,985 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1331 [2021-12-15 17:21:30,985 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1331 states and 1952 transitions. [2021-12-15 17:21:30,987 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:21:30,987 INFO L681 BuchiCegarLoop]: Abstraction has 1331 states and 1952 transitions. [2021-12-15 17:21:30,988 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1331 states and 1952 transitions. [2021-12-15 17:21:30,999 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1331 to 515. [2021-12-15 17:21:31,000 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 515 states, 515 states have (on average 1.4485436893203882) internal successors, (746), 514 states have internal predecessors, (746), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:31,001 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 515 states to 515 states and 746 transitions. [2021-12-15 17:21:31,001 INFO L704 BuchiCegarLoop]: Abstraction has 515 states and 746 transitions. [2021-12-15 17:21:31,001 INFO L587 BuchiCegarLoop]: Abstraction has 515 states and 746 transitions. [2021-12-15 17:21:31,002 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2021-12-15 17:21:31,002 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 515 states and 746 transitions. [2021-12-15 17:21:31,004 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 452 [2021-12-15 17:21:31,004 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:21:31,004 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:21:31,006 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:31,006 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:31,006 INFO L791 eck$LassoCheckResult]: Stem: 4682#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 4623#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 4586#L615 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4537#L274 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4538#L281 assume 1 == ~m_i~0;~m_st~0 := 0; 4595#L281-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4416#L286-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4417#L291-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4635#L296-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4373#L418 assume !(0 == ~M_E~0); 4374#L418-2 assume !(0 == ~T1_E~0); 4594#L423-1 assume !(0 == ~T2_E~0); 4640#L428-1 assume !(0 == ~T3_E~0); 4637#L433-1 assume !(0 == ~E_1~0); 4626#L438-1 assume !(0 == ~E_2~0); 4553#L443-1 assume !(0 == ~E_3~0); 4548#L448-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4509#L197 assume !(1 == ~m_pc~0); 4506#L197-2 is_master_triggered_~__retres1~0#1 := 0; 4667#L208 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4668#L209 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 4652#L510 assume !(0 != activate_threads_~tmp~1#1); 4357#L510-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4358#L216 assume 1 == ~t1_pc~0; 4401#L217 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4402#L227 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4534#L228 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 4359#L518 assume !(0 != activate_threads_~tmp___0~0#1); 4360#L518-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4560#L235 assume !(1 == ~t2_pc~0); 4630#L235-2 is_transmit2_triggered_~__retres1~2#1 := 0; 4493#L246 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4494#L247 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 4556#L526 assume !(0 != activate_threads_~tmp___1~0#1); 4657#L526-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4482#L254 assume 1 == ~t3_pc~0; 4383#L255 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4384#L265 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4369#L266 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 4370#L534 assume !(0 != activate_threads_~tmp___2~0#1); 4488#L534-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4348#L461 assume 1 == ~M_E~0;~M_E~0 := 2; 4349#L461-2 assume !(1 == ~T1_E~0); 4799#L466-1 assume !(1 == ~T2_E~0); 4643#L471-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4795#L476-1 assume !(1 == ~E_1~0); 4793#L481-1 assume !(1 == ~E_2~0); 4791#L486-1 assume !(1 == ~E_3~0); 4789#L491-1 assume { :end_inline_reset_delta_events } true; 4786#L652-2 [2021-12-15 17:21:31,006 INFO L793 eck$LassoCheckResult]: Loop: 4786#L652-2 assume !false; 4467#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4468#L393 assume !false; 4703#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 4702#L309 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 4589#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 4590#L332 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 4698#L346 assume !(0 != eval_~tmp~0#1); 4669#L408 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4650#L274-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4651#L418-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4696#L418-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4858#L423-3 assume !(0 == ~T2_E~0); 4857#L428-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4856#L433-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4855#L438-3 assume !(0 == ~E_2~0); 4854#L443-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4853#L448-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4613#L197-12 assume !(1 == ~m_pc~0); 4614#L197-14 is_master_triggered_~__retres1~0#1 := 0; 4852#L208-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4850#L209-4 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 4848#L510-12 assume !(0 != activate_threads_~tmp~1#1); 4846#L510-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4845#L216-12 assume 1 == ~t1_pc~0; 4843#L217-4 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4842#L227-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4841#L228-4 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 4840#L518-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4839#L518-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4838#L235-12 assume !(1 == ~t2_pc~0); 4836#L235-14 is_transmit2_triggered_~__retres1~2#1 := 0; 4835#L246-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4834#L247-4 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 4833#L526-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4832#L526-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4831#L254-12 assume 1 == ~t3_pc~0; 4829#L255-4 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4828#L265-4 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4827#L266-4 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 4826#L534-12 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4825#L534-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4824#L461-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4478#L461-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4823#L466-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4565#L471-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4822#L476-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4821#L481-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4820#L486-3 assume !(1 == ~E_3~0); 4819#L491-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 4817#L309-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 4814#L331-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 4813#L332-1 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 4812#L671 assume !(0 == start_simulation_~tmp~3#1); 4372#L671-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 4808#L309-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 4807#L331-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 4806#L332-2 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 4805#L626 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4804#L633 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4803#L634 start_simulation_#t~ret15#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 4788#L684 assume !(0 != start_simulation_~tmp___0~1#1); 4786#L652-2 [2021-12-15 17:21:31,007 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:31,007 INFO L85 PathProgramCache]: Analyzing trace with hash 1547544820, now seen corresponding path program 1 times [2021-12-15 17:21:31,007 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:31,008 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1692420777] [2021-12-15 17:21:31,008 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:31,008 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:31,016 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:31,033 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:31,033 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:31,034 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1692420777] [2021-12-15 17:21:31,034 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1692420777] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:31,034 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:31,034 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-15 17:21:31,035 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1658156940] [2021-12-15 17:21:31,035 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:31,035 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:21:31,035 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:31,036 INFO L85 PathProgramCache]: Analyzing trace with hash -184398787, now seen corresponding path program 1 times [2021-12-15 17:21:31,037 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:31,037 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [53630047] [2021-12-15 17:21:31,037 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:31,037 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:31,044 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:31,056 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:31,057 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:31,057 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [53630047] [2021-12-15 17:21:31,057 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [53630047] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:31,057 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:31,057 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:31,057 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [975753219] [2021-12-15 17:21:31,058 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:31,058 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:21:31,058 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:21:31,058 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:21:31,059 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:21:31,059 INFO L87 Difference]: Start difference. First operand 515 states and 746 transitions. cyclomatic complexity: 233 Second operand has 3 states, 3 states have (on average 16.333333333333332) internal successors, (49), 2 states have internal predecessors, (49), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:31,086 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:21:31,086 INFO L93 Difference]: Finished difference Result 889 states and 1276 transitions. [2021-12-15 17:21:31,086 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:21:31,087 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 889 states and 1276 transitions. [2021-12-15 17:21:31,092 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 825 [2021-12-15 17:21:31,096 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 889 states to 889 states and 1276 transitions. [2021-12-15 17:21:31,097 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 889 [2021-12-15 17:21:31,097 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 889 [2021-12-15 17:21:31,097 INFO L73 IsDeterministic]: Start isDeterministic. Operand 889 states and 1276 transitions. [2021-12-15 17:21:31,098 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:21:31,098 INFO L681 BuchiCegarLoop]: Abstraction has 889 states and 1276 transitions. [2021-12-15 17:21:31,099 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 889 states and 1276 transitions. [2021-12-15 17:21:31,108 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 889 to 885. [2021-12-15 17:21:31,110 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 885 states, 885 states have (on average 1.4372881355932203) internal successors, (1272), 884 states have internal predecessors, (1272), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:31,112 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 885 states to 885 states and 1272 transitions. [2021-12-15 17:21:31,112 INFO L704 BuchiCegarLoop]: Abstraction has 885 states and 1272 transitions. [2021-12-15 17:21:31,113 INFO L587 BuchiCegarLoop]: Abstraction has 885 states and 1272 transitions. [2021-12-15 17:21:31,113 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2021-12-15 17:21:31,113 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 885 states and 1272 transitions. [2021-12-15 17:21:31,117 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 821 [2021-12-15 17:21:31,117 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:21:31,117 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:21:31,118 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:31,118 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:31,118 INFO L791 eck$LassoCheckResult]: Stem: 6097#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 6037#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 5997#L615 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5947#L274 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5948#L281 assume 1 == ~m_i~0;~m_st~0 := 0; 6006#L281-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5825#L286-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5826#L291-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 6047#L296-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5784#L418 assume !(0 == ~M_E~0); 5785#L418-2 assume !(0 == ~T1_E~0); 6005#L423-1 assume !(0 == ~T2_E~0); 6053#L428-1 assume !(0 == ~T3_E~0); 6051#L433-1 assume !(0 == ~E_1~0); 6040#L438-1 assume !(0 == ~E_2~0); 5963#L443-1 assume !(0 == ~E_3~0); 5958#L448-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5920#L197 assume !(1 == ~m_pc~0); 5917#L197-2 is_master_triggered_~__retres1~0#1 := 0; 6087#L208 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6088#L209 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 6065#L510 assume !(0 != activate_threads_~tmp~1#1); 5768#L510-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5769#L216 assume !(1 == ~t1_pc~0); 5821#L216-2 is_transmit1_triggered_~__retres1~1#1 := 0; 5822#L227 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5944#L228 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 5770#L518 assume !(0 != activate_threads_~tmp___0~0#1); 5771#L518-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5969#L235 assume !(1 == ~t2_pc~0); 6044#L235-2 is_transmit2_triggered_~__retres1~2#1 := 0; 5903#L246 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5904#L247 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 5966#L526 assume !(0 != activate_threads_~tmp___1~0#1); 6076#L526-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5891#L254 assume 1 == ~t3_pc~0; 5794#L255 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5795#L265 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5780#L266 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 5781#L534 assume !(0 != activate_threads_~tmp___2~0#1); 5897#L534-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5759#L461 assume 1 == ~M_E~0;~M_E~0 := 2; 5760#L461-2 assume !(1 == ~T1_E~0); 6384#L466-1 assume !(1 == ~T2_E~0); 6056#L471-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 6382#L476-1 assume !(1 == ~E_1~0); 6092#L481-1 assume !(1 == ~E_2~0); 5988#L486-1 assume !(1 == ~E_3~0); 5864#L491-1 assume { :end_inline_reset_delta_events } true; 5776#L652-2 [2021-12-15 17:21:31,118 INFO L793 eck$LassoCheckResult]: Loop: 5776#L652-2 assume !false; 5777#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5875#L393 assume !false; 6307#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 6206#L309 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 6203#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 6195#L332 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 6196#L346 assume !(0 != eval_~tmp~0#1); 6302#L408 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 6300#L274-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 6297#L418-3 assume 0 == ~M_E~0;~M_E~0 := 1; 6296#L418-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 6295#L423-3 assume !(0 == ~T2_E~0); 6293#L428-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 6291#L433-3 assume 0 == ~E_1~0;~E_1~0 := 1; 6290#L438-3 assume !(0 == ~E_2~0); 6289#L443-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5762#L448-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5763#L197-12 assume 1 == ~m_pc~0; 6129#L198-4 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 6130#L208-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6134#L209-4 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 6133#L510-12 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 5775#L510-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5882#L216-12 assume !(1 == ~t1_pc~0); 5883#L216-14 is_transmit1_triggered_~__retres1~1#1 := 0; 5934#L227-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5844#L228-4 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 5845#L518-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5823#L518-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5824#L235-12 assume 1 == ~t2_pc~0; 6039#L236-4 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5902#L246-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6073#L247-4 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 6074#L526-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5959#L526-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5960#L254-12 assume 1 == ~t3_pc~0; 6067#L255-4 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6343#L265-4 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6342#L266-4 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 6341#L534-12 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5989#L534-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5886#L461-3 assume 1 == ~M_E~0;~M_E~0 := 2; 5887#L461-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 6105#L466-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5976#L471-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 6338#L476-3 assume 1 == ~E_1~0;~E_1~0 := 2; 6337#L481-3 assume 1 == ~E_2~0;~E_2~0 := 2; 6336#L486-3 assume !(1 == ~E_3~0); 6335#L491-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 6333#L309-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 6330#L331-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 6329#L332-1 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 6328#L671 assume !(0 == start_simulation_~tmp~3#1); 5783#L671-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 6011#L309-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 5877#L331-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 5945#L332-2 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 5946#L626 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5990#L633 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5991#L634 start_simulation_#t~ret15#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 5996#L684 assume !(0 != start_simulation_~tmp___0~1#1); 5776#L652-2 [2021-12-15 17:21:31,119 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:31,119 INFO L85 PathProgramCache]: Analyzing trace with hash -2108637997, now seen corresponding path program 1 times [2021-12-15 17:21:31,119 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:31,119 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [278511324] [2021-12-15 17:21:31,120 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:31,120 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:31,125 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:31,149 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:31,149 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:31,150 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [278511324] [2021-12-15 17:21:31,150 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [278511324] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:31,150 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:31,150 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-15 17:21:31,150 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [289790396] [2021-12-15 17:21:31,150 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:31,151 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:21:31,151 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:31,151 INFO L85 PathProgramCache]: Analyzing trace with hash 2066857248, now seen corresponding path program 1 times [2021-12-15 17:21:31,151 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:31,152 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [162252885] [2021-12-15 17:21:31,152 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:31,152 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:31,157 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:31,176 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:31,176 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:31,176 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [162252885] [2021-12-15 17:21:31,176 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [162252885] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:31,176 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:31,176 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:31,177 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [198770069] [2021-12-15 17:21:31,177 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:31,177 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:21:31,177 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:21:31,177 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:21:31,177 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:21:31,178 INFO L87 Difference]: Start difference. First operand 885 states and 1272 transitions. cyclomatic complexity: 391 Second operand has 3 states, 3 states have (on average 16.333333333333332) internal successors, (49), 2 states have internal predecessors, (49), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:31,210 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:21:31,211 INFO L93 Difference]: Finished difference Result 1687 states and 2398 transitions. [2021-12-15 17:21:31,211 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:21:31,211 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1687 states and 2398 transitions. [2021-12-15 17:21:31,221 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 1614 [2021-12-15 17:21:31,228 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1687 states to 1687 states and 2398 transitions. [2021-12-15 17:21:31,228 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1687 [2021-12-15 17:21:31,229 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1687 [2021-12-15 17:21:31,230 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1687 states and 2398 transitions. [2021-12-15 17:21:31,231 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:21:31,231 INFO L681 BuchiCegarLoop]: Abstraction has 1687 states and 2398 transitions. [2021-12-15 17:21:31,232 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1687 states and 2398 transitions. [2021-12-15 17:21:31,248 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1687 to 1671. [2021-12-15 17:21:31,250 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1671 states, 1671 states have (on average 1.4230999401555955) internal successors, (2378), 1670 states have internal predecessors, (2378), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:31,254 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1671 states to 1671 states and 2378 transitions. [2021-12-15 17:21:31,254 INFO L704 BuchiCegarLoop]: Abstraction has 1671 states and 2378 transitions. [2021-12-15 17:21:31,254 INFO L587 BuchiCegarLoop]: Abstraction has 1671 states and 2378 transitions. [2021-12-15 17:21:31,255 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2021-12-15 17:21:31,255 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1671 states and 2378 transitions. [2021-12-15 17:21:31,261 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 1606 [2021-12-15 17:21:31,261 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:21:31,261 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:21:31,262 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:31,262 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:31,262 INFO L791 eck$LassoCheckResult]: Stem: 8672#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 8608#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 8571#L615 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8518#L274 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 8519#L281 assume 1 == ~m_i~0;~m_st~0 := 0; 8583#L281-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8400#L286-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8401#L291-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 8621#L296-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8363#L418 assume !(0 == ~M_E~0); 8364#L418-2 assume !(0 == ~T1_E~0); 8582#L423-1 assume !(0 == ~T2_E~0); 8628#L428-1 assume !(0 == ~T3_E~0); 8625#L433-1 assume !(0 == ~E_1~0); 8611#L438-1 assume !(0 == ~E_2~0); 8537#L443-1 assume !(0 == ~E_3~0); 8531#L448-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8492#L197 assume !(1 == ~m_pc~0); 8489#L197-2 is_master_triggered_~__retres1~0#1 := 0; 8663#L208 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8664#L209 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 8640#L510 assume !(0 != activate_threads_~tmp~1#1); 8347#L510-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8348#L216 assume !(1 == ~t1_pc~0); 8396#L216-2 is_transmit1_triggered_~__retres1~1#1 := 0; 8397#L227 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8515#L228 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 8349#L518 assume !(0 != activate_threads_~tmp___0~0#1); 8350#L518-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8543#L235 assume !(1 == ~t2_pc~0); 8618#L235-2 is_transmit2_triggered_~__retres1~2#1 := 0; 8477#L246 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8478#L247 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 8539#L526 assume !(0 != activate_threads_~tmp___1~0#1); 8651#L526-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8465#L254 assume !(1 == ~t3_pc~0); 8404#L254-2 is_transmit3_triggered_~__retres1~3#1 := 0; 8405#L265 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8359#L266 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 8360#L534 assume !(0 != activate_threads_~tmp___2~0#1); 8471#L534-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8338#L461 assume 1 == ~M_E~0;~M_E~0 := 2; 8339#L461-2 assume !(1 == ~T1_E~0); 9847#L466-1 assume !(1 == ~T2_E~0); 8631#L471-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 9846#L476-1 assume !(1 == ~E_1~0); 9845#L481-1 assume !(1 == ~E_2~0); 9844#L486-1 assume !(1 == ~E_3~0); 9843#L491-1 assume { :end_inline_reset_delta_events } true; 9841#L652-2 [2021-12-15 17:21:31,263 INFO L793 eck$LassoCheckResult]: Loop: 9841#L652-2 assume !false; 9827#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 8523#L393 assume !false; 8419#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 8420#L309 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 9582#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 9581#L332 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 9579#L346 assume !(0 != eval_~tmp~0#1); 9580#L408 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 9622#L274-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 9611#L418-3 assume 0 == ~M_E~0;~M_E~0 := 1; 9610#L418-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 9609#L423-3 assume !(0 == ~T2_E~0); 9608#L428-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 9607#L433-3 assume 0 == ~E_1~0;~E_1~0 := 1; 9606#L438-3 assume !(0 == ~E_2~0); 9605#L443-3 assume 0 == ~E_3~0;~E_3~0 := 1; 9604#L448-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9603#L197-12 assume 1 == ~m_pc~0; 9601#L198-4 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 9602#L208-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9600#L209-4 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 9592#L510-12 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 9588#L510-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9586#L216-12 assume !(1 == ~t1_pc~0); 9565#L216-14 is_transmit1_triggered_~__retres1~1#1 := 0; 8506#L227-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8421#L228-4 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 8422#L518-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8398#L518-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8399#L235-12 assume 1 == ~t2_pc~0; 8610#L236-4 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 8476#L246-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8648#L247-4 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 8649#L526-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 8533#L526-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8534#L254-12 assume !(1 == ~t3_pc~0); 8643#L254-14 is_transmit3_triggered_~__retres1~3#1 := 0; 8535#L265-4 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8536#L266-4 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 8783#L534-12 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 8781#L534-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8779#L461-3 assume 1 == ~M_E~0;~M_E~0 := 2; 8776#L461-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8773#L466-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 8771#L471-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8769#L476-3 assume 1 == ~E_1~0;~E_1~0 := 2; 8766#L481-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8764#L486-3 assume !(1 == ~E_3~0); 8762#L491-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 8756#L309-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 8745#L331-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 8742#L332-1 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 8739#L671 assume !(0 == start_simulation_~tmp~3#1); 8362#L671-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 9853#L309-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 9852#L331-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 9851#L332-2 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 9850#L626 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 9849#L633 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 9848#L634 start_simulation_#t~ret15#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 9842#L684 assume !(0 != start_simulation_~tmp___0~1#1); 9841#L652-2 [2021-12-15 17:21:31,263 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:31,263 INFO L85 PathProgramCache]: Analyzing trace with hash 1181968178, now seen corresponding path program 1 times [2021-12-15 17:21:31,263 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:31,263 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [700923458] [2021-12-15 17:21:31,263 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:31,264 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:31,269 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:31,283 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:31,283 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:31,284 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [700923458] [2021-12-15 17:21:31,284 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [700923458] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:31,284 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:31,284 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-15 17:21:31,284 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [513096484] [2021-12-15 17:21:31,284 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:31,284 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:21:31,285 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:31,285 INFO L85 PathProgramCache]: Analyzing trace with hash -1589325569, now seen corresponding path program 1 times [2021-12-15 17:21:31,285 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:31,285 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1162339748] [2021-12-15 17:21:31,285 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:31,285 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:31,290 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:31,301 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:31,301 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:31,302 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1162339748] [2021-12-15 17:21:31,302 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1162339748] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:31,302 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:31,302 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:31,302 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [195381845] [2021-12-15 17:21:31,302 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:31,302 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:21:31,303 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:21:31,303 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:21:31,303 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:21:31,303 INFO L87 Difference]: Start difference. First operand 1671 states and 2378 transitions. cyclomatic complexity: 715 Second operand has 3 states, 3 states have (on average 16.333333333333332) internal successors, (49), 2 states have internal predecessors, (49), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:31,350 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:21:31,350 INFO L93 Difference]: Finished difference Result 2337 states and 3303 transitions. [2021-12-15 17:21:31,350 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:21:31,352 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2337 states and 3303 transitions. [2021-12-15 17:21:31,368 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 2275 [2021-12-15 17:21:31,379 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2337 states to 2337 states and 3303 transitions. [2021-12-15 17:21:31,379 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2337 [2021-12-15 17:21:31,381 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2337 [2021-12-15 17:21:31,381 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2337 states and 3303 transitions. [2021-12-15 17:21:31,392 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:21:31,393 INFO L681 BuchiCegarLoop]: Abstraction has 2337 states and 3303 transitions. [2021-12-15 17:21:31,394 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2337 states and 3303 transitions. [2021-12-15 17:21:31,409 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2337 to 1647. [2021-12-15 17:21:31,411 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1647 states, 1647 states have (on average 1.4189435336976322) internal successors, (2337), 1646 states have internal predecessors, (2337), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:31,416 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1647 states to 1647 states and 2337 transitions. [2021-12-15 17:21:31,416 INFO L704 BuchiCegarLoop]: Abstraction has 1647 states and 2337 transitions. [2021-12-15 17:21:31,416 INFO L587 BuchiCegarLoop]: Abstraction has 1647 states and 2337 transitions. [2021-12-15 17:21:31,416 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2021-12-15 17:21:31,416 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1647 states and 2337 transitions. [2021-12-15 17:21:31,422 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1592 [2021-12-15 17:21:31,422 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:21:31,422 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:21:31,423 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:31,426 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:31,426 INFO L791 eck$LassoCheckResult]: Stem: 12678#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 12626#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 12590#L615 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 12541#L274 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12542#L281 assume 1 == ~m_i~0;~m_st~0 := 0; 12601#L281-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12416#L286-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12417#L291-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 12640#L296-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12377#L418 assume !(0 == ~M_E~0); 12378#L418-2 assume !(0 == ~T1_E~0); 12600#L423-1 assume !(0 == ~T2_E~0); 12645#L428-1 assume !(0 == ~T3_E~0); 12643#L433-1 assume !(0 == ~E_1~0); 12630#L438-1 assume !(0 == ~E_2~0); 12559#L443-1 assume !(0 == ~E_3~0); 12554#L448-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12512#L197 assume !(1 == ~m_pc~0); 12509#L197-2 is_master_triggered_~__retres1~0#1 := 0; 12671#L208 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12672#L209 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 12657#L510 assume !(0 != activate_threads_~tmp~1#1); 12361#L510-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12362#L216 assume !(1 == ~t1_pc~0); 12412#L216-2 is_transmit1_triggered_~__retres1~1#1 := 0; 12413#L227 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12538#L228 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 12363#L518 assume !(0 != activate_threads_~tmp___0~0#1); 12364#L518-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12564#L235 assume !(1 == ~t2_pc~0); 12635#L235-2 is_transmit2_triggered_~__retres1~2#1 := 0; 12496#L246 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12497#L247 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 12561#L526 assume !(0 != activate_threads_~tmp___1~0#1); 12664#L526-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12484#L254 assume !(1 == ~t3_pc~0); 12420#L254-2 is_transmit3_triggered_~__retres1~3#1 := 0; 12421#L265 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12373#L266 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 12374#L534 assume !(0 != activate_threads_~tmp___2~0#1); 12490#L534-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12353#L461 assume !(1 == ~M_E~0); 12354#L461-2 assume !(1 == ~T1_E~0); 12418#L466-1 assume !(1 == ~T2_E~0); 12651#L471-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 12441#L476-1 assume !(1 == ~E_1~0); 12442#L481-1 assume !(1 == ~E_2~0); 12581#L486-1 assume !(1 == ~E_3~0); 12455#L491-1 assume { :end_inline_reset_delta_events } true; 12456#L652-2 [2021-12-15 17:21:31,426 INFO L793 eck$LassoCheckResult]: Loop: 12456#L652-2 assume !false; 13326#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 13319#L393 assume !false; 13316#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 13314#L309 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 13306#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 13299#L332 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 13292#L346 assume !(0 != eval_~tmp~0#1); 13293#L408 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 13999#L274-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 13998#L418-3 assume !(0 == ~M_E~0); 13997#L418-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 13996#L423-3 assume !(0 == ~T2_E~0); 13995#L428-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 13994#L433-3 assume 0 == ~E_1~0;~E_1~0 := 1; 13993#L438-3 assume !(0 == ~E_2~0); 13992#L443-3 assume 0 == ~E_3~0;~E_3~0 := 1; 13991#L448-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13990#L197-12 assume !(1 == ~m_pc~0); 13988#L197-14 is_master_triggered_~__retres1~0#1 := 0; 13986#L208-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13983#L209-4 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 13981#L510-12 assume !(0 != activate_threads_~tmp~1#1); 13980#L510-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12476#L216-12 assume !(1 == ~t1_pc~0); 12477#L216-14 is_transmit1_triggered_~__retres1~1#1 := 0; 12526#L227-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12437#L228-4 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 12438#L518-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 12414#L518-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12415#L235-12 assume 1 == ~t2_pc~0; 12629#L236-4 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 12495#L246-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12661#L247-4 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 12662#L526-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 12555#L526-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12556#L254-12 assume !(1 == ~t3_pc~0); 12658#L254-14 is_transmit3_triggered_~__retres1~3#1 := 0; 13978#L265-4 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13977#L266-4 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 13976#L534-12 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 13975#L534-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12480#L461-3 assume !(1 == ~M_E~0); 12481#L461-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12570#L466-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12571#L471-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 12472#L476-3 assume 1 == ~E_1~0;~E_1~0 := 2; 12473#L481-3 assume 1 == ~E_2~0;~E_2~0 := 2; 12504#L486-3 assume !(1 == ~E_3~0); 12505#L491-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 12387#L309-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 12388#L331-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 12419#L332-1 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 12445#L671 assume !(0 == start_simulation_~tmp~3#1); 12572#L671-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 13366#L309-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 13362#L331-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 13357#L332-2 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 13353#L626 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 13346#L633 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 13342#L634 start_simulation_#t~ret15#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 13338#L684 assume !(0 != start_simulation_~tmp___0~1#1); 12456#L652-2 [2021-12-15 17:21:31,427 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:31,427 INFO L85 PathProgramCache]: Analyzing trace with hash 372621552, now seen corresponding path program 1 times [2021-12-15 17:21:31,427 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:31,427 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1584809572] [2021-12-15 17:21:31,427 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:31,428 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:31,433 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:31,465 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:31,466 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:31,466 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1584809572] [2021-12-15 17:21:31,466 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1584809572] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:31,466 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:31,466 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:31,466 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [313008444] [2021-12-15 17:21:31,467 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:31,467 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:21:31,467 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:31,467 INFO L85 PathProgramCache]: Analyzing trace with hash 779423320, now seen corresponding path program 1 times [2021-12-15 17:21:31,467 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:31,468 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [578886861] [2021-12-15 17:21:31,468 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:31,468 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:31,473 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:31,485 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:31,485 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:31,486 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [578886861] [2021-12-15 17:21:31,486 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [578886861] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:31,486 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:31,486 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:31,486 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [420922426] [2021-12-15 17:21:31,486 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:31,487 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:21:31,487 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:21:31,487 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-15 17:21:31,487 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-15 17:21:31,488 INFO L87 Difference]: Start difference. First operand 1647 states and 2337 transitions. cyclomatic complexity: 694 Second operand has 4 states, 4 states have (on average 12.25) internal successors, (49), 3 states have internal predecessors, (49), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:31,548 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:21:31,548 INFO L93 Difference]: Finished difference Result 2662 states and 3742 transitions. [2021-12-15 17:21:31,549 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-15 17:21:31,549 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2662 states and 3742 transitions. [2021-12-15 17:21:31,562 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 2567 [2021-12-15 17:21:31,573 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2662 states to 2662 states and 3742 transitions. [2021-12-15 17:21:31,573 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2662 [2021-12-15 17:21:31,575 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2662 [2021-12-15 17:21:31,575 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2662 states and 3742 transitions. [2021-12-15 17:21:31,577 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:21:31,578 INFO L681 BuchiCegarLoop]: Abstraction has 2662 states and 3742 transitions. [2021-12-15 17:21:31,579 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2662 states and 3742 transitions. [2021-12-15 17:21:31,598 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2662 to 1973. [2021-12-15 17:21:31,601 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1973 states, 1973 states have (on average 1.4100354789660416) internal successors, (2782), 1972 states have internal predecessors, (2782), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:31,606 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1973 states to 1973 states and 2782 transitions. [2021-12-15 17:21:31,606 INFO L704 BuchiCegarLoop]: Abstraction has 1973 states and 2782 transitions. [2021-12-15 17:21:31,606 INFO L587 BuchiCegarLoop]: Abstraction has 1973 states and 2782 transitions. [2021-12-15 17:21:31,606 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2021-12-15 17:21:31,607 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1973 states and 2782 transitions. [2021-12-15 17:21:31,613 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1884 [2021-12-15 17:21:31,613 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:21:31,614 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:21:31,614 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:31,614 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:31,615 INFO L791 eck$LassoCheckResult]: Stem: 17002#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 16948#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 16913#L615 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 16864#L274 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 16865#L281 assume 1 == ~m_i~0;~m_st~0 := 0; 16924#L281-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 16735#L286-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 16736#L291-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 16962#L296-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 16699#L418 assume !(0 == ~M_E~0); 16700#L418-2 assume !(0 == ~T1_E~0); 16923#L423-1 assume !(0 == ~T2_E~0); 16967#L428-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 16964#L433-1 assume !(0 == ~E_1~0); 16965#L438-1 assume !(0 == ~E_2~0); 16880#L443-1 assume !(0 == ~E_3~0); 16875#L448-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16835#L197 assume !(1 == ~m_pc~0); 16832#L197-2 is_master_triggered_~__retres1~0#1 := 0; 16992#L208 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16993#L209 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 17027#L510 assume !(0 != activate_threads_~tmp~1#1); 16680#L510-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16681#L216 assume !(1 == ~t1_pc~0); 16733#L216-2 is_transmit1_triggered_~__retres1~1#1 := 0; 16734#L227 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16860#L228 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 16682#L518 assume !(0 != activate_threads_~tmp___0~0#1); 16683#L518-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 17000#L235 assume !(1 == ~t2_pc~0); 16958#L235-2 is_transmit2_triggered_~__retres1~2#1 := 0; 16959#L246 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17019#L247 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 17018#L526 assume !(0 != activate_threads_~tmp___1~0#1); 17017#L526-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16805#L254 assume !(1 == ~t3_pc~0); 16806#L254-2 is_transmit3_triggered_~__retres1~3#1 := 0; 16828#L265 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16829#L266 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 17013#L534 assume !(0 != activate_threads_~tmp___2~0#1); 16812#L534-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16672#L461 assume !(1 == ~M_E~0); 16673#L461-2 assume !(1 == ~T1_E~0); 16737#L466-1 assume !(1 == ~T2_E~0); 16972#L471-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 16760#L476-1 assume !(1 == ~E_1~0); 16761#L481-1 assume !(1 == ~E_2~0); 16905#L486-1 assume !(1 == ~E_3~0); 16776#L491-1 assume { :end_inline_reset_delta_events } true; 16777#L652-2 [2021-12-15 17:21:31,615 INFO L793 eck$LassoCheckResult]: Loop: 16777#L652-2 assume !false; 18112#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 18110#L393 assume !false; 18108#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 18106#L309 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 18098#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 18090#L332 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 18084#L346 assume !(0 != eval_~tmp~0#1); 18085#L408 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 18333#L274-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 18332#L418-3 assume !(0 == ~M_E~0); 18331#L418-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 18330#L423-3 assume !(0 == ~T2_E~0); 18328#L428-3 assume !(0 == ~T3_E~0); 18327#L433-3 assume 0 == ~E_1~0;~E_1~0 := 1; 18326#L438-3 assume !(0 == ~E_2~0); 18325#L443-3 assume 0 == ~E_3~0;~E_3~0 := 1; 18324#L448-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 18323#L197-12 assume !(1 == ~m_pc~0); 18321#L197-14 is_master_triggered_~__retres1~0#1 := 0; 18320#L208-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 18319#L209-4 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 18318#L510-12 assume !(0 != activate_threads_~tmp~1#1); 18317#L510-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 18316#L216-12 assume !(1 == ~t1_pc~0); 18315#L216-14 is_transmit1_triggered_~__retres1~1#1 := 0; 18314#L227-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18313#L228-4 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 18312#L518-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 18311#L518-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18310#L235-12 assume !(1 == ~t2_pc~0); 18308#L235-14 is_transmit2_triggered_~__retres1~2#1 := 0; 18307#L246-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 18306#L247-4 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 18305#L526-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 18304#L526-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18303#L254-12 assume !(1 == ~t3_pc~0); 18302#L254-14 is_transmit3_triggered_~__retres1~3#1 := 0; 18301#L265-4 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18300#L266-4 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 18299#L534-12 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 18298#L534-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 18297#L461-3 assume !(1 == ~M_E~0); 17537#L461-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 18296#L466-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 18294#L471-3 assume !(1 == ~T3_E~0); 18292#L476-3 assume 1 == ~E_1~0;~E_1~0 := 2; 18291#L481-3 assume 1 == ~E_2~0;~E_2~0 := 2; 18290#L486-3 assume !(1 == ~E_3~0); 18289#L491-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 18287#L309-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 18284#L331-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 18283#L332-1 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 16895#L671 assume !(0 == start_simulation_~tmp~3#1); 16896#L671-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 18220#L309-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 18217#L331-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 18212#L332-2 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 18208#L626 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 18202#L633 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 18195#L634 start_simulation_#t~ret15#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 18189#L684 assume !(0 != start_simulation_~tmp___0~1#1); 16777#L652-2 [2021-12-15 17:21:31,615 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:31,616 INFO L85 PathProgramCache]: Analyzing trace with hash -286909970, now seen corresponding path program 1 times [2021-12-15 17:21:31,616 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:31,616 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [416426836] [2021-12-15 17:21:31,616 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:31,616 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:31,620 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:31,632 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:31,632 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:31,633 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [416426836] [2021-12-15 17:21:31,633 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [416426836] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:31,633 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:31,633 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:31,633 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [780796255] [2021-12-15 17:21:31,633 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:31,634 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:21:31,634 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:31,634 INFO L85 PathProgramCache]: Analyzing trace with hash 94531323, now seen corresponding path program 1 times [2021-12-15 17:21:31,634 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:31,634 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [562920210] [2021-12-15 17:21:31,635 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:31,635 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:31,639 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:31,654 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:31,654 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:31,655 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [562920210] [2021-12-15 17:21:31,655 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [562920210] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:31,655 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:31,655 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:31,655 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1015498429] [2021-12-15 17:21:31,655 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:31,656 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:21:31,656 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:21:31,656 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-15 17:21:31,656 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-15 17:21:31,657 INFO L87 Difference]: Start difference. First operand 1973 states and 2782 transitions. cyclomatic complexity: 813 Second operand has 4 states, 4 states have (on average 12.25) internal successors, (49), 3 states have internal predecessors, (49), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:31,704 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:21:31,705 INFO L93 Difference]: Finished difference Result 2332 states and 3260 transitions. [2021-12-15 17:21:31,705 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-15 17:21:31,705 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2332 states and 3260 transitions. [2021-12-15 17:21:31,715 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 2275 [2021-12-15 17:21:31,724 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2332 states to 2332 states and 3260 transitions. [2021-12-15 17:21:31,725 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2332 [2021-12-15 17:21:31,726 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2332 [2021-12-15 17:21:31,727 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2332 states and 3260 transitions. [2021-12-15 17:21:31,729 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:21:31,729 INFO L681 BuchiCegarLoop]: Abstraction has 2332 states and 3260 transitions. [2021-12-15 17:21:31,730 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2332 states and 3260 transitions. [2021-12-15 17:21:31,779 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2332 to 1647. [2021-12-15 17:21:31,781 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1647 states, 1647 states have (on average 1.403157255616272) internal successors, (2311), 1646 states have internal predecessors, (2311), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:31,785 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1647 states to 1647 states and 2311 transitions. [2021-12-15 17:21:31,785 INFO L704 BuchiCegarLoop]: Abstraction has 1647 states and 2311 transitions. [2021-12-15 17:21:31,785 INFO L587 BuchiCegarLoop]: Abstraction has 1647 states and 2311 transitions. [2021-12-15 17:21:31,785 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2021-12-15 17:21:31,785 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1647 states and 2311 transitions. [2021-12-15 17:21:31,790 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1592 [2021-12-15 17:21:31,790 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:21:31,790 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:21:31,790 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:31,791 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:31,791 INFO L791 eck$LassoCheckResult]: Stem: 21319#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 21260#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 21224#L615 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 21176#L274 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 21177#L281 assume 1 == ~m_i~0;~m_st~0 := 0; 21234#L281-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 21048#L286-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 21049#L291-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 21273#L296-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 21013#L418 assume !(0 == ~M_E~0); 21014#L418-2 assume !(0 == ~T1_E~0); 21233#L423-1 assume !(0 == ~T2_E~0); 21278#L428-1 assume !(0 == ~T3_E~0); 21275#L433-1 assume !(0 == ~E_1~0); 21264#L438-1 assume !(0 == ~E_2~0); 21192#L443-1 assume !(0 == ~E_3~0); 21187#L448-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 21149#L197 assume !(1 == ~m_pc~0); 21146#L197-2 is_master_triggered_~__retres1~0#1 := 0; 21311#L208 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21312#L209 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 21291#L510 assume !(0 != activate_threads_~tmp~1#1); 20995#L510-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 20996#L216 assume !(1 == ~t1_pc~0); 21046#L216-2 is_transmit1_triggered_~__retres1~1#1 := 0; 21047#L227 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 21173#L228 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 20997#L518 assume !(0 != activate_threads_~tmp___0~0#1); 20998#L518-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 21198#L235 assume !(1 == ~t2_pc~0); 21272#L235-2 is_transmit2_triggered_~__retres1~2#1 := 0; 21132#L246 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 21133#L247 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 21194#L526 assume !(0 != activate_threads_~tmp___1~0#1); 21299#L526-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 21120#L254 assume !(1 == ~t3_pc~0); 21052#L254-2 is_transmit3_triggered_~__retres1~3#1 := 0; 21053#L265 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 21007#L266 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 21008#L534 assume !(0 != activate_threads_~tmp___2~0#1); 21126#L534-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 20987#L461 assume !(1 == ~M_E~0); 20988#L461-2 assume !(1 == ~T1_E~0); 21050#L466-1 assume !(1 == ~T2_E~0); 21282#L471-1 assume !(1 == ~T3_E~0); 21074#L476-1 assume !(1 == ~E_1~0); 21075#L481-1 assume !(1 == ~E_2~0); 21214#L486-1 assume !(1 == ~E_3~0); 21092#L491-1 assume { :end_inline_reset_delta_events } true; 21003#L652-2 [2021-12-15 17:21:31,791 INFO L793 eck$LassoCheckResult]: Loop: 21003#L652-2 assume !false; 21004#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 21103#L393 assume !false; 21237#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 21292#L309 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 21042#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 21227#L332 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 21093#L346 assume !(0 != eval_~tmp~0#1); 21094#L408 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 21289#L274-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 21290#L418-3 assume !(0 == ~M_E~0); 21195#L418-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 21196#L423-3 assume !(0 == ~T2_E~0); 21193#L428-3 assume !(0 == ~T3_E~0); 21147#L433-3 assume 0 == ~E_1~0;~E_1~0 := 1; 21148#L438-3 assume !(0 == ~E_2~0); 21244#L443-3 assume 0 == ~E_3~0;~E_3~0 := 1; 20989#L448-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20990#L197-12 assume !(1 == ~m_pc~0); 21251#L197-14 is_master_triggered_~__retres1~0#1 := 0; 21114#L208-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21115#L209-4 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 21001#L510-12 assume !(0 != activate_threads_~tmp~1#1); 21002#L510-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 21112#L216-12 assume !(1 == ~t1_pc~0); 21113#L216-14 is_transmit1_triggered_~__retres1~1#1 := 0; 21163#L227-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 21070#L228-4 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 21071#L518-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 21044#L518-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 21045#L235-12 assume !(1 == ~t2_pc~0); 21130#L235-14 is_transmit2_triggered_~__retres1~2#1 := 0; 21131#L246-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 21296#L247-4 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 21297#L526-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 21188#L526-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 21189#L254-12 assume !(1 == ~t3_pc~0); 21293#L254-14 is_transmit3_triggered_~__retres1~3#1 := 0; 22633#L265-4 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22632#L266-4 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 22629#L534-12 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 22627#L534-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 22625#L461-3 assume !(1 == ~M_E~0); 21326#L461-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 21203#L466-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 21204#L471-3 assume !(1 == ~T3_E~0); 21107#L476-3 assume 1 == ~E_1~0;~E_1~0 := 2; 21108#L481-3 assume 1 == ~E_2~0;~E_2~0 := 2; 21141#L486-3 assume !(1 == ~E_3~0); 21142#L491-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 22402#L309-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 22395#L331-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 21078#L332-1 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 21079#L671 assume !(0 == start_simulation_~tmp~3#1); 21010#L671-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 21238#L309-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 21105#L331-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 21174#L332-2 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 21175#L626 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 21218#L633 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 21219#L634 start_simulation_#t~ret15#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 21223#L684 assume !(0 != start_simulation_~tmp___0~1#1); 21003#L652-2 [2021-12-15 17:21:31,791 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:31,791 INFO L85 PathProgramCache]: Analyzing trace with hash 374468594, now seen corresponding path program 1 times [2021-12-15 17:21:31,792 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:31,792 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1484940408] [2021-12-15 17:21:31,792 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:31,792 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:31,798 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:21:31,798 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-15 17:21:31,801 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:21:31,830 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-15 17:21:31,831 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:31,831 INFO L85 PathProgramCache]: Analyzing trace with hash 94531323, now seen corresponding path program 2 times [2021-12-15 17:21:31,831 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:31,831 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [107691680] [2021-12-15 17:21:31,831 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:31,831 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:31,837 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:31,848 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:31,848 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:31,848 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [107691680] [2021-12-15 17:21:31,848 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [107691680] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:31,848 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:31,848 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:31,848 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [219030569] [2021-12-15 17:21:31,849 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:31,849 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:21:31,849 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:21:31,849 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:21:31,850 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:21:31,850 INFO L87 Difference]: Start difference. First operand 1647 states and 2311 transitions. cyclomatic complexity: 668 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:31,893 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:21:31,893 INFO L93 Difference]: Finished difference Result 2378 states and 3318 transitions. [2021-12-15 17:21:31,893 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:21:31,894 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2378 states and 3318 transitions. [2021-12-15 17:21:31,903 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2287 [2021-12-15 17:21:31,912 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2378 states to 2378 states and 3318 transitions. [2021-12-15 17:21:31,912 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2378 [2021-12-15 17:21:31,914 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2378 [2021-12-15 17:21:31,914 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2378 states and 3318 transitions. [2021-12-15 17:21:31,917 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:21:31,917 INFO L681 BuchiCegarLoop]: Abstraction has 2378 states and 3318 transitions. [2021-12-15 17:21:31,918 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2378 states and 3318 transitions. [2021-12-15 17:21:31,944 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2378 to 2374. [2021-12-15 17:21:31,948 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2374 states, 2374 states have (on average 1.395956192080876) internal successors, (3314), 2373 states have internal predecessors, (3314), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:31,953 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2374 states to 2374 states and 3314 transitions. [2021-12-15 17:21:31,953 INFO L704 BuchiCegarLoop]: Abstraction has 2374 states and 3314 transitions. [2021-12-15 17:21:31,953 INFO L587 BuchiCegarLoop]: Abstraction has 2374 states and 3314 transitions. [2021-12-15 17:21:31,953 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2021-12-15 17:21:31,953 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2374 states and 3314 transitions. [2021-12-15 17:21:31,959 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2283 [2021-12-15 17:21:31,959 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:21:31,959 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:21:31,960 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:31,960 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:31,960 INFO L791 eck$LassoCheckResult]: Stem: 25361#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 25296#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 25257#L615 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 25206#L274 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 25207#L281 assume 1 == ~m_i~0;~m_st~0 := 0; 25267#L281-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 25079#L286-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 25080#L291-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 25308#L296-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 25045#L418 assume !(0 == ~M_E~0); 25046#L418-2 assume !(0 == ~T1_E~0); 25266#L423-1 assume !(0 == ~T2_E~0); 25313#L428-1 assume !(0 == ~T3_E~0); 25311#L433-1 assume !(0 == ~E_1~0); 25299#L438-1 assume !(0 == ~E_2~0); 25225#L443-1 assume 0 == ~E_3~0;~E_3~0 := 1; 25218#L448-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 25219#L197 assume !(1 == ~m_pc~0); 25343#L197-2 is_master_triggered_~__retres1~0#1 := 0; 25344#L208 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 25351#L209 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 25352#L510 assume !(0 != activate_threads_~tmp~1#1); 25026#L510-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 25027#L216 assume !(1 == ~t1_pc~0); 25345#L216-2 is_transmit1_triggered_~__retres1~1#1 := 0; 25211#L227 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 25212#L228 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 25405#L518 assume !(0 != activate_threads_~tmp___0~0#1); 25404#L518-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 25403#L235 assume !(1 == ~t2_pc~0); 25305#L235-2 is_transmit2_triggered_~__retres1~2#1 := 0; 25162#L246 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 25163#L247 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 25229#L526 assume !(0 != activate_threads_~tmp___1~0#1); 25333#L526-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 25152#L254 assume !(1 == ~t3_pc~0); 25083#L254-2 is_transmit3_triggered_~__retres1~3#1 := 0; 25084#L265 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 25038#L266 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 25039#L534 assume !(0 != activate_threads_~tmp___2~0#1); 25155#L534-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 25018#L461 assume !(1 == ~M_E~0); 25019#L461-2 assume !(1 == ~T1_E~0); 25081#L466-1 assume !(1 == ~T2_E~0); 25317#L471-1 assume !(1 == ~T3_E~0); 25104#L476-1 assume !(1 == ~E_1~0); 25105#L481-1 assume !(1 == ~E_2~0); 25249#L486-1 assume 1 == ~E_3~0;~E_3~0 := 2; 25120#L491-1 assume { :end_inline_reset_delta_events } true; 25121#L652-2 [2021-12-15 17:21:31,960 INFO L793 eck$LassoCheckResult]: Loop: 25121#L652-2 assume !false; 26037#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 26035#L393 assume !false; 26033#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 25979#L309 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 25973#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 25967#L332 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 25961#L346 assume !(0 != eval_~tmp~0#1); 25962#L408 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 26251#L274-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 26248#L418-3 assume !(0 == ~M_E~0); 26245#L418-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 26242#L423-3 assume !(0 == ~T2_E~0); 26239#L428-3 assume !(0 == ~T3_E~0); 26236#L433-3 assume 0 == ~E_1~0;~E_1~0 := 1; 26235#L438-3 assume !(0 == ~E_2~0); 26232#L443-3 assume !(0 == ~E_3~0); 26230#L448-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 26227#L197-12 assume !(1 == ~m_pc~0); 26223#L197-14 is_master_triggered_~__retres1~0#1 := 0; 26220#L208-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 26215#L209-4 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 26211#L510-12 assume !(0 != activate_threads_~tmp~1#1); 26208#L510-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26206#L216-12 assume !(1 == ~t1_pc~0); 26204#L216-14 is_transmit1_triggered_~__retres1~1#1 := 0; 26178#L227-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 26169#L228-4 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 26165#L518-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 26160#L518-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 26156#L235-12 assume !(1 == ~t2_pc~0); 26151#L235-14 is_transmit2_triggered_~__retres1~2#1 := 0; 26147#L246-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 26143#L247-4 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 26141#L526-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 26140#L526-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 26139#L254-12 assume !(1 == ~t3_pc~0); 26138#L254-14 is_transmit3_triggered_~__retres1~3#1 := 0; 26136#L265-4 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 26134#L266-4 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 26132#L534-12 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 26130#L534-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 26127#L461-3 assume !(1 == ~M_E~0); 25783#L461-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 26124#L466-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 26122#L471-3 assume !(1 == ~T3_E~0); 26121#L476-3 assume 1 == ~E_1~0;~E_1~0 := 2; 26120#L481-3 assume 1 == ~E_2~0;~E_2~0 := 2; 26070#L486-3 assume !(1 == ~E_3~0); 26068#L491-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 26062#L309-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 26058#L331-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 26056#L332-1 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 26054#L671 assume !(0 == start_simulation_~tmp~3#1); 26055#L671-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 26174#L309-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 26168#L331-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 26164#L332-2 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 26159#L626 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 26155#L633 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 26150#L634 start_simulation_#t~ret15#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 26146#L684 assume !(0 != start_simulation_~tmp___0~1#1); 25121#L652-2 [2021-12-15 17:21:31,961 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:31,961 INFO L85 PathProgramCache]: Analyzing trace with hash -1676515466, now seen corresponding path program 1 times [2021-12-15 17:21:31,961 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:31,961 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [690102691] [2021-12-15 17:21:31,961 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:31,961 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:31,971 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:31,987 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:31,987 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:31,987 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [690102691] [2021-12-15 17:21:31,987 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [690102691] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:31,987 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:31,987 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:31,987 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [294201390] [2021-12-15 17:21:31,988 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:31,988 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:21:31,988 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:31,988 INFO L85 PathProgramCache]: Analyzing trace with hash 2022804025, now seen corresponding path program 1 times [2021-12-15 17:21:31,988 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:31,988 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [905058709] [2021-12-15 17:21:31,988 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:31,989 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:31,994 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:32,018 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:32,020 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:32,020 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [905058709] [2021-12-15 17:21:32,020 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [905058709] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:32,020 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:32,020 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-15 17:21:32,020 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [398401181] [2021-12-15 17:21:32,021 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:32,021 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:21:32,021 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:21:32,021 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-15 17:21:32,021 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-15 17:21:32,021 INFO L87 Difference]: Start difference. First operand 2374 states and 3314 transitions. cyclomatic complexity: 944 Second operand has 4 states, 4 states have (on average 12.25) internal successors, (49), 3 states have internal predecessors, (49), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:32,126 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:21:32,126 INFO L93 Difference]: Finished difference Result 3020 states and 4212 transitions. [2021-12-15 17:21:32,126 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-15 17:21:32,127 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3020 states and 4212 transitions. [2021-12-15 17:21:32,137 INFO L131 ngComponentsAnalysis]: Automaton has 10 accepting balls. 2866 [2021-12-15 17:21:32,156 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3020 states to 3020 states and 4212 transitions. [2021-12-15 17:21:32,156 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3020 [2021-12-15 17:21:32,158 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3020 [2021-12-15 17:21:32,158 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3020 states and 4212 transitions. [2021-12-15 17:21:32,161 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:21:32,161 INFO L681 BuchiCegarLoop]: Abstraction has 3020 states and 4212 transitions. [2021-12-15 17:21:32,162 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3020 states and 4212 transitions. [2021-12-15 17:21:32,190 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3020 to 2196. [2021-12-15 17:21:32,193 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2196 states, 2196 states have (on average 1.3966302367941712) internal successors, (3067), 2195 states have internal predecessors, (3067), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:32,197 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2196 states to 2196 states and 3067 transitions. [2021-12-15 17:21:32,197 INFO L704 BuchiCegarLoop]: Abstraction has 2196 states and 3067 transitions. [2021-12-15 17:21:32,197 INFO L587 BuchiCegarLoop]: Abstraction has 2196 states and 3067 transitions. [2021-12-15 17:21:32,198 INFO L425 BuchiCegarLoop]: ======== Iteration 13============ [2021-12-15 17:21:32,198 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2196 states and 3067 transitions. [2021-12-15 17:21:32,202 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2139 [2021-12-15 17:21:32,203 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:21:32,203 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:21:32,206 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:32,206 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:32,206 INFO L791 eck$LassoCheckResult]: Stem: 30763#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 30696#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 30659#L615 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 30612#L274 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 30613#L281 assume 1 == ~m_i~0;~m_st~0 := 0; 30671#L281-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 30484#L286-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 30485#L291-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 30713#L296-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 30452#L418 assume !(0 == ~M_E~0); 30453#L418-2 assume !(0 == ~T1_E~0); 30670#L423-1 assume !(0 == ~T2_E~0); 30719#L428-1 assume !(0 == ~T3_E~0); 30717#L433-1 assume !(0 == ~E_1~0); 30702#L438-1 assume !(0 == ~E_2~0); 30628#L443-1 assume !(0 == ~E_3~0); 30623#L448-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 30583#L197 assume !(1 == ~m_pc~0); 30580#L197-2 is_master_triggered_~__retres1~0#1 := 0; 30750#L208 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 30754#L209 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 30729#L510 assume !(0 != activate_threads_~tmp~1#1); 30432#L510-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 30433#L216 assume !(1 == ~t1_pc~0); 30482#L216-2 is_transmit1_triggered_~__retres1~1#1 := 0; 30483#L227 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 30609#L228 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 30434#L518 assume !(0 != activate_threads_~tmp___0~0#1); 30435#L518-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 30636#L235 assume !(1 == ~t2_pc~0); 30712#L235-2 is_transmit2_triggered_~__retres1~2#1 := 0; 30569#L246 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 30570#L247 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 30630#L526 assume !(0 != activate_threads_~tmp___1~0#1); 30739#L526-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 30558#L254 assume !(1 == ~t3_pc~0); 30488#L254-2 is_transmit3_triggered_~__retres1~3#1 := 0; 30489#L265 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 30444#L266 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 30445#L534 assume !(0 != activate_threads_~tmp___2~0#1); 30561#L534-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 30424#L461 assume !(1 == ~M_E~0); 30425#L461-2 assume !(1 == ~T1_E~0); 30486#L466-1 assume !(1 == ~T2_E~0); 30723#L471-1 assume !(1 == ~T3_E~0); 30510#L476-1 assume !(1 == ~E_1~0); 30511#L481-1 assume !(1 == ~E_2~0); 30651#L486-1 assume !(1 == ~E_3~0); 30527#L491-1 assume { :end_inline_reset_delta_events } true; 30528#L652-2 [2021-12-15 17:21:32,206 INFO L793 eck$LassoCheckResult]: Loop: 30528#L652-2 assume !false; 32079#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 32077#L393 assume !false; 32075#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 32073#L309 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 32068#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 32066#L332 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 32063#L346 assume !(0 != eval_~tmp~0#1); 32064#L408 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 32270#L274-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 32265#L418-3 assume !(0 == ~M_E~0); 32261#L418-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 32257#L423-3 assume !(0 == ~T2_E~0); 32253#L428-3 assume !(0 == ~T3_E~0); 32244#L433-3 assume 0 == ~E_1~0;~E_1~0 := 1; 32241#L438-3 assume !(0 == ~E_2~0); 32233#L443-3 assume !(0 == ~E_3~0); 32232#L448-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 32230#L197-12 assume !(1 == ~m_pc~0); 32082#L197-14 is_master_triggered_~__retres1~0#1 := 0; 32078#L208-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 32076#L209-4 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 32074#L510-12 assume !(0 != activate_threads_~tmp~1#1); 32069#L510-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 32067#L216-12 assume !(1 == ~t1_pc~0); 32065#L216-14 is_transmit1_triggered_~__retres1~1#1 := 0; 32062#L227-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 32035#L228-4 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 32025#L518-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 32021#L518-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 32015#L235-12 assume !(1 == ~t2_pc~0); 32010#L235-14 is_transmit2_triggered_~__retres1~2#1 := 0; 32004#L246-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 31996#L247-4 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 31990#L526-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 31985#L526-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 31981#L254-12 assume !(1 == ~t3_pc~0); 31975#L254-14 is_transmit3_triggered_~__retres1~3#1 := 0; 31962#L265-4 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 31956#L266-4 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 31951#L534-12 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 31944#L534-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 31936#L461-3 assume !(1 == ~M_E~0); 30856#L461-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 30853#L466-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 30850#L471-3 assume !(1 == ~T3_E~0); 30847#L476-3 assume 1 == ~E_1~0;~E_1~0 := 2; 30844#L481-3 assume 1 == ~E_2~0;~E_2~0 := 2; 30841#L486-3 assume !(1 == ~E_3~0); 30838#L491-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 30835#L309-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 30828#L331-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 30826#L332-1 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 30823#L671 assume !(0 == start_simulation_~tmp~3#1); 30824#L671-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 32097#L309-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 32095#L331-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 32093#L332-2 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 32091#L626 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 32089#L633 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 32087#L634 start_simulation_#t~ret15#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 32085#L684 assume !(0 != start_simulation_~tmp___0~1#1); 30528#L652-2 [2021-12-15 17:21:32,208 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:32,209 INFO L85 PathProgramCache]: Analyzing trace with hash 374468594, now seen corresponding path program 2 times [2021-12-15 17:21:32,209 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:32,210 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1025158145] [2021-12-15 17:21:32,210 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:32,210 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:32,218 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:21:32,218 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-15 17:21:32,222 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:21:32,232 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-15 17:21:32,233 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:32,234 INFO L85 PathProgramCache]: Analyzing trace with hash 2022804025, now seen corresponding path program 2 times [2021-12-15 17:21:32,234 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:32,234 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1828422761] [2021-12-15 17:21:32,234 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:32,234 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:32,242 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:32,260 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:32,260 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:32,261 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1828422761] [2021-12-15 17:21:32,261 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1828422761] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:32,261 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:32,261 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-15 17:21:32,261 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [664121695] [2021-12-15 17:21:32,261 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:32,261 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:21:32,261 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:21:32,262 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-15 17:21:32,262 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-15 17:21:32,262 INFO L87 Difference]: Start difference. First operand 2196 states and 3067 transitions. cyclomatic complexity: 875 Second operand has 5 states, 5 states have (on average 12.4) internal successors, (62), 5 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:32,337 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:21:32,338 INFO L93 Difference]: Finished difference Result 3785 states and 5224 transitions. [2021-12-15 17:21:32,338 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2021-12-15 17:21:32,339 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3785 states and 5224 transitions. [2021-12-15 17:21:32,350 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3722 [2021-12-15 17:21:32,360 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3785 states to 3785 states and 5224 transitions. [2021-12-15 17:21:32,360 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3785 [2021-12-15 17:21:32,362 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3785 [2021-12-15 17:21:32,363 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3785 states and 5224 transitions. [2021-12-15 17:21:32,366 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:21:32,366 INFO L681 BuchiCegarLoop]: Abstraction has 3785 states and 5224 transitions. [2021-12-15 17:21:32,367 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3785 states and 5224 transitions. [2021-12-15 17:21:32,426 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3785 to 2232. [2021-12-15 17:21:32,429 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2232 states, 2232 states have (on average 1.3902329749103943) internal successors, (3103), 2231 states have internal predecessors, (3103), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:32,433 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2232 states to 2232 states and 3103 transitions. [2021-12-15 17:21:32,433 INFO L704 BuchiCegarLoop]: Abstraction has 2232 states and 3103 transitions. [2021-12-15 17:21:32,433 INFO L587 BuchiCegarLoop]: Abstraction has 2232 states and 3103 transitions. [2021-12-15 17:21:32,433 INFO L425 BuchiCegarLoop]: ======== Iteration 14============ [2021-12-15 17:21:32,434 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2232 states and 3103 transitions. [2021-12-15 17:21:32,438 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2175 [2021-12-15 17:21:32,438 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:21:32,438 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:21:32,439 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:32,439 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:32,439 INFO L791 eck$LassoCheckResult]: Stem: 36746#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 36688#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 36653#L615 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 36603#L274 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 36604#L281 assume 1 == ~m_i~0;~m_st~0 := 0; 36664#L281-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 36482#L286-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 36483#L291-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 36702#L296-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 36449#L418 assume !(0 == ~M_E~0); 36450#L418-2 assume !(0 == ~T1_E~0); 36663#L423-1 assume !(0 == ~T2_E~0); 36707#L428-1 assume !(0 == ~T3_E~0); 36705#L433-1 assume !(0 == ~E_1~0); 36692#L438-1 assume !(0 == ~E_2~0); 36624#L443-1 assume !(0 == ~E_3~0); 36616#L448-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 36575#L197 assume !(1 == ~m_pc~0); 36572#L197-2 is_master_triggered_~__retres1~0#1 := 0; 36737#L208 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 36740#L209 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 36722#L510 assume !(0 != activate_threads_~tmp~1#1); 36429#L510-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 36430#L216 assume !(1 == ~t1_pc~0); 36480#L216-2 is_transmit1_triggered_~__retres1~1#1 := 0; 36481#L227 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 36600#L228 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 36431#L518 assume !(0 != activate_threads_~tmp___0~0#1); 36432#L518-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 36632#L235 assume !(1 == ~t2_pc~0); 36701#L235-2 is_transmit2_triggered_~__retres1~2#1 := 0; 36562#L246 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 36563#L247 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 36627#L526 assume !(0 != activate_threads_~tmp___1~0#1); 36727#L526-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 36552#L254 assume !(1 == ~t3_pc~0); 36486#L254-2 is_transmit3_triggered_~__retres1~3#1 := 0; 36487#L265 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 36441#L266 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 36442#L534 assume !(0 != activate_threads_~tmp___2~0#1); 36555#L534-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 36421#L461 assume !(1 == ~M_E~0); 36422#L461-2 assume !(1 == ~T1_E~0); 36484#L466-1 assume !(1 == ~T2_E~0); 36713#L471-1 assume !(1 == ~T3_E~0); 36507#L476-1 assume !(1 == ~E_1~0); 36508#L481-1 assume !(1 == ~E_2~0); 36644#L486-1 assume !(1 == ~E_3~0); 36524#L491-1 assume { :end_inline_reset_delta_events } true; 36525#L652-2 [2021-12-15 17:21:32,439 INFO L793 eck$LassoCheckResult]: Loop: 36525#L652-2 assume !false; 37544#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 37531#L393 assume !false; 37401#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 37399#L309 assume !(0 == ~m_st~0); 37397#L313 assume !(0 == ~t1_st~0); 37395#L317 assume !(0 == ~t2_st~0); 37392#L321 assume !(0 == ~t3_st~0);exists_runnable_thread_~__retres1~4#1 := 0; 37389#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 37388#L332 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 36926#L346 assume !(0 != eval_~tmp~0#1); 36739#L408 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 36718#L274-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 36719#L418-3 assume !(0 == ~M_E~0); 36753#L418-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 37529#L423-3 assume !(0 == ~T2_E~0); 36625#L428-3 assume !(0 == ~T3_E~0); 36573#L433-3 assume 0 == ~E_1~0;~E_1~0 := 1; 36574#L438-3 assume !(0 == ~E_2~0); 36672#L443-3 assume !(0 == ~E_3~0); 36423#L448-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 36424#L197-12 assume !(1 == ~m_pc~0); 36680#L197-14 is_master_triggered_~__retres1~0#1 := 0; 37726#L208-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 37725#L209-4 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 37724#L510-12 assume !(0 != activate_threads_~tmp~1#1); 37723#L510-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 36541#L216-12 assume !(1 == ~t1_pc~0); 36542#L216-14 is_transmit1_triggered_~__retres1~1#1 := 0; 37808#L227-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 37807#L228-4 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 37806#L518-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 37805#L518-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 37804#L235-12 assume !(1 == ~t2_pc~0); 37802#L235-14 is_transmit2_triggered_~__retres1~2#1 := 0; 37801#L246-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 37800#L247-4 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 37799#L526-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 37798#L526-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 37797#L254-12 assume !(1 == ~t3_pc~0); 37796#L254-14 is_transmit3_triggered_~__retres1~3#1 := 0; 37795#L265-4 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 37793#L266-4 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 37789#L534-12 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 37788#L534-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 37787#L461-3 assume !(1 == ~M_E~0); 37704#L461-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 37786#L466-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 37785#L471-3 assume !(1 == ~T3_E~0); 37690#L476-3 assume 1 == ~E_1~0;~E_1~0 := 2; 37689#L481-3 assume 1 == ~E_2~0;~E_2~0 := 2; 37688#L486-3 assume !(1 == ~E_3~0); 37687#L491-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 37685#L309-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 36955#L331-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 36949#L332-1 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 36950#L671 assume !(0 == start_simulation_~tmp~3#1); 37599#L671-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 37595#L309-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 37594#L331-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 37590#L332-2 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 37588#L626 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 37586#L633 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 37584#L634 start_simulation_#t~ret15#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 37573#L684 assume !(0 != start_simulation_~tmp___0~1#1); 36525#L652-2 [2021-12-15 17:21:32,440 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:32,440 INFO L85 PathProgramCache]: Analyzing trace with hash 374468594, now seen corresponding path program 3 times [2021-12-15 17:21:32,440 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:32,440 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [671383500] [2021-12-15 17:21:32,440 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:32,441 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:32,447 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:21:32,447 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-15 17:21:32,451 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:21:32,466 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-15 17:21:32,468 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:32,468 INFO L85 PathProgramCache]: Analyzing trace with hash 1792484659, now seen corresponding path program 1 times [2021-12-15 17:21:32,468 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:32,468 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [779913544] [2021-12-15 17:21:32,468 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:32,469 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:32,473 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:32,501 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:32,501 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:32,501 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [779913544] [2021-12-15 17:21:32,501 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [779913544] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:32,501 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:32,501 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:32,502 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [855173853] [2021-12-15 17:21:32,502 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:32,502 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:21:32,502 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:21:32,502 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:21:32,503 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:21:32,503 INFO L87 Difference]: Start difference. First operand 2232 states and 3103 transitions. cyclomatic complexity: 875 Second operand has 3 states, 3 states have (on average 21.666666666666668) internal successors, (65), 3 states have internal predecessors, (65), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:32,535 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:21:32,535 INFO L93 Difference]: Finished difference Result 3519 states and 4853 transitions. [2021-12-15 17:21:32,535 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:21:32,536 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3519 states and 4853 transitions. [2021-12-15 17:21:32,547 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3458 [2021-12-15 17:21:32,557 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3519 states to 3519 states and 4853 transitions. [2021-12-15 17:21:32,557 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3519 [2021-12-15 17:21:32,564 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3519 [2021-12-15 17:21:32,565 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3519 states and 4853 transitions. [2021-12-15 17:21:32,569 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:21:32,569 INFO L681 BuchiCegarLoop]: Abstraction has 3519 states and 4853 transitions. [2021-12-15 17:21:32,571 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3519 states and 4853 transitions. [2021-12-15 17:21:32,602 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3519 to 3391. [2021-12-15 17:21:32,607 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3391 states, 3391 states have (on average 1.3824830433500441) internal successors, (4688), 3390 states have internal predecessors, (4688), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:32,613 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3391 states to 3391 states and 4688 transitions. [2021-12-15 17:21:32,613 INFO L704 BuchiCegarLoop]: Abstraction has 3391 states and 4688 transitions. [2021-12-15 17:21:32,613 INFO L587 BuchiCegarLoop]: Abstraction has 3391 states and 4688 transitions. [2021-12-15 17:21:32,613 INFO L425 BuchiCegarLoop]: ======== Iteration 15============ [2021-12-15 17:21:32,613 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3391 states and 4688 transitions. [2021-12-15 17:21:32,620 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3330 [2021-12-15 17:21:32,620 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:21:32,620 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:21:32,622 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:32,622 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:32,622 INFO L791 eck$LassoCheckResult]: Stem: 42527#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 42458#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 42418#L615 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 42362#L274 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 42363#L281 assume 1 == ~m_i~0;~m_st~0 := 0; 42431#L281-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 42237#L286-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 42238#L291-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 42473#L296-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 42206#L418 assume !(0 == ~M_E~0); 42207#L418-2 assume !(0 == ~T1_E~0); 42430#L423-1 assume !(0 == ~T2_E~0); 42478#L428-1 assume !(0 == ~T3_E~0); 42476#L433-1 assume !(0 == ~E_1~0); 42462#L438-1 assume !(0 == ~E_2~0); 42382#L443-1 assume !(0 == ~E_3~0); 42376#L448-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 42334#L197 assume !(1 == ~m_pc~0); 42331#L197-2 is_master_triggered_~__retres1~0#1 := 0; 42510#L208 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 42515#L209 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 42489#L510 assume !(0 != activate_threads_~tmp~1#1); 42186#L510-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 42187#L216 assume !(1 == ~t1_pc~0); 42235#L216-2 is_transmit1_triggered_~__retres1~1#1 := 0; 42236#L227 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 42359#L228 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 42188#L518 assume !(0 != activate_threads_~tmp___0~0#1); 42189#L518-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 42389#L235 assume !(1 == ~t2_pc~0); 42472#L235-2 is_transmit2_triggered_~__retres1~2#1 := 0; 42319#L246 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 42320#L247 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 42385#L526 assume !(0 != activate_threads_~tmp___1~0#1); 42501#L526-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 42307#L254 assume !(1 == ~t3_pc~0); 42242#L254-2 is_transmit3_triggered_~__retres1~3#1 := 0; 42243#L265 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 42198#L266 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 42199#L534 assume !(0 != activate_threads_~tmp___2~0#1); 42312#L534-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 42178#L461 assume !(1 == ~M_E~0); 42179#L461-2 assume !(1 == ~T1_E~0); 42239#L466-1 assume !(1 == ~T2_E~0); 42482#L471-1 assume !(1 == ~T3_E~0); 42263#L476-1 assume !(1 == ~E_1~0); 42264#L481-1 assume !(1 == ~E_2~0); 42405#L486-1 assume !(1 == ~E_3~0); 42280#L491-1 assume { :end_inline_reset_delta_events } true; 42281#L652-2 [2021-12-15 17:21:32,628 INFO L793 eck$LassoCheckResult]: Loop: 42281#L652-2 assume !false; 43758#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 43755#L393 assume !false; 43753#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 43750#L309 assume !(0 == ~m_st~0); 43751#L313 assume !(0 == ~t1_st~0); 45117#L317 assume !(0 == ~t2_st~0); 45118#L321 assume !(0 == ~t3_st~0);exists_runnable_thread_~__retres1~4#1 := 0; 45119#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 45500#L332 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 45498#L346 assume !(0 != eval_~tmp~0#1); 45496#L408 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 45494#L274-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 45492#L418-3 assume !(0 == ~M_E~0); 45491#L418-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 45489#L423-3 assume !(0 == ~T2_E~0); 45487#L428-3 assume !(0 == ~T3_E~0); 45486#L433-3 assume 0 == ~E_1~0;~E_1~0 := 1; 45485#L438-3 assume !(0 == ~E_2~0); 45484#L443-3 assume !(0 == ~E_3~0); 45483#L448-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 45072#L197-12 assume !(1 == ~m_pc~0); 45069#L197-14 is_master_triggered_~__retres1~0#1 := 0; 45066#L208-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 45064#L209-4 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 45062#L510-12 assume !(0 != activate_threads_~tmp~1#1); 45060#L510-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 45058#L216-12 assume !(1 == ~t1_pc~0); 45056#L216-14 is_transmit1_triggered_~__retres1~1#1 := 0; 45054#L227-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 45052#L228-4 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 45050#L518-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 45048#L518-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 45046#L235-12 assume !(1 == ~t2_pc~0); 45042#L235-14 is_transmit2_triggered_~__retres1~2#1 := 0; 45040#L246-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 45037#L247-4 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 45035#L526-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 45033#L526-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 45031#L254-12 assume !(1 == ~t3_pc~0); 45029#L254-14 is_transmit3_triggered_~__retres1~3#1 := 0; 45027#L265-4 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 45025#L266-4 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 45023#L534-12 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 45008#L534-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 45005#L461-3 assume !(1 == ~M_E~0); 44987#L461-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 44998#L466-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 44994#L471-3 assume !(1 == ~T3_E~0); 44990#L476-3 assume 1 == ~E_1~0;~E_1~0 := 2; 44988#L481-3 assume 1 == ~E_2~0;~E_2~0 := 2; 44984#L486-3 assume !(1 == ~E_3~0); 44980#L491-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 44976#L309-1 assume !(0 == ~m_st~0); 43870#L313-1 assume 0 == ~t1_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 42611#L331-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 42608#L332-1 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 42609#L671 assume 0 == start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 4;assume { :begin_inline_fire_time_events } true;~M_E~0 := 1; 44347#L560 assume { :end_inline_fire_time_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 44346#L197-15 assume 1 == ~m_pc~0; 44343#L198-5 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 44341#L208-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 44340#L209-5 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 42600#L510-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 42547#L510-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 42548#L216-15 assume !(1 == ~t1_pc~0); 43976#L216-17 is_transmit1_triggered_~__retres1~1#1 := 0; 43974#L227-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 43972#L228-5 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 43970#L518-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 43968#L518-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 43965#L235-15 assume 1 == ~t2_pc~0; 43928#L236-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 43926#L246-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 43923#L247-5 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 43921#L526-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 43919#L526-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 43917#L254-15 assume !(1 == ~t3_pc~0); 43915#L254-17 is_transmit3_triggered_~__retres1~3#1 := 0; 43913#L265-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 43911#L266-5 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 43909#L534-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 43907#L534-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_time_events } true; 43903#L567 assume 1 == ~M_E~0;~M_E~0 := 2; 43901#L567-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 43899#L572-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 43897#L577-1 assume !(1 == ~T3_E~0); 43895#L582-1 assume 1 == ~E_1~0;~E_1~0 := 2; 43893#L587-1 assume !(1 == ~E_2~0); 43891#L592-1 assume 1 == ~E_3~0;~E_3~0 := 2; 43862#L597-1 assume { :end_inline_reset_time_events } true; 43860#L671-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 43857#L309-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 43855#L331-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 43853#L332-2 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 43851#L626 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 43848#L633 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 43846#L634 start_simulation_#t~ret15#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 43844#L684 assume !(0 != start_simulation_~tmp___0~1#1); 42281#L652-2 [2021-12-15 17:21:32,630 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:32,631 INFO L85 PathProgramCache]: Analyzing trace with hash 374468594, now seen corresponding path program 4 times [2021-12-15 17:21:32,631 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:32,631 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1883409335] [2021-12-15 17:21:32,631 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:32,631 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:32,640 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:21:32,640 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-15 17:21:32,644 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:21:32,652 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-15 17:21:32,652 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:32,652 INFO L85 PathProgramCache]: Analyzing trace with hash 1354010581, now seen corresponding path program 1 times [2021-12-15 17:21:32,652 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:32,653 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1881259439] [2021-12-15 17:21:32,653 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:32,653 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:32,658 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:32,707 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:32,708 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:32,708 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1881259439] [2021-12-15 17:21:32,708 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1881259439] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:32,708 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:32,708 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:32,708 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [937280018] [2021-12-15 17:21:32,709 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:32,709 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:21:32,709 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:21:32,709 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:21:32,710 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:21:32,710 INFO L87 Difference]: Start difference. First operand 3391 states and 4688 transitions. cyclomatic complexity: 1301 Second operand has 3 states, 3 states have (on average 33.0) internal successors, (99), 3 states have internal predecessors, (99), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:32,751 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:21:32,752 INFO L93 Difference]: Finished difference Result 5895 states and 8092 transitions. [2021-12-15 17:21:32,752 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:21:32,752 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5895 states and 8092 transitions. [2021-12-15 17:21:32,772 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5785 [2021-12-15 17:21:32,796 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5895 states to 5895 states and 8092 transitions. [2021-12-15 17:21:32,797 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5895 [2021-12-15 17:21:32,802 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5895 [2021-12-15 17:21:32,802 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5895 states and 8092 transitions. [2021-12-15 17:21:32,810 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:21:32,810 INFO L681 BuchiCegarLoop]: Abstraction has 5895 states and 8092 transitions. [2021-12-15 17:21:32,813 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5895 states and 8092 transitions. [2021-12-15 17:21:32,875 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5895 to 5875. [2021-12-15 17:21:32,895 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5875 states, 5875 states have (on average 1.3739574468085107) internal successors, (8072), 5874 states have internal predecessors, (8072), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:32,909 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5875 states to 5875 states and 8072 transitions. [2021-12-15 17:21:32,909 INFO L704 BuchiCegarLoop]: Abstraction has 5875 states and 8072 transitions. [2021-12-15 17:21:32,909 INFO L587 BuchiCegarLoop]: Abstraction has 5875 states and 8072 transitions. [2021-12-15 17:21:32,909 INFO L425 BuchiCegarLoop]: ======== Iteration 16============ [2021-12-15 17:21:32,909 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5875 states and 8072 transitions. [2021-12-15 17:21:32,934 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5765 [2021-12-15 17:21:32,935 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:21:32,935 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:21:32,937 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:32,937 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:32,937 INFO L791 eck$LassoCheckResult]: Stem: 51799#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 51738#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 51705#L615 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 51651#L274 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 51652#L281 assume 1 == ~m_i~0;~m_st~0 := 0; 51715#L281-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 51530#L286-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 51531#L291-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 51754#L296-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 51498#L418 assume !(0 == ~M_E~0); 51499#L418-2 assume !(0 == ~T1_E~0); 51714#L423-1 assume !(0 == ~T2_E~0); 51761#L428-1 assume !(0 == ~T3_E~0); 51759#L433-1 assume !(0 == ~E_1~0); 51742#L438-1 assume !(0 == ~E_2~0); 51670#L443-1 assume !(0 == ~E_3~0); 51663#L448-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 51620#L197 assume !(1 == ~m_pc~0); 51621#L197-2 is_master_triggered_~__retres1~0#1 := 0; 51787#L208 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 51790#L209 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 51772#L510 assume !(0 != activate_threads_~tmp~1#1); 51478#L510-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 51479#L216 assume !(1 == ~t1_pc~0); 51528#L216-2 is_transmit1_triggered_~__retres1~1#1 := 0; 51529#L227 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 51648#L228 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 51480#L518 assume !(0 != activate_threads_~tmp___0~0#1); 51481#L518-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 51676#L235 assume !(1 == ~t2_pc~0); 51751#L235-2 is_transmit2_triggered_~__retres1~2#1 := 0; 51610#L246 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 51611#L247 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 51672#L526 assume !(0 != activate_threads_~tmp___1~0#1); 51778#L526-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 51600#L254 assume !(1 == ~t3_pc~0); 51535#L254-2 is_transmit3_triggered_~__retres1~3#1 := 0; 51536#L265 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 51490#L266 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 51491#L534 assume !(0 != activate_threads_~tmp___2~0#1); 51603#L534-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 51470#L461 assume !(1 == ~M_E~0); 51471#L461-2 assume !(1 == ~T1_E~0); 51532#L466-1 assume !(1 == ~T2_E~0); 51765#L471-1 assume !(1 == ~T3_E~0); 51556#L476-1 assume !(1 == ~E_1~0); 51557#L481-1 assume !(1 == ~E_2~0); 51692#L486-1 assume !(1 == ~E_3~0); 51572#L491-1 assume { :end_inline_reset_delta_events } true; 51573#L652-2 [2021-12-15 17:21:32,939 INFO L793 eck$LassoCheckResult]: Loop: 51573#L652-2 assume !false; 53213#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 53212#L393 assume !false; 53211#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 53209#L309 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 53208#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 53207#L332 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 53206#L346 assume 0 != eval_~tmp~0#1; 53204#L346-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 53202#L354 assume 0 != eval_~tmp_ndt_1~0#1;~m_st~0 := 1;assume { :begin_inline_master } true; 53200#L53 assume 0 == ~m_pc~0; 53173#L80 assume !false; 53199#L65 ~E_1~0 := 1;assume { :begin_inline_immediate_notify } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 53198#L197-3 assume !(1 == ~m_pc~0); 53197#L197-5 is_master_triggered_~__retres1~0#1 := 0; 53196#L208-1 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 53195#L209-1 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 53194#L510-3 assume !(0 != activate_threads_~tmp~1#1); 53193#L510-5 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 53192#L216-3 assume !(1 == ~t1_pc~0); 53191#L216-5 is_transmit1_triggered_~__retres1~1#1 := 0; 53190#L227-1 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 53189#L228-1 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 53188#L518-3 assume !(0 != activate_threads_~tmp___0~0#1); 53187#L518-5 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 53186#L235-3 assume 1 == ~t2_pc~0; 53184#L236-1 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 53183#L246-1 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 53182#L247-1 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 53181#L526-3 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 53180#L526-5 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 53179#L254-3 assume !(1 == ~t3_pc~0); 53178#L254-5 is_transmit3_triggered_~__retres1~3#1 := 0; 53177#L265-1 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 53176#L266-1 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 53175#L534-3 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 53174#L534-5 assume { :end_inline_activate_threads } true; 53171#L551 assume { :end_inline_immediate_notify } true;~E_1~0 := 2; 53170#L57 assume !false; 53086#L73 ~m_pc~0 := 1;~m_st~0 := 2; 53078#L83 assume { :end_inline_master } true; 52990#L351 assume !(0 == ~t1_st~0); 53074#L365 assume !(0 == ~t2_st~0); 52978#L379 assume !(0 == ~t3_st~0); 52977#L393 assume !false; 53002#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 52587#L309 assume !(0 == ~m_st~0); 52584#L313 assume !(0 == ~t1_st~0); 52581#L317 assume !(0 == ~t2_st~0); 52576#L321 assume !(0 == ~t3_st~0);exists_runnable_thread_~__retres1~4#1 := 0; 52573#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 52570#L332 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 52566#L346 assume !(0 != eval_~tmp~0#1); 52562#L408 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 52559#L274-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 52556#L418-3 assume !(0 == ~M_E~0); 52553#L418-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 52549#L423-3 assume !(0 == ~T2_E~0); 52546#L428-3 assume !(0 == ~T3_E~0); 52543#L433-3 assume 0 == ~E_1~0;~E_1~0 := 1; 52539#L438-3 assume !(0 == ~E_2~0); 52537#L443-3 assume !(0 == ~E_3~0); 52534#L448-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 52531#L197-12 assume 1 == ~m_pc~0; 52529#L198-4 assume !(1 == ~M_E~0); 52528#L197-14 is_master_triggered_~__retres1~0#1 := 0; 52527#L208-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 52525#L209-4 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 52523#L510-12 assume !(0 != activate_threads_~tmp~1#1); 52521#L510-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 52520#L216-12 assume !(1 == ~t1_pc~0); 52518#L216-14 is_transmit1_triggered_~__retres1~1#1 := 0; 52515#L227-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 52512#L228-4 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 52509#L518-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 52507#L518-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 52504#L235-12 assume !(1 == ~t2_pc~0); 52500#L235-14 is_transmit2_triggered_~__retres1~2#1 := 0; 52496#L246-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 52493#L247-4 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 52490#L526-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 52487#L526-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 52484#L254-12 assume !(1 == ~t3_pc~0); 52480#L254-14 is_transmit3_triggered_~__retres1~3#1 := 0; 52477#L265-4 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 52473#L266-4 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 52469#L534-12 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 52465#L534-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 52462#L461-3 assume !(1 == ~M_E~0); 52457#L461-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 52453#L466-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 52449#L471-3 assume !(1 == ~T3_E~0); 52445#L476-3 assume 1 == ~E_1~0;~E_1~0 := 2; 52441#L481-3 assume 1 == ~E_2~0;~E_2~0 := 2; 52436#L486-3 assume !(1 == ~E_3~0); 52432#L491-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 52427#L309-1 assume !(0 == ~m_st~0); 52345#L313-1 assume 0 == ~t1_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 52417#L331-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 52413#L332-1 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 52333#L671 assume 0 == start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 4;assume { :begin_inline_fire_time_events } true;~M_E~0 := 1; 52331#L560 assume { :end_inline_fire_time_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 52326#L197-15 assume 1 == ~m_pc~0; 52321#L198-5 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 52317#L208-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 52313#L209-5 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 52308#L510-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 52306#L510-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 52304#L216-15 assume !(1 == ~t1_pc~0); 52302#L216-17 is_transmit1_triggered_~__retres1~1#1 := 0; 52300#L227-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 52295#L228-5 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 52292#L518-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 52288#L518-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 52285#L235-15 assume 1 == ~t2_pc~0; 52278#L236-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 52272#L246-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 52267#L247-5 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 52262#L526-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 52256#L526-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 52253#L254-15 assume !(1 == ~t3_pc~0); 52250#L254-17 is_transmit3_triggered_~__retres1~3#1 := 0; 52246#L265-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 52243#L266-5 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 52240#L534-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 52237#L534-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_time_events } true; 52233#L567 assume !(1 == ~M_E~0); 52230#L567-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 52226#L572-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 52223#L577-1 assume !(1 == ~T3_E~0); 52219#L582-1 assume 1 == ~E_1~0;~E_1~0 := 2; 52216#L587-1 assume !(1 == ~E_2~0); 52213#L592-1 assume 1 == ~E_3~0;~E_3~0 := 2; 52209#L597-1 assume { :end_inline_reset_time_events } true; 52207#L671-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 52204#L309-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 52202#L331-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 52200#L332-2 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 52198#L626 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 52194#L633 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 52192#L634 start_simulation_#t~ret15#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 52190#L684 assume !(0 != start_simulation_~tmp___0~1#1); 52186#L652-2 assume !false; 52181#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 52179#L393 assume !false; 52177#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 52175#L309 assume !(0 == ~m_st~0); 52176#L313 assume !(0 == ~t1_st~0); 52374#L317 assume !(0 == ~t2_st~0); 52371#L321 assume !(0 == ~t3_st~0);exists_runnable_thread_~__retres1~4#1 := 0; 52369#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 52367#L332 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 52364#L346 assume !(0 != eval_~tmp~0#1); 52362#L408 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 52360#L274-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 52359#L418-3 assume 0 == ~M_E~0;~M_E~0 := 1; 52358#L418-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 52356#L423-3 assume !(0 == ~T2_E~0); 52354#L428-3 assume !(0 == ~T3_E~0); 52352#L433-3 assume 0 == ~E_1~0;~E_1~0 := 1; 52350#L438-3 assume !(0 == ~E_2~0); 52348#L443-3 assume !(0 == ~E_3~0); 52346#L448-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 52342#L197-12 assume 1 == ~m_pc~0; 52339#L198-4 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 52337#L208-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 52332#L209-4 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 52329#L510-12 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 52325#L510-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 52320#L216-12 assume !(1 == ~t1_pc~0); 52316#L216-14 is_transmit1_triggered_~__retres1~1#1 := 0; 52312#L227-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 52307#L228-4 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 52305#L518-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 52303#L518-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 52301#L235-12 assume !(1 == ~t2_pc~0); 52296#L235-14 is_transmit2_triggered_~__retres1~2#1 := 0; 52293#L246-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 52289#L247-4 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 52286#L526-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 52280#L526-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 52273#L254-12 assume !(1 == ~t3_pc~0); 52268#L254-14 is_transmit3_triggered_~__retres1~3#1 := 0; 52263#L265-4 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 52257#L266-4 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 52254#L534-12 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 52251#L534-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 52247#L461-3 assume !(1 == ~M_E~0); 52244#L461-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 52241#L466-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 52238#L471-3 assume !(1 == ~T3_E~0); 52235#L476-3 assume 1 == ~E_1~0;~E_1~0 := 2; 52231#L481-3 assume 1 == ~E_2~0;~E_2~0 := 2; 52227#L486-3 assume !(1 == ~E_3~0); 52224#L491-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 52220#L309-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 52217#L331-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 52214#L332-1 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 52210#L671 assume 0 == start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 4;assume { :begin_inline_fire_time_events } true;~M_E~0 := 1; 52211#L560 assume { :end_inline_fire_time_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 52327#L197-15 assume !(1 == ~m_pc~0); 52328#L197-17 is_master_triggered_~__retres1~0#1 := 0; 53290#L208-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 53289#L209-5 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 53288#L510-15 assume !(0 != activate_threads_~tmp~1#1); 53287#L510-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 53285#L216-15 assume !(1 == ~t1_pc~0); 53284#L216-17 is_transmit1_triggered_~__retres1~1#1 := 0; 53282#L227-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 53280#L228-5 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 53278#L518-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 53276#L518-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 53274#L235-15 assume 1 == ~t2_pc~0; 53271#L236-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 53269#L246-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 53267#L247-5 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 53265#L526-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 53263#L526-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 53261#L254-15 assume !(1 == ~t3_pc~0); 53258#L254-17 is_transmit3_triggered_~__retres1~3#1 := 0; 53256#L265-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 53254#L266-5 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 53252#L534-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 53250#L534-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_time_events } true; 53247#L567 assume 1 == ~M_E~0;~M_E~0 := 2; 53245#L567-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 53243#L572-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 53241#L577-1 assume !(1 == ~T3_E~0); 53239#L582-1 assume 1 == ~E_1~0;~E_1~0 := 2; 53237#L587-1 assume !(1 == ~E_2~0); 53236#L592-1 assume 1 == ~E_3~0;~E_3~0 := 2; 53235#L597-1 assume { :end_inline_reset_time_events } true; 53234#L671-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 53230#L309-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 53228#L331-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 53226#L332-2 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 53225#L626 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 53224#L633 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 53223#L634 start_simulation_#t~ret15#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 53220#L684 assume !(0 != start_simulation_~tmp___0~1#1); 51573#L652-2 [2021-12-15 17:21:32,939 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:32,940 INFO L85 PathProgramCache]: Analyzing trace with hash 374468594, now seen corresponding path program 5 times [2021-12-15 17:21:32,940 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:32,940 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [142341793] [2021-12-15 17:21:32,940 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:32,940 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:32,948 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:21:32,948 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-15 17:21:32,952 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:21:32,958 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-15 17:21:32,958 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:32,958 INFO L85 PathProgramCache]: Analyzing trace with hash -240659673, now seen corresponding path program 1 times [2021-12-15 17:21:32,959 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:32,959 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2073112903] [2021-12-15 17:21:32,959 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:32,959 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:32,967 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:32,999 INFO L134 CoverageAnalysis]: Checked inductivity of 109 backedges. 14 proven. 0 refuted. 0 times theorem prover too weak. 95 trivial. 0 not checked. [2021-12-15 17:21:32,999 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:32,999 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2073112903] [2021-12-15 17:21:33,000 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2073112903] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:33,000 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:33,000 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-15 17:21:33,000 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1856180549] [2021-12-15 17:21:33,000 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:33,001 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:21:33,001 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:21:33,001 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-15 17:21:33,001 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-15 17:21:33,002 INFO L87 Difference]: Start difference. First operand 5875 states and 8072 transitions. cyclomatic complexity: 2205 Second operand has 5 states, 5 states have (on average 30.4) internal successors, (152), 5 states have internal predecessors, (152), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:33,104 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:21:33,105 INFO L93 Difference]: Finished difference Result 10168 states and 13845 transitions. [2021-12-15 17:21:33,105 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-15 17:21:33,106 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 10168 states and 13845 transitions. [2021-12-15 17:21:33,149 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 10018 [2021-12-15 17:21:33,231 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 10168 states to 10168 states and 13845 transitions. [2021-12-15 17:21:33,231 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10168 [2021-12-15 17:21:33,238 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10168 [2021-12-15 17:21:33,238 INFO L73 IsDeterministic]: Start isDeterministic. Operand 10168 states and 13845 transitions. [2021-12-15 17:21:33,248 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:21:33,248 INFO L681 BuchiCegarLoop]: Abstraction has 10168 states and 13845 transitions. [2021-12-15 17:21:33,253 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10168 states and 13845 transitions. [2021-12-15 17:21:33,337 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10168 to 5983. [2021-12-15 17:21:33,346 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5983 states, 5983 states have (on average 1.3543372889854588) internal successors, (8103), 5982 states have internal predecessors, (8103), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:33,358 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5983 states to 5983 states and 8103 transitions. [2021-12-15 17:21:33,359 INFO L704 BuchiCegarLoop]: Abstraction has 5983 states and 8103 transitions. [2021-12-15 17:21:33,359 INFO L587 BuchiCegarLoop]: Abstraction has 5983 states and 8103 transitions. [2021-12-15 17:21:33,359 INFO L425 BuchiCegarLoop]: ======== Iteration 17============ [2021-12-15 17:21:33,359 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5983 states and 8103 transitions. [2021-12-15 17:21:33,376 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5867 [2021-12-15 17:21:33,376 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:21:33,376 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:21:33,378 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:33,378 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:33,379 INFO L791 eck$LassoCheckResult]: Stem: 67894#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 67812#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 67770#L615 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 67714#L274 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 67715#L281 assume 1 == ~m_i~0;~m_st~0 := 0; 67781#L281-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 67586#L286-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 67587#L291-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 67829#L296-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 67551#L418 assume !(0 == ~M_E~0); 67552#L418-2 assume !(0 == ~T1_E~0); 67780#L423-1 assume !(0 == ~T2_E~0); 67836#L428-1 assume !(0 == ~T3_E~0); 67834#L433-1 assume !(0 == ~E_1~0); 67817#L438-1 assume !(0 == ~E_2~0); 67731#L443-1 assume !(0 == ~E_3~0); 67724#L448-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 67683#L197 assume !(1 == ~m_pc~0); 67684#L197-2 is_master_triggered_~__retres1~0#1 := 0; 67877#L208 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 67882#L209 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 67852#L510 assume !(0 != activate_threads_~tmp~1#1); 67535#L510-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 67536#L216 assume !(1 == ~t1_pc~0); 67584#L216-2 is_transmit1_triggered_~__retres1~1#1 := 0; 67585#L227 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 67711#L228 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 67537#L518 assume !(0 != activate_threads_~tmp___0~0#1); 67538#L518-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 67741#L235 assume !(1 == ~t2_pc~0); 67824#L235-2 is_transmit2_triggered_~__retres1~2#1 := 0; 67671#L246 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 67672#L247 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 67733#L526 assume !(0 != activate_threads_~tmp___1~0#1); 67865#L526-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 67660#L254 assume !(1 == ~t3_pc~0); 67591#L254-2 is_transmit3_triggered_~__retres1~3#1 := 0; 67592#L265 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 67547#L266 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 67548#L534 assume !(0 != activate_threads_~tmp___2~0#1); 67663#L534-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 67527#L461 assume !(1 == ~M_E~0); 67528#L461-2 assume !(1 == ~T1_E~0); 67588#L466-1 assume !(1 == ~T2_E~0); 67841#L471-1 assume !(1 == ~T3_E~0); 67613#L476-1 assume !(1 == ~E_1~0); 67614#L481-1 assume !(1 == ~E_2~0); 67758#L486-1 assume !(1 == ~E_3~0); 67630#L491-1 assume { :end_inline_reset_delta_events } true; 67631#L652-2 [2021-12-15 17:21:33,379 INFO L793 eck$LassoCheckResult]: Loop: 67631#L652-2 assume !false; 68673#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 68667#L393 assume !false; 68662#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 68656#L309 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 68651#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 68646#L332 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 68641#L346 assume 0 != eval_~tmp~0#1; 68634#L346-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 68626#L354 assume 0 != eval_~tmp_ndt_1~0#1;~m_st~0 := 1;assume { :begin_inline_master } true; 68620#L53 assume 0 == ~m_pc~0; 68059#L80 assume !false; 68060#L65 ~E_1~0 := 1;assume { :begin_inline_immediate_notify } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 68055#L197-3 assume !(1 == ~m_pc~0); 68056#L197-5 is_master_triggered_~__retres1~0#1 := 0; 68505#L208-1 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 68504#L209-1 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 68049#L510-3 assume !(0 != activate_threads_~tmp~1#1); 68050#L510-5 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 68045#L216-3 assume !(1 == ~t1_pc~0); 68046#L216-5 is_transmit1_triggered_~__retres1~1#1 := 0; 68716#L227-1 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 68711#L228-1 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 68704#L518-3 assume !(0 != activate_threads_~tmp___0~0#1); 68699#L518-5 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 68692#L235-3 assume !(1 == ~t2_pc~0); 68685#L235-5 is_transmit2_triggered_~__retres1~2#1 := 0; 68672#L246-1 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 68666#L247-1 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 68661#L526-3 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 68655#L526-5 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 68650#L254-3 assume !(1 == ~t3_pc~0); 68645#L254-5 is_transmit3_triggered_~__retres1~3#1 := 0; 68640#L265-1 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 68633#L266-1 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 68625#L534-3 assume !(0 != activate_threads_~tmp___2~0#1); 68619#L534-5 assume { :end_inline_activate_threads } true; 68612#L551 assume { :end_inline_immediate_notify } true;~E_1~0 := 2; 68603#L57 assume !false; 68602#L73 ~m_pc~0 := 1;~m_st~0 := 2; 68587#L83 assume { :end_inline_master } true; 68579#L351 assume !(0 == ~t1_st~0); 68569#L365 assume !(0 == ~t2_st~0); 68560#L379 assume !(0 == ~t3_st~0); 68555#L393 assume !false; 68553#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 68550#L309 assume !(0 == ~m_st~0); 68549#L313 assume !(0 == ~t1_st~0); 68548#L317 assume !(0 == ~t2_st~0); 68546#L321 assume !(0 == ~t3_st~0);exists_runnable_thread_~__retres1~4#1 := 0; 68545#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 68544#L332 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 68542#L346 assume !(0 != eval_~tmp~0#1); 68541#L408 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 68540#L274-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 68539#L418-3 assume !(0 == ~M_E~0); 68538#L418-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 68537#L423-3 assume !(0 == ~T2_E~0); 68536#L428-3 assume !(0 == ~T3_E~0); 68535#L433-3 assume 0 == ~E_1~0;~E_1~0 := 1; 68534#L438-3 assume !(0 == ~E_2~0); 68533#L443-3 assume !(0 == ~E_3~0); 68532#L448-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 68530#L197-12 assume 1 == ~m_pc~0; 68529#L198-4 assume !(1 == ~M_E~0); 68528#L197-14 is_master_triggered_~__retres1~0#1 := 0; 68527#L208-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 68526#L209-4 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 68525#L510-12 assume !(0 != activate_threads_~tmp~1#1); 68524#L510-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 68523#L216-12 assume !(1 == ~t1_pc~0); 68519#L216-14 is_transmit1_triggered_~__retres1~1#1 := 0; 68518#L227-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 68513#L228-4 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 68508#L518-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 68507#L518-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 68506#L235-12 assume 1 == ~t2_pc~0; 68499#L236-4 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 68494#L246-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 68491#L247-4 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 68489#L526-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 68486#L526-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 68483#L254-12 assume !(1 == ~t3_pc~0); 68480#L254-14 is_transmit3_triggered_~__retres1~3#1 := 0; 68477#L265-4 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 68474#L266-4 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 68471#L534-12 assume !(0 != activate_threads_~tmp___2~0#1); 68467#L534-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 68463#L461-3 assume !(1 == ~M_E~0); 68349#L461-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 68458#L466-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 68455#L471-3 assume !(1 == ~T3_E~0); 68452#L476-3 assume 1 == ~E_1~0;~E_1~0 := 2; 68448#L481-3 assume 1 == ~E_2~0;~E_2~0 := 2; 68444#L486-3 assume !(1 == ~E_3~0); 68440#L491-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 68437#L309-1 assume !(0 == ~m_st~0); 68290#L313-1 assume 0 == ~t1_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 68406#L331-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 68394#L332-1 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 68392#L671 assume 0 == start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 4;assume { :begin_inline_fire_time_events } true;~M_E~0 := 1; 68279#L560 assume { :end_inline_fire_time_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 68388#L197-15 assume 1 == ~m_pc~0; 68384#L198-5 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 68382#L208-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 68380#L209-5 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 68366#L510-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 68363#L510-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 68359#L216-15 assume !(1 == ~t1_pc~0); 68356#L216-17 is_transmit1_triggered_~__retres1~1#1 := 0; 68353#L227-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 68350#L228-5 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 68346#L518-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 68343#L518-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 68340#L235-15 assume !(1 == ~t2_pc~0); 68337#L235-17 is_transmit2_triggered_~__retres1~2#1 := 0; 68333#L246-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 68330#L247-5 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 68327#L526-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 68323#L526-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 68321#L254-15 assume !(1 == ~t3_pc~0); 68319#L254-17 is_transmit3_triggered_~__retres1~3#1 := 0; 68317#L265-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 68315#L266-5 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 68313#L534-15 assume !(0 != activate_threads_~tmp___2~0#1); 68311#L534-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_time_events } true; 68308#L567 assume !(1 == ~M_E~0); 68306#L567-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 68304#L572-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 68295#L577-1 assume !(1 == ~T3_E~0); 68289#L582-1 assume 1 == ~E_1~0;~E_1~0 := 2; 68285#L587-1 assume !(1 == ~E_2~0); 68281#L592-1 assume 1 == ~E_3~0;~E_3~0 := 2; 68276#L597-1 assume { :end_inline_reset_time_events } true; 68273#L671-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 68269#L309-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 68270#L331-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 68427#L332-2 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 68426#L626 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 68376#L633 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 68250#L634 start_simulation_#t~ret15#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 68248#L684 assume !(0 != start_simulation_~tmp___0~1#1); 68237#L652-2 assume !false; 68228#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 68223#L393 assume !false; 68221#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 68218#L309 assume !(0 == ~m_st~0); 68216#L313 assume !(0 == ~t1_st~0); 68215#L317 assume !(0 == ~t2_st~0); 68213#L321 assume !(0 == ~t3_st~0);exists_runnable_thread_~__retres1~4#1 := 0; 68212#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 68211#L332 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 68209#L346 assume !(0 != eval_~tmp~0#1); 68208#L408 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 68207#L274-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 68206#L418-3 assume 0 == ~M_E~0;~M_E~0 := 1; 68205#L418-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 68204#L423-3 assume !(0 == ~T2_E~0); 68203#L428-3 assume !(0 == ~T3_E~0); 68202#L433-3 assume 0 == ~E_1~0;~E_1~0 := 1; 68201#L438-3 assume !(0 == ~E_2~0); 68200#L443-3 assume !(0 == ~E_3~0); 68199#L448-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 68197#L197-12 assume 1 == ~m_pc~0; 68195#L198-4 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 68194#L208-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 68193#L209-4 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 68191#L510-12 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 68190#L510-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 68189#L216-12 assume !(1 == ~t1_pc~0); 68188#L216-14 is_transmit1_triggered_~__retres1~1#1 := 0; 68187#L227-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 68186#L228-4 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 68185#L518-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 68184#L518-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 68183#L235-12 assume !(1 == ~t2_pc~0); 68181#L235-14 is_transmit2_triggered_~__retres1~2#1 := 0; 68180#L246-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 68179#L247-4 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 68178#L526-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 68177#L526-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 68176#L254-12 assume !(1 == ~t3_pc~0); 68175#L254-14 is_transmit3_triggered_~__retres1~3#1 := 0; 68174#L265-4 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 68173#L266-4 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 68172#L534-12 assume !(0 != activate_threads_~tmp___2~0#1); 68171#L534-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 68169#L461-3 assume 1 == ~M_E~0;~M_E~0 := 2; 68167#L461-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 68168#L466-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 68163#L471-3 assume !(1 == ~T3_E~0); 68164#L476-3 assume 1 == ~E_1~0;~E_1~0 := 2; 68160#L481-3 assume 1 == ~E_2~0;~E_2~0 := 2; 68159#L486-3 assume !(1 == ~E_3~0); 68157#L491-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 68158#L309-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 68152#L331-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 68153#L332-1 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 68147#L671 assume 0 == start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 4;assume { :begin_inline_fire_time_events } true;~M_E~0 := 1; 68149#L560 assume { :end_inline_fire_time_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 68390#L197-15 assume !(1 == ~m_pc~0); 68391#L197-17 is_master_triggered_~__retres1~0#1 := 0; 68792#L208-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 68791#L209-5 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 68790#L510-15 assume !(0 != activate_threads_~tmp~1#1); 68789#L510-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 68788#L216-15 assume !(1 == ~t1_pc~0); 68787#L216-17 is_transmit1_triggered_~__retres1~1#1 := 0; 68786#L227-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 68785#L228-5 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 68784#L518-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 68783#L518-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 68782#L235-15 assume 1 == ~t2_pc~0; 68779#L236-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 68778#L246-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 68776#L247-5 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 68774#L526-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 68772#L526-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 68770#L254-15 assume !(1 == ~t3_pc~0); 68768#L254-17 is_transmit3_triggered_~__retres1~3#1 := 0; 68766#L265-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 68764#L266-5 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 68762#L534-15 assume !(0 != activate_threads_~tmp___2~0#1); 68760#L534-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_time_events } true; 68757#L567 assume 1 == ~M_E~0;~M_E~0 := 2; 68755#L567-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 68752#L572-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 68750#L577-1 assume !(1 == ~T3_E~0); 68746#L582-1 assume 1 == ~E_1~0;~E_1~0 := 2; 68743#L587-1 assume !(1 == ~E_2~0); 68738#L592-1 assume 1 == ~E_3~0;~E_3~0 := 2; 68734#L597-1 assume { :end_inline_reset_time_events } true; 68730#L671-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 68725#L309-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 68721#L331-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 68717#L332-2 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 68712#L626 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 68705#L633 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 68700#L634 start_simulation_#t~ret15#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 68693#L684 assume !(0 != start_simulation_~tmp___0~1#1); 67631#L652-2 [2021-12-15 17:21:33,380 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:33,380 INFO L85 PathProgramCache]: Analyzing trace with hash 374468594, now seen corresponding path program 6 times [2021-12-15 17:21:33,381 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:33,381 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1247638315] [2021-12-15 17:21:33,382 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:33,382 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:33,387 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:21:33,387 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-15 17:21:33,394 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:21:33,403 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-15 17:21:33,405 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:33,405 INFO L85 PathProgramCache]: Analyzing trace with hash 1071447716, now seen corresponding path program 1 times [2021-12-15 17:21:33,405 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:33,405 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1821773059] [2021-12-15 17:21:33,405 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:33,406 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:33,414 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:33,448 INFO L134 CoverageAnalysis]: Checked inductivity of 107 backedges. 14 proven. 0 refuted. 0 times theorem prover too weak. 93 trivial. 0 not checked. [2021-12-15 17:21:33,448 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:33,448 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1821773059] [2021-12-15 17:21:33,448 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1821773059] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:33,449 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:33,449 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-15 17:21:33,449 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1436354411] [2021-12-15 17:21:33,449 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:33,450 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:21:33,450 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:21:33,450 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-15 17:21:33,450 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-15 17:21:33,451 INFO L87 Difference]: Start difference. First operand 5983 states and 8103 transitions. cyclomatic complexity: 2128 Second operand has 5 states, 5 states have (on average 31.4) internal successors, (157), 5 states have internal predecessors, (157), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:33,628 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:21:33,628 INFO L93 Difference]: Finished difference Result 15365 states and 20683 transitions. [2021-12-15 17:21:33,629 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-15 17:21:33,629 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 15365 states and 20683 transitions. [2021-12-15 17:21:33,687 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 15124 [2021-12-15 17:21:33,734 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 15365 states to 15365 states and 20683 transitions. [2021-12-15 17:21:33,735 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 15365 [2021-12-15 17:21:33,741 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 15365 [2021-12-15 17:21:33,741 INFO L73 IsDeterministic]: Start isDeterministic. Operand 15365 states and 20683 transitions. [2021-12-15 17:21:33,753 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:21:33,753 INFO L681 BuchiCegarLoop]: Abstraction has 15365 states and 20683 transitions. [2021-12-15 17:21:33,760 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15365 states and 20683 transitions. [2021-12-15 17:21:33,840 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15365 to 6322. [2021-12-15 17:21:33,846 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6322 states, 6322 states have (on average 1.335336918696615) internal successors, (8442), 6321 states have internal predecessors, (8442), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:33,912 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6322 states to 6322 states and 8442 transitions. [2021-12-15 17:21:33,913 INFO L704 BuchiCegarLoop]: Abstraction has 6322 states and 8442 transitions. [2021-12-15 17:21:33,913 INFO L587 BuchiCegarLoop]: Abstraction has 6322 states and 8442 transitions. [2021-12-15 17:21:33,913 INFO L425 BuchiCegarLoop]: ======== Iteration 18============ [2021-12-15 17:21:33,913 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6322 states and 8442 transitions. [2021-12-15 17:21:33,925 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 6197 [2021-12-15 17:21:33,937 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:21:33,937 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:21:33,939 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:33,939 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:33,940 INFO L791 eck$LassoCheckResult]: Stem: 89248#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 89172#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 89133#L615 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 89080#L274 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 89081#L281 assume 1 == ~m_i~0;~m_st~0 := 0; 89144#L281-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 88949#L286-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 88950#L291-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 89187#L296-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 88913#L418 assume !(0 == ~M_E~0); 88914#L418-2 assume !(0 == ~T1_E~0); 89143#L423-1 assume !(0 == ~T2_E~0); 89194#L428-1 assume !(0 == ~T3_E~0); 89191#L433-1 assume !(0 == ~E_1~0); 89176#L438-1 assume !(0 == ~E_2~0); 89098#L443-1 assume !(0 == ~E_3~0); 89092#L448-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 89051#L197 assume !(1 == ~m_pc~0); 89052#L197-2 is_master_triggered_~__retres1~0#1 := 0; 89228#L208 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 89229#L209 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 89209#L510 assume !(0 != activate_threads_~tmp~1#1); 88897#L510-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 88898#L216 assume !(1 == ~t1_pc~0); 88945#L216-2 is_transmit1_triggered_~__retres1~1#1 := 0; 88946#L227 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 89077#L228 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 88899#L518 assume !(0 != activate_threads_~tmp___0~0#1); 88900#L518-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 89106#L235 assume !(1 == ~t2_pc~0); 89184#L235-2 is_transmit2_triggered_~__retres1~2#1 := 0; 89035#L246 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 89036#L247 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 89215#L526 assume !(0 != activate_threads_~tmp___1~0#1); 89216#L526-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 89022#L254 assume !(1 == ~t3_pc~0); 88954#L254-2 is_transmit3_triggered_~__retres1~3#1 := 0; 88955#L265 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 88909#L266 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 88910#L534 assume !(0 != activate_threads_~tmp___2~0#1); 89029#L534-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 88889#L461 assume !(1 == ~M_E~0); 88890#L461-2 assume !(1 == ~T1_E~0); 88951#L466-1 assume !(1 == ~T2_E~0); 89200#L471-1 assume !(1 == ~T3_E~0); 88976#L476-1 assume !(1 == ~E_1~0); 88977#L481-1 assume !(1 == ~E_2~0); 89122#L486-1 assume !(1 == ~E_3~0); 88991#L491-1 assume { :end_inline_reset_delta_events } true; 88992#L652-2 [2021-12-15 17:21:33,940 INFO L793 eck$LassoCheckResult]: Loop: 88992#L652-2 assume !false; 92929#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 92924#L393 assume !false; 92917#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 92914#L309 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 92915#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 92907#L332 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 92908#L346 assume 0 != eval_~tmp~0#1; 92900#L346-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 92901#L354 assume 0 != eval_~tmp_ndt_1~0#1;~m_st~0 := 1;assume { :begin_inline_master } true; 92451#L53 assume 0 == ~m_pc~0; 92447#L80 assume !false; 89256#L65 ~E_1~0 := 1;assume { :begin_inline_immediate_notify } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 89257#L197-3 assume !(1 == ~m_pc~0); 92432#L197-5 is_master_triggered_~__retres1~0#1 := 0; 92428#L208-1 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 92425#L209-1 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 92422#L510-3 assume !(0 != activate_threads_~tmp~1#1); 92419#L510-5 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 88923#L216-3 assume !(1 == ~t1_pc~0); 88924#L216-5 is_transmit1_triggered_~__retres1~1#1 := 0; 93002#L227-1 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 93001#L228-1 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 93000#L518-3 assume !(0 != activate_threads_~tmp___0~0#1); 92999#L518-5 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 92998#L235-3 assume !(1 == ~t2_pc~0); 92997#L235-5 is_transmit2_triggered_~__retres1~2#1 := 0; 92995#L246-1 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 92993#L247-1 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 92991#L526-3 assume !(0 != activate_threads_~tmp___1~0#1); 92989#L526-5 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 92987#L254-3 assume !(1 == ~t3_pc~0); 92985#L254-5 is_transmit3_triggered_~__retres1~3#1 := 0; 92983#L265-1 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 92981#L266-1 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 92978#L534-3 assume !(0 != activate_threads_~tmp___2~0#1); 92976#L534-5 assume { :end_inline_activate_threads } true; 92971#L551 assume { :end_inline_immediate_notify } true;~E_1~0 := 2; 92968#L57 assume !false; 92965#L73 ~m_pc~0 := 1;~m_st~0 := 2; 92963#L83 assume { :end_inline_master } true; 92936#L351 assume !(0 == ~t1_st~0); 92928#L365 assume !(0 == ~t2_st~0); 92923#L379 assume !(0 == ~t3_st~0); 92919#L393 assume !false; 92744#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 92693#L309 assume !(0 == ~m_st~0); 92691#L313 assume !(0 == ~t1_st~0); 92689#L317 assume !(0 == ~t2_st~0); 92686#L321 assume !(0 == ~t3_st~0);exists_runnable_thread_~__retres1~4#1 := 0; 92685#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 92683#L332 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 92680#L346 assume !(0 != eval_~tmp~0#1); 92678#L408 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 92676#L274-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 92674#L418-3 assume !(0 == ~M_E~0); 92672#L418-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 92669#L423-3 assume !(0 == ~T2_E~0); 92665#L428-3 assume !(0 == ~T3_E~0); 92662#L433-3 assume 0 == ~E_1~0;~E_1~0 := 1; 92659#L438-3 assume !(0 == ~E_2~0); 92636#L443-3 assume !(0 == ~E_3~0); 92633#L448-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 92632#L197-12 assume 1 == ~m_pc~0; 92631#L198-4 assume !(1 == ~M_E~0); 92630#L197-14 is_master_triggered_~__retres1~0#1 := 0; 92629#L208-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 92628#L209-4 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 92627#L510-12 assume !(0 != activate_threads_~tmp~1#1); 92626#L510-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 92625#L216-12 assume !(1 == ~t1_pc~0); 92624#L216-14 is_transmit1_triggered_~__retres1~1#1 := 0; 92623#L227-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 92622#L228-4 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 92621#L518-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 92620#L518-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 92619#L235-12 assume 1 == ~t2_pc~0; 92617#L236-4 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 92615#L246-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 92613#L247-4 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 92611#L526-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 92606#L526-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 92603#L254-12 assume !(1 == ~t3_pc~0); 92599#L254-14 is_transmit3_triggered_~__retres1~3#1 := 0; 92596#L265-4 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 92573#L266-4 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 92546#L534-12 assume !(0 != activate_threads_~tmp___2~0#1); 92539#L534-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 92532#L461-3 assume !(1 == ~M_E~0); 92309#L461-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 92525#L466-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 92521#L471-3 assume !(1 == ~T3_E~0); 92501#L476-3 assume 1 == ~E_1~0;~E_1~0 := 2; 92495#L481-3 assume 1 == ~E_2~0;~E_2~0 := 2; 92491#L486-3 assume !(1 == ~E_3~0); 92487#L491-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 92486#L309-1 assume !(0 == ~m_st~0); 92128#L313-1 assume 0 == ~t1_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 92449#L331-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 92445#L332-1 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 92435#L671 assume 0 == start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 4;assume { :begin_inline_fire_time_events } true;~M_E~0 := 1; 89278#L560 assume { :end_inline_fire_time_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 89279#L197-15 assume 1 == ~m_pc~0; 89119#L198-5 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 89120#L208-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 92171#L209-5 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 92093#L510-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 92092#L510-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 92091#L216-15 assume !(1 == ~t1_pc~0); 92090#L216-17 is_transmit1_triggered_~__retres1~1#1 := 0; 92089#L227-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 92088#L228-5 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 92087#L518-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 92086#L518-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 92085#L235-15 assume 1 == ~t2_pc~0; 92083#L236-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 92081#L246-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 92079#L247-5 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 92077#L526-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 92074#L526-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 92070#L254-15 assume !(1 == ~t3_pc~0); 92065#L254-17 is_transmit3_triggered_~__retres1~3#1 := 0; 92062#L265-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 92058#L266-5 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 92053#L534-15 assume !(0 != activate_threads_~tmp___2~0#1); 92049#L534-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_time_events } true; 92044#L567 assume !(1 == ~M_E~0); 92041#L567-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 92037#L572-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 92033#L577-1 assume !(1 == ~T3_E~0); 92030#L582-1 assume 1 == ~E_1~0;~E_1~0 := 2; 92002#L587-1 assume !(1 == ~E_2~0); 91713#L592-1 assume 1 == ~E_3~0;~E_3~0 := 2; 91238#L597-1 assume { :end_inline_reset_time_events } true; 91236#L671-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 91233#L309-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 91231#L331-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 91229#L332-2 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 91227#L626 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 91225#L633 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 91224#L634 start_simulation_#t~ret15#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 91223#L684 assume !(0 != start_simulation_~tmp___0~1#1); 91219#L652-2 assume !false; 91208#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 91206#L393 assume !false; 91204#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 91201#L309 assume !(0 == ~m_st~0); 91202#L313 assume !(0 == ~t1_st~0); 92003#L317 assume !(0 == ~t2_st~0); 91997#L321 assume !(0 == ~t3_st~0);exists_runnable_thread_~__retres1~4#1 := 0; 91933#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 91927#L332 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 91920#L346 assume !(0 != eval_~tmp~0#1); 91913#L408 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 91906#L274-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 91880#L418-3 assume 0 == ~M_E~0;~M_E~0 := 1; 91873#L418-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 91864#L423-3 assume !(0 == ~T2_E~0); 91857#L428-3 assume !(0 == ~T3_E~0); 91850#L433-3 assume 0 == ~E_1~0;~E_1~0 := 1; 91842#L438-3 assume !(0 == ~E_2~0); 91835#L443-3 assume !(0 == ~E_3~0); 91828#L448-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 91826#L197-12 assume 1 == ~m_pc~0; 91824#L198-4 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 91823#L208-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 91822#L209-4 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 91820#L510-12 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 91819#L510-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 91818#L216-12 assume !(1 == ~t1_pc~0); 91817#L216-14 is_transmit1_triggered_~__retres1~1#1 := 0; 91816#L227-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 91815#L228-4 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 91814#L518-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 91813#L518-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 91812#L235-12 assume !(1 == ~t2_pc~0); 91811#L235-14 is_transmit2_triggered_~__retres1~2#1 := 0; 91809#L246-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 91807#L247-4 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 91805#L526-12 assume !(0 != activate_threads_~tmp___1~0#1); 91795#L526-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 91788#L254-12 assume !(1 == ~t3_pc~0); 91783#L254-14 is_transmit3_triggered_~__retres1~3#1 := 0; 91782#L265-4 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 91781#L266-4 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 91779#L534-12 assume !(0 != activate_threads_~tmp___2~0#1); 91777#L534-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 91774#L461-3 assume !(1 == ~M_E~0); 91773#L461-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 91772#L466-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 91703#L471-3 assume !(1 == ~T3_E~0); 91674#L476-3 assume 1 == ~E_1~0;~E_1~0 := 2; 91670#L481-3 assume 1 == ~E_2~0;~E_2~0 := 2; 91666#L486-3 assume !(1 == ~E_3~0); 91659#L491-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 91652#L309-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 91649#L331-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 91242#L332-1 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 91239#L671 assume 0 == start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 4;assume { :begin_inline_fire_time_events } true;~M_E~0 := 1; 91240#L560 assume { :end_inline_fire_time_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 92102#L197-15 assume !(1 == ~m_pc~0); 92103#L197-17 is_master_triggered_~__retres1~0#1 := 0; 92520#L208-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 92519#L209-5 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 92518#L510-15 assume !(0 != activate_threads_~tmp~1#1); 92517#L510-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 92516#L216-15 assume !(1 == ~t1_pc~0); 92515#L216-17 is_transmit1_triggered_~__retres1~1#1 := 0; 92514#L227-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 92513#L228-5 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 92512#L518-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 92511#L518-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 92510#L235-15 assume !(1 == ~t2_pc~0); 92509#L235-17 is_transmit2_triggered_~__retres1~2#1 := 0; 92507#L246-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 92505#L247-5 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 92503#L526-15 assume !(0 != activate_threads_~tmp___1~0#1); 92496#L526-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 92492#L254-15 assume !(1 == ~t3_pc~0); 92488#L254-17 is_transmit3_triggered_~__retres1~3#1 := 0; 92457#L265-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 92450#L266-5 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 92446#L534-15 assume !(0 != activate_threads_~tmp___2~0#1); 92437#L534-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_time_events } true; 92397#L567 assume 1 == ~M_E~0;~M_E~0 := 2; 92398#L567-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 93059#L572-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 93057#L577-1 assume !(1 == ~T3_E~0); 93055#L582-1 assume 1 == ~E_1~0;~E_1~0 := 2; 93053#L587-1 assume !(1 == ~E_2~0); 93051#L592-1 assume 1 == ~E_3~0;~E_3~0 := 2; 93049#L597-1 assume { :end_inline_reset_time_events } true; 93047#L671-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 93044#L309-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 93040#L331-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 93038#L332-2 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 93036#L626 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 93033#L633 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 93031#L634 start_simulation_#t~ret15#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 93019#L684 assume !(0 != start_simulation_~tmp___0~1#1); 88992#L652-2 [2021-12-15 17:21:33,941 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:33,941 INFO L85 PathProgramCache]: Analyzing trace with hash 374468594, now seen corresponding path program 7 times [2021-12-15 17:21:33,941 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:33,941 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1223527705] [2021-12-15 17:21:33,941 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:33,941 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:33,946 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:21:33,946 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-15 17:21:33,949 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:21:33,953 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-15 17:21:33,953 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:33,954 INFO L85 PathProgramCache]: Analyzing trace with hash -1802005592, now seen corresponding path program 1 times [2021-12-15 17:21:33,954 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:33,954 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [358455500] [2021-12-15 17:21:33,954 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:33,954 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:33,962 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:33,980 INFO L134 CoverageAnalysis]: Checked inductivity of 107 backedges. 30 proven. 0 refuted. 0 times theorem prover too weak. 77 trivial. 0 not checked. [2021-12-15 17:21:33,981 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:33,981 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [358455500] [2021-12-15 17:21:33,981 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [358455500] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:33,981 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:33,981 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:33,982 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [227405878] [2021-12-15 17:21:33,982 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:33,982 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:21:33,982 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:21:33,982 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:21:33,983 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:21:33,983 INFO L87 Difference]: Start difference. First operand 6322 states and 8442 transitions. cyclomatic complexity: 2128 Second operand has 3 states, 3 states have (on average 57.666666666666664) internal successors, (173), 3 states have internal predecessors, (173), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:34,026 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:21:34,026 INFO L93 Difference]: Finished difference Result 6322 states and 8271 transitions. [2021-12-15 17:21:34,027 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:21:34,027 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6322 states and 8271 transitions. [2021-12-15 17:21:34,046 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 6197 [2021-12-15 17:21:34,060 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6322 states to 6322 states and 8271 transitions. [2021-12-15 17:21:34,060 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6322 [2021-12-15 17:21:34,063 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6322 [2021-12-15 17:21:34,063 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6322 states and 8271 transitions. [2021-12-15 17:21:34,067 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:21:34,067 INFO L681 BuchiCegarLoop]: Abstraction has 6322 states and 8271 transitions. [2021-12-15 17:21:34,069 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6322 states and 8271 transitions. [2021-12-15 17:21:34,154 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6322 to 6322. [2021-12-15 17:21:34,160 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6322 states, 6322 states have (on average 1.3082885162923126) internal successors, (8271), 6321 states have internal predecessors, (8271), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:34,171 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6322 states to 6322 states and 8271 transitions. [2021-12-15 17:21:34,171 INFO L704 BuchiCegarLoop]: Abstraction has 6322 states and 8271 transitions. [2021-12-15 17:21:34,171 INFO L587 BuchiCegarLoop]: Abstraction has 6322 states and 8271 transitions. [2021-12-15 17:21:34,171 INFO L425 BuchiCegarLoop]: ======== Iteration 19============ [2021-12-15 17:21:34,171 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6322 states and 8271 transitions. [2021-12-15 17:21:34,183 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 6197 [2021-12-15 17:21:34,183 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:21:34,183 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:21:34,185 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:34,185 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:34,185 INFO L791 eck$LassoCheckResult]: Stem: 101883#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 101815#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 101777#L615 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 101722#L274 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 101723#L281 assume 1 == ~m_i~0;~m_st~0 := 0; 101787#L281-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 101598#L286-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 101599#L291-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 101834#L296-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 101568#L418 assume !(0 == ~M_E~0); 101569#L418-2 assume !(0 == ~T1_E~0); 101786#L423-1 assume !(0 == ~T2_E~0); 101842#L428-1 assume !(0 == ~T3_E~0); 101839#L433-1 assume !(0 == ~E_1~0); 101822#L438-1 assume !(0 == ~E_2~0); 101741#L443-1 assume !(0 == ~E_3~0); 101733#L448-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 101692#L197 assume !(1 == ~m_pc~0); 101693#L197-2 is_master_triggered_~__retres1~0#1 := 0; 101874#L208 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 101878#L209 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 101855#L510 assume !(0 != activate_threads_~tmp~1#1); 101547#L510-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 101548#L216 assume !(1 == ~t1_pc~0); 101596#L216-2 is_transmit1_triggered_~__retres1~1#1 := 0; 101597#L227 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 101719#L228 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 101549#L518 assume !(0 != activate_threads_~tmp___0~0#1); 101550#L518-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 101749#L235 assume !(1 == ~t2_pc~0); 101831#L235-2 is_transmit2_triggered_~__retres1~2#1 := 0; 101680#L246 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 101681#L247 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 101863#L526 assume !(0 != activate_threads_~tmp___1~0#1); 101864#L526-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 101669#L254 assume !(1 == ~t3_pc~0); 101603#L254-2 is_transmit3_triggered_~__retres1~3#1 := 0; 101604#L265 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 101559#L266 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 101560#L534 assume !(0 != activate_threads_~tmp___2~0#1); 101672#L534-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 101539#L461 assume !(1 == ~M_E~0); 101540#L461-2 assume !(1 == ~T1_E~0); 101600#L466-1 assume !(1 == ~T2_E~0); 101847#L471-1 assume !(1 == ~T3_E~0); 101625#L476-1 assume !(1 == ~E_1~0); 101626#L481-1 assume !(1 == ~E_2~0); 101765#L486-1 assume !(1 == ~E_3~0); 101641#L491-1 assume { :end_inline_reset_delta_events } true; 101642#L652-2 [2021-12-15 17:21:34,185 INFO L793 eck$LassoCheckResult]: Loop: 101642#L652-2 assume !false; 102999#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 102992#L393 assume !false; 102985#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 102976#L309 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 102969#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 102959#L332 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 102950#L346 assume 0 != eval_~tmp~0#1; 102942#L346-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 102935#L354 assume 0 != eval_~tmp_ndt_1~0#1;~m_st~0 := 1;assume { :begin_inline_master } true; 101923#L53 assume 0 == ~m_pc~0; 101924#L80 assume !false; 101919#L65 ~E_1~0 := 1;assume { :begin_inline_immediate_notify } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 101920#L197-3 assume !(1 == ~m_pc~0); 101915#L197-5 is_master_triggered_~__retres1~0#1 := 0; 101916#L208-1 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 101772#L209-1 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 101773#L510-3 assume !(0 != activate_threads_~tmp~1#1); 101612#L510-5 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 101613#L216-3 assume !(1 == ~t1_pc~0); 102794#L216-5 is_transmit1_triggered_~__retres1~1#1 := 0; 102789#L227-1 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 102784#L228-1 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 102780#L518-3 assume !(0 != activate_threads_~tmp___0~0#1); 102777#L518-5 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 102746#L235-3 assume !(1 == ~t2_pc~0); 102711#L235-5 is_transmit2_triggered_~__retres1~2#1 := 0; 102708#L246-1 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 102706#L247-1 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 102704#L526-3 assume !(0 != activate_threads_~tmp___1~0#1); 102701#L526-5 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 102699#L254-3 assume !(1 == ~t3_pc~0); 102697#L254-5 is_transmit3_triggered_~__retres1~3#1 := 0; 102695#L265-1 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 102689#L266-1 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 102684#L534-3 assume !(0 != activate_threads_~tmp___2~0#1); 102677#L534-5 assume { :end_inline_activate_threads } true; 102675#L551 assume { :end_inline_immediate_notify } true;~E_1~0 := 2; 102673#L57 assume !false; 102671#L73 ~m_pc~0 := 1;~m_st~0 := 2; 102643#L83 assume { :end_inline_master } true; 102632#L351 assume !(0 == ~t1_st~0); 102629#L365 assume !(0 == ~t2_st~0); 103395#L379 assume !(0 == ~t3_st~0); 103390#L393 assume !false; 103388#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 103387#L309 assume !(0 == ~m_st~0); 102652#L313 assume !(0 == ~t1_st~0); 103378#L317 assume !(0 == ~t2_st~0); 103379#L321 assume !(0 == ~t3_st~0);exists_runnable_thread_~__retres1~4#1 := 0; 103380#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 103604#L332 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 103603#L346 assume !(0 != eval_~tmp~0#1); 103602#L408 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 103600#L274-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 103599#L418-3 assume !(0 == ~M_E~0); 103598#L418-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 103597#L423-3 assume !(0 == ~T2_E~0); 103595#L428-3 assume !(0 == ~T3_E~0); 103593#L433-3 assume !(0 == ~E_1~0); 103591#L438-3 assume !(0 == ~E_2~0); 103590#L443-3 assume !(0 == ~E_3~0); 103588#L448-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 103586#L197-12 assume 1 == ~m_pc~0; 103584#L198-4 assume !(1 == ~M_E~0); 103582#L197-14 is_master_triggered_~__retres1~0#1 := 0; 103580#L208-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 103578#L209-4 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 103574#L510-12 assume !(0 != activate_threads_~tmp~1#1); 103572#L510-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 103570#L216-12 assume !(1 == ~t1_pc~0); 103568#L216-14 is_transmit1_triggered_~__retres1~1#1 := 0; 103565#L227-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 103563#L228-4 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 103561#L518-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 103559#L518-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 103557#L235-12 assume !(1 == ~t2_pc~0); 103555#L235-14 is_transmit2_triggered_~__retres1~2#1 := 0; 103515#L246-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 103512#L247-4 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 103510#L526-12 assume !(0 != activate_threads_~tmp___1~0#1); 103507#L526-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 103505#L254-12 assume !(1 == ~t3_pc~0); 103503#L254-14 is_transmit3_triggered_~__retres1~3#1 := 0; 103501#L265-4 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 103499#L266-4 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 103497#L534-12 assume !(0 != activate_threads_~tmp___2~0#1); 103496#L534-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 103495#L461-3 assume !(1 == ~M_E~0); 103491#L461-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 103489#L466-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 103487#L471-3 assume !(1 == ~T3_E~0); 103485#L476-3 assume !(1 == ~E_1~0); 103484#L481-3 assume 1 == ~E_2~0;~E_2~0 := 2; 103483#L486-3 assume !(1 == ~E_3~0); 103480#L491-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 103478#L309-1 assume !(0 == ~m_st~0); 102783#L313-1 assume 0 == ~t1_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 103473#L331-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 103471#L332-1 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 103469#L671 assume 0 == start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 4;assume { :begin_inline_fire_time_events } true;~M_E~0 := 1; 103204#L560 assume { :end_inline_fire_time_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 103199#L197-15 assume 1 == ~m_pc~0; 103194#L198-5 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 103190#L208-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 103178#L209-5 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 102928#L510-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 102922#L510-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 102914#L216-15 assume !(1 == ~t1_pc~0); 102909#L216-17 is_transmit1_triggered_~__retres1~1#1 := 0; 102901#L227-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 102896#L228-5 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 102879#L518-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 102870#L518-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 102861#L235-15 assume 1 == ~t2_pc~0; 102853#L236-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 102848#L246-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 102843#L247-5 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 102835#L526-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 102831#L526-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 102827#L254-15 assume !(1 == ~t3_pc~0); 102823#L254-17 is_transmit3_triggered_~__retres1~3#1 := 0; 102817#L265-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 102812#L266-5 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 102807#L534-15 assume !(0 != activate_threads_~tmp___2~0#1); 102804#L534-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_time_events } true; 102799#L567 assume !(1 == ~M_E~0); 102800#L567-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 103654#L572-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 103648#L577-1 assume !(1 == ~T3_E~0); 103400#L582-1 assume !(1 == ~E_1~0); 103396#L587-1 assume !(1 == ~E_2~0); 103391#L592-1 assume 1 == ~E_3~0;~E_3~0 := 2; 103389#L597-1 assume { :end_inline_reset_time_events } true; 102981#L671-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 103385#L309-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 103384#L331-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 103383#L332-2 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 103381#L626 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 103377#L633 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 103375#L634 start_simulation_#t~ret15#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 103370#L684 assume !(0 != start_simulation_~tmp___0~1#1); 103368#L652-2 assume !false; 103361#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 103359#L393 assume !false; 103357#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 103355#L309 assume !(0 == ~m_st~0); 103057#L313 assume !(0 == ~t1_st~0); 103055#L317 assume !(0 == ~t2_st~0); 103053#L321 assume !(0 == ~t3_st~0);exists_runnable_thread_~__retres1~4#1 := 0; 103051#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 103049#L332 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 103046#L346 assume !(0 != eval_~tmp~0#1); 103044#L408 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 103041#L274-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 103039#L418-3 assume 0 == ~M_E~0;~M_E~0 := 1; 103037#L418-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 103035#L423-3 assume !(0 == ~T2_E~0); 103033#L428-3 assume !(0 == ~T3_E~0); 102998#L433-3 assume !(0 == ~E_1~0); 102991#L438-3 assume !(0 == ~E_2~0); 102984#L443-3 assume !(0 == ~E_3~0); 102975#L448-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 102967#L197-12 assume 1 == ~m_pc~0; 102957#L198-4 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 102949#L208-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 102941#L209-4 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 102933#L510-12 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 102924#L510-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 102916#L216-12 assume !(1 == ~t1_pc~0); 102911#L216-14 is_transmit1_triggered_~__retres1~1#1 := 0; 102906#L227-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 102898#L228-4 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 102889#L518-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 102885#L518-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 102884#L235-12 assume !(1 == ~t2_pc~0); 102883#L235-14 is_transmit2_triggered_~__retres1~2#1 := 0; 102881#L246-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 102872#L247-4 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 102863#L526-12 assume !(0 != activate_threads_~tmp___1~0#1); 102855#L526-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 102850#L254-12 assume !(1 == ~t3_pc~0); 102845#L254-14 is_transmit3_triggered_~__retres1~3#1 := 0; 102837#L265-4 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 102832#L266-4 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 102828#L534-12 assume !(0 != activate_threads_~tmp___2~0#1); 102824#L534-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 102818#L461-3 assume !(1 == ~M_E~0); 102819#L461-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 103031#L466-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 103027#L471-3 assume !(1 == ~T3_E~0); 103025#L476-3 assume !(1 == ~E_1~0); 103023#L481-3 assume 1 == ~E_2~0;~E_2~0 := 2; 103021#L486-3 assume !(1 == ~E_3~0); 103018#L491-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 103015#L309-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 102996#L331-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 102988#L332-1 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 102980#L671 assume 0 == start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 4;assume { :begin_inline_fire_time_events } true;~M_E~0 := 1; 102771#L560 assume { :end_inline_fire_time_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 102963#L197-15 assume !(1 == ~m_pc~0); 102964#L197-17 is_master_triggered_~__retres1~0#1 := 0; 103291#L208-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 103290#L209-5 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 103289#L510-15 assume !(0 != activate_threads_~tmp~1#1); 103287#L510-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 103284#L216-15 assume !(1 == ~t1_pc~0); 103282#L216-17 is_transmit1_triggered_~__retres1~1#1 := 0; 103280#L227-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 103278#L228-5 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 103273#L518-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 103269#L518-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 103264#L235-15 assume !(1 == ~t2_pc~0); 103259#L235-17 is_transmit2_triggered_~__retres1~2#1 := 0; 103241#L246-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 103238#L247-5 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 103236#L526-15 assume !(0 != activate_threads_~tmp___1~0#1); 103225#L526-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 103218#L254-15 assume !(1 == ~t3_pc~0); 103213#L254-17 is_transmit3_triggered_~__retres1~3#1 := 0; 103208#L265-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 103203#L266-5 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 103198#L534-15 assume !(0 != activate_threads_~tmp___2~0#1); 103193#L534-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_time_events } true; 103188#L567 assume 1 == ~M_E~0;~M_E~0 := 2; 103184#L567-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 103182#L572-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 103174#L577-1 assume !(1 == ~T3_E~0); 103097#L582-1 assume !(1 == ~E_1~0); 103096#L587-1 assume !(1 == ~E_2~0); 103095#L592-1 assume 1 == ~E_3~0;~E_3~0 := 2; 103088#L597-1 assume { :end_inline_reset_time_events } true; 103083#L671-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 103079#L309-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 103077#L331-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 103075#L332-2 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 103073#L626 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 103069#L633 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 103065#L634 start_simulation_#t~ret15#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 103059#L684 assume !(0 != start_simulation_~tmp___0~1#1); 101642#L652-2 [2021-12-15 17:21:34,186 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:34,186 INFO L85 PathProgramCache]: Analyzing trace with hash 374468594, now seen corresponding path program 8 times [2021-12-15 17:21:34,186 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:34,187 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [479242182] [2021-12-15 17:21:34,187 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:34,187 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:34,192 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:21:34,192 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-15 17:21:34,195 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:21:34,199 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-15 17:21:34,200 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:34,200 INFO L85 PathProgramCache]: Analyzing trace with hash 7909957, now seen corresponding path program 1 times [2021-12-15 17:21:34,200 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:34,200 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1916120256] [2021-12-15 17:21:34,200 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:34,200 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:34,208 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:34,236 INFO L134 CoverageAnalysis]: Checked inductivity of 108 backedges. 38 proven. 0 refuted. 0 times theorem prover too weak. 70 trivial. 0 not checked. [2021-12-15 17:21:34,237 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:34,237 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1916120256] [2021-12-15 17:21:34,237 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1916120256] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:34,237 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:34,237 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-15 17:21:34,237 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1501553347] [2021-12-15 17:21:34,238 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:34,238 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:21:34,238 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:21:34,239 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-15 17:21:34,239 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-15 17:21:34,239 INFO L87 Difference]: Start difference. First operand 6322 states and 8271 transitions. cyclomatic complexity: 1957 Second operand has 5 states, 5 states have (on average 35.6) internal successors, (178), 5 states have internal predecessors, (178), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:34,354 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:21:34,354 INFO L93 Difference]: Finished difference Result 7364 states and 9496 transitions. [2021-12-15 17:21:34,355 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-15 17:21:34,355 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7364 states and 9496 transitions. [2021-12-15 17:21:34,379 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 7159 [2021-12-15 17:21:34,423 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7364 states to 7364 states and 9496 transitions. [2021-12-15 17:21:34,424 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7364 [2021-12-15 17:21:34,446 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7364 [2021-12-15 17:21:34,447 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7364 states and 9496 transitions. [2021-12-15 17:21:34,453 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:21:34,454 INFO L681 BuchiCegarLoop]: Abstraction has 7364 states and 9496 transitions. [2021-12-15 17:21:34,456 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7364 states and 9496 transitions. [2021-12-15 17:21:34,515 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7364 to 6340. [2021-12-15 17:21:34,521 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6340 states, 6340 states have (on average 1.2905362776025238) internal successors, (8182), 6339 states have internal predecessors, (8182), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:34,531 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6340 states to 6340 states and 8182 transitions. [2021-12-15 17:21:34,531 INFO L704 BuchiCegarLoop]: Abstraction has 6340 states and 8182 transitions. [2021-12-15 17:21:34,532 INFO L587 BuchiCegarLoop]: Abstraction has 6340 states and 8182 transitions. [2021-12-15 17:21:34,532 INFO L425 BuchiCegarLoop]: ======== Iteration 20============ [2021-12-15 17:21:34,532 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6340 states and 8182 transitions. [2021-12-15 17:21:34,545 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 6215 [2021-12-15 17:21:34,545 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:21:34,545 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:21:34,547 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:34,547 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:34,547 INFO L791 eck$LassoCheckResult]: Stem: 115614#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 115527#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 115487#L615 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 115426#L274 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 115427#L281 assume 1 == ~m_i~0;~m_st~0 := 0; 115497#L281-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 115296#L286-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 115297#L291-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 115547#L296-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 115263#L418 assume !(0 == ~M_E~0); 115264#L418-2 assume !(0 == ~T1_E~0); 115496#L423-1 assume !(0 == ~T2_E~0); 115555#L428-1 assume !(0 == ~T3_E~0); 115553#L433-1 assume !(0 == ~E_1~0); 115533#L438-1 assume !(0 == ~E_2~0); 115444#L443-1 assume !(0 == ~E_3~0); 115437#L448-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 115395#L197 assume !(1 == ~m_pc~0); 115396#L197-2 is_master_triggered_~__retres1~0#1 := 0; 115601#L208 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 115602#L209 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 115576#L510 assume !(0 != activate_threads_~tmp~1#1); 115247#L510-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 115248#L216 assume !(1 == ~t1_pc~0); 115294#L216-2 is_transmit1_triggered_~__retres1~1#1 := 0; 115295#L227 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 115423#L228 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 115249#L518 assume !(0 != activate_threads_~tmp___0~0#1); 115250#L518-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 115456#L235 assume !(1 == ~t2_pc~0); 115541#L235-2 is_transmit2_triggered_~__retres1~2#1 := 0; 115542#L246 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 115625#L247 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 115586#L526 assume !(0 != activate_threads_~tmp___1~0#1); 115587#L526-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 115366#L254 assume !(1 == ~t3_pc~0); 115301#L254-2 is_transmit3_triggered_~__retres1~3#1 := 0; 115302#L265 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 115259#L266 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 115260#L534 assume !(0 != activate_threads_~tmp___2~0#1); 115373#L534-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 115239#L461 assume !(1 == ~M_E~0); 115240#L461-2 assume !(1 == ~T1_E~0); 115298#L466-1 assume !(1 == ~T2_E~0); 115564#L471-1 assume !(1 == ~T3_E~0); 115323#L476-1 assume !(1 == ~E_1~0); 115324#L481-1 assume !(1 == ~E_2~0); 115474#L486-1 assume !(1 == ~E_3~0); 115338#L491-1 assume { :end_inline_reset_delta_events } true; 115339#L652-2 [2021-12-15 17:21:34,548 INFO L793 eck$LassoCheckResult]: Loop: 115339#L652-2 assume !false; 117076#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 117069#L393 assume !false; 117068#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 117066#L309 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 117062#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 117061#L332 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 115658#L346 assume 0 != eval_~tmp~0#1; 115652#L346-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 115653#L354 assume 0 != eval_~tmp_ndt_1~0#1;~m_st~0 := 1;assume { :begin_inline_master } true; 117035#L53 assume 0 == ~m_pc~0; 115637#L80 assume !false; 115638#L65 ~E_1~0 := 1;assume { :begin_inline_immediate_notify } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 115367#L197-3 assume !(1 == ~m_pc~0); 115368#L197-5 is_master_triggered_~__retres1~0#1 := 0; 115545#L208-1 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 115546#L209-1 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 117034#L510-3 assume !(0 != activate_threads_~tmp~1#1); 117033#L510-5 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 115271#L216-3 assume !(1 == ~t1_pc~0); 115272#L216-5 is_transmit1_triggered_~__retres1~1#1 := 0; 117227#L227-1 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 117220#L228-1 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 117219#L518-3 assume !(0 != activate_threads_~tmp___0~0#1); 117218#L518-5 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 117216#L235-3 assume 1 == ~t2_pc~0; 117213#L236-1 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 117211#L246-1 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 117209#L247-1 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 117201#L526-3 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 117195#L526-5 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 117190#L254-3 assume !(1 == ~t3_pc~0); 117185#L254-5 is_transmit3_triggered_~__retres1~3#1 := 0; 117181#L265-1 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 117177#L266-1 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 117173#L534-3 assume !(0 != activate_threads_~tmp___2~0#1); 117169#L534-5 assume { :end_inline_activate_threads } true; 117167#L551 assume { :end_inline_immediate_notify } true;~E_1~0 := 2; 117165#L57 assume !false; 117163#L73 ~m_pc~0 := 1;~m_st~0 := 2; 117157#L83 assume { :end_inline_master } true; 117127#L351 assume !(0 == ~t1_st~0); 117075#L365 assume !(0 == ~t2_st~0); 117072#L379 assume !(0 == ~t3_st~0); 117040#L393 assume !false; 117041#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 116939#L309 assume !(0 == ~m_st~0); 116937#L313 assume !(0 == ~t1_st~0); 116935#L317 assume !(0 == ~t2_st~0); 116932#L321 assume !(0 == ~t3_st~0);exists_runnable_thread_~__retres1~4#1 := 0; 116930#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 116928#L332 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 116925#L346 assume !(0 != eval_~tmp~0#1); 116923#L408 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 116921#L274-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 116919#L418-3 assume !(0 == ~M_E~0); 116916#L418-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 116914#L423-3 assume !(0 == ~T2_E~0); 116912#L428-3 assume !(0 == ~T3_E~0); 116909#L433-3 assume !(0 == ~E_1~0); 116907#L438-3 assume !(0 == ~E_2~0); 116905#L443-3 assume !(0 == ~E_3~0); 116903#L448-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 116900#L197-12 assume 1 == ~m_pc~0; 116897#L198-4 assume !(1 == ~M_E~0); 116893#L197-14 is_master_triggered_~__retres1~0#1 := 0; 116889#L208-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 116884#L209-4 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 116844#L510-12 assume !(0 != activate_threads_~tmp~1#1); 116840#L510-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 116839#L216-12 assume !(1 == ~t1_pc~0); 116838#L216-14 is_transmit1_triggered_~__retres1~1#1 := 0; 116825#L227-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 116818#L228-4 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 116811#L518-12 assume !(0 != activate_threads_~tmp___0~0#1); 116804#L518-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 116803#L235-12 assume 1 == ~t2_pc~0; 116801#L236-4 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 116793#L246-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 116787#L247-4 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 116781#L526-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 116776#L526-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 116771#L254-12 assume !(1 == ~t3_pc~0); 116766#L254-14 is_transmit3_triggered_~__retres1~3#1 := 0; 116761#L265-4 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 116756#L266-4 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 116751#L534-12 assume !(0 != activate_threads_~tmp___2~0#1); 116748#L534-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 116732#L461-3 assume !(1 == ~M_E~0); 116251#L461-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 116721#L466-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 116718#L471-3 assume !(1 == ~T3_E~0); 116716#L476-3 assume !(1 == ~E_1~0); 116714#L481-3 assume 1 == ~E_2~0;~E_2~0 := 2; 116712#L486-3 assume !(1 == ~E_3~0); 116708#L491-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 116706#L309-1 assume !(0 == ~m_st~0); 116335#L313-1 assume 0 == ~t1_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 116668#L331-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 116666#L332-1 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 116663#L671 assume 0 == start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 4;assume { :begin_inline_fire_time_events } true;~M_E~0 := 1; 116153#L560 assume { :end_inline_fire_time_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 116659#L197-15 assume 1 == ~m_pc~0; 116656#L198-5 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 116615#L208-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 116586#L209-5 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 116587#L510-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 116641#L510-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 116640#L216-15 assume !(1 == ~t1_pc~0); 116638#L216-17 is_transmit1_triggered_~__retres1~1#1 := 0; 116632#L227-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 116624#L228-5 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 116618#L518-15 assume !(0 != activate_threads_~tmp___0~0#1); 116610#L518-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 116532#L235-15 assume 1 == ~t2_pc~0; 116530#L236-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 116531#L246-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 116539#L247-5 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 116519#L526-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 116516#L526-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 116514#L254-15 assume !(1 == ~t3_pc~0); 116510#L254-17 is_transmit3_triggered_~__retres1~3#1 := 0; 116508#L265-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 116506#L266-5 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 116504#L534-15 assume !(0 != activate_threads_~tmp___2~0#1); 116502#L534-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_time_events } true; 116499#L567 assume !(1 == ~M_E~0); 116496#L567-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 116494#L572-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 116492#L577-1 assume !(1 == ~T3_E~0); 116490#L582-1 assume !(1 == ~E_1~0); 116488#L587-1 assume !(1 == ~E_2~0); 116486#L592-1 assume 1 == ~E_3~0;~E_3~0 := 2; 115967#L597-1 assume { :end_inline_reset_time_events } true; 115965#L671-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 115962#L309-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 115960#L331-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 115958#L332-2 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 115957#L626 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 115956#L633 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 115952#L634 start_simulation_#t~ret15#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 115950#L684 assume !(0 != start_simulation_~tmp___0~1#1); 115948#L652-2 assume !false; 115947#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 115918#L393 assume !false; 115946#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 115944#L309 assume !(0 == ~m_st~0); 115945#L313 assume !(0 == ~t1_st~0); 116106#L317 assume !(0 == ~t2_st~0); 116107#L321 assume !(0 == ~t3_st~0);exists_runnable_thread_~__retres1~4#1 := 0; 116104#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 116101#L332 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 116098#L346 assume !(0 != eval_~tmp~0#1); 116096#L408 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 116094#L274-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 116092#L418-3 assume 0 == ~M_E~0;~M_E~0 := 1; 116090#L418-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 116088#L423-3 assume !(0 == ~T2_E~0); 116085#L428-3 assume !(0 == ~T3_E~0); 116082#L433-3 assume !(0 == ~E_1~0); 116079#L438-3 assume !(0 == ~E_2~0); 116076#L443-3 assume !(0 == ~E_3~0); 116074#L448-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 116071#L197-12 assume 1 == ~m_pc~0; 116068#L198-4 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 116066#L208-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 116064#L209-4 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 116061#L510-12 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 116059#L510-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 116055#L216-12 assume !(1 == ~t1_pc~0); 116053#L216-14 is_transmit1_triggered_~__retres1~1#1 := 0; 116050#L227-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 116047#L228-4 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 116044#L518-12 assume !(0 != activate_threads_~tmp___0~0#1); 116042#L518-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 116039#L235-12 assume !(1 == ~t2_pc~0); 116037#L235-14 is_transmit2_triggered_~__retres1~2#1 := 0; 116033#L246-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 116030#L247-4 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 116024#L526-12 assume !(0 != activate_threads_~tmp___1~0#1); 116018#L526-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 116014#L254-12 assume !(1 == ~t3_pc~0); 116010#L254-14 is_transmit3_triggered_~__retres1~3#1 := 0; 116005#L265-4 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 116003#L266-4 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 116001#L534-12 assume !(0 != activate_threads_~tmp___2~0#1); 115999#L534-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 115996#L461-3 assume !(1 == ~M_E~0); 115994#L461-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 115992#L466-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 115990#L471-3 assume !(1 == ~T3_E~0); 115988#L476-3 assume !(1 == ~E_1~0); 115985#L481-3 assume 1 == ~E_2~0;~E_2~0 := 2; 115982#L486-3 assume !(1 == ~E_3~0); 115979#L491-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 115975#L309-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 115973#L331-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 115971#L332-1 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 115968#L671 assume 0 == start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 4;assume { :begin_inline_fire_time_events } true;~M_E~0 := 1; 115969#L560 assume { :end_inline_fire_time_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 116323#L197-15 assume !(1 == ~m_pc~0); 116319#L197-17 is_master_triggered_~__retres1~0#1 := 0; 116315#L208-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 116311#L209-5 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 116306#L510-15 assume !(0 != activate_threads_~tmp~1#1); 116301#L510-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 116296#L216-15 assume !(1 == ~t1_pc~0); 116291#L216-17 is_transmit1_triggered_~__retres1~1#1 := 0; 116287#L227-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 116283#L228-5 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 116278#L518-15 assume !(0 != activate_threads_~tmp___0~0#1); 116272#L518-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 116266#L235-15 assume 1 == ~t2_pc~0; 116259#L236-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 116253#L246-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 116247#L247-5 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 116242#L526-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 116238#L526-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 116234#L254-15 assume !(1 == ~t3_pc~0); 116230#L254-17 is_transmit3_triggered_~__retres1~3#1 := 0; 116226#L265-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 116221#L266-5 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 116215#L534-15 assume !(0 != activate_threads_~tmp___2~0#1); 116211#L534-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_time_events } true; 116205#L567 assume 1 == ~M_E~0;~M_E~0 := 2; 116206#L567-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 117241#L572-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 117238#L577-1 assume !(1 == ~T3_E~0); 117234#L582-1 assume !(1 == ~E_1~0); 117229#L587-1 assume !(1 == ~E_2~0); 117222#L592-1 assume 1 == ~E_3~0;~E_3~0 := 2; 117203#L597-1 assume { :end_inline_reset_time_events } true; 117196#L671-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 117191#L309-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 117186#L331-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 117182#L332-2 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 117178#L626 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 117174#L633 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 117170#L634 start_simulation_#t~ret15#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 117158#L684 assume !(0 != start_simulation_~tmp___0~1#1); 115339#L652-2 [2021-12-15 17:21:34,548 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:34,548 INFO L85 PathProgramCache]: Analyzing trace with hash 374468594, now seen corresponding path program 9 times [2021-12-15 17:21:34,548 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:34,549 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [140325041] [2021-12-15 17:21:34,549 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:34,549 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:34,553 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:21:34,554 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-15 17:21:34,556 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:21:34,561 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-15 17:21:34,561 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:34,561 INFO L85 PathProgramCache]: Analyzing trace with hash 851081028, now seen corresponding path program 1 times [2021-12-15 17:21:34,561 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:34,562 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [321861351] [2021-12-15 17:21:34,562 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:34,562 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:34,571 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:34,589 INFO L134 CoverageAnalysis]: Checked inductivity of 108 backedges. 14 proven. 0 refuted. 0 times theorem prover too weak. 94 trivial. 0 not checked. [2021-12-15 17:21:34,589 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:34,589 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [321861351] [2021-12-15 17:21:34,589 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [321861351] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:34,589 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:34,589 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:34,590 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [82463283] [2021-12-15 17:21:34,590 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:34,590 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:21:34,590 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:21:34,590 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:21:34,591 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:21:34,591 INFO L87 Difference]: Start difference. First operand 6340 states and 8182 transitions. cyclomatic complexity: 1850 Second operand has 3 states, 3 states have (on average 51.666666666666664) internal successors, (155), 3 states have internal predecessors, (155), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:34,640 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:21:34,640 INFO L93 Difference]: Finished difference Result 10696 states and 13744 transitions. [2021-12-15 17:21:34,640 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:21:34,641 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 10696 states and 13744 transitions. [2021-12-15 17:21:34,681 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 10539 [2021-12-15 17:21:34,716 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 10696 states to 10696 states and 13744 transitions. [2021-12-15 17:21:34,717 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10696 [2021-12-15 17:21:34,721 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10696 [2021-12-15 17:21:34,721 INFO L73 IsDeterministic]: Start isDeterministic. Operand 10696 states and 13744 transitions. [2021-12-15 17:21:34,730 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:21:34,730 INFO L681 BuchiCegarLoop]: Abstraction has 10696 states and 13744 transitions. [2021-12-15 17:21:34,734 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10696 states and 13744 transitions. [2021-12-15 17:21:34,924 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10696 to 10312. [2021-12-15 17:21:34,934 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10312 states, 10312 states have (on average 1.2924747866563226) internal successors, (13328), 10311 states have internal predecessors, (13328), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:34,950 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10312 states to 10312 states and 13328 transitions. [2021-12-15 17:21:34,950 INFO L704 BuchiCegarLoop]: Abstraction has 10312 states and 13328 transitions. [2021-12-15 17:21:34,950 INFO L587 BuchiCegarLoop]: Abstraction has 10312 states and 13328 transitions. [2021-12-15 17:21:34,950 INFO L425 BuchiCegarLoop]: ======== Iteration 21============ [2021-12-15 17:21:34,950 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 10312 states and 13328 transitions. [2021-12-15 17:21:34,970 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 10155 [2021-12-15 17:21:34,971 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:21:34,971 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:21:34,973 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:34,973 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:34,973 INFO L791 eck$LassoCheckResult]: Stem: 132642#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 132567#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 132531#L615 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 132473#L274 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 132474#L281 assume 1 == ~m_i~0;~m_st~0 := 0; 132541#L281-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 132341#L286-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 132342#L291-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 132583#L296-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 132305#L418 assume !(0 == ~M_E~0); 132306#L418-2 assume !(0 == ~T1_E~0); 132540#L423-1 assume !(0 == ~T2_E~0); 132592#L428-1 assume !(0 == ~T3_E~0); 132589#L433-1 assume !(0 == ~E_1~0); 132572#L438-1 assume !(0 == ~E_2~0); 132491#L443-1 assume !(0 == ~E_3~0); 132484#L448-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 132439#L197 assume !(1 == ~m_pc~0); 132440#L197-2 is_master_triggered_~__retres1~0#1 := 0; 132630#L208 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 132633#L209 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 132608#L510 assume !(0 != activate_threads_~tmp~1#1); 132289#L510-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 132290#L216 assume !(1 == ~t1_pc~0); 132339#L216-2 is_transmit1_triggered_~__retres1~1#1 := 0; 132340#L227 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 132470#L228 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 132291#L518 assume !(0 != activate_threads_~tmp___0~0#1); 132292#L518-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 132501#L235 assume !(1 == ~t2_pc~0); 132580#L235-2 is_transmit2_triggered_~__retres1~2#1 := 0; 132423#L246 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 132424#L247 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 132619#L526 assume !(0 != activate_threads_~tmp___1~0#1); 132620#L526-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 132413#L254 assume !(1 == ~t3_pc~0); 132346#L254-2 is_transmit3_triggered_~__retres1~3#1 := 0; 132347#L265 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 132301#L266 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 132302#L534 assume !(0 != activate_threads_~tmp___2~0#1); 132417#L534-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 132281#L461 assume !(1 == ~M_E~0); 132282#L461-2 assume !(1 == ~T1_E~0); 132343#L466-1 assume !(1 == ~T2_E~0); 132598#L471-1 assume !(1 == ~T3_E~0); 132368#L476-1 assume !(1 == ~E_1~0); 132369#L481-1 assume !(1 == ~E_2~0); 132518#L486-1 assume !(1 == ~E_3~0); 132385#L491-1 assume { :end_inline_reset_delta_events } true; 132386#L652-2 [2021-12-15 17:21:34,973 INFO L793 eck$LassoCheckResult]: Loop: 132386#L652-2 assume !false; 135148#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 135145#L393 assume !false; 135142#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 135138#L309 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 135135#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 135132#L332 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 135131#L346 assume 0 != eval_~tmp~0#1; 135123#L346-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 135088#L354 assume 0 != eval_~tmp_ndt_1~0#1;~m_st~0 := 1;assume { :begin_inline_master } true; 135042#L53 assume 0 == ~m_pc~0; 135008#L80 assume !false; 135005#L65 ~E_1~0 := 1;assume { :begin_inline_immediate_notify } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 135003#L197-3 assume !(1 == ~m_pc~0); 135001#L197-5 is_master_triggered_~__retres1~0#1 := 0; 134999#L208-1 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 134997#L209-1 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 134995#L510-3 assume !(0 != activate_threads_~tmp~1#1); 134993#L510-5 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 134991#L216-3 assume !(1 == ~t1_pc~0); 134989#L216-5 is_transmit1_triggered_~__retres1~1#1 := 0; 134985#L227-1 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 134983#L228-1 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 134981#L518-3 assume !(0 != activate_threads_~tmp___0~0#1); 134979#L518-5 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 134976#L235-3 assume !(1 == ~t2_pc~0); 132330#L235-5 is_transmit2_triggered_~__retres1~2#1 := 0; 132331#L246-1 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 132640#L247-1 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 132564#L526-3 assume !(0 != activate_threads_~tmp___1~0#1); 132388#L526-5 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 132389#L254-3 assume !(1 == ~t3_pc~0); 132550#L254-5 is_transmit3_triggered_~__retres1~3#1 := 0; 135083#L265-1 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 135078#L266-1 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 135060#L534-3 assume !(0 != activate_threads_~tmp___2~0#1); 135040#L534-5 assume { :end_inline_activate_threads } true; 135036#L551 assume { :end_inline_immediate_notify } true;~E_1~0 := 2; 135031#L57 assume !false; 135026#L73 ~m_pc~0 := 1;~m_st~0 := 2; 134910#L83 assume { :end_inline_master } true; 133030#L351 assume !(0 == ~t1_st~0); 134906#L365 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 134830#L382 assume 0 != eval_~tmp_ndt_3~0#1;~t2_st~0 := 1;assume { :begin_inline_transmit2 } true; 134902#L129 assume 0 == ~t2_pc~0; 134897#L140-1 assume !false; 134833#L141 ~t2_pc~0 := 1;~t2_st~0 := 2; 134829#L153 assume { :end_inline_transmit2 } true; 134827#L379 assume !(0 == ~t3_st~0); 134822#L393 assume !false; 134771#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 134764#L309 assume !(0 == ~m_st~0); 132920#L313 assume !(0 == ~t1_st~0); 134761#L317 assume !(0 == ~t2_st~0); 134756#L321 assume !(0 == ~t3_st~0);exists_runnable_thread_~__retres1~4#1 := 0; 134625#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 134621#L332 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 134618#L346 assume !(0 != eval_~tmp~0#1); 134619#L408 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 135202#L274-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 135201#L418-3 assume !(0 == ~M_E~0); 135200#L418-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 135199#L423-3 assume !(0 == ~T2_E~0); 135198#L428-3 assume !(0 == ~T3_E~0); 135197#L433-3 assume !(0 == ~E_1~0); 135196#L438-3 assume !(0 == ~E_2~0); 135195#L443-3 assume !(0 == ~E_3~0); 135194#L448-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 135193#L197-12 assume 1 == ~m_pc~0; 135192#L198-4 assume !(1 == ~M_E~0); 135191#L197-14 is_master_triggered_~__retres1~0#1 := 0; 135190#L208-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 135189#L209-4 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 135188#L510-12 assume !(0 != activate_threads_~tmp~1#1); 135186#L510-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 135184#L216-12 assume !(1 == ~t1_pc~0); 135182#L216-14 is_transmit1_triggered_~__retres1~1#1 := 0; 135180#L227-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 135178#L228-4 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 135176#L518-12 assume !(0 != activate_threads_~tmp___0~0#1); 135174#L518-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 135171#L235-12 assume 1 == ~t2_pc~0; 135168#L236-4 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 135165#L246-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 135126#L247-4 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 135127#L526-12 assume !(0 != activate_threads_~tmp___1~0#1); 135020#L526-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 134896#L254-12 assume !(1 == ~t3_pc~0); 134895#L254-14 is_transmit3_triggered_~__retres1~3#1 := 0; 134894#L265-4 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 134893#L266-4 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 134891#L534-12 assume !(0 != activate_threads_~tmp___2~0#1); 134890#L534-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 134889#L461-3 assume !(1 == ~M_E~0); 133370#L461-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 134886#L466-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 134884#L471-3 assume !(1 == ~T3_E~0); 134882#L476-3 assume !(1 == ~E_1~0); 134880#L481-3 assume 1 == ~E_2~0;~E_2~0 := 2; 134879#L486-3 assume !(1 == ~E_3~0); 134877#L491-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 134876#L309-1 assume !(0 == ~m_st~0); 132977#L313-1 assume 0 == ~t1_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 134872#L331-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 134871#L332-1 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 134869#L671 assume 0 == start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 4;assume { :begin_inline_fire_time_events } true;~M_E~0 := 1; 133339#L560 assume { :end_inline_fire_time_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 135368#L197-15 assume 1 == ~m_pc~0; 135364#L198-5 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 135339#L208-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 135333#L209-5 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 135334#L510-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 135467#L510-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 135462#L216-15 assume !(1 == ~t1_pc~0); 135459#L216-17 is_transmit1_triggered_~__retres1~1#1 := 0; 135455#L227-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 135451#L228-5 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 135447#L518-15 assume !(0 != activate_threads_~tmp___0~0#1); 135442#L518-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 135438#L235-15 assume !(1 == ~t2_pc~0); 135434#L235-17 is_transmit2_triggered_~__retres1~2#1 := 0; 135443#L246-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 135407#L247-5 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 133010#L526-15 assume !(0 != activate_threads_~tmp___1~0#1); 133008#L526-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 133006#L254-15 assume !(1 == ~t3_pc~0); 133004#L254-17 is_transmit3_triggered_~__retres1~3#1 := 0; 133002#L265-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 132999#L266-5 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 132996#L534-15 assume !(0 != activate_threads_~tmp___2~0#1); 132993#L534-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_time_events } true; 132990#L567 assume !(1 == ~M_E~0); 132986#L567-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 132982#L572-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 132978#L577-1 assume !(1 == ~T3_E~0); 132972#L582-1 assume !(1 == ~E_1~0); 132968#L587-1 assume !(1 == ~E_2~0); 132964#L592-1 assume 1 == ~E_3~0;~E_3~0 := 2; 132959#L597-1 assume { :end_inline_reset_time_events } true; 132957#L671-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 132953#L309-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 132951#L331-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 132949#L332-2 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 132947#L626 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 132945#L633 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 132943#L634 start_simulation_#t~ret15#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 132939#L684 assume !(0 != start_simulation_~tmp___0~1#1); 132933#L652-2 assume !false; 132925#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 132923#L393 assume !false; 132921#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 132917#L309 assume !(0 == ~m_st~0); 132918#L313 assume !(0 == ~t1_st~0); 133285#L317 assume !(0 == ~t2_st~0); 133284#L321 assume !(0 == ~t3_st~0);exists_runnable_thread_~__retres1~4#1 := 0; 133249#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 133240#L332 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 133232#L346 assume !(0 != eval_~tmp~0#1); 133233#L408 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 134347#L274-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 134346#L418-3 assume 0 == ~M_E~0;~M_E~0 := 1; 134345#L418-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 134344#L423-3 assume !(0 == ~T2_E~0); 134343#L428-3 assume !(0 == ~T3_E~0); 134342#L433-3 assume !(0 == ~E_1~0); 134341#L438-3 assume !(0 == ~E_2~0); 134340#L443-3 assume !(0 == ~E_3~0); 134339#L448-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 134337#L197-12 assume 1 == ~m_pc~0; 134334#L198-4 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 134335#L208-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 134319#L209-4 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 134320#L510-12 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 135456#L510-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 135452#L216-12 assume !(1 == ~t1_pc~0); 135448#L216-14 is_transmit1_triggered_~__retres1~1#1 := 0; 135444#L227-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 135439#L228-4 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 135435#L518-12 assume !(0 != activate_threads_~tmp___0~0#1); 135429#L518-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 135426#L235-12 assume !(1 == ~t2_pc~0); 135424#L235-14 is_transmit2_triggered_~__retres1~2#1 := 0; 135403#L246-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 133017#L247-4 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 133015#L526-12 assume !(0 != activate_threads_~tmp___1~0#1); 133014#L526-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 133013#L254-12 assume !(1 == ~t3_pc~0); 133012#L254-14 is_transmit3_triggered_~__retres1~3#1 := 0; 133011#L265-4 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 133009#L266-4 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 133007#L534-12 assume !(0 != activate_threads_~tmp___2~0#1); 133005#L534-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 133003#L461-3 assume !(1 == ~M_E~0); 133000#L461-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 132997#L466-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 132994#L471-3 assume !(1 == ~T3_E~0); 132991#L476-3 assume !(1 == ~E_1~0); 132987#L481-3 assume 1 == ~E_2~0;~E_2~0 := 2; 132983#L486-3 assume !(1 == ~E_3~0); 132979#L491-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 132973#L309-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 132969#L331-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 132965#L332-1 start_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 132960#L671 assume 0 == start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 4;assume { :begin_inline_fire_time_events } true;~M_E~0 := 1; 132961#L560 assume { :end_inline_fire_time_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 134026#L197-15 assume !(1 == ~m_pc~0); 134024#L197-17 is_master_triggered_~__retres1~0#1 := 0; 134022#L208-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 134020#L209-5 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 134017#L510-15 assume !(0 != activate_threads_~tmp~1#1); 134015#L510-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 134013#L216-15 assume !(1 == ~t1_pc~0); 134011#L216-17 is_transmit1_triggered_~__retres1~1#1 := 0; 134009#L227-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 134007#L228-5 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 134005#L518-15 assume !(0 != activate_threads_~tmp___0~0#1); 134003#L518-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 134001#L235-15 assume 1 == ~t2_pc~0; 133997#L236-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 133995#L246-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 133993#L247-5 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 133961#L526-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 133959#L526-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 133957#L254-15 assume !(1 == ~t3_pc~0); 133954#L254-17 is_transmit3_triggered_~__retres1~3#1 := 0; 133951#L265-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 133950#L266-5 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 133947#L534-15 assume !(0 != activate_threads_~tmp___2~0#1); 133946#L534-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_time_events } true; 133943#L567 assume 1 == ~M_E~0;~M_E~0 := 2; 133944#L567-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 135187#L572-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 135185#L577-1 assume !(1 == ~T3_E~0); 135183#L582-1 assume !(1 == ~E_1~0); 135181#L587-1 assume !(1 == ~E_2~0); 135179#L592-1 assume 1 == ~E_3~0;~E_3~0 := 2; 135177#L597-1 assume { :end_inline_reset_time_events } true; 135175#L671-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret13#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 135172#L309-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 135170#L331-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 135167#L332-2 stop_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret13#1;havoc stop_simulation_#t~ret13#1; 135163#L626 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 135161#L633 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 135160#L634 start_simulation_#t~ret15#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 135157#L684 assume !(0 != start_simulation_~tmp___0~1#1); 132386#L652-2 [2021-12-15 17:21:34,974 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:34,974 INFO L85 PathProgramCache]: Analyzing trace with hash 374468594, now seen corresponding path program 10 times [2021-12-15 17:21:34,974 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:34,974 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1098739299] [2021-12-15 17:21:34,975 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:34,975 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:34,979 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:21:34,979 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-15 17:21:34,982 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:21:34,986 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-15 17:21:34,986 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:34,987 INFO L85 PathProgramCache]: Analyzing trace with hash 580244623, now seen corresponding path program 1 times [2021-12-15 17:21:34,987 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:34,987 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1816667933] [2021-12-15 17:21:34,987 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:34,987 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:34,996 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:35,028 INFO L134 CoverageAnalysis]: Checked inductivity of 107 backedges. 43 proven. 0 refuted. 0 times theorem prover too weak. 64 trivial. 0 not checked. [2021-12-15 17:21:35,028 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:35,028 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1816667933] [2021-12-15 17:21:35,028 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1816667933] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:35,028 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:35,029 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2021-12-15 17:21:35,029 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [130303511] [2021-12-15 17:21:35,029 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:35,029 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:21:35,029 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:21:35,030 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2021-12-15 17:21:35,030 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2021-12-15 17:21:35,030 INFO L87 Difference]: Start difference. First operand 10312 states and 13328 transitions. cyclomatic complexity: 3024 Second operand has 6 states, 6 states have (on average 31.5) internal successors, (189), 6 states have internal predecessors, (189), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:35,252 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:21:35,252 INFO L93 Difference]: Finished difference Result 22551 states and 28494 transitions. [2021-12-15 17:21:35,252 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2021-12-15 17:21:35,254 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 22551 states and 28494 transitions. [2021-12-15 17:21:35,348 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 22273 [2021-12-15 17:21:35,402 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 22551 states to 22551 states and 28494 transitions. [2021-12-15 17:21:35,403 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 22551 [2021-12-15 17:21:35,418 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 22551 [2021-12-15 17:21:35,418 INFO L73 IsDeterministic]: Start isDeterministic. Operand 22551 states and 28494 transitions. [2021-12-15 17:21:35,441 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:21:35,441 INFO L681 BuchiCegarLoop]: Abstraction has 22551 states and 28494 transitions. [2021-12-15 17:21:35,454 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22551 states and 28494 transitions. [2021-12-15 17:21:35,712 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22551 to 10715. [2021-12-15 17:21:35,720 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10715 states, 10715 states have (on average 1.2800746616892207) internal successors, (13716), 10714 states have internal predecessors, (13716), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:35,737 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10715 states to 10715 states and 13716 transitions. [2021-12-15 17:21:35,737 INFO L704 BuchiCegarLoop]: Abstraction has 10715 states and 13716 transitions. [2021-12-15 17:21:35,738 INFO L587 BuchiCegarLoop]: Abstraction has 10715 states and 13716 transitions. [2021-12-15 17:21:35,738 INFO L425 BuchiCegarLoop]: ======== Iteration 22============ [2021-12-15 17:21:35,738 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 10715 states and 13716 transitions. [2021-12-15 17:21:35,762 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 10542 [2021-12-15 17:21:35,762 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:21:35,762 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:21:35,763 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:35,763 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:35,763 INFO L791 eck$LassoCheckResult]: Stem: 165525#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 165439#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 165408#L615 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14#1, start_simulation_#t~ret15#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 165350#L274 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 165351#L281 assume 1 == ~m_i~0;~m_st~0 := 0; 165416#L281-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 165225#L286-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 165226#L291-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 165456#L296-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 165191#L418 assume !(0 == ~M_E~0); 165192#L418-2 assume !(0 == ~T1_E~0); 165415#L423-1 assume !(0 == ~T2_E~0); 165465#L428-1 assume !(0 == ~T3_E~0); 165462#L433-1 assume !(0 == ~E_1~0); 165445#L438-1 assume !(0 == ~E_2~0); 165368#L443-1 assume !(0 == ~E_3~0); 165362#L448-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 165318#L197 assume !(1 == ~m_pc~0); 165319#L197-2 is_master_triggered_~__retres1~0#1 := 0; 165511#L208 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 165512#L209 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 165481#L510 assume !(0 != activate_threads_~tmp~1#1); 165175#L510-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 165176#L216 assume !(1 == ~t1_pc~0); 165223#L216-2 is_transmit1_triggered_~__retres1~1#1 := 0; 165224#L227 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 165347#L228 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 165177#L518 assume !(0 != activate_threads_~tmp___0~0#1); 165178#L518-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 165379#L235 assume !(1 == ~t2_pc~0); 165453#L235-2 is_transmit2_triggered_~__retres1~2#1 := 0; 165304#L246 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 165305#L247 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 165493#L526 assume !(0 != activate_threads_~tmp___1~0#1); 165494#L526-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 165292#L254 assume !(1 == ~t3_pc~0); 165230#L254-2 is_transmit3_triggered_~__retres1~3#1 := 0; 165231#L265 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 165187#L266 activate_threads_#t~ret12#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 165188#L534 assume !(0 != activate_threads_~tmp___2~0#1); 165297#L534-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 165167#L461 assume !(1 == ~M_E~0); 165168#L461-2 assume !(1 == ~T1_E~0); 165227#L466-1 assume !(1 == ~T2_E~0); 165473#L471-1 assume !(1 == ~T3_E~0); 165250#L476-1 assume !(1 == ~E_1~0); 165251#L481-1 assume !(1 == ~E_2~0); 165394#L486-1 assume !(1 == ~E_3~0); 165265#L491-1 assume { :end_inline_reset_delta_events } true; 165266#L652-2 assume !false; 172302#L653 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 172297#L393 [2021-12-15 17:21:35,764 INFO L793 eck$LassoCheckResult]: Loop: 172297#L393 assume !false; 172292#L342 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 172288#L309 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 172284#L331 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 172279#L332 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 172269#L346 assume 0 != eval_~tmp~0#1; 172254#L346-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 172247#L354 assume !(0 != eval_~tmp_ndt_1~0#1); 172240#L351 assume !(0 == ~t1_st~0); 172233#L365 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 172309#L382 assume !(0 != eval_~tmp_ndt_3~0#1); 172305#L379 assume !(0 == ~t3_st~0); 172297#L393 [2021-12-15 17:21:35,764 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:35,764 INFO L85 PathProgramCache]: Analyzing trace with hash -912926924, now seen corresponding path program 1 times [2021-12-15 17:21:35,764 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:35,764 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [427497676] [2021-12-15 17:21:35,765 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:35,765 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:35,769 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:21:35,770 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-15 17:21:35,772 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:21:35,777 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-15 17:21:35,779 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:35,779 INFO L85 PathProgramCache]: Analyzing trace with hash -1352291815, now seen corresponding path program 1 times [2021-12-15 17:21:35,779 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:35,779 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [354144106] [2021-12-15 17:21:35,779 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:35,780 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:35,782 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:21:35,782 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-15 17:21:35,783 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:21:35,784 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-15 17:21:35,785 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:35,785 INFO L85 PathProgramCache]: Analyzing trace with hash 1342917836, now seen corresponding path program 1 times [2021-12-15 17:21:35,785 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:35,785 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [706489766] [2021-12-15 17:21:35,785 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:35,785 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:35,791 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:35,802 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:35,802 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:35,802 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [706489766] [2021-12-15 17:21:35,804 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [706489766] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:35,804 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:35,804 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:35,804 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1047427499] [2021-12-15 17:21:35,804 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:35,888 FATAL L? ?]: The Plugin de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer has thrown an exception: java.lang.UnsupportedOperationException: Set is immutable at de.uni_freiburg.informatik.ultimate.util.datastructures.ImmutableSet.retainAll(ImmutableSet.java:338) at de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.cfg.transitions.UnmodifiableTransFormula.removeSuperfluousVars(UnmodifiableTransFormula.java:212) at de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.cfg.transitions.TransFormulaBuilder.finishConstruction(TransFormulaBuilder.java:273) at de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.cfg.transitions.TransFormulaBuilder.getTrivialTransFormula(TransFormulaBuilder.java:285) at de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.LassoCheck.synthesize(LassoCheck.java:548) at de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.LassoCheck$LassoCheckResult.checkLoopTermination(LassoCheck.java:944) at de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.LassoCheck$LassoCheckResult.(LassoCheck.java:834) at de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.LassoCheck.(LassoCheck.java:252) at de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiCegarLoop.iterate(BuchiCegarLoop.java:457) at de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver.doTerminationAnalysis(BuchiAutomizerObserver.java:142) at de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver.finish(BuchiAutomizerObserver.java:397) at de.uni_freiburg.informatik.ultimate.core.coreplugin.PluginConnector.runObserver(PluginConnector.java:168) at de.uni_freiburg.informatik.ultimate.core.coreplugin.PluginConnector.runTool(PluginConnector.java:151) at de.uni_freiburg.informatik.ultimate.core.coreplugin.PluginConnector.run(PluginConnector.java:128) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.executePluginConnector(ToolchainWalker.java:232) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.processPlugin(ToolchainWalker.java:226) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.walkUnprotected(ToolchainWalker.java:142) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.walk(ToolchainWalker.java:104) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainManager$Toolchain.processToolchain(ToolchainManager.java:320) at de.uni_freiburg.informatik.ultimate.core.coreplugin.toolchain.DefaultToolchainJob.run(DefaultToolchainJob.java:145) at org.eclipse.core.internal.jobs.Worker.run(Worker.java:63) [2021-12-15 17:21:35,895 INFO L158 Benchmark]: Toolchain (without parser) took 7277.10ms. Allocated memory was 104.9MB in the beginning and 566.2MB in the end (delta: 461.4MB). Free memory was 79.3MB in the beginning and 336.9MB in the end (delta: -257.6MB). Peak memory consumption was 204.0MB. Max. memory is 16.1GB. [2021-12-15 17:21:35,895 INFO L158 Benchmark]: CDTParser took 0.17ms. Allocated memory is still 83.9MB. Free memory is still 49.0MB. There was no memory consumed. Max. memory is 16.1GB. [2021-12-15 17:21:35,896 INFO L158 Benchmark]: CACSL2BoogieTranslator took 250.65ms. Allocated memory is still 104.9MB. Free memory was 79.0MB in the beginning and 78.7MB in the end (delta: 346.9kB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2021-12-15 17:21:35,896 INFO L158 Benchmark]: Boogie Procedure Inliner took 46.80ms. Allocated memory is still 104.9MB. Free memory was 78.7MB in the beginning and 75.3MB in the end (delta: 3.4MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2021-12-15 17:21:35,896 INFO L158 Benchmark]: Boogie Preprocessor took 34.60ms. Allocated memory is still 104.9MB. Free memory was 75.3MB in the beginning and 72.5MB in the end (delta: 2.9MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2021-12-15 17:21:35,896 INFO L158 Benchmark]: RCFGBuilder took 671.55ms. Allocated memory is still 104.9MB. Free memory was 72.5MB in the beginning and 74.2MB in the end (delta: -1.7MB). Peak memory consumption was 27.3MB. Max. memory is 16.1GB. [2021-12-15 17:21:35,896 INFO L158 Benchmark]: BuchiAutomizer took 6269.20ms. Allocated memory was 104.9MB in the beginning and 566.2MB in the end (delta: 461.4MB). Free memory was 74.2MB in the beginning and 336.9MB in the end (delta: -262.7MB). Peak memory consumption was 201.2MB. Max. memory is 16.1GB. [2021-12-15 17:21:35,898 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.17ms. Allocated memory is still 83.9MB. Free memory is still 49.0MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 250.65ms. Allocated memory is still 104.9MB. Free memory was 79.0MB in the beginning and 78.7MB in the end (delta: 346.9kB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 46.80ms. Allocated memory is still 104.9MB. Free memory was 78.7MB in the beginning and 75.3MB in the end (delta: 3.4MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * Boogie Preprocessor took 34.60ms. Allocated memory is still 104.9MB. Free memory was 75.3MB in the beginning and 72.5MB in the end (delta: 2.9MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * RCFGBuilder took 671.55ms. Allocated memory is still 104.9MB. Free memory was 72.5MB in the beginning and 74.2MB in the end (delta: -1.7MB). Peak memory consumption was 27.3MB. Max. memory is 16.1GB. * BuchiAutomizer took 6269.20ms. Allocated memory was 104.9MB in the beginning and 566.2MB in the end (delta: 461.4MB). Free memory was 74.2MB in the beginning and 336.9MB in the end (delta: -262.7MB). Peak memory consumption was 201.2MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer: - ExceptionOrErrorResult: UnsupportedOperationException: Set is immutable de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer: UnsupportedOperationException: Set is immutable: de.uni_freiburg.informatik.ultimate.util.datastructures.ImmutableSet.retainAll(ImmutableSet.java:338) RESULT: Ultimate could not prove your program: Toolchain returned no result. [2021-12-15 17:21:35,937 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Ended with exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Using bit-precise analysis No suitable file found in config dir /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config using search string *Termination*32bit*_Bitvector*.epf No suitable settings file found using Termination*32bit*_Bitvector ERROR: UNSUPPORTED PROPERTY Writing output log to file Ultimate.log Result: ERROR: ExceptionOrErrorResult: UnsupportedOperationException: Set is immutable