./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/transmitter.08.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 3a877d22 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/transmitter.08.cil.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash d0fbb3eaba725aed5c3b8bf09c66f0f1daed4feeee0b9a3792dc033de334e501 --- Real Ultimate output --- This is Ultimate 0.2.2-3a877d227dc491413fd706022d0c47cd97beb353-3a877d2 [2021-12-15 17:21:33,728 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-12-15 17:21:33,729 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-12-15 17:21:33,750 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-12-15 17:21:33,752 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-12-15 17:21:33,754 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-12-15 17:21:33,756 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-12-15 17:21:33,760 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-12-15 17:21:33,762 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-12-15 17:21:33,765 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-12-15 17:21:33,765 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-12-15 17:21:33,766 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-12-15 17:21:33,767 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-12-15 17:21:33,769 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-12-15 17:21:33,770 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-12-15 17:21:33,773 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-12-15 17:21:33,774 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-12-15 17:21:33,774 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-12-15 17:21:33,777 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-12-15 17:21:33,781 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-12-15 17:21:33,782 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-12-15 17:21:33,783 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-12-15 17:21:33,784 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-12-15 17:21:33,785 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-12-15 17:21:33,789 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-12-15 17:21:33,789 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-12-15 17:21:33,790 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-12-15 17:21:33,791 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-12-15 17:21:33,791 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-12-15 17:21:33,792 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-12-15 17:21:33,792 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-12-15 17:21:33,793 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-12-15 17:21:33,794 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-12-15 17:21:33,795 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-12-15 17:21:33,796 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-12-15 17:21:33,796 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-12-15 17:21:33,796 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-12-15 17:21:33,796 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-12-15 17:21:33,797 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-12-15 17:21:33,797 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-12-15 17:21:33,798 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-12-15 17:21:33,798 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2021-12-15 17:21:33,826 INFO L113 SettingsManager]: Loading preferences was successful [2021-12-15 17:21:33,826 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-12-15 17:21:33,827 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2021-12-15 17:21:33,827 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2021-12-15 17:21:33,828 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-12-15 17:21:33,828 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-12-15 17:21:33,828 INFO L138 SettingsManager]: * Use SBE=true [2021-12-15 17:21:33,828 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2021-12-15 17:21:33,828 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2021-12-15 17:21:33,829 INFO L138 SettingsManager]: * Use old map elimination=false [2021-12-15 17:21:33,829 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2021-12-15 17:21:33,829 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2021-12-15 17:21:33,829 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2021-12-15 17:21:33,830 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-12-15 17:21:33,830 INFO L138 SettingsManager]: * sizeof long=4 [2021-12-15 17:21:33,830 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2021-12-15 17:21:33,830 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-12-15 17:21:33,830 INFO L138 SettingsManager]: * sizeof POINTER=4 [2021-12-15 17:21:33,830 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-12-15 17:21:33,830 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2021-12-15 17:21:33,831 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2021-12-15 17:21:33,831 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2021-12-15 17:21:33,831 INFO L138 SettingsManager]: * sizeof long double=12 [2021-12-15 17:21:33,831 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-12-15 17:21:33,832 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2021-12-15 17:21:33,832 INFO L138 SettingsManager]: * Use constant arrays=true [2021-12-15 17:21:33,832 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2021-12-15 17:21:33,832 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-12-15 17:21:33,833 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-12-15 17:21:33,833 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-12-15 17:21:33,833 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-12-15 17:21:33,833 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2021-12-15 17:21:33,834 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2021-12-15 17:21:33,834 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> d0fbb3eaba725aed5c3b8bf09c66f0f1daed4feeee0b9a3792dc033de334e501 [2021-12-15 17:21:34,024 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-12-15 17:21:34,039 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-12-15 17:21:34,041 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-12-15 17:21:34,042 INFO L271 PluginConnector]: Initializing CDTParser... [2021-12-15 17:21:34,054 INFO L275 PluginConnector]: CDTParser initialized [2021-12-15 17:21:34,064 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/transmitter.08.cil.c [2021-12-15 17:21:34,121 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/1d5e872f0/4c9212e936184bc4a838ee45f80ac1a4/FLAG55b6d589d [2021-12-15 17:21:34,449 INFO L306 CDTParser]: Found 1 translation units. [2021-12-15 17:21:34,450 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.08.cil.c [2021-12-15 17:21:34,461 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/1d5e872f0/4c9212e936184bc4a838ee45f80ac1a4/FLAG55b6d589d [2021-12-15 17:21:34,851 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/1d5e872f0/4c9212e936184bc4a838ee45f80ac1a4 [2021-12-15 17:21:34,868 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-12-15 17:21:34,869 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-12-15 17:21:34,870 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-12-15 17:21:34,871 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-12-15 17:21:34,874 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-12-15 17:21:34,874 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 15.12 05:21:34" (1/1) ... [2021-12-15 17:21:34,875 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@3e7c833f and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:21:34, skipping insertion in model container [2021-12-15 17:21:34,875 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 15.12 05:21:34" (1/1) ... [2021-12-15 17:21:34,879 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-12-15 17:21:34,915 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-12-15 17:21:35,092 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.08.cil.c[706,719] [2021-12-15 17:21:35,168 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-15 17:21:35,174 INFO L203 MainTranslator]: Completed pre-run [2021-12-15 17:21:35,181 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.08.cil.c[706,719] [2021-12-15 17:21:35,225 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-15 17:21:35,247 INFO L208 MainTranslator]: Completed translation [2021-12-15 17:21:35,249 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:21:35 WrapperNode [2021-12-15 17:21:35,249 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-12-15 17:21:35,250 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-12-15 17:21:35,250 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-12-15 17:21:35,251 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-12-15 17:21:35,267 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:21:35" (1/1) ... [2021-12-15 17:21:35,284 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:21:35" (1/1) ... [2021-12-15 17:21:35,343 INFO L137 Inliner]: procedures = 44, calls = 54, calls flagged for inlining = 49, calls inlined = 146, statements flattened = 2198 [2021-12-15 17:21:35,343 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-12-15 17:21:35,344 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-12-15 17:21:35,344 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-12-15 17:21:35,344 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-12-15 17:21:35,350 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:21:35" (1/1) ... [2021-12-15 17:21:35,350 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:21:35" (1/1) ... [2021-12-15 17:21:35,355 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:21:35" (1/1) ... [2021-12-15 17:21:35,356 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:21:35" (1/1) ... [2021-12-15 17:21:35,373 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:21:35" (1/1) ... [2021-12-15 17:21:35,388 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:21:35" (1/1) ... [2021-12-15 17:21:35,392 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:21:35" (1/1) ... [2021-12-15 17:21:35,398 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-12-15 17:21:35,399 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-12-15 17:21:35,399 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-12-15 17:21:35,399 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-12-15 17:21:35,400 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:21:35" (1/1) ... [2021-12-15 17:21:35,404 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-15 17:21:35,413 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-15 17:21:35,435 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-15 17:21:35,437 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2021-12-15 17:21:35,477 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2021-12-15 17:21:35,477 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2021-12-15 17:21:35,477 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-12-15 17:21:35,477 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-12-15 17:21:35,605 INFO L236 CfgBuilder]: Building ICFG [2021-12-15 17:21:35,606 INFO L262 CfgBuilder]: Building CFG for each procedure with an implementation [2021-12-15 17:21:36,547 INFO L277 CfgBuilder]: Performing block encoding [2021-12-15 17:21:36,557 INFO L296 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-12-15 17:21:36,557 INFO L301 CfgBuilder]: Removed 12 assume(true) statements. [2021-12-15 17:21:36,559 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 15.12 05:21:36 BoogieIcfgContainer [2021-12-15 17:21:36,559 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-12-15 17:21:36,559 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2021-12-15 17:21:36,560 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2021-12-15 17:21:36,562 INFO L275 PluginConnector]: BuchiAutomizer initialized [2021-12-15 17:21:36,596 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-15 17:21:36,596 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 15.12 05:21:34" (1/3) ... [2021-12-15 17:21:36,597 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@536f8940 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 15.12 05:21:36, skipping insertion in model container [2021-12-15 17:21:36,597 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-15 17:21:36,597 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:21:35" (2/3) ... [2021-12-15 17:21:36,598 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@536f8940 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 15.12 05:21:36, skipping insertion in model container [2021-12-15 17:21:36,598 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-15 17:21:36,598 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 15.12 05:21:36" (3/3) ... [2021-12-15 17:21:36,599 INFO L388 chiAutomizerObserver]: Analyzing ICFG transmitter.08.cil.c [2021-12-15 17:21:36,639 INFO L359 BuchiCegarLoop]: Interprodecural is true [2021-12-15 17:21:36,640 INFO L360 BuchiCegarLoop]: Hoare is false [2021-12-15 17:21:36,640 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2021-12-15 17:21:36,640 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2021-12-15 17:21:36,640 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2021-12-15 17:21:36,640 INFO L364 BuchiCegarLoop]: Difference is false [2021-12-15 17:21:36,640 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2021-12-15 17:21:36,640 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2021-12-15 17:21:36,669 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 931 states, 930 states have (on average 1.5182795698924731) internal successors, (1412), 930 states have internal predecessors, (1412), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:36,717 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 814 [2021-12-15 17:21:36,718 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:21:36,718 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:21:36,728 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:36,729 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:36,729 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2021-12-15 17:21:36,730 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 931 states, 930 states have (on average 1.5182795698924731) internal successors, (1412), 930 states have internal predecessors, (1412), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:36,737 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 814 [2021-12-15 17:21:36,738 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:21:36,738 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:21:36,741 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:36,741 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:36,747 INFO L791 eck$LassoCheckResult]: Stem: 422#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 841#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 848#L1235true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 47#L574true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 671#L581true assume !(1 == ~m_i~0);~m_st~0 := 2; 193#L581-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 808#L586-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 664#L591-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 637#L596-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 232#L601-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 672#L606-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 405#L611-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 752#L616-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 287#L621-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 697#L838true assume !(0 == ~M_E~0); 413#L838-2true assume !(0 == ~T1_E~0); 28#L843-1true assume !(0 == ~T2_E~0); 86#L848-1true assume !(0 == ~T3_E~0); 426#L853-1true assume !(0 == ~T4_E~0); 278#L858-1true assume 0 == ~T5_E~0;~T5_E~0 := 1; 3#L863-1true assume !(0 == ~T6_E~0); 745#L868-1true assume !(0 == ~T7_E~0); 864#L873-1true assume !(0 == ~T8_E~0); 740#L878-1true assume !(0 == ~E_1~0); 706#L883-1true assume !(0 == ~E_2~0); 778#L888-1true assume !(0 == ~E_3~0); 383#L893-1true assume !(0 == ~E_4~0); 779#L898-1true assume 0 == ~E_5~0;~E_5~0 := 1; 913#L903-1true assume !(0 == ~E_6~0); 704#L908-1true assume !(0 == ~E_7~0); 496#L913-1true assume !(0 == ~E_8~0); 34#L918-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 513#L402true assume !(1 == ~m_pc~0); 262#L402-2true is_master_triggered_~__retres1~0#1 := 0; 98#L413true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 920#L414true activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 236#L1035true assume !(0 != activate_threads_~tmp~1#1); 271#L1035-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 693#L421true assume 1 == ~t1_pc~0; 807#L422true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 883#L432true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 264#L433true activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 308#L1043true assume !(0 != activate_threads_~tmp___0~0#1); 767#L1043-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 896#L440true assume 1 == ~t2_pc~0; 21#L441true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 103#L451true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 865#L452true activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 816#L1051true assume !(0 != activate_threads_~tmp___1~0#1); 515#L1051-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 211#L459true assume !(1 == ~t3_pc~0); 686#L459-2true is_transmit3_triggered_~__retres1~3#1 := 0; 763#L470true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 446#L471true activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 94#L1059true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 921#L1059-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 100#L478true assume 1 == ~t4_pc~0; 387#L479true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 662#L489true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 809#L490true activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 196#L1067true assume !(0 != activate_threads_~tmp___3~0#1); 56#L1067-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 423#L497true assume !(1 == ~t5_pc~0); 354#L497-2true is_transmit5_triggered_~__retres1~5#1 := 0; 450#L508true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 245#L509true activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 768#L1075true assume !(0 != activate_threads_~tmp___4~0#1); 678#L1075-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 875#L516true assume 1 == ~t6_pc~0; 876#L517true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 404#L527true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 844#L528true activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 122#L1083true assume !(0 != activate_threads_~tmp___5~0#1); 462#L1083-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 400#L535true assume !(1 == ~t7_pc~0); 783#L535-2true is_transmit7_triggered_~__retres1~7#1 := 0; 461#L546true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 589#L547true activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 489#L1091true assume !(0 != activate_threads_~tmp___6~0#1); 482#L1091-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 673#L554true assume 1 == ~t8_pc~0; 430#L555true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 810#L565true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 535#L566true activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 171#L1099true assume !(0 != activate_threads_~tmp___7~0#1); 490#L1099-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9#L931true assume !(1 == ~M_E~0); 726#L931-2true assume 1 == ~T1_E~0;~T1_E~0 := 2; 805#L936-1true assume !(1 == ~T2_E~0); 891#L941-1true assume !(1 == ~T3_E~0); 272#L946-1true assume !(1 == ~T4_E~0); 689#L951-1true assume !(1 == ~T5_E~0); 131#L956-1true assume !(1 == ~T6_E~0); 877#L961-1true assume !(1 == ~T7_E~0); 384#L966-1true assume !(1 == ~T8_E~0); 484#L971-1true assume 1 == ~E_1~0;~E_1~0 := 2; 829#L976-1true assume !(1 == ~E_2~0); 455#L981-1true assume !(1 == ~E_3~0); 275#L986-1true assume !(1 == ~E_4~0); 148#L991-1true assume !(1 == ~E_5~0); 854#L996-1true assume !(1 == ~E_6~0); 757#L1001-1true assume !(1 == ~E_7~0); 421#L1006-1true assume !(1 == ~E_8~0); 690#L1011-1true assume { :end_inline_reset_delta_events } true; 39#L1272-2true [2021-12-15 17:21:36,749 INFO L793 eck$LassoCheckResult]: Loop: 39#L1272-2true assume !false; 417#L1273true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 40#L813true assume false; 424#L828true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 552#L574-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 642#L838-3true assume !(0 == ~M_E~0); 467#L838-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 789#L843-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 345#L848-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 385#L853-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 571#L858-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 444#L863-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 434#L868-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 453#L873-3true assume !(0 == ~T8_E~0); 160#L878-3true assume 0 == ~E_1~0;~E_1~0 := 1; 22#L883-3true assume 0 == ~E_2~0;~E_2~0 := 1; 657#L888-3true assume 0 == ~E_3~0;~E_3~0 := 1; 23#L893-3true assume 0 == ~E_4~0;~E_4~0 := 1; 289#L898-3true assume 0 == ~E_5~0;~E_5~0 := 1; 592#L903-3true assume 0 == ~E_6~0;~E_6~0 := 1; 777#L908-3true assume 0 == ~E_7~0;~E_7~0 := 1; 297#L913-3true assume !(0 == ~E_8~0); 43#L918-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 885#L402-27true assume 1 == ~m_pc~0; 17#L403-9true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 835#L413-9true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 292#L414-9true activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 732#L1035-27true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 623#L1035-29true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 659#L421-27true assume !(1 == ~t1_pc~0); 156#L421-29true is_transmit1_triggered_~__retres1~1#1 := 0; 815#L432-9true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 318#L433-9true activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 758#L1043-27true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 881#L1043-29true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 401#L440-27true assume 1 == ~t2_pc~0; 859#L441-9true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 929#L451-9true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 207#L452-9true activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 325#L1051-27true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 411#L1051-29true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 150#L459-27true assume 1 == ~t3_pc~0; 458#L460-9true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 831#L470-9true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 189#L471-9true activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 399#L1059-27true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 743#L1059-29true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 878#L478-27true assume !(1 == ~t4_pc~0); 143#L478-29true is_transmit4_triggered_~__retres1~4#1 := 0; 406#L489-9true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 886#L490-9true activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 541#L1067-27true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 744#L1067-29true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 593#L497-27true assume !(1 == ~t5_pc~0); 240#L497-29true is_transmit5_triggered_~__retres1~5#1 := 0; 165#L508-9true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 341#L509-9true activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 134#L1075-27true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 665#L1075-29true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 293#L516-27true assume 1 == ~t6_pc~0; 337#L517-9true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 200#L527-9true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 294#L528-9true activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 415#L1083-27true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 755#L1083-29true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 246#L535-27true assume !(1 == ~t7_pc~0); 521#L535-29true is_transmit7_triggered_~__retres1~7#1 := 0; 926#L546-9true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 554#L547-9true activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 825#L1091-27true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 220#L1091-29true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 766#L554-27true assume !(1 == ~t8_pc~0); 30#L554-29true is_transmit8_triggered_~__retres1~8#1 := 0; 102#L565-9true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 309#L566-9true activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 329#L1099-27true assume !(0 != activate_threads_~tmp___7~0#1); 158#L1099-29true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 517#L931-3true assume 1 == ~M_E~0;~M_E~0 := 2; 92#L931-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 218#L936-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 304#L941-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 519#L946-3true assume !(1 == ~T4_E~0); 169#L951-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 502#L956-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 364#L961-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 225#L966-3true assume 1 == ~T8_E~0;~T8_E~0 := 2; 710#L971-3true assume 1 == ~E_1~0;~E_1~0 := 2; 403#L976-3true assume 1 == ~E_2~0;~E_2~0 := 2; 38#L981-3true assume 1 == ~E_3~0;~E_3~0 := 2; 159#L986-3true assume !(1 == ~E_4~0); 33#L991-3true assume 1 == ~E_5~0;~E_5~0 := 2; 470#L996-3true assume 1 == ~E_6~0;~E_6~0 := 2; 596#L1001-3true assume 1 == ~E_7~0;~E_7~0 := 2; 213#L1006-3true assume 1 == ~E_8~0;~E_8~0 := 2; 504#L1011-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 54#L634-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 307#L681-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 228#L682-1true start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 773#L1291true assume !(0 == start_simulation_~tmp~3#1); 741#L1291-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 285#L634-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 5#L681-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 564#L682-2true stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 714#L1246true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 258#L1253true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 438#L1254true start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 542#L1304true assume !(0 != start_simulation_~tmp___0~1#1); 39#L1272-2true [2021-12-15 17:21:36,753 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:36,753 INFO L85 PathProgramCache]: Analyzing trace with hash -1897256038, now seen corresponding path program 1 times [2021-12-15 17:21:36,758 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:36,759 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1998700054] [2021-12-15 17:21:36,759 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:36,760 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:36,823 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:36,892 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:36,893 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:36,893 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1998700054] [2021-12-15 17:21:36,894 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1998700054] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:36,894 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:36,894 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:36,895 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [899288979] [2021-12-15 17:21:36,907 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:36,910 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:21:36,911 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:36,911 INFO L85 PathProgramCache]: Analyzing trace with hash -650170989, now seen corresponding path program 1 times [2021-12-15 17:21:36,911 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:36,911 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1746340093] [2021-12-15 17:21:36,911 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:36,912 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:36,919 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:36,950 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:36,950 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:36,963 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1746340093] [2021-12-15 17:21:36,963 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1746340093] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:36,964 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:36,964 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-15 17:21:36,964 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1117349828] [2021-12-15 17:21:36,964 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:36,965 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:21:36,966 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:21:37,013 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:21:37,013 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:21:37,016 INFO L87 Difference]: Start difference. First operand has 931 states, 930 states have (on average 1.5182795698924731) internal successors, (1412), 930 states have internal predecessors, (1412), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:37,158 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:21:37,159 INFO L93 Difference]: Finished difference Result 930 states and 1385 transitions. [2021-12-15 17:21:37,160 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:21:37,163 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 930 states and 1385 transitions. [2021-12-15 17:21:37,170 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 811 [2021-12-15 17:21:37,176 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 930 states to 924 states and 1379 transitions. [2021-12-15 17:21:37,180 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 924 [2021-12-15 17:21:37,181 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 924 [2021-12-15 17:21:37,182 INFO L73 IsDeterministic]: Start isDeterministic. Operand 924 states and 1379 transitions. [2021-12-15 17:21:37,186 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:21:37,188 INFO L681 BuchiCegarLoop]: Abstraction has 924 states and 1379 transitions. [2021-12-15 17:21:37,200 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 924 states and 1379 transitions. [2021-12-15 17:21:37,231 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 924 to 924. [2021-12-15 17:21:37,233 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 924 states, 924 states have (on average 1.4924242424242424) internal successors, (1379), 923 states have internal predecessors, (1379), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:37,235 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 924 states to 924 states and 1379 transitions. [2021-12-15 17:21:37,236 INFO L704 BuchiCegarLoop]: Abstraction has 924 states and 1379 transitions. [2021-12-15 17:21:37,236 INFO L587 BuchiCegarLoop]: Abstraction has 924 states and 1379 transitions. [2021-12-15 17:21:37,236 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2021-12-15 17:21:37,236 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 924 states and 1379 transitions. [2021-12-15 17:21:37,240 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 811 [2021-12-15 17:21:37,241 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:21:37,241 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:21:37,243 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:37,245 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:37,246 INFO L791 eck$LassoCheckResult]: Stem: 2546#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 2547#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 2789#L1235 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1961#L574 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1962#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 2233#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2234#L586-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 2731#L591-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2721#L596-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2301#L601-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 2302#L606-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 2526#L611-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 2527#L616-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 2383#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2384#L838 assume !(0 == ~M_E~0); 2533#L838-2 assume !(0 == ~T1_E~0); 1923#L843-1 assume !(0 == ~T2_E~0); 1924#L848-1 assume !(0 == ~T3_E~0); 2043#L853-1 assume !(0 == ~T4_E~0); 2369#L858-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1870#L863-1 assume !(0 == ~T6_E~0); 1871#L868-1 assume !(0 == ~T7_E~0); 2763#L873-1 assume !(0 == ~T8_E~0); 2761#L878-1 assume !(0 == ~E_1~0); 2750#L883-1 assume !(0 == ~E_2~0); 2751#L888-1 assume !(0 == ~E_3~0); 2498#L893-1 assume !(0 == ~E_4~0); 2499#L898-1 assume 0 == ~E_5~0;~E_5~0 := 1; 2775#L903-1 assume !(0 == ~E_6~0); 2749#L908-1 assume !(0 == ~E_7~0); 2623#L913-1 assume !(0 == ~E_8~0); 1937#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1938#L402 assume !(1 == ~m_pc~0); 2146#L402-2 is_master_triggered_~__retres1~0#1 := 0; 2064#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2065#L414 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2307#L1035 assume !(0 != activate_threads_~tmp~1#1); 2308#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2360#L421 assume 1 == ~t1_pc~0; 2745#L422 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2764#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2352#L433 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2353#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 2411#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2772#L440 assume 1 == ~t2_pc~0; 1907#L441 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1908#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2074#L452 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2783#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 2637#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2261#L459 assume !(1 == ~t3_pc~0); 2262#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2744#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2568#L471 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2058#L1059 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2059#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2068#L478 assume 1 == ~t4_pc~0; 2069#L479 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2503#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2730#L490 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2239#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 1982#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1983#L497 assume !(1 == ~t5_pc~0); 2029#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 2030#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2321#L509 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2322#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 2737#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2738#L516 assume 1 == ~t6_pc~0; 2792#L517 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 2524#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2525#L528 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2113#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 2114#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2515#L535 assume !(1 == ~t7_pc~0); 2516#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 2585#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2586#L547 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2614#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 2604#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2605#L554 assume 1 == ~t8_pc~0; 2554#L555 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 1899#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2655#L566 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2201#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 2202#L1099-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1883#L931 assume !(1 == ~M_E~0); 1884#L931-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2758#L936-1 assume !(1 == ~T2_E~0); 2781#L941-1 assume !(1 == ~T3_E~0); 2361#L946-1 assume !(1 == ~T4_E~0); 2362#L951-1 assume !(1 == ~T5_E~0); 2128#L956-1 assume !(1 == ~T6_E~0); 2129#L961-1 assume !(1 == ~T7_E~0); 2500#L966-1 assume !(1 == ~T8_E~0); 2501#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 2607#L976-1 assume !(1 == ~E_2~0); 2577#L981-1 assume !(1 == ~E_3~0); 2366#L986-1 assume !(1 == ~E_4~0); 2158#L991-1 assume !(1 == ~E_5~0); 2159#L996-1 assume !(1 == ~E_6~0); 2768#L1001-1 assume !(1 == ~E_7~0); 2544#L1006-1 assume !(1 == ~E_8~0); 2545#L1011-1 assume { :end_inline_reset_delta_events } true; 1946#L1272-2 [2021-12-15 17:21:37,247 INFO L793 eck$LassoCheckResult]: Loop: 1946#L1272-2 assume !false; 1947#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1948#L813 assume !false; 1949#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 2695#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1951#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 2495#L682 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 2505#L696 assume !(0 != eval_~tmp~0#1); 2548#L828 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2549#L574-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2670#L838-3 assume !(0 == ~M_E~0); 2590#L838-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2591#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2453#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2454#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2502#L858-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2565#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2557#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 2558#L873-3 assume !(0 == ~T8_E~0); 2181#L878-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1910#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1911#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1912#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1913#L898-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2387#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 2696#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 2400#L913-3 assume !(0 == ~E_8~0); 1953#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1954#L402-27 assume 1 == ~m_pc~0; 1900#L403-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1901#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2390#L414-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2391#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2709#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2710#L421-27 assume !(1 == ~t1_pc~0); 2173#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 2174#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2423#L433-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2424#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2769#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2518#L440-27 assume 1 == ~t2_pc~0; 2519#L441-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2692#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2257#L452-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2258#L1051-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2432#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2161#L459-27 assume !(1 == ~t3_pc~0); 2162#L459-29 is_transmit3_triggered_~__retres1~3#1 := 0; 2580#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2225#L471-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2226#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2514#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2762#L478-27 assume 1 == ~t4_pc~0; 2784#L479-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2152#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2528#L490-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2660#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2661#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2697#L497-27 assume 1 == ~t5_pc~0; 2698#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2190#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2191#L509-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2134#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2135#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2392#L516-27 assume 1 == ~t6_pc~0; 2393#L517-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 2247#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2248#L528-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2395#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 2535#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2324#L535-27 assume 1 == ~t7_pc~0; 2325#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 2641#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2671#L547-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2672#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 2278#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2279#L554-27 assume !(1 == ~t8_pc~0); 1927#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 1928#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2073#L566-9 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2412#L1099-27 assume !(0 != activate_threads_~tmp___7~0#1); 2178#L1099-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2179#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2054#L931-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2055#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2275#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2407#L946-3 assume !(1 == ~T4_E~0); 2196#L951-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2197#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2476#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 2285#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 2286#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2523#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1944#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1945#L986-3 assume !(1 == ~E_4~0); 1935#L991-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1936#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2595#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 2266#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 2267#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1977#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1979#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 2293#L682-1 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 2294#L1291 assume !(0 == start_simulation_~tmp~3#1); 2473#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 2379#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1874#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1875#L682-2 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 2679#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2343#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2344#L1254 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 2560#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 1946#L1272-2 [2021-12-15 17:21:37,249 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:37,250 INFO L85 PathProgramCache]: Analyzing trace with hash 500214492, now seen corresponding path program 1 times [2021-12-15 17:21:37,250 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:37,251 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1218226442] [2021-12-15 17:21:37,251 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:37,251 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:37,264 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:37,334 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:37,335 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:37,336 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1218226442] [2021-12-15 17:21:37,336 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1218226442] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:37,336 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:37,336 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:37,352 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1425078050] [2021-12-15 17:21:37,352 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:37,352 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:21:37,354 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:37,354 INFO L85 PathProgramCache]: Analyzing trace with hash 1268138686, now seen corresponding path program 1 times [2021-12-15 17:21:37,354 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:37,355 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2049863608] [2021-12-15 17:21:37,355 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:37,355 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:37,426 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:37,518 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:37,519 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:37,519 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2049863608] [2021-12-15 17:21:37,519 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2049863608] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:37,520 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:37,520 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:37,520 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [114089860] [2021-12-15 17:21:37,521 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:37,521 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:21:37,522 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:21:37,522 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:21:37,522 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:21:37,522 INFO L87 Difference]: Start difference. First operand 924 states and 1379 transitions. cyclomatic complexity: 456 Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:37,553 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:21:37,554 INFO L93 Difference]: Finished difference Result 924 states and 1378 transitions. [2021-12-15 17:21:37,554 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:21:37,555 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 924 states and 1378 transitions. [2021-12-15 17:21:37,560 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 811 [2021-12-15 17:21:37,564 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 924 states to 924 states and 1378 transitions. [2021-12-15 17:21:37,564 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 924 [2021-12-15 17:21:37,564 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 924 [2021-12-15 17:21:37,565 INFO L73 IsDeterministic]: Start isDeterministic. Operand 924 states and 1378 transitions. [2021-12-15 17:21:37,567 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:21:37,568 INFO L681 BuchiCegarLoop]: Abstraction has 924 states and 1378 transitions. [2021-12-15 17:21:37,569 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 924 states and 1378 transitions. [2021-12-15 17:21:37,580 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 924 to 924. [2021-12-15 17:21:37,581 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 924 states, 924 states have (on average 1.4913419913419914) internal successors, (1378), 923 states have internal predecessors, (1378), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:37,583 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 924 states to 924 states and 1378 transitions. [2021-12-15 17:21:37,583 INFO L704 BuchiCegarLoop]: Abstraction has 924 states and 1378 transitions. [2021-12-15 17:21:37,584 INFO L587 BuchiCegarLoop]: Abstraction has 924 states and 1378 transitions. [2021-12-15 17:21:37,584 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2021-12-15 17:21:37,584 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 924 states and 1378 transitions. [2021-12-15 17:21:37,588 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 811 [2021-12-15 17:21:37,588 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:21:37,588 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:21:37,592 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:37,592 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:37,593 INFO L791 eck$LassoCheckResult]: Stem: 4401#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 4402#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 4644#L1235 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3816#L574 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3817#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 4088#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4089#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4586#L591-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 4576#L596-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 4156#L601-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 4157#L606-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 4381#L611-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 4382#L616-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 4238#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4239#L838 assume !(0 == ~M_E~0); 4388#L838-2 assume !(0 == ~T1_E~0); 3778#L843-1 assume !(0 == ~T2_E~0); 3779#L848-1 assume !(0 == ~T3_E~0); 3898#L853-1 assume !(0 == ~T4_E~0); 4224#L858-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3725#L863-1 assume !(0 == ~T6_E~0); 3726#L868-1 assume !(0 == ~T7_E~0); 4618#L873-1 assume !(0 == ~T8_E~0); 4616#L878-1 assume !(0 == ~E_1~0); 4605#L883-1 assume !(0 == ~E_2~0); 4606#L888-1 assume !(0 == ~E_3~0); 4353#L893-1 assume !(0 == ~E_4~0); 4354#L898-1 assume 0 == ~E_5~0;~E_5~0 := 1; 4630#L903-1 assume !(0 == ~E_6~0); 4604#L908-1 assume !(0 == ~E_7~0); 4478#L913-1 assume !(0 == ~E_8~0); 3792#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3793#L402 assume !(1 == ~m_pc~0); 4001#L402-2 is_master_triggered_~__retres1~0#1 := 0; 3919#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3920#L414 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4162#L1035 assume !(0 != activate_threads_~tmp~1#1); 4163#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4215#L421 assume 1 == ~t1_pc~0; 4600#L422 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4619#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4207#L433 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4208#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 4266#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4627#L440 assume 1 == ~t2_pc~0; 3762#L441 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3763#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3929#L452 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4638#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 4492#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4116#L459 assume !(1 == ~t3_pc~0); 4117#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 4599#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4423#L471 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3913#L1059 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3914#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3923#L478 assume 1 == ~t4_pc~0; 3924#L479 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4358#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4585#L490 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4094#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 3837#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3838#L497 assume !(1 == ~t5_pc~0); 3884#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 3885#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4176#L509 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4177#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 4592#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4593#L516 assume 1 == ~t6_pc~0; 4647#L517 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4379#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4380#L528 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3968#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 3969#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4370#L535 assume !(1 == ~t7_pc~0); 4371#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 4440#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4441#L547 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4469#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 4459#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4460#L554 assume 1 == ~t8_pc~0; 4409#L555 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 3754#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4510#L566 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4056#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 4057#L1099-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3738#L931 assume !(1 == ~M_E~0); 3739#L931-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4613#L936-1 assume !(1 == ~T2_E~0); 4636#L941-1 assume !(1 == ~T3_E~0); 4216#L946-1 assume !(1 == ~T4_E~0); 4217#L951-1 assume !(1 == ~T5_E~0); 3983#L956-1 assume !(1 == ~T6_E~0); 3984#L961-1 assume !(1 == ~T7_E~0); 4355#L966-1 assume !(1 == ~T8_E~0); 4356#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 4462#L976-1 assume !(1 == ~E_2~0); 4432#L981-1 assume !(1 == ~E_3~0); 4221#L986-1 assume !(1 == ~E_4~0); 4013#L991-1 assume !(1 == ~E_5~0); 4014#L996-1 assume !(1 == ~E_6~0); 4623#L1001-1 assume !(1 == ~E_7~0); 4399#L1006-1 assume !(1 == ~E_8~0); 4400#L1011-1 assume { :end_inline_reset_delta_events } true; 3801#L1272-2 [2021-12-15 17:21:37,594 INFO L793 eck$LassoCheckResult]: Loop: 3801#L1272-2 assume !false; 3802#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3803#L813 assume !false; 3804#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 4550#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 3806#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 4350#L682 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 4360#L696 assume !(0 != eval_~tmp~0#1); 4403#L828 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4404#L574-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4525#L838-3 assume !(0 == ~M_E~0); 4445#L838-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4446#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4308#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4309#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4357#L858-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4420#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4412#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 4413#L873-3 assume !(0 == ~T8_E~0); 4036#L878-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3765#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3766#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3767#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3768#L898-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4242#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 4551#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 4255#L913-3 assume !(0 == ~E_8~0); 3808#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3809#L402-27 assume 1 == ~m_pc~0; 3755#L403-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 3756#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4245#L414-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4246#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4564#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4565#L421-27 assume !(1 == ~t1_pc~0); 4028#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 4029#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4278#L433-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4279#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4624#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4373#L440-27 assume 1 == ~t2_pc~0; 4374#L441-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4547#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4112#L452-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4113#L1051-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4287#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4016#L459-27 assume !(1 == ~t3_pc~0); 4017#L459-29 is_transmit3_triggered_~__retres1~3#1 := 0; 4435#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4080#L471-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4081#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4369#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4617#L478-27 assume !(1 == ~t4_pc~0); 4006#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 4007#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4383#L490-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4515#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4516#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4552#L497-27 assume 1 == ~t5_pc~0; 4553#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 4045#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4046#L509-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3989#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 3990#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4247#L516-27 assume 1 == ~t6_pc~0; 4248#L517-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4102#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4103#L528-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4250#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 4390#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4179#L535-27 assume 1 == ~t7_pc~0; 4180#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 4496#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4526#L547-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4527#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 4133#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4134#L554-27 assume !(1 == ~t8_pc~0); 3782#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 3783#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3928#L566-9 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4267#L1099-27 assume !(0 != activate_threads_~tmp___7~0#1); 4033#L1099-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4034#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3909#L931-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3910#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4130#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4262#L946-3 assume !(1 == ~T4_E~0); 4051#L951-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4052#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 4331#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 4140#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 4141#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4378#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3799#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3800#L986-3 assume !(1 == ~E_4~0); 3790#L991-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3791#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 4450#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 4121#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 4122#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 3832#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 3834#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 4148#L682-1 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 4149#L1291 assume !(0 == start_simulation_~tmp~3#1); 4328#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 4234#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 3729#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 3730#L682-2 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 4534#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4198#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4199#L1254 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 4415#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 3801#L1272-2 [2021-12-15 17:21:37,596 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:37,596 INFO L85 PathProgramCache]: Analyzing trace with hash -1888349538, now seen corresponding path program 1 times [2021-12-15 17:21:37,597 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:37,597 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [997474644] [2021-12-15 17:21:37,597 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:37,598 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:37,623 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:37,651 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:37,652 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:37,652 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [997474644] [2021-12-15 17:21:37,652 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [997474644] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:37,652 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:37,652 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:37,653 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1257386864] [2021-12-15 17:21:37,653 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:37,653 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:21:37,654 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:37,655 INFO L85 PathProgramCache]: Analyzing trace with hash -638345507, now seen corresponding path program 1 times [2021-12-15 17:21:37,655 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:37,655 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1998278343] [2021-12-15 17:21:37,656 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:37,656 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:37,669 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:37,710 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:37,710 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:37,711 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1998278343] [2021-12-15 17:21:37,711 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1998278343] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:37,711 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:37,711 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:37,712 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [588164395] [2021-12-15 17:21:37,712 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:37,712 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:21:37,712 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:21:37,713 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:21:37,713 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:21:37,713 INFO L87 Difference]: Start difference. First operand 924 states and 1378 transitions. cyclomatic complexity: 455 Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:37,727 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:21:37,728 INFO L93 Difference]: Finished difference Result 924 states and 1377 transitions. [2021-12-15 17:21:37,728 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:21:37,729 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 924 states and 1377 transitions. [2021-12-15 17:21:37,734 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 811 [2021-12-15 17:21:37,737 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 924 states to 924 states and 1377 transitions. [2021-12-15 17:21:37,737 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 924 [2021-12-15 17:21:37,738 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 924 [2021-12-15 17:21:37,738 INFO L73 IsDeterministic]: Start isDeterministic. Operand 924 states and 1377 transitions. [2021-12-15 17:21:37,739 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:21:37,739 INFO L681 BuchiCegarLoop]: Abstraction has 924 states and 1377 transitions. [2021-12-15 17:21:37,740 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 924 states and 1377 transitions. [2021-12-15 17:21:37,747 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 924 to 924. [2021-12-15 17:21:37,748 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 924 states, 924 states have (on average 1.4902597402597402) internal successors, (1377), 923 states have internal predecessors, (1377), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:37,750 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 924 states to 924 states and 1377 transitions. [2021-12-15 17:21:37,750 INFO L704 BuchiCegarLoop]: Abstraction has 924 states and 1377 transitions. [2021-12-15 17:21:37,750 INFO L587 BuchiCegarLoop]: Abstraction has 924 states and 1377 transitions. [2021-12-15 17:21:37,750 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2021-12-15 17:21:37,750 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 924 states and 1377 transitions. [2021-12-15 17:21:37,753 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 811 [2021-12-15 17:21:37,753 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:21:37,753 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:21:37,777 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:37,777 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:37,778 INFO L791 eck$LassoCheckResult]: Stem: 6256#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 6257#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 6499#L1235 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5671#L574 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5672#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 5943#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5944#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6441#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 6431#L596-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 6011#L601-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 6012#L606-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 6236#L611-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 6237#L616-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 6093#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6094#L838 assume !(0 == ~M_E~0); 6243#L838-2 assume !(0 == ~T1_E~0); 5633#L843-1 assume !(0 == ~T2_E~0); 5634#L848-1 assume !(0 == ~T3_E~0); 5753#L853-1 assume !(0 == ~T4_E~0); 6079#L858-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5580#L863-1 assume !(0 == ~T6_E~0); 5581#L868-1 assume !(0 == ~T7_E~0); 6473#L873-1 assume !(0 == ~T8_E~0); 6471#L878-1 assume !(0 == ~E_1~0); 6460#L883-1 assume !(0 == ~E_2~0); 6461#L888-1 assume !(0 == ~E_3~0); 6208#L893-1 assume !(0 == ~E_4~0); 6209#L898-1 assume 0 == ~E_5~0;~E_5~0 := 1; 6485#L903-1 assume !(0 == ~E_6~0); 6459#L908-1 assume !(0 == ~E_7~0); 6333#L913-1 assume !(0 == ~E_8~0); 5647#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5648#L402 assume !(1 == ~m_pc~0); 5856#L402-2 is_master_triggered_~__retres1~0#1 := 0; 5774#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5775#L414 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 6017#L1035 assume !(0 != activate_threads_~tmp~1#1); 6018#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6070#L421 assume 1 == ~t1_pc~0; 6455#L422 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 6474#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6062#L433 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 6063#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 6121#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6482#L440 assume 1 == ~t2_pc~0; 5617#L441 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5618#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5784#L452 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6493#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 6347#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5971#L459 assume !(1 == ~t3_pc~0); 5972#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 6454#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6278#L471 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5768#L1059 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5769#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5778#L478 assume 1 == ~t4_pc~0; 5779#L479 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 6213#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6440#L490 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5949#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 5692#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5693#L497 assume !(1 == ~t5_pc~0); 5739#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 5740#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6031#L509 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 6032#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 6447#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6448#L516 assume 1 == ~t6_pc~0; 6502#L517 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 6234#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6235#L528 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5823#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 5824#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6225#L535 assume !(1 == ~t7_pc~0); 6226#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 6295#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 6296#L547 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 6324#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 6314#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 6315#L554 assume 1 == ~t8_pc~0; 6264#L555 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 5609#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 6365#L566 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5911#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 5912#L1099-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5593#L931 assume !(1 == ~M_E~0); 5594#L931-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 6468#L936-1 assume !(1 == ~T2_E~0); 6491#L941-1 assume !(1 == ~T3_E~0); 6071#L946-1 assume !(1 == ~T4_E~0); 6072#L951-1 assume !(1 == ~T5_E~0); 5838#L956-1 assume !(1 == ~T6_E~0); 5839#L961-1 assume !(1 == ~T7_E~0); 6210#L966-1 assume !(1 == ~T8_E~0); 6211#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 6317#L976-1 assume !(1 == ~E_2~0); 6287#L981-1 assume !(1 == ~E_3~0); 6076#L986-1 assume !(1 == ~E_4~0); 5868#L991-1 assume !(1 == ~E_5~0); 5869#L996-1 assume !(1 == ~E_6~0); 6478#L1001-1 assume !(1 == ~E_7~0); 6254#L1006-1 assume !(1 == ~E_8~0); 6255#L1011-1 assume { :end_inline_reset_delta_events } true; 5656#L1272-2 [2021-12-15 17:21:37,778 INFO L793 eck$LassoCheckResult]: Loop: 5656#L1272-2 assume !false; 5657#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5658#L813 assume !false; 5659#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 6405#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 5661#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 6205#L682 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 6215#L696 assume !(0 != eval_~tmp~0#1); 6258#L828 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 6259#L574-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 6380#L838-3 assume !(0 == ~M_E~0); 6300#L838-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 6301#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 6163#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 6164#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 6212#L858-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 6275#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 6267#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 6268#L873-3 assume !(0 == ~T8_E~0); 5891#L878-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5620#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5621#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5622#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 5623#L898-3 assume 0 == ~E_5~0;~E_5~0 := 1; 6097#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 6406#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 6110#L913-3 assume !(0 == ~E_8~0); 5663#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5664#L402-27 assume 1 == ~m_pc~0; 5610#L403-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 5611#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6100#L414-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 6101#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 6419#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6420#L421-27 assume !(1 == ~t1_pc~0); 5883#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 5884#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6133#L433-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 6134#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 6479#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6228#L440-27 assume 1 == ~t2_pc~0; 6229#L441-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 6402#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5967#L452-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5968#L1051-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 6142#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5871#L459-27 assume !(1 == ~t3_pc~0); 5872#L459-29 is_transmit3_triggered_~__retres1~3#1 := 0; 6290#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5935#L471-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5936#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 6224#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6472#L478-27 assume !(1 == ~t4_pc~0); 5861#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 5862#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6238#L490-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6370#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 6371#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6407#L497-27 assume 1 == ~t5_pc~0; 6408#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5900#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5901#L509-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5844#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 5845#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6102#L516-27 assume 1 == ~t6_pc~0; 6103#L517-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 5957#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5958#L528-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 6105#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 6245#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6034#L535-27 assume 1 == ~t7_pc~0; 6035#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 6351#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 6381#L547-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 6382#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 5988#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 5989#L554-27 assume !(1 == ~t8_pc~0); 5637#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 5638#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 5783#L566-9 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 6122#L1099-27 assume !(0 != activate_threads_~tmp___7~0#1); 5888#L1099-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5889#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 5764#L931-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5765#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5985#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 6117#L946-3 assume !(1 == ~T4_E~0); 5906#L951-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5907#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 6186#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 5995#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 5996#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 6233#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5654#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5655#L986-3 assume !(1 == ~E_4~0); 5645#L991-3 assume 1 == ~E_5~0;~E_5~0 := 2; 5646#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 6305#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 5976#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 5977#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 5687#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 5689#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 6003#L682-1 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 6004#L1291 assume !(0 == start_simulation_~tmp~3#1); 6183#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 6089#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 5584#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 5585#L682-2 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 6389#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 6053#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6054#L1254 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 6270#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 5656#L1272-2 [2021-12-15 17:21:37,779 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:37,779 INFO L85 PathProgramCache]: Analyzing trace with hash 805546652, now seen corresponding path program 1 times [2021-12-15 17:21:37,779 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:37,779 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1271762439] [2021-12-15 17:21:37,780 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:37,780 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:37,794 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:37,815 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:37,815 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:37,815 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1271762439] [2021-12-15 17:21:37,816 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1271762439] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:37,816 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:37,816 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:37,818 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1721985377] [2021-12-15 17:21:37,819 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:37,819 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:21:37,819 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:37,819 INFO L85 PathProgramCache]: Analyzing trace with hash -638345507, now seen corresponding path program 2 times [2021-12-15 17:21:37,820 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:37,822 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1956148386] [2021-12-15 17:21:37,823 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:37,823 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:37,837 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:37,869 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:37,870 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:37,870 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1956148386] [2021-12-15 17:21:37,870 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1956148386] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:37,870 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:37,870 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:37,871 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1181544681] [2021-12-15 17:21:37,871 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:37,871 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:21:37,871 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:21:37,872 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:21:37,872 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:21:37,873 INFO L87 Difference]: Start difference. First operand 924 states and 1377 transitions. cyclomatic complexity: 454 Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:37,884 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:21:37,884 INFO L93 Difference]: Finished difference Result 924 states and 1376 transitions. [2021-12-15 17:21:37,884 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:21:37,885 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 924 states and 1376 transitions. [2021-12-15 17:21:37,888 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 811 [2021-12-15 17:21:37,891 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 924 states to 924 states and 1376 transitions. [2021-12-15 17:21:37,892 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 924 [2021-12-15 17:21:37,892 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 924 [2021-12-15 17:21:37,892 INFO L73 IsDeterministic]: Start isDeterministic. Operand 924 states and 1376 transitions. [2021-12-15 17:21:37,893 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:21:37,893 INFO L681 BuchiCegarLoop]: Abstraction has 924 states and 1376 transitions. [2021-12-15 17:21:37,895 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 924 states and 1376 transitions. [2021-12-15 17:21:37,901 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 924 to 924. [2021-12-15 17:21:37,902 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 924 states, 924 states have (on average 1.4891774891774892) internal successors, (1376), 923 states have internal predecessors, (1376), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:37,904 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 924 states to 924 states and 1376 transitions. [2021-12-15 17:21:37,904 INFO L704 BuchiCegarLoop]: Abstraction has 924 states and 1376 transitions. [2021-12-15 17:21:37,904 INFO L587 BuchiCegarLoop]: Abstraction has 924 states and 1376 transitions. [2021-12-15 17:21:37,904 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2021-12-15 17:21:37,905 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 924 states and 1376 transitions. [2021-12-15 17:21:37,907 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 811 [2021-12-15 17:21:37,908 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:21:37,908 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:21:37,909 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:37,909 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:37,909 INFO L791 eck$LassoCheckResult]: Stem: 8111#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 8112#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 8354#L1235 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7526#L574 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7527#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 7798#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7799#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8296#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 8286#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 7866#L601-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 7867#L606-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 8091#L611-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 8092#L616-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 7948#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7949#L838 assume !(0 == ~M_E~0); 8098#L838-2 assume !(0 == ~T1_E~0); 7488#L843-1 assume !(0 == ~T2_E~0); 7489#L848-1 assume !(0 == ~T3_E~0); 7608#L853-1 assume !(0 == ~T4_E~0); 7934#L858-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 7435#L863-1 assume !(0 == ~T6_E~0); 7436#L868-1 assume !(0 == ~T7_E~0); 8328#L873-1 assume !(0 == ~T8_E~0); 8326#L878-1 assume !(0 == ~E_1~0); 8315#L883-1 assume !(0 == ~E_2~0); 8316#L888-1 assume !(0 == ~E_3~0); 8063#L893-1 assume !(0 == ~E_4~0); 8064#L898-1 assume 0 == ~E_5~0;~E_5~0 := 1; 8340#L903-1 assume !(0 == ~E_6~0); 8314#L908-1 assume !(0 == ~E_7~0); 8188#L913-1 assume !(0 == ~E_8~0); 7502#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7503#L402 assume !(1 == ~m_pc~0); 7711#L402-2 is_master_triggered_~__retres1~0#1 := 0; 7629#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7630#L414 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 7872#L1035 assume !(0 != activate_threads_~tmp~1#1); 7873#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7925#L421 assume 1 == ~t1_pc~0; 8310#L422 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8329#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7917#L433 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 7918#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 7976#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8337#L440 assume 1 == ~t2_pc~0; 7472#L441 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 7473#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7639#L452 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8348#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 8202#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7826#L459 assume !(1 == ~t3_pc~0); 7827#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 8309#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8133#L471 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7623#L1059 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 7624#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7633#L478 assume 1 == ~t4_pc~0; 7634#L479 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 8068#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8295#L490 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 7804#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 7547#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7548#L497 assume !(1 == ~t5_pc~0); 7594#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 7595#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7886#L509 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7887#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 8302#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8303#L516 assume 1 == ~t6_pc~0; 8357#L517 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 8089#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8090#L528 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7678#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 7679#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8080#L535 assume !(1 == ~t7_pc~0); 8081#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 8150#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8151#L547 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8179#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 8169#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 8170#L554 assume 1 == ~t8_pc~0; 8119#L555 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 7464#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 8220#L566 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 7766#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 7767#L1099-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7448#L931 assume !(1 == ~M_E~0); 7449#L931-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8323#L936-1 assume !(1 == ~T2_E~0); 8346#L941-1 assume !(1 == ~T3_E~0); 7926#L946-1 assume !(1 == ~T4_E~0); 7927#L951-1 assume !(1 == ~T5_E~0); 7693#L956-1 assume !(1 == ~T6_E~0); 7694#L961-1 assume !(1 == ~T7_E~0); 8065#L966-1 assume !(1 == ~T8_E~0); 8066#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 8172#L976-1 assume !(1 == ~E_2~0); 8142#L981-1 assume !(1 == ~E_3~0); 7931#L986-1 assume !(1 == ~E_4~0); 7723#L991-1 assume !(1 == ~E_5~0); 7724#L996-1 assume !(1 == ~E_6~0); 8333#L1001-1 assume !(1 == ~E_7~0); 8109#L1006-1 assume !(1 == ~E_8~0); 8110#L1011-1 assume { :end_inline_reset_delta_events } true; 7511#L1272-2 [2021-12-15 17:21:37,909 INFO L793 eck$LassoCheckResult]: Loop: 7511#L1272-2 assume !false; 7512#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7513#L813 assume !false; 7514#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 8260#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 7516#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 8060#L682 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 8070#L696 assume !(0 != eval_~tmp~0#1); 8113#L828 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8114#L574-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8235#L838-3 assume !(0 == ~M_E~0); 8155#L838-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 8156#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 8018#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8019#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 8067#L858-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 8130#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 8122#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 8123#L873-3 assume !(0 == ~T8_E~0); 7746#L878-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7475#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 7476#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 7477#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 7478#L898-3 assume 0 == ~E_5~0;~E_5~0 := 1; 7952#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 8261#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 7965#L913-3 assume !(0 == ~E_8~0); 7518#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7519#L402-27 assume 1 == ~m_pc~0; 7465#L403-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 7466#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7955#L414-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 7956#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8274#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8275#L421-27 assume !(1 == ~t1_pc~0); 7738#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 7739#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7988#L433-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 7989#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8334#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8083#L440-27 assume 1 == ~t2_pc~0; 8084#L441-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 8257#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7822#L452-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 7823#L1051-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 7997#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7726#L459-27 assume 1 == ~t3_pc~0; 7728#L460-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 8145#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7790#L471-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7791#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 8079#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8327#L478-27 assume !(1 == ~t4_pc~0); 7716#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 7717#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8093#L490-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8225#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 8226#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8262#L497-27 assume 1 == ~t5_pc~0; 8263#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 7755#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7756#L509-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7699#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 7700#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7957#L516-27 assume 1 == ~t6_pc~0; 7958#L517-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 7812#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7813#L528-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7960#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 8100#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 7889#L535-27 assume 1 == ~t7_pc~0; 7890#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 8206#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8236#L547-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8237#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 7843#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 7844#L554-27 assume !(1 == ~t8_pc~0); 7492#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 7493#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 7638#L566-9 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 7977#L1099-27 assume !(0 != activate_threads_~tmp___7~0#1); 7743#L1099-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7744#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 7619#L931-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7620#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7840#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7972#L946-3 assume !(1 == ~T4_E~0); 7761#L951-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 7762#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 8041#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 7850#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 7851#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 8088#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 7509#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 7510#L986-3 assume !(1 == ~E_4~0); 7500#L991-3 assume 1 == ~E_5~0;~E_5~0 := 2; 7501#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 8160#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 7831#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 7832#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 7542#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 7544#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 7858#L682-1 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 7859#L1291 assume !(0 == start_simulation_~tmp~3#1); 8038#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 7944#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 7439#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 7440#L682-2 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 8244#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 7908#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 7909#L1254 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 8125#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 7511#L1272-2 [2021-12-15 17:21:37,910 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:37,910 INFO L85 PathProgramCache]: Analyzing trace with hash 1862277854, now seen corresponding path program 1 times [2021-12-15 17:21:37,910 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:37,910 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1531192964] [2021-12-15 17:21:37,910 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:37,910 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:37,922 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:37,940 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:37,940 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:37,940 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1531192964] [2021-12-15 17:21:37,940 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1531192964] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:37,941 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:37,941 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:37,941 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [48921742] [2021-12-15 17:21:37,941 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:37,941 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:21:37,941 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:37,942 INFO L85 PathProgramCache]: Analyzing trace with hash 539629054, now seen corresponding path program 1 times [2021-12-15 17:21:37,942 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:37,942 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [339925498] [2021-12-15 17:21:37,942 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:37,942 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:37,950 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:37,966 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:37,966 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:37,966 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [339925498] [2021-12-15 17:21:37,967 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [339925498] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:37,967 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:37,967 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:37,967 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1926902663] [2021-12-15 17:21:37,967 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:37,967 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:21:37,968 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:21:37,968 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:21:37,968 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:21:37,968 INFO L87 Difference]: Start difference. First operand 924 states and 1376 transitions. cyclomatic complexity: 453 Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:37,980 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:21:37,980 INFO L93 Difference]: Finished difference Result 924 states and 1375 transitions. [2021-12-15 17:21:37,980 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:21:37,982 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 924 states and 1375 transitions. [2021-12-15 17:21:37,986 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 811 [2021-12-15 17:21:37,990 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 924 states to 924 states and 1375 transitions. [2021-12-15 17:21:37,990 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 924 [2021-12-15 17:21:37,990 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 924 [2021-12-15 17:21:37,991 INFO L73 IsDeterministic]: Start isDeterministic. Operand 924 states and 1375 transitions. [2021-12-15 17:21:37,991 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:21:37,992 INFO L681 BuchiCegarLoop]: Abstraction has 924 states and 1375 transitions. [2021-12-15 17:21:37,992 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 924 states and 1375 transitions. [2021-12-15 17:21:37,999 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 924 to 924. [2021-12-15 17:21:38,001 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 924 states, 924 states have (on average 1.4880952380952381) internal successors, (1375), 923 states have internal predecessors, (1375), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:38,003 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 924 states to 924 states and 1375 transitions. [2021-12-15 17:21:38,003 INFO L704 BuchiCegarLoop]: Abstraction has 924 states and 1375 transitions. [2021-12-15 17:21:38,003 INFO L587 BuchiCegarLoop]: Abstraction has 924 states and 1375 transitions. [2021-12-15 17:21:38,003 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2021-12-15 17:21:38,003 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 924 states and 1375 transitions. [2021-12-15 17:21:38,006 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 811 [2021-12-15 17:21:38,006 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:21:38,007 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:21:38,007 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:38,008 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:38,008 INFO L791 eck$LassoCheckResult]: Stem: 9966#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 9967#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 10209#L1235 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 9381#L574 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9382#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 9653#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9654#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10151#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 10141#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 9721#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 9722#L606-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 9946#L611-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 9947#L616-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 9803#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 9804#L838 assume !(0 == ~M_E~0); 9953#L838-2 assume !(0 == ~T1_E~0); 9343#L843-1 assume !(0 == ~T2_E~0); 9344#L848-1 assume !(0 == ~T3_E~0); 9463#L853-1 assume !(0 == ~T4_E~0); 9789#L858-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 9290#L863-1 assume !(0 == ~T6_E~0); 9291#L868-1 assume !(0 == ~T7_E~0); 10183#L873-1 assume !(0 == ~T8_E~0); 10181#L878-1 assume !(0 == ~E_1~0); 10170#L883-1 assume !(0 == ~E_2~0); 10171#L888-1 assume !(0 == ~E_3~0); 9918#L893-1 assume !(0 == ~E_4~0); 9919#L898-1 assume 0 == ~E_5~0;~E_5~0 := 1; 10195#L903-1 assume !(0 == ~E_6~0); 10169#L908-1 assume !(0 == ~E_7~0); 10043#L913-1 assume !(0 == ~E_8~0); 9357#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9358#L402 assume !(1 == ~m_pc~0); 9566#L402-2 is_master_triggered_~__retres1~0#1 := 0; 9484#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9485#L414 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 9727#L1035 assume !(0 != activate_threads_~tmp~1#1); 9728#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9780#L421 assume 1 == ~t1_pc~0; 10165#L422 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 10184#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9772#L433 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 9773#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 9831#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10192#L440 assume 1 == ~t2_pc~0; 9327#L441 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 9328#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9494#L452 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 10203#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 10057#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9681#L459 assume !(1 == ~t3_pc~0); 9682#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 10164#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9988#L471 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 9478#L1059 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9479#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9488#L478 assume 1 == ~t4_pc~0; 9489#L479 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 9923#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10150#L490 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9659#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 9402#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9403#L497 assume !(1 == ~t5_pc~0); 9449#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 9450#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9741#L509 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 9742#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 10157#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10158#L516 assume 1 == ~t6_pc~0; 10212#L517 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 9944#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9945#L528 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 9533#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 9534#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9935#L535 assume !(1 == ~t7_pc~0); 9936#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 10005#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10006#L547 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 10034#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 10024#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 10025#L554 assume 1 == ~t8_pc~0; 9974#L555 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 9319#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 10075#L566 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9621#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 9622#L1099-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9303#L931 assume !(1 == ~M_E~0); 9304#L931-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 10178#L936-1 assume !(1 == ~T2_E~0); 10201#L941-1 assume !(1 == ~T3_E~0); 9781#L946-1 assume !(1 == ~T4_E~0); 9782#L951-1 assume !(1 == ~T5_E~0); 9548#L956-1 assume !(1 == ~T6_E~0); 9549#L961-1 assume !(1 == ~T7_E~0); 9920#L966-1 assume !(1 == ~T8_E~0); 9921#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 10027#L976-1 assume !(1 == ~E_2~0); 9997#L981-1 assume !(1 == ~E_3~0); 9786#L986-1 assume !(1 == ~E_4~0); 9578#L991-1 assume !(1 == ~E_5~0); 9579#L996-1 assume !(1 == ~E_6~0); 10188#L1001-1 assume !(1 == ~E_7~0); 9964#L1006-1 assume !(1 == ~E_8~0); 9965#L1011-1 assume { :end_inline_reset_delta_events } true; 9366#L1272-2 [2021-12-15 17:21:38,008 INFO L793 eck$LassoCheckResult]: Loop: 9366#L1272-2 assume !false; 9367#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 9368#L813 assume !false; 9369#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 10115#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 9371#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 9915#L682 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 9925#L696 assume !(0 != eval_~tmp~0#1); 9968#L828 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 9969#L574-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 10090#L838-3 assume !(0 == ~M_E~0); 10010#L838-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 10011#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 9873#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 9874#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 9922#L858-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 9985#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 9977#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 9978#L873-3 assume !(0 == ~T8_E~0); 9601#L878-3 assume 0 == ~E_1~0;~E_1~0 := 1; 9330#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 9331#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 9332#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 9333#L898-3 assume 0 == ~E_5~0;~E_5~0 := 1; 9807#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 10116#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 9820#L913-3 assume !(0 == ~E_8~0); 9373#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9374#L402-27 assume 1 == ~m_pc~0; 9320#L403-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 9321#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9810#L414-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 9811#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 10129#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10130#L421-27 assume !(1 == ~t1_pc~0); 9593#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 9594#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9843#L433-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 9844#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 10189#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9938#L440-27 assume 1 == ~t2_pc~0; 9939#L441-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 10112#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9677#L452-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 9678#L1051-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 9852#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9581#L459-27 assume !(1 == ~t3_pc~0); 9582#L459-29 is_transmit3_triggered_~__retres1~3#1 := 0; 10000#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9645#L471-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 9646#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9934#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10182#L478-27 assume !(1 == ~t4_pc~0); 9571#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 9572#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9948#L490-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 10080#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 10081#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10117#L497-27 assume 1 == ~t5_pc~0; 10118#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 9610#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9611#L509-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 9554#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 9555#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9812#L516-27 assume 1 == ~t6_pc~0; 9813#L517-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 9667#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9668#L528-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 9815#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 9955#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9744#L535-27 assume 1 == ~t7_pc~0; 9745#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 10061#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10091#L547-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 10092#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 9698#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 9699#L554-27 assume !(1 == ~t8_pc~0); 9347#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 9348#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 9493#L566-9 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9832#L1099-27 assume !(0 != activate_threads_~tmp___7~0#1); 9598#L1099-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9599#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 9474#L931-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9475#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9695#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 9827#L946-3 assume !(1 == ~T4_E~0); 9616#L951-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 9617#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 9896#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 9705#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 9706#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 9943#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 9364#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 9365#L986-3 assume !(1 == ~E_4~0); 9355#L991-3 assume 1 == ~E_5~0;~E_5~0 := 2; 9356#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 10015#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 9686#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 9687#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 9397#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 9399#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 9713#L682-1 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 9714#L1291 assume !(0 == start_simulation_~tmp~3#1); 9893#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 9799#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 9294#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 9295#L682-2 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 10099#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 9763#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 9764#L1254 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 9980#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 9366#L1272-2 [2021-12-15 17:21:38,009 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:38,009 INFO L85 PathProgramCache]: Analyzing trace with hash 510892636, now seen corresponding path program 1 times [2021-12-15 17:21:38,009 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:38,009 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1979884831] [2021-12-15 17:21:38,010 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:38,010 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:38,021 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:38,036 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:38,036 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:38,036 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1979884831] [2021-12-15 17:21:38,036 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1979884831] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:38,037 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:38,037 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:38,037 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [837155880] [2021-12-15 17:21:38,037 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:38,037 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:21:38,039 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:38,039 INFO L85 PathProgramCache]: Analyzing trace with hash -638345507, now seen corresponding path program 3 times [2021-12-15 17:21:38,039 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:38,041 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2029712372] [2021-12-15 17:21:38,041 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:38,042 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:38,049 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:38,063 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:38,063 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:38,064 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2029712372] [2021-12-15 17:21:38,064 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2029712372] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:38,064 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:38,064 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:38,064 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [286723832] [2021-12-15 17:21:38,064 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:38,065 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:21:38,065 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:21:38,065 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:21:38,065 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:21:38,065 INFO L87 Difference]: Start difference. First operand 924 states and 1375 transitions. cyclomatic complexity: 452 Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:38,077 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:21:38,077 INFO L93 Difference]: Finished difference Result 924 states and 1374 transitions. [2021-12-15 17:21:38,078 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:21:38,078 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 924 states and 1374 transitions. [2021-12-15 17:21:38,082 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 811 [2021-12-15 17:21:38,108 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 924 states to 924 states and 1374 transitions. [2021-12-15 17:21:38,108 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 924 [2021-12-15 17:21:38,109 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 924 [2021-12-15 17:21:38,109 INFO L73 IsDeterministic]: Start isDeterministic. Operand 924 states and 1374 transitions. [2021-12-15 17:21:38,110 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:21:38,110 INFO L681 BuchiCegarLoop]: Abstraction has 924 states and 1374 transitions. [2021-12-15 17:21:38,111 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 924 states and 1374 transitions. [2021-12-15 17:21:38,117 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 924 to 924. [2021-12-15 17:21:38,118 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 924 states, 924 states have (on average 1.4870129870129871) internal successors, (1374), 923 states have internal predecessors, (1374), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:38,120 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 924 states to 924 states and 1374 transitions. [2021-12-15 17:21:38,120 INFO L704 BuchiCegarLoop]: Abstraction has 924 states and 1374 transitions. [2021-12-15 17:21:38,120 INFO L587 BuchiCegarLoop]: Abstraction has 924 states and 1374 transitions. [2021-12-15 17:21:38,120 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2021-12-15 17:21:38,120 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 924 states and 1374 transitions. [2021-12-15 17:21:38,123 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 811 [2021-12-15 17:21:38,123 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:21:38,123 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:21:38,124 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:38,124 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:38,125 INFO L791 eck$LassoCheckResult]: Stem: 11821#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 11822#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 12064#L1235 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 11236#L574 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 11237#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 11508#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 11509#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12006#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 11997#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 11576#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 11577#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 11802#L611-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 11803#L616-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 11658#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 11659#L838 assume !(0 == ~M_E~0); 11809#L838-2 assume !(0 == ~T1_E~0); 11198#L843-1 assume !(0 == ~T2_E~0); 11199#L848-1 assume !(0 == ~T3_E~0); 11318#L853-1 assume !(0 == ~T4_E~0); 11644#L858-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 11145#L863-1 assume !(0 == ~T6_E~0); 11146#L868-1 assume !(0 == ~T7_E~0); 12038#L873-1 assume !(0 == ~T8_E~0); 12036#L878-1 assume !(0 == ~E_1~0); 12025#L883-1 assume !(0 == ~E_2~0); 12026#L888-1 assume !(0 == ~E_3~0); 11773#L893-1 assume !(0 == ~E_4~0); 11774#L898-1 assume 0 == ~E_5~0;~E_5~0 := 1; 12050#L903-1 assume !(0 == ~E_6~0); 12024#L908-1 assume !(0 == ~E_7~0); 11898#L913-1 assume !(0 == ~E_8~0); 11212#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11213#L402 assume !(1 == ~m_pc~0); 11421#L402-2 is_master_triggered_~__retres1~0#1 := 0; 11339#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11340#L414 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 11582#L1035 assume !(0 != activate_threads_~tmp~1#1); 11583#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11635#L421 assume 1 == ~t1_pc~0; 12020#L422 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 12039#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11627#L433 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 11628#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 11686#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12047#L440 assume 1 == ~t2_pc~0; 11182#L441 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 11183#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11349#L452 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 12058#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 11912#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11536#L459 assume !(1 == ~t3_pc~0); 11537#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 12019#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11843#L471 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 11333#L1059 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 11334#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 11343#L478 assume 1 == ~t4_pc~0; 11344#L479 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 11778#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12005#L490 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 11514#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 11257#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11258#L497 assume !(1 == ~t5_pc~0); 11304#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 11305#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11596#L509 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 11597#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 12012#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 12013#L516 assume 1 == ~t6_pc~0; 12067#L517 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 11799#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11800#L528 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 11388#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 11389#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 11790#L535 assume !(1 == ~t7_pc~0); 11791#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 11860#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 11861#L547 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 11889#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 11879#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 11880#L554 assume 1 == ~t8_pc~0; 11829#L555 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 11174#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 11930#L566 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 11476#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 11477#L1099-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11158#L931 assume !(1 == ~M_E~0); 11159#L931-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12033#L936-1 assume !(1 == ~T2_E~0); 12056#L941-1 assume !(1 == ~T3_E~0); 11636#L946-1 assume !(1 == ~T4_E~0); 11637#L951-1 assume !(1 == ~T5_E~0); 11403#L956-1 assume !(1 == ~T6_E~0); 11404#L961-1 assume !(1 == ~T7_E~0); 11775#L966-1 assume !(1 == ~T8_E~0); 11776#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 11882#L976-1 assume !(1 == ~E_2~0); 11852#L981-1 assume !(1 == ~E_3~0); 11641#L986-1 assume !(1 == ~E_4~0); 11433#L991-1 assume !(1 == ~E_5~0); 11434#L996-1 assume !(1 == ~E_6~0); 12043#L1001-1 assume !(1 == ~E_7~0); 11819#L1006-1 assume !(1 == ~E_8~0); 11820#L1011-1 assume { :end_inline_reset_delta_events } true; 11221#L1272-2 [2021-12-15 17:21:38,125 INFO L793 eck$LassoCheckResult]: Loop: 11221#L1272-2 assume !false; 11222#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 11223#L813 assume !false; 11224#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 11970#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 11226#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 11770#L682 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 11780#L696 assume !(0 != eval_~tmp~0#1); 11823#L828 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 11824#L574-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 11945#L838-3 assume !(0 == ~M_E~0); 11865#L838-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 11866#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 11728#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11729#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 11777#L858-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 11840#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 11832#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 11833#L873-3 assume !(0 == ~T8_E~0); 11456#L878-3 assume 0 == ~E_1~0;~E_1~0 := 1; 11185#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 11186#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 11187#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 11188#L898-3 assume 0 == ~E_5~0;~E_5~0 := 1; 11662#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 11971#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 11675#L913-3 assume !(0 == ~E_8~0); 11228#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11229#L402-27 assume 1 == ~m_pc~0; 11175#L403-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 11176#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11665#L414-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 11666#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 11984#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11985#L421-27 assume !(1 == ~t1_pc~0); 11448#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 11449#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11698#L433-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 11699#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 12044#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11793#L440-27 assume 1 == ~t2_pc~0; 11794#L441-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 11967#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11532#L452-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 11533#L1051-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 11707#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11436#L459-27 assume !(1 == ~t3_pc~0); 11437#L459-29 is_transmit3_triggered_~__retres1~3#1 := 0; 11855#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11500#L471-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 11501#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 11789#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12037#L478-27 assume !(1 == ~t4_pc~0); 11426#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 11427#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11801#L490-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 11935#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 11936#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11972#L497-27 assume 1 == ~t5_pc~0; 11973#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 11465#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11466#L509-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 11409#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 11410#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11667#L516-27 assume 1 == ~t6_pc~0; 11668#L517-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 11522#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11523#L528-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 11670#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 11810#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 11599#L535-27 assume 1 == ~t7_pc~0; 11600#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 11916#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 11946#L547-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 11947#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 11553#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 11554#L554-27 assume !(1 == ~t8_pc~0); 11202#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 11203#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 11348#L566-9 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 11687#L1099-27 assume !(0 != activate_threads_~tmp___7~0#1); 11453#L1099-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11454#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 11329#L931-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 11330#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 11550#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 11682#L946-3 assume !(1 == ~T4_E~0); 11471#L951-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 11472#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 11751#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 11560#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 11561#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 11798#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 11219#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 11220#L986-3 assume !(1 == ~E_4~0); 11210#L991-3 assume 1 == ~E_5~0;~E_5~0 := 2; 11211#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 11870#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 11541#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 11542#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 11252#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 11254#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 11568#L682-1 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 11569#L1291 assume !(0 == start_simulation_~tmp~3#1); 11748#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 11654#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 11149#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 11150#L682-2 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 11954#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 11618#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 11619#L1254 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 11835#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 11221#L1272-2 [2021-12-15 17:21:38,125 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:38,125 INFO L85 PathProgramCache]: Analyzing trace with hash 2129867550, now seen corresponding path program 1 times [2021-12-15 17:21:38,126 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:38,126 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1841005298] [2021-12-15 17:21:38,126 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:38,126 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:38,132 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:38,141 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:38,142 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:38,142 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1841005298] [2021-12-15 17:21:38,142 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1841005298] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:38,142 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:38,142 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:38,142 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2145642085] [2021-12-15 17:21:38,142 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:38,143 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:21:38,143 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:38,143 INFO L85 PathProgramCache]: Analyzing trace with hash -638345507, now seen corresponding path program 4 times [2021-12-15 17:21:38,143 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:38,143 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [667466050] [2021-12-15 17:21:38,143 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:38,144 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:38,150 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:38,163 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:38,163 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:38,163 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [667466050] [2021-12-15 17:21:38,163 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [667466050] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:38,164 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:38,164 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:38,164 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1393321506] [2021-12-15 17:21:38,164 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:38,164 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:21:38,164 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:21:38,165 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:21:38,165 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:21:38,165 INFO L87 Difference]: Start difference. First operand 924 states and 1374 transitions. cyclomatic complexity: 451 Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:38,176 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:21:38,177 INFO L93 Difference]: Finished difference Result 924 states and 1373 transitions. [2021-12-15 17:21:38,177 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:21:38,177 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 924 states and 1373 transitions. [2021-12-15 17:21:38,181 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 811 [2021-12-15 17:21:38,184 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 924 states to 924 states and 1373 transitions. [2021-12-15 17:21:38,184 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 924 [2021-12-15 17:21:38,185 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 924 [2021-12-15 17:21:38,185 INFO L73 IsDeterministic]: Start isDeterministic. Operand 924 states and 1373 transitions. [2021-12-15 17:21:38,186 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:21:38,186 INFO L681 BuchiCegarLoop]: Abstraction has 924 states and 1373 transitions. [2021-12-15 17:21:38,187 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 924 states and 1373 transitions. [2021-12-15 17:21:38,193 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 924 to 924. [2021-12-15 17:21:38,194 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 924 states, 924 states have (on average 1.4859307359307359) internal successors, (1373), 923 states have internal predecessors, (1373), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:38,196 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 924 states to 924 states and 1373 transitions. [2021-12-15 17:21:38,196 INFO L704 BuchiCegarLoop]: Abstraction has 924 states and 1373 transitions. [2021-12-15 17:21:38,196 INFO L587 BuchiCegarLoop]: Abstraction has 924 states and 1373 transitions. [2021-12-15 17:21:38,197 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2021-12-15 17:21:38,197 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 924 states and 1373 transitions. [2021-12-15 17:21:38,200 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 811 [2021-12-15 17:21:38,200 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:21:38,200 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:21:38,201 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:38,201 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:38,201 INFO L791 eck$LassoCheckResult]: Stem: 13676#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 13677#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 13919#L1235 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 13091#L574 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 13092#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 13363#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 13364#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 13861#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 13852#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 13431#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 13432#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 13657#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 13658#L616-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 13513#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 13514#L838 assume !(0 == ~M_E~0); 13664#L838-2 assume !(0 == ~T1_E~0); 13053#L843-1 assume !(0 == ~T2_E~0); 13054#L848-1 assume !(0 == ~T3_E~0); 13173#L853-1 assume !(0 == ~T4_E~0); 13501#L858-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 13002#L863-1 assume !(0 == ~T6_E~0); 13003#L868-1 assume !(0 == ~T7_E~0); 13893#L873-1 assume !(0 == ~T8_E~0); 13891#L878-1 assume !(0 == ~E_1~0); 13880#L883-1 assume !(0 == ~E_2~0); 13881#L888-1 assume !(0 == ~E_3~0); 13628#L893-1 assume !(0 == ~E_4~0); 13629#L898-1 assume 0 == ~E_5~0;~E_5~0 := 1; 13905#L903-1 assume !(0 == ~E_6~0); 13879#L908-1 assume !(0 == ~E_7~0); 13755#L913-1 assume !(0 == ~E_8~0); 13067#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13068#L402 assume !(1 == ~m_pc~0); 13280#L402-2 is_master_triggered_~__retres1~0#1 := 0; 13194#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13195#L414 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 13437#L1035 assume !(0 != activate_threads_~tmp~1#1); 13438#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13490#L421 assume 1 == ~t1_pc~0; 13875#L422 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 13897#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13482#L433 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 13483#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 13542#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13902#L440 assume 1 == ~t2_pc~0; 13037#L441 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 13038#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13204#L452 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 13913#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 13767#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 13395#L459 assume !(1 == ~t3_pc~0); 13396#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 13874#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13699#L471 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 13188#L1059 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 13189#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13198#L478 assume 1 == ~t4_pc~0; 13199#L479 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 13633#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13860#L490 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 13369#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 13114#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13115#L497 assume !(1 == ~t5_pc~0); 13159#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 13160#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13451#L509 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 13452#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 13868#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 13869#L516 assume 1 == ~t6_pc~0; 13922#L517 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 13654#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 13655#L528 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 13243#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 13244#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 13645#L535 assume !(1 == ~t7_pc~0); 13646#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 13715#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 13716#L547 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 13744#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 13735#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 13736#L554 assume 1 == ~t8_pc~0; 13685#L555 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 13029#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 13785#L566 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 13334#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 13335#L1099-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13013#L931 assume !(1 == ~M_E~0); 13014#L931-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 13888#L936-1 assume !(1 == ~T2_E~0); 13911#L941-1 assume !(1 == ~T3_E~0); 13491#L946-1 assume !(1 == ~T4_E~0); 13492#L951-1 assume !(1 == ~T5_E~0); 13258#L956-1 assume !(1 == ~T6_E~0); 13259#L961-1 assume !(1 == ~T7_E~0); 13630#L966-1 assume !(1 == ~T8_E~0); 13631#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 13738#L976-1 assume !(1 == ~E_2~0); 13707#L981-1 assume !(1 == ~E_3~0); 13496#L986-1 assume !(1 == ~E_4~0); 13288#L991-1 assume !(1 == ~E_5~0); 13289#L996-1 assume !(1 == ~E_6~0); 13898#L1001-1 assume !(1 == ~E_7~0); 13674#L1006-1 assume !(1 == ~E_8~0); 13675#L1011-1 assume { :end_inline_reset_delta_events } true; 13076#L1272-2 [2021-12-15 17:21:38,201 INFO L793 eck$LassoCheckResult]: Loop: 13076#L1272-2 assume !false; 13077#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 13078#L813 assume !false; 13079#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 13825#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 13081#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 13627#L682 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 13635#L696 assume !(0 != eval_~tmp~0#1); 13678#L828 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 13679#L574-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 13802#L838-3 assume !(0 == ~M_E~0); 13720#L838-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 13721#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 13584#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 13585#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 13632#L858-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 13695#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 13687#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 13688#L873-3 assume !(0 == ~T8_E~0); 13311#L878-3 assume 0 == ~E_1~0;~E_1~0 := 1; 13040#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 13041#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 13042#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 13043#L898-3 assume 0 == ~E_5~0;~E_5~0 := 1; 13517#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 13826#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 13530#L913-3 assume !(0 == ~E_8~0); 13083#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13084#L402-27 assume 1 == ~m_pc~0; 13030#L403-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 13031#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13520#L414-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 13521#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 13839#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13840#L421-27 assume 1 == ~t1_pc~0; 13750#L422-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 13304#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13553#L433-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 13554#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 13899#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13648#L440-27 assume 1 == ~t2_pc~0; 13649#L441-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 13821#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13387#L452-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 13388#L1051-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 13562#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 13291#L459-27 assume !(1 == ~t3_pc~0); 13292#L459-29 is_transmit3_triggered_~__retres1~3#1 := 0; 13710#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13355#L471-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 13356#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 13644#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13892#L478-27 assume !(1 == ~t4_pc~0); 13281#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 13282#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13656#L490-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 13790#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 13791#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13827#L497-27 assume 1 == ~t5_pc~0; 13828#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 13320#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13321#L509-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 13264#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 13265#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 13522#L516-27 assume 1 == ~t6_pc~0; 13523#L517-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 13374#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 13375#L528-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 13525#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 13665#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 13454#L535-27 assume !(1 == ~t7_pc~0); 13456#L535-29 is_transmit7_triggered_~__retres1~7#1 := 0; 13771#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 13800#L547-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 13801#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 13408#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 13409#L554-27 assume !(1 == ~t8_pc~0); 13057#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 13058#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 13203#L566-9 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 13541#L1099-27 assume !(0 != activate_threads_~tmp___7~0#1); 13308#L1099-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13309#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 13184#L931-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 13185#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 13405#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 13537#L946-3 assume !(1 == ~T4_E~0); 13326#L951-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 13327#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 13606#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 13415#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 13416#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 13653#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 13074#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 13075#L986-3 assume !(1 == ~E_4~0); 13065#L991-3 assume 1 == ~E_5~0;~E_5~0 := 2; 13066#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 13725#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 13393#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 13394#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 13107#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 13109#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 13423#L682-1 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 13424#L1291 assume !(0 == start_simulation_~tmp~3#1); 13603#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 13509#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 13004#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 13005#L682-2 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 13809#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 13473#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 13474#L1254 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 13690#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 13076#L1272-2 [2021-12-15 17:21:38,202 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:38,202 INFO L85 PathProgramCache]: Analyzing trace with hash -1281590756, now seen corresponding path program 1 times [2021-12-15 17:21:38,202 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:38,202 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1257393260] [2021-12-15 17:21:38,202 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:38,203 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:38,208 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:38,220 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:38,220 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:38,220 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1257393260] [2021-12-15 17:21:38,220 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1257393260] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:38,221 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:38,221 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:38,221 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [96134685] [2021-12-15 17:21:38,221 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:38,221 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:21:38,222 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:38,222 INFO L85 PathProgramCache]: Analyzing trace with hash -1516707235, now seen corresponding path program 1 times [2021-12-15 17:21:38,222 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:38,222 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1466834015] [2021-12-15 17:21:38,222 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:38,222 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:38,229 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:38,242 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:38,242 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:38,242 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1466834015] [2021-12-15 17:21:38,242 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1466834015] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:38,242 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:38,242 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:38,243 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [773580520] [2021-12-15 17:21:38,243 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:38,243 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:21:38,243 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:21:38,244 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:21:38,244 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:21:38,244 INFO L87 Difference]: Start difference. First operand 924 states and 1373 transitions. cyclomatic complexity: 450 Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:38,255 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:21:38,256 INFO L93 Difference]: Finished difference Result 924 states and 1372 transitions. [2021-12-15 17:21:38,256 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:21:38,256 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 924 states and 1372 transitions. [2021-12-15 17:21:38,260 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 811 [2021-12-15 17:21:38,263 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 924 states to 924 states and 1372 transitions. [2021-12-15 17:21:38,264 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 924 [2021-12-15 17:21:38,264 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 924 [2021-12-15 17:21:38,264 INFO L73 IsDeterministic]: Start isDeterministic. Operand 924 states and 1372 transitions. [2021-12-15 17:21:38,265 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:21:38,265 INFO L681 BuchiCegarLoop]: Abstraction has 924 states and 1372 transitions. [2021-12-15 17:21:38,266 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 924 states and 1372 transitions. [2021-12-15 17:21:38,272 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 924 to 924. [2021-12-15 17:21:38,273 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 924 states, 924 states have (on average 1.4848484848484849) internal successors, (1372), 923 states have internal predecessors, (1372), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:38,275 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 924 states to 924 states and 1372 transitions. [2021-12-15 17:21:38,275 INFO L704 BuchiCegarLoop]: Abstraction has 924 states and 1372 transitions. [2021-12-15 17:21:38,276 INFO L587 BuchiCegarLoop]: Abstraction has 924 states and 1372 transitions. [2021-12-15 17:21:38,276 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2021-12-15 17:21:38,276 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 924 states and 1372 transitions. [2021-12-15 17:21:38,279 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 811 [2021-12-15 17:21:38,279 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:21:38,279 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:21:38,280 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:38,280 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:38,280 INFO L791 eck$LassoCheckResult]: Stem: 15531#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 15532#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 15774#L1235 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 14946#L574 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 14947#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 15218#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 15219#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 15716#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 15706#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 15286#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 15287#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 15512#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 15513#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 15368#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 15369#L838 assume !(0 == ~M_E~0); 15519#L838-2 assume !(0 == ~T1_E~0); 14908#L843-1 assume !(0 == ~T2_E~0); 14909#L848-1 assume !(0 == ~T3_E~0); 15028#L853-1 assume !(0 == ~T4_E~0); 15356#L858-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 14855#L863-1 assume !(0 == ~T6_E~0); 14856#L868-1 assume !(0 == ~T7_E~0); 15748#L873-1 assume !(0 == ~T8_E~0); 15746#L878-1 assume !(0 == ~E_1~0); 15735#L883-1 assume !(0 == ~E_2~0); 15736#L888-1 assume !(0 == ~E_3~0); 15483#L893-1 assume !(0 == ~E_4~0); 15484#L898-1 assume 0 == ~E_5~0;~E_5~0 := 1; 15760#L903-1 assume !(0 == ~E_6~0); 15734#L908-1 assume !(0 == ~E_7~0); 15608#L913-1 assume !(0 == ~E_8~0); 14922#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14923#L402 assume !(1 == ~m_pc~0); 15133#L402-2 is_master_triggered_~__retres1~0#1 := 0; 15049#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 15050#L414 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 15292#L1035 assume !(0 != activate_threads_~tmp~1#1); 15293#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15345#L421 assume 1 == ~t1_pc~0; 15730#L422 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 15752#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15337#L433 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 15338#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 15397#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15757#L440 assume 1 == ~t2_pc~0; 14892#L441 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 14893#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 15059#L452 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 15768#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 15622#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15250#L459 assume !(1 == ~t3_pc~0); 15251#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 15729#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15554#L471 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 15043#L1059 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 15044#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 15053#L478 assume 1 == ~t4_pc~0; 15054#L479 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 15488#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 15715#L490 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 15224#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 14969#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14970#L497 assume !(1 == ~t5_pc~0); 15014#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 15015#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15306#L509 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 15307#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 15723#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 15724#L516 assume 1 == ~t6_pc~0; 15777#L517 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 15509#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 15510#L528 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 15098#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 15099#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 15500#L535 assume !(1 == ~t7_pc~0); 15501#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 15570#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 15571#L547 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 15599#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 15589#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 15590#L554 assume 1 == ~t8_pc~0; 15540#L555 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 14884#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 15640#L566 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 15189#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 15190#L1099-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14868#L931 assume !(1 == ~M_E~0); 14869#L931-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 15743#L936-1 assume !(1 == ~T2_E~0); 15766#L941-1 assume !(1 == ~T3_E~0); 15346#L946-1 assume !(1 == ~T4_E~0); 15347#L951-1 assume !(1 == ~T5_E~0); 15113#L956-1 assume !(1 == ~T6_E~0); 15114#L961-1 assume !(1 == ~T7_E~0); 15485#L966-1 assume !(1 == ~T8_E~0); 15486#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 15592#L976-1 assume !(1 == ~E_2~0); 15562#L981-1 assume !(1 == ~E_3~0); 15351#L986-1 assume !(1 == ~E_4~0); 15143#L991-1 assume !(1 == ~E_5~0); 15144#L996-1 assume !(1 == ~E_6~0); 15753#L1001-1 assume !(1 == ~E_7~0); 15529#L1006-1 assume !(1 == ~E_8~0); 15530#L1011-1 assume { :end_inline_reset_delta_events } true; 14931#L1272-2 [2021-12-15 17:21:38,280 INFO L793 eck$LassoCheckResult]: Loop: 14931#L1272-2 assume !false; 14932#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 14933#L813 assume !false; 14934#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 15680#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 14936#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 15480#L682 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 15490#L696 assume !(0 != eval_~tmp~0#1); 15533#L828 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 15534#L574-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 15657#L838-3 assume !(0 == ~M_E~0); 15575#L838-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 15576#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 15438#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 15439#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 15487#L858-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 15550#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 15542#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 15543#L873-3 assume !(0 == ~T8_E~0); 15168#L878-3 assume 0 == ~E_1~0;~E_1~0 := 1; 14895#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 14896#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 14897#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 14898#L898-3 assume 0 == ~E_5~0;~E_5~0 := 1; 15374#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 15683#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 15385#L913-3 assume !(0 == ~E_8~0); 14938#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14939#L402-27 assume 1 == ~m_pc~0; 14885#L403-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 14886#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 15379#L414-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 15380#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 15697#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15698#L421-27 assume 1 == ~t1_pc~0; 15605#L422-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 15159#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15408#L433-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 15409#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 15754#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15503#L440-27 assume 1 == ~t2_pc~0; 15504#L441-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 15676#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 15242#L452-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 15243#L1051-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 15417#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15146#L459-27 assume !(1 == ~t3_pc~0); 15147#L459-29 is_transmit3_triggered_~__retres1~3#1 := 0; 15565#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15210#L471-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 15211#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 15499#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 15747#L478-27 assume !(1 == ~t4_pc~0); 15136#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 15137#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 15511#L490-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 15645#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 15646#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 15681#L497-27 assume !(1 == ~t5_pc~0); 15298#L497-29 is_transmit5_triggered_~__retres1~5#1 := 0; 15175#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15176#L509-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 15119#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 15120#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 15375#L516-27 assume 1 == ~t6_pc~0; 15376#L517-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 15225#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 15226#L528-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 15378#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 15520#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 15309#L535-27 assume 1 == ~t7_pc~0; 15310#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 15626#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 15655#L547-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 15656#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 15263#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 15264#L554-27 assume !(1 == ~t8_pc~0); 14912#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 14913#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 15058#L566-9 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 15396#L1099-27 assume !(0 != activate_threads_~tmp___7~0#1); 15163#L1099-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15164#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 15039#L931-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 15040#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 15260#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 15392#L946-3 assume !(1 == ~T4_E~0); 15181#L951-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 15182#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 15461#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 15270#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 15271#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 15508#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 14929#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 14930#L986-3 assume !(1 == ~E_4~0); 14920#L991-3 assume 1 == ~E_5~0;~E_5~0 := 2; 14921#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 15580#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 15248#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 15249#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 14962#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 14964#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 15278#L682-1 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 15279#L1291 assume !(0 == start_simulation_~tmp~3#1); 15458#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 15364#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 14859#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 14860#L682-2 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 15664#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 15328#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 15329#L1254 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 15545#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 14931#L1272-2 [2021-12-15 17:21:38,281 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:38,281 INFO L85 PathProgramCache]: Analyzing trace with hash -1253090466, now seen corresponding path program 1 times [2021-12-15 17:21:38,281 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:38,281 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [581993214] [2021-12-15 17:21:38,281 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:38,281 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:38,288 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:38,303 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:38,303 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:38,303 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [581993214] [2021-12-15 17:21:38,303 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [581993214] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:38,304 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:38,304 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:38,304 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [62786143] [2021-12-15 17:21:38,304 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:38,304 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:21:38,304 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:38,304 INFO L85 PathProgramCache]: Analyzing trace with hash 741608413, now seen corresponding path program 1 times [2021-12-15 17:21:38,305 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:38,305 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [332086197] [2021-12-15 17:21:38,305 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:38,305 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:38,328 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:38,341 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:38,341 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:38,341 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [332086197] [2021-12-15 17:21:38,342 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [332086197] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:38,342 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:38,342 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:38,342 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1187418049] [2021-12-15 17:21:38,342 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:38,342 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:21:38,342 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:21:38,343 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-15 17:21:38,343 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-15 17:21:38,343 INFO L87 Difference]: Start difference. First operand 924 states and 1372 transitions. cyclomatic complexity: 449 Second operand has 4 states, 4 states have (on average 26.0) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:38,454 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:21:38,454 INFO L93 Difference]: Finished difference Result 1670 states and 2471 transitions. [2021-12-15 17:21:38,455 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-15 17:21:38,455 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1670 states and 2471 transitions. [2021-12-15 17:21:38,464 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1540 [2021-12-15 17:21:38,470 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1670 states to 1670 states and 2471 transitions. [2021-12-15 17:21:38,470 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1670 [2021-12-15 17:21:38,471 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1670 [2021-12-15 17:21:38,471 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1670 states and 2471 transitions. [2021-12-15 17:21:38,473 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:21:38,473 INFO L681 BuchiCegarLoop]: Abstraction has 1670 states and 2471 transitions. [2021-12-15 17:21:38,474 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1670 states and 2471 transitions. [2021-12-15 17:21:38,489 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1670 to 1670. [2021-12-15 17:21:38,491 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1670 states, 1670 states have (on average 1.4796407185628742) internal successors, (2471), 1669 states have internal predecessors, (2471), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:38,495 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1670 states to 1670 states and 2471 transitions. [2021-12-15 17:21:38,495 INFO L704 BuchiCegarLoop]: Abstraction has 1670 states and 2471 transitions. [2021-12-15 17:21:38,495 INFO L587 BuchiCegarLoop]: Abstraction has 1670 states and 2471 transitions. [2021-12-15 17:21:38,495 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2021-12-15 17:21:38,495 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1670 states and 2471 transitions. [2021-12-15 17:21:38,499 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1540 [2021-12-15 17:21:38,499 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:21:38,499 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:21:38,500 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:38,500 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:38,500 INFO L791 eck$LassoCheckResult]: Stem: 18145#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 18146#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 18417#L1235 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 17551#L574 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 17552#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 17824#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 17825#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 18345#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 18332#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 17893#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 17894#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 18126#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 18127#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 17979#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 17980#L838 assume !(0 == ~M_E~0); 18133#L838-2 assume !(0 == ~T1_E~0); 17513#L843-1 assume !(0 == ~T2_E~0); 17514#L848-1 assume !(0 == ~T3_E~0); 17633#L853-1 assume !(0 == ~T4_E~0); 17967#L858-1 assume !(0 == ~T5_E~0); 17459#L863-1 assume !(0 == ~T6_E~0); 17460#L868-1 assume !(0 == ~T7_E~0); 18387#L873-1 assume !(0 == ~T8_E~0); 18384#L878-1 assume !(0 == ~E_1~0); 18368#L883-1 assume !(0 == ~E_2~0); 18369#L888-1 assume !(0 == ~E_3~0); 18097#L893-1 assume !(0 == ~E_4~0); 18098#L898-1 assume 0 == ~E_5~0;~E_5~0 := 1; 18401#L903-1 assume !(0 == ~E_6~0); 18367#L908-1 assume !(0 == ~E_7~0); 18223#L913-1 assume !(0 == ~E_8~0); 17527#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17528#L402 assume !(1 == ~m_pc~0); 17740#L402-2 is_master_triggered_~__retres1~0#1 := 0; 17654#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 17655#L414 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 17899#L1035 assume !(0 != activate_threads_~tmp~1#1); 17900#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17956#L421 assume 1 == ~t1_pc~0; 18363#L422 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 18392#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17947#L433 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 17948#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 18008#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18398#L440 assume 1 == ~t2_pc~0; 17497#L441 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 17498#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17664#L452 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 18411#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 18238#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 17857#L459 assume !(1 == ~t3_pc~0); 17858#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 18359#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18168#L471 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 17648#L1059 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 17649#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 17658#L478 assume 1 == ~t4_pc~0; 17659#L479 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 18102#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 18344#L490 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 17830#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 17574#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 17575#L497 assume !(1 == ~t5_pc~0); 17619#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 17620#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 17914#L509 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 17915#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 18353#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 18354#L516 assume 1 == ~t6_pc~0; 18423#L517 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 18123#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 18124#L528 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 17703#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 17704#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 18114#L535 assume !(1 == ~t7_pc~0); 18115#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 18184#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 18185#L547 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 18213#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 18204#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 18205#L554 assume 1 == ~t8_pc~0; 18154#L555 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 17489#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 18257#L566 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 17795#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 17796#L1099-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17472#L931 assume 1 == ~M_E~0;~M_E~0 := 2; 17473#L931-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 18379#L936-1 assume !(1 == ~T2_E~0); 18409#L941-1 assume !(1 == ~T3_E~0); 17957#L946-1 assume !(1 == ~T4_E~0); 17958#L951-1 assume !(1 == ~T5_E~0); 17718#L956-1 assume !(1 == ~T6_E~0); 17719#L961-1 assume !(1 == ~T7_E~0); 18099#L966-1 assume !(1 == ~T8_E~0); 18100#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 18206#L976-1 assume !(1 == ~E_2~0); 18176#L981-1 assume !(1 == ~E_3~0); 17962#L986-1 assume !(1 == ~E_4~0); 17748#L991-1 assume !(1 == ~E_5~0); 17749#L996-1 assume !(1 == ~E_6~0); 18393#L1001-1 assume !(1 == ~E_7~0); 18143#L1006-1 assume !(1 == ~E_8~0); 18144#L1011-1 assume { :end_inline_reset_delta_events } true; 18446#L1272-2 [2021-12-15 17:21:38,501 INFO L793 eck$LassoCheckResult]: Loop: 18446#L1272-2 assume !false; 18441#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 18438#L813 assume !false; 18300#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 18301#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 17541#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 18096#L682 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 18104#L696 assume !(0 != eval_~tmp~0#1); 18426#L828 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 18275#L574-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 18276#L838-3 assume !(0 == ~M_E~0); 18189#L838-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 18190#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 18050#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 18051#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 18101#L858-3 assume !(0 == ~T5_E~0); 18164#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 18156#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 18157#L873-3 assume !(0 == ~T8_E~0); 17773#L878-3 assume 0 == ~E_1~0;~E_1~0 := 1; 17500#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 17501#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 17502#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 17503#L898-3 assume 0 == ~E_5~0;~E_5~0 := 1; 17985#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 18304#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 17996#L913-3 assume !(0 == ~E_8~0); 17543#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17544#L402-27 assume 1 == ~m_pc~0; 17490#L403-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 17491#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 17986#L414-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 17987#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 18320#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 18321#L421-27 assume !(1 == ~t1_pc~0); 17763#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 17764#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18020#L433-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 18021#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 18394#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18117#L440-27 assume 1 == ~t2_pc~0; 18118#L441-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 18296#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17849#L452-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 17850#L1051-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 18029#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 17751#L459-27 assume !(1 == ~t3_pc~0); 17752#L459-29 is_transmit3_triggered_~__retres1~3#1 := 0; 18179#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 17816#L471-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 17817#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 18113#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 18386#L478-27 assume 1 == ~t4_pc~0; 18412#L479-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 17742#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 18125#L490-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 18262#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 18263#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 18302#L497-27 assume !(1 == ~t5_pc~0); 17906#L497-29 is_transmit5_triggered_~__retres1~5#1 := 0; 17780#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 17781#L509-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 17724#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 17725#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 17988#L516-27 assume 1 == ~t6_pc~0; 17989#L517-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 17835#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 17836#L528-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 17991#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 18134#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 17917#L535-27 assume 1 == ~t7_pc~0; 17918#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 18243#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 18425#L547-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 18809#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 18806#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 18804#L554-27 assume 1 == ~t8_pc~0; 18801#L555-9 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 18799#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 18797#L566-9 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 18795#L1099-27 assume !(0 != activate_threads_~tmp___7~0#1); 18792#L1099-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 18790#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 18239#L931-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 18787#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 18785#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 18783#L946-3 assume !(1 == ~T4_E~0); 18780#L951-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 17787#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 18777#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 18775#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 18773#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 18771#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 18768#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 18766#L986-3 assume !(1 == ~E_4~0); 18764#L991-3 assume 1 == ~E_5~0;~E_5~0 := 2; 18762#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 18760#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 18758#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 18755#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 18753#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 18743#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 18741#L682-1 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 18740#L1291 assume !(0 == start_simulation_~tmp~3#1); 18070#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 18686#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 18684#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 18682#L682-2 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 18373#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 17938#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 17939#L1254 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 18159#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 18446#L1272-2 [2021-12-15 17:21:38,501 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:38,501 INFO L85 PathProgramCache]: Analyzing trace with hash -1677430238, now seen corresponding path program 1 times [2021-12-15 17:21:38,501 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:38,501 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [428801063] [2021-12-15 17:21:38,502 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:38,502 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:38,508 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:38,521 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:38,521 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:38,521 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [428801063] [2021-12-15 17:21:38,522 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [428801063] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:38,522 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:38,522 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:38,522 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1681275475] [2021-12-15 17:21:38,522 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:38,522 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:21:38,523 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:38,523 INFO L85 PathProgramCache]: Analyzing trace with hash 441860352, now seen corresponding path program 1 times [2021-12-15 17:21:38,523 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:38,523 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1714396250] [2021-12-15 17:21:38,523 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:38,523 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:38,530 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:38,545 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:38,546 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:38,546 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1714396250] [2021-12-15 17:21:38,546 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1714396250] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:38,546 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:38,546 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:38,546 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1396634888] [2021-12-15 17:21:38,546 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:38,547 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:21:38,547 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:21:38,547 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-15 17:21:38,547 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-15 17:21:38,547 INFO L87 Difference]: Start difference. First operand 1670 states and 2471 transitions. cyclomatic complexity: 803 Second operand has 4 states, 4 states have (on average 26.0) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:38,659 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:21:38,659 INFO L93 Difference]: Finished difference Result 3016 states and 4452 transitions. [2021-12-15 17:21:38,659 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-15 17:21:38,660 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3016 states and 4452 transitions. [2021-12-15 17:21:38,672 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2868 [2021-12-15 17:21:38,697 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3016 states to 3016 states and 4452 transitions. [2021-12-15 17:21:38,698 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3016 [2021-12-15 17:21:38,699 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3016 [2021-12-15 17:21:38,699 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3016 states and 4452 transitions. [2021-12-15 17:21:38,702 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:21:38,702 INFO L681 BuchiCegarLoop]: Abstraction has 3016 states and 4452 transitions. [2021-12-15 17:21:38,703 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3016 states and 4452 transitions. [2021-12-15 17:21:38,730 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3016 to 3014. [2021-12-15 17:21:38,734 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3014 states, 3014 states have (on average 1.4764432647644326) internal successors, (4450), 3013 states have internal predecessors, (4450), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:38,740 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3014 states to 3014 states and 4450 transitions. [2021-12-15 17:21:38,740 INFO L704 BuchiCegarLoop]: Abstraction has 3014 states and 4450 transitions. [2021-12-15 17:21:38,740 INFO L587 BuchiCegarLoop]: Abstraction has 3014 states and 4450 transitions. [2021-12-15 17:21:38,741 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2021-12-15 17:21:38,741 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3014 states and 4450 transitions. [2021-12-15 17:21:38,748 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2868 [2021-12-15 17:21:38,748 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:21:38,748 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:21:38,749 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:38,749 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:38,749 INFO L791 eck$LassoCheckResult]: Stem: 22846#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 22847#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 23109#L1235 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 22247#L574 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 22248#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 22525#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 22526#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 23044#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 23034#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 22593#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 22594#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 22827#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 22828#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 22677#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 22678#L838 assume !(0 == ~M_E~0); 22834#L838-2 assume !(0 == ~T1_E~0); 22209#L843-1 assume !(0 == ~T2_E~0); 22210#L848-1 assume !(0 == ~T3_E~0); 22329#L853-1 assume !(0 == ~T4_E~0); 22665#L858-1 assume !(0 == ~T5_E~0); 22155#L863-1 assume !(0 == ~T6_E~0); 22156#L868-1 assume !(0 == ~T7_E~0); 23081#L873-1 assume !(0 == ~T8_E~0); 23078#L878-1 assume !(0 == ~E_1~0); 23064#L883-1 assume !(0 == ~E_2~0); 23065#L888-1 assume !(0 == ~E_3~0); 22797#L893-1 assume !(0 == ~E_4~0); 22798#L898-1 assume !(0 == ~E_5~0); 23093#L903-1 assume !(0 == ~E_6~0); 23063#L908-1 assume !(0 == ~E_7~0); 22925#L913-1 assume !(0 == ~E_8~0); 22223#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 22224#L402 assume !(1 == ~m_pc~0); 22434#L402-2 is_master_triggered_~__retres1~0#1 := 0; 22350#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 22351#L414 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 22599#L1035 assume !(0 != activate_threads_~tmp~1#1); 22600#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 22653#L421 assume 1 == ~t1_pc~0; 23059#L422 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 23085#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22645#L433 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 22646#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 22707#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 23090#L440 assume 1 == ~t2_pc~0; 22193#L441 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 22194#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 22360#L452 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 23101#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 22942#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22557#L459 assume !(1 == ~t3_pc~0); 22558#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 23057#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22871#L471 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 22344#L1059 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 22345#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 22354#L478 assume 1 == ~t4_pc~0; 22355#L479 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 22802#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 23043#L490 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 22531#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 22270#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 22271#L497 assume !(1 == ~t5_pc~0); 22315#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 22316#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 22613#L509 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 22614#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 23051#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 23052#L516 assume 1 == ~t6_pc~0; 23112#L517 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 22824#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 22825#L528 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 22399#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 22400#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 22815#L535 assume !(1 == ~t7_pc~0); 22816#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 22887#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 22888#L547 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 22916#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 22906#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 22907#L554 assume 1 == ~t8_pc~0; 22855#L555 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 22185#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 22961#L566 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 22496#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 22497#L1099-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 22168#L931 assume 1 == ~M_E~0;~M_E~0 := 2; 22169#L931-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 23073#L936-1 assume !(1 == ~T2_E~0); 23099#L941-1 assume !(1 == ~T3_E~0); 22654#L946-1 assume !(1 == ~T4_E~0); 22655#L951-1 assume !(1 == ~T5_E~0); 23058#L956-1 assume !(1 == ~T6_E~0); 23113#L961-1 assume !(1 == ~T7_E~0); 22799#L966-1 assume !(1 == ~T8_E~0); 22800#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 22909#L976-1 assume !(1 == ~E_2~0); 22879#L981-1 assume !(1 == ~E_3~0); 22659#L986-1 assume !(1 == ~E_4~0); 22660#L991-1 assume !(1 == ~E_5~0); 23183#L996-1 assume !(1 == ~E_6~0); 23181#L1001-1 assume !(1 == ~E_7~0); 23163#L1006-1 assume !(1 == ~E_8~0); 23154#L1011-1 assume { :end_inline_reset_delta_events } true; 23146#L1272-2 [2021-12-15 17:21:38,750 INFO L793 eck$LassoCheckResult]: Loop: 23146#L1272-2 assume !false; 23140#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 23136#L813 assume !false; 23135#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 23133#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 23125#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 23124#L682 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 23122#L696 assume !(0 != eval_~tmp~0#1); 23121#L828 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 23120#L574-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 23118#L838-3 assume !(0 == ~M_E~0); 23119#L838-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 23937#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 23935#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 23933#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 23922#L858-3 assume !(0 == ~T5_E~0); 23918#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 23916#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 23914#L873-3 assume !(0 == ~T8_E~0); 23912#L878-3 assume 0 == ~E_1~0;~E_1~0 := 1; 23911#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 23892#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 23890#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 23888#L898-3 assume !(0 == ~E_5~0); 23848#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 23846#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 23843#L913-3 assume !(0 == ~E_8~0); 23841#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 23839#L402-27 assume 1 == ~m_pc~0; 23835#L403-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 23834#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 23831#L414-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 23829#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 23827#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 23825#L421-27 assume 1 == ~t1_pc~0; 23769#L422-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 23767#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 23716#L433-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 23714#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 23712#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 23709#L440-27 assume 1 == ~t2_pc~0; 23706#L441-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 23698#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 23689#L452-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 23682#L1051-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 23677#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 23670#L459-27 assume !(1 == ~t3_pc~0); 23657#L459-29 is_transmit3_triggered_~__retres1~3#1 := 0; 23652#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 23651#L471-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 23650#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 23649#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 23648#L478-27 assume 1 == ~t4_pc~0; 23646#L479-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 23645#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 23644#L490-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 23643#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 23642#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 23641#L497-27 assume !(1 == ~t5_pc~0); 23639#L497-29 is_transmit5_triggered_~__retres1~5#1 := 0; 23577#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 23574#L509-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 23572#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 23570#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 23568#L516-27 assume 1 == ~t6_pc~0; 23565#L517-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 23563#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 23560#L528-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 23558#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 23557#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 23556#L535-27 assume !(1 == ~t7_pc~0); 23554#L535-29 is_transmit7_triggered_~__retres1~7#1 := 0; 23553#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 22976#L547-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 22977#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 22570#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 22571#L554-27 assume 1 == ~t8_pc~0; 22771#L555-9 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 22214#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 22359#L566-9 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 22706#L1099-27 assume !(0 != activate_threads_~tmp___7~0#1); 22467#L1099-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 22468#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 22340#L931-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 22341#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 22567#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 22702#L946-3 assume !(1 == ~T4_E~0); 23254#L951-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 23251#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 23249#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 23247#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 23245#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 23243#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 23241#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 23239#L986-3 assume !(1 == ~E_4~0); 23238#L991-3 assume 1 == ~E_5~0;~E_5~0 := 2; 23235#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 23234#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 23233#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 23232#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 23231#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 23219#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 23217#L682-1 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 23215#L1291 assume !(0 == start_simulation_~tmp~3#1); 22769#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 23184#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 23182#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 23180#L682-2 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 23176#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 23174#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 23162#L1254 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 23153#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 23146#L1272-2 [2021-12-15 17:21:38,750 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:38,751 INFO L85 PathProgramCache]: Analyzing trace with hash -1650364636, now seen corresponding path program 1 times [2021-12-15 17:21:38,751 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:38,751 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [547265012] [2021-12-15 17:21:38,751 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:38,751 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:38,758 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:38,769 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:38,770 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:38,770 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [547265012] [2021-12-15 17:21:38,770 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [547265012] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:38,770 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:38,770 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-15 17:21:38,770 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1741051048] [2021-12-15 17:21:38,771 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:38,771 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:21:38,771 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:38,771 INFO L85 PathProgramCache]: Analyzing trace with hash -1207234942, now seen corresponding path program 1 times [2021-12-15 17:21:38,771 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:38,772 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1706303730] [2021-12-15 17:21:38,772 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:38,772 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:38,779 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:38,794 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:38,795 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:38,795 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1706303730] [2021-12-15 17:21:38,795 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1706303730] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:38,795 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:38,795 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:38,795 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [64113146] [2021-12-15 17:21:38,795 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:38,796 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:21:38,796 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:21:38,796 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:21:38,796 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:21:38,797 INFO L87 Difference]: Start difference. First operand 3014 states and 4450 transitions. cyclomatic complexity: 1440 Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 2 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:38,863 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:21:38,863 INFO L93 Difference]: Finished difference Result 5582 states and 8185 transitions. [2021-12-15 17:21:38,863 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:21:38,864 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5582 states and 8185 transitions. [2021-12-15 17:21:38,884 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5433 [2021-12-15 17:21:38,901 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5582 states to 5582 states and 8185 transitions. [2021-12-15 17:21:38,901 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5582 [2021-12-15 17:21:38,904 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5582 [2021-12-15 17:21:38,904 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5582 states and 8185 transitions. [2021-12-15 17:21:38,909 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:21:38,909 INFO L681 BuchiCegarLoop]: Abstraction has 5582 states and 8185 transitions. [2021-12-15 17:21:38,911 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5582 states and 8185 transitions. [2021-12-15 17:21:38,997 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5582 to 5574. [2021-12-15 17:21:39,004 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5574 states, 5574 states have (on average 1.466989594546107) internal successors, (8177), 5573 states have internal predecessors, (8177), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:39,014 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5574 states to 5574 states and 8177 transitions. [2021-12-15 17:21:39,018 INFO L704 BuchiCegarLoop]: Abstraction has 5574 states and 8177 transitions. [2021-12-15 17:21:39,018 INFO L587 BuchiCegarLoop]: Abstraction has 5574 states and 8177 transitions. [2021-12-15 17:21:39,018 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2021-12-15 17:21:39,018 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5574 states and 8177 transitions. [2021-12-15 17:21:39,031 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5425 [2021-12-15 17:21:39,031 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:21:39,031 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:21:39,032 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:39,032 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:39,032 INFO L791 eck$LassoCheckResult]: Stem: 31479#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 31480#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 31851#L1235 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 30851#L574 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 30852#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 31130#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 31131#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 31738#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 31717#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 31205#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 31206#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 31459#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 31460#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 31294#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 31295#L838 assume !(0 == ~M_E~0); 31466#L838-2 assume !(0 == ~T1_E~0); 30812#L843-1 assume !(0 == ~T2_E~0); 30813#L848-1 assume !(0 == ~T3_E~0); 30932#L853-1 assume !(0 == ~T4_E~0); 31280#L858-1 assume !(0 == ~T5_E~0); 30758#L863-1 assume !(0 == ~T6_E~0); 30759#L868-1 assume !(0 == ~T7_E~0); 31797#L873-1 assume !(0 == ~T8_E~0); 31794#L878-1 assume !(0 == ~E_1~0); 31770#L883-1 assume !(0 == ~E_2~0); 31771#L888-1 assume !(0 == ~E_3~0); 31429#L893-1 assume !(0 == ~E_4~0); 31430#L898-1 assume !(0 == ~E_5~0); 31819#L903-1 assume !(0 == ~E_6~0); 31769#L908-1 assume !(0 == ~E_7~0); 31574#L913-1 assume !(0 == ~E_8~0); 30827#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 30828#L402 assume !(1 == ~m_pc~0); 31039#L402-2 is_master_triggered_~__retres1~0#1 := 0; 30954#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 30955#L414 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 31211#L1035 assume !(0 != activate_threads_~tmp~1#1); 31212#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 31271#L421 assume !(1 == ~t1_pc~0); 31761#L421-2 is_transmit1_triggered_~__retres1~1#1 := 0; 31798#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 31259#L433 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 31260#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 31323#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 31811#L440 assume 1 == ~t2_pc~0; 30796#L441 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 30797#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 30966#L452 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 31838#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 31595#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 31160#L459 assume !(1 == ~t3_pc~0); 31161#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 31758#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 31508#L471 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 30947#L1059 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 30948#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 30958#L478 assume 1 == ~t4_pc~0; 30959#L479 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 31434#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 31735#L490 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 31136#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 30871#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 30872#L497 assume !(1 == ~t5_pc~0); 30918#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 30919#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 31225#L509 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 31226#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 31748#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 31749#L516 assume 1 == ~t6_pc~0; 31864#L517 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 31457#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 31458#L528 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 31006#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 31007#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 31448#L535 assume !(1 == ~t7_pc~0); 31449#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 31526#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 31527#L547 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 31563#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 31549#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 31550#L554 assume 1 == ~t8_pc~0; 31488#L555 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 30788#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 31620#L566 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 31095#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 31096#L1099-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 30771#L931 assume 1 == ~M_E~0;~M_E~0 := 2; 30772#L931-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 31786#L936-1 assume !(1 == ~T2_E~0); 31833#L941-1 assume !(1 == ~T3_E~0); 31272#L946-1 assume !(1 == ~T4_E~0); 31273#L951-1 assume !(1 == ~T5_E~0); 31021#L956-1 assume !(1 == ~T6_E~0); 31022#L961-1 assume !(1 == ~T7_E~0); 31431#L966-1 assume !(1 == ~T8_E~0); 31432#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 31553#L976-1 assume !(1 == ~E_2~0); 31845#L981-1 assume !(1 == ~E_3~0); 32705#L986-1 assume !(1 == ~E_4~0); 32704#L991-1 assume !(1 == ~E_5~0); 32701#L996-1 assume !(1 == ~E_6~0); 32700#L1001-1 assume !(1 == ~E_7~0); 32668#L1006-1 assume !(1 == ~E_8~0); 32585#L1011-1 assume { :end_inline_reset_delta_events } true; 32577#L1272-2 [2021-12-15 17:21:39,033 INFO L793 eck$LassoCheckResult]: Loop: 32577#L1272-2 assume !false; 32571#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 32567#L813 assume !false; 32566#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 32564#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 32556#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 32555#L682 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 32553#L696 assume !(0 != eval_~tmp~0#1); 32552#L828 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 32551#L574-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 32550#L838-3 assume !(0 == ~M_E~0); 32546#L838-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 32547#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 32542#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 32543#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 32538#L858-3 assume !(0 == ~T5_E~0); 32539#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 33790#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 33789#L873-3 assume !(0 == ~T8_E~0); 33788#L878-3 assume 0 == ~E_1~0;~E_1~0 := 1; 33787#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 33786#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 33785#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 33784#L898-3 assume !(0 == ~E_5~0); 33783#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 33782#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 33781#L913-3 assume !(0 == ~E_8~0); 33780#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 33779#L402-27 assume 1 == ~m_pc~0; 33777#L403-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 33775#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 33773#L414-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 33771#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 33769#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 33767#L421-27 assume !(1 == ~t1_pc~0); 33765#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 33763#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 33761#L433-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 33759#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 33757#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 33755#L440-27 assume 1 == ~t2_pc~0; 33752#L441-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 33750#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 33748#L452-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 33746#L1051-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 33744#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 33742#L459-27 assume !(1 == ~t3_pc~0); 33739#L459-29 is_transmit3_triggered_~__retres1~3#1 := 0; 33737#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 33735#L471-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 33732#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 33730#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 33728#L478-27 assume 1 == ~t4_pc~0; 33725#L479-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 33723#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 33721#L490-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 33719#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 33717#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 33715#L497-27 assume !(1 == ~t5_pc~0); 33712#L497-29 is_transmit5_triggered_~__retres1~5#1 := 0; 33710#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 33708#L509-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 33705#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 33703#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 33701#L516-27 assume 1 == ~t6_pc~0; 33698#L517-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 33696#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 33694#L528-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 33691#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 33689#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 33687#L535-27 assume !(1 == ~t7_pc~0); 33684#L535-29 is_transmit7_triggered_~__retres1~7#1 := 0; 33682#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 33680#L547-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 33677#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 33675#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 33673#L554-27 assume 1 == ~t8_pc~0; 33348#L555-9 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 33273#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 33270#L566-9 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 33268#L1099-27 assume !(0 != activate_threads_~tmp___7~0#1); 33266#L1099-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 33226#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 32396#L931-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 33197#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 33190#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 33182#L946-3 assume !(1 == ~T4_E~0); 33119#L951-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 33112#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 33108#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 33104#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 33101#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 33096#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 33094#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 33091#L986-3 assume !(1 == ~E_4~0); 33089#L991-3 assume 1 == ~E_5~0;~E_5~0 := 2; 33085#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 32733#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 32698#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 32696#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 32658#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 32649#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 32648#L682-1 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 32647#L1291 assume !(0 == start_simulation_~tmp~3#1); 32326#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 32628#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 32626#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 32617#L682-2 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 32607#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 32600#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 32594#L1254 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 32584#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 32577#L1272-2 [2021-12-15 17:21:39,033 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:39,033 INFO L85 PathProgramCache]: Analyzing trace with hash 1466628099, now seen corresponding path program 1 times [2021-12-15 17:21:39,033 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:39,033 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1927990990] [2021-12-15 17:21:39,034 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:39,034 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:39,040 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:39,053 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:39,053 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:39,054 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1927990990] [2021-12-15 17:21:39,054 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1927990990] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:39,054 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:39,054 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:39,054 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [282884815] [2021-12-15 17:21:39,054 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:39,054 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:21:39,055 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:39,055 INFO L85 PathProgramCache]: Analyzing trace with hash 1810579681, now seen corresponding path program 1 times [2021-12-15 17:21:39,055 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:39,055 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [131401924] [2021-12-15 17:21:39,055 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:39,055 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:39,062 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:39,074 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:39,075 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:39,075 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [131401924] [2021-12-15 17:21:39,075 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [131401924] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:39,075 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:39,075 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:39,075 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1578717367] [2021-12-15 17:21:39,075 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:39,076 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:21:39,076 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:21:39,076 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-15 17:21:39,076 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-15 17:21:39,076 INFO L87 Difference]: Start difference. First operand 5574 states and 8177 transitions. cyclomatic complexity: 2611 Second operand has 4 states, 4 states have (on average 26.0) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:39,215 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:21:39,215 INFO L93 Difference]: Finished difference Result 13086 states and 19034 transitions. [2021-12-15 17:21:39,215 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-15 17:21:39,216 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 13086 states and 19034 transitions. [2021-12-15 17:21:39,263 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 12906 [2021-12-15 17:21:39,354 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 13086 states to 13086 states and 19034 transitions. [2021-12-15 17:21:39,354 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13086 [2021-12-15 17:21:39,361 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13086 [2021-12-15 17:21:39,362 INFO L73 IsDeterministic]: Start isDeterministic. Operand 13086 states and 19034 transitions. [2021-12-15 17:21:39,373 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:21:39,374 INFO L681 BuchiCegarLoop]: Abstraction has 13086 states and 19034 transitions. [2021-12-15 17:21:39,380 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13086 states and 19034 transitions. [2021-12-15 17:21:39,475 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13086 to 10404. [2021-12-15 17:21:39,491 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10404 states, 10404 states have (on average 1.459919261822376) internal successors, (15189), 10403 states have internal predecessors, (15189), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:39,580 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10404 states to 10404 states and 15189 transitions. [2021-12-15 17:21:39,580 INFO L704 BuchiCegarLoop]: Abstraction has 10404 states and 15189 transitions. [2021-12-15 17:21:39,580 INFO L587 BuchiCegarLoop]: Abstraction has 10404 states and 15189 transitions. [2021-12-15 17:21:39,580 INFO L425 BuchiCegarLoop]: ======== Iteration 13============ [2021-12-15 17:21:39,581 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 10404 states and 15189 transitions. [2021-12-15 17:21:39,606 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 10252 [2021-12-15 17:21:39,607 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:21:39,607 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:21:39,608 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:39,608 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:39,608 INFO L791 eck$LassoCheckResult]: Stem: 50130#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 50131#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 50431#L1235 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 49520#L574 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 49521#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 49797#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 49798#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 50355#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 50342#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 49872#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 49873#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 50110#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 50111#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 49957#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 49958#L838 assume !(0 == ~M_E~0); 50117#L838-2 assume !(0 == ~T1_E~0); 49481#L843-1 assume !(0 == ~T2_E~0); 49482#L848-1 assume !(0 == ~T3_E~0); 49601#L853-1 assume !(0 == ~T4_E~0); 49943#L858-1 assume !(0 == ~T5_E~0); 49428#L863-1 assume !(0 == ~T6_E~0); 49429#L868-1 assume !(0 == ~T7_E~0); 50398#L873-1 assume !(0 == ~T8_E~0); 50395#L878-1 assume !(0 == ~E_1~0); 50376#L883-1 assume !(0 == ~E_2~0); 50377#L888-1 assume !(0 == ~E_3~0); 50082#L893-1 assume !(0 == ~E_4~0); 50083#L898-1 assume !(0 == ~E_5~0); 50413#L903-1 assume !(0 == ~E_6~0); 50375#L908-1 assume !(0 == ~E_7~0); 50215#L913-1 assume !(0 == ~E_8~0); 49496#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 49497#L402 assume !(1 == ~m_pc~0); 49707#L402-2 is_master_triggered_~__retres1~0#1 := 0; 49623#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 49624#L414 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 49878#L1035 assume !(0 != activate_threads_~tmp~1#1); 49879#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 49934#L421 assume !(1 == ~t1_pc~0); 50371#L421-2 is_transmit1_triggered_~__retres1~1#1 := 0; 50399#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 49926#L433 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 49927#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 49986#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 50410#L440 assume !(1 == ~t2_pc~0); 50447#L440-2 is_transmit2_triggered_~__retres1~2#1 := 0; 49633#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 49634#L452 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 50423#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 50230#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 49828#L459 assume !(1 == ~t3_pc~0); 49829#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 50369#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 50155#L471 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 49616#L1059 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 49617#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 49627#L478 assume 1 == ~t4_pc~0; 49628#L479 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 50087#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 50354#L490 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 49803#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 49540#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 49541#L497 assume !(1 == ~t5_pc~0); 49587#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 49588#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 49893#L509 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 49894#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 50362#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 50363#L516 assume 1 == ~t6_pc~0; 50441#L517 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 50108#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 50109#L528 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 49672#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 49673#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 50100#L535 assume !(1 == ~t7_pc~0); 50101#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 50173#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 50174#L547 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 50204#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 50194#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 50195#L554 assume 1 == ~t8_pc~0; 50140#L555 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 49458#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 50256#L566 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 49764#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 49765#L1099-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 49441#L931 assume 1 == ~M_E~0;~M_E~0 := 2; 49442#L931-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 56803#L936-1 assume !(1 == ~T2_E~0); 56802#L941-1 assume !(1 == ~T3_E~0); 56801#L946-1 assume !(1 == ~T4_E~0); 56800#L951-1 assume !(1 == ~T5_E~0); 56799#L956-1 assume !(1 == ~T6_E~0); 56797#L961-1 assume !(1 == ~T7_E~0); 56795#L966-1 assume !(1 == ~T8_E~0); 56793#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 56791#L976-1 assume !(1 == ~E_2~0); 56789#L981-1 assume !(1 == ~E_3~0); 56787#L986-1 assume !(1 == ~E_4~0); 56786#L991-1 assume !(1 == ~E_5~0); 56783#L996-1 assume !(1 == ~E_6~0); 56779#L1001-1 assume !(1 == ~E_7~0); 56778#L1006-1 assume !(1 == ~E_8~0); 56776#L1011-1 assume { :end_inline_reset_delta_events } true; 56773#L1272-2 [2021-12-15 17:21:39,609 INFO L793 eck$LassoCheckResult]: Loop: 56773#L1272-2 assume !false; 56770#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 56766#L813 assume !false; 56765#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 56763#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 56755#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 56731#L682 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 56720#L696 assume !(0 != eval_~tmp~0#1); 50132#L828 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 50133#L574-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 50278#L838-3 assume !(0 == ~M_E~0); 50178#L838-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 50179#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 50033#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 50034#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 50086#L858-3 assume !(0 == ~T5_E~0); 50152#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 50143#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 50144#L873-3 assume !(0 == ~T8_E~0); 49743#L878-3 assume 0 == ~E_1~0;~E_1~0 := 1; 49468#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 49469#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 49470#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 49471#L898-3 assume !(0 == ~E_5~0); 49961#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 50311#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 49975#L913-3 assume !(0 == ~E_8~0); 49512#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 49513#L402-27 assume 1 == ~m_pc~0; 50443#L403-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 50428#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 50429#L414-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 59507#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 59506#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 50353#L421-27 assume !(1 == ~t1_pc~0); 49735#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 49736#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 49999#L433-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 50000#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 50407#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 50442#L440-27 assume !(1 == ~t2_pc~0); 56984#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 56982#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 56980#L452-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 56978#L1051-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 56976#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 56974#L459-27 assume !(1 == ~t3_pc~0); 56970#L459-29 is_transmit3_triggered_~__retres1~3#1 := 0; 56968#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 56966#L471-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 56964#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 56962#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 56960#L478-27 assume 1 == ~t4_pc~0; 56956#L479-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 56954#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 56952#L490-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 56950#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 56948#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 56946#L497-27 assume 1 == ~t5_pc~0; 56944#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 56941#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 56939#L509-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 56937#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 56936#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 56935#L516-27 assume 1 == ~t6_pc~0; 56933#L517-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 56932#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 56931#L528-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 56930#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 56929#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 56927#L535-27 assume !(1 == ~t7_pc~0); 56924#L535-29 is_transmit7_triggered_~__retres1~7#1 := 0; 56921#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 56919#L547-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 56917#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 56915#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 56913#L554-27 assume 1 == ~t8_pc~0; 56910#L555-9 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 56908#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 56906#L566-9 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 56904#L1099-27 assume !(0 != activate_threads_~tmp___7~0#1); 56902#L1099-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 56900#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 56898#L931-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 56897#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 56895#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 56893#L946-3 assume !(1 == ~T4_E~0); 56891#L951-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 56887#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 56885#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 56882#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 56880#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 56878#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 56876#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 56874#L986-3 assume !(1 == ~E_4~0); 56872#L991-3 assume 1 == ~E_5~0;~E_5~0 := 2; 56867#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 56865#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 56863#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 56861#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 56859#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 56849#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 56846#L682-1 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 56844#L1291 assume !(0 == start_simulation_~tmp~3#1); 56841#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 56819#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 56817#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 56815#L682-2 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 56813#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 56811#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 56808#L1254 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 56775#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 56773#L1272-2 [2021-12-15 17:21:39,609 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:39,609 INFO L85 PathProgramCache]: Analyzing trace with hash -439856094, now seen corresponding path program 1 times [2021-12-15 17:21:39,609 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:39,609 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [360570619] [2021-12-15 17:21:39,609 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:39,610 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:39,616 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:39,634 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:39,635 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:39,635 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [360570619] [2021-12-15 17:21:39,635 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [360570619] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:39,635 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:39,635 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-15 17:21:39,635 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1192834822] [2021-12-15 17:21:39,635 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:39,636 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:21:39,636 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:39,636 INFO L85 PathProgramCache]: Analyzing trace with hash 1222362913, now seen corresponding path program 1 times [2021-12-15 17:21:39,636 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:39,636 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2084806444] [2021-12-15 17:21:39,637 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:39,637 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:39,643 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:39,656 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:39,656 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:39,656 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2084806444] [2021-12-15 17:21:39,656 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2084806444] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:39,657 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:39,657 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:39,657 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1373949004] [2021-12-15 17:21:39,657 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:39,657 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:21:39,657 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:21:39,658 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-15 17:21:39,658 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-15 17:21:39,658 INFO L87 Difference]: Start difference. First operand 10404 states and 15189 transitions. cyclomatic complexity: 4793 Second operand has 5 states, 5 states have (on average 20.8) internal successors, (104), 5 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:40,016 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:21:40,017 INFO L93 Difference]: Finished difference Result 27497 states and 40178 transitions. [2021-12-15 17:21:40,017 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-15 17:21:40,017 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 27497 states and 40178 transitions. [2021-12-15 17:21:40,223 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 27152 [2021-12-15 17:21:40,311 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 27497 states to 27497 states and 40178 transitions. [2021-12-15 17:21:40,312 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 27497 [2021-12-15 17:21:40,334 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 27497 [2021-12-15 17:21:40,335 INFO L73 IsDeterministic]: Start isDeterministic. Operand 27497 states and 40178 transitions. [2021-12-15 17:21:40,492 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:21:40,492 INFO L681 BuchiCegarLoop]: Abstraction has 27497 states and 40178 transitions. [2021-12-15 17:21:40,516 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 27497 states and 40178 transitions. [2021-12-15 17:21:40,798 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 27497 to 10779. [2021-12-15 17:21:40,819 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10779 states, 10779 states have (on average 1.4439187308655719) internal successors, (15564), 10778 states have internal predecessors, (15564), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:40,836 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10779 states to 10779 states and 15564 transitions. [2021-12-15 17:21:40,837 INFO L704 BuchiCegarLoop]: Abstraction has 10779 states and 15564 transitions. [2021-12-15 17:21:40,837 INFO L587 BuchiCegarLoop]: Abstraction has 10779 states and 15564 transitions. [2021-12-15 17:21:40,837 INFO L425 BuchiCegarLoop]: ======== Iteration 14============ [2021-12-15 17:21:40,837 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 10779 states and 15564 transitions. [2021-12-15 17:21:40,855 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 10624 [2021-12-15 17:21:40,855 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:21:40,855 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:21:40,856 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:40,856 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:40,857 INFO L791 eck$LassoCheckResult]: Stem: 88067#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 88068#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 88474#L1235 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 87431#L574 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 87432#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 87706#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 87707#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 88339#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 88319#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 87780#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 87781#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 88046#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 88047#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 87873#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 87874#L838 assume !(0 == ~M_E~0); 88055#L838-2 assume !(0 == ~T1_E~0); 87393#L843-1 assume !(0 == ~T2_E~0); 87394#L848-1 assume !(0 == ~T3_E~0); 87511#L853-1 assume !(0 == ~T4_E~0); 87861#L858-1 assume !(0 == ~T5_E~0); 87344#L863-1 assume !(0 == ~T6_E~0); 87345#L868-1 assume !(0 == ~T7_E~0); 88402#L873-1 assume !(0 == ~T8_E~0); 88399#L878-1 assume !(0 == ~E_1~0); 88372#L883-1 assume !(0 == ~E_2~0); 88373#L888-1 assume !(0 == ~E_3~0); 88014#L893-1 assume !(0 == ~E_4~0); 88015#L898-1 assume !(0 == ~E_5~0); 88427#L903-1 assume !(0 == ~E_6~0); 88371#L908-1 assume !(0 == ~E_7~0); 88165#L913-1 assume !(0 == ~E_8~0); 87407#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 87408#L402 assume !(1 == ~m_pc~0); 87623#L402-2 is_master_triggered_~__retres1~0#1 := 0; 87532#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 87533#L414 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 87787#L1035 assume !(0 != activate_threads_~tmp~1#1); 87788#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 87850#L421 assume !(1 == ~t1_pc~0); 88363#L421-2 is_transmit1_triggered_~__retres1~1#1 := 0; 88406#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 87838#L433 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 87839#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 87903#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 88418#L440 assume !(1 == ~t2_pc~0); 88508#L440-2 is_transmit2_triggered_~__retres1~2#1 := 0; 87542#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 87543#L452 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 88454#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 88186#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 87740#L459 assume !(1 == ~t3_pc~0); 87741#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 88360#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 88417#L471 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 87526#L1059 assume !(0 != activate_threads_~tmp___2~0#1); 87527#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 87536#L478 assume 1 == ~t4_pc~0; 87537#L479 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 88018#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 88338#L490 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 87712#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 87453#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 87454#L497 assume !(1 == ~t5_pc~0); 87497#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 87498#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 87801#L509 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 87802#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 88351#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 88352#L516 assume 1 == ~t6_pc~0; 88495#L517 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 88043#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 88044#L528 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 87582#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 87583#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 88035#L535 assume !(1 == ~t7_pc~0); 88036#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 88120#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 88121#L547 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 88154#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 88144#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 88145#L554 assume 1 == ~t8_pc~0; 88078#L555 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 87372#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 88211#L566 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 87676#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 87677#L1099-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 87355#L931 assume 1 == ~M_E~0;~M_E~0 := 2; 87356#L931-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 88390#L936-1 assume !(1 == ~T2_E~0); 88506#L941-1 assume !(1 == ~T3_E~0); 88507#L946-1 assume !(1 == ~T4_E~0); 88361#L951-1 assume !(1 == ~T5_E~0); 88362#L956-1 assume !(1 == ~T6_E~0); 93698#L961-1 assume !(1 == ~T7_E~0); 93606#L966-1 assume !(1 == ~T8_E~0); 93603#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 93601#L976-1 assume !(1 == ~E_2~0); 93599#L981-1 assume !(1 == ~E_3~0); 93597#L986-1 assume !(1 == ~E_4~0); 93595#L991-1 assume !(1 == ~E_5~0); 92038#L996-1 assume !(1 == ~E_6~0); 93591#L1001-1 assume !(1 == ~E_7~0); 93589#L1006-1 assume !(1 == ~E_8~0); 93493#L1011-1 assume { :end_inline_reset_delta_events } true; 91465#L1272-2 [2021-12-15 17:21:40,857 INFO L793 eck$LassoCheckResult]: Loop: 91465#L1272-2 assume !false; 91189#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 91185#L813 assume !false; 91173#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 91163#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 91147#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 91140#L682 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 91132#L696 assume !(0 != eval_~tmp~0#1); 91133#L828 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 95633#L574-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 95631#L838-3 assume !(0 == ~M_E~0); 95629#L838-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 95627#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 95626#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 95625#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 95622#L858-3 assume !(0 == ~T5_E~0); 95620#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 95618#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 95616#L873-3 assume !(0 == ~T8_E~0); 95614#L878-3 assume 0 == ~E_1~0;~E_1~0 := 1; 95551#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 95548#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 95546#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 95544#L898-3 assume !(0 == ~E_5~0); 95536#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 95529#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 95522#L913-3 assume !(0 == ~E_8~0); 95514#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 95513#L402-27 assume 1 == ~m_pc~0; 95511#L403-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 95510#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 95509#L414-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 95508#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 95507#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 95506#L421-27 assume !(1 == ~t1_pc~0); 95505#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 95504#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 95503#L433-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 95502#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 95501#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 95500#L440-27 assume !(1 == ~t2_pc~0); 93242#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 95499#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 95498#L452-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 95497#L1051-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 95496#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 95495#L459-27 assume 1 == ~t3_pc~0; 95493#L460-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 95491#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 95489#L471-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 95487#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 95483#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 95479#L478-27 assume 1 == ~t4_pc~0; 95463#L479-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 95461#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 95459#L490-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 95456#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 95454#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 95452#L497-27 assume !(1 == ~t5_pc~0); 95449#L497-29 is_transmit5_triggered_~__retres1~5#1 := 0; 95397#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 95388#L509-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 95380#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 95373#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 95331#L516-27 assume 1 == ~t6_pc~0; 95323#L517-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 95204#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 95202#L528-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 95200#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 95197#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 95195#L535-27 assume 1 == ~t7_pc~0; 95193#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 95190#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 95188#L547-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 95156#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 95155#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 94696#L554-27 assume 1 == ~t8_pc~0; 94549#L555-9 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 94546#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 94544#L566-9 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 94542#L1099-27 assume !(0 != activate_threads_~tmp___7~0#1); 94540#L1099-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 94538#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 89857#L931-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 94534#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 94532#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 94530#L946-3 assume !(1 == ~T4_E~0); 94528#L951-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 89845#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 94526#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 94525#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 94521#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 94519#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 94517#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 94234#L986-3 assume !(1 == ~E_4~0); 94231#L991-3 assume 1 == ~E_5~0;~E_5~0 := 2; 93386#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 93981#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 93979#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 93977#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 93887#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 93877#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 93875#L682-1 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 93874#L1291 assume !(0 == start_simulation_~tmp~3#1); 87978#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 93624#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 93622#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 93620#L682-2 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 93618#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 93616#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 93546#L1254 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 93492#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 91465#L1272-2 [2021-12-15 17:21:40,857 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:40,857 INFO L85 PathProgramCache]: Analyzing trace with hash -920936352, now seen corresponding path program 1 times [2021-12-15 17:21:40,858 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:40,858 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1425623465] [2021-12-15 17:21:40,858 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:40,858 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:40,866 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:40,880 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:40,881 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:40,881 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1425623465] [2021-12-15 17:21:40,881 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1425623465] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:40,881 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:40,881 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:40,881 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2053287048] [2021-12-15 17:21:40,881 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:40,882 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:21:40,882 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:40,882 INFO L85 PathProgramCache]: Analyzing trace with hash 363685826, now seen corresponding path program 1 times [2021-12-15 17:21:40,882 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:40,882 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [276366365] [2021-12-15 17:21:40,882 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:40,883 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:40,889 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:40,901 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:40,901 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:40,901 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [276366365] [2021-12-15 17:21:40,901 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [276366365] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:40,901 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:40,901 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:40,902 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1993467095] [2021-12-15 17:21:40,902 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:40,902 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:21:40,902 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:21:40,902 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-15 17:21:40,903 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-15 17:21:40,903 INFO L87 Difference]: Start difference. First operand 10779 states and 15564 transitions. cyclomatic complexity: 4793 Second operand has 4 states, 4 states have (on average 26.0) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:41,164 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:21:41,164 INFO L93 Difference]: Finished difference Result 25687 states and 36794 transitions. [2021-12-15 17:21:41,164 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-15 17:21:41,165 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 25687 states and 36794 transitions. [2021-12-15 17:21:41,255 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 25469 [2021-12-15 17:21:41,320 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 25687 states to 25687 states and 36794 transitions. [2021-12-15 17:21:41,320 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 25687 [2021-12-15 17:21:41,352 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 25687 [2021-12-15 17:21:41,353 INFO L73 IsDeterministic]: Start isDeterministic. Operand 25687 states and 36794 transitions. [2021-12-15 17:21:41,388 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:21:41,388 INFO L681 BuchiCegarLoop]: Abstraction has 25687 states and 36794 transitions. [2021-12-15 17:21:41,400 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 25687 states and 36794 transitions. [2021-12-15 17:21:41,769 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 25687 to 20710. [2021-12-15 17:21:41,796 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 20710 states, 20710 states have (on average 1.4362626750362144) internal successors, (29745), 20709 states have internal predecessors, (29745), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:41,833 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20710 states to 20710 states and 29745 transitions. [2021-12-15 17:21:41,834 INFO L704 BuchiCegarLoop]: Abstraction has 20710 states and 29745 transitions. [2021-12-15 17:21:41,834 INFO L587 BuchiCegarLoop]: Abstraction has 20710 states and 29745 transitions. [2021-12-15 17:21:41,834 INFO L425 BuchiCegarLoop]: ======== Iteration 15============ [2021-12-15 17:21:41,834 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 20710 states and 29745 transitions. [2021-12-15 17:21:41,889 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 20548 [2021-12-15 17:21:41,889 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:21:41,890 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:21:41,891 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:41,891 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:41,891 INFO L791 eck$LassoCheckResult]: Stem: 124524#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 124525#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 124927#L1235 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 123908#L574 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 123909#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 124185#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 124186#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 124791#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 124771#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 124257#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 124258#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 124502#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 124503#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 124347#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 124348#L838 assume !(0 == ~M_E~0); 124511#L838-2 assume !(0 == ~T1_E~0); 123869#L843-1 assume !(0 == ~T2_E~0); 123870#L848-1 assume !(0 == ~T3_E~0); 123989#L853-1 assume !(0 == ~T4_E~0); 124333#L858-1 assume !(0 == ~T5_E~0); 123818#L863-1 assume !(0 == ~T6_E~0); 123819#L868-1 assume !(0 == ~T7_E~0); 124861#L873-1 assume !(0 == ~T8_E~0); 124856#L878-1 assume !(0 == ~E_1~0); 124831#L883-1 assume !(0 == ~E_2~0); 124832#L888-1 assume !(0 == ~E_3~0); 124475#L893-1 assume !(0 == ~E_4~0); 124476#L898-1 assume !(0 == ~E_5~0); 124893#L903-1 assume !(0 == ~E_6~0); 124830#L908-1 assume !(0 == ~E_7~0); 124614#L913-1 assume !(0 == ~E_8~0); 123884#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 123885#L402 assume !(1 == ~m_pc~0); 124095#L402-2 is_master_triggered_~__retres1~0#1 := 0; 124012#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 124013#L414 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 124264#L1035 assume !(0 != activate_threads_~tmp~1#1); 124265#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 124323#L421 assume !(1 == ~t1_pc~0); 124821#L421-2 is_transmit1_triggered_~__retres1~1#1 := 0; 124862#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 124311#L433 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 124312#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 124377#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 124882#L440 assume !(1 == ~t2_pc~0); 124953#L440-2 is_transmit2_triggered_~__retres1~2#1 := 0; 124022#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 124023#L452 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 124912#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 124634#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 124215#L459 assume !(1 == ~t3_pc~0); 124216#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 124813#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 124552#L471 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 124006#L1059 assume !(0 != activate_threads_~tmp___2~0#1); 124007#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 124016#L478 assume !(1 == ~t4_pc~0); 124017#L478-2 is_transmit4_triggered_~__retres1~4#1 := 0; 124704#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 124790#L490 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 124191#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 123928#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 123929#L497 assume !(1 == ~t5_pc~0); 123975#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 123976#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 124279#L509 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 124280#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 124805#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 124806#L516 assume 1 == ~t6_pc~0; 124941#L517 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 124500#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 124501#L528 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 124060#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 124061#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 124492#L535 assume !(1 == ~t7_pc~0); 124493#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 124570#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 124571#L547 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 124604#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 124592#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 124593#L554 assume 1 == ~t8_pc~0; 124534#L555 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 123848#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 124662#L566 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 124152#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 124153#L1099-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 123831#L931 assume 1 == ~M_E~0;~M_E~0 := 2; 123832#L931-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 124848#L936-1 assume !(1 == ~T2_E~0); 124950#L941-1 assume !(1 == ~T3_E~0); 124951#L946-1 assume !(1 == ~T4_E~0); 124816#L951-1 assume !(1 == ~T5_E~0); 124817#L956-1 assume !(1 == ~T6_E~0); 124942#L961-1 assume !(1 == ~T7_E~0); 124943#L966-1 assume !(1 == ~T8_E~0); 124596#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 124597#L976-1 assume !(1 == ~E_2~0); 124561#L981-1 assume !(1 == ~E_3~0); 124562#L986-1 assume !(1 == ~E_4~0); 124107#L991-1 assume !(1 == ~E_5~0); 124108#L996-1 assume !(1 == ~E_6~0); 124871#L1001-1 assume !(1 == ~E_7~0); 124872#L1006-1 assume !(1 == ~E_8~0); 124818#L1011-1 assume { :end_inline_reset_delta_events } true; 124819#L1272-2 [2021-12-15 17:21:41,892 INFO L793 eck$LassoCheckResult]: Loop: 124819#L1272-2 assume !false; 134822#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 134815#L813 assume !false; 134813#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 134792#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 134780#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 134388#L682 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 134383#L696 assume !(0 != eval_~tmp~0#1); 134384#L828 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 136495#L574-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 136494#L838-3 assume !(0 == ~M_E~0); 136493#L838-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 136492#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 136491#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 136490#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 136489#L858-3 assume !(0 == ~T5_E~0); 136488#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 136487#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 136486#L873-3 assume !(0 == ~T8_E~0); 136485#L878-3 assume 0 == ~E_1~0;~E_1~0 := 1; 136484#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 136483#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 136482#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 136481#L898-3 assume !(0 == ~E_5~0); 136480#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 136479#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 136478#L913-3 assume !(0 == ~E_8~0); 136477#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 136476#L402-27 assume 1 == ~m_pc~0; 136474#L403-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 136473#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 136472#L414-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 136471#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 136470#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 136469#L421-27 assume !(1 == ~t1_pc~0); 136468#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 136467#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 136466#L433-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 136465#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 136435#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 124495#L440-27 assume !(1 == ~t2_pc~0); 124496#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 136254#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 136253#L452-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 136252#L1051-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 136251#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 136250#L459-27 assume 1 == ~t3_pc~0; 136248#L460-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 136246#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 136244#L471-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 136242#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 135781#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 124944#L478-27 assume !(1 == ~t4_pc~0); 124945#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 136305#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 136304#L490-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 136303#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 136302#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 136301#L497-27 assume !(1 == ~t5_pc~0); 136299#L497-29 is_transmit5_triggered_~__retres1~5#1 := 0; 136298#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 136297#L509-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 136296#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 136295#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 136294#L516-27 assume 1 == ~t6_pc~0; 136292#L517-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 136291#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 136290#L528-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 136289#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 136288#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 136287#L535-27 assume 1 == ~t7_pc~0; 136286#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 136284#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 136283#L547-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 136282#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 136281#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 136280#L554-27 assume 1 == ~t8_pc~0; 136278#L555-9 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 136277#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 136276#L566-9 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 136275#L1099-27 assume !(0 != activate_threads_~tmp___7~0#1); 136274#L1099-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 136273#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 130319#L931-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 136272#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 136271#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 136270#L946-3 assume !(1 == ~T4_E~0); 136269#L951-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 134493#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 136268#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 136267#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 136266#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 136265#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 136264#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 136263#L986-3 assume !(1 == ~E_4~0); 136262#L991-3 assume 1 == ~E_5~0;~E_5~0 := 2; 130288#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 124730#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 124220#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 124221#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 123923#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 123925#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 124249#L682-1 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 124250#L1291 assume !(0 == start_simulation_~tmp~3#1); 124887#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 134924#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 134894#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 134887#L682-2 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 134880#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 134879#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 134878#L1254 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 134842#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 124819#L1272-2 [2021-12-15 17:21:41,892 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:41,892 INFO L85 PathProgramCache]: Analyzing trace with hash 511898367, now seen corresponding path program 1 times [2021-12-15 17:21:41,893 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:41,893 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1793967638] [2021-12-15 17:21:41,893 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:41,893 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:41,907 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:41,923 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:41,924 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:41,924 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1793967638] [2021-12-15 17:21:41,924 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1793967638] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:41,924 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:41,924 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:41,924 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [95291650] [2021-12-15 17:21:41,924 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:41,925 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:21:41,925 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:41,925 INFO L85 PathProgramCache]: Analyzing trace with hash -1542798367, now seen corresponding path program 1 times [2021-12-15 17:21:41,925 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:41,925 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1418461635] [2021-12-15 17:21:41,926 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:41,926 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:41,933 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:41,947 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:41,947 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:41,947 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1418461635] [2021-12-15 17:21:41,947 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1418461635] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:41,947 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:41,948 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:41,948 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [203500060] [2021-12-15 17:21:41,948 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:41,948 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:21:41,948 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:21:41,949 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-15 17:21:41,949 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-15 17:21:41,949 INFO L87 Difference]: Start difference. First operand 20710 states and 29745 transitions. cyclomatic complexity: 9043 Second operand has 4 states, 4 states have (on average 26.0) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:42,323 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:21:42,323 INFO L93 Difference]: Finished difference Result 48067 states and 68632 transitions. [2021-12-15 17:21:42,323 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-15 17:21:42,324 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 48067 states and 68632 transitions. [2021-12-15 17:21:42,509 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 47778 [2021-12-15 17:21:42,640 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 48067 states to 48067 states and 68632 transitions. [2021-12-15 17:21:42,640 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 48067 [2021-12-15 17:21:42,899 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 48067 [2021-12-15 17:21:42,899 INFO L73 IsDeterministic]: Start isDeterministic. Operand 48067 states and 68632 transitions. [2021-12-15 17:21:42,925 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:21:42,925 INFO L681 BuchiCegarLoop]: Abstraction has 48067 states and 68632 transitions. [2021-12-15 17:21:42,940 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 48067 states and 68632 transitions. [2021-12-15 17:21:43,299 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 48067 to 38841. [2021-12-15 17:21:43,345 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 38841 states, 38841 states have (on average 1.4317345073504801) internal successors, (55610), 38840 states have internal predecessors, (55610), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:43,417 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 38841 states to 38841 states and 55610 transitions. [2021-12-15 17:21:43,417 INFO L704 BuchiCegarLoop]: Abstraction has 38841 states and 55610 transitions. [2021-12-15 17:21:43,417 INFO L587 BuchiCegarLoop]: Abstraction has 38841 states and 55610 transitions. [2021-12-15 17:21:43,417 INFO L425 BuchiCegarLoop]: ======== Iteration 16============ [2021-12-15 17:21:43,417 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 38841 states and 55610 transitions. [2021-12-15 17:21:43,519 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 38664 [2021-12-15 17:21:43,519 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:21:43,519 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:21:43,521 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:43,521 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:43,522 INFO L791 eck$LassoCheckResult]: Stem: 193302#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 193303#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 193644#L1235 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 192696#L574 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 192697#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 192966#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 192967#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 193542#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 193527#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 193041#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 193042#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 193280#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 193281#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 193129#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 193130#L838 assume !(0 == ~M_E~0); 193288#L838-2 assume !(0 == ~T1_E~0); 192658#L843-1 assume !(0 == ~T2_E~0); 192659#L848-1 assume !(0 == ~T3_E~0); 192776#L853-1 assume !(0 == ~T4_E~0); 193115#L858-1 assume !(0 == ~T5_E~0); 192605#L863-1 assume !(0 == ~T6_E~0); 192606#L868-1 assume !(0 == ~T7_E~0); 193602#L873-1 assume !(0 == ~T8_E~0); 193598#L878-1 assume !(0 == ~E_1~0); 193570#L883-1 assume !(0 == ~E_2~0); 193571#L888-1 assume !(0 == ~E_3~0); 193253#L893-1 assume !(0 == ~E_4~0); 193254#L898-1 assume !(0 == ~E_5~0); 193621#L903-1 assume !(0 == ~E_6~0); 193568#L908-1 assume !(0 == ~E_7~0); 193392#L913-1 assume !(0 == ~E_8~0); 192672#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 192673#L402 assume !(1 == ~m_pc~0); 192882#L402-2 is_master_triggered_~__retres1~0#1 := 0; 192800#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 192801#L414 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 193049#L1035 assume !(0 != activate_threads_~tmp~1#1); 193050#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 193105#L421 assume !(1 == ~t1_pc~0); 193562#L421-2 is_transmit1_triggered_~__retres1~1#1 := 0; 193603#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 193097#L433 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 193098#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 193157#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 193613#L440 assume !(1 == ~t2_pc~0); 193660#L440-2 is_transmit2_triggered_~__retres1~2#1 := 0; 192810#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 192811#L452 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 193632#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 193410#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 192997#L459 assume !(1 == ~t3_pc~0); 192998#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 193560#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 193327#L471 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 192793#L1059 assume !(0 != activate_threads_~tmp___2~0#1); 192794#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 192804#L478 assume !(1 == ~t4_pc~0); 192805#L478-2 is_transmit4_triggered_~__retres1~4#1 := 0; 193468#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 193541#L490 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 192972#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 192716#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 192717#L497 assume !(1 == ~t5_pc~0); 192762#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 192763#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 193063#L509 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 193064#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 193552#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 193553#L516 assume !(1 == ~t6_pc~0); 193484#L516-2 is_transmit6_triggered_~__retres1~6#1 := 0; 193278#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 193279#L528 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 192849#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 192850#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 193270#L535 assume !(1 == ~t7_pc~0); 193271#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 193346#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 193347#L547 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 193381#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 193370#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 193371#L554 assume 1 == ~t8_pc~0; 193311#L555 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 192635#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 193435#L566 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 192934#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 192935#L1099-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 192618#L931 assume 1 == ~M_E~0;~M_E~0 := 2; 192619#L931-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 193589#L936-1 assume !(1 == ~T2_E~0); 193630#L941-1 assume !(1 == ~T3_E~0); 193106#L946-1 assume !(1 == ~T4_E~0); 193107#L951-1 assume !(1 == ~T5_E~0); 192864#L956-1 assume !(1 == ~T6_E~0); 192865#L961-1 assume !(1 == ~T7_E~0); 193255#L966-1 assume !(1 == ~T8_E~0); 193256#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 222950#L976-1 assume !(1 == ~E_2~0); 193337#L981-1 assume !(1 == ~E_3~0); 193338#L986-1 assume !(1 == ~E_4~0); 222934#L991-1 assume !(1 == ~E_5~0); 222928#L996-1 assume !(1 == ~E_6~0); 222916#L1001-1 assume !(1 == ~E_7~0); 222912#L1006-1 assume !(1 == ~E_8~0); 222902#L1011-1 assume { :end_inline_reset_delta_events } true; 222900#L1272-2 [2021-12-15 17:21:43,523 INFO L793 eck$LassoCheckResult]: Loop: 222900#L1272-2 assume !false; 222888#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 222839#L813 assume !false; 222836#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 222734#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 222725#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 222723#L682 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 222719#L696 assume !(0 != eval_~tmp~0#1); 222720#L828 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 231296#L574-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 231293#L838-3 assume !(0 == ~M_E~0); 231291#L838-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 231290#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 231289#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 231288#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 231286#L858-3 assume !(0 == ~T5_E~0); 231283#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 230565#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 230564#L873-3 assume !(0 == ~T8_E~0); 230563#L878-3 assume 0 == ~E_1~0;~E_1~0 := 1; 230562#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 230560#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 230539#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 230535#L898-3 assume !(0 == ~E_5~0); 230514#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 230500#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 230494#L913-3 assume !(0 == ~E_8~0); 230476#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 230470#L402-27 assume !(1 == ~m_pc~0); 230463#L402-29 is_master_triggered_~__retres1~0#1 := 0; 230455#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 230454#L414-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 230436#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 230402#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 230393#L421-27 assume !(1 == ~t1_pc~0); 230386#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 230364#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 230357#L433-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 230354#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 230352#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 224206#L440-27 assume !(1 == ~t2_pc~0); 224204#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 224201#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 224199#L452-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 224197#L1051-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 224195#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 224193#L459-27 assume 1 == ~t3_pc~0; 224191#L460-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 224192#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 224295#L471-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 224182#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 224181#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 223175#L478-27 assume !(1 == ~t4_pc~0); 223172#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 223170#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 223168#L490-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 223166#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 223164#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 223162#L497-27 assume !(1 == ~t5_pc~0); 223159#L497-29 is_transmit5_triggered_~__retres1~5#1 := 0; 223157#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 223155#L509-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 223152#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 223150#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 223148#L516-27 assume !(1 == ~t6_pc~0); 204503#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 223145#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 223143#L528-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 223142#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 223140#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 223138#L535-27 assume 1 == ~t7_pc~0; 223136#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 223133#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 223131#L547-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 223128#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 223126#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 223124#L554-27 assume !(1 == ~t8_pc~0); 223122#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 223119#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 223117#L566-9 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 223114#L1099-27 assume !(0 != activate_threads_~tmp___7~0#1); 223112#L1099-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 223110#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 223107#L931-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 223105#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 223103#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 223101#L946-3 assume !(1 == ~T4_E~0); 223099#L951-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 223095#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 223093#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 223091#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 223089#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 223087#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 223085#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 223083#L986-3 assume !(1 == ~E_4~0); 223081#L991-3 assume 1 == ~E_5~0;~E_5~0 := 2; 223077#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 223075#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 223073#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 223071#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 223069#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 223059#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 223058#L682-1 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 223057#L1291 assume !(0 == start_simulation_~tmp~3#1); 223054#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 222989#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 222987#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 222985#L682-2 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 222982#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 222980#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 222978#L1254 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 222901#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 222900#L1272-2 [2021-12-15 17:21:43,523 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:43,523 INFO L85 PathProgramCache]: Analyzing trace with hash -1252918242, now seen corresponding path program 1 times [2021-12-15 17:21:43,524 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:43,524 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [561146193] [2021-12-15 17:21:43,524 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:43,524 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:43,531 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:43,549 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:43,549 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:43,549 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [561146193] [2021-12-15 17:21:43,549 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [561146193] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:43,549 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:43,549 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:43,549 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1079591503] [2021-12-15 17:21:43,550 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:43,550 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:21:43,550 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:43,550 INFO L85 PathProgramCache]: Analyzing trace with hash 1965280958, now seen corresponding path program 1 times [2021-12-15 17:21:43,551 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:43,551 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [94114404] [2021-12-15 17:21:43,551 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:43,551 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:43,558 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:43,572 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:43,573 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:43,573 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [94114404] [2021-12-15 17:21:43,573 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [94114404] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:43,573 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:43,573 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:43,573 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [853022221] [2021-12-15 17:21:43,573 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:43,574 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:21:43,574 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:21:43,574 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-15 17:21:43,574 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-15 17:21:43,574 INFO L87 Difference]: Start difference. First operand 38841 states and 55610 transitions. cyclomatic complexity: 16777 Second operand has 4 states, 4 states have (on average 26.0) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:44,049 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:21:44,050 INFO L93 Difference]: Finished difference Result 94836 states and 134699 transitions. [2021-12-15 17:21:44,050 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-15 17:21:44,050 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 94836 states and 134699 transitions. [2021-12-15 17:21:44,795 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 94404 [2021-12-15 17:21:45,183 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 94836 states to 94836 states and 134699 transitions. [2021-12-15 17:21:45,184 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 94836 [2021-12-15 17:21:45,225 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 94836 [2021-12-15 17:21:45,226 INFO L73 IsDeterministic]: Start isDeterministic. Operand 94836 states and 134699 transitions. [2021-12-15 17:21:45,277 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:21:45,278 INFO L681 BuchiCegarLoop]: Abstraction has 94836 states and 134699 transitions. [2021-12-15 17:21:45,310 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 94836 states and 134699 transitions. [2021-12-15 17:21:46,025 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 94836 to 76768. [2021-12-15 17:21:46,133 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 76768 states, 76768 states have (on average 1.4232883493122135) internal successors, (109263), 76767 states have internal predecessors, (109263), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:46,295 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 76768 states to 76768 states and 109263 transitions. [2021-12-15 17:21:46,296 INFO L704 BuchiCegarLoop]: Abstraction has 76768 states and 109263 transitions. [2021-12-15 17:21:46,296 INFO L587 BuchiCegarLoop]: Abstraction has 76768 states and 109263 transitions. [2021-12-15 17:21:46,296 INFO L425 BuchiCegarLoop]: ======== Iteration 17============ [2021-12-15 17:21:46,296 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 76768 states and 109263 transitions. [2021-12-15 17:21:46,541 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 76560 [2021-12-15 17:21:46,541 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:21:46,541 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:21:46,546 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:46,546 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:46,547 INFO L791 eck$LassoCheckResult]: Stem: 327003#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 327004#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 327394#L1235 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 326383#L574 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 326384#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 326655#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 326656#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 327267#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 327250#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 326735#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 326736#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 326982#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 326983#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 326820#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 326821#L838 assume !(0 == ~M_E~0); 326992#L838-2 assume !(0 == ~T1_E~0); 326345#L843-1 assume !(0 == ~T2_E~0); 326346#L848-1 assume !(0 == ~T3_E~0); 326462#L853-1 assume !(0 == ~T4_E~0); 326808#L858-1 assume !(0 == ~T5_E~0); 326294#L863-1 assume !(0 == ~T6_E~0); 326295#L868-1 assume !(0 == ~T7_E~0); 327333#L873-1 assume !(0 == ~T8_E~0); 327330#L878-1 assume !(0 == ~E_1~0); 327303#L883-1 assume !(0 == ~E_2~0); 327304#L888-1 assume !(0 == ~E_3~0); 326953#L893-1 assume !(0 == ~E_4~0); 326954#L898-1 assume !(0 == ~E_5~0); 327361#L903-1 assume !(0 == ~E_6~0); 327299#L908-1 assume !(0 == ~E_7~0); 327097#L913-1 assume !(0 == ~E_8~0); 326359#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 326360#L402 assume !(1 == ~m_pc~0); 326571#L402-2 is_master_triggered_~__retres1~0#1 := 0; 326484#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 326485#L414 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 326743#L1035 assume !(0 != activate_threads_~tmp~1#1); 326744#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 326797#L421 assume !(1 == ~t1_pc~0); 327291#L421-2 is_transmit1_triggered_~__retres1~1#1 := 0; 327339#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 326787#L433 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 326788#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 326851#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 327351#L440 assume !(1 == ~t2_pc~0); 327414#L440-2 is_transmit2_triggered_~__retres1~2#1 := 0; 326493#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 326494#L452 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 327377#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 327118#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 326694#L459 assume !(1 == ~t3_pc~0); 326695#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 327286#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 327031#L471 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 326477#L1059 assume !(0 != activate_threads_~tmp___2~0#1); 326478#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 326488#L478 assume !(1 == ~t4_pc~0); 326489#L478-2 is_transmit4_triggered_~__retres1~4#1 := 0; 327182#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 327266#L490 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 326661#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 326405#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 326406#L497 assume !(1 == ~t5_pc~0); 326448#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 326449#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 326757#L509 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 326758#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 327278#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 327279#L516 assume !(1 == ~t6_pc~0); 327201#L516-2 is_transmit6_triggered_~__retres1~6#1 := 0; 326979#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 326980#L528 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 326533#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 326534#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 326970#L535 assume !(1 == ~t7_pc~0); 326971#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 327047#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 327048#L547 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 327084#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 327073#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 327074#L554 assume !(1 == ~t8_pc~0); 326321#L554-2 is_transmit8_triggered_~__retres1~8#1 := 0; 326322#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 327143#L566 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 326625#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 326626#L1099-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 326305#L931 assume 1 == ~M_E~0;~M_E~0 := 2; 326306#L931-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 327321#L936-1 assume !(1 == ~T2_E~0); 358845#L941-1 assume !(1 == ~T3_E~0); 358843#L946-1 assume !(1 == ~T4_E~0); 358840#L951-1 assume !(1 == ~T5_E~0); 358841#L956-1 assume !(1 == ~T6_E~0); 360278#L961-1 assume !(1 == ~T7_E~0); 360277#L966-1 assume !(1 == ~T8_E~0); 360276#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 360275#L976-1 assume !(1 == ~E_2~0); 360274#L981-1 assume !(1 == ~E_3~0); 360273#L986-1 assume !(1 == ~E_4~0); 360269#L991-1 assume !(1 == ~E_5~0); 326581#L996-1 assume !(1 == ~E_6~0); 360266#L1001-1 assume !(1 == ~E_7~0); 360261#L1006-1 assume !(1 == ~E_8~0); 360257#L1011-1 assume { :end_inline_reset_delta_events } true; 360251#L1272-2 [2021-12-15 17:21:46,547 INFO L793 eck$LassoCheckResult]: Loop: 360251#L1272-2 assume !false; 360250#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 360247#L813 assume !false; 360246#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 360244#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 360236#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 360232#L682 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 360229#L696 assume !(0 != eval_~tmp~0#1); 360230#L828 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 402971#L574-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 402970#L838-3 assume !(0 == ~M_E~0); 402969#L838-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 402968#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 402966#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 402964#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 402963#L858-3 assume !(0 == ~T5_E~0); 402962#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 402961#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 402960#L873-3 assume !(0 == ~T8_E~0); 402959#L878-3 assume 0 == ~E_1~0;~E_1~0 := 1; 402958#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 402957#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 402956#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 402955#L898-3 assume !(0 == ~E_5~0); 402954#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 402953#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 402952#L913-3 assume !(0 == ~E_8~0); 402951#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 402950#L402-27 assume !(1 == ~m_pc~0); 402948#L402-29 is_master_triggered_~__retres1~0#1 := 0; 402945#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 402943#L414-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 327324#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 327236#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 327237#L421-27 assume !(1 == ~t1_pc~0); 326594#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 326595#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 326864#L433-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 326865#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 327344#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 326973#L440-27 assume !(1 == ~t2_pc~0); 326974#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 327200#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 402671#L452-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 402670#L1051-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 402669#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 402667#L459-27 assume !(1 == ~t3_pc~0); 402664#L459-29 is_transmit3_triggered_~__retres1~3#1 := 0; 402663#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 402661#L471-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 402659#L1059-27 assume !(0 != activate_threads_~tmp___2~0#1); 402657#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 396914#L478-27 assume !(1 == ~t4_pc~0); 396907#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 396901#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 396897#L490-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 396893#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 396889#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 396885#L497-27 assume 1 == ~t5_pc~0; 396880#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 396873#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 396869#L509-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 396865#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 396733#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 362555#L516-27 assume !(1 == ~t6_pc~0); 362552#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 362551#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 362548#L528-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 362546#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 362544#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 362442#L535-27 assume 1 == ~t7_pc~0; 362439#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 362435#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 362433#L547-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 362431#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 361585#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 361584#L554-27 assume !(1 == ~t8_pc~0); 344284#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 361582#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 361579#L566-9 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 361577#L1099-27 assume !(0 != activate_threads_~tmp___7~0#1); 361575#L1099-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 361573#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 359034#L931-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 361568#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 361567#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 361564#L946-3 assume !(1 == ~T4_E~0); 361562#L951-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 361558#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 361556#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 361554#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 361552#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 361545#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 361541#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 361539#L986-3 assume !(1 == ~E_4~0); 361267#L991-3 assume 1 == ~E_5~0;~E_5~0 := 2; 361263#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 361260#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 361258#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 361256#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 361213#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 361202#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 361200#L682-1 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 361198#L1291 assume !(0 == start_simulation_~tmp~3#1); 361195#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 361182#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 361180#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 361178#L682-2 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 361176#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 361174#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 361172#L1254 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 360256#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 360251#L1272-2 [2021-12-15 17:21:46,547 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:46,548 INFO L85 PathProgramCache]: Analyzing trace with hash 1451654077, now seen corresponding path program 1 times [2021-12-15 17:21:46,548 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:46,548 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1743004007] [2021-12-15 17:21:46,548 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:46,548 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:46,556 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:46,570 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:46,570 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:46,571 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1743004007] [2021-12-15 17:21:46,571 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1743004007] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:46,571 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:46,571 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-15 17:21:46,571 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [777294499] [2021-12-15 17:21:46,571 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:46,572 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:21:46,572 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:46,572 INFO L85 PathProgramCache]: Analyzing trace with hash 1363777404, now seen corresponding path program 1 times [2021-12-15 17:21:46,572 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:46,572 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1328427319] [2021-12-15 17:21:46,572 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:46,573 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:46,580 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:46,595 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:46,595 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:46,595 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1328427319] [2021-12-15 17:21:46,595 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1328427319] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:46,596 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:46,596 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:46,596 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [572081017] [2021-12-15 17:21:46,596 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:46,596 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:21:46,596 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:21:46,597 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:21:46,597 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:21:46,597 INFO L87 Difference]: Start difference. First operand 76768 states and 109263 transitions. cyclomatic complexity: 32503 Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 2 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:47,146 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:21:47,146 INFO L93 Difference]: Finished difference Result 96323 states and 136291 transitions. [2021-12-15 17:21:47,147 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:21:47,147 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 96323 states and 136291 transitions. [2021-12-15 17:21:47,473 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 96112 [2021-12-15 17:21:47,673 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 96323 states to 96323 states and 136291 transitions. [2021-12-15 17:21:47,673 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 96323 [2021-12-15 17:21:47,720 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 96323 [2021-12-15 17:21:47,720 INFO L73 IsDeterministic]: Start isDeterministic. Operand 96323 states and 136291 transitions. [2021-12-15 17:21:47,768 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:21:47,768 INFO L681 BuchiCegarLoop]: Abstraction has 96323 states and 136291 transitions. [2021-12-15 17:21:47,811 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 96323 states and 136291 transitions. [2021-12-15 17:21:48,445 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 96323 to 41343. [2021-12-15 17:21:48,483 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 41343 states, 41343 states have (on average 1.4237476719154392) internal successors, (58862), 41342 states have internal predecessors, (58862), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:48,545 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 41343 states to 41343 states and 58862 transitions. [2021-12-15 17:21:48,545 INFO L704 BuchiCegarLoop]: Abstraction has 41343 states and 58862 transitions. [2021-12-15 17:21:48,545 INFO L587 BuchiCegarLoop]: Abstraction has 41343 states and 58862 transitions. [2021-12-15 17:21:48,545 INFO L425 BuchiCegarLoop]: ======== Iteration 18============ [2021-12-15 17:21:48,546 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 41343 states and 58862 transitions. [2021-12-15 17:21:48,659 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 41200 [2021-12-15 17:21:48,660 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:21:48,660 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:21:48,664 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:48,665 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:48,666 INFO L791 eck$LassoCheckResult]: Stem: 500094#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 500095#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 500479#L1235 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 499477#L574 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 499478#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 499747#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 499748#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 500356#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 500333#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 499825#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 499826#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 500071#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 500072#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 499908#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 499909#L838 assume !(0 == ~M_E~0); 500080#L838-2 assume !(0 == ~T1_E~0); 499439#L843-1 assume !(0 == ~T2_E~0); 499440#L848-1 assume !(0 == ~T3_E~0); 499556#L853-1 assume !(0 == ~T4_E~0); 499894#L858-1 assume !(0 == ~T5_E~0); 499390#L863-1 assume !(0 == ~T6_E~0); 499391#L868-1 assume !(0 == ~T7_E~0); 500422#L873-1 assume !(0 == ~T8_E~0); 500420#L878-1 assume !(0 == ~E_1~0); 500390#L883-1 assume !(0 == ~E_2~0); 500391#L888-1 assume !(0 == ~E_3~0); 500041#L893-1 assume !(0 == ~E_4~0); 500042#L898-1 assume !(0 == ~E_5~0); 500444#L903-1 assume !(0 == ~E_6~0); 500388#L908-1 assume !(0 == ~E_7~0); 500193#L913-1 assume !(0 == ~E_8~0); 499453#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 499454#L402 assume !(1 == ~m_pc~0); 499660#L402-2 is_master_triggered_~__retres1~0#1 := 0; 499578#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 499579#L414 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 499833#L1035 assume !(0 != activate_threads_~tmp~1#1); 499834#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 499885#L421 assume !(1 == ~t1_pc~0); 500382#L421-2 is_transmit1_triggered_~__retres1~1#1 := 0; 500423#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 499876#L433 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 499877#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 499939#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 500437#L440 assume !(1 == ~t2_pc~0); 500501#L440-2 is_transmit2_triggered_~__retres1~2#1 := 0; 499588#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 499589#L452 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 500461#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 500209#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 499780#L459 assume !(1 == ~t3_pc~0); 499781#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 500380#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 500122#L471 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 499571#L1059 assume !(0 != activate_threads_~tmp___2~0#1); 499572#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 499582#L478 assume !(1 == ~t4_pc~0); 499583#L478-2 is_transmit4_triggered_~__retres1~4#1 := 0; 500266#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 500354#L490 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 499753#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 499497#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 499498#L497 assume !(1 == ~t5_pc~0); 499542#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 499543#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 499846#L509 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 499847#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 500371#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 500372#L516 assume !(1 == ~t6_pc~0); 500281#L516-2 is_transmit6_triggered_~__retres1~6#1 := 0; 500069#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 500070#L528 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 499626#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 499627#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 500061#L535 assume !(1 == ~t7_pc~0); 500062#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 500142#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 500143#L547 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 500181#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 500169#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 500170#L554 assume !(1 == ~t8_pc~0); 499418#L554-2 is_transmit8_triggered_~__retres1~8#1 := 0; 499419#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 500233#L566 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 499714#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 499715#L1099-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 499403#L931 assume !(1 == ~M_E~0); 499404#L931-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 500405#L936-1 assume !(1 == ~T2_E~0); 500458#L941-1 assume !(1 == ~T3_E~0); 499886#L946-1 assume !(1 == ~T4_E~0); 499887#L951-1 assume !(1 == ~T5_E~0); 499642#L956-1 assume !(1 == ~T6_E~0); 499643#L961-1 assume !(1 == ~T7_E~0); 500043#L966-1 assume !(1 == ~T8_E~0); 500044#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 500172#L976-1 assume !(1 == ~E_2~0); 500133#L981-1 assume !(1 == ~E_3~0); 499891#L986-1 assume !(1 == ~E_4~0); 499673#L991-1 assume !(1 == ~E_5~0); 499674#L996-1 assume !(1 == ~E_6~0); 500430#L1001-1 assume !(1 == ~E_7~0); 500092#L1006-1 assume !(1 == ~E_8~0); 500093#L1011-1 assume { :end_inline_reset_delta_events } true; 500381#L1272-2 [2021-12-15 17:21:48,666 INFO L793 eck$LassoCheckResult]: Loop: 500381#L1272-2 assume !false; 532327#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 532323#L813 assume !false; 532322#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 532320#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 532312#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 532311#L682 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 532310#L696 assume !(0 != eval_~tmp~0#1); 500096#L828 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 500097#L574-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 540614#L838-3 assume !(0 == ~M_E~0); 500148#L838-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 500149#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 499989#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 499990#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 500268#L858-3 assume !(0 == ~T5_E~0); 500118#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 500119#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 540597#L873-3 assume !(0 == ~T8_E~0); 540594#L878-3 assume 0 == ~E_1~0;~E_1~0 := 1; 499426#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 499427#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 499428#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 499429#L898-3 assume !(0 == ~E_5~0); 500287#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 500288#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 499925#L913-3 assume !(0 == ~E_8~0); 499926#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 500496#L402-27 assume !(1 == ~m_pc~0); 499421#L402-29 is_master_triggered_~__retres1~0#1 := 0; 500475#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 499916#L414-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 499917#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 500411#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 500351#L421-27 assume !(1 == ~t1_pc~0); 499687#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 499688#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 499953#L433-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 499954#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 500431#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 500064#L440-27 assume !(1 == ~t2_pc~0); 500065#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 500282#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 499774#L452-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 499775#L1051-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 499964#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 499676#L459-27 assume 1 == ~t3_pc~0; 499678#L460-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 500137#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 499738#L471-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 499739#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 500060#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 500421#L478-27 assume !(1 == ~t4_pc~0); 499665#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 499666#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 540102#L490-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 500236#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 500237#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 500289#L497-27 assume 1 == ~t5_pc~0; 500290#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 499703#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 499704#L509-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 499648#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 499649#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 530199#L516-27 assume !(1 == ~t6_pc~0); 530196#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 530194#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 530192#L528-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 530190#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 530188#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 530186#L535-27 assume 1 == ~t7_pc~0; 530184#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 530180#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 530178#L547-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 530176#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 530174#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 522856#L554-27 assume !(1 == ~t8_pc~0); 522852#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 522849#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 522845#L566-9 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 522439#L1099-27 assume !(0 != activate_threads_~tmp___7~0#1); 522438#L1099-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 522437#L931-3 assume !(1 == ~M_E~0); 513617#L931-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 522436#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 522435#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 522434#L946-3 assume !(1 == ~T4_E~0); 522433#L951-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 522432#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 522431#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 522430#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 522429#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 522428#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 522427#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 522426#L986-3 assume !(1 == ~E_4~0); 522425#L991-3 assume 1 == ~E_5~0;~E_5~0 := 2; 522424#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 522423#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 522422#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 522421#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 522420#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 522411#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 522410#L682-1 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 513763#L1291 assume !(0 == start_simulation_~tmp~3#1); 513764#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 532349#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 532348#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 532344#L682-2 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 532342#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 532340#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 532336#L1254 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 532332#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 500381#L1272-2 [2021-12-15 17:21:48,666 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:48,667 INFO L85 PathProgramCache]: Analyzing trace with hash -542490629, now seen corresponding path program 1 times [2021-12-15 17:21:48,667 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:48,667 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [452588395] [2021-12-15 17:21:48,667 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:48,667 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:48,674 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:48,690 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:48,691 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:48,691 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [452588395] [2021-12-15 17:21:48,691 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [452588395] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:48,691 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:48,691 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:48,692 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1247623974] [2021-12-15 17:21:48,692 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:48,692 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:21:48,692 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:48,692 INFO L85 PathProgramCache]: Analyzing trace with hash 1885111965, now seen corresponding path program 1 times [2021-12-15 17:21:48,693 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:48,693 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1689359163] [2021-12-15 17:21:48,693 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:48,693 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:48,703 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:48,715 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:48,715 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:48,716 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1689359163] [2021-12-15 17:21:48,716 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1689359163] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:48,716 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:48,716 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:48,716 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [193625788] [2021-12-15 17:21:48,716 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:48,717 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:21:48,717 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:21:48,718 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-15 17:21:48,718 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-15 17:21:48,718 INFO L87 Difference]: Start difference. First operand 41343 states and 58862 transitions. cyclomatic complexity: 17521 Second operand has 4 states, 4 states have (on average 26.0) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:49,146 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:21:49,147 INFO L93 Difference]: Finished difference Result 65678 states and 93097 transitions. [2021-12-15 17:21:49,147 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-15 17:21:49,148 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 65678 states and 93097 transitions. [2021-12-15 17:21:49,379 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 65424 [2021-12-15 17:21:49,513 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 65678 states to 65678 states and 93097 transitions. [2021-12-15 17:21:49,513 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 65678 [2021-12-15 17:21:49,548 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 65678 [2021-12-15 17:21:49,548 INFO L73 IsDeterministic]: Start isDeterministic. Operand 65678 states and 93097 transitions. [2021-12-15 17:21:49,581 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:21:49,581 INFO L681 BuchiCegarLoop]: Abstraction has 65678 states and 93097 transitions. [2021-12-15 17:21:49,613 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 65678 states and 93097 transitions. [2021-12-15 17:21:50,146 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 65678 to 46638. [2021-12-15 17:21:50,187 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 46638 states, 46638 states have (on average 1.4229169346884514) internal successors, (66362), 46637 states have internal predecessors, (66362), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:50,257 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 46638 states to 46638 states and 66362 transitions. [2021-12-15 17:21:50,257 INFO L704 BuchiCegarLoop]: Abstraction has 46638 states and 66362 transitions. [2021-12-15 17:21:50,258 INFO L587 BuchiCegarLoop]: Abstraction has 46638 states and 66362 transitions. [2021-12-15 17:21:50,258 INFO L425 BuchiCegarLoop]: ======== Iteration 19============ [2021-12-15 17:21:50,258 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 46638 states and 66362 transitions. [2021-12-15 17:21:50,405 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 46416 [2021-12-15 17:21:50,406 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:21:50,406 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:21:50,412 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:50,413 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:50,413 INFO L791 eck$LassoCheckResult]: Stem: 607125#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 607126#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 607532#L1235 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 606508#L574 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 606509#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 606777#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 606778#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 607391#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 607374#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 606851#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 606852#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 607102#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 607103#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 606940#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 606941#L838 assume !(0 == ~M_E~0); 607112#L838-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 606470#L843-1 assume !(0 == ~T2_E~0); 606471#L848-1 assume !(0 == ~T3_E~0); 607133#L853-1 assume !(0 == ~T4_E~0); 607134#L858-1 assume !(0 == ~T5_E~0); 606421#L863-1 assume !(0 == ~T6_E~0); 606422#L868-1 assume !(0 == ~T7_E~0); 607543#L873-1 assume !(0 == ~T8_E~0); 607544#L878-1 assume !(0 == ~E_1~0); 607432#L883-1 assume !(0 == ~E_2~0); 607433#L888-1 assume !(0 == ~E_3~0); 607072#L893-1 assume !(0 == ~E_4~0); 607073#L898-1 assume !(0 == ~E_5~0); 607572#L903-1 assume !(0 == ~E_6~0); 607573#L908-1 assume !(0 == ~E_7~0); 607608#L913-1 assume !(0 == ~E_8~0); 607607#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 607605#L402 assume !(1 == ~m_pc~0); 607604#L402-2 is_master_triggered_~__retres1~0#1 := 0; 606612#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 606613#L414 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 606858#L1035 assume !(0 != activate_threads_~tmp~1#1); 606859#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 607417#L421 assume !(1 == ~t1_pc~0); 607418#L421-2 is_transmit1_triggered_~__retres1~1#1 := 0; 607555#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 607556#L433 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 606969#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 606970#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 607562#L440 assume !(1 == ~t2_pc~0); 607563#L440-2 is_transmit2_triggered_~__retres1~2#1 := 0; 606621#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 606622#L452 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 607520#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 607242#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 607243#L459 assume !(1 == ~t3_pc~0); 607414#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 607415#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 607484#L471 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 606606#L1059 assume !(0 != activate_threads_~tmp___2~0#1); 606607#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 607574#L478 assume !(1 == ~t4_pc~0); 607308#L478-2 is_transmit4_triggered_~__retres1~4#1 := 0; 607309#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 607514#L490 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 607515#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 606528#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 606529#L497 assume !(1 == ~t5_pc~0); 606573#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 606574#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 606871#L509 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 606872#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 607407#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 607408#L516 assume !(1 == ~t6_pc~0); 607550#L516-2 is_transmit6_triggered_~__retres1~6#1 := 0; 607100#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 607101#L528 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 607590#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 607589#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 607092#L535 assume !(1 == ~t7_pc~0); 607093#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 607588#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 607326#L547 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 607212#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 607202#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 607203#L554 assume !(1 == ~t8_pc~0); 607585#L554-2 is_transmit8_triggered_~__retres1~8#1 := 0; 607516#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 607517#L566 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 606743#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 606744#L1099-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 606434#L931 assume !(1 == ~M_E~0); 606435#L931-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 607450#L936-1 assume !(1 == ~T2_E~0); 607513#L941-1 assume !(1 == ~T3_E~0); 606915#L946-1 assume !(1 == ~T4_E~0); 606916#L951-1 assume !(1 == ~T5_E~0); 606673#L956-1 assume !(1 == ~T6_E~0); 606674#L961-1 assume !(1 == ~T7_E~0); 607074#L966-1 assume !(1 == ~T8_E~0); 607075#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 607205#L976-1 assume !(1 == ~E_2~0); 607166#L981-1 assume !(1 == ~E_3~0); 606920#L986-1 assume !(1 == ~E_4~0); 606703#L991-1 assume !(1 == ~E_5~0); 606704#L996-1 assume !(1 == ~E_6~0); 607478#L1001-1 assume !(1 == ~E_7~0); 607123#L1006-1 assume !(1 == ~E_8~0); 607124#L1011-1 assume { :end_inline_reset_delta_events } true; 607416#L1272-2 [2021-12-15 17:21:50,413 INFO L793 eck$LassoCheckResult]: Loop: 607416#L1272-2 assume !false; 636922#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 636551#L813 assume !false; 636921#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 636919#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 636911#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 636908#L682 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 636905#L696 assume !(0 != eval_~tmp~0#1); 636906#L828 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 607289#L574-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 607290#L838-3 assume !(0 == ~M_E~0); 607181#L838-5 assume !(0 == ~T1_E~0); 607183#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 653058#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 607076#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 607077#L858-3 assume !(0 == ~T5_E~0); 607152#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 607141#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 607142#L873-3 assume !(0 == ~T8_E~0); 606725#L878-3 assume 0 == ~E_1~0;~E_1~0 := 1; 606457#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 606458#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 606459#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 606460#L898-3 assume !(0 == ~E_5~0); 606944#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 653032#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 606956#L913-3 assume !(0 == ~E_8~0); 606500#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 606501#L402-27 assume !(1 == ~m_pc~0); 606452#L402-29 is_master_triggered_~__retres1~0#1 := 0; 606962#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 606947#L414-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 606948#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 607359#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 607360#L421-27 assume !(1 == ~t1_pc~0); 652912#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 652908#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 652904#L433-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 652900#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 652895#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 607095#L440-27 assume !(1 == ~t2_pc~0); 607096#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 652817#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 652815#L452-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 652813#L1051-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 652811#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 652807#L459-27 assume !(1 == ~t3_pc~0); 652803#L459-29 is_transmit3_triggered_~__retres1~3#1 := 0; 652801#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 652799#L471-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 652796#L1059-27 assume !(0 != activate_threads_~tmp___2~0#1); 652793#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 607551#L478-27 assume !(1 == ~t4_pc~0); 607552#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 652708#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 652707#L490-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 652706#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 652705#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 652704#L497-27 assume 1 == ~t5_pc~0; 652703#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 652700#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 652698#L509-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 652696#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 652694#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 606949#L516-27 assume !(1 == ~t6_pc~0); 606950#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 652554#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 652553#L528-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 652552#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 652551#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 652550#L535-27 assume 1 == ~t7_pc~0; 652547#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 652544#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 652542#L547-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 607524#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 607525#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 649672#L554-27 assume !(1 == ~t8_pc~0); 649670#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 649667#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 649666#L566-9 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 649660#L1099-27 assume !(0 != activate_threads_~tmp___7~0#1); 649653#L1099-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 649646#L931-3 assume !(1 == ~M_E~0); 623544#L931-5 assume !(1 == ~T1_E~0); 649635#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 649633#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 649632#L946-3 assume !(1 == ~T4_E~0); 649630#L951-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 649628#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 649626#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 649624#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 649622#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 647730#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 647728#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 647726#L986-3 assume !(1 == ~E_4~0); 647724#L991-3 assume 1 == ~E_5~0;~E_5~0 := 2; 647722#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 647720#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 647718#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 647716#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 647714#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 644565#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 644130#L682-1 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 619723#L1291 assume !(0 == start_simulation_~tmp~3#1); 619724#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 636933#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 636932#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 636930#L682-2 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 636928#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 636926#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 636924#L1254 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 636923#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 607416#L1272-2 [2021-12-15 17:21:50,414 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:50,414 INFO L85 PathProgramCache]: Analyzing trace with hash 228242937, now seen corresponding path program 1 times [2021-12-15 17:21:50,414 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:50,414 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [557615431] [2021-12-15 17:21:50,414 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:50,415 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:50,420 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:50,433 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:50,434 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:50,434 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [557615431] [2021-12-15 17:21:50,434 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [557615431] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:50,434 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:50,434 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:50,434 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1110296394] [2021-12-15 17:21:50,435 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:50,435 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:21:50,435 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:50,435 INFO L85 PathProgramCache]: Analyzing trace with hash 1465470654, now seen corresponding path program 1 times [2021-12-15 17:21:50,435 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:50,436 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1670428651] [2021-12-15 17:21:50,436 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:50,436 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:50,442 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:50,457 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:50,457 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:50,457 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1670428651] [2021-12-15 17:21:50,457 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1670428651] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:50,458 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:50,458 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:50,458 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [515297489] [2021-12-15 17:21:50,458 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:50,458 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:21:50,458 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:21:50,459 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-15 17:21:50,459 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-15 17:21:50,459 INFO L87 Difference]: Start difference. First operand 46638 states and 66362 transitions. cyclomatic complexity: 19726 Second operand has 4 states, 4 states have (on average 26.0) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:50,662 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:21:50,663 INFO L93 Difference]: Finished difference Result 60367 states and 85340 transitions. [2021-12-15 17:21:50,663 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-15 17:21:50,663 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 60367 states and 85340 transitions. [2021-12-15 17:21:50,938 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 60208 [2021-12-15 17:21:51,111 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 60367 states to 60367 states and 85340 transitions. [2021-12-15 17:21:51,111 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 60367 [2021-12-15 17:21:51,156 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 60367 [2021-12-15 17:21:51,157 INFO L73 IsDeterministic]: Start isDeterministic. Operand 60367 states and 85340 transitions. [2021-12-15 17:21:51,198 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:21:51,198 INFO L681 BuchiCegarLoop]: Abstraction has 60367 states and 85340 transitions. [2021-12-15 17:21:51,234 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 60367 states and 85340 transitions. [2021-12-15 17:21:51,845 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 60367 to 41343. [2021-12-15 17:21:51,878 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 41343 states, 41343 states have (on average 1.4190552209563891) internal successors, (58668), 41342 states have internal predecessors, (58668), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:51,940 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 41343 states to 41343 states and 58668 transitions. [2021-12-15 17:21:51,940 INFO L704 BuchiCegarLoop]: Abstraction has 41343 states and 58668 transitions. [2021-12-15 17:21:51,940 INFO L587 BuchiCegarLoop]: Abstraction has 41343 states and 58668 transitions. [2021-12-15 17:21:51,940 INFO L425 BuchiCegarLoop]: ======== Iteration 20============ [2021-12-15 17:21:51,941 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 41343 states and 58668 transitions. [2021-12-15 17:21:52,051 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 41200 [2021-12-15 17:21:52,052 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:21:52,052 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:21:52,083 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:52,084 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:52,084 INFO L791 eck$LassoCheckResult]: Stem: 714136#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 714137#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 714493#L1235 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 713525#L574 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 713526#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 713792#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 713793#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 714386#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 714371#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 713863#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 713864#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 714114#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 714115#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 713952#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 713953#L838 assume !(0 == ~M_E~0); 714124#L838-2 assume !(0 == ~T1_E~0); 713487#L843-1 assume !(0 == ~T2_E~0); 713488#L848-1 assume !(0 == ~T3_E~0); 713605#L853-1 assume !(0 == ~T4_E~0); 713940#L858-1 assume !(0 == ~T5_E~0); 713438#L863-1 assume !(0 == ~T6_E~0); 713439#L868-1 assume !(0 == ~T7_E~0); 714446#L873-1 assume !(0 == ~T8_E~0); 714443#L878-1 assume !(0 == ~E_1~0); 714419#L883-1 assume !(0 == ~E_2~0); 714420#L888-1 assume !(0 == ~E_3~0); 714084#L893-1 assume !(0 == ~E_4~0); 714085#L898-1 assume !(0 == ~E_5~0); 714468#L903-1 assume !(0 == ~E_6~0); 714417#L908-1 assume !(0 == ~E_7~0); 714230#L913-1 assume !(0 == ~E_8~0); 713501#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 713502#L402 assume !(1 == ~m_pc~0); 713713#L402-2 is_master_triggered_~__retres1~0#1 := 0; 713628#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 713629#L414 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 713871#L1035 assume !(0 != activate_threads_~tmp~1#1); 713872#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 713927#L421 assume !(1 == ~t1_pc~0); 714405#L421-2 is_transmit1_triggered_~__retres1~1#1 := 0; 714453#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 713917#L433 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 713918#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 713982#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 714463#L440 assume !(1 == ~t2_pc~0); 714510#L440-2 is_transmit2_triggered_~__retres1~2#1 := 0; 713638#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 713639#L452 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 714481#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 714246#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 713825#L459 assume !(1 == ~t3_pc~0); 713826#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 714404#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 714462#L471 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 713622#L1059 assume !(0 != activate_threads_~tmp___2~0#1); 713623#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 713632#L478 assume !(1 == ~t4_pc~0); 713633#L478-2 is_transmit4_triggered_~__retres1~4#1 := 0; 714306#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 714385#L490 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 713798#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 713547#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 713548#L497 assume !(1 == ~t5_pc~0); 713590#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 713591#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 713885#L509 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 713886#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 714398#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 714399#L516 assume !(1 == ~t6_pc~0); 714320#L516-2 is_transmit6_triggered_~__retres1~6#1 := 0; 714111#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 714112#L528 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 713675#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 713676#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 714103#L535 assume !(1 == ~t7_pc~0); 714104#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 714183#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 714184#L547 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 714219#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 714210#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 714211#L554 assume !(1 == ~t8_pc~0); 713464#L554-2 is_transmit8_triggered_~__retres1~8#1 := 0; 713465#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 714270#L566 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 713763#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 713764#L1099-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 713449#L931 assume !(1 == ~M_E~0); 713450#L931-2 assume !(1 == ~T1_E~0); 714435#L936-1 assume !(1 == ~T2_E~0); 714478#L941-1 assume !(1 == ~T3_E~0); 713928#L946-1 assume !(1 == ~T4_E~0); 713929#L951-1 assume !(1 == ~T5_E~0); 713691#L956-1 assume !(1 == ~T6_E~0); 713692#L961-1 assume !(1 == ~T7_E~0); 714086#L966-1 assume !(1 == ~T8_E~0); 714087#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 714213#L976-1 assume !(1 == ~E_2~0); 714174#L981-1 assume !(1 == ~E_3~0); 713933#L986-1 assume !(1 == ~E_4~0); 713721#L991-1 assume !(1 == ~E_5~0); 713722#L996-1 assume !(1 == ~E_6~0); 714456#L1001-1 assume !(1 == ~E_7~0); 714134#L1006-1 assume !(1 == ~E_8~0); 714135#L1011-1 assume { :end_inline_reset_delta_events } true; 713512#L1272-2 [2021-12-15 17:21:52,084 INFO L793 eck$LassoCheckResult]: Loop: 713512#L1272-2 assume !false; 713513#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 713510#L813 assume !false; 713511#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 714323#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 713515#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 714080#L682 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 714090#L696 assume !(0 != eval_~tmp~0#1); 714138#L828 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 714139#L574-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 714291#L838-3 assume !(0 == ~M_E~0); 714189#L838-5 assume !(0 == ~T1_E~0); 714190#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 714032#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 714033#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 714083#L858-3 assume !(0 == ~T5_E~0); 714159#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 714148#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 714149#L873-3 assume !(0 == ~T8_E~0); 713742#L878-3 assume 0 == ~E_1~0;~E_1~0 := 1; 713474#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 713475#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 713476#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 713477#L898-3 assume !(0 == ~E_5~0); 713957#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 714324#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 713969#L913-3 assume !(0 == ~E_8~0); 713517#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 713518#L402-27 assume !(1 == ~m_pc~0); 713467#L402-29 is_master_triggered_~__retres1~0#1 := 0; 713975#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 713960#L414-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 713961#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 714357#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 714358#L421-27 assume !(1 == ~t1_pc~0); 754715#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 754714#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 754713#L433-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 754660#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 714507#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 714508#L440-27 assume !(1 == ~t2_pc~0); 750274#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 750272#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 750270#L452-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 750268#L1051-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 750266#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 750264#L459-27 assume !(1 == ~t3_pc~0); 750262#L459-29 is_transmit3_triggered_~__retres1~3#1 := 0; 752307#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 752305#L471-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 750180#L1059-27 assume !(0 != activate_threads_~tmp___2~0#1); 750177#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 750174#L478-27 assume !(1 == ~t4_pc~0); 727836#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 750171#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 750169#L490-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 750167#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 750165#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 750162#L497-27 assume !(1 == ~t5_pc~0); 750159#L497-29 is_transmit5_triggered_~__retres1~5#1 := 0; 750157#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 750155#L509-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 750153#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 750151#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 750150#L516-27 assume !(1 == ~t6_pc~0); 724777#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 750147#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 750145#L528-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 750143#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 750141#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 750138#L535-27 assume 1 == ~t7_pc~0; 750136#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 750133#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 750131#L547-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 750129#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 750127#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 750124#L554-27 assume !(1 == ~t8_pc~0); 724593#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 750121#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 750119#L566-9 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 750117#L1099-27 assume !(0 != activate_threads_~tmp___7~0#1); 750113#L1099-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 750111#L931-3 assume !(1 == ~M_E~0); 723203#L931-5 assume !(1 == ~T1_E~0); 750108#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 750105#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 750103#L946-3 assume !(1 == ~T4_E~0); 750101#L951-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 750100#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 750098#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 750096#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 750094#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 750092#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 750090#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 750087#L986-3 assume !(1 == ~E_4~0); 750085#L991-3 assume 1 == ~E_5~0;~E_5~0 := 2; 750083#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 750081#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 750079#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 750076#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 750066#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 750056#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 750055#L682-1 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 714612#L1291 assume !(0 == start_simulation_~tmp~3#1); 714052#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 713948#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 713440#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 713441#L682-2 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 714303#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 713908#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 713909#L1254 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 714152#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 713512#L1272-2 [2021-12-15 17:21:52,085 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:52,085 INFO L85 PathProgramCache]: Analyzing trace with hash -2130838531, now seen corresponding path program 1 times [2021-12-15 17:21:52,085 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:52,085 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1694612202] [2021-12-15 17:21:52,085 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:52,085 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:52,094 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:52,130 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:52,130 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:52,130 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1694612202] [2021-12-15 17:21:52,131 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1694612202] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:52,131 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:52,131 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-15 17:21:52,131 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1676207892] [2021-12-15 17:21:52,131 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:52,131 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:21:52,132 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:52,132 INFO L85 PathProgramCache]: Analyzing trace with hash 1568271901, now seen corresponding path program 1 times [2021-12-15 17:21:52,132 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:52,132 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019009888] [2021-12-15 17:21:52,132 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:52,132 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:52,138 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:52,149 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:52,149 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:52,149 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019009888] [2021-12-15 17:21:52,149 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2019009888] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:52,149 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:52,149 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:52,150 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [166285648] [2021-12-15 17:21:52,150 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:52,150 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:21:52,150 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:21:52,150 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:21:52,151 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:21:52,151 INFO L87 Difference]: Start difference. First operand 41343 states and 58668 transitions. cyclomatic complexity: 17327 Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 2 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:52,268 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:21:52,269 INFO L93 Difference]: Finished difference Result 41343 states and 58250 transitions. [2021-12-15 17:21:52,269 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:21:52,269 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 41343 states and 58250 transitions. [2021-12-15 17:21:52,436 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 41200 [2021-12-15 17:21:52,531 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 41343 states to 41343 states and 58250 transitions. [2021-12-15 17:21:52,531 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 41343 [2021-12-15 17:21:52,559 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 41343 [2021-12-15 17:21:52,560 INFO L73 IsDeterministic]: Start isDeterministic. Operand 41343 states and 58250 transitions. [2021-12-15 17:21:52,584 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:21:52,584 INFO L681 BuchiCegarLoop]: Abstraction has 41343 states and 58250 transitions. [2021-12-15 17:21:52,609 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 41343 states and 58250 transitions. [2021-12-15 17:21:53,155 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 41343 to 41343. [2021-12-15 17:21:53,188 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 41343 states, 41343 states have (on average 1.4089446822920446) internal successors, (58250), 41342 states have internal predecessors, (58250), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:53,245 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 41343 states to 41343 states and 58250 transitions. [2021-12-15 17:21:53,246 INFO L704 BuchiCegarLoop]: Abstraction has 41343 states and 58250 transitions. [2021-12-15 17:21:53,246 INFO L587 BuchiCegarLoop]: Abstraction has 41343 states and 58250 transitions. [2021-12-15 17:21:53,246 INFO L425 BuchiCegarLoop]: ======== Iteration 21============ [2021-12-15 17:21:53,246 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 41343 states and 58250 transitions. [2021-12-15 17:21:53,362 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 41200 [2021-12-15 17:21:53,362 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:21:53,362 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:21:53,372 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:53,373 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:53,373 INFO L791 eck$LassoCheckResult]: Stem: 796826#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 796827#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 797190#L1235 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 796217#L574 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 796218#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 796488#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 796489#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 797076#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 797062#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 796562#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 796563#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 796804#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 796805#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 796646#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 796647#L838 assume !(0 == ~M_E~0); 796815#L838-2 assume !(0 == ~T1_E~0); 796179#L843-1 assume !(0 == ~T2_E~0); 796180#L848-1 assume !(0 == ~T3_E~0); 796297#L853-1 assume !(0 == ~T4_E~0); 796634#L858-1 assume !(0 == ~T5_E~0); 796129#L863-1 assume !(0 == ~T6_E~0); 796130#L868-1 assume !(0 == ~T7_E~0); 797139#L873-1 assume !(0 == ~T8_E~0); 797135#L878-1 assume !(0 == ~E_1~0); 797110#L883-1 assume !(0 == ~E_2~0); 797111#L888-1 assume !(0 == ~E_3~0); 796774#L893-1 assume !(0 == ~E_4~0); 796775#L898-1 assume !(0 == ~E_5~0); 797159#L903-1 assume !(0 == ~E_6~0); 797107#L908-1 assume !(0 == ~E_7~0); 796921#L913-1 assume !(0 == ~E_8~0); 796193#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 796194#L402 assume !(1 == ~m_pc~0); 796407#L402-2 is_master_triggered_~__retres1~0#1 := 0; 796321#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 796322#L414 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 796569#L1035 assume !(0 != activate_threads_~tmp~1#1); 796570#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 796623#L421 assume !(1 == ~t1_pc~0); 797099#L421-2 is_transmit1_triggered_~__retres1~1#1 := 0; 797143#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 796613#L433 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 796614#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 796676#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 797153#L440 assume !(1 == ~t2_pc~0); 797211#L440-2 is_transmit2_triggered_~__retres1~2#1 := 0; 796331#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 796332#L452 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 797175#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 796934#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 796523#L459 assume !(1 == ~t3_pc~0); 796524#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 797097#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 797151#L471 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 796314#L1059 assume !(0 != activate_threads_~tmp___2~0#1); 796315#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 796325#L478 assume !(1 == ~t4_pc~0); 796326#L478-2 is_transmit4_triggered_~__retres1~4#1 := 0; 796999#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 797075#L490 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 796494#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 796239#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 796240#L497 assume !(1 == ~t5_pc~0); 796283#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 796284#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 796583#L509 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 796584#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 797090#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 797091#L516 assume !(1 == ~t6_pc~0); 797015#L516-2 is_transmit6_triggered_~__retres1~6#1 := 0; 796801#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 796802#L528 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 796369#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 796370#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 796793#L535 assume !(1 == ~t7_pc~0); 796794#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 796872#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 796873#L547 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 796909#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 796900#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 796901#L554 assume !(1 == ~t8_pc~0); 796155#L554-2 is_transmit8_triggered_~__retres1~8#1 := 0; 796156#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 796960#L566 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 796460#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 796461#L1099-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 796141#L931 assume !(1 == ~M_E~0); 796142#L931-2 assume !(1 == ~T1_E~0); 797127#L936-1 assume !(1 == ~T2_E~0); 797172#L941-1 assume !(1 == ~T3_E~0); 796624#L946-1 assume !(1 == ~T4_E~0); 796625#L951-1 assume !(1 == ~T5_E~0); 796387#L956-1 assume !(1 == ~T6_E~0); 796388#L961-1 assume !(1 == ~T7_E~0); 796776#L966-1 assume !(1 == ~T8_E~0); 796777#L971-1 assume !(1 == ~E_1~0); 796902#L976-1 assume !(1 == ~E_2~0); 796864#L981-1 assume !(1 == ~E_3~0); 796629#L986-1 assume !(1 == ~E_4~0); 796417#L991-1 assume !(1 == ~E_5~0); 796418#L996-1 assume !(1 == ~E_6~0); 797146#L1001-1 assume !(1 == ~E_7~0); 796824#L1006-1 assume !(1 == ~E_8~0); 796825#L1011-1 assume { :end_inline_reset_delta_events } true; 797098#L1272-2 [2021-12-15 17:21:53,373 INFO L793 eck$LassoCheckResult]: Loop: 797098#L1272-2 assume !false; 818444#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 818306#L813 assume !false; 818441#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 818434#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 818425#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 818423#L682 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 818421#L696 assume !(0 != eval_~tmp~0#1); 818422#L828 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 832649#L574-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 832648#L838-3 assume !(0 == ~M_E~0); 832647#L838-5 assume !(0 == ~T1_E~0); 832644#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 832642#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 832640#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 832638#L858-3 assume !(0 == ~T5_E~0); 832636#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 832634#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 832632#L873-3 assume !(0 == ~T8_E~0); 832630#L878-3 assume !(0 == ~E_1~0); 832628#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 832626#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 832624#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 832622#L898-3 assume !(0 == ~E_5~0); 832621#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 832620#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 832189#L913-3 assume !(0 == ~E_8~0); 832188#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 832187#L402-27 assume !(1 == ~m_pc~0); 832185#L402-29 is_master_triggered_~__retres1~0#1 := 0; 832184#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 832182#L414-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 832179#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 832177#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 832175#L421-27 assume !(1 == ~t1_pc~0); 832173#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 832171#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 832169#L433-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 832167#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 831079#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 818613#L440-27 assume !(1 == ~t2_pc~0); 818611#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 818609#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 818607#L452-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 818605#L1051-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 818602#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 818600#L459-27 assume !(1 == ~t3_pc~0); 818596#L459-29 is_transmit3_triggered_~__retres1~3#1 := 0; 818594#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 818592#L471-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 818590#L1059-27 assume !(0 != activate_threads_~tmp___2~0#1); 818588#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 818586#L478-27 assume !(1 == ~t4_pc~0); 805909#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 818583#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 818581#L490-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 818579#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 818576#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 818574#L497-27 assume 1 == ~t5_pc~0; 818572#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 818569#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 818567#L509-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 818565#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 818564#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 818562#L516-27 assume !(1 == ~t6_pc~0); 816002#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 818559#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 818557#L528-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 818554#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 818552#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 818550#L535-27 assume 1 == ~t7_pc~0; 818548#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 818545#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 818543#L547-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 818541#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 818539#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 818537#L554-27 assume !(1 == ~t8_pc~0); 808259#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 818534#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 818532#L566-9 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 818530#L1099-27 assume !(0 != activate_threads_~tmp___7~0#1); 818528#L1099-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 818526#L931-3 assume !(1 == ~M_E~0); 818522#L931-5 assume !(1 == ~T1_E~0); 818520#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 818519#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 818518#L946-3 assume !(1 == ~T4_E~0); 818517#L951-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 818516#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 818515#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 818514#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 818513#L971-3 assume !(1 == ~E_1~0); 818512#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 818511#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 818509#L986-3 assume !(1 == ~E_4~0); 818507#L991-3 assume 1 == ~E_5~0;~E_5~0 := 2; 818505#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 818503#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 818501#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 818499#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 818497#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 818486#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 818484#L682-1 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 818481#L1291 assume !(0 == start_simulation_~tmp~3#1); 818477#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 818458#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 818456#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 818454#L682-2 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 818452#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 818450#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 818449#L1254 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 818447#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 797098#L1272-2 [2021-12-15 17:21:53,374 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:53,374 INFO L85 PathProgramCache]: Analyzing trace with hash -1450780161, now seen corresponding path program 1 times [2021-12-15 17:21:53,374 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:53,374 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1337313231] [2021-12-15 17:21:53,374 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:53,374 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:53,399 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:21:53,419 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-15 17:21:53,425 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:21:53,498 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-15 17:21:53,498 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:53,499 INFO L85 PathProgramCache]: Analyzing trace with hash 1004663490, now seen corresponding path program 1 times [2021-12-15 17:21:53,499 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:53,499 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1790719353] [2021-12-15 17:21:53,499 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:53,499 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:53,510 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:53,538 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:53,538 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:53,538 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1790719353] [2021-12-15 17:21:53,538 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1790719353] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:53,538 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:53,538 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:53,539 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1855486829] [2021-12-15 17:21:53,539 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:53,539 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:21:53,539 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:21:53,539 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:21:53,540 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:21:53,540 INFO L87 Difference]: Start difference. First operand 41343 states and 58250 transitions. cyclomatic complexity: 16909 Second operand has 3 states, 3 states have (on average 37.333333333333336) internal successors, (112), 3 states have internal predecessors, (112), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:53,648 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:21:53,648 INFO L93 Difference]: Finished difference Result 46638 states and 65652 transitions. [2021-12-15 17:21:53,648 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:21:53,649 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 46638 states and 65652 transitions. [2021-12-15 17:21:53,822 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 46416 [2021-12-15 17:21:53,927 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 46638 states to 46638 states and 65652 transitions. [2021-12-15 17:21:53,927 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 46638 [2021-12-15 17:21:53,961 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 46638 [2021-12-15 17:21:53,961 INFO L73 IsDeterministic]: Start isDeterministic. Operand 46638 states and 65652 transitions. [2021-12-15 17:21:53,990 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:21:53,991 INFO L681 BuchiCegarLoop]: Abstraction has 46638 states and 65652 transitions. [2021-12-15 17:21:54,019 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 46638 states and 65652 transitions. [2021-12-15 17:21:54,577 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 46638 to 46638. [2021-12-15 17:21:54,616 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 46638 states, 46638 states have (on average 1.4076932973112055) internal successors, (65652), 46637 states have internal predecessors, (65652), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:54,684 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 46638 states to 46638 states and 65652 transitions. [2021-12-15 17:21:54,685 INFO L704 BuchiCegarLoop]: Abstraction has 46638 states and 65652 transitions. [2021-12-15 17:21:54,685 INFO L587 BuchiCegarLoop]: Abstraction has 46638 states and 65652 transitions. [2021-12-15 17:21:54,685 INFO L425 BuchiCegarLoop]: ======== Iteration 22============ [2021-12-15 17:21:54,685 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 46638 states and 65652 transitions. [2021-12-15 17:21:54,818 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 46416 [2021-12-15 17:21:54,818 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:21:54,818 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:21:54,823 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:54,823 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:54,823 INFO L791 eck$LassoCheckResult]: Stem: 884838#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 884839#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 885251#L1235 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 884203#L574 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 884204#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 884475#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 884476#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 885107#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 885089#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 884552#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 884553#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 884815#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 884816#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 884645#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 884646#L838 assume !(0 == ~M_E~0); 884826#L838-2 assume !(0 == ~T1_E~0); 884165#L843-1 assume !(0 == ~T2_E~0); 884166#L848-1 assume !(0 == ~T3_E~0); 884283#L853-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 884846#L858-1 assume !(0 == ~T5_E~0); 884118#L863-1 assume !(0 == ~T6_E~0); 884119#L868-1 assume !(0 == ~T7_E~0); 885266#L873-1 assume !(0 == ~T8_E~0); 885267#L878-1 assume !(0 == ~E_1~0); 885147#L883-1 assume !(0 == ~E_2~0); 885148#L888-1 assume !(0 == ~E_3~0); 884785#L893-1 assume !(0 == ~E_4~0); 884786#L898-1 assume !(0 == ~E_5~0); 885299#L903-1 assume !(0 == ~E_6~0); 885300#L908-1 assume !(0 == ~E_7~0); 885341#L913-1 assume !(0 == ~E_8~0); 885340#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 885338#L402 assume !(1 == ~m_pc~0); 885337#L402-2 is_master_triggered_~__retres1~0#1 := 0; 884307#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 884308#L414 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 884558#L1035 assume !(0 != activate_threads_~tmp~1#1); 884559#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 885136#L421 assume !(1 == ~t1_pc~0); 885137#L421-2 is_transmit1_triggered_~__retres1~1#1 := 0; 885281#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 885282#L433 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 884677#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 884678#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 885288#L440 assume !(1 == ~t2_pc~0); 885289#L440-2 is_transmit2_triggered_~__retres1~2#1 := 0; 884317#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 884318#L452 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 885233#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 884948#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 884949#L459 assume !(1 == ~t3_pc~0); 885131#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 885132#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 885192#L471 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 884300#L1059 assume !(0 != activate_threads_~tmp___2~0#1); 884301#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 885306#L478 assume !(1 == ~t4_pc~0); 885017#L478-2 is_transmit4_triggered_~__retres1~4#1 := 0; 885018#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 885228#L490 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 885229#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 884226#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 884227#L497 assume !(1 == ~t5_pc~0); 884269#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 884270#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 885326#L509 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 885197#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 885198#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 885276#L516 assume !(1 == ~t6_pc~0); 885277#L516-2 is_transmit6_triggered_~__retres1~6#1 := 0; 884812#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 884813#L528 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 884354#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 884355#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 884892#L535 assume !(1 == ~t7_pc~0); 885069#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 884890#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 884891#L547 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 885321#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 885320#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 885113#L554 assume !(1 == ~t8_pc~0); 884142#L554-2 is_transmit8_triggered_~__retres1~8#1 := 0; 884143#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 884976#L566 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 884445#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 884446#L1099-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 884128#L931 assume !(1 == ~M_E~0); 884129#L931-2 assume !(1 == ~T1_E~0); 885163#L936-1 assume !(1 == ~T2_E~0); 885225#L941-1 assume !(1 == ~T3_E~0); 884620#L946-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 884621#L951-1 assume !(1 == ~T5_E~0); 884372#L956-1 assume !(1 == ~T6_E~0); 884373#L961-1 assume !(1 == ~T7_E~0); 884787#L966-1 assume !(1 == ~T8_E~0); 884788#L971-1 assume !(1 == ~E_1~0); 884919#L976-1 assume !(1 == ~E_2~0); 884882#L981-1 assume !(1 == ~E_3~0); 884626#L986-1 assume !(1 == ~E_4~0); 884402#L991-1 assume !(1 == ~E_5~0); 884403#L996-1 assume !(1 == ~E_6~0); 885186#L1001-1 assume !(1 == ~E_7~0); 884836#L1006-1 assume !(1 == ~E_8~0); 884837#L1011-1 assume { :end_inline_reset_delta_events } true; 885134#L1272-2 [2021-12-15 17:21:54,823 INFO L793 eck$LassoCheckResult]: Loop: 885134#L1272-2 assume !false; 914108#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 907824#L813 assume !false; 914107#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 914105#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 914097#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 914096#L682 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 914094#L696 assume !(0 != eval_~tmp~0#1); 914095#L828 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 927685#L574-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 927684#L838-3 assume !(0 == ~M_E~0); 927683#L838-5 assume !(0 == ~T1_E~0); 927682#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 927681#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 927678#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 927679#L858-3 assume !(0 == ~T5_E~0); 928983#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 928981#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 928979#L873-3 assume !(0 == ~T8_E~0); 928977#L878-3 assume !(0 == ~E_1~0); 928975#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 928973#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 928971#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 928969#L898-3 assume !(0 == ~E_5~0); 928967#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 928964#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 928962#L913-3 assume !(0 == ~E_8~0); 928960#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 928958#L402-27 assume !(1 == ~m_pc~0); 928954#L402-29 is_master_triggered_~__retres1~0#1 := 0; 928952#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 928950#L414-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 928948#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 928946#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 928944#L421-27 assume !(1 == ~t1_pc~0); 928942#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 928940#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 928938#L433-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 928937#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 928935#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 928933#L440-27 assume !(1 == ~t2_pc~0); 926692#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 928930#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 928928#L452-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 928925#L1051-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 928922#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 928919#L459-27 assume !(1 == ~t3_pc~0); 928916#L459-29 is_transmit3_triggered_~__retres1~3#1 := 0; 928913#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 928910#L471-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 928908#L1059-27 assume !(0 != activate_threads_~tmp___2~0#1); 928904#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 928902#L478-27 assume !(1 == ~t4_pc~0); 928889#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 928886#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 928884#L490-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 928883#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 928882#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 928880#L497-27 assume !(1 == ~t5_pc~0); 928876#L497-29 is_transmit5_triggered_~__retres1~5#1 := 0; 928874#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 928871#L509-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 928869#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 928867#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 914568#L516-27 assume !(1 == ~t6_pc~0); 914558#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 914554#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 914420#L528-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 914417#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 914415#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 914413#L535-27 assume 1 == ~t7_pc~0; 914411#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 914408#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 914406#L547-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 914405#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 914403#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 914401#L554-27 assume !(1 == ~t8_pc~0); 907920#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 914398#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 914396#L566-9 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 914395#L1099-27 assume !(0 != activate_threads_~tmp___7~0#1); 914393#L1099-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 914391#L931-3 assume !(1 == ~M_E~0); 907555#L931-5 assume !(1 == ~T1_E~0); 914390#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 914388#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 914386#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 914383#L951-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 914381#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 914379#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 914377#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 914375#L971-3 assume !(1 == ~E_1~0); 914372#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 914371#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 914369#L986-3 assume !(1 == ~E_4~0); 914367#L991-3 assume 1 == ~E_5~0;~E_5~0 := 2; 914365#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 914363#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 914361#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 914359#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 914357#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 914341#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 914333#L682-1 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 914325#L1291 assume !(0 == start_simulation_~tmp~3#1); 914318#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 914153#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 914122#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 914115#L682-2 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 914112#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 914111#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 914110#L1254 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 914109#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 885134#L1272-2 [2021-12-15 17:21:54,824 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:54,824 INFO L85 PathProgramCache]: Analyzing trace with hash 1518911875, now seen corresponding path program 1 times [2021-12-15 17:21:54,824 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:54,824 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1521093119] [2021-12-15 17:21:54,824 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:54,825 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:54,829 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:54,840 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:54,840 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:54,841 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1521093119] [2021-12-15 17:21:54,841 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1521093119] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:54,841 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:54,841 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:54,841 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1160074910] [2021-12-15 17:21:54,841 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:54,841 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:21:54,842 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:54,842 INFO L85 PathProgramCache]: Analyzing trace with hash 1045425123, now seen corresponding path program 1 times [2021-12-15 17:21:54,842 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:54,842 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1959295602] [2021-12-15 17:21:54,842 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:54,842 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:54,848 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:54,859 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:54,859 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:54,859 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1959295602] [2021-12-15 17:21:54,860 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1959295602] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:54,860 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:54,860 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:54,860 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1556191448] [2021-12-15 17:21:54,860 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:54,860 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:21:54,860 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:21:54,861 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-15 17:21:54,861 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-15 17:21:54,861 INFO L87 Difference]: Start difference. First operand 46638 states and 65652 transitions. cyclomatic complexity: 19016 Second operand has 4 states, 4 states have (on average 26.0) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:55,055 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:21:55,056 INFO L93 Difference]: Finished difference Result 60380 states and 84681 transitions. [2021-12-15 17:21:55,056 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-15 17:21:55,057 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 60380 states and 84681 transitions. [2021-12-15 17:21:55,302 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 60208 [2021-12-15 17:21:55,795 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 60380 states to 60380 states and 84681 transitions. [2021-12-15 17:21:55,796 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 60380 [2021-12-15 17:21:55,820 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 60380 [2021-12-15 17:21:55,820 INFO L73 IsDeterministic]: Start isDeterministic. Operand 60380 states and 84681 transitions. [2021-12-15 17:21:55,842 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:21:55,842 INFO L681 BuchiCegarLoop]: Abstraction has 60380 states and 84681 transitions. [2021-12-15 17:21:55,862 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 60380 states and 84681 transitions. [2021-12-15 17:21:56,188 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 60380 to 41343. [2021-12-15 17:21:56,229 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 41343 states, 41343 states have (on average 1.4073724693418475) internal successors, (58185), 41342 states have internal predecessors, (58185), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:56,292 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 41343 states to 41343 states and 58185 transitions. [2021-12-15 17:21:56,292 INFO L704 BuchiCegarLoop]: Abstraction has 41343 states and 58185 transitions. [2021-12-15 17:21:56,293 INFO L587 BuchiCegarLoop]: Abstraction has 41343 states and 58185 transitions. [2021-12-15 17:21:56,293 INFO L425 BuchiCegarLoop]: ======== Iteration 23============ [2021-12-15 17:21:56,293 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 41343 states and 58185 transitions. [2021-12-15 17:21:56,413 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 41200 [2021-12-15 17:21:56,414 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:21:56,414 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:21:56,418 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:56,418 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:56,418 INFO L791 eck$LassoCheckResult]: Stem: 991861#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 991862#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 992237#L1235 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 991231#L574 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 991232#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 991507#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 991508#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 992116#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 992100#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 991581#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 991582#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 991838#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 991839#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 991671#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 991672#L838 assume !(0 == ~M_E~0); 991847#L838-2 assume !(0 == ~T1_E~0); 991193#L843-1 assume !(0 == ~T2_E~0); 991194#L848-1 assume !(0 == ~T3_E~0); 991313#L853-1 assume !(0 == ~T4_E~0); 991655#L858-1 assume !(0 == ~T5_E~0); 991144#L863-1 assume !(0 == ~T6_E~0); 991145#L868-1 assume !(0 == ~T7_E~0); 992180#L873-1 assume !(0 == ~T8_E~0); 992178#L878-1 assume !(0 == ~E_1~0); 992153#L883-1 assume !(0 == ~E_2~0); 992154#L888-1 assume !(0 == ~E_3~0); 991809#L893-1 assume !(0 == ~E_4~0); 991810#L898-1 assume !(0 == ~E_5~0); 992203#L903-1 assume !(0 == ~E_6~0); 992152#L908-1 assume !(0 == ~E_7~0); 991957#L913-1 assume !(0 == ~E_8~0); 991207#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 991208#L402 assume !(1 == ~m_pc~0); 991417#L402-2 is_master_triggered_~__retres1~0#1 := 0; 991335#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 991336#L414 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 991589#L1035 assume !(0 != activate_threads_~tmp~1#1); 991590#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 991645#L421 assume !(1 == ~t1_pc~0); 992142#L421-2 is_transmit1_triggered_~__retres1~1#1 := 0; 992182#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 991635#L433 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 991636#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 991702#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 992197#L440 assume !(1 == ~t2_pc~0); 992260#L440-2 is_transmit2_triggered_~__retres1~2#1 := 0; 991345#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 991346#L452 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 992220#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 991974#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 991539#L459 assume !(1 == ~t3_pc~0); 991540#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 992139#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 991888#L471 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 991328#L1059 assume !(0 != activate_threads_~tmp___2~0#1); 991329#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 991339#L478 assume !(1 == ~t4_pc~0); 991340#L478-2 is_transmit4_triggered_~__retres1~4#1 := 0; 992032#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 992115#L490 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 991513#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 991252#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 991253#L497 assume !(1 == ~t5_pc~0); 991297#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 991298#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 991603#L509 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 991604#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 992130#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 992131#L516 assume !(1 == ~t6_pc~0); 992045#L516-2 is_transmit6_triggered_~__retres1~6#1 := 0; 991836#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 991837#L528 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 991382#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 991383#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 991828#L535 assume !(1 == ~t7_pc~0); 991829#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 991910#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 991911#L547 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 991946#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 991936#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 991937#L554 assume !(1 == ~t8_pc~0); 991170#L554-2 is_transmit8_triggered_~__retres1~8#1 := 0; 991171#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 991996#L566 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 991474#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 991475#L1099-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 991156#L931 assume !(1 == ~M_E~0); 991157#L931-2 assume !(1 == ~T1_E~0); 992168#L936-1 assume !(1 == ~T2_E~0); 992216#L941-1 assume !(1 == ~T3_E~0); 991646#L946-1 assume !(1 == ~T4_E~0); 991647#L951-1 assume !(1 == ~T5_E~0); 991398#L956-1 assume !(1 == ~T6_E~0); 991399#L961-1 assume !(1 == ~T7_E~0); 991811#L966-1 assume !(1 == ~T8_E~0); 991812#L971-1 assume !(1 == ~E_1~0); 991939#L976-1 assume !(1 == ~E_2~0); 991901#L981-1 assume !(1 == ~E_3~0); 991651#L986-1 assume !(1 == ~E_4~0); 991430#L991-1 assume !(1 == ~E_5~0); 991431#L996-1 assume !(1 == ~E_6~0); 992189#L1001-1 assume !(1 == ~E_7~0); 991859#L1006-1 assume !(1 == ~E_8~0); 991860#L1011-1 assume { :end_inline_reset_delta_events } true; 992140#L1272-2 [2021-12-15 17:21:56,418 INFO L793 eck$LassoCheckResult]: Loop: 992140#L1272-2 assume !false; 1029228#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1028350#L813 assume !false; 1029227#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1029225#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1029217#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1029215#L682 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1029213#L696 assume !(0 != eval_~tmp~0#1); 1029214#L828 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1031129#L574-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1031127#L838-3 assume !(0 == ~M_E~0); 1031125#L838-5 assume !(0 == ~T1_E~0); 1031123#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1031121#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1031119#L853-3 assume !(0 == ~T4_E~0); 1031117#L858-3 assume !(0 == ~T5_E~0); 1031115#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1031113#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1031111#L873-3 assume !(0 == ~T8_E~0); 1031109#L878-3 assume !(0 == ~E_1~0); 1031107#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1031105#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1031103#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1031101#L898-3 assume !(0 == ~E_5~0); 1031099#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1031097#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1031095#L913-3 assume !(0 == ~E_8~0); 1031093#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1031090#L402-27 assume !(1 == ~m_pc~0); 1031087#L402-29 is_master_triggered_~__retres1~0#1 := 0; 1031085#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1031083#L414-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1031081#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1031079#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1031077#L421-27 assume !(1 == ~t1_pc~0); 1031075#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 1031073#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1031071#L433-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1031069#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1031067#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1031065#L440-27 assume !(1 == ~t2_pc~0); 1029918#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 1031063#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1031061#L452-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1031060#L1051-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1031058#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1031057#L459-27 assume 1 == ~t3_pc~0; 1031055#L460-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1031053#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1031051#L471-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1031049#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1031047#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1011443#L478-27 assume !(1 == ~t4_pc~0); 1011440#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 1011438#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1011436#L490-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1011434#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1011432#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1011430#L497-27 assume 1 == ~t5_pc~0; 1011428#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1011426#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1011424#L509-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1011422#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1011420#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1011418#L516-27 assume !(1 == ~t6_pc~0); 1008011#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 1011414#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1011411#L528-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1011408#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1011406#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1011404#L535-27 assume 1 == ~t7_pc~0; 1011402#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1011399#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1011396#L547-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1011395#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1011392#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1011390#L554-27 assume !(1 == ~t8_pc~0); 1007565#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 1011387#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1011385#L566-9 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1011383#L1099-27 assume !(0 != activate_threads_~tmp___7~0#1); 1011382#L1099-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1011380#L931-3 assume !(1 == ~M_E~0); 1005679#L931-5 assume !(1 == ~T1_E~0); 1011377#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1011375#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1011373#L946-3 assume !(1 == ~T4_E~0); 1011371#L951-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1011369#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1011367#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1011365#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1011363#L971-3 assume !(1 == ~E_1~0); 1011361#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1011343#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1011335#L986-3 assume !(1 == ~E_4~0); 1011329#L991-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1011324#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1011320#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1011265#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1010703#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1008863#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1008853#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1008851#L682-1 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 1005709#L1291 assume !(0 == start_simulation_~tmp~3#1); 1005710#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1029237#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1029235#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1029233#L682-2 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 1029232#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1029231#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1029230#L1254 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 1029229#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 992140#L1272-2 [2021-12-15 17:21:56,424 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:56,425 INFO L85 PathProgramCache]: Analyzing trace with hash -1450780161, now seen corresponding path program 2 times [2021-12-15 17:21:56,425 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:56,425 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [248480469] [2021-12-15 17:21:56,425 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:56,426 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:56,480 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:21:56,481 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-15 17:21:56,485 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:21:56,510 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-15 17:21:56,510 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:56,511 INFO L85 PathProgramCache]: Analyzing trace with hash -403037469, now seen corresponding path program 1 times [2021-12-15 17:21:56,511 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:56,511 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1582576867] [2021-12-15 17:21:56,511 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:56,511 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:56,517 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:56,530 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:56,530 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:56,530 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1582576867] [2021-12-15 17:21:56,530 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1582576867] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:56,530 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:56,531 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:56,531 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [281841845] [2021-12-15 17:21:56,531 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:56,531 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:21:56,531 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:21:56,532 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:21:56,532 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:21:56,532 INFO L87 Difference]: Start difference. First operand 41343 states and 58185 transitions. cyclomatic complexity: 16844 Second operand has 3 states, 3 states have (on average 37.333333333333336) internal successors, (112), 3 states have internal predecessors, (112), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:56,746 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:21:56,746 INFO L93 Difference]: Finished difference Result 73790 states and 103076 transitions. [2021-12-15 17:21:56,746 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:21:56,747 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 73790 states and 103076 transitions. [2021-12-15 17:21:57,052 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 73536 [2021-12-15 17:21:57,626 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 73790 states to 73790 states and 103076 transitions. [2021-12-15 17:21:57,626 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 73790 [2021-12-15 17:21:57,651 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 73790 [2021-12-15 17:21:57,651 INFO L73 IsDeterministic]: Start isDeterministic. Operand 73790 states and 103076 transitions. [2021-12-15 17:21:57,677 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:21:57,677 INFO L681 BuchiCegarLoop]: Abstraction has 73790 states and 103076 transitions. [2021-12-15 17:21:57,697 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 73790 states and 103076 transitions. [2021-12-15 17:21:58,086 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 73790 to 73726. [2021-12-15 17:21:58,142 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 73726 states, 73726 states have (on average 1.3972275723625316) internal successors, (103012), 73725 states have internal predecessors, (103012), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:58,259 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 73726 states to 73726 states and 103012 transitions. [2021-12-15 17:21:58,259 INFO L704 BuchiCegarLoop]: Abstraction has 73726 states and 103012 transitions. [2021-12-15 17:21:58,259 INFO L587 BuchiCegarLoop]: Abstraction has 73726 states and 103012 transitions. [2021-12-15 17:21:58,259 INFO L425 BuchiCegarLoop]: ======== Iteration 24============ [2021-12-15 17:21:58,260 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 73726 states and 103012 transitions. [2021-12-15 17:21:58,472 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 73472 [2021-12-15 17:21:58,472 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:21:58,472 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:21:58,477 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:58,477 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:58,478 INFO L791 eck$LassoCheckResult]: Stem: 1106994#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 1106995#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 1107412#L1235 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1106369#L574 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1106370#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 1106641#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1106642#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1107271#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1107258#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1106719#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1106720#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1106972#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1106973#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1106808#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1106809#L838 assume !(0 == ~M_E~0); 1106981#L838-2 assume !(0 == ~T1_E~0); 1106331#L843-1 assume !(0 == ~T2_E~0); 1106332#L848-1 assume !(0 == ~T3_E~0); 1106448#L853-1 assume !(0 == ~T4_E~0); 1106796#L858-1 assume !(0 == ~T5_E~0); 1106285#L863-1 assume !(0 == ~T6_E~0); 1106286#L868-1 assume !(0 == ~T7_E~0); 1107338#L873-1 assume !(0 == ~T8_E~0); 1107335#L878-1 assume !(0 == ~E_1~0); 1107314#L883-1 assume !(0 == ~E_2~0); 1107315#L888-1 assume !(0 == ~E_3~0); 1106942#L893-1 assume 0 == ~E_4~0;~E_4~0 := 1; 1106943#L898-1 assume !(0 == ~E_5~0); 1107369#L903-1 assume !(0 == ~E_6~0); 1107452#L908-1 assume !(0 == ~E_7~0); 1107484#L913-1 assume !(0 == ~E_8~0); 1107483#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1107481#L402 assume !(1 == ~m_pc~0); 1107480#L402-2 is_master_triggered_~__retres1~0#1 := 0; 1106472#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1106473#L414 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1106726#L1035 assume !(0 != activate_threads_~tmp~1#1); 1106727#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1107299#L421 assume !(1 == ~t1_pc~0); 1107300#L421-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1107435#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1107436#L433 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1106841#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 1106842#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1107446#L440 assume !(1 == ~t2_pc~0); 1107447#L440-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1106482#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1106483#L452 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1107390#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 1107118#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1107119#L459 assume !(1 == ~t3_pc~0); 1107294#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1107295#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1107486#L471 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1106465#L1059 assume !(0 != activate_threads_~tmp___2~0#1); 1106466#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1107456#L478 assume !(1 == ~t4_pc~0); 1107192#L478-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1107193#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1107385#L490 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1107386#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 1106392#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1106393#L497 assume !(1 == ~t5_pc~0); 1106434#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1106435#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1107470#L509 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1107359#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 1107360#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1107429#L516 assume !(1 == ~t6_pc~0); 1107430#L516-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1106969#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1106970#L528 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1107469#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 1107468#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1106961#L535 assume !(1 == ~t7_pc~0); 1106962#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1107467#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1107211#L547 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1107084#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 1107075#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1107076#L554 assume !(1 == ~t8_pc~0); 1107464#L554-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1107387#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1107388#L566 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1106611#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 1106612#L1099-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1107085#L931 assume !(1 == ~M_E~0); 1107328#L931-2 assume !(1 == ~T1_E~0); 1107329#L936-1 assume !(1 == ~T2_E~0); 1107442#L941-1 assume !(1 == ~T3_E~0); 1107443#L946-1 assume !(1 == ~T4_E~0); 1107296#L951-1 assume !(1 == ~T5_E~0); 1106536#L956-1 assume !(1 == ~T6_E~0); 1106537#L961-1 assume !(1 == ~T7_E~0); 1106945#L966-1 assume !(1 == ~T8_E~0); 1106946#L971-1 assume !(1 == ~E_1~0); 1107078#L976-1 assume !(1 == ~E_2~0); 1107036#L981-1 assume !(1 == ~E_3~0); 1106791#L986-1 assume 1 == ~E_4~0;~E_4~0 := 2; 1106567#L991-1 assume !(1 == ~E_5~0); 1106568#L996-1 assume !(1 == ~E_6~0); 1107347#L1001-1 assume !(1 == ~E_7~0); 1106992#L1006-1 assume !(1 == ~E_8~0); 1106993#L1011-1 assume { :end_inline_reset_delta_events } true; 1107297#L1272-2 [2021-12-15 17:21:58,478 INFO L793 eck$LassoCheckResult]: Loop: 1107297#L1272-2 assume !false; 1121562#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1121557#L813 assume !false; 1121555#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1121549#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1121541#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1121539#L682 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1121536#L696 assume !(0 != eval_~tmp~0#1); 1121537#L828 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1137850#L574-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1137842#L838-3 assume !(0 == ~M_E~0); 1137843#L838-5 assume !(0 == ~T1_E~0); 1137836#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1137837#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1137830#L853-3 assume !(0 == ~T4_E~0); 1137831#L858-3 assume !(0 == ~T5_E~0); 1137823#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1137824#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1137817#L873-3 assume !(0 == ~T8_E~0); 1137818#L878-3 assume !(0 == ~E_1~0); 1137810#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1137811#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1137744#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1137745#L898-3 assume !(0 == ~E_5~0); 1137738#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1137739#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1137732#L913-3 assume !(0 == ~E_8~0); 1137733#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1137728#L402-27 assume !(1 == ~m_pc~0); 1137727#L402-29 is_master_triggered_~__retres1~0#1 := 0; 1137720#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1137721#L414-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1137714#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1137715#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1137706#L421-27 assume !(1 == ~t1_pc~0); 1137707#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 1137700#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1137701#L433-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1137693#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1137694#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1137446#L440-27 assume !(1 == ~t2_pc~0); 1137445#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 1137444#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1137443#L452-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1137441#L1051-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1137438#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1137436#L459-27 assume !(1 == ~t3_pc~0); 1137432#L459-29 is_transmit3_triggered_~__retres1~3#1 := 0; 1137430#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1137428#L471-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1137426#L1059-27 assume !(0 != activate_threads_~tmp___2~0#1); 1137423#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1137421#L478-27 assume !(1 == ~t4_pc~0); 1135042#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 1137418#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1137416#L490-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1137414#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1137411#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1137409#L497-27 assume 1 == ~t5_pc~0; 1137407#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1137404#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1137402#L509-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1137319#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1137315#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1130579#L516-27 assume !(1 == ~t6_pc~0); 1130578#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 1130577#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1130576#L528-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1130575#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1130574#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1130573#L535-27 assume !(1 == ~t7_pc~0); 1130571#L535-29 is_transmit7_triggered_~__retres1~7#1 := 0; 1130570#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1130569#L547-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1130568#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1130567#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1122187#L554-27 assume !(1 == ~t8_pc~0); 1122184#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 1122181#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1122176#L566-9 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1122174#L1099-27 assume !(0 != activate_threads_~tmp___7~0#1); 1122172#L1099-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1122170#L931-3 assume !(1 == ~M_E~0); 1122165#L931-5 assume !(1 == ~T1_E~0); 1122162#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1122158#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1122156#L946-3 assume !(1 == ~T4_E~0); 1122154#L951-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1122152#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1122150#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1122148#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1122146#L971-3 assume !(1 == ~E_1~0); 1122143#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1122141#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1122139#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1122136#L991-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1122134#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1122132#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1122131#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1122129#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1122127#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1122117#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1122115#L682-1 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 1122112#L1291 assume !(0 == start_simulation_~tmp~3#1); 1122108#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1121577#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1121576#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1121574#L682-2 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 1121571#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1121569#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1121567#L1254 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 1121565#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 1107297#L1272-2 [2021-12-15 17:21:58,478 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:58,479 INFO L85 PathProgramCache]: Analyzing trace with hash 1947895171, now seen corresponding path program 1 times [2021-12-15 17:21:58,479 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:58,479 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1290510009] [2021-12-15 17:21:58,479 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:58,479 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:58,484 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:58,496 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:58,496 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:58,496 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1290510009] [2021-12-15 17:21:58,496 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1290510009] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:58,496 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:58,497 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:58,497 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [918329374] [2021-12-15 17:21:58,497 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:58,497 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:21:58,497 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:58,497 INFO L85 PathProgramCache]: Analyzing trace with hash -1063109471, now seen corresponding path program 1 times [2021-12-15 17:21:58,498 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:58,498 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [548402695] [2021-12-15 17:21:58,498 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:58,498 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:58,504 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:58,518 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:58,518 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:58,519 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [548402695] [2021-12-15 17:21:58,519 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [548402695] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:58,519 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:58,519 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-15 17:21:58,519 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [378117722] [2021-12-15 17:21:58,519 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:58,519 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:21:58,520 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:21:58,520 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-15 17:21:58,520 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-15 17:21:58,520 INFO L87 Difference]: Start difference. First operand 73726 states and 103012 transitions. cyclomatic complexity: 29288 Second operand has 4 states, 4 states have (on average 26.0) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:59,188 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:21:59,189 INFO L93 Difference]: Finished difference Result 106332 states and 148145 transitions. [2021-12-15 17:21:59,189 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-15 17:21:59,190 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 106332 states and 148145 transitions. [2021-12-15 17:21:59,738 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 103016 [2021-12-15 17:22:00,070 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 106332 states to 106332 states and 148145 transitions. [2021-12-15 17:22:00,070 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 106332 [2021-12-15 17:22:00,150 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 106332 [2021-12-15 17:22:00,150 INFO L73 IsDeterministic]: Start isDeterministic. Operand 106332 states and 148145 transitions. [2021-12-15 17:22:00,222 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:22:00,222 INFO L681 BuchiCegarLoop]: Abstraction has 106332 states and 148145 transitions. [2021-12-15 17:22:00,283 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 106332 states and 148145 transitions. [2021-12-15 17:22:01,225 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 106332 to 73647. [2021-12-15 17:22:01,287 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 73647 states, 73647 states have (on average 1.3963908916860157) internal successors, (102840), 73646 states have internal predecessors, (102840), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:22:01,415 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 73647 states to 73647 states and 102840 transitions. [2021-12-15 17:22:01,416 INFO L704 BuchiCegarLoop]: Abstraction has 73647 states and 102840 transitions. [2021-12-15 17:22:01,416 INFO L587 BuchiCegarLoop]: Abstraction has 73647 states and 102840 transitions. [2021-12-15 17:22:01,416 INFO L425 BuchiCegarLoop]: ======== Iteration 25============ [2021-12-15 17:22:01,416 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 73647 states and 102840 transitions. [2021-12-15 17:22:01,664 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 73472 [2021-12-15 17:22:01,664 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:22:01,664 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:22:01,671 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:22:01,671 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:22:01,671 INFO L791 eck$LassoCheckResult]: Stem: 1287042#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 1287043#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 1287430#L1235 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1286439#L574 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1286440#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 1286706#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1286707#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1287301#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1287282#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1286779#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1286780#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1287020#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1287021#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1286864#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1286865#L838 assume !(0 == ~M_E~0); 1287029#L838-2 assume !(0 == ~T1_E~0); 1286401#L843-1 assume !(0 == ~T2_E~0); 1286402#L848-1 assume !(0 == ~T3_E~0); 1286518#L853-1 assume !(0 == ~T4_E~0); 1286848#L858-1 assume !(0 == ~T5_E~0); 1286353#L863-1 assume !(0 == ~T6_E~0); 1286354#L868-1 assume !(0 == ~T7_E~0); 1287362#L873-1 assume !(0 == ~T8_E~0); 1287360#L878-1 assume !(0 == ~E_1~0); 1287336#L883-1 assume !(0 == ~E_2~0); 1287337#L888-1 assume !(0 == ~E_3~0); 1286992#L893-1 assume !(0 == ~E_4~0); 1286993#L898-1 assume !(0 == ~E_5~0); 1287387#L903-1 assume !(0 == ~E_6~0); 1287334#L908-1 assume !(0 == ~E_7~0); 1287139#L913-1 assume !(0 == ~E_8~0); 1286415#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1286416#L402 assume !(1 == ~m_pc~0); 1286620#L402-2 is_master_triggered_~__retres1~0#1 := 0; 1286542#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1286543#L414 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1286787#L1035 assume !(0 != activate_threads_~tmp~1#1); 1286788#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1286839#L421 assume !(1 == ~t1_pc~0); 1287326#L421-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1287365#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1286829#L433 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1286830#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 1286893#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1287379#L440 assume !(1 == ~t2_pc~0); 1287454#L440-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1286551#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1286552#L452 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1287411#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 1287158#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1286737#L459 assume !(1 == ~t3_pc~0); 1286738#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1287323#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1287073#L471 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1286535#L1059 assume !(0 != activate_threads_~tmp___2~0#1); 1286536#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1286546#L478 assume !(1 == ~t4_pc~0); 1286547#L478-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1287217#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1287298#L490 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1286712#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 1286460#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1286461#L497 assume !(1 == ~t5_pc~0); 1286504#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1286505#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1286800#L509 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1286801#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 1287313#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1287314#L516 assume !(1 == ~t6_pc~0); 1287229#L516-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1287018#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1287019#L528 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1286587#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 1286588#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1287010#L535 assume !(1 == ~t7_pc~0); 1287011#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1287093#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1287094#L547 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1287128#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 1287118#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1287119#L554 assume !(1 == ~t8_pc~0); 1286379#L554-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1286380#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1287184#L566 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1286674#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 1286675#L1099-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1286365#L931 assume !(1 == ~M_E~0); 1286366#L931-2 assume !(1 == ~T1_E~0); 1287347#L936-1 assume !(1 == ~T2_E~0); 1287404#L941-1 assume !(1 == ~T3_E~0); 1286840#L946-1 assume !(1 == ~T4_E~0); 1286841#L951-1 assume !(1 == ~T5_E~0); 1286602#L956-1 assume !(1 == ~T6_E~0); 1286603#L961-1 assume !(1 == ~T7_E~0); 1286994#L966-1 assume !(1 == ~T8_E~0); 1286995#L971-1 assume !(1 == ~E_1~0); 1287121#L976-1 assume !(1 == ~E_2~0); 1287085#L981-1 assume !(1 == ~E_3~0); 1286845#L986-1 assume !(1 == ~E_4~0); 1286633#L991-1 assume !(1 == ~E_5~0); 1286634#L996-1 assume !(1 == ~E_6~0); 1287373#L1001-1 assume !(1 == ~E_7~0); 1287040#L1006-1 assume !(1 == ~E_8~0); 1287041#L1011-1 assume { :end_inline_reset_delta_events } true; 1287325#L1272-2 [2021-12-15 17:22:01,672 INFO L793 eck$LassoCheckResult]: Loop: 1287325#L1272-2 assume !false; 1317631#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1317625#L813 assume !false; 1317624#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1317595#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1317580#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1317575#L682 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1317570#L696 assume !(0 != eval_~tmp~0#1); 1317571#L828 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1321626#L574-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1321622#L838-3 assume !(0 == ~M_E~0); 1321623#L838-5 assume !(0 == ~T1_E~0); 1321618#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1321619#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1321923#L853-3 assume !(0 == ~T4_E~0); 1321613#L858-3 assume !(0 == ~T5_E~0); 1321614#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1321609#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1321610#L873-3 assume !(0 == ~T8_E~0); 1321605#L878-3 assume !(0 == ~E_1~0); 1321606#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1321601#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1321602#L893-3 assume !(0 == ~E_4~0); 1321597#L898-3 assume !(0 == ~E_5~0); 1321598#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1321593#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1321594#L913-3 assume !(0 == ~E_8~0); 1321589#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1321590#L402-27 assume !(1 == ~m_pc~0); 1321585#L402-29 is_master_triggered_~__retres1~0#1 := 0; 1321584#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1321582#L414-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1321583#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1321578#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1321579#L421-27 assume !(1 == ~t1_pc~0); 1321919#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 1321573#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1321574#L433-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1321569#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1321570#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1319666#L440-27 assume !(1 == ~t2_pc~0); 1319664#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 1319663#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1319661#L452-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1319662#L1051-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1321744#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1321742#L459-27 assume !(1 == ~t3_pc~0); 1319652#L459-29 is_transmit3_triggered_~__retres1~3#1 := 0; 1319653#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1321759#L471-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1319646#L1059-27 assume !(0 != activate_threads_~tmp___2~0#1); 1319644#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1319511#L478-27 assume !(1 == ~t4_pc~0); 1319510#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 1319509#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1319507#L490-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1319505#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1319503#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1319501#L497-27 assume !(1 == ~t5_pc~0); 1319498#L497-29 is_transmit5_triggered_~__retres1~5#1 := 0; 1319496#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1319494#L509-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1319492#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1319490#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1319488#L516-27 assume !(1 == ~t6_pc~0); 1303342#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 1319485#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1319483#L528-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1319481#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1319479#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1319475#L535-27 assume 1 == ~t7_pc~0; 1319476#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1319468#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1319469#L547-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1319402#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1319403#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1301648#L554-27 assume !(1 == ~t8_pc~0); 1301646#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 1301644#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1301642#L566-9 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1301640#L1099-27 assume !(0 != activate_threads_~tmp___7~0#1); 1301639#L1099-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1301637#L931-3 assume !(1 == ~M_E~0); 1296311#L931-5 assume !(1 == ~T1_E~0); 1301634#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1301632#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1301630#L946-3 assume !(1 == ~T4_E~0); 1301627#L951-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1301625#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1301623#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1301621#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1301619#L971-3 assume !(1 == ~E_1~0); 1301617#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1301615#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1301584#L986-3 assume !(1 == ~E_4~0); 1301583#L991-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1301581#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1301579#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1301577#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1301575#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1301573#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1301509#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1301466#L682-1 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 1297122#L1291 assume !(0 == start_simulation_~tmp~3#1); 1297123#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1317668#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1317666#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1317663#L682-2 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 1317661#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1317659#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1317657#L1254 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 1317655#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 1287325#L1272-2 [2021-12-15 17:22:01,674 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:22:01,674 INFO L85 PathProgramCache]: Analyzing trace with hash -1450780161, now seen corresponding path program 3 times [2021-12-15 17:22:01,674 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:22:01,679 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1529268821] [2021-12-15 17:22:01,679 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:22:01,680 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:22:01,696 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:22:01,707 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-15 17:22:01,713 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:22:01,765 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-15 17:22:01,765 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:22:01,766 INFO L85 PathProgramCache]: Analyzing trace with hash 1078124701, now seen corresponding path program 1 times [2021-12-15 17:22:01,766 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:22:01,766 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1084392652] [2021-12-15 17:22:01,766 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:22:01,766 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:22:01,773 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:22:01,789 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:22:01,790 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:22:01,790 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1084392652] [2021-12-15 17:22:01,790 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1084392652] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:22:01,790 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:22:01,790 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-15 17:22:01,790 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [238081383] [2021-12-15 17:22:01,790 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:22:01,791 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:22:01,791 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:22:01,791 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-15 17:22:01,791 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-15 17:22:01,792 INFO L87 Difference]: Start difference. First operand 73647 states and 102840 transitions. cyclomatic complexity: 29195 Second operand has 5 states, 5 states have (on average 22.4) internal successors, (112), 5 states have internal predecessors, (112), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:22:02,211 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:22:02,211 INFO L93 Difference]: Finished difference Result 134031 states and 185560 transitions. [2021-12-15 17:22:02,212 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2021-12-15 17:22:02,212 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 134031 states and 185560 transitions. [2021-12-15 17:22:03,312 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 133792 [2021-12-15 17:22:03,659 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 134031 states to 134031 states and 185560 transitions. [2021-12-15 17:22:03,659 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 134031 [2021-12-15 17:22:03,749 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 134031 [2021-12-15 17:22:03,750 INFO L73 IsDeterministic]: Start isDeterministic. Operand 134031 states and 185560 transitions. [2021-12-15 17:22:03,839 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:22:03,839 INFO L681 BuchiCegarLoop]: Abstraction has 134031 states and 185560 transitions. [2021-12-15 17:22:03,910 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 134031 states and 185560 transitions. [2021-12-15 17:22:04,983 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 134031 to 74031. [2021-12-15 17:22:05,038 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 74031 states, 74031 states have (on average 1.3943348056895084) internal successors, (103224), 74030 states have internal predecessors, (103224), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:22:05,166 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 74031 states to 74031 states and 103224 transitions. [2021-12-15 17:22:05,166 INFO L704 BuchiCegarLoop]: Abstraction has 74031 states and 103224 transitions. [2021-12-15 17:22:05,166 INFO L587 BuchiCegarLoop]: Abstraction has 74031 states and 103224 transitions. [2021-12-15 17:22:05,167 INFO L425 BuchiCegarLoop]: ======== Iteration 26============ [2021-12-15 17:22:05,167 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 74031 states and 103224 transitions. [2021-12-15 17:22:05,376 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 73856 [2021-12-15 17:22:05,376 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:22:05,376 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:22:05,396 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:22:05,396 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:22:05,397 INFO L791 eck$LassoCheckResult]: Stem: 1494741#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 1494742#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 1495106#L1235 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1494133#L574 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1494134#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 1494400#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1494401#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1494986#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1494970#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1494474#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1494475#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1494718#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1494719#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1494560#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1494561#L838 assume !(0 == ~M_E~0); 1494726#L838-2 assume !(0 == ~T1_E~0); 1494095#L843-1 assume !(0 == ~T2_E~0); 1494096#L848-1 assume !(0 == ~T3_E~0); 1494212#L853-1 assume !(0 == ~T4_E~0); 1494546#L858-1 assume !(0 == ~T5_E~0); 1494047#L863-1 assume !(0 == ~T6_E~0); 1494048#L868-1 assume !(0 == ~T7_E~0); 1495048#L873-1 assume !(0 == ~T8_E~0); 1495046#L878-1 assume !(0 == ~E_1~0); 1495026#L883-1 assume !(0 == ~E_2~0); 1495027#L888-1 assume !(0 == ~E_3~0); 1494688#L893-1 assume !(0 == ~E_4~0); 1494689#L898-1 assume !(0 == ~E_5~0); 1495069#L903-1 assume !(0 == ~E_6~0); 1495023#L908-1 assume !(0 == ~E_7~0); 1494833#L913-1 assume !(0 == ~E_8~0); 1494109#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1494110#L402 assume !(1 == ~m_pc~0); 1494316#L402-2 is_master_triggered_~__retres1~0#1 := 0; 1494236#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1494237#L414 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1494482#L1035 assume !(0 != activate_threads_~tmp~1#1); 1494483#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1494537#L421 assume !(1 == ~t1_pc~0); 1495012#L421-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1495049#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1494528#L433 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1494529#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 1494592#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1495061#L440 assume !(1 == ~t2_pc~0); 1495123#L440-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1494246#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1494247#L452 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1495088#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 1494852#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1494432#L459 assume !(1 == ~t3_pc~0); 1494433#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1495010#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1494767#L471 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1494229#L1059 assume !(0 != activate_threads_~tmp___2~0#1); 1494230#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1494240#L478 assume !(1 == ~t4_pc~0); 1494241#L478-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1494916#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1494985#L490 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1494406#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 1494154#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1494155#L497 assume !(1 == ~t5_pc~0); 1494198#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1494199#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1494496#L509 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1494497#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 1495001#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1495002#L516 assume !(1 == ~t6_pc~0); 1494926#L516-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1494716#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1494717#L528 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1494282#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 1494283#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1494708#L535 assume !(1 == ~t7_pc~0); 1494709#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1494786#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1494787#L547 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1494823#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 1494813#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1494814#L554 assume !(1 == ~t8_pc~0); 1494073#L554-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1494074#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1494878#L566 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1494369#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 1494370#L1099-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1494059#L931 assume !(1 == ~M_E~0); 1494060#L931-2 assume !(1 == ~T1_E~0); 1495037#L936-1 assume !(1 == ~T2_E~0); 1495084#L941-1 assume !(1 == ~T3_E~0); 1494538#L946-1 assume !(1 == ~T4_E~0); 1494539#L951-1 assume !(1 == ~T5_E~0); 1494298#L956-1 assume !(1 == ~T6_E~0); 1494299#L961-1 assume !(1 == ~T7_E~0); 1494690#L966-1 assume !(1 == ~T8_E~0); 1494691#L971-1 assume !(1 == ~E_1~0); 1494816#L976-1 assume !(1 == ~E_2~0); 1494778#L981-1 assume !(1 == ~E_3~0); 1494543#L986-1 assume !(1 == ~E_4~0); 1494328#L991-1 assume !(1 == ~E_5~0); 1494329#L996-1 assume !(1 == ~E_6~0); 1495054#L1001-1 assume !(1 == ~E_7~0); 1494739#L1006-1 assume !(1 == ~E_8~0); 1494740#L1011-1 assume { :end_inline_reset_delta_events } true; 1495011#L1272-2 [2021-12-15 17:22:05,406 INFO L793 eck$LassoCheckResult]: Loop: 1495011#L1272-2 assume !false; 1527207#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1518400#L813 assume !false; 1527038#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1527008#L634 assume !(0 == ~m_st~0); 1527009#L638 assume !(0 == ~t1_st~0); 1527004#L642 assume !(0 == ~t2_st~0); 1527005#L646 assume !(0 == ~t3_st~0); 1527007#L650 assume !(0 == ~t4_st~0); 1527000#L654 assume !(0 == ~t5_st~0); 1527001#L658 assume !(0 == ~t6_st~0); 1527006#L662 assume !(0 == ~t7_st~0); 1527002#L666 assume !(0 == ~t8_st~0);exists_runnable_thread_~__retres1~9#1 := 0; 1527003#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1518176#L682 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1518177#L696 assume !(0 != eval_~tmp~0#1); 1528876#L828 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1528874#L574-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1528871#L838-3 assume !(0 == ~M_E~0); 1528868#L838-5 assume !(0 == ~T1_E~0); 1528865#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1528862#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1528859#L853-3 assume !(0 == ~T4_E~0); 1528856#L858-3 assume !(0 == ~T5_E~0); 1528853#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1528850#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1528847#L873-3 assume !(0 == ~T8_E~0); 1528844#L878-3 assume !(0 == ~E_1~0); 1528841#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1528838#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1528835#L893-3 assume !(0 == ~E_4~0); 1528832#L898-3 assume !(0 == ~E_5~0); 1528828#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1528825#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1528822#L913-3 assume !(0 == ~E_8~0); 1528819#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1528816#L402-27 assume !(1 == ~m_pc~0); 1528812#L402-29 is_master_triggered_~__retres1~0#1 := 0; 1528809#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1528805#L414-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1528802#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1528799#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1528796#L421-27 assume !(1 == ~t1_pc~0); 1528793#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 1528790#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1528788#L433-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1528785#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1528782#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1528779#L440-27 assume !(1 == ~t2_pc~0); 1519535#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 1528774#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1528771#L452-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1528767#L1051-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1528763#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1528759#L459-27 assume !(1 == ~t3_pc~0); 1528756#L459-29 is_transmit3_triggered_~__retres1~3#1 := 0; 1528752#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1528748#L471-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1528743#L1059-27 assume !(0 != activate_threads_~tmp___2~0#1); 1528738#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1528734#L478-27 assume !(1 == ~t4_pc~0); 1522137#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 1528729#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1528726#L490-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1528723#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1528720#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1528717#L497-27 assume 1 == ~t5_pc~0; 1528714#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1528710#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1528707#L509-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1528704#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1528701#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1528698#L516-27 assume !(1 == ~t6_pc~0); 1525416#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 1528693#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1528690#L528-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1528687#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1528684#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1528681#L535-27 assume 1 == ~t7_pc~0; 1528678#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1528674#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1528671#L547-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1528668#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1528665#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1528662#L554-27 assume !(1 == ~t8_pc~0); 1514556#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 1495275#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1495276#L566-9 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1495269#L1099-27 assume !(0 != activate_threads_~tmp___7~0#1); 1495270#L1099-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1495264#L931-3 assume !(1 == ~M_E~0); 1495260#L931-5 assume !(1 == ~T1_E~0); 1495258#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1495256#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1495254#L946-3 assume !(1 == ~T4_E~0); 1495252#L951-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1495250#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1495248#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1495246#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1495244#L971-3 assume !(1 == ~E_1~0); 1495242#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1495240#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1495238#L986-3 assume !(1 == ~E_4~0); 1495237#L991-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1495236#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1495235#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1495234#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1495233#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1495232#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1495220#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1495215#L682-1 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 1495205#L1291 assume !(0 == start_simulation_~tmp~3#1); 1495206#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1527229#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1527225#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1527223#L682-2 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 1527221#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1527217#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1527213#L1254 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 1527211#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 1495011#L1272-2 [2021-12-15 17:22:05,407 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:22:05,407 INFO L85 PathProgramCache]: Analyzing trace with hash -1450780161, now seen corresponding path program 4 times [2021-12-15 17:22:05,407 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:22:05,408 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1554787291] [2021-12-15 17:22:05,408 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:22:05,408 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:22:05,413 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:22:05,414 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-15 17:22:05,418 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:22:05,455 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-15 17:22:05,456 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:22:05,456 INFO L85 PathProgramCache]: Analyzing trace with hash 844561512, now seen corresponding path program 1 times [2021-12-15 17:22:05,457 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:22:05,457 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1868963825] [2021-12-15 17:22:05,457 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:22:05,457 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:22:05,469 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:22:05,512 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:22:05,512 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:22:05,512 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1868963825] [2021-12-15 17:22:05,512 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1868963825] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:22:05,512 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:22:05,513 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-15 17:22:05,513 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [351308330] [2021-12-15 17:22:05,513 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:22:05,513 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:22:05,513 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:22:05,514 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-15 17:22:05,514 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-15 17:22:05,514 INFO L87 Difference]: Start difference. First operand 74031 states and 103224 transitions. cyclomatic complexity: 29195 Second operand has 5 states, 5 states have (on average 24.0) internal successors, (120), 5 states have internal predecessors, (120), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:22:06,044 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:22:06,044 INFO L93 Difference]: Finished difference Result 158047 states and 222007 transitions. [2021-12-15 17:22:06,045 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-15 17:22:06,045 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 158047 states and 222007 transitions. [2021-12-15 17:22:07,247 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 157776 [2021-12-15 17:22:07,609 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 158047 states to 158047 states and 222007 transitions. [2021-12-15 17:22:07,609 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 158047 [2021-12-15 17:22:07,715 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 158047 [2021-12-15 17:22:07,715 INFO L73 IsDeterministic]: Start isDeterministic. Operand 158047 states and 222007 transitions. [2021-12-15 17:22:07,806 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:22:07,806 INFO L681 BuchiCegarLoop]: Abstraction has 158047 states and 222007 transitions. [2021-12-15 17:22:07,894 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 158047 states and 222007 transitions. [2021-12-15 17:22:08,997 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 158047 to 75375. [2021-12-15 17:22:09,048 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 75375 states, 75375 states have (on average 1.381771144278607) internal successors, (104151), 75374 states have internal predecessors, (104151), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:22:09,169 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 75375 states to 75375 states and 104151 transitions. [2021-12-15 17:22:09,169 INFO L704 BuchiCegarLoop]: Abstraction has 75375 states and 104151 transitions. [2021-12-15 17:22:09,169 INFO L587 BuchiCegarLoop]: Abstraction has 75375 states and 104151 transitions. [2021-12-15 17:22:09,169 INFO L425 BuchiCegarLoop]: ======== Iteration 27============ [2021-12-15 17:22:09,169 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 75375 states and 104151 transitions. [2021-12-15 17:22:09,373 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 75200 [2021-12-15 17:22:09,374 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:22:09,374 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:22:09,379 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:22:09,379 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:22:09,380 INFO L791 eck$LassoCheckResult]: Stem: 1726840#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 1726841#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 1727233#L1235 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1726226#L574 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1726227#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 1726495#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1726496#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1727106#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1727087#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1726569#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1726570#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1726820#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1726821#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1726656#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1726657#L838 assume !(0 == ~M_E~0); 1726828#L838-2 assume !(0 == ~T1_E~0); 1726188#L843-1 assume !(0 == ~T2_E~0); 1726189#L848-1 assume !(0 == ~T3_E~0); 1726306#L853-1 assume !(0 == ~T4_E~0); 1726644#L858-1 assume !(0 == ~T5_E~0); 1726140#L863-1 assume !(0 == ~T6_E~0); 1726141#L868-1 assume !(0 == ~T7_E~0); 1727174#L873-1 assume !(0 == ~T8_E~0); 1727169#L878-1 assume !(0 == ~E_1~0); 1727143#L883-1 assume !(0 == ~E_2~0); 1727144#L888-1 assume !(0 == ~E_3~0); 1726791#L893-1 assume !(0 == ~E_4~0); 1726792#L898-1 assume !(0 == ~E_5~0); 1727200#L903-1 assume !(0 == ~E_6~0); 1727142#L908-1 assume !(0 == ~E_7~0); 1726940#L913-1 assume !(0 == ~E_8~0); 1726202#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1726203#L402 assume !(1 == ~m_pc~0); 1726415#L402-2 is_master_triggered_~__retres1~0#1 := 0; 1726330#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1726331#L414 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1726577#L1035 assume !(0 != activate_threads_~tmp~1#1); 1726578#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1726633#L421 assume !(1 == ~t1_pc~0); 1727130#L421-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1727178#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1726623#L433 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1726624#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 1726689#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1727189#L440 assume !(1 == ~t2_pc~0); 1727261#L440-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1726340#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1726341#L452 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1727216#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 1726958#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1726531#L459 assume !(1 == ~t3_pc~0); 1726532#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1727127#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1727186#L471 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1726323#L1059 assume !(0 != activate_threads_~tmp___2~0#1); 1726324#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1726334#L478 assume !(1 == ~t4_pc~0); 1726335#L478-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1727021#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1727105#L490 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1726501#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 1726249#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1726250#L497 assume !(1 == ~t5_pc~0); 1726291#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1726292#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1726591#L509 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1726592#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 1727120#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1727121#L516 assume !(1 == ~t6_pc~0); 1727039#L516-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1726817#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1726818#L528 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1726377#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 1726378#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1726809#L535 assume !(1 == ~t7_pc~0); 1726810#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1726893#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1726894#L547 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1726928#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 1726919#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1726920#L554 assume !(1 == ~t8_pc~0); 1726164#L554-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1726165#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1726986#L566 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1726466#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 1726467#L1099-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1726150#L931 assume !(1 == ~M_E~0); 1726151#L931-2 assume !(1 == ~T1_E~0); 1727161#L936-1 assume !(1 == ~T2_E~0); 1727213#L941-1 assume !(1 == ~T3_E~0); 1726634#L946-1 assume !(1 == ~T4_E~0); 1726635#L951-1 assume !(1 == ~T5_E~0); 1726393#L956-1 assume !(1 == ~T6_E~0); 1726394#L961-1 assume !(1 == ~T7_E~0); 1726793#L966-1 assume !(1 == ~T8_E~0); 1726794#L971-1 assume !(1 == ~E_1~0); 1726922#L976-1 assume !(1 == ~E_2~0); 1726885#L981-1 assume !(1 == ~E_3~0); 1726639#L986-1 assume !(1 == ~E_4~0); 1726423#L991-1 assume !(1 == ~E_5~0); 1726424#L996-1 assume !(1 == ~E_6~0); 1727181#L1001-1 assume !(1 == ~E_7~0); 1726838#L1006-1 assume !(1 == ~E_8~0); 1726839#L1011-1 assume { :end_inline_reset_delta_events } true; 1727128#L1272-2 [2021-12-15 17:22:09,380 INFO L793 eck$LassoCheckResult]: Loop: 1727128#L1272-2 assume !false; 1800859#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1800164#L813 assume !false; 1800856#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1800854#L634 assume !(0 == ~m_st~0); 1800852#L638 assume !(0 == ~t1_st~0); 1800850#L642 assume !(0 == ~t2_st~0); 1800848#L646 assume !(0 == ~t3_st~0); 1800846#L650 assume !(0 == ~t4_st~0); 1800844#L654 assume !(0 == ~t5_st~0); 1800842#L658 assume !(0 == ~t6_st~0); 1800839#L662 assume !(0 == ~t7_st~0); 1800836#L666 assume !(0 == ~t8_st~0);exists_runnable_thread_~__retres1~9#1 := 0; 1800834#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1800832#L682 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1800830#L696 assume !(0 != eval_~tmp~0#1); 1800828#L828 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1800826#L574-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1800824#L838-3 assume !(0 == ~M_E~0); 1800822#L838-5 assume !(0 == ~T1_E~0); 1800820#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1800818#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1800816#L853-3 assume !(0 == ~T4_E~0); 1800814#L858-3 assume !(0 == ~T5_E~0); 1800812#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1800810#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1800808#L873-3 assume !(0 == ~T8_E~0); 1800806#L878-3 assume !(0 == ~E_1~0); 1800804#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1800802#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1800800#L893-3 assume !(0 == ~E_4~0); 1800796#L898-3 assume !(0 == ~E_5~0); 1800794#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1799296#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1798969#L913-3 assume !(0 == ~E_8~0); 1798970#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1798812#L402-27 assume !(1 == ~m_pc~0); 1798811#L402-29 is_master_triggered_~__retres1~0#1 := 0; 1798806#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1798807#L414-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1798802#L1035-27 assume !(0 != activate_threads_~tmp~1#1); 1798803#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1798798#L421-27 assume !(1 == ~t1_pc~0); 1798799#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 1798794#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1798795#L433-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1798790#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1798791#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1798787#L440-27 assume !(1 == ~t2_pc~0); 1798538#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 1798783#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1798784#L452-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1798779#L1051-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1798780#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1798774#L459-27 assume 1 == ~t3_pc~0; 1798776#L460-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1798766#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1798767#L471-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1798759#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1798760#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1798756#L478-27 assume !(1 == ~t4_pc~0); 1763754#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 1798753#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1798754#L490-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1798749#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1798750#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1798744#L497-27 assume 1 == ~t5_pc~0; 1798746#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1798739#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1798740#L509-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1798735#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1798736#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1798732#L516-27 assume !(1 == ~t6_pc~0); 1753871#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 1798728#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1798729#L528-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1798724#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1798725#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1798719#L535-27 assume !(1 == ~t7_pc~0); 1798721#L535-29 is_transmit7_triggered_~__retres1~7#1 := 0; 1798714#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1798715#L547-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1798710#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1798711#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1798707#L554-27 assume !(1 == ~t8_pc~0); 1798706#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 1798705#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1798704#L566-9 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1798703#L1099-27 assume !(0 != activate_threads_~tmp___7~0#1); 1798702#L1099-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1798701#L931-3 assume !(1 == ~M_E~0); 1790037#L931-5 assume !(1 == ~T1_E~0); 1798448#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1798446#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1798442#L946-3 assume !(1 == ~T4_E~0); 1798438#L951-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1798434#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1798430#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1798426#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1798421#L971-3 assume !(1 == ~E_1~0); 1798416#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1798411#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1798406#L986-3 assume !(1 == ~E_4~0); 1798402#L991-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1798398#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1798395#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1798391#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1798387#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1798380#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1798361#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1798358#L682-1 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 1798355#L1291 assume !(0 == start_simulation_~tmp~3#1); 1798356#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1800905#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1800892#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1800880#L682-2 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 1800879#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1800875#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1800870#L1254 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 1800864#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 1727128#L1272-2 [2021-12-15 17:22:09,380 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:22:09,381 INFO L85 PathProgramCache]: Analyzing trace with hash -1450780161, now seen corresponding path program 5 times [2021-12-15 17:22:09,381 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:22:09,381 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [385085123] [2021-12-15 17:22:09,381 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:22:09,381 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:22:09,387 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:22:09,387 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-15 17:22:09,391 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:22:09,405 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-15 17:22:09,405 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:22:09,405 INFO L85 PathProgramCache]: Analyzing trace with hash -1954753048, now seen corresponding path program 1 times [2021-12-15 17:22:09,406 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:22:09,406 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [352512055] [2021-12-15 17:22:09,406 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:22:09,406 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:22:09,411 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:22:09,422 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:22:09,422 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:22:09,423 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [352512055] [2021-12-15 17:22:09,423 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [352512055] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:22:09,423 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:22:09,423 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:22:09,423 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1189661180] [2021-12-15 17:22:09,423 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:22:09,424 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:22:09,424 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:22:09,424 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:22:09,424 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:22:09,424 INFO L87 Difference]: Start difference. First operand 75375 states and 104151 transitions. cyclomatic complexity: 28778 Second operand has 3 states, 3 states have (on average 40.0) internal successors, (120), 3 states have internal predecessors, (120), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:22:09,738 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:22:09,738 INFO L93 Difference]: Finished difference Result 135375 states and 185719 transitions. [2021-12-15 17:22:09,738 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:22:09,739 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 135375 states and 185719 transitions. [2021-12-15 17:22:10,332 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 135136 [2021-12-15 17:22:11,202 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 135375 states to 135375 states and 185719 transitions. [2021-12-15 17:22:11,203 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 135375 [2021-12-15 17:22:11,267 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 135375 [2021-12-15 17:22:11,268 INFO L73 IsDeterministic]: Start isDeterministic. Operand 135375 states and 185719 transitions. [2021-12-15 17:22:11,336 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:22:11,336 INFO L681 BuchiCegarLoop]: Abstraction has 135375 states and 185719 transitions. [2021-12-15 17:22:11,393 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 135375 states and 185719 transitions. [2021-12-15 17:22:12,833 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 135375 to 131519. [2021-12-15 17:22:12,911 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 131519 states, 131519 states have (on average 1.3736646416107179) internal successors, (180663), 131518 states have internal predecessors, (180663), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:22:13,129 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 131519 states to 131519 states and 180663 transitions. [2021-12-15 17:22:13,129 INFO L704 BuchiCegarLoop]: Abstraction has 131519 states and 180663 transitions. [2021-12-15 17:22:13,129 INFO L587 BuchiCegarLoop]: Abstraction has 131519 states and 180663 transitions. [2021-12-15 17:22:13,129 INFO L425 BuchiCegarLoop]: ======== Iteration 28============ [2021-12-15 17:22:13,129 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 131519 states and 180663 transitions. [2021-12-15 17:22:13,509 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 131280 [2021-12-15 17:22:13,510 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:22:13,510 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:22:13,541 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:22:13,542 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:22:13,542 INFO L791 eck$LassoCheckResult]: Stem: 1937598#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 1937599#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 1938000#L1235 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1936980#L574 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1936981#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 1937251#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1937252#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1937861#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1937846#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1937324#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1937325#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1937575#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1937576#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1937410#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1937411#L838 assume !(0 == ~M_E~0); 1937584#L838-2 assume !(0 == ~T1_E~0); 1936942#L843-1 assume !(0 == ~T2_E~0); 1936943#L848-1 assume !(0 == ~T3_E~0); 1937058#L853-1 assume !(0 == ~T4_E~0); 1937398#L858-1 assume !(0 == ~T5_E~0); 1936896#L863-1 assume !(0 == ~T6_E~0); 1936897#L868-1 assume !(0 == ~T7_E~0); 1937930#L873-1 assume !(0 == ~T8_E~0); 1937926#L878-1 assume !(0 == ~E_1~0); 1937897#L883-1 assume !(0 == ~E_2~0); 1937898#L888-1 assume !(0 == ~E_3~0); 1937548#L893-1 assume !(0 == ~E_4~0); 1937549#L898-1 assume !(0 == ~E_5~0); 1937959#L903-1 assume !(0 == ~E_6~0); 1937894#L908-1 assume !(0 == ~E_7~0); 1937693#L913-1 assume !(0 == ~E_8~0); 1936956#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1936957#L402 assume !(1 == ~m_pc~0); 1937168#L402-2 is_master_triggered_~__retres1~0#1 := 0; 1937082#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1937083#L414 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1937331#L1035 assume !(0 != activate_threads_~tmp~1#1); 1937332#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1937387#L421 assume !(1 == ~t1_pc~0); 1937885#L421-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1937936#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1937375#L433 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1937376#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 1937443#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1937948#L440 assume !(1 == ~t2_pc~0); 1938027#L440-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1937092#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1937093#L452 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1937982#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 1937711#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1937284#L459 assume !(1 == ~t3_pc~0); 1937285#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1937882#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1937947#L471 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1937075#L1059 assume !(0 != activate_threads_~tmp___2~0#1); 1937076#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1937086#L478 assume !(1 == ~t4_pc~0); 1937087#L478-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1937777#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1937860#L490 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1937257#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 1937002#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1937003#L497 assume !(1 == ~t5_pc~0); 1937044#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1937045#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1937345#L509 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1937346#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 1937873#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1937874#L516 assume !(1 == ~t6_pc~0); 1937791#L516-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1937572#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1937573#L528 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1937129#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 1937130#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1937564#L535 assume !(1 == ~t7_pc~0); 1937565#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1937642#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1937643#L547 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1937679#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 1937670#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1937671#L554 assume !(1 == ~t8_pc~0); 1936920#L554-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1936921#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1937740#L566 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1937222#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 1937223#L1099-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1936906#L931 assume !(1 == ~M_E~0); 1936907#L931-2 assume !(1 == ~T1_E~0); 1937913#L936-1 assume !(1 == ~T2_E~0); 1937976#L941-1 assume !(1 == ~T3_E~0); 1937388#L946-1 assume !(1 == ~T4_E~0); 1937389#L951-1 assume !(1 == ~T5_E~0); 1937146#L956-1 assume !(1 == ~T6_E~0); 1937147#L961-1 assume !(1 == ~T7_E~0); 1937550#L966-1 assume !(1 == ~T8_E~0); 1937551#L971-1 assume !(1 == ~E_1~0); 1937673#L976-1 assume !(1 == ~E_2~0); 1937634#L981-1 assume !(1 == ~E_3~0); 1937393#L986-1 assume !(1 == ~E_4~0); 1937176#L991-1 assume !(1 == ~E_5~0); 1937177#L996-1 assume !(1 == ~E_6~0); 1937938#L1001-1 assume !(1 == ~E_7~0); 1937596#L1006-1 assume !(1 == ~E_8~0); 1937597#L1011-1 assume { :end_inline_reset_delta_events } true; 1937883#L1272-2 [2021-12-15 17:22:13,549 INFO L793 eck$LassoCheckResult]: Loop: 1937883#L1272-2 assume !false; 1966450#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1966445#L813 assume !false; 1966443#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1966441#L634 assume !(0 == ~m_st~0); 1966442#L638 assume !(0 == ~t1_st~0); 1982814#L642 assume !(0 == ~t2_st~0); 1982815#L646 assume !(0 == ~t3_st~0); 1982819#L650 assume !(0 == ~t4_st~0); 1982812#L654 assume !(0 == ~t5_st~0); 1982813#L658 assume !(0 == ~t6_st~0); 1982818#L662 assume !(0 == ~t7_st~0); 1982816#L666 assume !(0 == ~t8_st~0);exists_runnable_thread_~__retres1~9#1 := 0; 1982817#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1982805#L682 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1982806#L696 assume !(0 != eval_~tmp~0#1); 1988039#L828 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1988034#L574-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1988029#L838-3 assume !(0 == ~M_E~0); 1988023#L838-5 assume !(0 == ~T1_E~0); 1988017#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1987999#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1987992#L853-3 assume !(0 == ~T4_E~0); 1987987#L858-3 assume !(0 == ~T5_E~0); 1987982#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1987970#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1987963#L873-3 assume !(0 == ~T8_E~0); 1987957#L878-3 assume !(0 == ~E_1~0); 1987952#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1987946#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1987940#L893-3 assume !(0 == ~E_4~0); 1987935#L898-3 assume !(0 == ~E_5~0); 1987929#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1987924#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1987847#L913-3 assume !(0 == ~E_8~0); 1987840#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1987832#L402-27 assume !(1 == ~m_pc~0); 1987822#L402-29 is_master_triggered_~__retres1~0#1 := 0; 1987813#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1987805#L414-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1987797#L1035-27 assume !(0 != activate_threads_~tmp~1#1); 1987782#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1987773#L421-27 assume !(1 == ~t1_pc~0); 1987764#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 1987756#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1987750#L433-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1983056#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1983055#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1983052#L440-27 assume !(1 == ~t2_pc~0); 1973295#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 1983051#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1983049#L452-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1983047#L1051-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1983046#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1983045#L459-27 assume !(1 == ~t3_pc~0); 1983042#L459-29 is_transmit3_triggered_~__retres1~3#1 := 0; 1983040#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1983037#L471-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1983035#L1059-27 assume !(0 != activate_threads_~tmp___2~0#1); 1983032#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1983030#L478-27 assume !(1 == ~t4_pc~0); 1976274#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 1983027#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1983024#L490-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1983022#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1983020#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1983018#L497-27 assume !(1 == ~t5_pc~0); 1983007#L497-29 is_transmit5_triggered_~__retres1~5#1 := 0; 1983005#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1983002#L509-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1983000#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1982998#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1982996#L516-27 assume !(1 == ~t6_pc~0); 1944216#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 1982993#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1982991#L528-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1982990#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1982989#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1982988#L535-27 assume !(1 == ~t7_pc~0); 1982986#L535-29 is_transmit7_triggered_~__retres1~7#1 := 0; 1982985#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1982984#L547-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1982983#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1982982#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1982981#L554-27 assume !(1 == ~t8_pc~0); 1966040#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 1982980#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1982972#L566-9 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1982970#L1099-27 assume !(0 != activate_threads_~tmp___7~0#1); 1982968#L1099-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1959030#L931-3 assume !(1 == ~M_E~0); 1959029#L931-5 assume !(1 == ~T1_E~0); 1983096#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1983095#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1983094#L946-3 assume !(1 == ~T4_E~0); 1983093#L951-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1983092#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1983090#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1983088#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1983086#L971-3 assume !(1 == ~E_1~0); 1983084#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1983081#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1983003#L986-3 assume !(1 == ~E_4~0); 1983001#L991-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1982999#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1982997#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1982995#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1982994#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1982992#L634-1 assume !(0 == ~m_st~0); 1943734#L638-1 assume 0 == ~t1_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1982971#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1982969#L682-1 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 1982967#L1291 assume 0 == start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 4;assume { :begin_inline_fire_time_events } true;~M_E~0 := 1; 1943699#L1125 assume { :end_inline_fire_time_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1943693#L402-30 assume 1 == ~m_pc~0; 1943683#L403-10 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1943675#L413-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1943667#L414-10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1943582#L1035-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1943580#L1035-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1943578#L421-30 assume !(1 == ~t1_pc~0); 1943576#L421-32 is_transmit1_triggered_~__retres1~1#1 := 0; 1943573#L432-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1943571#L433-10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1943569#L1043-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1943567#L1043-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1943565#L440-30 assume !(1 == ~t2_pc~0); 1943561#L440-32 is_transmit2_triggered_~__retres1~2#1 := 0; 1943559#L451-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1943557#L452-10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1943555#L1051-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1943553#L1051-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1943552#L459-30 assume !(1 == ~t3_pc~0); 1943551#L459-32 is_transmit3_triggered_~__retres1~3#1 := 0; 1943549#L470-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1943547#L471-10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1943515#L1059-30 assume !(0 != activate_threads_~tmp___2~0#1); 1943505#L1059-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1943495#L478-30 assume !(1 == ~t4_pc~0); 1943485#L478-32 is_transmit4_triggered_~__retres1~4#1 := 0; 1943478#L489-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1943473#L490-10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1943465#L1067-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1943458#L1067-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1943450#L497-30 assume 1 == ~t5_pc~0; 1943444#L498-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1943441#L508-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1943437#L509-10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1943435#L1075-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1943434#L1075-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1943428#L516-30 assume !(1 == ~t6_pc~0); 1942273#L516-32 is_transmit6_triggered_~__retres1~6#1 := 0; 1943405#L527-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1943400#L528-10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1943395#L1083-30 assume !(0 != activate_threads_~tmp___5~0#1); 1943388#L1083-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1943381#L535-30 assume !(1 == ~t7_pc~0); 1943372#L535-32 is_transmit7_triggered_~__retres1~7#1 := 0; 1943362#L546-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1943355#L547-10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1943347#L1091-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1943341#L1091-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1943335#L554-30 assume !(1 == ~t8_pc~0); 1943192#L554-32 is_transmit8_triggered_~__retres1~8#1 := 0; 1943322#L565-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1943316#L566-10 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1943310#L1099-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1943303#L1099-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_time_events } true; 1943296#L1132 assume 1 == ~M_E~0;~M_E~0 := 2; 1943297#L1132-2 assume !(1 == ~T1_E~0); 1966518#L1137-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1966516#L1142-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1966514#L1147-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1966512#L1152-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1966508#L1157-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1966506#L1162-1 assume !(1 == ~T7_E~0); 1966504#L1167-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1966502#L1172-1 assume !(1 == ~E_1~0); 1966498#L1177-1 assume 1 == ~E_2~0;~E_2~0 := 2; 1966495#L1182-1 assume 1 == ~E_3~0;~E_3~0 := 2; 1966492#L1187-1 assume 1 == ~E_4~0;~E_4~0 := 2; 1966489#L1192-1 assume 1 == ~E_5~0;~E_5~0 := 2; 1966486#L1197-1 assume 1 == ~E_6~0;~E_6~0 := 2; 1966483#L1202-1 assume !(1 == ~E_7~0); 1966480#L1207-1 assume 1 == ~E_8~0;~E_8~0 := 2; 1966477#L1212-1 assume { :end_inline_reset_time_events } true; 1943708#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1966469#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1966466#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1966463#L682-2 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 1966460#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1966457#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1966455#L1254 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 1966453#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 1937883#L1272-2 [2021-12-15 17:22:13,549 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:22:13,549 INFO L85 PathProgramCache]: Analyzing trace with hash -1450780161, now seen corresponding path program 6 times [2021-12-15 17:22:13,550 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:22:13,559 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1569832151] [2021-12-15 17:22:13,559 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:22:13,563 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:22:13,569 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:22:13,569 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-15 17:22:13,573 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-15 17:22:13,588 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-15 17:22:13,588 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:22:13,588 INFO L85 PathProgramCache]: Analyzing trace with hash -1910271708, now seen corresponding path program 1 times [2021-12-15 17:22:13,589 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:22:13,589 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [792809638] [2021-12-15 17:22:13,589 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:22:13,589 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:22:13,596 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:22:13,611 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:22:13,611 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:22:13,611 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [792809638] [2021-12-15 17:22:13,611 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [792809638] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:22:13,611 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:22:13,611 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:22:13,612 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1640815786] [2021-12-15 17:22:13,612 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:22:13,612 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:22:13,612 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:22:13,612 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:22:13,612 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:22:13,613 INFO L87 Difference]: Start difference. First operand 131519 states and 180663 transitions. cyclomatic complexity: 49146 Second operand has 3 states, 3 states have (on average 64.66666666666667) internal successors, (194), 3 states have internal predecessors, (194), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:22:14,818 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:22:14,839 INFO L93 Difference]: Finished difference Result 244446 states and 334069 transitions. [2021-12-15 17:22:14,839 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:22:14,840 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 244446 states and 334069 transitions. [2021-12-15 17:22:16,064 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 244080 [2021-12-15 17:22:16,700 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 244446 states to 244446 states and 334069 transitions. [2021-12-15 17:22:16,701 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 244446 [2021-12-15 17:22:16,862 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 244446 [2021-12-15 17:22:16,862 INFO L73 IsDeterministic]: Start isDeterministic. Operand 244446 states and 334069 transitions. [2021-12-15 17:22:17,605 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:22:17,606 INFO L681 BuchiCegarLoop]: Abstraction has 244446 states and 334069 transitions. [2021-12-15 17:22:17,775 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 244446 states and 334069 transitions.