./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/transmitter.15.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 3a877d22 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/transmitter.15.cil.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 05397c7941b2acd95b1b6d02c6c64b476ab8b290a5b56301ff8db7ca1986067b --- Real Ultimate output --- This is Ultimate 0.2.2-3a877d227dc491413fd706022d0c47cd97beb353-3a877d2 [2021-12-15 17:21:43,761 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-12-15 17:21:43,762 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-12-15 17:21:43,811 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-12-15 17:21:43,812 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-12-15 17:21:43,812 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-12-15 17:21:43,813 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-12-15 17:21:43,814 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-12-15 17:21:43,815 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-12-15 17:21:43,816 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-12-15 17:21:43,817 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-12-15 17:21:43,817 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-12-15 17:21:43,818 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-12-15 17:21:43,818 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-12-15 17:21:43,819 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-12-15 17:21:43,820 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-12-15 17:21:43,820 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-12-15 17:21:43,821 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-12-15 17:21:43,822 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-12-15 17:21:43,823 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-12-15 17:21:43,824 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-12-15 17:21:43,825 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-12-15 17:21:43,826 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-12-15 17:21:43,826 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-12-15 17:21:43,828 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-12-15 17:21:43,828 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-12-15 17:21:43,828 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-12-15 17:21:43,829 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-12-15 17:21:43,829 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-12-15 17:21:43,830 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-12-15 17:21:43,830 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-12-15 17:21:43,830 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-12-15 17:21:43,831 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-12-15 17:21:43,831 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-12-15 17:21:43,832 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-12-15 17:21:43,832 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-12-15 17:21:43,833 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-12-15 17:21:43,833 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-12-15 17:21:43,833 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-12-15 17:21:43,834 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-12-15 17:21:43,834 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-12-15 17:21:43,835 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2021-12-15 17:21:43,849 INFO L113 SettingsManager]: Loading preferences was successful [2021-12-15 17:21:43,849 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-12-15 17:21:43,850 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2021-12-15 17:21:43,850 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2021-12-15 17:21:43,851 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-12-15 17:21:43,851 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-12-15 17:21:43,851 INFO L138 SettingsManager]: * Use SBE=true [2021-12-15 17:21:43,851 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2021-12-15 17:21:43,851 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2021-12-15 17:21:43,852 INFO L138 SettingsManager]: * Use old map elimination=false [2021-12-15 17:21:43,852 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2021-12-15 17:21:43,852 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2021-12-15 17:21:43,852 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2021-12-15 17:21:43,852 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-12-15 17:21:43,852 INFO L138 SettingsManager]: * sizeof long=4 [2021-12-15 17:21:43,853 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2021-12-15 17:21:43,853 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-12-15 17:21:43,853 INFO L138 SettingsManager]: * sizeof POINTER=4 [2021-12-15 17:21:43,853 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-12-15 17:21:43,853 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2021-12-15 17:21:43,853 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2021-12-15 17:21:43,854 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2021-12-15 17:21:43,854 INFO L138 SettingsManager]: * sizeof long double=12 [2021-12-15 17:21:43,854 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-12-15 17:21:43,854 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2021-12-15 17:21:43,854 INFO L138 SettingsManager]: * Use constant arrays=true [2021-12-15 17:21:43,854 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2021-12-15 17:21:43,855 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-12-15 17:21:43,855 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-12-15 17:21:43,855 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-12-15 17:21:43,855 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-12-15 17:21:43,855 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2021-12-15 17:21:43,856 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2021-12-15 17:21:43,856 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 05397c7941b2acd95b1b6d02c6c64b476ab8b290a5b56301ff8db7ca1986067b [2021-12-15 17:21:44,020 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-12-15 17:21:44,035 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-12-15 17:21:44,037 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-12-15 17:21:44,038 INFO L271 PluginConnector]: Initializing CDTParser... [2021-12-15 17:21:44,038 INFO L275 PluginConnector]: CDTParser initialized [2021-12-15 17:21:44,039 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/transmitter.15.cil.c [2021-12-15 17:21:44,091 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/2e12062ca/ff2d8d72b6d84d7281019fbe796ded1b/FLAGaf61dee28 [2021-12-15 17:21:44,471 INFO L306 CDTParser]: Found 1 translation units. [2021-12-15 17:21:44,472 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.15.cil.c [2021-12-15 17:21:44,481 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/2e12062ca/ff2d8d72b6d84d7281019fbe796ded1b/FLAGaf61dee28 [2021-12-15 17:21:44,491 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/2e12062ca/ff2d8d72b6d84d7281019fbe796ded1b [2021-12-15 17:21:44,493 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-12-15 17:21:44,494 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-12-15 17:21:44,495 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-12-15 17:21:44,495 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-12-15 17:21:44,498 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-12-15 17:21:44,498 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 15.12 05:21:44" (1/1) ... [2021-12-15 17:21:44,499 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@14221207 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:21:44, skipping insertion in model container [2021-12-15 17:21:44,499 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 15.12 05:21:44" (1/1) ... [2021-12-15 17:21:44,504 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-12-15 17:21:44,530 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-12-15 17:21:44,662 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.15.cil.c[706,719] [2021-12-15 17:21:44,733 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-15 17:21:44,741 INFO L203 MainTranslator]: Completed pre-run [2021-12-15 17:21:44,748 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.15.cil.c[706,719] [2021-12-15 17:21:44,785 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-15 17:21:44,799 INFO L208 MainTranslator]: Completed translation [2021-12-15 17:21:44,799 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:21:44 WrapperNode [2021-12-15 17:21:44,799 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-12-15 17:21:44,800 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-12-15 17:21:44,800 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-12-15 17:21:44,800 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-12-15 17:21:44,805 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:21:44" (1/1) ... [2021-12-15 17:21:44,813 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:21:44" (1/1) ... [2021-12-15 17:21:44,901 INFO L137 Inliner]: procedures = 54, calls = 69, calls flagged for inlining = 64, calls inlined = 286, statements flattened = 4413 [2021-12-15 17:21:44,901 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-12-15 17:21:44,903 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-12-15 17:21:44,903 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-12-15 17:21:44,903 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-12-15 17:21:44,909 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:21:44" (1/1) ... [2021-12-15 17:21:44,909 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:21:44" (1/1) ... [2021-12-15 17:21:44,919 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:21:44" (1/1) ... [2021-12-15 17:21:44,920 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:21:44" (1/1) ... [2021-12-15 17:21:44,959 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:21:44" (1/1) ... [2021-12-15 17:21:44,987 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:21:44" (1/1) ... [2021-12-15 17:21:44,995 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:21:44" (1/1) ... [2021-12-15 17:21:45,008 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-12-15 17:21:45,010 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-12-15 17:21:45,010 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-12-15 17:21:45,011 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-12-15 17:21:45,012 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:21:44" (1/1) ... [2021-12-15 17:21:45,017 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-15 17:21:45,025 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-15 17:21:45,038 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-15 17:21:45,058 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2021-12-15 17:21:45,070 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2021-12-15 17:21:45,070 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2021-12-15 17:21:45,071 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-12-15 17:21:45,071 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-12-15 17:21:45,190 INFO L236 CfgBuilder]: Building ICFG [2021-12-15 17:21:45,191 INFO L262 CfgBuilder]: Building CFG for each procedure with an implementation [2021-12-15 17:21:46,613 INFO L277 CfgBuilder]: Performing block encoding [2021-12-15 17:21:46,630 INFO L296 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-12-15 17:21:46,631 INFO L301 CfgBuilder]: Removed 17 assume(true) statements. [2021-12-15 17:21:46,634 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 15.12 05:21:46 BoogieIcfgContainer [2021-12-15 17:21:46,634 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-12-15 17:21:46,636 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2021-12-15 17:21:46,636 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2021-12-15 17:21:46,638 INFO L275 PluginConnector]: BuchiAutomizer initialized [2021-12-15 17:21:46,639 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-15 17:21:46,639 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 15.12 05:21:44" (1/3) ... [2021-12-15 17:21:46,640 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@583b9d06 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 15.12 05:21:46, skipping insertion in model container [2021-12-15 17:21:46,640 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-15 17:21:46,640 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.12 05:21:44" (2/3) ... [2021-12-15 17:21:46,640 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@583b9d06 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 15.12 05:21:46, skipping insertion in model container [2021-12-15 17:21:46,640 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-15 17:21:46,641 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 15.12 05:21:46" (3/3) ... [2021-12-15 17:21:46,641 INFO L388 chiAutomizerObserver]: Analyzing ICFG transmitter.15.cil.c [2021-12-15 17:21:46,676 INFO L359 BuchiCegarLoop]: Interprodecural is true [2021-12-15 17:21:46,676 INFO L360 BuchiCegarLoop]: Hoare is false [2021-12-15 17:21:46,676 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2021-12-15 17:21:46,676 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2021-12-15 17:21:46,676 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2021-12-15 17:21:46,676 INFO L364 BuchiCegarLoop]: Difference is false [2021-12-15 17:21:46,677 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2021-12-15 17:21:46,677 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2021-12-15 17:21:46,734 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1920 states, 1919 states have (on average 1.498697238144867) internal successors, (2876), 1919 states have internal predecessors, (2876), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:46,790 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1743 [2021-12-15 17:21:46,791 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:21:46,791 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:21:46,808 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:46,808 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:46,809 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2021-12-15 17:21:46,811 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1920 states, 1919 states have (on average 1.498697238144867) internal successors, (2876), 1919 states have internal predecessors, (2876), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:46,824 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1743 [2021-12-15 17:21:46,824 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:21:46,824 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:21:46,826 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:46,826 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:46,833 INFO L791 eck$LassoCheckResult]: Stem: 461#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 1833#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 352#L1855true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 201#L874true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1759#L881true assume !(1 == ~m_i~0);~m_st~0 := 2; 1072#L881-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 1410#L886-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 272#L891-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1401#L896-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 545#L901-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 439#L906-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 795#L911-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 306#L916-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 554#L921-1true assume 1 == ~t9_i~0;~t9_st~0 := 0; 683#L926-1true assume !(1 == ~t10_i~0);~t10_st~0 := 2; 803#L931-1true assume !(1 == ~t11_i~0);~t11_st~0 := 2; 833#L936-1true assume !(1 == ~t12_i~0);~t12_st~0 := 2; 920#L941-1true assume !(1 == ~t13_i~0);~t13_st~0 := 2; 313#L946-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1814#L1258true assume 0 == ~M_E~0;~M_E~0 := 1; 1399#L1258-2true assume !(0 == ~T1_E~0); 490#L1263-1true assume !(0 == ~T2_E~0); 709#L1268-1true assume !(0 == ~T3_E~0); 1365#L1273-1true assume !(0 == ~T4_E~0); 1748#L1278-1true assume !(0 == ~T5_E~0); 1152#L1283-1true assume !(0 == ~T6_E~0); 1780#L1288-1true assume !(0 == ~T7_E~0); 1568#L1293-1true assume 0 == ~T8_E~0;~T8_E~0 := 1; 1539#L1298-1true assume !(0 == ~T9_E~0); 1383#L1303-1true assume !(0 == ~T10_E~0); 215#L1308-1true assume !(0 == ~T11_E~0); 186#L1313-1true assume !(0 == ~T12_E~0); 1838#L1318-1true assume !(0 == ~T13_E~0); 189#L1323-1true assume !(0 == ~E_1~0); 277#L1328-1true assume !(0 == ~E_2~0); 1789#L1333-1true assume 0 == ~E_3~0;~E_3~0 := 1; 973#L1338-1true assume !(0 == ~E_4~0); 1112#L1343-1true assume !(0 == ~E_5~0); 1650#L1348-1true assume !(0 == ~E_6~0); 1667#L1353-1true assume !(0 == ~E_7~0); 725#L1358-1true assume !(0 == ~E_8~0); 999#L1363-1true assume !(0 == ~E_9~0); 1061#L1368-1true assume !(0 == ~E_10~0); 105#L1373-1true assume 0 == ~E_11~0;~E_11~0 := 1; 489#L1378-1true assume !(0 == ~E_12~0); 250#L1383-1true assume !(0 == ~E_13~0); 1101#L1388-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 729#L607true assume 1 == ~m_pc~0; 1009#L608true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1108#L618true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1626#L619true activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 667#L1560true assume !(0 != activate_threads_~tmp~1#1); 1724#L1560-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 196#L626true assume !(1 == ~t1_pc~0); 1266#L626-2true is_transmit1_triggered_~__retres1~1#1 := 0; 339#L637true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 441#L638true activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1907#L1568true assume !(0 != activate_threads_~tmp___0~0#1); 147#L1568-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1336#L645true assume 1 == ~t2_pc~0; 205#L646true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1300#L656true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 584#L657true activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1899#L1576true assume !(0 != activate_threads_~tmp___1~0#1); 652#L1576-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1704#L664true assume 1 == ~t3_pc~0; 1633#L665true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 66#L675true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1126#L676true activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 417#L1584true assume !(0 != activate_threads_~tmp___2~0#1); 1419#L1584-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1627#L683true assume !(1 == ~t4_pc~0); 986#L683-2true is_transmit4_triggered_~__retres1~4#1 := 0; 785#L694true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 810#L695true activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1694#L1592true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 931#L1592-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 615#L702true assume 1 == ~t5_pc~0; 1684#L703true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 925#L713true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1343#L714true activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1391#L1600true assume !(0 != activate_threads_~tmp___4~0#1); 1237#L1600-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 90#L721true assume !(1 == ~t6_pc~0); 77#L721-2true is_transmit6_triggered_~__retres1~6#1 := 0; 161#L732true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 557#L733true activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 422#L1608true assume !(0 != activate_threads_~tmp___5~0#1); 1524#L1608-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 867#L740true assume 1 == ~t7_pc~0; 116#L741true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 21#L751true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 757#L752true activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 16#L1616true assume !(0 != activate_threads_~tmp___6~0#1); 762#L1616-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 385#L759true assume !(1 == ~t8_pc~0); 1373#L759-2true is_transmit8_triggered_~__retres1~8#1 := 0; 1843#L770true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 923#L771true activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1083#L1624true assume !(0 != activate_threads_~tmp___7~0#1); 1670#L1624-2true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1567#L778true assume 1 == ~t9_pc~0; 1341#L779true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1273#L789true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 73#L790true activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 36#L1632true assume !(0 != activate_threads_~tmp___8~0#1); 733#L1632-2true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 203#L797true assume !(1 == ~t10_pc~0); 265#L797-2true is_transmit10_triggered_~__retres1~10#1 := 0; 1306#L808true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1181#L809true activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 488#L1640true assume !(0 != activate_threads_~tmp___9~0#1); 696#L1640-2true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1390#L816true assume 1 == ~t11_pc~0; 57#L817true assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 588#L827true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 463#L828true activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 427#L1648true assume !(0 != activate_threads_~tmp___10~0#1); 1511#L1648-2true assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 802#L835true assume 1 == ~t12_pc~0; 705#L836true assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 151#L846true is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 222#L847true activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1783#L1656true assume !(0 != activate_threads_~tmp___11~0#1); 527#L1656-2true assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 1442#L854true assume !(1 == ~t13_pc~0); 307#L854-2true is_transmit13_triggered_~__retres1~13#1 := 0; 336#L865true is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 1081#L866true activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 160#L1664true assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 1230#L1664-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1790#L1401true assume !(1 == ~M_E~0); 419#L1401-2true assume !(1 == ~T1_E~0); 1240#L1406-1true assume !(1 == ~T2_E~0); 858#L1411-1true assume !(1 == ~T3_E~0); 1611#L1416-1true assume 1 == ~T4_E~0;~T4_E~0 := 2; 595#L1421-1true assume !(1 == ~T5_E~0); 305#L1426-1true assume !(1 == ~T6_E~0); 1014#L1431-1true assume !(1 == ~T7_E~0); 75#L1436-1true assume !(1 == ~T8_E~0); 745#L1441-1true assume !(1 == ~T9_E~0); 483#L1446-1true assume !(1 == ~T10_E~0); 1772#L1451-1true assume !(1 == ~T11_E~0); 1107#L1456-1true assume 1 == ~T12_E~0;~T12_E~0 := 2; 744#L1461-1true assume !(1 == ~T13_E~0); 436#L1466-1true assume !(1 == ~E_1~0); 1767#L1471-1true assume !(1 == ~E_2~0); 1082#L1476-1true assume !(1 == ~E_3~0); 1314#L1481-1true assume !(1 == ~E_4~0); 1592#L1486-1true assume !(1 == ~E_5~0); 225#L1491-1true assume !(1 == ~E_6~0); 42#L1496-1true assume 1 == ~E_7~0;~E_7~0 := 2; 756#L1501-1true assume !(1 == ~E_8~0); 481#L1506-1true assume !(1 == ~E_9~0); 1037#L1511-1true assume !(1 == ~E_10~0); 454#L1516-1true assume !(1 == ~E_11~0); 14#L1521-1true assume !(1 == ~E_12~0); 41#L1526-1true assume !(1 == ~E_13~0); 319#L1531-1true assume { :end_inline_reset_delta_events } true; 1171#L1892-2true [2021-12-15 17:21:46,835 INFO L793 eck$LassoCheckResult]: Loop: 1171#L1892-2true assume !false; 1867#L1893true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1513#L1233true assume !true; 81#L1248true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 804#L874-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1629#L1258-3true assume 0 == ~M_E~0;~M_E~0 := 1; 1898#L1258-5true assume !(0 == ~T1_E~0); 154#L1263-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 1603#L1268-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 1618#L1273-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 1905#L1278-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 1620#L1283-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 267#L1288-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 1788#L1293-3true assume 0 == ~T8_E~0;~T8_E~0 := 1; 1168#L1298-3true assume !(0 == ~T9_E~0); 1693#L1303-3true assume 0 == ~T10_E~0;~T10_E~0 := 1; 1427#L1308-3true assume 0 == ~T11_E~0;~T11_E~0 := 1; 1167#L1313-3true assume 0 == ~T12_E~0;~T12_E~0 := 1; 658#L1318-3true assume 0 == ~T13_E~0;~T13_E~0 := 1; 155#L1323-3true assume 0 == ~E_1~0;~E_1~0 := 1; 1301#L1328-3true assume 0 == ~E_2~0;~E_2~0 := 1; 1672#L1333-3true assume 0 == ~E_3~0;~E_3~0 := 1; 229#L1338-3true assume !(0 == ~E_4~0); 1055#L1343-3true assume 0 == ~E_5~0;~E_5~0 := 1; 1540#L1348-3true assume 0 == ~E_6~0;~E_6~0 := 1; 1311#L1353-3true assume 0 == ~E_7~0;~E_7~0 := 1; 1352#L1358-3true assume 0 == ~E_8~0;~E_8~0 := 1; 627#L1363-3true assume 0 == ~E_9~0;~E_9~0 := 1; 340#L1368-3true assume 0 == ~E_10~0;~E_10~0 := 1; 1884#L1373-3true assume 0 == ~E_11~0;~E_11~0 := 1; 884#L1378-3true assume !(0 == ~E_12~0); 1459#L1383-3true assume 0 == ~E_13~0;~E_13~0 := 1; 1099#L1388-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1766#L607-42true assume !(1 == ~m_pc~0); 911#L607-44true is_master_triggered_~__retres1~0#1 := 0; 510#L618-14true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1075#L619-14true activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 349#L1560-42true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 697#L1560-44true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1219#L626-42true assume 1 == ~t1_pc~0; 399#L627-14true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1471#L637-14true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 600#L638-14true activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1130#L1568-42true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 171#L1568-44true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1573#L645-42true assume 1 == ~t2_pc~0; 1415#L646-14true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1695#L656-14true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1252#L657-14true activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 278#L1576-42true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 24#L1576-44true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1661#L664-42true assume 1 == ~t3_pc~0; 457#L665-14true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1623#L675-14true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1474#L676-14true activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 832#L1584-42true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1015#L1584-44true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1787#L683-42true assume 1 == ~t4_pc~0; 1698#L684-14true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 840#L694-14true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1768#L695-14true activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1411#L1592-42true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1903#L1592-44true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1162#L702-42true assume !(1 == ~t5_pc~0); 395#L702-44true is_transmit5_triggered_~__retres1~5#1 := 0; 590#L713-14true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1733#L714-14true activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1287#L1600-42true assume !(0 != activate_threads_~tmp___4~0#1); 33#L1600-44true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 114#L721-42true assume 1 == ~t6_pc~0; 123#L722-14true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 368#L732-14true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1619#L733-14true activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1587#L1608-42true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 470#L1608-44true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 379#L740-42true assume !(1 == ~t7_pc~0); 236#L740-44true is_transmit7_triggered_~__retres1~7#1 := 0; 561#L751-14true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 560#L752-14true activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 459#L1616-42true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 650#L1616-44true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1895#L759-42true assume 1 == ~t8_pc~0; 540#L760-14true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 493#L770-14true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 673#L771-14true activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 547#L1624-42true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 617#L1624-44true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1174#L778-42true assume !(1 == ~t9_pc~0); 620#L778-44true is_transmit9_triggered_~__retres1~9#1 := 0; 808#L789-14true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1749#L790-14true activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 732#L1632-42true assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1612#L1632-44true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 780#L797-42true assume !(1 == ~t10_pc~0); 1045#L797-44true is_transmit10_triggered_~__retres1~10#1 := 0; 937#L808-14true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1375#L809-14true activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1876#L1640-42true assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 809#L1640-44true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1708#L816-42true assume !(1 == ~t11_pc~0); 347#L816-44true is_transmit11_triggered_~__retres1~11#1 := 0; 1851#L827-14true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 285#L828-14true activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 486#L1648-42true assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 328#L1648-44true assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 587#L835-42true assume !(1 == ~t12_pc~0); 507#L835-44true is_transmit12_triggered_~__retres1~12#1 := 0; 1243#L846-14true is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 314#L847-14true activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1837#L1656-42true assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 1236#L1656-44true assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 949#L854-42true assume 1 == ~t13_pc~0; 1781#L855-14true assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 482#L865-14true is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 86#L866-14true activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 515#L1664-42true assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 435#L1664-44true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1854#L1401-3true assume !(1 == ~M_E~0); 1093#L1401-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 204#L1406-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 136#L1411-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 1679#L1416-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 465#L1421-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 1052#L1426-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 228#L1431-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 293#L1436-3true assume !(1 == ~T8_E~0); 17#L1441-3true assume 1 == ~T9_E~0;~T9_E~0 := 2; 1144#L1446-3true assume 1 == ~T10_E~0;~T10_E~0 := 2; 1135#L1451-3true assume 1 == ~T11_E~0;~T11_E~0 := 2; 521#L1456-3true assume 1 == ~T12_E~0;~T12_E~0 := 2; 309#L1461-3true assume 1 == ~T13_E~0;~T13_E~0 := 2; 1610#L1466-3true assume 1 == ~E_1~0;~E_1~0 := 2; 1816#L1471-3true assume 1 == ~E_2~0;~E_2~0 := 2; 279#L1476-3true assume !(1 == ~E_3~0); 1686#L1481-3true assume 1 == ~E_4~0;~E_4~0 := 2; 514#L1486-3true assume 1 == ~E_5~0;~E_5~0 := 2; 292#L1491-3true assume 1 == ~E_6~0;~E_6~0 := 2; 1481#L1496-3true assume 1 == ~E_7~0;~E_7~0 := 2; 544#L1501-3true assume 1 == ~E_8~0;~E_8~0 := 2; 1594#L1506-3true assume 1 == ~E_9~0;~E_9~0 := 2; 881#L1511-3true assume 1 == ~E_10~0;~E_10~0 := 2; 874#L1516-3true assume !(1 == ~E_11~0); 1718#L1521-3true assume 1 == ~E_12~0;~E_12~0 := 2; 630#L1526-3true assume 1 == ~E_13~0;~E_13~0 := 2; 969#L1531-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 1842#L959-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 1880#L1031-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 760#L1032-1true start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 494#L1911true assume !(0 == start_simulation_~tmp~3#1); 1304#L1911-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 906#L959-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 1024#L1031-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 842#L1032-2true stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 107#L1866true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 520#L1873true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 224#L1874true start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 1348#L1924true assume !(0 != start_simulation_~tmp___0~1#1); 1171#L1892-2true [2021-12-15 17:21:46,839 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:46,839 INFO L85 PathProgramCache]: Analyzing trace with hash 517365666, now seen corresponding path program 1 times [2021-12-15 17:21:46,844 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:46,845 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [608479526] [2021-12-15 17:21:46,845 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:46,846 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:46,933 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:47,020 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:47,020 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:47,021 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [608479526] [2021-12-15 17:21:47,021 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [608479526] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:47,021 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:47,021 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:47,023 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [971575952] [2021-12-15 17:21:47,023 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:47,026 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:21:47,027 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:47,027 INFO L85 PathProgramCache]: Analyzing trace with hash 1403862028, now seen corresponding path program 1 times [2021-12-15 17:21:47,027 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:47,027 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1577460596] [2021-12-15 17:21:47,027 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:47,027 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:47,039 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:47,081 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:47,082 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:47,082 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1577460596] [2021-12-15 17:21:47,082 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1577460596] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:47,082 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:47,082 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-15 17:21:47,082 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [71239408] [2021-12-15 17:21:47,082 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:47,084 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:21:47,084 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:21:47,147 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2021-12-15 17:21:47,148 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2021-12-15 17:21:47,151 INFO L87 Difference]: Start difference. First operand has 1920 states, 1919 states have (on average 1.498697238144867) internal successors, (2876), 1919 states have internal predecessors, (2876), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 2 states, 2 states have (on average 78.5) internal successors, (157), 2 states have internal predecessors, (157), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:47,210 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:21:47,217 INFO L93 Difference]: Finished difference Result 1919 states and 2840 transitions. [2021-12-15 17:21:47,222 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2021-12-15 17:21:47,226 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1919 states and 2840 transitions. [2021-12-15 17:21:47,236 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2021-12-15 17:21:47,249 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1919 states to 1914 states and 2835 transitions. [2021-12-15 17:21:47,250 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1914 [2021-12-15 17:21:47,252 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1914 [2021-12-15 17:21:47,253 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1914 states and 2835 transitions. [2021-12-15 17:21:47,261 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:21:47,261 INFO L681 BuchiCegarLoop]: Abstraction has 1914 states and 2835 transitions. [2021-12-15 17:21:47,277 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1914 states and 2835 transitions. [2021-12-15 17:21:47,321 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1914 to 1914. [2021-12-15 17:21:47,333 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1914 states, 1914 states have (on average 1.4811912225705328) internal successors, (2835), 1913 states have internal predecessors, (2835), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:47,338 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1914 states to 1914 states and 2835 transitions. [2021-12-15 17:21:47,338 INFO L704 BuchiCegarLoop]: Abstraction has 1914 states and 2835 transitions. [2021-12-15 17:21:47,339 INFO L587 BuchiCegarLoop]: Abstraction has 1914 states and 2835 transitions. [2021-12-15 17:21:47,339 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2021-12-15 17:21:47,339 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1914 states and 2835 transitions. [2021-12-15 17:21:47,346 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2021-12-15 17:21:47,346 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:21:47,346 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:21:47,348 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:47,348 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:47,348 INFO L791 eck$LassoCheckResult]: Stem: 4709#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 4710#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 4529#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4245#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4246#L881 assume !(1 == ~m_i~0);~m_st~0 := 2; 5422#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5423#L886-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 4381#L891-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 4382#L896-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 4836#L901-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 4671#L906-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 4672#L911-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 4448#L916-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 4449#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 4847#L926-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 5024#L931-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 5178#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 5215#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 4459#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4460#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 5635#L1258-2 assume !(0 == ~T1_E~0); 4754#L1263-1 assume !(0 == ~T2_E~0); 4755#L1268-1 assume !(0 == ~T3_E~0); 5058#L1273-1 assume !(0 == ~T4_E~0); 5617#L1278-1 assume !(0 == ~T5_E~0); 5478#L1283-1 assume !(0 == ~T6_E~0); 5479#L1288-1 assume !(0 == ~T7_E~0); 5715#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 5703#L1298-1 assume !(0 == ~T9_E~0); 5629#L1303-1 assume !(0 == ~T10_E~0); 4274#L1308-1 assume !(0 == ~T11_E~0); 4216#L1313-1 assume !(0 == ~T12_E~0); 4217#L1318-1 assume !(0 == ~T13_E~0); 4223#L1323-1 assume !(0 == ~E_1~0); 4224#L1328-1 assume !(0 == ~E_2~0); 4391#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 5350#L1338-1 assume !(0 == ~E_4~0); 5351#L1343-1 assume !(0 == ~E_5~0); 5452#L1348-1 assume !(0 == ~E_6~0); 5738#L1353-1 assume !(0 == ~E_7~0); 5077#L1358-1 assume !(0 == ~E_8~0); 5078#L1363-1 assume !(0 == ~E_9~0); 5368#L1368-1 assume !(0 == ~E_10~0); 4053#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 4054#L1378-1 assume !(0 == ~E_12~0); 4340#L1383-1 assume !(0 == ~E_13~0); 4341#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5084#L607 assume 1 == ~m_pc~0; 5085#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 4411#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5450#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5004#L1560 assume !(0 != activate_threads_~tmp~1#1); 5005#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4236#L626 assume !(1 == ~t1_pc~0); 4237#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4505#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4506#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4675#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 4136#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4137#L645 assume 1 == ~t2_pc~0; 4253#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4210#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4887#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4888#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 4980#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4981#L664 assume 1 == ~t3_pc~0; 5737#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3977#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3978#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4636#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 4637#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5645#L683 assume !(1 == ~t4_pc~0); 5200#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 5152#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5153#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 5187#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5311#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4930#L702 assume 1 == ~t5_pc~0; 4931#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 4856#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5306#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 5604#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 5545#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4025#L721 assume !(1 == ~t6_pc~0); 3999#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 4000#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4163#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4645#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 4646#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5247#L740 assume 1 == ~t7_pc~0; 4074#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 3887#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3888#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3877#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 3878#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4581#L759 assume !(1 == ~t8_pc~0); 4582#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 4611#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 5304#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 5305#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 5436#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 5714#L778 assume 1 == ~t9_pc~0; 5601#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 4052#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3992#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 3921#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 3922#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4249#L797 assume !(1 == ~t10_pc~0); 4250#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 4368#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 5502#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 4752#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 4753#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 5042#L816 assume 1 == ~t11_pc~0; 3957#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 3958#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 4713#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 4652#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 4653#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 5177#L835 assume 1 == ~t12_pc~0; 5055#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 4121#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 4143#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 4284#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 4809#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 4810#L854 assume !(1 == ~t13_pc~0); 4450#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 4451#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 4501#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 4161#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 4162#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5541#L1401 assume !(1 == ~M_E~0); 4640#L1401-2 assume !(1 == ~T1_E~0); 4641#L1406-1 assume !(1 == ~T2_E~0); 5236#L1411-1 assume !(1 == ~T3_E~0); 5237#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4903#L1421-1 assume !(1 == ~T5_E~0); 4446#L1426-1 assume !(1 == ~T6_E~0); 4447#L1431-1 assume !(1 == ~T7_E~0); 3995#L1436-1 assume !(1 == ~T8_E~0); 3996#L1441-1 assume !(1 == ~T9_E~0); 4743#L1446-1 assume !(1 == ~T10_E~0); 4744#L1451-1 assume !(1 == ~T11_E~0); 5449#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 5103#L1461-1 assume !(1 == ~T13_E~0); 4664#L1466-1 assume !(1 == ~E_1~0); 4665#L1471-1 assume !(1 == ~E_2~0); 5434#L1476-1 assume !(1 == ~E_3~0); 5435#L1481-1 assume !(1 == ~E_4~0); 5583#L1486-1 assume !(1 == ~E_5~0); 4289#L1491-1 assume !(1 == ~E_6~0); 3929#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 3930#L1501-1 assume !(1 == ~E_8~0); 4741#L1506-1 assume !(1 == ~E_9~0); 4742#L1511-1 assume !(1 == ~E_10~0); 4698#L1516-1 assume !(1 == ~E_11~0); 3873#L1521-1 assume !(1 == ~E_12~0); 3874#L1526-1 assume !(1 == ~E_13~0); 3928#L1531-1 assume { :end_inline_reset_delta_events } true; 4471#L1892-2 [2021-12-15 17:21:47,349 INFO L793 eck$LassoCheckResult]: Loop: 4471#L1892-2 assume !false; 5494#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5692#L1233 assume !false; 5675#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 5007#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 4987#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 5145#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 3971#L1046 assume !(0 != eval_~tmp~0#1); 3973#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4007#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5179#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5736#L1258-5 assume !(0 == ~T1_E~0); 4149#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4150#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5728#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5734#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5735#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4373#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 4374#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 5491#L1298-3 assume !(0 == ~T9_E~0); 5492#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 5651#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 5490#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 4991#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 4151#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4152#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5575#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4294#L1338-3 assume !(0 == ~E_4~0); 4295#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 5407#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 5580#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 5581#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 4947#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 4507#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 4508#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 5264#L1378-3 assume !(0 == ~E_12~0); 5265#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 5446#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5447#L607-42 assume 1 == ~m_pc~0; 5060#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 4788#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4789#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4521#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4522#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5043#L626-42 assume 1 == ~t1_pc~0; 4605#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4606#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4910#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4911#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4185#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4186#L645-42 assume !(1 == ~t2_pc~0); 5385#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 5386#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5551#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4392#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3899#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3900#L664-42 assume !(1 == ~t3_pc~0); 4426#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 4427#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5678#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5213#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5214#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5379#L683-42 assume 1 == ~t4_pc~0; 5744#L684-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5088#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5220#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 5640#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5641#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5485#L702-42 assume !(1 == ~t5_pc~0); 4597#L702-44 is_transmit5_triggered_~__retres1~5#1 := 0; 4598#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4894#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 5567#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 3915#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3916#L721-42 assume 1 == ~t6_pc~0; 4069#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4089#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4553#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 5720#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 4725#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4571#L740-42 assume !(1 == ~t7_pc~0); 4308#L740-44 is_transmit7_triggered_~__retres1~7#1 := 0; 4309#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4850#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4705#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 4706#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4979#L759-42 assume 1 == ~t8_pc~0; 4828#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 4760#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4761#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 4839#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 4840#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4935#L778-42 assume 1 == ~t9_pc~0; 4772#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 4774#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 5184#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 5089#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 5090#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 5147#L797-42 assume 1 == ~t10_pc~0; 4314#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 4315#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 5316#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 5625#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 5185#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 5186#L816-42 assume 1 == ~t11_pc~0; 3863#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 3864#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 4406#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 4407#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 4486#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 4487#L835-42 assume 1 == ~t12_pc~0; 4891#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 4784#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 4461#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 4462#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 5544#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 5328#L854-42 assume 1 == ~t13_pc~0; 5329#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 4405#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 4015#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 4016#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 4662#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4663#L1401-3 assume !(1 == ~M_E~0); 5441#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4252#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4116#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4117#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4716#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4717#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 4292#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 4293#L1436-3 assume !(1 == ~T8_E~0); 3879#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 3880#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 5469#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 4800#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 4453#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 4454#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5731#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4393#L1476-3 assume !(1 == ~E_3~0); 4394#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4794#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4421#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 4422#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 4834#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 4835#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 5261#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 5251#L1516-3 assume !(1 == ~E_11~0); 5252#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 4951#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 4952#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 5346#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 4228#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 5121#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 4762#L1911 assume !(0 == start_simulation_~tmp~3#1); 4763#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 5285#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 4353#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 5223#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 4057#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4058#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4287#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 4288#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 4471#L1892-2 [2021-12-15 17:21:47,350 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:47,350 INFO L85 PathProgramCache]: Analyzing trace with hash 517365666, now seen corresponding path program 2 times [2021-12-15 17:21:47,350 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:47,351 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1745282083] [2021-12-15 17:21:47,351 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:47,351 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:47,373 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:47,417 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:47,417 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:47,417 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1745282083] [2021-12-15 17:21:47,417 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1745282083] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:47,417 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:47,418 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:47,418 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1895543977] [2021-12-15 17:21:47,418 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:47,418 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:21:47,419 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:47,419 INFO L85 PathProgramCache]: Analyzing trace with hash 1475252753, now seen corresponding path program 1 times [2021-12-15 17:21:47,419 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:47,419 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1937606801] [2021-12-15 17:21:47,419 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:47,419 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:47,447 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:47,498 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:47,498 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:47,499 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1937606801] [2021-12-15 17:21:47,499 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1937606801] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:47,499 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:47,499 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:47,499 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [76023702] [2021-12-15 17:21:47,499 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:47,500 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:21:47,500 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:21:47,500 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:21:47,500 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:21:47,501 INFO L87 Difference]: Start difference. First operand 1914 states and 2835 transitions. cyclomatic complexity: 922 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:47,558 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:21:47,558 INFO L93 Difference]: Finished difference Result 1914 states and 2834 transitions. [2021-12-15 17:21:47,558 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:21:47,559 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1914 states and 2834 transitions. [2021-12-15 17:21:47,569 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2021-12-15 17:21:47,576 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1914 states to 1914 states and 2834 transitions. [2021-12-15 17:21:47,576 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1914 [2021-12-15 17:21:47,578 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1914 [2021-12-15 17:21:47,578 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1914 states and 2834 transitions. [2021-12-15 17:21:47,580 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:21:47,580 INFO L681 BuchiCegarLoop]: Abstraction has 1914 states and 2834 transitions. [2021-12-15 17:21:47,581 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1914 states and 2834 transitions. [2021-12-15 17:21:47,599 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1914 to 1914. [2021-12-15 17:21:47,601 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1914 states, 1914 states have (on average 1.4806687565308254) internal successors, (2834), 1913 states have internal predecessors, (2834), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:47,606 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1914 states to 1914 states and 2834 transitions. [2021-12-15 17:21:47,606 INFO L704 BuchiCegarLoop]: Abstraction has 1914 states and 2834 transitions. [2021-12-15 17:21:47,606 INFO L587 BuchiCegarLoop]: Abstraction has 1914 states and 2834 transitions. [2021-12-15 17:21:47,606 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2021-12-15 17:21:47,606 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1914 states and 2834 transitions. [2021-12-15 17:21:47,613 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2021-12-15 17:21:47,614 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:21:47,614 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:21:47,615 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:47,616 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:47,616 INFO L791 eck$LassoCheckResult]: Stem: 8544#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 8545#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 8364#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8080#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 8081#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 9257#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9258#L886-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 8216#L891-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 8217#L896-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 8671#L901-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 8506#L906-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 8507#L911-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 8283#L916-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 8284#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 8682#L926-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 8859#L931-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 9013#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 9050#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 8294#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8295#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 9470#L1258-2 assume !(0 == ~T1_E~0); 8589#L1263-1 assume !(0 == ~T2_E~0); 8590#L1268-1 assume !(0 == ~T3_E~0); 8893#L1273-1 assume !(0 == ~T4_E~0); 9452#L1278-1 assume !(0 == ~T5_E~0); 9313#L1283-1 assume !(0 == ~T6_E~0); 9314#L1288-1 assume !(0 == ~T7_E~0); 9550#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 9538#L1298-1 assume !(0 == ~T9_E~0); 9464#L1303-1 assume !(0 == ~T10_E~0); 8109#L1308-1 assume !(0 == ~T11_E~0); 8051#L1313-1 assume !(0 == ~T12_E~0); 8052#L1318-1 assume !(0 == ~T13_E~0); 8058#L1323-1 assume !(0 == ~E_1~0); 8059#L1328-1 assume !(0 == ~E_2~0); 8226#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 9185#L1338-1 assume !(0 == ~E_4~0); 9186#L1343-1 assume !(0 == ~E_5~0); 9287#L1348-1 assume !(0 == ~E_6~0); 9573#L1353-1 assume !(0 == ~E_7~0); 8912#L1358-1 assume !(0 == ~E_8~0); 8913#L1363-1 assume !(0 == ~E_9~0); 9203#L1368-1 assume !(0 == ~E_10~0); 7888#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 7889#L1378-1 assume !(0 == ~E_12~0); 8175#L1383-1 assume !(0 == ~E_13~0); 8176#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8919#L607 assume 1 == ~m_pc~0; 8920#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 8246#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9285#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8839#L1560 assume !(0 != activate_threads_~tmp~1#1); 8840#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8071#L626 assume !(1 == ~t1_pc~0); 8072#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 8340#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8341#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8510#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 7971#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7972#L645 assume 1 == ~t2_pc~0; 8088#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 8045#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8722#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8723#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 8815#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8816#L664 assume 1 == ~t3_pc~0; 9572#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 7812#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7813#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 8471#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 8472#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9480#L683 assume !(1 == ~t4_pc~0); 9035#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 8987#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8988#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 9022#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 9146#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8765#L702 assume 1 == ~t5_pc~0; 8766#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 8691#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9141#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 9439#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 9380#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7860#L721 assume !(1 == ~t6_pc~0); 7834#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 7835#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7998#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 8480#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 8481#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9082#L740 assume 1 == ~t7_pc~0; 7909#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 7722#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 7723#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 7712#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 7713#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 8416#L759 assume !(1 == ~t8_pc~0); 8417#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 8446#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 9139#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 9140#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 9271#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 9549#L778 assume 1 == ~t9_pc~0; 9436#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 7887#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 7827#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 7756#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 7757#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 8084#L797 assume !(1 == ~t10_pc~0); 8085#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 8203#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 9337#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 8587#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 8588#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 8877#L816 assume 1 == ~t11_pc~0; 7792#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 7793#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 8548#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 8487#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 8488#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 9012#L835 assume 1 == ~t12_pc~0; 8890#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 7956#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 7978#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 8119#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 8644#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 8645#L854 assume !(1 == ~t13_pc~0); 8285#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 8286#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 8336#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 7996#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 7997#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9376#L1401 assume !(1 == ~M_E~0); 8475#L1401-2 assume !(1 == ~T1_E~0); 8476#L1406-1 assume !(1 == ~T2_E~0); 9071#L1411-1 assume !(1 == ~T3_E~0); 9072#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8738#L1421-1 assume !(1 == ~T5_E~0); 8281#L1426-1 assume !(1 == ~T6_E~0); 8282#L1431-1 assume !(1 == ~T7_E~0); 7830#L1436-1 assume !(1 == ~T8_E~0); 7831#L1441-1 assume !(1 == ~T9_E~0); 8578#L1446-1 assume !(1 == ~T10_E~0); 8579#L1451-1 assume !(1 == ~T11_E~0); 9284#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 8938#L1461-1 assume !(1 == ~T13_E~0); 8499#L1466-1 assume !(1 == ~E_1~0); 8500#L1471-1 assume !(1 == ~E_2~0); 9269#L1476-1 assume !(1 == ~E_3~0); 9270#L1481-1 assume !(1 == ~E_4~0); 9418#L1486-1 assume !(1 == ~E_5~0); 8124#L1491-1 assume !(1 == ~E_6~0); 7764#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 7765#L1501-1 assume !(1 == ~E_8~0); 8576#L1506-1 assume !(1 == ~E_9~0); 8577#L1511-1 assume !(1 == ~E_10~0); 8533#L1516-1 assume !(1 == ~E_11~0); 7708#L1521-1 assume !(1 == ~E_12~0); 7709#L1526-1 assume !(1 == ~E_13~0); 7763#L1531-1 assume { :end_inline_reset_delta_events } true; 8306#L1892-2 [2021-12-15 17:21:47,616 INFO L793 eck$LassoCheckResult]: Loop: 8306#L1892-2 assume !false; 9329#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 9527#L1233 assume !false; 9510#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 8842#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 8822#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 8980#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 7806#L1046 assume !(0 != eval_~tmp~0#1); 7808#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 7842#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 9014#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 9571#L1258-5 assume !(0 == ~T1_E~0); 7984#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7985#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 9563#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 9569#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 9570#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 8208#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 8209#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 9326#L1298-3 assume !(0 == ~T9_E~0); 9327#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 9486#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 9325#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 8826#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 7986#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7987#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 9410#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 8129#L1338-3 assume !(0 == ~E_4~0); 8130#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 9242#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 9415#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 9416#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 8782#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 8342#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 8343#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 9099#L1378-3 assume !(0 == ~E_12~0); 9100#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 9281#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9282#L607-42 assume !(1 == ~m_pc~0); 8896#L607-44 is_master_triggered_~__retres1~0#1 := 0; 8623#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8624#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8356#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8357#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8878#L626-42 assume 1 == ~t1_pc~0; 8440#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8441#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8745#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8746#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8020#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8021#L645-42 assume !(1 == ~t2_pc~0); 9220#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 9221#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9386#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8227#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 7734#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7735#L664-42 assume !(1 == ~t3_pc~0); 8261#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 8262#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9513#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9048#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9049#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9214#L683-42 assume !(1 == ~t4_pc~0); 8922#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 8923#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9055#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 9475#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 9476#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9320#L702-42 assume !(1 == ~t5_pc~0); 8432#L702-44 is_transmit5_triggered_~__retres1~5#1 := 0; 8433#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8729#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 9402#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 7750#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7751#L721-42 assume 1 == ~t6_pc~0; 7904#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 7924#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8388#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 9555#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 8560#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8406#L740-42 assume 1 == ~t7_pc~0; 8407#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 8144#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8685#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 8540#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 8541#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 8814#L759-42 assume 1 == ~t8_pc~0; 8663#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 8595#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 8596#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 8674#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 8675#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 8770#L778-42 assume !(1 == ~t9_pc~0); 8608#L778-44 is_transmit9_triggered_~__retres1~9#1 := 0; 8609#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 9019#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 8924#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 8925#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 8982#L797-42 assume 1 == ~t10_pc~0; 8149#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 8150#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 9151#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 9460#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 9020#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 9021#L816-42 assume 1 == ~t11_pc~0; 7698#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 7699#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 8241#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 8242#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 8321#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 8322#L835-42 assume 1 == ~t12_pc~0; 8726#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 8619#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 8296#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 8297#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 9379#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 9163#L854-42 assume 1 == ~t13_pc~0; 9164#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 8240#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 7850#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 7851#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 8497#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8498#L1401-3 assume !(1 == ~M_E~0); 9276#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8087#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7951#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7952#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8551#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 8552#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 8127#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 8128#L1436-3 assume !(1 == ~T8_E~0); 7714#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 7715#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 9304#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 8635#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 8288#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 8289#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 9566#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8228#L1476-3 assume !(1 == ~E_3~0); 8229#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 8629#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 8256#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 8257#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 8669#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 8670#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 9096#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 9086#L1516-3 assume !(1 == ~E_11~0); 9087#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 8786#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 8787#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 9181#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 8063#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 8956#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 8597#L1911 assume !(0 == start_simulation_~tmp~3#1); 8598#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 9120#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 8188#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 9058#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 7892#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 7893#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8122#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 8123#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 8306#L1892-2 [2021-12-15 17:21:47,617 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:47,617 INFO L85 PathProgramCache]: Analyzing trace with hash -2008130016, now seen corresponding path program 1 times [2021-12-15 17:21:47,617 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:47,617 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [359728511] [2021-12-15 17:21:47,617 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:47,618 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:47,630 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:47,649 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:47,650 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:47,650 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [359728511] [2021-12-15 17:21:47,650 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [359728511] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:47,650 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:47,650 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:47,650 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1821775654] [2021-12-15 17:21:47,650 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:47,651 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:21:47,651 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:47,651 INFO L85 PathProgramCache]: Analyzing trace with hash 673979855, now seen corresponding path program 1 times [2021-12-15 17:21:47,651 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:47,651 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1961695331] [2021-12-15 17:21:47,652 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:47,652 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:47,667 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:47,701 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:47,701 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:47,701 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1961695331] [2021-12-15 17:21:47,701 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1961695331] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:47,701 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:47,702 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:47,702 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1707097825] [2021-12-15 17:21:47,702 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:47,702 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:21:47,702 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:21:47,702 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:21:47,703 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:21:47,703 INFO L87 Difference]: Start difference. First operand 1914 states and 2834 transitions. cyclomatic complexity: 921 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:47,724 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:21:47,724 INFO L93 Difference]: Finished difference Result 1914 states and 2833 transitions. [2021-12-15 17:21:47,724 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:21:47,725 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1914 states and 2833 transitions. [2021-12-15 17:21:47,734 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2021-12-15 17:21:47,740 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1914 states to 1914 states and 2833 transitions. [2021-12-15 17:21:47,740 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1914 [2021-12-15 17:21:47,741 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1914 [2021-12-15 17:21:47,742 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1914 states and 2833 transitions. [2021-12-15 17:21:47,743 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:21:47,743 INFO L681 BuchiCegarLoop]: Abstraction has 1914 states and 2833 transitions. [2021-12-15 17:21:47,745 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1914 states and 2833 transitions. [2021-12-15 17:21:47,762 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1914 to 1914. [2021-12-15 17:21:47,764 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1914 states, 1914 states have (on average 1.480146290491118) internal successors, (2833), 1913 states have internal predecessors, (2833), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:47,768 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1914 states to 1914 states and 2833 transitions. [2021-12-15 17:21:47,768 INFO L704 BuchiCegarLoop]: Abstraction has 1914 states and 2833 transitions. [2021-12-15 17:21:47,768 INFO L587 BuchiCegarLoop]: Abstraction has 1914 states and 2833 transitions. [2021-12-15 17:21:47,768 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2021-12-15 17:21:47,768 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1914 states and 2833 transitions. [2021-12-15 17:21:47,774 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2021-12-15 17:21:47,775 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:21:47,775 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:21:47,776 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:47,776 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:47,777 INFO L791 eck$LassoCheckResult]: Stem: 12379#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 12380#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 12199#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 11915#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 11916#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 13092#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 13093#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12051#L891-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 12052#L896-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 12506#L901-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 12341#L906-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 12342#L911-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 12118#L916-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 12119#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 12517#L926-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 12694#L931-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 12848#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 12885#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 12129#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12130#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 13305#L1258-2 assume !(0 == ~T1_E~0); 12424#L1263-1 assume !(0 == ~T2_E~0); 12425#L1268-1 assume !(0 == ~T3_E~0); 12728#L1273-1 assume !(0 == ~T4_E~0); 13287#L1278-1 assume !(0 == ~T5_E~0); 13148#L1283-1 assume !(0 == ~T6_E~0); 13149#L1288-1 assume !(0 == ~T7_E~0); 13385#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 13373#L1298-1 assume !(0 == ~T9_E~0); 13299#L1303-1 assume !(0 == ~T10_E~0); 11944#L1308-1 assume !(0 == ~T11_E~0); 11886#L1313-1 assume !(0 == ~T12_E~0); 11887#L1318-1 assume !(0 == ~T13_E~0); 11893#L1323-1 assume !(0 == ~E_1~0); 11894#L1328-1 assume !(0 == ~E_2~0); 12061#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 13020#L1338-1 assume !(0 == ~E_4~0); 13021#L1343-1 assume !(0 == ~E_5~0); 13122#L1348-1 assume !(0 == ~E_6~0); 13408#L1353-1 assume !(0 == ~E_7~0); 12747#L1358-1 assume !(0 == ~E_8~0); 12748#L1363-1 assume !(0 == ~E_9~0); 13038#L1368-1 assume !(0 == ~E_10~0); 11723#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 11724#L1378-1 assume !(0 == ~E_12~0); 12010#L1383-1 assume !(0 == ~E_13~0); 12011#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12754#L607 assume 1 == ~m_pc~0; 12755#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 12081#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13120#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12674#L1560 assume !(0 != activate_threads_~tmp~1#1); 12675#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11906#L626 assume !(1 == ~t1_pc~0); 11907#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 12175#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12176#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12345#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 11806#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11807#L645 assume 1 == ~t2_pc~0; 11923#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 11880#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12557#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12558#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 12650#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12651#L664 assume 1 == ~t3_pc~0; 13407#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 11647#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11648#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 12306#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 12307#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13315#L683 assume !(1 == ~t4_pc~0); 12870#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 12822#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12823#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 12857#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 12981#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12600#L702 assume 1 == ~t5_pc~0; 12601#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12526#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12976#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 13274#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 13215#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11695#L721 assume !(1 == ~t6_pc~0); 11669#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 11670#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11833#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 12315#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 12316#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12917#L740 assume 1 == ~t7_pc~0; 11744#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 11557#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 11558#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 11547#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 11548#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12251#L759 assume !(1 == ~t8_pc~0); 12252#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 12281#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12974#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 12975#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 13106#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 13384#L778 assume 1 == ~t9_pc~0; 13271#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 11722#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 11662#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 11591#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 11592#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 11919#L797 assume !(1 == ~t10_pc~0); 11920#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 12038#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 13172#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 12422#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 12423#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 12712#L816 assume 1 == ~t11_pc~0; 11627#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 11628#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 12383#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 12322#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 12323#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 12847#L835 assume 1 == ~t12_pc~0; 12725#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 11791#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 11813#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 11954#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 12479#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 12480#L854 assume !(1 == ~t13_pc~0); 12120#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 12121#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 12171#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 11831#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 11832#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13211#L1401 assume !(1 == ~M_E~0); 12310#L1401-2 assume !(1 == ~T1_E~0); 12311#L1406-1 assume !(1 == ~T2_E~0); 12906#L1411-1 assume !(1 == ~T3_E~0); 12907#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12573#L1421-1 assume !(1 == ~T5_E~0); 12116#L1426-1 assume !(1 == ~T6_E~0); 12117#L1431-1 assume !(1 == ~T7_E~0); 11665#L1436-1 assume !(1 == ~T8_E~0); 11666#L1441-1 assume !(1 == ~T9_E~0); 12413#L1446-1 assume !(1 == ~T10_E~0); 12414#L1451-1 assume !(1 == ~T11_E~0); 13119#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 12773#L1461-1 assume !(1 == ~T13_E~0); 12334#L1466-1 assume !(1 == ~E_1~0); 12335#L1471-1 assume !(1 == ~E_2~0); 13104#L1476-1 assume !(1 == ~E_3~0); 13105#L1481-1 assume !(1 == ~E_4~0); 13253#L1486-1 assume !(1 == ~E_5~0); 11959#L1491-1 assume !(1 == ~E_6~0); 11599#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 11600#L1501-1 assume !(1 == ~E_8~0); 12411#L1506-1 assume !(1 == ~E_9~0); 12412#L1511-1 assume !(1 == ~E_10~0); 12368#L1516-1 assume !(1 == ~E_11~0); 11543#L1521-1 assume !(1 == ~E_12~0); 11544#L1526-1 assume !(1 == ~E_13~0); 11598#L1531-1 assume { :end_inline_reset_delta_events } true; 12141#L1892-2 [2021-12-15 17:21:47,777 INFO L793 eck$LassoCheckResult]: Loop: 12141#L1892-2 assume !false; 13164#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 13362#L1233 assume !false; 13345#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 12677#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 12657#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 12815#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 11641#L1046 assume !(0 != eval_~tmp~0#1); 11643#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 11677#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 12849#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 13406#L1258-5 assume !(0 == ~T1_E~0); 11819#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 11820#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 13398#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 13404#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 13405#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 12043#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 12044#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 13161#L1298-3 assume !(0 == ~T9_E~0); 13162#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 13321#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 13160#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 12661#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 11821#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 11822#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 13245#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 11964#L1338-3 assume !(0 == ~E_4~0); 11965#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 13077#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 13250#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 13251#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 12617#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 12177#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 12178#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 12934#L1378-3 assume !(0 == ~E_12~0); 12935#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 13116#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13117#L607-42 assume 1 == ~m_pc~0; 12730#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 12458#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12459#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12191#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12192#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12713#L626-42 assume 1 == ~t1_pc~0; 12275#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 12276#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12580#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12581#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 11855#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11856#L645-42 assume 1 == ~t2_pc~0; 13314#L646-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 13056#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13221#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12062#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 11569#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11570#L664-42 assume !(1 == ~t3_pc~0); 12096#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 12097#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13348#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 12883#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 12884#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13049#L683-42 assume !(1 == ~t4_pc~0); 12757#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 12758#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12890#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 13310#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 13311#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13155#L702-42 assume 1 == ~t5_pc~0; 12643#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12268#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12564#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 13237#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 11585#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11586#L721-42 assume 1 == ~t6_pc~0; 11739#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 11759#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12223#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 13390#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 12395#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12241#L740-42 assume 1 == ~t7_pc~0; 12242#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 11979#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12520#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 12375#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 12376#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12649#L759-42 assume 1 == ~t8_pc~0; 12498#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 12430#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12431#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 12509#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 12510#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 12605#L778-42 assume 1 == ~t9_pc~0; 12442#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 12444#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 12854#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 12759#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 12760#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 12817#L797-42 assume 1 == ~t10_pc~0; 11984#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 11985#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 12986#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 13295#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 12855#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 12856#L816-42 assume 1 == ~t11_pc~0; 11533#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 11534#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 12076#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 12077#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 12156#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 12157#L835-42 assume 1 == ~t12_pc~0; 12561#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 12454#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 12131#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 12132#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 13214#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 12998#L854-42 assume 1 == ~t13_pc~0; 12999#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 12075#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 11685#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 11686#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 12332#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12333#L1401-3 assume !(1 == ~M_E~0); 13111#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 11922#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 11786#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 11787#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12386#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 12387#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 11962#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 11963#L1436-3 assume !(1 == ~T8_E~0); 11549#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 11550#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 13139#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 12470#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 12123#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 12124#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 13401#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 12063#L1476-3 assume !(1 == ~E_3~0); 12064#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 12464#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 12091#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 12092#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 12504#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 12505#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 12931#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 12921#L1516-3 assume !(1 == ~E_11~0); 12922#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 12621#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 12622#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 13016#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 11898#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 12791#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 12432#L1911 assume !(0 == start_simulation_~tmp~3#1); 12433#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 12955#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 12023#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 12893#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 11727#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 11728#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 11957#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 11958#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 12141#L1892-2 [2021-12-15 17:21:47,779 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:47,779 INFO L85 PathProgramCache]: Analyzing trace with hash -602938338, now seen corresponding path program 1 times [2021-12-15 17:21:47,780 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:47,780 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1688827346] [2021-12-15 17:21:47,780 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:47,780 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:47,803 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:47,831 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:47,831 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:47,831 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1688827346] [2021-12-15 17:21:47,847 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1688827346] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:47,847 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:47,847 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:47,848 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [717205187] [2021-12-15 17:21:47,848 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:47,848 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:21:47,848 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:47,848 INFO L85 PathProgramCache]: Analyzing trace with hash 1181403475, now seen corresponding path program 1 times [2021-12-15 17:21:47,848 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:47,849 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2050217637] [2021-12-15 17:21:47,849 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:47,849 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:47,865 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:47,939 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:47,940 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:47,940 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2050217637] [2021-12-15 17:21:47,940 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2050217637] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:47,940 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:47,940 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:47,941 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1147697263] [2021-12-15 17:21:47,941 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:47,941 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:21:47,941 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:21:47,942 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:21:47,943 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:21:47,943 INFO L87 Difference]: Start difference. First operand 1914 states and 2833 transitions. cyclomatic complexity: 920 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:47,967 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:21:47,967 INFO L93 Difference]: Finished difference Result 1914 states and 2832 transitions. [2021-12-15 17:21:47,968 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:21:47,969 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1914 states and 2832 transitions. [2021-12-15 17:21:47,977 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2021-12-15 17:21:47,983 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1914 states to 1914 states and 2832 transitions. [2021-12-15 17:21:47,983 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1914 [2021-12-15 17:21:47,984 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1914 [2021-12-15 17:21:47,984 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1914 states and 2832 transitions. [2021-12-15 17:21:47,988 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:21:47,988 INFO L681 BuchiCegarLoop]: Abstraction has 1914 states and 2832 transitions. [2021-12-15 17:21:47,990 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1914 states and 2832 transitions. [2021-12-15 17:21:48,008 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1914 to 1914. [2021-12-15 17:21:48,011 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1914 states, 1914 states have (on average 1.4796238244514106) internal successors, (2832), 1913 states have internal predecessors, (2832), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:48,016 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1914 states to 1914 states and 2832 transitions. [2021-12-15 17:21:48,016 INFO L704 BuchiCegarLoop]: Abstraction has 1914 states and 2832 transitions. [2021-12-15 17:21:48,016 INFO L587 BuchiCegarLoop]: Abstraction has 1914 states and 2832 transitions. [2021-12-15 17:21:48,016 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2021-12-15 17:21:48,016 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1914 states and 2832 transitions. [2021-12-15 17:21:48,024 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2021-12-15 17:21:48,024 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:21:48,024 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:21:48,025 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:48,025 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:48,026 INFO L791 eck$LassoCheckResult]: Stem: 16214#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 16215#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 16034#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 15750#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 15751#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 16927#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 16928#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 15886#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 15887#L896-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 16341#L901-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 16176#L906-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 16177#L911-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 15953#L916-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 15954#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 16352#L926-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 16529#L931-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 16683#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 16720#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 15964#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 15965#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 17140#L1258-2 assume !(0 == ~T1_E~0); 16259#L1263-1 assume !(0 == ~T2_E~0); 16260#L1268-1 assume !(0 == ~T3_E~0); 16563#L1273-1 assume !(0 == ~T4_E~0); 17122#L1278-1 assume !(0 == ~T5_E~0); 16983#L1283-1 assume !(0 == ~T6_E~0); 16984#L1288-1 assume !(0 == ~T7_E~0); 17220#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 17208#L1298-1 assume !(0 == ~T9_E~0); 17134#L1303-1 assume !(0 == ~T10_E~0); 15779#L1308-1 assume !(0 == ~T11_E~0); 15721#L1313-1 assume !(0 == ~T12_E~0); 15722#L1318-1 assume !(0 == ~T13_E~0); 15728#L1323-1 assume !(0 == ~E_1~0); 15729#L1328-1 assume !(0 == ~E_2~0); 15896#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 16855#L1338-1 assume !(0 == ~E_4~0); 16856#L1343-1 assume !(0 == ~E_5~0); 16957#L1348-1 assume !(0 == ~E_6~0); 17243#L1353-1 assume !(0 == ~E_7~0); 16582#L1358-1 assume !(0 == ~E_8~0); 16583#L1363-1 assume !(0 == ~E_9~0); 16873#L1368-1 assume !(0 == ~E_10~0); 15558#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 15559#L1378-1 assume !(0 == ~E_12~0); 15845#L1383-1 assume !(0 == ~E_13~0); 15846#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16589#L607 assume 1 == ~m_pc~0; 16590#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 15916#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16955#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 16509#L1560 assume !(0 != activate_threads_~tmp~1#1); 16510#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15741#L626 assume !(1 == ~t1_pc~0); 15742#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 16010#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16011#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 16180#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 15641#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15642#L645 assume 1 == ~t2_pc~0; 15758#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 15715#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16392#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 16393#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 16485#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16486#L664 assume 1 == ~t3_pc~0; 17242#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 15482#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15483#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 16141#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 16142#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 17150#L683 assume !(1 == ~t4_pc~0); 16705#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 16657#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 16658#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 16692#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 16816#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16435#L702 assume 1 == ~t5_pc~0; 16436#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 16361#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 16811#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 17109#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 17050#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 15530#L721 assume !(1 == ~t6_pc~0); 15504#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 15505#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 15668#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 16150#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 16151#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 16752#L740 assume 1 == ~t7_pc~0; 15579#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 15392#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 15393#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 15382#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 15383#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 16086#L759 assume !(1 == ~t8_pc~0); 16087#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 16116#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 16809#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 16810#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 16941#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 17219#L778 assume 1 == ~t9_pc~0; 17106#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 15557#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 15497#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 15426#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 15427#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 15754#L797 assume !(1 == ~t10_pc~0); 15755#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 15873#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 17007#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 16257#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 16258#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 16547#L816 assume 1 == ~t11_pc~0; 15462#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 15463#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 16218#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 16157#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 16158#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 16682#L835 assume 1 == ~t12_pc~0; 16560#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 15626#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 15648#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 15789#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 16314#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 16315#L854 assume !(1 == ~t13_pc~0); 15955#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 15956#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 16006#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 15666#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 15667#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17046#L1401 assume !(1 == ~M_E~0); 16145#L1401-2 assume !(1 == ~T1_E~0); 16146#L1406-1 assume !(1 == ~T2_E~0); 16741#L1411-1 assume !(1 == ~T3_E~0); 16742#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 16408#L1421-1 assume !(1 == ~T5_E~0); 15951#L1426-1 assume !(1 == ~T6_E~0); 15952#L1431-1 assume !(1 == ~T7_E~0); 15500#L1436-1 assume !(1 == ~T8_E~0); 15501#L1441-1 assume !(1 == ~T9_E~0); 16248#L1446-1 assume !(1 == ~T10_E~0); 16249#L1451-1 assume !(1 == ~T11_E~0); 16954#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 16608#L1461-1 assume !(1 == ~T13_E~0); 16169#L1466-1 assume !(1 == ~E_1~0); 16170#L1471-1 assume !(1 == ~E_2~0); 16939#L1476-1 assume !(1 == ~E_3~0); 16940#L1481-1 assume !(1 == ~E_4~0); 17088#L1486-1 assume !(1 == ~E_5~0); 15794#L1491-1 assume !(1 == ~E_6~0); 15434#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 15435#L1501-1 assume !(1 == ~E_8~0); 16246#L1506-1 assume !(1 == ~E_9~0); 16247#L1511-1 assume !(1 == ~E_10~0); 16203#L1516-1 assume !(1 == ~E_11~0); 15378#L1521-1 assume !(1 == ~E_12~0); 15379#L1526-1 assume !(1 == ~E_13~0); 15433#L1531-1 assume { :end_inline_reset_delta_events } true; 15976#L1892-2 [2021-12-15 17:21:48,026 INFO L793 eck$LassoCheckResult]: Loop: 15976#L1892-2 assume !false; 16999#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 17197#L1233 assume !false; 17180#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 16512#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 16492#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 16650#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 15476#L1046 assume !(0 != eval_~tmp~0#1); 15478#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 15512#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 16684#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 17241#L1258-5 assume !(0 == ~T1_E~0); 15654#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 15655#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 17233#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 17239#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 17240#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 15878#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 15879#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 16996#L1298-3 assume !(0 == ~T9_E~0); 16997#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 17156#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 16995#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 16496#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 15656#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 15657#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 17080#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 15799#L1338-3 assume !(0 == ~E_4~0); 15800#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 16912#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 17085#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 17086#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 16452#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 16012#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 16013#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 16769#L1378-3 assume !(0 == ~E_12~0); 16770#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 16951#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16952#L607-42 assume 1 == ~m_pc~0; 16565#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 16293#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16294#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 16026#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 16027#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16548#L626-42 assume !(1 == ~t1_pc~0); 16112#L626-44 is_transmit1_triggered_~__retres1~1#1 := 0; 16111#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16415#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 16416#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 15690#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15691#L645-42 assume !(1 == ~t2_pc~0); 16890#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 16891#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17056#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 15897#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 15404#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15405#L664-42 assume !(1 == ~t3_pc~0); 15931#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 15932#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 17183#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 16718#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 16719#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16884#L683-42 assume !(1 == ~t4_pc~0); 16592#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 16593#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 16725#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 17145#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 17146#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16990#L702-42 assume !(1 == ~t5_pc~0); 16102#L702-44 is_transmit5_triggered_~__retres1~5#1 := 0; 16103#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 16399#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 17072#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 15420#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 15421#L721-42 assume 1 == ~t6_pc~0; 15574#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 15594#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 16058#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 17225#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 16230#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 16076#L740-42 assume !(1 == ~t7_pc~0); 15813#L740-44 is_transmit7_triggered_~__retres1~7#1 := 0; 15814#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16355#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 16210#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 16211#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 16484#L759-42 assume 1 == ~t8_pc~0; 16333#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 16265#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 16266#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 16344#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 16345#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 16440#L778-42 assume 1 == ~t9_pc~0; 16277#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 16279#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 16689#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 16594#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 16595#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 16652#L797-42 assume 1 == ~t10_pc~0; 15819#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 15820#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 16821#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 17130#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 16690#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 16691#L816-42 assume 1 == ~t11_pc~0; 15368#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 15369#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 15911#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 15912#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 15991#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 15992#L835-42 assume !(1 == ~t12_pc~0); 16288#L835-44 is_transmit12_triggered_~__retres1~12#1 := 0; 16289#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 15966#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 15967#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 17049#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 16833#L854-42 assume 1 == ~t13_pc~0; 16834#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 15910#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 15520#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 15521#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 16167#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16168#L1401-3 assume !(1 == ~M_E~0); 16946#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 15757#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 15621#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 15622#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 16221#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 16222#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 15797#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 15798#L1436-3 assume !(1 == ~T8_E~0); 15384#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 15385#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 16974#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 16305#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 15958#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 15959#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 17236#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 15898#L1476-3 assume !(1 == ~E_3~0); 15899#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 16299#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 15926#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 15927#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 16339#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 16340#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 16766#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 16756#L1516-3 assume !(1 == ~E_11~0); 16757#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 16456#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 16457#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 16851#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 15733#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 16626#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 16267#L1911 assume !(0 == start_simulation_~tmp~3#1); 16268#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 16790#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 15858#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 16728#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 15562#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 15563#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 15792#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 15793#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 15976#L1892-2 [2021-12-15 17:21:48,026 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:48,026 INFO L85 PathProgramCache]: Analyzing trace with hash 1797695072, now seen corresponding path program 1 times [2021-12-15 17:21:48,027 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:48,027 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1081291969] [2021-12-15 17:21:48,027 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:48,027 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:48,036 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:48,057 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:48,058 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:48,058 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1081291969] [2021-12-15 17:21:48,058 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1081291969] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:48,058 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:48,058 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:48,058 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [808891019] [2021-12-15 17:21:48,059 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:48,059 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:21:48,059 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:48,059 INFO L85 PathProgramCache]: Analyzing trace with hash -1106627154, now seen corresponding path program 1 times [2021-12-15 17:21:48,059 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:48,060 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1676192549] [2021-12-15 17:21:48,060 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:48,060 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:48,071 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:48,096 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:48,097 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:48,097 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1676192549] [2021-12-15 17:21:48,097 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1676192549] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:48,097 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:48,097 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:48,097 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [786409225] [2021-12-15 17:21:48,097 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:48,097 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:21:48,098 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:21:48,098 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:21:48,098 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:21:48,098 INFO L87 Difference]: Start difference. First operand 1914 states and 2832 transitions. cyclomatic complexity: 919 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:48,120 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:21:48,120 INFO L93 Difference]: Finished difference Result 1914 states and 2831 transitions. [2021-12-15 17:21:48,121 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:21:48,123 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1914 states and 2831 transitions. [2021-12-15 17:21:48,130 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2021-12-15 17:21:48,136 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1914 states to 1914 states and 2831 transitions. [2021-12-15 17:21:48,136 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1914 [2021-12-15 17:21:48,137 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1914 [2021-12-15 17:21:48,137 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1914 states and 2831 transitions. [2021-12-15 17:21:48,139 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:21:48,139 INFO L681 BuchiCegarLoop]: Abstraction has 1914 states and 2831 transitions. [2021-12-15 17:21:48,140 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1914 states and 2831 transitions. [2021-12-15 17:21:48,157 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1914 to 1914. [2021-12-15 17:21:48,160 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1914 states, 1914 states have (on average 1.4791013584117032) internal successors, (2831), 1913 states have internal predecessors, (2831), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:48,164 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1914 states to 1914 states and 2831 transitions. [2021-12-15 17:21:48,164 INFO L704 BuchiCegarLoop]: Abstraction has 1914 states and 2831 transitions. [2021-12-15 17:21:48,164 INFO L587 BuchiCegarLoop]: Abstraction has 1914 states and 2831 transitions. [2021-12-15 17:21:48,164 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2021-12-15 17:21:48,164 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1914 states and 2831 transitions. [2021-12-15 17:21:48,171 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2021-12-15 17:21:48,171 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:21:48,171 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:21:48,173 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:48,173 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:48,173 INFO L791 eck$LassoCheckResult]: Stem: 20049#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 20050#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 19869#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 19585#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 19586#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 20762#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 20763#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 19721#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 19722#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 20176#L901-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 20011#L906-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 20012#L911-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 19788#L916-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 19789#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 20187#L926-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 20364#L931-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 20518#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 20555#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 19799#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 19800#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 20975#L1258-2 assume !(0 == ~T1_E~0); 20094#L1263-1 assume !(0 == ~T2_E~0); 20095#L1268-1 assume !(0 == ~T3_E~0); 20398#L1273-1 assume !(0 == ~T4_E~0); 20957#L1278-1 assume !(0 == ~T5_E~0); 20818#L1283-1 assume !(0 == ~T6_E~0); 20819#L1288-1 assume !(0 == ~T7_E~0); 21055#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 21043#L1298-1 assume !(0 == ~T9_E~0); 20969#L1303-1 assume !(0 == ~T10_E~0); 19614#L1308-1 assume !(0 == ~T11_E~0); 19556#L1313-1 assume !(0 == ~T12_E~0); 19557#L1318-1 assume !(0 == ~T13_E~0); 19563#L1323-1 assume !(0 == ~E_1~0); 19564#L1328-1 assume !(0 == ~E_2~0); 19731#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 20690#L1338-1 assume !(0 == ~E_4~0); 20691#L1343-1 assume !(0 == ~E_5~0); 20792#L1348-1 assume !(0 == ~E_6~0); 21078#L1353-1 assume !(0 == ~E_7~0); 20417#L1358-1 assume !(0 == ~E_8~0); 20418#L1363-1 assume !(0 == ~E_9~0); 20708#L1368-1 assume !(0 == ~E_10~0); 19393#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 19394#L1378-1 assume !(0 == ~E_12~0); 19680#L1383-1 assume !(0 == ~E_13~0); 19681#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20424#L607 assume 1 == ~m_pc~0; 20425#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 19751#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 20790#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 20344#L1560 assume !(0 != activate_threads_~tmp~1#1); 20345#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19576#L626 assume !(1 == ~t1_pc~0); 19577#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 19845#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19846#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 20015#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 19476#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 19477#L645 assume 1 == ~t2_pc~0; 19593#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 19550#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20227#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 20228#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 20320#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 20321#L664 assume 1 == ~t3_pc~0; 21077#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 19317#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19318#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 19976#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 19977#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 20985#L683 assume !(1 == ~t4_pc~0); 20540#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 20492#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 20493#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 20527#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 20651#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 20270#L702 assume 1 == ~t5_pc~0; 20271#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 20196#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 20646#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 20944#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 20885#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19365#L721 assume !(1 == ~t6_pc~0); 19339#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 19340#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19503#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 19985#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 19986#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 20587#L740 assume 1 == ~t7_pc~0; 19414#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 19227#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19228#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 19217#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 19218#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 19921#L759 assume !(1 == ~t8_pc~0); 19922#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 19951#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 20644#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 20645#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 20776#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 21054#L778 assume 1 == ~t9_pc~0; 20941#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 19392#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 19332#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 19261#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 19262#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 19589#L797 assume !(1 == ~t10_pc~0); 19590#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 19708#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 20842#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 20092#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 20093#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 20382#L816 assume 1 == ~t11_pc~0; 19297#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 19298#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 20053#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 19992#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 19993#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 20517#L835 assume 1 == ~t12_pc~0; 20395#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 19461#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 19483#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 19624#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 20149#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 20150#L854 assume !(1 == ~t13_pc~0); 19790#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 19791#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 19841#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 19501#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 19502#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 20881#L1401 assume !(1 == ~M_E~0); 19980#L1401-2 assume !(1 == ~T1_E~0); 19981#L1406-1 assume !(1 == ~T2_E~0); 20576#L1411-1 assume !(1 == ~T3_E~0); 20577#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 20243#L1421-1 assume !(1 == ~T5_E~0); 19786#L1426-1 assume !(1 == ~T6_E~0); 19787#L1431-1 assume !(1 == ~T7_E~0); 19335#L1436-1 assume !(1 == ~T8_E~0); 19336#L1441-1 assume !(1 == ~T9_E~0); 20083#L1446-1 assume !(1 == ~T10_E~0); 20084#L1451-1 assume !(1 == ~T11_E~0); 20789#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 20443#L1461-1 assume !(1 == ~T13_E~0); 20004#L1466-1 assume !(1 == ~E_1~0); 20005#L1471-1 assume !(1 == ~E_2~0); 20774#L1476-1 assume !(1 == ~E_3~0); 20775#L1481-1 assume !(1 == ~E_4~0); 20923#L1486-1 assume !(1 == ~E_5~0); 19629#L1491-1 assume !(1 == ~E_6~0); 19269#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 19270#L1501-1 assume !(1 == ~E_8~0); 20081#L1506-1 assume !(1 == ~E_9~0); 20082#L1511-1 assume !(1 == ~E_10~0); 20038#L1516-1 assume !(1 == ~E_11~0); 19213#L1521-1 assume !(1 == ~E_12~0); 19214#L1526-1 assume !(1 == ~E_13~0); 19268#L1531-1 assume { :end_inline_reset_delta_events } true; 19811#L1892-2 [2021-12-15 17:21:48,173 INFO L793 eck$LassoCheckResult]: Loop: 19811#L1892-2 assume !false; 20834#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 21032#L1233 assume !false; 21015#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 20347#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 20327#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 20485#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 19311#L1046 assume !(0 != eval_~tmp~0#1); 19313#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 19347#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 20519#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 21076#L1258-5 assume !(0 == ~T1_E~0); 19489#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 19490#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 21068#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 21074#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 21075#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 19713#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 19714#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 20831#L1298-3 assume !(0 == ~T9_E~0); 20832#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 20991#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 20830#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 20331#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 19491#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 19492#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 20915#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 19634#L1338-3 assume !(0 == ~E_4~0); 19635#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 20747#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 20920#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 20921#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 20287#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 19847#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 19848#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 20604#L1378-3 assume !(0 == ~E_12~0); 20605#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 20786#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20787#L607-42 assume 1 == ~m_pc~0; 20400#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 20128#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 20129#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 19861#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 19862#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 20383#L626-42 assume 1 == ~t1_pc~0; 19945#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 19946#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 20250#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 20251#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 19525#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 19526#L645-42 assume !(1 == ~t2_pc~0); 20725#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 20726#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20891#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 19732#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 19239#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19240#L664-42 assume !(1 == ~t3_pc~0); 19766#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 19767#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 21018#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 20553#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 20554#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 20719#L683-42 assume !(1 == ~t4_pc~0); 20427#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 20428#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 20560#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 20980#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 20981#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 20825#L702-42 assume !(1 == ~t5_pc~0); 19937#L702-44 is_transmit5_triggered_~__retres1~5#1 := 0; 19938#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 20234#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 20907#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 19255#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19256#L721-42 assume 1 == ~t6_pc~0; 19409#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 19429#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19893#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 21060#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 20065#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 19911#L740-42 assume !(1 == ~t7_pc~0); 19648#L740-44 is_transmit7_triggered_~__retres1~7#1 := 0; 19649#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 20190#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 20045#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 20046#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 20319#L759-42 assume 1 == ~t8_pc~0; 20168#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 20100#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 20101#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 20179#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 20180#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 20275#L778-42 assume 1 == ~t9_pc~0; 20112#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 20114#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 20524#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 20429#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 20430#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 20487#L797-42 assume 1 == ~t10_pc~0; 19654#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 19655#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 20656#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 20965#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 20525#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 20526#L816-42 assume 1 == ~t11_pc~0; 19203#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 19204#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 19746#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 19747#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 19826#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 19827#L835-42 assume 1 == ~t12_pc~0; 20231#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 20124#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 19801#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 19802#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 20884#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 20668#L854-42 assume !(1 == ~t13_pc~0); 19744#L854-44 is_transmit13_triggered_~__retres1~13#1 := 0; 19745#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 19355#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 19356#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 20002#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 20003#L1401-3 assume !(1 == ~M_E~0); 20781#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 19592#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 19456#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 19457#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 20056#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 20057#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 19632#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 19633#L1436-3 assume !(1 == ~T8_E~0); 19219#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 19220#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 20809#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 20140#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 19793#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 19794#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 21071#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 19733#L1476-3 assume !(1 == ~E_3~0); 19734#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 20134#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 19761#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 19762#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 20174#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 20175#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 20601#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 20591#L1516-3 assume !(1 == ~E_11~0); 20592#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 20291#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 20292#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 20686#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 19568#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 20461#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 20102#L1911 assume !(0 == start_simulation_~tmp~3#1); 20103#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 20625#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 19693#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 20563#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 19397#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 19398#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 19627#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 19628#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 19811#L1892-2 [2021-12-15 17:21:48,177 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:48,177 INFO L85 PathProgramCache]: Analyzing trace with hash 351114206, now seen corresponding path program 1 times [2021-12-15 17:21:48,177 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:48,178 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [864422085] [2021-12-15 17:21:48,178 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:48,178 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:48,188 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:48,203 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:48,204 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:48,204 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [864422085] [2021-12-15 17:21:48,204 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [864422085] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:48,204 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:48,204 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:48,205 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [223407885] [2021-12-15 17:21:48,205 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:48,206 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:21:48,206 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:48,208 INFO L85 PathProgramCache]: Analyzing trace with hash -835808881, now seen corresponding path program 1 times [2021-12-15 17:21:48,208 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:48,211 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1805400400] [2021-12-15 17:21:48,211 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:48,212 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:48,229 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:48,272 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:48,272 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:48,272 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1805400400] [2021-12-15 17:21:48,272 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1805400400] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:48,272 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:48,272 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:48,273 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [467908758] [2021-12-15 17:21:48,273 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:48,273 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:21:48,273 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:21:48,273 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:21:48,273 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:21:48,274 INFO L87 Difference]: Start difference. First operand 1914 states and 2831 transitions. cyclomatic complexity: 918 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:48,323 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:21:48,323 INFO L93 Difference]: Finished difference Result 1914 states and 2830 transitions. [2021-12-15 17:21:48,323 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:21:48,324 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1914 states and 2830 transitions. [2021-12-15 17:21:48,331 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2021-12-15 17:21:48,337 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1914 states to 1914 states and 2830 transitions. [2021-12-15 17:21:48,337 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1914 [2021-12-15 17:21:48,338 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1914 [2021-12-15 17:21:48,338 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1914 states and 2830 transitions. [2021-12-15 17:21:48,340 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:21:48,340 INFO L681 BuchiCegarLoop]: Abstraction has 1914 states and 2830 transitions. [2021-12-15 17:21:48,342 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1914 states and 2830 transitions. [2021-12-15 17:21:48,360 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1914 to 1914. [2021-12-15 17:21:48,363 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1914 states, 1914 states have (on average 1.4785788923719958) internal successors, (2830), 1913 states have internal predecessors, (2830), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:48,367 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1914 states to 1914 states and 2830 transitions. [2021-12-15 17:21:48,367 INFO L704 BuchiCegarLoop]: Abstraction has 1914 states and 2830 transitions. [2021-12-15 17:21:48,367 INFO L587 BuchiCegarLoop]: Abstraction has 1914 states and 2830 transitions. [2021-12-15 17:21:48,367 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2021-12-15 17:21:48,367 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1914 states and 2830 transitions. [2021-12-15 17:21:48,372 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2021-12-15 17:21:48,372 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:21:48,372 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:21:48,373 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:48,373 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:48,374 INFO L791 eck$LassoCheckResult]: Stem: 23884#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 23885#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 23704#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 23420#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 23421#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 24597#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 24598#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 23556#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 23557#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 24011#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 23846#L906-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 23847#L911-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 23623#L916-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 23624#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 24022#L926-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 24199#L931-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 24353#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 24390#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 23634#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 23635#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 24810#L1258-2 assume !(0 == ~T1_E~0); 23929#L1263-1 assume !(0 == ~T2_E~0); 23930#L1268-1 assume !(0 == ~T3_E~0); 24233#L1273-1 assume !(0 == ~T4_E~0); 24792#L1278-1 assume !(0 == ~T5_E~0); 24653#L1283-1 assume !(0 == ~T6_E~0); 24654#L1288-1 assume !(0 == ~T7_E~0); 24890#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 24878#L1298-1 assume !(0 == ~T9_E~0); 24804#L1303-1 assume !(0 == ~T10_E~0); 23449#L1308-1 assume !(0 == ~T11_E~0); 23391#L1313-1 assume !(0 == ~T12_E~0); 23392#L1318-1 assume !(0 == ~T13_E~0); 23398#L1323-1 assume !(0 == ~E_1~0); 23399#L1328-1 assume !(0 == ~E_2~0); 23566#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 24525#L1338-1 assume !(0 == ~E_4~0); 24526#L1343-1 assume !(0 == ~E_5~0); 24627#L1348-1 assume !(0 == ~E_6~0); 24913#L1353-1 assume !(0 == ~E_7~0); 24252#L1358-1 assume !(0 == ~E_8~0); 24253#L1363-1 assume !(0 == ~E_9~0); 24543#L1368-1 assume !(0 == ~E_10~0); 23228#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 23229#L1378-1 assume !(0 == ~E_12~0); 23515#L1383-1 assume !(0 == ~E_13~0); 23516#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 24259#L607 assume 1 == ~m_pc~0; 24260#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 23586#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 24625#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 24179#L1560 assume !(0 != activate_threads_~tmp~1#1); 24180#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 23411#L626 assume !(1 == ~t1_pc~0); 23412#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 23680#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 23681#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 23850#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 23311#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 23312#L645 assume 1 == ~t2_pc~0; 23428#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 23385#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 24062#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 24063#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 24155#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 24156#L664 assume 1 == ~t3_pc~0; 24912#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 23152#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 23153#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 23811#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 23812#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 24820#L683 assume !(1 == ~t4_pc~0); 24375#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 24327#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 24328#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 24362#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 24486#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 24105#L702 assume 1 == ~t5_pc~0; 24106#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 24031#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 24481#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 24779#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 24720#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 23200#L721 assume !(1 == ~t6_pc~0); 23174#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 23175#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 23338#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 23820#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 23821#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 24422#L740 assume 1 == ~t7_pc~0; 23249#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 23062#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 23063#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 23052#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 23053#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 23756#L759 assume !(1 == ~t8_pc~0); 23757#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 23786#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 24479#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 24480#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 24611#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 24889#L778 assume 1 == ~t9_pc~0; 24776#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 23227#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 23167#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 23096#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 23097#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 23424#L797 assume !(1 == ~t10_pc~0); 23425#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 23543#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 24677#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 23927#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 23928#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 24217#L816 assume 1 == ~t11_pc~0; 23132#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 23133#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 23888#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 23827#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 23828#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 24352#L835 assume 1 == ~t12_pc~0; 24230#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 23296#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 23318#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 23459#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 23984#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 23985#L854 assume !(1 == ~t13_pc~0); 23625#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 23626#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 23676#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 23336#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 23337#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 24716#L1401 assume !(1 == ~M_E~0); 23815#L1401-2 assume !(1 == ~T1_E~0); 23816#L1406-1 assume !(1 == ~T2_E~0); 24411#L1411-1 assume !(1 == ~T3_E~0); 24412#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 24078#L1421-1 assume !(1 == ~T5_E~0); 23621#L1426-1 assume !(1 == ~T6_E~0); 23622#L1431-1 assume !(1 == ~T7_E~0); 23170#L1436-1 assume !(1 == ~T8_E~0); 23171#L1441-1 assume !(1 == ~T9_E~0); 23918#L1446-1 assume !(1 == ~T10_E~0); 23919#L1451-1 assume !(1 == ~T11_E~0); 24624#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 24278#L1461-1 assume !(1 == ~T13_E~0); 23839#L1466-1 assume !(1 == ~E_1~0); 23840#L1471-1 assume !(1 == ~E_2~0); 24609#L1476-1 assume !(1 == ~E_3~0); 24610#L1481-1 assume !(1 == ~E_4~0); 24758#L1486-1 assume !(1 == ~E_5~0); 23464#L1491-1 assume !(1 == ~E_6~0); 23104#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 23105#L1501-1 assume !(1 == ~E_8~0); 23916#L1506-1 assume !(1 == ~E_9~0); 23917#L1511-1 assume !(1 == ~E_10~0); 23873#L1516-1 assume !(1 == ~E_11~0); 23048#L1521-1 assume !(1 == ~E_12~0); 23049#L1526-1 assume !(1 == ~E_13~0); 23103#L1531-1 assume { :end_inline_reset_delta_events } true; 23646#L1892-2 [2021-12-15 17:21:48,374 INFO L793 eck$LassoCheckResult]: Loop: 23646#L1892-2 assume !false; 24669#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 24867#L1233 assume !false; 24850#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 24182#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 24162#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 24320#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 23146#L1046 assume !(0 != eval_~tmp~0#1); 23148#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 23182#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 24354#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 24911#L1258-5 assume !(0 == ~T1_E~0); 23324#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 23325#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 24903#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 24909#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 24910#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 23548#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 23549#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 24666#L1298-3 assume !(0 == ~T9_E~0); 24667#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 24826#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 24665#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 24166#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 23326#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 23327#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 24750#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 23469#L1338-3 assume !(0 == ~E_4~0); 23470#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 24582#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 24755#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 24756#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 24122#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 23682#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 23683#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 24439#L1378-3 assume !(0 == ~E_12~0); 24440#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 24621#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 24622#L607-42 assume 1 == ~m_pc~0; 24235#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 23963#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 23964#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 23696#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 23697#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 24218#L626-42 assume 1 == ~t1_pc~0; 23780#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 23781#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 24085#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 24086#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 23360#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 23361#L645-42 assume !(1 == ~t2_pc~0); 24560#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 24561#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 24726#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 23567#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 23074#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 23075#L664-42 assume !(1 == ~t3_pc~0); 23601#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 23602#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 24853#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 24388#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 24389#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 24554#L683-42 assume !(1 == ~t4_pc~0); 24262#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 24263#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 24395#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 24815#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 24816#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 24660#L702-42 assume 1 == ~t5_pc~0; 24148#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 23773#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 24069#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 24742#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 23090#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 23091#L721-42 assume 1 == ~t6_pc~0; 23244#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 23264#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 23728#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 24895#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 23900#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 23746#L740-42 assume 1 == ~t7_pc~0; 23747#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 23484#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 24025#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 23880#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 23881#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 24154#L759-42 assume 1 == ~t8_pc~0; 24003#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 23935#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 23936#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 24014#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 24015#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 24110#L778-42 assume 1 == ~t9_pc~0; 23947#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 23949#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 24359#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 24264#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 24265#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 24322#L797-42 assume 1 == ~t10_pc~0; 23489#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 23490#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 24491#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 24800#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 24360#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 24361#L816-42 assume !(1 == ~t11_pc~0); 23040#L816-44 is_transmit11_triggered_~__retres1~11#1 := 0; 23039#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 23581#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 23582#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 23661#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 23662#L835-42 assume 1 == ~t12_pc~0; 24066#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 23959#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 23636#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 23637#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 24719#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 24503#L854-42 assume 1 == ~t13_pc~0; 24504#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 23580#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 23190#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 23191#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 23837#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 23838#L1401-3 assume !(1 == ~M_E~0); 24616#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 23427#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 23291#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 23292#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 23891#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 23892#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 23467#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 23468#L1436-3 assume !(1 == ~T8_E~0); 23054#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 23055#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 24644#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 23975#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 23628#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 23629#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 24906#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 23568#L1476-3 assume !(1 == ~E_3~0); 23569#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 23969#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 23596#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 23597#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 24009#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 24010#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 24436#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 24426#L1516-3 assume !(1 == ~E_11~0); 24427#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 24126#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 24127#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 24521#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 23403#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 24296#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 23937#L1911 assume !(0 == start_simulation_~tmp~3#1); 23938#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 24460#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 23528#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 24398#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 23232#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 23233#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 23462#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 23463#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 23646#L1892-2 [2021-12-15 17:21:48,374 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:48,375 INFO L85 PathProgramCache]: Analyzing trace with hash 1274281632, now seen corresponding path program 1 times [2021-12-15 17:21:48,375 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:48,375 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [602201611] [2021-12-15 17:21:48,375 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:48,375 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:48,384 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:48,401 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:48,401 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:48,401 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [602201611] [2021-12-15 17:21:48,401 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [602201611] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:48,401 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:48,401 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:48,402 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1970079731] [2021-12-15 17:21:48,402 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:48,402 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:21:48,402 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:48,402 INFO L85 PathProgramCache]: Analyzing trace with hash 1042381777, now seen corresponding path program 1 times [2021-12-15 17:21:48,403 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:48,403 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1037956752] [2021-12-15 17:21:48,403 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:48,403 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:48,413 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:48,447 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:48,447 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:48,447 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1037956752] [2021-12-15 17:21:48,447 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1037956752] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:48,447 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:48,447 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:48,448 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1729909710] [2021-12-15 17:21:48,448 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:48,448 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:21:48,448 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:21:48,448 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:21:48,448 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:21:48,449 INFO L87 Difference]: Start difference. First operand 1914 states and 2830 transitions. cyclomatic complexity: 917 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:48,471 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:21:48,472 INFO L93 Difference]: Finished difference Result 1914 states and 2829 transitions. [2021-12-15 17:21:48,472 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:21:48,473 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1914 states and 2829 transitions. [2021-12-15 17:21:48,480 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2021-12-15 17:21:48,486 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1914 states to 1914 states and 2829 transitions. [2021-12-15 17:21:48,487 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1914 [2021-12-15 17:21:48,488 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1914 [2021-12-15 17:21:48,488 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1914 states and 2829 transitions. [2021-12-15 17:21:48,490 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:21:48,490 INFO L681 BuchiCegarLoop]: Abstraction has 1914 states and 2829 transitions. [2021-12-15 17:21:48,492 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1914 states and 2829 transitions. [2021-12-15 17:21:48,509 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1914 to 1914. [2021-12-15 17:21:48,511 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1914 states, 1914 states have (on average 1.4780564263322884) internal successors, (2829), 1913 states have internal predecessors, (2829), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:48,515 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1914 states to 1914 states and 2829 transitions. [2021-12-15 17:21:48,515 INFO L704 BuchiCegarLoop]: Abstraction has 1914 states and 2829 transitions. [2021-12-15 17:21:48,515 INFO L587 BuchiCegarLoop]: Abstraction has 1914 states and 2829 transitions. [2021-12-15 17:21:48,515 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2021-12-15 17:21:48,516 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1914 states and 2829 transitions. [2021-12-15 17:21:48,520 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2021-12-15 17:21:48,520 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:21:48,520 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:21:48,522 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:48,522 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:48,522 INFO L791 eck$LassoCheckResult]: Stem: 27719#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 27720#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 27539#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 27255#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 27256#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 28432#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 28433#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 27391#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 27392#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 27846#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 27681#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 27682#L911-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 27458#L916-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 27459#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 27857#L926-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 28034#L931-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 28188#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 28225#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 27469#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 27470#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 28645#L1258-2 assume !(0 == ~T1_E~0); 27764#L1263-1 assume !(0 == ~T2_E~0); 27765#L1268-1 assume !(0 == ~T3_E~0); 28068#L1273-1 assume !(0 == ~T4_E~0); 28627#L1278-1 assume !(0 == ~T5_E~0); 28488#L1283-1 assume !(0 == ~T6_E~0); 28489#L1288-1 assume !(0 == ~T7_E~0); 28725#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 28713#L1298-1 assume !(0 == ~T9_E~0); 28639#L1303-1 assume !(0 == ~T10_E~0); 27284#L1308-1 assume !(0 == ~T11_E~0); 27226#L1313-1 assume !(0 == ~T12_E~0); 27227#L1318-1 assume !(0 == ~T13_E~0); 27233#L1323-1 assume !(0 == ~E_1~0); 27234#L1328-1 assume !(0 == ~E_2~0); 27401#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 28360#L1338-1 assume !(0 == ~E_4~0); 28361#L1343-1 assume !(0 == ~E_5~0); 28462#L1348-1 assume !(0 == ~E_6~0); 28748#L1353-1 assume !(0 == ~E_7~0); 28087#L1358-1 assume !(0 == ~E_8~0); 28088#L1363-1 assume !(0 == ~E_9~0); 28378#L1368-1 assume !(0 == ~E_10~0); 27063#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 27064#L1378-1 assume !(0 == ~E_12~0); 27350#L1383-1 assume !(0 == ~E_13~0); 27351#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 28094#L607 assume 1 == ~m_pc~0; 28095#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 27421#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 28460#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 28014#L1560 assume !(0 != activate_threads_~tmp~1#1); 28015#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 27246#L626 assume !(1 == ~t1_pc~0); 27247#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 27515#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 27516#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 27685#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 27146#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 27147#L645 assume 1 == ~t2_pc~0; 27263#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 27220#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 27897#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 27898#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 27990#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 27991#L664 assume 1 == ~t3_pc~0; 28747#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 26987#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 26988#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 27646#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 27647#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 28655#L683 assume !(1 == ~t4_pc~0); 28210#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 28162#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 28163#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 28197#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 28321#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 27940#L702 assume 1 == ~t5_pc~0; 27941#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 27866#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 28316#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 28614#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 28555#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 27035#L721 assume !(1 == ~t6_pc~0); 27009#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 27010#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 27173#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 27655#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 27656#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 28257#L740 assume 1 == ~t7_pc~0; 27084#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 26897#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 26898#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 26887#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 26888#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 27591#L759 assume !(1 == ~t8_pc~0); 27592#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 27621#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 28314#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 28315#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 28446#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 28724#L778 assume 1 == ~t9_pc~0; 28611#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 27062#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 27002#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 26931#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 26932#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 27259#L797 assume !(1 == ~t10_pc~0); 27260#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 27378#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 28512#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 27762#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 27763#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 28052#L816 assume 1 == ~t11_pc~0; 26967#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 26968#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 27723#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 27662#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 27663#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 28187#L835 assume 1 == ~t12_pc~0; 28065#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 27131#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 27153#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 27294#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 27819#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 27820#L854 assume !(1 == ~t13_pc~0); 27460#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 27461#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 27511#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 27171#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 27172#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 28551#L1401 assume !(1 == ~M_E~0); 27650#L1401-2 assume !(1 == ~T1_E~0); 27651#L1406-1 assume !(1 == ~T2_E~0); 28246#L1411-1 assume !(1 == ~T3_E~0); 28247#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 27913#L1421-1 assume !(1 == ~T5_E~0); 27456#L1426-1 assume !(1 == ~T6_E~0); 27457#L1431-1 assume !(1 == ~T7_E~0); 27005#L1436-1 assume !(1 == ~T8_E~0); 27006#L1441-1 assume !(1 == ~T9_E~0); 27753#L1446-1 assume !(1 == ~T10_E~0); 27754#L1451-1 assume !(1 == ~T11_E~0); 28459#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 28113#L1461-1 assume !(1 == ~T13_E~0); 27674#L1466-1 assume !(1 == ~E_1~0); 27675#L1471-1 assume !(1 == ~E_2~0); 28444#L1476-1 assume !(1 == ~E_3~0); 28445#L1481-1 assume !(1 == ~E_4~0); 28593#L1486-1 assume !(1 == ~E_5~0); 27299#L1491-1 assume !(1 == ~E_6~0); 26939#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 26940#L1501-1 assume !(1 == ~E_8~0); 27751#L1506-1 assume !(1 == ~E_9~0); 27752#L1511-1 assume !(1 == ~E_10~0); 27708#L1516-1 assume !(1 == ~E_11~0); 26883#L1521-1 assume !(1 == ~E_12~0); 26884#L1526-1 assume !(1 == ~E_13~0); 26938#L1531-1 assume { :end_inline_reset_delta_events } true; 27481#L1892-2 [2021-12-15 17:21:48,523 INFO L793 eck$LassoCheckResult]: Loop: 27481#L1892-2 assume !false; 28504#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 28702#L1233 assume !false; 28685#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 28017#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 27997#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 28155#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 26981#L1046 assume !(0 != eval_~tmp~0#1); 26983#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 27017#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 28189#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 28746#L1258-5 assume !(0 == ~T1_E~0); 27159#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 27160#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 28738#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 28744#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 28745#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 27383#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 27384#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 28501#L1298-3 assume !(0 == ~T9_E~0); 28502#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 28661#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 28500#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 28001#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 27161#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 27162#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 28585#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 27304#L1338-3 assume !(0 == ~E_4~0); 27305#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 28417#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 28590#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 28591#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 27957#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 27517#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 27518#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 28274#L1378-3 assume !(0 == ~E_12~0); 28275#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 28456#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 28457#L607-42 assume 1 == ~m_pc~0; 28070#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 27798#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 27799#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 27531#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 27532#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 28053#L626-42 assume !(1 == ~t1_pc~0); 27617#L626-44 is_transmit1_triggered_~__retres1~1#1 := 0; 27616#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 27920#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 27921#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 27195#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 27196#L645-42 assume !(1 == ~t2_pc~0); 28395#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 28396#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 28561#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 27402#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 26909#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 26910#L664-42 assume 1 == ~t3_pc~0; 27712#L665-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 27437#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 28688#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 28223#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 28224#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 28389#L683-42 assume !(1 == ~t4_pc~0); 28097#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 28098#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 28230#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 28650#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 28651#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 28495#L702-42 assume !(1 == ~t5_pc~0); 27607#L702-44 is_transmit5_triggered_~__retres1~5#1 := 0; 27608#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 27904#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 28577#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 26925#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 26926#L721-42 assume 1 == ~t6_pc~0; 27079#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 27099#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 27563#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 28730#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 27735#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 27581#L740-42 assume !(1 == ~t7_pc~0); 27318#L740-44 is_transmit7_triggered_~__retres1~7#1 := 0; 27319#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 27860#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 27715#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 27716#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 27989#L759-42 assume 1 == ~t8_pc~0; 27838#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 27770#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 27771#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 27849#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 27850#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 27945#L778-42 assume 1 == ~t9_pc~0; 27782#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 27784#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 28194#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 28099#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 28100#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 28157#L797-42 assume 1 == ~t10_pc~0; 27324#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 27325#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 28326#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 28635#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 28195#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 28196#L816-42 assume 1 == ~t11_pc~0; 26873#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 26874#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 27416#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 27417#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 27496#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 27497#L835-42 assume !(1 == ~t12_pc~0); 27793#L835-44 is_transmit12_triggered_~__retres1~12#1 := 0; 27794#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 27471#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 27472#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 28554#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 28338#L854-42 assume 1 == ~t13_pc~0; 28339#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 27415#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 27025#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 27026#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 27672#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 27673#L1401-3 assume !(1 == ~M_E~0); 28451#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 27262#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 27126#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 27127#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 27726#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 27727#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 27302#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 27303#L1436-3 assume !(1 == ~T8_E~0); 26889#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 26890#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 28479#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 27810#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 27463#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 27464#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 28741#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 27403#L1476-3 assume !(1 == ~E_3~0); 27404#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 27804#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 27431#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 27432#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 27844#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 27845#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 28271#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 28261#L1516-3 assume !(1 == ~E_11~0); 28262#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 27961#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 27962#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 28356#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 27238#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 28131#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 27772#L1911 assume !(0 == start_simulation_~tmp~3#1); 27773#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 28295#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 27363#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 28233#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 27067#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 27068#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 27297#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 27298#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 27481#L1892-2 [2021-12-15 17:21:48,523 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:48,523 INFO L85 PathProgramCache]: Analyzing trace with hash 888419230, now seen corresponding path program 1 times [2021-12-15 17:21:48,524 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:48,524 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1739329269] [2021-12-15 17:21:48,524 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:48,524 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:48,532 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:48,551 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:48,551 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:48,551 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1739329269] [2021-12-15 17:21:48,552 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1739329269] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:48,552 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:48,553 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:48,553 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [529214505] [2021-12-15 17:21:48,553 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:48,553 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:21:48,553 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:48,553 INFO L85 PathProgramCache]: Analyzing trace with hash -1427949617, now seen corresponding path program 1 times [2021-12-15 17:21:48,556 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:48,559 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1977900059] [2021-12-15 17:21:48,560 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:48,561 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:48,570 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:48,592 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:48,592 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:48,593 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1977900059] [2021-12-15 17:21:48,594 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1977900059] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:48,595 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:48,595 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:48,595 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1093371571] [2021-12-15 17:21:48,596 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:48,596 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:21:48,596 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:21:48,597 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:21:48,597 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:21:48,597 INFO L87 Difference]: Start difference. First operand 1914 states and 2829 transitions. cyclomatic complexity: 916 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:48,621 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:21:48,621 INFO L93 Difference]: Finished difference Result 1914 states and 2828 transitions. [2021-12-15 17:21:48,621 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:21:48,624 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1914 states and 2828 transitions. [2021-12-15 17:21:48,636 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2021-12-15 17:21:48,641 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1914 states to 1914 states and 2828 transitions. [2021-12-15 17:21:48,642 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1914 [2021-12-15 17:21:48,643 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1914 [2021-12-15 17:21:48,643 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1914 states and 2828 transitions. [2021-12-15 17:21:48,644 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:21:48,644 INFO L681 BuchiCegarLoop]: Abstraction has 1914 states and 2828 transitions. [2021-12-15 17:21:48,646 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1914 states and 2828 transitions. [2021-12-15 17:21:48,665 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1914 to 1914. [2021-12-15 17:21:48,668 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1914 states, 1914 states have (on average 1.477533960292581) internal successors, (2828), 1913 states have internal predecessors, (2828), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:48,671 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1914 states to 1914 states and 2828 transitions. [2021-12-15 17:21:48,671 INFO L704 BuchiCegarLoop]: Abstraction has 1914 states and 2828 transitions. [2021-12-15 17:21:48,671 INFO L587 BuchiCegarLoop]: Abstraction has 1914 states and 2828 transitions. [2021-12-15 17:21:48,671 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2021-12-15 17:21:48,672 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1914 states and 2828 transitions. [2021-12-15 17:21:48,677 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2021-12-15 17:21:48,677 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:21:48,677 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:21:48,679 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:48,679 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:48,679 INFO L791 eck$LassoCheckResult]: Stem: 31554#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 31555#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 31374#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 31090#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 31091#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 32267#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 32268#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 31226#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 31227#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 31681#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 31516#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 31517#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 31293#L916-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 31294#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 31692#L926-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 31869#L931-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 32023#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 32060#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 31304#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 31305#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 32480#L1258-2 assume !(0 == ~T1_E~0); 31599#L1263-1 assume !(0 == ~T2_E~0); 31600#L1268-1 assume !(0 == ~T3_E~0); 31903#L1273-1 assume !(0 == ~T4_E~0); 32462#L1278-1 assume !(0 == ~T5_E~0); 32323#L1283-1 assume !(0 == ~T6_E~0); 32324#L1288-1 assume !(0 == ~T7_E~0); 32560#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 32548#L1298-1 assume !(0 == ~T9_E~0); 32474#L1303-1 assume !(0 == ~T10_E~0); 31119#L1308-1 assume !(0 == ~T11_E~0); 31061#L1313-1 assume !(0 == ~T12_E~0); 31062#L1318-1 assume !(0 == ~T13_E~0); 31068#L1323-1 assume !(0 == ~E_1~0); 31069#L1328-1 assume !(0 == ~E_2~0); 31236#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 32195#L1338-1 assume !(0 == ~E_4~0); 32196#L1343-1 assume !(0 == ~E_5~0); 32297#L1348-1 assume !(0 == ~E_6~0); 32583#L1353-1 assume !(0 == ~E_7~0); 31922#L1358-1 assume !(0 == ~E_8~0); 31923#L1363-1 assume !(0 == ~E_9~0); 32213#L1368-1 assume !(0 == ~E_10~0); 30898#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 30899#L1378-1 assume !(0 == ~E_12~0); 31185#L1383-1 assume !(0 == ~E_13~0); 31186#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 31929#L607 assume 1 == ~m_pc~0; 31930#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 31256#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 32295#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 31849#L1560 assume !(0 != activate_threads_~tmp~1#1); 31850#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 31081#L626 assume !(1 == ~t1_pc~0); 31082#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 31350#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 31351#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 31520#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 30981#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 30982#L645 assume 1 == ~t2_pc~0; 31098#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 31055#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 31732#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 31733#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 31825#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 31826#L664 assume 1 == ~t3_pc~0; 32582#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 30822#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 30823#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 31481#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 31482#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 32490#L683 assume !(1 == ~t4_pc~0); 32045#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 31997#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 31998#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 32032#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 32156#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 31775#L702 assume 1 == ~t5_pc~0; 31776#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 31701#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 32151#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 32449#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 32390#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 30870#L721 assume !(1 == ~t6_pc~0); 30844#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 30845#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 31008#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 31490#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 31491#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 32092#L740 assume 1 == ~t7_pc~0; 30919#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 30732#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 30733#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 30722#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 30723#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 31426#L759 assume !(1 == ~t8_pc~0); 31427#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 31456#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 32149#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 32150#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 32281#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 32559#L778 assume 1 == ~t9_pc~0; 32446#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 30897#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 30837#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 30766#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 30767#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 31094#L797 assume !(1 == ~t10_pc~0); 31095#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 31213#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 32347#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 31597#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 31598#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 31887#L816 assume 1 == ~t11_pc~0; 30802#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 30803#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 31558#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 31497#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 31498#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 32022#L835 assume 1 == ~t12_pc~0; 31900#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 30966#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 30988#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 31129#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 31654#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 31655#L854 assume !(1 == ~t13_pc~0); 31295#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 31296#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 31346#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 31006#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 31007#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 32386#L1401 assume !(1 == ~M_E~0); 31485#L1401-2 assume !(1 == ~T1_E~0); 31486#L1406-1 assume !(1 == ~T2_E~0); 32081#L1411-1 assume !(1 == ~T3_E~0); 32082#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 31748#L1421-1 assume !(1 == ~T5_E~0); 31291#L1426-1 assume !(1 == ~T6_E~0); 31292#L1431-1 assume !(1 == ~T7_E~0); 30840#L1436-1 assume !(1 == ~T8_E~0); 30841#L1441-1 assume !(1 == ~T9_E~0); 31588#L1446-1 assume !(1 == ~T10_E~0); 31589#L1451-1 assume !(1 == ~T11_E~0); 32294#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 31948#L1461-1 assume !(1 == ~T13_E~0); 31509#L1466-1 assume !(1 == ~E_1~0); 31510#L1471-1 assume !(1 == ~E_2~0); 32279#L1476-1 assume !(1 == ~E_3~0); 32280#L1481-1 assume !(1 == ~E_4~0); 32428#L1486-1 assume !(1 == ~E_5~0); 31134#L1491-1 assume !(1 == ~E_6~0); 30774#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 30775#L1501-1 assume !(1 == ~E_8~0); 31586#L1506-1 assume !(1 == ~E_9~0); 31587#L1511-1 assume !(1 == ~E_10~0); 31543#L1516-1 assume !(1 == ~E_11~0); 30718#L1521-1 assume !(1 == ~E_12~0); 30719#L1526-1 assume !(1 == ~E_13~0); 30773#L1531-1 assume { :end_inline_reset_delta_events } true; 31316#L1892-2 [2021-12-15 17:21:48,679 INFO L793 eck$LassoCheckResult]: Loop: 31316#L1892-2 assume !false; 32339#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 32537#L1233 assume !false; 32520#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 31852#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 31832#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 31990#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 30816#L1046 assume !(0 != eval_~tmp~0#1); 30818#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 30852#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 32024#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 32581#L1258-5 assume !(0 == ~T1_E~0); 30994#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 30995#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 32573#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 32579#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 32580#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 31218#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 31219#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 32336#L1298-3 assume !(0 == ~T9_E~0); 32337#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 32496#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 32335#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 31836#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 30996#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 30997#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 32420#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 31139#L1338-3 assume !(0 == ~E_4~0); 31140#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 32252#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 32425#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 32426#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 31792#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 31352#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 31353#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 32109#L1378-3 assume !(0 == ~E_12~0); 32110#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 32291#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 32292#L607-42 assume 1 == ~m_pc~0; 31905#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 31633#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 31634#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 31366#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 31367#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 31888#L626-42 assume 1 == ~t1_pc~0; 31450#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 31451#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 31755#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 31756#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 31030#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 31031#L645-42 assume !(1 == ~t2_pc~0); 32230#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 32231#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 32396#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 31237#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 30744#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 30745#L664-42 assume !(1 == ~t3_pc~0); 31271#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 31272#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 32523#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 32058#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 32059#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 32224#L683-42 assume !(1 == ~t4_pc~0); 31932#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 31933#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 32065#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 32485#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 32486#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 32330#L702-42 assume !(1 == ~t5_pc~0); 31442#L702-44 is_transmit5_triggered_~__retres1~5#1 := 0; 31443#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 31739#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 32412#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 30760#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 30761#L721-42 assume 1 == ~t6_pc~0; 30914#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 30934#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 31398#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 32565#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 31570#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 31416#L740-42 assume !(1 == ~t7_pc~0); 31153#L740-44 is_transmit7_triggered_~__retres1~7#1 := 0; 31154#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 31695#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 31550#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 31551#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 31824#L759-42 assume 1 == ~t8_pc~0; 31673#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 31605#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 31606#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 31684#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 31685#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 31780#L778-42 assume 1 == ~t9_pc~0; 31617#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 31619#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 32029#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 31934#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 31935#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 31992#L797-42 assume 1 == ~t10_pc~0; 31159#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 31160#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 32161#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 32470#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 32030#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 32031#L816-42 assume 1 == ~t11_pc~0; 30708#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 30709#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 31251#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 31252#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 31331#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 31332#L835-42 assume 1 == ~t12_pc~0; 31736#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 31629#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 31306#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 31307#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 32389#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 32173#L854-42 assume !(1 == ~t13_pc~0); 31249#L854-44 is_transmit13_triggered_~__retres1~13#1 := 0; 31250#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 30860#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 30861#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 31507#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 31508#L1401-3 assume !(1 == ~M_E~0); 32286#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 31097#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 30961#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 30962#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 31561#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 31562#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 31137#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 31138#L1436-3 assume !(1 == ~T8_E~0); 30724#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 30725#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 32314#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 31645#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 31298#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 31299#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 32576#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 31238#L1476-3 assume !(1 == ~E_3~0); 31239#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 31639#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 31266#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 31267#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 31679#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 31680#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 32106#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 32096#L1516-3 assume !(1 == ~E_11~0); 32097#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 31796#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 31797#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 32191#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 31073#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 31966#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 31607#L1911 assume !(0 == start_simulation_~tmp~3#1); 31608#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 32130#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 31198#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 32068#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 30902#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 30903#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 31132#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 31133#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 31316#L1892-2 [2021-12-15 17:21:48,680 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:48,680 INFO L85 PathProgramCache]: Analyzing trace with hash 1153066720, now seen corresponding path program 1 times [2021-12-15 17:21:48,680 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:48,680 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1779015004] [2021-12-15 17:21:48,680 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:48,680 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:48,689 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:48,703 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:48,703 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:48,703 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1779015004] [2021-12-15 17:21:48,704 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1779015004] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:48,704 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:48,704 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:48,704 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [472086574] [2021-12-15 17:21:48,704 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:48,704 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:21:48,705 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:48,705 INFO L85 PathProgramCache]: Analyzing trace with hash -835808881, now seen corresponding path program 2 times [2021-12-15 17:21:48,705 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:48,705 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1130489939] [2021-12-15 17:21:48,705 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:48,705 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:48,715 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:48,735 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:48,735 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:48,735 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1130489939] [2021-12-15 17:21:48,735 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1130489939] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:48,735 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:48,735 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:48,735 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1279941259] [2021-12-15 17:21:48,735 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:48,736 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:21:48,736 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:21:48,737 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:21:48,737 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:21:48,737 INFO L87 Difference]: Start difference. First operand 1914 states and 2828 transitions. cyclomatic complexity: 915 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:48,759 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:21:48,760 INFO L93 Difference]: Finished difference Result 1914 states and 2827 transitions. [2021-12-15 17:21:48,760 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:21:48,761 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1914 states and 2827 transitions. [2021-12-15 17:21:48,767 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2021-12-15 17:21:48,773 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1914 states to 1914 states and 2827 transitions. [2021-12-15 17:21:48,773 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1914 [2021-12-15 17:21:48,774 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1914 [2021-12-15 17:21:48,774 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1914 states and 2827 transitions. [2021-12-15 17:21:48,776 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:21:48,776 INFO L681 BuchiCegarLoop]: Abstraction has 1914 states and 2827 transitions. [2021-12-15 17:21:48,778 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1914 states and 2827 transitions. [2021-12-15 17:21:48,796 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1914 to 1914. [2021-12-15 17:21:48,799 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1914 states, 1914 states have (on average 1.4770114942528736) internal successors, (2827), 1913 states have internal predecessors, (2827), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:48,802 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1914 states to 1914 states and 2827 transitions. [2021-12-15 17:21:48,802 INFO L704 BuchiCegarLoop]: Abstraction has 1914 states and 2827 transitions. [2021-12-15 17:21:48,802 INFO L587 BuchiCegarLoop]: Abstraction has 1914 states and 2827 transitions. [2021-12-15 17:21:48,802 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2021-12-15 17:21:48,802 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1914 states and 2827 transitions. [2021-12-15 17:21:48,806 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2021-12-15 17:21:48,807 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:21:48,807 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:21:48,808 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:48,808 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:48,809 INFO L791 eck$LassoCheckResult]: Stem: 35389#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 35390#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 35209#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 34925#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 34926#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 36102#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 36103#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 35061#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 35062#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 35520#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 35351#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 35352#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 35128#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 35129#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 35527#L926-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 35704#L931-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 35859#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 35895#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 35141#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 35142#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 36315#L1258-2 assume !(0 == ~T1_E~0); 35434#L1263-1 assume !(0 == ~T2_E~0); 35435#L1268-1 assume !(0 == ~T3_E~0); 35738#L1273-1 assume !(0 == ~T4_E~0); 36297#L1278-1 assume !(0 == ~T5_E~0); 36158#L1283-1 assume !(0 == ~T6_E~0); 36159#L1288-1 assume !(0 == ~T7_E~0); 36396#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 36383#L1298-1 assume !(0 == ~T9_E~0); 36309#L1303-1 assume !(0 == ~T10_E~0); 34954#L1308-1 assume !(0 == ~T11_E~0); 34899#L1313-1 assume !(0 == ~T12_E~0); 34900#L1318-1 assume !(0 == ~T13_E~0); 34905#L1323-1 assume !(0 == ~E_1~0); 34906#L1328-1 assume !(0 == ~E_2~0); 35071#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 36030#L1338-1 assume !(0 == ~E_4~0); 36031#L1343-1 assume !(0 == ~E_5~0); 36132#L1348-1 assume !(0 == ~E_6~0); 36418#L1353-1 assume !(0 == ~E_7~0); 35757#L1358-1 assume !(0 == ~E_8~0); 35758#L1363-1 assume !(0 == ~E_9~0); 36049#L1368-1 assume !(0 == ~E_10~0); 34733#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 34734#L1378-1 assume !(0 == ~E_12~0); 35022#L1383-1 assume !(0 == ~E_13~0); 35023#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 35764#L607 assume 1 == ~m_pc~0; 35765#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 35091#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 36130#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 35684#L1560 assume !(0 != activate_threads_~tmp~1#1); 35685#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 34916#L626 assume !(1 == ~t1_pc~0); 34917#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 35187#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 35188#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 35357#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 34819#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 34820#L645 assume 1 == ~t2_pc~0; 34933#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 34890#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 35570#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 35571#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 35660#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 35661#L664 assume 1 == ~t3_pc~0; 36417#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 34661#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 34662#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 35316#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 35317#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 36325#L683 assume !(1 == ~t4_pc~0); 35880#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 35832#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 35833#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 35867#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 35991#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 35614#L702 assume 1 == ~t5_pc~0; 35615#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 35537#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 35986#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 36285#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 36226#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 34705#L721 assume !(1 == ~t6_pc~0); 34679#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 34680#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 34843#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 35325#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 35326#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 35927#L740 assume 1 == ~t7_pc~0; 34754#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 34567#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 34568#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 34557#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 34558#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 35262#L759 assume !(1 == ~t8_pc~0); 35263#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 35291#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 35984#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 35985#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 36116#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 36394#L778 assume 1 == ~t9_pc~0; 36283#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 34732#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 34672#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 34601#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 34602#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 34930#L797 assume !(1 == ~t10_pc~0); 34931#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 35048#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 36182#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 35432#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 35433#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 35722#L816 assume 1 == ~t11_pc~0; 34637#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 34638#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 35395#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 35332#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 35333#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 35857#L835 assume 1 == ~t12_pc~0; 35735#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 34801#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 34823#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 34964#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 35489#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 35490#L854 assume !(1 == ~t13_pc~0); 35130#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 35131#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 35183#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 34841#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 34842#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 36221#L1401 assume !(1 == ~M_E~0); 35320#L1401-2 assume !(1 == ~T1_E~0); 35321#L1406-1 assume !(1 == ~T2_E~0); 35916#L1411-1 assume !(1 == ~T3_E~0); 35917#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 35583#L1421-1 assume !(1 == ~T5_E~0); 35126#L1426-1 assume !(1 == ~T6_E~0); 35127#L1431-1 assume !(1 == ~T7_E~0); 34675#L1436-1 assume !(1 == ~T8_E~0); 34676#L1441-1 assume !(1 == ~T9_E~0); 35423#L1446-1 assume !(1 == ~T10_E~0); 35424#L1451-1 assume !(1 == ~T11_E~0); 36129#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 35783#L1461-1 assume !(1 == ~T13_E~0); 35344#L1466-1 assume !(1 == ~E_1~0); 35345#L1471-1 assume !(1 == ~E_2~0); 36114#L1476-1 assume !(1 == ~E_3~0); 36115#L1481-1 assume !(1 == ~E_4~0); 36263#L1486-1 assume !(1 == ~E_5~0); 34969#L1491-1 assume !(1 == ~E_6~0); 34609#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 34610#L1501-1 assume !(1 == ~E_8~0); 35421#L1506-1 assume !(1 == ~E_9~0); 35422#L1511-1 assume !(1 == ~E_10~0); 35378#L1516-1 assume !(1 == ~E_11~0); 34553#L1521-1 assume !(1 == ~E_12~0); 34554#L1526-1 assume !(1 == ~E_13~0); 34608#L1531-1 assume { :end_inline_reset_delta_events } true; 35151#L1892-2 [2021-12-15 17:21:48,809 INFO L793 eck$LassoCheckResult]: Loop: 35151#L1892-2 assume !false; 36174#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 36372#L1233 assume !false; 36355#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 35687#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 35667#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 35825#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 34651#L1046 assume !(0 != eval_~tmp~0#1); 34653#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 34687#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 35858#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 36416#L1258-5 assume !(0 == ~T1_E~0); 34829#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 34830#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 36408#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 36414#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 36415#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 35053#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 35054#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 36171#L1298-3 assume !(0 == ~T9_E~0); 36172#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 36331#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 36170#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 35671#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 34831#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 34832#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 36255#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 34974#L1338-3 assume !(0 == ~E_4~0); 34975#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 36087#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 36260#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 36261#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 35627#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 35185#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 35186#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 35944#L1378-3 assume !(0 == ~E_12~0); 35945#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 36126#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 36127#L607-42 assume 1 == ~m_pc~0; 35740#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 35468#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 35469#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 35201#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 35202#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 35723#L626-42 assume 1 == ~t1_pc~0; 35285#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 35286#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 35590#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 35591#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 34865#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 34866#L645-42 assume !(1 == ~t2_pc~0); 36065#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 36066#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 36231#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 35072#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 34579#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 34580#L664-42 assume !(1 == ~t3_pc~0); 35106#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 35107#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 36358#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 35893#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 35894#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 36059#L683-42 assume !(1 == ~t4_pc~0); 35767#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 35768#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 35900#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 36320#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 36321#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 36165#L702-42 assume 1 == ~t5_pc~0; 35653#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 35278#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 35574#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 36247#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 34595#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 34596#L721-42 assume 1 == ~t6_pc~0; 34749#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 34769#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 35233#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 36400#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 35405#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 35251#L740-42 assume 1 == ~t7_pc~0; 35252#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 34989#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 35530#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 35385#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 35386#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 35659#L759-42 assume 1 == ~t8_pc~0; 35508#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 35440#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 35441#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 35518#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 35519#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 35613#L778-42 assume 1 == ~t9_pc~0; 35452#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 35454#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 35864#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 35769#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 35770#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 35827#L797-42 assume 1 == ~t10_pc~0; 34994#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 34995#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 35996#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 36305#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 35865#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 35866#L816-42 assume !(1 == ~t11_pc~0); 34545#L816-44 is_transmit11_triggered_~__retres1~11#1 := 0; 34544#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 35086#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 35087#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 35166#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 35167#L835-42 assume 1 == ~t12_pc~0; 35569#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 35464#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 35139#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 35140#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 36224#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 36008#L854-42 assume 1 == ~t13_pc~0; 36009#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 35085#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 34695#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 34696#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 35342#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 35343#L1401-3 assume !(1 == ~M_E~0); 36121#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 34929#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 34796#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 34797#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 35396#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 35397#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 34972#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 34973#L1436-3 assume !(1 == ~T8_E~0); 34559#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 34560#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 36149#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 35480#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 35133#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 35134#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 36411#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 35073#L1476-3 assume !(1 == ~E_3~0); 35074#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 35474#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 35101#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 35102#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 35514#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 35515#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 35941#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 35931#L1516-3 assume !(1 == ~E_11~0); 35932#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 35631#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 35632#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 36026#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 34908#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 35801#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 35442#L1911 assume !(0 == start_simulation_~tmp~3#1); 35443#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 35965#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 35033#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 35903#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 34737#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 34738#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 34967#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 34968#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 35151#L1892-2 [2021-12-15 17:21:48,809 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:48,809 INFO L85 PathProgramCache]: Analyzing trace with hash -778058914, now seen corresponding path program 1 times [2021-12-15 17:21:48,809 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:48,810 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [973590614] [2021-12-15 17:21:48,810 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:48,810 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:48,819 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:48,836 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:48,836 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:48,836 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [973590614] [2021-12-15 17:21:48,836 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [973590614] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:48,836 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:48,836 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:48,836 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [51452336] [2021-12-15 17:21:48,836 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:48,837 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:21:48,837 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:48,838 INFO L85 PathProgramCache]: Analyzing trace with hash 1042381777, now seen corresponding path program 2 times [2021-12-15 17:21:48,838 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:48,838 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [862858521] [2021-12-15 17:21:48,838 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:48,838 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:48,851 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:48,868 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:48,868 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:48,868 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [862858521] [2021-12-15 17:21:48,868 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [862858521] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:48,868 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:48,869 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:48,869 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1210569796] [2021-12-15 17:21:48,869 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:48,869 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:21:48,869 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:21:48,870 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:21:48,870 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:21:48,870 INFO L87 Difference]: Start difference. First operand 1914 states and 2827 transitions. cyclomatic complexity: 914 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:48,889 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:21:48,889 INFO L93 Difference]: Finished difference Result 1914 states and 2826 transitions. [2021-12-15 17:21:48,890 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:21:48,890 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1914 states and 2826 transitions. [2021-12-15 17:21:48,896 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2021-12-15 17:21:48,907 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1914 states to 1914 states and 2826 transitions. [2021-12-15 17:21:48,907 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1914 [2021-12-15 17:21:48,908 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1914 [2021-12-15 17:21:48,908 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1914 states and 2826 transitions. [2021-12-15 17:21:48,910 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:21:48,910 INFO L681 BuchiCegarLoop]: Abstraction has 1914 states and 2826 transitions. [2021-12-15 17:21:48,912 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1914 states and 2826 transitions. [2021-12-15 17:21:48,929 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1914 to 1914. [2021-12-15 17:21:48,942 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1914 states, 1914 states have (on average 1.4764890282131662) internal successors, (2826), 1913 states have internal predecessors, (2826), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:48,946 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1914 states to 1914 states and 2826 transitions. [2021-12-15 17:21:48,946 INFO L704 BuchiCegarLoop]: Abstraction has 1914 states and 2826 transitions. [2021-12-15 17:21:48,946 INFO L587 BuchiCegarLoop]: Abstraction has 1914 states and 2826 transitions. [2021-12-15 17:21:48,946 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2021-12-15 17:21:48,946 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1914 states and 2826 transitions. [2021-12-15 17:21:48,950 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2021-12-15 17:21:48,950 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:21:48,950 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:21:48,952 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:48,952 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:48,952 INFO L791 eck$LassoCheckResult]: Stem: 39224#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 39225#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 39044#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 38760#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 38761#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 39937#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 39938#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 38896#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 38897#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 39355#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 39186#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 39187#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 38963#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 38964#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 39362#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 39539#L931-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 39693#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 39730#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 38976#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 38977#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 40150#L1258-2 assume !(0 == ~T1_E~0); 39269#L1263-1 assume !(0 == ~T2_E~0); 39270#L1268-1 assume !(0 == ~T3_E~0); 39573#L1273-1 assume !(0 == ~T4_E~0); 40132#L1278-1 assume !(0 == ~T5_E~0); 39993#L1283-1 assume !(0 == ~T6_E~0); 39994#L1288-1 assume !(0 == ~T7_E~0); 40231#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 40218#L1298-1 assume !(0 == ~T9_E~0); 40144#L1303-1 assume !(0 == ~T10_E~0); 38789#L1308-1 assume !(0 == ~T11_E~0); 38731#L1313-1 assume !(0 == ~T12_E~0); 38732#L1318-1 assume !(0 == ~T13_E~0); 38740#L1323-1 assume !(0 == ~E_1~0); 38741#L1328-1 assume !(0 == ~E_2~0); 38906#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 39865#L1338-1 assume !(0 == ~E_4~0); 39866#L1343-1 assume !(0 == ~E_5~0); 39967#L1348-1 assume !(0 == ~E_6~0); 40253#L1353-1 assume !(0 == ~E_7~0); 39592#L1358-1 assume !(0 == ~E_8~0); 39593#L1363-1 assume !(0 == ~E_9~0); 39884#L1368-1 assume !(0 == ~E_10~0); 38568#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 38569#L1378-1 assume !(0 == ~E_12~0); 38857#L1383-1 assume !(0 == ~E_13~0); 38858#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 39599#L607 assume 1 == ~m_pc~0; 39600#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 38926#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 39965#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 39519#L1560 assume !(0 != activate_threads_~tmp~1#1); 39520#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 38751#L626 assume !(1 == ~t1_pc~0); 38752#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 39022#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 39023#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 39192#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 38653#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 38654#L645 assume 1 == ~t2_pc~0; 38768#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 38725#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 39405#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 39406#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 39495#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 39496#L664 assume 1 == ~t3_pc~0; 40252#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 38496#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 38497#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 39151#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 39152#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 40160#L683 assume !(1 == ~t4_pc~0); 39715#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 39667#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 39668#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 39702#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 39826#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 39449#L702 assume 1 == ~t5_pc~0; 39450#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 39372#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 39821#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 40120#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 40061#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 38540#L721 assume !(1 == ~t6_pc~0); 38514#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 38515#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 38678#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 39160#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 39161#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 39762#L740 assume 1 == ~t7_pc~0; 38589#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 38402#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 38403#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 38392#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 38393#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 39097#L759 assume !(1 == ~t8_pc~0); 39098#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 39126#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 39819#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 39820#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 39951#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 40229#L778 assume 1 == ~t9_pc~0; 40118#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 38567#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 38507#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 38436#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 38437#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 38765#L797 assume !(1 == ~t10_pc~0); 38766#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 38883#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 40017#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 39267#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 39268#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 39557#L816 assume 1 == ~t11_pc~0; 38472#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 38473#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 39230#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 39167#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 39168#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 39692#L835 assume 1 == ~t12_pc~0; 39570#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 38636#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 38658#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 38799#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 39324#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 39325#L854 assume !(1 == ~t13_pc~0); 38965#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 38966#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 39018#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 38676#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 38677#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 40056#L1401 assume !(1 == ~M_E~0); 39155#L1401-2 assume !(1 == ~T1_E~0); 39156#L1406-1 assume !(1 == ~T2_E~0); 39751#L1411-1 assume !(1 == ~T3_E~0); 39752#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 39418#L1421-1 assume !(1 == ~T5_E~0); 38961#L1426-1 assume !(1 == ~T6_E~0); 38962#L1431-1 assume !(1 == ~T7_E~0); 38510#L1436-1 assume !(1 == ~T8_E~0); 38511#L1441-1 assume !(1 == ~T9_E~0); 39260#L1446-1 assume !(1 == ~T10_E~0); 39261#L1451-1 assume !(1 == ~T11_E~0); 39964#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 39618#L1461-1 assume !(1 == ~T13_E~0); 39179#L1466-1 assume !(1 == ~E_1~0); 39180#L1471-1 assume !(1 == ~E_2~0); 39949#L1476-1 assume !(1 == ~E_3~0); 39950#L1481-1 assume !(1 == ~E_4~0); 40098#L1486-1 assume !(1 == ~E_5~0); 38804#L1491-1 assume !(1 == ~E_6~0); 38444#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 38445#L1501-1 assume !(1 == ~E_8~0); 39256#L1506-1 assume !(1 == ~E_9~0); 39257#L1511-1 assume !(1 == ~E_10~0); 39213#L1516-1 assume !(1 == ~E_11~0); 38390#L1521-1 assume !(1 == ~E_12~0); 38391#L1526-1 assume !(1 == ~E_13~0); 38443#L1531-1 assume { :end_inline_reset_delta_events } true; 38986#L1892-2 [2021-12-15 17:21:48,952 INFO L793 eck$LassoCheckResult]: Loop: 38986#L1892-2 assume !false; 40009#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 40207#L1233 assume !false; 40190#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 39522#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 39502#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 39660#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 38486#L1046 assume !(0 != eval_~tmp~0#1); 38488#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 38522#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 39694#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 40251#L1258-5 assume !(0 == ~T1_E~0); 38666#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 38667#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 40243#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 40249#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 40250#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 38890#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 38891#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 40006#L1298-3 assume !(0 == ~T9_E~0); 40007#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 40166#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 40005#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 39506#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 38668#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 38669#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 40090#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 38809#L1338-3 assume !(0 == ~E_4~0); 38810#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 39922#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 40095#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 40096#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 39462#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 39020#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 39021#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 39779#L1378-3 assume !(0 == ~E_12~0); 39780#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 39961#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 39962#L607-42 assume 1 == ~m_pc~0; 39575#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 39303#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 39304#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 39036#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 39037#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 39558#L626-42 assume 1 == ~t1_pc~0; 39120#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 39121#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 39425#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 39426#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 38700#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 38701#L645-42 assume !(1 == ~t2_pc~0); 39900#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 39901#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 40066#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 38907#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 38414#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 38415#L664-42 assume 1 == ~t3_pc~0; 39217#L665-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 38942#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 40193#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 39728#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 39729#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 39894#L683-42 assume !(1 == ~t4_pc~0); 39602#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 39603#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 39735#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 40155#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 40156#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 40000#L702-42 assume 1 == ~t5_pc~0; 39488#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 39113#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 39409#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 40082#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 38430#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 38431#L721-42 assume 1 == ~t6_pc~0; 38584#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 38604#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 39068#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 40235#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 39240#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 39086#L740-42 assume !(1 == ~t7_pc~0); 38823#L740-44 is_transmit7_triggered_~__retres1~7#1 := 0; 38824#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 39365#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 39220#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 39221#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 39494#L759-42 assume !(1 == ~t8_pc~0); 39344#L759-44 is_transmit8_triggered_~__retres1~8#1 := 0; 39275#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 39276#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 39353#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 39354#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 39448#L778-42 assume 1 == ~t9_pc~0; 39287#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 39289#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 39698#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 39604#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 39605#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 39662#L797-42 assume 1 == ~t10_pc~0; 38829#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 38830#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 39831#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 40140#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 39700#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 39701#L816-42 assume 1 == ~t11_pc~0; 38378#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 38379#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 38921#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 38922#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 39001#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 39002#L835-42 assume !(1 == ~t12_pc~0); 39298#L835-44 is_transmit12_triggered_~__retres1~12#1 := 0; 39299#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 38974#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 38975#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 40059#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 39843#L854-42 assume 1 == ~t13_pc~0; 39844#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 38918#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 38530#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 38531#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 39177#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 39178#L1401-3 assume !(1 == ~M_E~0); 39956#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 38764#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 38631#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 38632#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 39231#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 39232#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 38807#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 38808#L1436-3 assume !(1 == ~T8_E~0); 38394#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 38395#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 39984#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 39315#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 38968#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 38969#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 40246#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 38908#L1476-3 assume !(1 == ~E_3~0); 38909#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 39309#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 38936#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 38937#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 39349#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 39350#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 39776#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 39766#L1516-3 assume !(1 == ~E_11~0); 39767#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 39466#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 39467#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 39861#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 38743#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 39636#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 39277#L1911 assume !(0 == start_simulation_~tmp~3#1); 39278#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 39800#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 38868#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 39738#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 38572#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 38573#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 38802#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 38803#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 38986#L1892-2 [2021-12-15 17:21:48,953 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:48,953 INFO L85 PathProgramCache]: Analyzing trace with hash 1619928924, now seen corresponding path program 1 times [2021-12-15 17:21:48,953 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:48,953 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [418296664] [2021-12-15 17:21:48,953 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:48,953 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:48,961 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:48,978 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:48,978 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:48,979 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [418296664] [2021-12-15 17:21:48,979 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [418296664] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:48,979 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:48,979 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:48,979 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [22837777] [2021-12-15 17:21:48,979 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:48,979 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:21:48,979 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:48,980 INFO L85 PathProgramCache]: Analyzing trace with hash -744572368, now seen corresponding path program 1 times [2021-12-15 17:21:48,980 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:48,980 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [606592208] [2021-12-15 17:21:48,980 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:48,980 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:48,988 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:49,049 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:49,049 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:49,049 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [606592208] [2021-12-15 17:21:49,049 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [606592208] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:49,049 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:49,049 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:49,049 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [645640234] [2021-12-15 17:21:49,049 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:49,050 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:21:49,050 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:21:49,050 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:21:49,050 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:21:49,051 INFO L87 Difference]: Start difference. First operand 1914 states and 2826 transitions. cyclomatic complexity: 913 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:49,069 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:21:49,069 INFO L93 Difference]: Finished difference Result 1914 states and 2825 transitions. [2021-12-15 17:21:49,070 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:21:49,070 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1914 states and 2825 transitions. [2021-12-15 17:21:49,076 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2021-12-15 17:21:49,080 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1914 states to 1914 states and 2825 transitions. [2021-12-15 17:21:49,080 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1914 [2021-12-15 17:21:49,081 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1914 [2021-12-15 17:21:49,082 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1914 states and 2825 transitions. [2021-12-15 17:21:49,083 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:21:49,083 INFO L681 BuchiCegarLoop]: Abstraction has 1914 states and 2825 transitions. [2021-12-15 17:21:49,085 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1914 states and 2825 transitions. [2021-12-15 17:21:49,101 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1914 to 1914. [2021-12-15 17:21:49,102 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1914 states, 1914 states have (on average 1.4759665621734588) internal successors, (2825), 1913 states have internal predecessors, (2825), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:49,105 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1914 states to 1914 states and 2825 transitions. [2021-12-15 17:21:49,105 INFO L704 BuchiCegarLoop]: Abstraction has 1914 states and 2825 transitions. [2021-12-15 17:21:49,105 INFO L587 BuchiCegarLoop]: Abstraction has 1914 states and 2825 transitions. [2021-12-15 17:21:49,105 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2021-12-15 17:21:49,105 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1914 states and 2825 transitions. [2021-12-15 17:21:49,109 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2021-12-15 17:21:49,109 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:21:49,110 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:21:49,111 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:49,111 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:49,111 INFO L791 eck$LassoCheckResult]: Stem: 43059#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 43060#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 42879#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 42595#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 42596#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 43772#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 43773#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 42731#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 42732#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 43190#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 43021#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 43022#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 42798#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 42799#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 43197#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 43374#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 43528#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 43565#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 42811#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 42812#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 43985#L1258-2 assume !(0 == ~T1_E~0); 43104#L1263-1 assume !(0 == ~T2_E~0); 43105#L1268-1 assume !(0 == ~T3_E~0); 43408#L1273-1 assume !(0 == ~T4_E~0); 43967#L1278-1 assume !(0 == ~T5_E~0); 43828#L1283-1 assume !(0 == ~T6_E~0); 43829#L1288-1 assume !(0 == ~T7_E~0); 44066#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 44053#L1298-1 assume !(0 == ~T9_E~0); 43979#L1303-1 assume !(0 == ~T10_E~0); 42624#L1308-1 assume !(0 == ~T11_E~0); 42566#L1313-1 assume !(0 == ~T12_E~0); 42567#L1318-1 assume !(0 == ~T13_E~0); 42575#L1323-1 assume !(0 == ~E_1~0); 42576#L1328-1 assume !(0 == ~E_2~0); 42741#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 43700#L1338-1 assume !(0 == ~E_4~0); 43701#L1343-1 assume !(0 == ~E_5~0); 43802#L1348-1 assume !(0 == ~E_6~0); 44088#L1353-1 assume !(0 == ~E_7~0); 43427#L1358-1 assume !(0 == ~E_8~0); 43428#L1363-1 assume !(0 == ~E_9~0); 43718#L1368-1 assume !(0 == ~E_10~0); 42403#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 42404#L1378-1 assume !(0 == ~E_12~0); 42692#L1383-1 assume !(0 == ~E_13~0); 42693#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 43434#L607 assume 1 == ~m_pc~0; 43435#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 42761#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 43800#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 43354#L1560 assume !(0 != activate_threads_~tmp~1#1); 43355#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 42586#L626 assume !(1 == ~t1_pc~0); 42587#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 42855#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 42856#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 43027#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 42488#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 42489#L645 assume 1 == ~t2_pc~0; 42603#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 42560#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 43240#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 43241#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 43330#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 43331#L664 assume 1 == ~t3_pc~0; 44087#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 42331#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 42332#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 42986#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 42987#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 43995#L683 assume !(1 == ~t4_pc~0); 43550#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 43502#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 43503#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 43537#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 43661#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 43284#L702 assume 1 == ~t5_pc~0; 43285#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 43207#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 43656#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 43955#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 43896#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 42375#L721 assume !(1 == ~t6_pc~0); 42349#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 42350#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 42513#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 42995#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 42996#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 43597#L740 assume 1 == ~t7_pc~0; 42424#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 42237#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 42238#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 42227#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 42228#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 42932#L759 assume !(1 == ~t8_pc~0); 42933#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 42961#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 43654#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 43655#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 43786#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 44064#L778 assume 1 == ~t9_pc~0; 43951#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 42402#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 42342#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 42271#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 42272#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 42600#L797 assume !(1 == ~t10_pc~0); 42601#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 42718#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 43852#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 43102#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 43103#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 43392#L816 assume 1 == ~t11_pc~0; 42307#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 42308#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 43065#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 43002#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 43003#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 43527#L835 assume 1 == ~t12_pc~0; 43405#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 42471#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 42493#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 42634#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 43159#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 43160#L854 assume !(1 == ~t13_pc~0); 42800#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 42801#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 42851#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 42511#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 42512#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 43891#L1401 assume !(1 == ~M_E~0); 42990#L1401-2 assume !(1 == ~T1_E~0); 42991#L1406-1 assume !(1 == ~T2_E~0); 43586#L1411-1 assume !(1 == ~T3_E~0); 43587#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 43253#L1421-1 assume !(1 == ~T5_E~0); 42796#L1426-1 assume !(1 == ~T6_E~0); 42797#L1431-1 assume !(1 == ~T7_E~0); 42345#L1436-1 assume !(1 == ~T8_E~0); 42346#L1441-1 assume !(1 == ~T9_E~0); 43095#L1446-1 assume !(1 == ~T10_E~0); 43096#L1451-1 assume !(1 == ~T11_E~0); 43799#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 43453#L1461-1 assume !(1 == ~T13_E~0); 43014#L1466-1 assume !(1 == ~E_1~0); 43015#L1471-1 assume !(1 == ~E_2~0); 43784#L1476-1 assume !(1 == ~E_3~0); 43785#L1481-1 assume !(1 == ~E_4~0); 43933#L1486-1 assume !(1 == ~E_5~0); 42639#L1491-1 assume !(1 == ~E_6~0); 42279#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 42280#L1501-1 assume !(1 == ~E_8~0); 43091#L1506-1 assume !(1 == ~E_9~0); 43092#L1511-1 assume !(1 == ~E_10~0); 43048#L1516-1 assume !(1 == ~E_11~0); 42225#L1521-1 assume !(1 == ~E_12~0); 42226#L1526-1 assume !(1 == ~E_13~0); 42278#L1531-1 assume { :end_inline_reset_delta_events } true; 42821#L1892-2 [2021-12-15 17:21:49,111 INFO L793 eck$LassoCheckResult]: Loop: 42821#L1892-2 assume !false; 43844#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 44042#L1233 assume !false; 44025#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 43357#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 43337#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 43495#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 42321#L1046 assume !(0 != eval_~tmp~0#1); 42323#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 42357#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 43529#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 44086#L1258-5 assume !(0 == ~T1_E~0); 42501#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 42502#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 44078#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 44084#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 44085#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 42725#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 42726#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 43841#L1298-3 assume !(0 == ~T9_E~0); 43842#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 44001#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 43840#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 43341#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 42503#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 42504#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 43925#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 42644#L1338-3 assume !(0 == ~E_4~0); 42645#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 43757#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 43931#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 43932#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 43299#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 42857#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 42858#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 43614#L1378-3 assume !(0 == ~E_12~0); 43615#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 43796#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 43797#L607-42 assume 1 == ~m_pc~0; 43412#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 43138#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 43139#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 42871#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 42872#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 43393#L626-42 assume 1 == ~t1_pc~0; 42955#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 42956#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 43260#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 43261#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 42535#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 42536#L645-42 assume !(1 == ~t2_pc~0); 43734#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 43735#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 43901#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 42742#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 42249#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 42250#L664-42 assume !(1 == ~t3_pc~0); 42776#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 42777#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 44028#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 43563#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 43564#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 43729#L683-42 assume !(1 == ~t4_pc~0); 43437#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 43438#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 43569#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 43990#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 43991#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 43835#L702-42 assume !(1 == ~t5_pc~0); 42947#L702-44 is_transmit5_triggered_~__retres1~5#1 := 0; 42948#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 43244#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 43917#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 42265#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 42266#L721-42 assume 1 == ~t6_pc~0; 42419#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 42439#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 42903#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 44070#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 43075#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 42921#L740-42 assume !(1 == ~t7_pc~0); 42658#L740-44 is_transmit7_triggered_~__retres1~7#1 := 0; 42659#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 43200#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 43055#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 43056#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 43329#L759-42 assume 1 == ~t8_pc~0; 43178#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 43110#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 43111#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 43188#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 43189#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 43283#L778-42 assume 1 == ~t9_pc~0; 43122#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 43124#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 43533#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 43439#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 43440#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 43497#L797-42 assume 1 == ~t10_pc~0; 42664#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 42665#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 43666#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 43975#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 43535#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 43536#L816-42 assume 1 == ~t11_pc~0; 42213#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 42214#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 42756#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 42757#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 42836#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 42837#L835-42 assume 1 == ~t12_pc~0; 43239#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 43133#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 42809#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 42810#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 43894#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 43678#L854-42 assume !(1 == ~t13_pc~0); 42752#L854-44 is_transmit13_triggered_~__retres1~13#1 := 0; 42753#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 42365#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 42366#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 43012#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 43013#L1401-3 assume !(1 == ~M_E~0); 43791#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 42599#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 42466#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 42467#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 43066#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 43067#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 42642#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 42643#L1436-3 assume !(1 == ~T8_E~0); 42229#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 42230#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 43819#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 43150#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 42803#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 42804#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 44081#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 42743#L1476-3 assume !(1 == ~E_3~0); 42744#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 43144#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 42771#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 42772#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 43183#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 43184#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 43611#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 43601#L1516-3 assume !(1 == ~E_11~0); 43602#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 43301#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 43302#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 43696#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 42578#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 43471#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 43112#L1911 assume !(0 == start_simulation_~tmp~3#1); 43113#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 43635#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 42703#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 43573#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 42407#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 42408#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 42637#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 42638#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 42821#L1892-2 [2021-12-15 17:21:49,112 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:49,112 INFO L85 PathProgramCache]: Analyzing trace with hash 1281641374, now seen corresponding path program 1 times [2021-12-15 17:21:49,112 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:49,112 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [307538863] [2021-12-15 17:21:49,112 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:49,112 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:49,125 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:49,137 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:49,137 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:49,137 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [307538863] [2021-12-15 17:21:49,137 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [307538863] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:49,138 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:49,139 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:49,139 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [699201125] [2021-12-15 17:21:49,139 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:49,140 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:21:49,140 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:49,140 INFO L85 PathProgramCache]: Analyzing trace with hash -835808881, now seen corresponding path program 3 times [2021-12-15 17:21:49,140 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:49,140 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [71536573] [2021-12-15 17:21:49,140 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:49,140 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:49,150 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:49,166 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:49,167 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:49,167 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [71536573] [2021-12-15 17:21:49,167 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [71536573] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:49,167 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:49,167 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:49,167 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2117408747] [2021-12-15 17:21:49,167 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:49,167 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:21:49,167 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:21:49,168 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:21:49,168 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:21:49,168 INFO L87 Difference]: Start difference. First operand 1914 states and 2825 transitions. cyclomatic complexity: 912 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:49,186 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:21:49,187 INFO L93 Difference]: Finished difference Result 1914 states and 2824 transitions. [2021-12-15 17:21:49,187 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:21:49,188 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1914 states and 2824 transitions. [2021-12-15 17:21:49,194 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2021-12-15 17:21:49,199 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1914 states to 1914 states and 2824 transitions. [2021-12-15 17:21:49,199 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1914 [2021-12-15 17:21:49,201 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1914 [2021-12-15 17:21:49,201 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1914 states and 2824 transitions. [2021-12-15 17:21:49,202 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:21:49,202 INFO L681 BuchiCegarLoop]: Abstraction has 1914 states and 2824 transitions. [2021-12-15 17:21:49,204 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1914 states and 2824 transitions. [2021-12-15 17:21:49,219 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1914 to 1914. [2021-12-15 17:21:49,221 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1914 states, 1914 states have (on average 1.4754440961337514) internal successors, (2824), 1913 states have internal predecessors, (2824), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:49,224 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1914 states to 1914 states and 2824 transitions. [2021-12-15 17:21:49,224 INFO L704 BuchiCegarLoop]: Abstraction has 1914 states and 2824 transitions. [2021-12-15 17:21:49,224 INFO L587 BuchiCegarLoop]: Abstraction has 1914 states and 2824 transitions. [2021-12-15 17:21:49,224 INFO L425 BuchiCegarLoop]: ======== Iteration 13============ [2021-12-15 17:21:49,224 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1914 states and 2824 transitions. [2021-12-15 17:21:49,228 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2021-12-15 17:21:49,228 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:21:49,228 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:21:49,230 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:49,230 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:49,230 INFO L791 eck$LassoCheckResult]: Stem: 46894#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 46895#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 46714#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 46430#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 46431#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 47607#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 47608#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 46566#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 46567#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 47025#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 46856#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 46857#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 46633#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 46634#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 47032#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 47209#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 47363#L936-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 47400#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 46646#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 46647#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 47820#L1258-2 assume !(0 == ~T1_E~0); 46939#L1263-1 assume !(0 == ~T2_E~0); 46940#L1268-1 assume !(0 == ~T3_E~0); 47243#L1273-1 assume !(0 == ~T4_E~0); 47802#L1278-1 assume !(0 == ~T5_E~0); 47663#L1283-1 assume !(0 == ~T6_E~0); 47664#L1288-1 assume !(0 == ~T7_E~0); 47900#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 47888#L1298-1 assume !(0 == ~T9_E~0); 47814#L1303-1 assume !(0 == ~T10_E~0); 46459#L1308-1 assume !(0 == ~T11_E~0); 46401#L1313-1 assume !(0 == ~T12_E~0); 46402#L1318-1 assume !(0 == ~T13_E~0); 46410#L1323-1 assume !(0 == ~E_1~0); 46411#L1328-1 assume !(0 == ~E_2~0); 46576#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 47535#L1338-1 assume !(0 == ~E_4~0); 47536#L1343-1 assume !(0 == ~E_5~0); 47637#L1348-1 assume !(0 == ~E_6~0); 47923#L1353-1 assume !(0 == ~E_7~0); 47262#L1358-1 assume !(0 == ~E_8~0); 47263#L1363-1 assume !(0 == ~E_9~0); 47553#L1368-1 assume !(0 == ~E_10~0); 46238#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 46239#L1378-1 assume !(0 == ~E_12~0); 46527#L1383-1 assume !(0 == ~E_13~0); 46528#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 47269#L607 assume 1 == ~m_pc~0; 47270#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 46596#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 47635#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 47189#L1560 assume !(0 != activate_threads_~tmp~1#1); 47190#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 46421#L626 assume !(1 == ~t1_pc~0); 46422#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 46690#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 46691#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 46860#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 46323#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 46324#L645 assume 1 == ~t2_pc~0; 46438#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 46395#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 47075#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 47076#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 47165#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 47166#L664 assume 1 == ~t3_pc~0; 47922#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 46164#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 46165#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 46821#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 46822#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 47830#L683 assume !(1 == ~t4_pc~0); 47385#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 47337#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 47338#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 47372#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 47496#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 47119#L702 assume 1 == ~t5_pc~0; 47120#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 47042#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 47491#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 47790#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 47731#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 46210#L721 assume !(1 == ~t6_pc~0); 46184#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 46185#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 46348#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 46830#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 46831#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 47432#L740 assume 1 == ~t7_pc~0; 46259#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 46072#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 46073#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 46062#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 46063#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 46767#L759 assume !(1 == ~t8_pc~0); 46768#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 46796#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 47489#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 47490#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 47621#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 47899#L778 assume 1 == ~t9_pc~0; 47786#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 46237#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 46177#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 46106#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 46107#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 46435#L797 assume !(1 == ~t10_pc~0); 46436#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 46553#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 47687#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 46937#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 46938#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 47227#L816 assume 1 == ~t11_pc~0; 46142#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 46143#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 46900#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 46837#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 46838#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 47362#L835 assume 1 == ~t12_pc~0; 47240#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 46306#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 46328#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 46469#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 46994#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 46995#L854 assume !(1 == ~t13_pc~0); 46635#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 46636#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 46686#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 46346#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 46347#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 47726#L1401 assume !(1 == ~M_E~0); 46825#L1401-2 assume !(1 == ~T1_E~0); 46826#L1406-1 assume !(1 == ~T2_E~0); 47421#L1411-1 assume !(1 == ~T3_E~0); 47422#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 47088#L1421-1 assume !(1 == ~T5_E~0); 46631#L1426-1 assume !(1 == ~T6_E~0); 46632#L1431-1 assume !(1 == ~T7_E~0); 46180#L1436-1 assume !(1 == ~T8_E~0); 46181#L1441-1 assume !(1 == ~T9_E~0); 46930#L1446-1 assume !(1 == ~T10_E~0); 46931#L1451-1 assume !(1 == ~T11_E~0); 47634#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 47288#L1461-1 assume !(1 == ~T13_E~0); 46849#L1466-1 assume !(1 == ~E_1~0); 46850#L1471-1 assume !(1 == ~E_2~0); 47619#L1476-1 assume !(1 == ~E_3~0); 47620#L1481-1 assume !(1 == ~E_4~0); 47768#L1486-1 assume !(1 == ~E_5~0); 46474#L1491-1 assume !(1 == ~E_6~0); 46114#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 46115#L1501-1 assume !(1 == ~E_8~0); 46926#L1506-1 assume !(1 == ~E_9~0); 46927#L1511-1 assume !(1 == ~E_10~0); 46883#L1516-1 assume !(1 == ~E_11~0); 46060#L1521-1 assume !(1 == ~E_12~0); 46061#L1526-1 assume !(1 == ~E_13~0); 46113#L1531-1 assume { :end_inline_reset_delta_events } true; 46656#L1892-2 [2021-12-15 17:21:49,230 INFO L793 eck$LassoCheckResult]: Loop: 46656#L1892-2 assume !false; 47679#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 47877#L1233 assume !false; 47860#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 47192#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 47172#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 47330#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 46156#L1046 assume !(0 != eval_~tmp~0#1); 46158#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 46192#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 47364#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 47921#L1258-5 assume !(0 == ~T1_E~0); 46336#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 46337#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 47913#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 47919#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 47920#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 46560#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 46561#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 47676#L1298-3 assume !(0 == ~T9_E~0); 47677#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 47836#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 47675#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 47176#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 46338#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 46339#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 47760#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 46479#L1338-3 assume !(0 == ~E_4~0); 46480#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 47592#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 47766#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 47767#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 47134#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 46692#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 46693#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 47449#L1378-3 assume !(0 == ~E_12~0); 47450#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 47631#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 47632#L607-42 assume !(1 == ~m_pc~0); 47248#L607-44 is_master_triggered_~__retres1~0#1 := 0; 46973#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 46974#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 46706#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 46707#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 47231#L626-42 assume 1 == ~t1_pc~0; 46793#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 46794#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 47095#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 47096#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 46370#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 46371#L645-42 assume !(1 == ~t2_pc~0); 47570#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 47571#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 47736#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 46577#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 46084#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 46085#L664-42 assume !(1 == ~t3_pc~0); 46608#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 46609#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 47863#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 47398#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 47399#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 47564#L683-42 assume !(1 == ~t4_pc~0); 47271#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 47272#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 47404#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 47825#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 47826#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 47670#L702-42 assume 1 == ~t5_pc~0; 47158#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 46782#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 47079#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 47752#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 46098#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 46099#L721-42 assume 1 == ~t6_pc~0; 46254#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 46274#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 46738#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 47905#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 46910#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 46756#L740-42 assume 1 == ~t7_pc~0; 46757#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 46494#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 47035#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 46890#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 46891#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 47164#L759-42 assume 1 == ~t8_pc~0; 47013#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 46945#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 46946#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 47023#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 47024#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 47118#L778-42 assume 1 == ~t9_pc~0; 46957#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 46959#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 47368#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 47273#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 47274#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 47332#L797-42 assume 1 == ~t10_pc~0; 46499#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 46500#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 47501#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 47810#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 47370#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 47371#L816-42 assume 1 == ~t11_pc~0; 46048#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 46049#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 46591#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 46592#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 46671#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 46672#L835-42 assume 1 == ~t12_pc~0; 47074#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 46966#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 46644#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 46645#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 47729#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 47513#L854-42 assume 1 == ~t13_pc~0; 47514#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 46588#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 46200#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 46201#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 46847#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 46848#L1401-3 assume !(1 == ~M_E~0); 47626#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 46434#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 46301#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 46302#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 46901#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 46902#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 46477#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 46478#L1436-3 assume !(1 == ~T8_E~0); 46064#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 46065#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 47654#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 46985#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 46638#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 46639#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 47916#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 46578#L1476-3 assume !(1 == ~E_3~0); 46579#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 46979#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 46606#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 46607#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 47018#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 47019#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 47446#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 47436#L1516-3 assume !(1 == ~E_11~0); 47437#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 47136#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 47137#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 47531#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 46413#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 47306#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 46947#L1911 assume !(0 == start_simulation_~tmp~3#1); 46948#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 47470#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 46538#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 47408#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 46242#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 46243#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 46472#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 46473#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 46656#L1892-2 [2021-12-15 17:21:49,231 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:49,231 INFO L85 PathProgramCache]: Analyzing trace with hash 855086876, now seen corresponding path program 1 times [2021-12-15 17:21:49,231 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:49,231 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [684356371] [2021-12-15 17:21:49,231 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:49,231 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:49,239 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:49,261 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:49,261 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:49,261 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [684356371] [2021-12-15 17:21:49,262 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [684356371] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:49,262 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:49,262 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:49,262 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1150168171] [2021-12-15 17:21:49,262 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:49,262 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:21:49,263 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:49,263 INFO L85 PathProgramCache]: Analyzing trace with hash -505772015, now seen corresponding path program 1 times [2021-12-15 17:21:49,263 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:49,263 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1005912597] [2021-12-15 17:21:49,263 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:49,263 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:49,271 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:49,287 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:49,287 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:49,287 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1005912597] [2021-12-15 17:21:49,287 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1005912597] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:49,288 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:49,288 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:49,288 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [127978818] [2021-12-15 17:21:49,288 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:49,288 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:21:49,288 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:21:49,289 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:21:49,289 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:21:49,289 INFO L87 Difference]: Start difference. First operand 1914 states and 2824 transitions. cyclomatic complexity: 911 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:49,306 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:21:49,306 INFO L93 Difference]: Finished difference Result 1914 states and 2823 transitions. [2021-12-15 17:21:49,306 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:21:49,307 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1914 states and 2823 transitions. [2021-12-15 17:21:49,312 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2021-12-15 17:21:49,316 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1914 states to 1914 states and 2823 transitions. [2021-12-15 17:21:49,316 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1914 [2021-12-15 17:21:49,317 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1914 [2021-12-15 17:21:49,317 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1914 states and 2823 transitions. [2021-12-15 17:21:49,319 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:21:49,319 INFO L681 BuchiCegarLoop]: Abstraction has 1914 states and 2823 transitions. [2021-12-15 17:21:49,321 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1914 states and 2823 transitions. [2021-12-15 17:21:49,335 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1914 to 1914. [2021-12-15 17:21:49,337 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1914 states, 1914 states have (on average 1.474921630094044) internal successors, (2823), 1913 states have internal predecessors, (2823), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:49,340 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1914 states to 1914 states and 2823 transitions. [2021-12-15 17:21:49,340 INFO L704 BuchiCegarLoop]: Abstraction has 1914 states and 2823 transitions. [2021-12-15 17:21:49,340 INFO L587 BuchiCegarLoop]: Abstraction has 1914 states and 2823 transitions. [2021-12-15 17:21:49,340 INFO L425 BuchiCegarLoop]: ======== Iteration 14============ [2021-12-15 17:21:49,340 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1914 states and 2823 transitions. [2021-12-15 17:21:49,344 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2021-12-15 17:21:49,344 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:21:49,344 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:21:49,346 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:49,346 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:49,346 INFO L791 eck$LassoCheckResult]: Stem: 50729#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 50730#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 50549#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 50265#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 50266#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 51442#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 51443#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 50401#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 50402#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 50858#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 50691#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 50692#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 50468#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 50469#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 50867#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 51044#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 51198#L936-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 51235#L941-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 50481#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 50482#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 51655#L1258-2 assume !(0 == ~T1_E~0); 50774#L1263-1 assume !(0 == ~T2_E~0); 50775#L1268-1 assume !(0 == ~T3_E~0); 51078#L1273-1 assume !(0 == ~T4_E~0); 51637#L1278-1 assume !(0 == ~T5_E~0); 51498#L1283-1 assume !(0 == ~T6_E~0); 51499#L1288-1 assume !(0 == ~T7_E~0); 51735#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 51723#L1298-1 assume !(0 == ~T9_E~0); 51649#L1303-1 assume !(0 == ~T10_E~0); 50294#L1308-1 assume !(0 == ~T11_E~0); 50236#L1313-1 assume !(0 == ~T12_E~0); 50237#L1318-1 assume !(0 == ~T13_E~0); 50245#L1323-1 assume !(0 == ~E_1~0); 50246#L1328-1 assume !(0 == ~E_2~0); 50411#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 51370#L1338-1 assume !(0 == ~E_4~0); 51371#L1343-1 assume !(0 == ~E_5~0); 51472#L1348-1 assume !(0 == ~E_6~0); 51758#L1353-1 assume !(0 == ~E_7~0); 51097#L1358-1 assume !(0 == ~E_8~0); 51098#L1363-1 assume !(0 == ~E_9~0); 51388#L1368-1 assume !(0 == ~E_10~0); 50073#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 50074#L1378-1 assume !(0 == ~E_12~0); 50362#L1383-1 assume !(0 == ~E_13~0); 50363#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 51104#L607 assume 1 == ~m_pc~0; 51105#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 50431#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 51470#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 51024#L1560 assume !(0 != activate_threads_~tmp~1#1); 51025#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 50256#L626 assume !(1 == ~t1_pc~0); 50257#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 50525#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 50526#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 50695#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 50156#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 50157#L645 assume 1 == ~t2_pc~0; 50273#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 50230#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 50910#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 50911#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 51000#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 51001#L664 assume 1 == ~t3_pc~0; 51757#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 49997#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 49998#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 50656#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 50657#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 51665#L683 assume !(1 == ~t4_pc~0); 51220#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 51172#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 51173#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 51207#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 51331#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 50954#L702 assume 1 == ~t5_pc~0; 50955#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 50877#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 51326#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 51625#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 51566#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 50045#L721 assume !(1 == ~t6_pc~0); 50019#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 50020#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 50183#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 50665#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 50666#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 51267#L740 assume 1 == ~t7_pc~0; 50094#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 49907#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 49908#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 49897#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 49898#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 50602#L759 assume !(1 == ~t8_pc~0); 50603#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 50631#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 51324#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 51325#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 51456#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 51734#L778 assume 1 == ~t9_pc~0; 51621#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 50072#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 50012#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 49941#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 49942#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 50270#L797 assume !(1 == ~t10_pc~0); 50271#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 50388#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 51522#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 50772#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 50773#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 51062#L816 assume 1 == ~t11_pc~0; 49977#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 49978#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 50735#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 50672#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 50673#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 51197#L835 assume 1 == ~t12_pc~0; 51075#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 50141#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 50163#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 50304#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 50829#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 50830#L854 assume !(1 == ~t13_pc~0); 50470#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 50471#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 50521#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 50181#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 50182#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 51561#L1401 assume !(1 == ~M_E~0); 50660#L1401-2 assume !(1 == ~T1_E~0); 50661#L1406-1 assume !(1 == ~T2_E~0); 51256#L1411-1 assume !(1 == ~T3_E~0); 51257#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 50923#L1421-1 assume !(1 == ~T5_E~0); 50466#L1426-1 assume !(1 == ~T6_E~0); 50467#L1431-1 assume !(1 == ~T7_E~0); 50015#L1436-1 assume !(1 == ~T8_E~0); 50016#L1441-1 assume !(1 == ~T9_E~0); 50765#L1446-1 assume !(1 == ~T10_E~0); 50766#L1451-1 assume !(1 == ~T11_E~0); 51469#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 51123#L1461-1 assume !(1 == ~T13_E~0); 50684#L1466-1 assume !(1 == ~E_1~0); 50685#L1471-1 assume !(1 == ~E_2~0); 51454#L1476-1 assume !(1 == ~E_3~0); 51455#L1481-1 assume !(1 == ~E_4~0); 51603#L1486-1 assume !(1 == ~E_5~0); 50309#L1491-1 assume !(1 == ~E_6~0); 49949#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 49950#L1501-1 assume !(1 == ~E_8~0); 50761#L1506-1 assume !(1 == ~E_9~0); 50762#L1511-1 assume !(1 == ~E_10~0); 50718#L1516-1 assume !(1 == ~E_11~0); 49893#L1521-1 assume !(1 == ~E_12~0); 49894#L1526-1 assume !(1 == ~E_13~0); 49948#L1531-1 assume { :end_inline_reset_delta_events } true; 50491#L1892-2 [2021-12-15 17:21:49,347 INFO L793 eck$LassoCheckResult]: Loop: 50491#L1892-2 assume !false; 51514#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 51712#L1233 assume !false; 51695#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 51027#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 51007#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 51165#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 49991#L1046 assume !(0 != eval_~tmp~0#1); 49993#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 50027#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 51199#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 51756#L1258-5 assume !(0 == ~T1_E~0); 50169#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 50170#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 51748#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 51754#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 51755#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 50393#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 50394#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 51511#L1298-3 assume !(0 == ~T9_E~0); 51512#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 51671#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 51510#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 51011#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 50171#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 50172#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 51595#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 50314#L1338-3 assume !(0 == ~E_4~0); 50315#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 51427#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 51601#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 51602#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 50969#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 50527#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 50528#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 51284#L1378-3 assume !(0 == ~E_12~0); 51285#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 51466#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 51467#L607-42 assume 1 == ~m_pc~0; 51082#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 50808#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 50809#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 50541#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 50542#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 51066#L626-42 assume 1 == ~t1_pc~0; 50628#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 50629#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 50930#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 50931#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 50205#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 50206#L645-42 assume 1 == ~t2_pc~0; 51664#L646-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 51406#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 51571#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 50412#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 49919#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 49920#L664-42 assume 1 == ~t3_pc~0; 50724#L665-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 50448#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 51698#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 51233#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 51234#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 51399#L683-42 assume 1 == ~t4_pc~0; 51764#L684-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 51110#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 51240#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 51660#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 51661#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 51508#L702-42 assume 1 == ~t5_pc~0; 50996#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 50618#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 50916#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 51587#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 49933#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 49934#L721-42 assume 1 == ~t6_pc~0; 50088#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 50109#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 50573#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 51740#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 50745#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 50589#L740-42 assume !(1 == ~t7_pc~0); 50325#L740-44 is_transmit7_triggered_~__retres1~7#1 := 0; 50326#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 50870#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 50725#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 50726#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 50999#L759-42 assume 1 == ~t8_pc~0; 50848#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 50780#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 50781#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 50856#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 50857#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 50953#L778-42 assume 1 == ~t9_pc~0; 50792#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 50794#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 51202#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 51106#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 51107#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 51167#L797-42 assume !(1 == ~t10_pc~0); 50336#L797-44 is_transmit10_triggered_~__retres1~10#1 := 0; 50335#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 51336#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 51645#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 51205#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 51206#L816-42 assume 1 == ~t11_pc~0; 49883#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 49884#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 50426#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 50427#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 50506#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 50507#L835-42 assume !(1 == ~t12_pc~0); 50800#L835-44 is_transmit12_triggered_~__retres1~12#1 := 0; 50801#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 50479#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 50480#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 51564#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 51348#L854-42 assume 1 == ~t13_pc~0; 51349#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 50423#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 50035#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 50036#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 50682#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 50683#L1401-3 assume !(1 == ~M_E~0); 51461#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 50269#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 50136#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 50137#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 50736#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 50737#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 50312#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 50313#L1436-3 assume !(1 == ~T8_E~0); 49899#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 49900#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 51489#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 50820#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 50473#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 50474#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 51751#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 50413#L1476-3 assume !(1 == ~E_3~0); 50414#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 50814#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 50441#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 50442#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 50853#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 50854#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 51281#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 51270#L1516-3 assume !(1 == ~E_11~0); 51271#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 50971#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 50972#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 51366#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 50248#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 51141#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 50782#L1911 assume !(0 == start_simulation_~tmp~3#1); 50783#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 51305#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 50373#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 51243#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 50077#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 50078#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 50307#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 50308#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 50491#L1892-2 [2021-12-15 17:21:49,347 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:49,347 INFO L85 PathProgramCache]: Analyzing trace with hash 1395516382, now seen corresponding path program 1 times [2021-12-15 17:21:49,347 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:49,347 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [973984879] [2021-12-15 17:21:49,348 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:49,348 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:49,356 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:49,370 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:49,371 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:49,371 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [973984879] [2021-12-15 17:21:49,371 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [973984879] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:49,371 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:49,371 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-15 17:21:49,371 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [859345122] [2021-12-15 17:21:49,371 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:49,372 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:21:49,372 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:49,372 INFO L85 PathProgramCache]: Analyzing trace with hash -118340366, now seen corresponding path program 1 times [2021-12-15 17:21:49,372 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:49,372 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [996725667] [2021-12-15 17:21:49,372 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:49,373 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:49,380 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:49,395 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:49,395 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:49,395 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [996725667] [2021-12-15 17:21:49,395 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [996725667] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:49,395 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:49,395 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:49,396 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1920680065] [2021-12-15 17:21:49,396 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:49,396 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:21:49,396 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:21:49,396 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-15 17:21:49,396 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-15 17:21:49,397 INFO L87 Difference]: Start difference. First operand 1914 states and 2823 transitions. cyclomatic complexity: 910 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 2 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:49,481 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:21:49,481 INFO L93 Difference]: Finished difference Result 3555 states and 5213 transitions. [2021-12-15 17:21:49,481 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-15 17:21:49,481 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3555 states and 5213 transitions. [2021-12-15 17:21:49,491 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3382 [2021-12-15 17:21:49,498 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3555 states to 3555 states and 5213 transitions. [2021-12-15 17:21:49,498 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3555 [2021-12-15 17:21:49,500 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3555 [2021-12-15 17:21:49,500 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3555 states and 5213 transitions. [2021-12-15 17:21:49,503 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:21:49,503 INFO L681 BuchiCegarLoop]: Abstraction has 3555 states and 5213 transitions. [2021-12-15 17:21:49,505 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3555 states and 5213 transitions. [2021-12-15 17:21:49,536 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3555 to 3555. [2021-12-15 17:21:49,539 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3555 states, 3555 states have (on average 1.4663853727144867) internal successors, (5213), 3554 states have internal predecessors, (5213), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:49,544 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3555 states to 3555 states and 5213 transitions. [2021-12-15 17:21:49,545 INFO L704 BuchiCegarLoop]: Abstraction has 3555 states and 5213 transitions. [2021-12-15 17:21:49,545 INFO L587 BuchiCegarLoop]: Abstraction has 3555 states and 5213 transitions. [2021-12-15 17:21:49,545 INFO L425 BuchiCegarLoop]: ======== Iteration 15============ [2021-12-15 17:21:49,545 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3555 states and 5213 transitions. [2021-12-15 17:21:49,552 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3382 [2021-12-15 17:21:49,552 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:21:49,552 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:21:49,554 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:49,554 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:49,554 INFO L791 eck$LassoCheckResult]: Stem: 56208#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 56209#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 56027#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 55741#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 55742#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 56940#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 56941#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 55878#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 55879#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 56337#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 56170#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 56171#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 55946#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 55947#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 56348#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 56531#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 56683#L936-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 56722#L941-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 55957#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 55958#L1258 assume !(0 == ~M_E~0); 57173#L1258-2 assume !(0 == ~T1_E~0); 56254#L1263-1 assume !(0 == ~T2_E~0); 56255#L1268-1 assume !(0 == ~T3_E~0); 56565#L1273-1 assume !(0 == ~T4_E~0); 57152#L1278-1 assume !(0 == ~T5_E~0); 57000#L1283-1 assume !(0 == ~T6_E~0); 57001#L1288-1 assume !(0 == ~T7_E~0); 57267#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 57255#L1298-1 assume !(0 == ~T9_E~0); 57165#L1303-1 assume !(0 == ~T10_E~0); 55770#L1308-1 assume !(0 == ~T11_E~0); 55712#L1313-1 assume !(0 == ~T12_E~0); 55713#L1318-1 assume !(0 == ~T13_E~0); 55719#L1323-1 assume !(0 == ~E_1~0); 55720#L1328-1 assume !(0 == ~E_2~0); 55889#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 56863#L1338-1 assume !(0 == ~E_4~0); 56864#L1343-1 assume !(0 == ~E_5~0); 56972#L1348-1 assume !(0 == ~E_6~0); 57295#L1353-1 assume !(0 == ~E_7~0); 56584#L1358-1 assume !(0 == ~E_8~0); 56585#L1363-1 assume !(0 == ~E_9~0); 56882#L1368-1 assume !(0 == ~E_10~0); 55549#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 55550#L1378-1 assume !(0 == ~E_12~0); 55837#L1383-1 assume !(0 == ~E_13~0); 55838#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 56590#L607 assume !(1 == ~m_pc~0); 55908#L607-2 is_master_triggered_~__retres1~0#1 := 0; 55909#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 56970#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 56509#L1560 assume !(0 != activate_threads_~tmp~1#1); 56510#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 55732#L626 assume !(1 == ~t1_pc~0); 55733#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 56003#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 56004#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 56174#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 55632#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 55633#L645 assume 1 == ~t2_pc~0; 55749#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 55706#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 56389#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 56390#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 56485#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 56486#L664 assume 1 == ~t3_pc~0; 57293#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 55473#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 55474#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 56135#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 56136#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 57183#L683 assume !(1 == ~t4_pc~0); 56707#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 56657#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 56658#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 56693#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 56822#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 56432#L702 assume 1 == ~t5_pc~0; 56433#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 56358#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 56817#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 57137#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 57072#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 55521#L721 assume !(1 == ~t6_pc~0); 55495#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 55496#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 55659#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 56144#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 56145#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 56755#L740 assume 1 == ~t7_pc~0; 55570#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 55383#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 55384#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 55373#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 55374#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 56079#L759 assume !(1 == ~t8_pc~0); 56080#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 56110#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 56815#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 56816#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 56955#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 57266#L778 assume 1 == ~t9_pc~0; 57134#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 55548#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 55488#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 55417#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 55418#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 55745#L797 assume !(1 == ~t10_pc~0); 55746#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 55865#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 57027#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 56252#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 56253#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 56549#L816 assume 1 == ~t11_pc~0; 55453#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 55454#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 56212#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 56151#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 56152#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 56682#L835 assume 1 == ~t12_pc~0; 56562#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 55617#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 55639#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 55780#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 56310#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 56311#L854 assume !(1 == ~t13_pc~0); 55948#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 55949#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 55999#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 55657#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 55658#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 57067#L1401 assume !(1 == ~M_E~0); 56139#L1401-2 assume !(1 == ~T1_E~0); 56140#L1406-1 assume !(1 == ~T2_E~0); 56744#L1411-1 assume !(1 == ~T3_E~0); 56745#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 56405#L1421-1 assume !(1 == ~T5_E~0); 55944#L1426-1 assume !(1 == ~T6_E~0); 55945#L1431-1 assume !(1 == ~T7_E~0); 55491#L1436-1 assume !(1 == ~T8_E~0); 55492#L1441-1 assume !(1 == ~T9_E~0); 56243#L1446-1 assume !(1 == ~T10_E~0); 56244#L1451-1 assume !(1 == ~T11_E~0); 56969#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 56609#L1461-1 assume !(1 == ~T13_E~0); 56163#L1466-1 assume !(1 == ~E_1~0); 56164#L1471-1 assume !(1 == ~E_2~0); 56953#L1476-1 assume !(1 == ~E_3~0); 56954#L1481-1 assume !(1 == ~E_4~0); 57115#L1486-1 assume !(1 == ~E_5~0); 55785#L1491-1 assume !(1 == ~E_6~0); 55425#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 55426#L1501-1 assume !(1 == ~E_8~0); 56241#L1506-1 assume !(1 == ~E_9~0); 56242#L1511-1 assume !(1 == ~E_10~0); 56197#L1516-1 assume !(1 == ~E_11~0); 55369#L1521-1 assume !(1 == ~E_12~0); 55370#L1526-1 assume !(1 == ~E_13~0); 55424#L1531-1 assume { :end_inline_reset_delta_events } true; 55969#L1892-2 [2021-12-15 17:21:49,554 INFO L793 eck$LassoCheckResult]: Loop: 55969#L1892-2 assume !false; 57386#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 57384#L1233 assume !false; 57218#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 56512#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 56492#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 56650#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 55467#L1046 assume !(0 != eval_~tmp~0#1); 55469#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 58593#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 58592#L1258-3 assume !(0 == ~M_E~0); 57333#L1258-5 assume !(0 == ~T1_E~0); 55645#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 55646#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 57281#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 57288#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 57289#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 55870#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 55871#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 57013#L1298-3 assume !(0 == ~T9_E~0); 57014#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 57190#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 57012#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 56496#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 55647#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 55648#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 57106#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 55790#L1338-3 assume !(0 == ~E_4~0); 55791#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 56923#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 57112#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 57113#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 56450#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 56005#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 56006#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 56775#L1378-3 assume !(0 == ~E_12~0); 56776#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 56966#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 56967#L607-42 assume !(1 == ~m_pc~0); 56568#L607-44 is_master_triggered_~__retres1~0#1 := 0; 58412#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 58411#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 58410#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 58409#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 58408#L626-42 assume 1 == ~t1_pc~0; 58406#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 58405#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 58404#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 58403#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 58402#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 58401#L645-42 assume 1 == ~t2_pc~0; 58400#L646-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 58398#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 58397#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 58396#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 58395#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 58394#L664-42 assume 1 == ~t3_pc~0; 58392#L665-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 58391#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 58390#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 58389#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 58388#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 58387#L683-42 assume !(1 == ~t4_pc~0); 58385#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 58384#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 58383#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 58382#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 58381#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 58380#L702-42 assume 1 == ~t5_pc~0; 58378#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 58377#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 58376#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 58375#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 58374#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 58373#L721-42 assume 1 == ~t6_pc~0; 58371#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 58370#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 58369#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 58368#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 58367#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 58366#L740-42 assume 1 == ~t7_pc~0; 58364#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 58363#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 58362#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 58361#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 58360#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 58359#L759-42 assume 1 == ~t8_pc~0; 58357#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 58356#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 58355#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 58354#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 58353#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 58352#L778-42 assume 1 == ~t9_pc~0; 56272#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 56274#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 58350#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 58348#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 58345#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 58343#L797-42 assume 1 == ~t10_pc~0; 58340#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 56827#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 56828#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 57161#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 57331#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 58327#L816-42 assume !(1 == ~t11_pc~0); 58323#L816-44 is_transmit11_triggered_~__retres1~11#1 := 0; 58321#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 58320#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 58319#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 58318#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 58317#L835-42 assume 1 == ~t12_pc~0; 58315#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 58314#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 58313#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 58312#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 58311#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 58310#L854-42 assume !(1 == ~t13_pc~0); 58308#L854-44 is_transmit13_triggered_~__retres1~13#1 := 0; 58307#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 58306#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 58305#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 58304#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 57326#L1401-3 assume !(1 == ~M_E~0); 57327#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 58805#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 58096#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 58095#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 58093#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 58090#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 58088#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 58086#L1436-3 assume !(1 == ~T8_E~0); 58084#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 58082#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 58080#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 58077#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 58075#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 58073#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 58071#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 58070#L1476-3 assume !(1 == ~E_3~0); 58069#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 58068#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 58067#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 58066#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 58065#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 58064#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 58063#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 58062#L1516-3 assume !(1 == ~E_11~0); 58061#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 58060#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 58059#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 57867#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 57332#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 56626#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 56262#L1911 assume !(0 == start_simulation_~tmp~3#1); 56263#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 57473#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 57458#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 57455#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 57453#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 57451#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 57449#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 57447#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 55969#L1892-2 [2021-12-15 17:21:49,555 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:49,555 INFO L85 PathProgramCache]: Analyzing trace with hash -1486214853, now seen corresponding path program 1 times [2021-12-15 17:21:49,555 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:49,555 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1932817548] [2021-12-15 17:21:49,555 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:49,556 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:49,562 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:49,576 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:49,577 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:49,577 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1932817548] [2021-12-15 17:21:49,577 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1932817548] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:49,577 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:49,577 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:49,577 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1627548636] [2021-12-15 17:21:49,577 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:49,578 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:21:49,578 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:49,578 INFO L85 PathProgramCache]: Analyzing trace with hash 1909928847, now seen corresponding path program 1 times [2021-12-15 17:21:49,578 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:49,578 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1298629457] [2021-12-15 17:21:49,578 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:49,579 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:49,586 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:49,602 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:49,603 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:49,603 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1298629457] [2021-12-15 17:21:49,603 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1298629457] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:49,603 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:49,603 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:49,603 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [693919110] [2021-12-15 17:21:49,603 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:49,604 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:21:49,604 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:21:49,604 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-15 17:21:49,604 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-15 17:21:49,604 INFO L87 Difference]: Start difference. First operand 3555 states and 5213 transitions. cyclomatic complexity: 1659 Second operand has 4 states, 4 states have (on average 39.75) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:49,736 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:21:49,736 INFO L93 Difference]: Finished difference Result 5188 states and 7586 transitions. [2021-12-15 17:21:49,736 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-15 17:21:49,737 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5188 states and 7586 transitions. [2021-12-15 17:21:49,755 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4996 [2021-12-15 17:21:49,770 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5188 states to 5188 states and 7586 transitions. [2021-12-15 17:21:49,771 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5188 [2021-12-15 17:21:49,774 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5188 [2021-12-15 17:21:49,774 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5188 states and 7586 transitions. [2021-12-15 17:21:49,780 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:21:49,780 INFO L681 BuchiCegarLoop]: Abstraction has 5188 states and 7586 transitions. [2021-12-15 17:21:49,786 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5188 states and 7586 transitions. [2021-12-15 17:21:49,834 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5188 to 3555. [2021-12-15 17:21:49,838 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3555 states, 3555 states have (on average 1.4655414908579465) internal successors, (5210), 3554 states have internal predecessors, (5210), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:49,843 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3555 states to 3555 states and 5210 transitions. [2021-12-15 17:21:49,844 INFO L704 BuchiCegarLoop]: Abstraction has 3555 states and 5210 transitions. [2021-12-15 17:21:49,844 INFO L587 BuchiCegarLoop]: Abstraction has 3555 states and 5210 transitions. [2021-12-15 17:21:49,844 INFO L425 BuchiCegarLoop]: ======== Iteration 16============ [2021-12-15 17:21:49,844 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3555 states and 5210 transitions. [2021-12-15 17:21:49,850 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3382 [2021-12-15 17:21:49,850 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:21:49,850 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:21:49,852 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:49,852 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:49,852 INFO L791 eck$LassoCheckResult]: Stem: 64958#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 64959#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 64778#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 64493#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 64494#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 65672#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 65673#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 64630#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 64631#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 65086#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 64920#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 64921#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 64697#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 64698#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 65097#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 65274#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 65426#L936-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 65463#L941-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 64708#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 64709#L1258 assume !(0 == ~M_E~0); 65888#L1258-2 assume !(0 == ~T1_E~0); 65004#L1263-1 assume !(0 == ~T2_E~0); 65005#L1268-1 assume !(0 == ~T3_E~0); 65308#L1273-1 assume !(0 == ~T4_E~0); 65870#L1278-1 assume !(0 == ~T5_E~0); 65728#L1283-1 assume !(0 == ~T6_E~0); 65729#L1288-1 assume !(0 == ~T7_E~0); 65969#L1293-1 assume !(0 == ~T8_E~0); 65957#L1298-1 assume !(0 == ~T9_E~0); 65882#L1303-1 assume !(0 == ~T10_E~0); 64522#L1308-1 assume !(0 == ~T11_E~0); 64464#L1313-1 assume !(0 == ~T12_E~0); 64465#L1318-1 assume !(0 == ~T13_E~0); 64471#L1323-1 assume !(0 == ~E_1~0); 64472#L1328-1 assume !(0 == ~E_2~0); 64640#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 65599#L1338-1 assume !(0 == ~E_4~0); 65600#L1343-1 assume !(0 == ~E_5~0); 65702#L1348-1 assume !(0 == ~E_6~0); 65993#L1353-1 assume !(0 == ~E_7~0); 65327#L1358-1 assume !(0 == ~E_8~0); 65328#L1363-1 assume !(0 == ~E_9~0); 65617#L1368-1 assume !(0 == ~E_10~0); 64301#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 64302#L1378-1 assume !(0 == ~E_12~0); 64589#L1383-1 assume !(0 == ~E_13~0); 64590#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 65333#L607 assume !(1 == ~m_pc~0); 64659#L607-2 is_master_triggered_~__retres1~0#1 := 0; 64660#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 65700#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 65254#L1560 assume !(0 != activate_threads_~tmp~1#1); 65255#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 64484#L626 assume !(1 == ~t1_pc~0); 64485#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 64754#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 64755#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 64924#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 64384#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 64385#L645 assume 1 == ~t2_pc~0; 64501#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 64458#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 65137#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 65138#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 65230#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 65231#L664 assume 1 == ~t3_pc~0; 65992#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 64226#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 64227#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 64885#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 64886#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 65898#L683 assume !(1 == ~t4_pc~0); 65448#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 65400#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 65401#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 65435#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 65560#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 65180#L702 assume 1 == ~t5_pc~0; 65181#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 65106#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 65555#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 65855#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 65796#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 64273#L721 assume !(1 == ~t6_pc~0); 64248#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 64249#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 64411#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 64894#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 64895#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 65496#L740 assume 1 == ~t7_pc~0; 64322#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 64136#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 64137#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 64126#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 64127#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 64830#L759 assume !(1 == ~t8_pc~0); 64831#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 64860#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 65553#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 65554#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 65686#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 65968#L778 assume 1 == ~t9_pc~0; 65852#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 64300#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 64241#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 64170#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 64171#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 64497#L797 assume !(1 == ~t10_pc~0); 64498#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 64617#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 65752#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 65002#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 65003#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 65292#L816 assume 1 == ~t11_pc~0; 64206#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 64207#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 64962#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 64901#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 64902#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 65425#L835 assume 1 == ~t12_pc~0; 65305#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 64369#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 64391#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 64532#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 65059#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 65060#L854 assume !(1 == ~t13_pc~0); 64699#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 64700#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 64750#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 64409#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 64410#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 65791#L1401 assume !(1 == ~M_E~0); 64889#L1401-2 assume !(1 == ~T1_E~0); 64890#L1406-1 assume !(1 == ~T2_E~0); 65485#L1411-1 assume !(1 == ~T3_E~0); 65486#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 65153#L1421-1 assume !(1 == ~T5_E~0); 64695#L1426-1 assume !(1 == ~T6_E~0); 64696#L1431-1 assume !(1 == ~T7_E~0); 64244#L1436-1 assume !(1 == ~T8_E~0); 64245#L1441-1 assume !(1 == ~T9_E~0); 64993#L1446-1 assume !(1 == ~T10_E~0); 64994#L1451-1 assume !(1 == ~T11_E~0); 65699#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 65351#L1461-1 assume !(1 == ~T13_E~0); 64913#L1466-1 assume !(1 == ~E_1~0); 64914#L1471-1 assume !(1 == ~E_2~0); 65684#L1476-1 assume !(1 == ~E_3~0); 65685#L1481-1 assume !(1 == ~E_4~0); 65834#L1486-1 assume !(1 == ~E_5~0); 64537#L1491-1 assume !(1 == ~E_6~0); 64178#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 64179#L1501-1 assume !(1 == ~E_8~0); 64991#L1506-1 assume !(1 == ~E_9~0); 64992#L1511-1 assume !(1 == ~E_10~0); 64947#L1516-1 assume !(1 == ~E_11~0); 64122#L1521-1 assume !(1 == ~E_12~0); 64123#L1526-1 assume !(1 == ~E_13~0); 64177#L1531-1 assume { :end_inline_reset_delta_events } true; 64720#L1892-2 [2021-12-15 17:21:49,852 INFO L793 eck$LassoCheckResult]: Loop: 64720#L1892-2 assume !false; 65744#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 65946#L1233 assume !false; 65928#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 65257#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 65237#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 65393#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 64220#L1046 assume !(0 != eval_~tmp~0#1); 64222#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 64256#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 65427#L1258-3 assume !(0 == ~M_E~0); 65991#L1258-5 assume !(0 == ~T1_E~0); 64397#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 64398#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 65983#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 65989#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 65990#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 64622#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 64623#L1293-3 assume !(0 == ~T8_E~0); 65741#L1298-3 assume !(0 == ~T9_E~0); 65742#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 65904#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 65740#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 65241#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 64399#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 64400#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 65826#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 64542#L1338-3 assume !(0 == ~E_4~0); 64543#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 65657#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 65831#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 65832#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 65197#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 64756#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 64757#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 65514#L1378-3 assume !(0 == ~E_12~0); 65515#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 65696#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 65697#L607-42 assume !(1 == ~m_pc~0); 65311#L607-44 is_master_triggered_~__retres1~0#1 := 0; 65038#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 65039#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 64770#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 64771#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 65293#L626-42 assume 1 == ~t1_pc~0; 64854#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 64855#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 65160#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 65161#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 64433#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 64434#L645-42 assume !(1 == ~t2_pc~0); 65634#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 65635#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 65802#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 64641#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 64148#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 64149#L664-42 assume !(1 == ~t3_pc~0); 64675#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 64676#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 65931#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 65461#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 65462#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 65628#L683-42 assume !(1 == ~t4_pc~0); 65336#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 65337#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 65468#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 65893#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 65894#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 65735#L702-42 assume 1 == ~t5_pc~0; 65223#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 64847#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 65144#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 65818#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 64164#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 64165#L721-42 assume 1 == ~t6_pc~0; 64317#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 64337#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 64802#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 65974#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 64974#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 64820#L740-42 assume 1 == ~t7_pc~0; 64821#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 64558#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 65100#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 64954#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 64955#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 65229#L759-42 assume 1 == ~t8_pc~0; 65078#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 65010#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 65011#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 65089#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 65090#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 65185#L778-42 assume 1 == ~t9_pc~0; 65022#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 65024#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 65432#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 65338#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 65339#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 65395#L797-42 assume 1 == ~t10_pc~0; 64563#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 64564#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 65565#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 65878#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 65433#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 65434#L816-42 assume 1 == ~t11_pc~0; 64112#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 64113#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 64655#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 64656#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 64735#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 64736#L835-42 assume 1 == ~t12_pc~0; 65141#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 65034#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 64710#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 64711#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 65795#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 65577#L854-42 assume 1 == ~t13_pc~0; 65578#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 64654#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 64264#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 64265#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 64911#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 64912#L1401-3 assume !(1 == ~M_E~0); 65691#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 64500#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 64364#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 64365#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 64965#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 64966#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 64540#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 64541#L1436-3 assume !(1 == ~T8_E~0); 64128#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 64129#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 65719#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 65050#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 64702#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 64703#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 65986#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 64642#L1476-3 assume !(1 == ~E_3~0); 64643#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 65044#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 64670#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 64671#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 65084#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 65085#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 65511#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 65501#L1516-3 assume !(1 == ~E_11~0); 65502#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 65201#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 65202#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 65595#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 64476#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 65369#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 65012#L1911 assume !(0 == start_simulation_~tmp~3#1); 65013#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 65534#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 64602#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 65471#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 64305#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 64306#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 64535#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 64536#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 64720#L1892-2 [2021-12-15 17:21:49,852 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:49,853 INFO L85 PathProgramCache]: Analyzing trace with hash -1197395463, now seen corresponding path program 1 times [2021-12-15 17:21:49,853 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:49,853 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2068148633] [2021-12-15 17:21:49,853 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:49,853 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:49,863 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:49,880 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:49,880 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:49,880 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2068148633] [2021-12-15 17:21:49,880 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2068148633] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:49,880 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:49,880 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:49,880 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [996194460] [2021-12-15 17:21:49,881 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:49,881 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:21:49,881 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:49,881 INFO L85 PathProgramCache]: Analyzing trace with hash 1726849421, now seen corresponding path program 1 times [2021-12-15 17:21:49,881 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:49,881 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1541293423] [2021-12-15 17:21:49,881 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:49,881 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:49,893 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:49,913 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:49,914 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:49,914 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1541293423] [2021-12-15 17:21:49,914 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1541293423] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:49,914 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:49,914 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:49,914 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1276503659] [2021-12-15 17:21:49,914 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:49,914 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:21:49,914 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:21:49,914 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-15 17:21:49,915 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-15 17:21:49,915 INFO L87 Difference]: Start difference. First operand 3555 states and 5210 transitions. cyclomatic complexity: 1656 Second operand has 4 states, 4 states have (on average 39.75) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:50,065 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:21:50,065 INFO L93 Difference]: Finished difference Result 5081 states and 7426 transitions. [2021-12-15 17:21:50,065 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-15 17:21:50,066 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5081 states and 7426 transitions. [2021-12-15 17:21:50,080 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4896 [2021-12-15 17:21:50,090 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5081 states to 5081 states and 7426 transitions. [2021-12-15 17:21:50,090 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5081 [2021-12-15 17:21:50,093 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5081 [2021-12-15 17:21:50,093 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5081 states and 7426 transitions. [2021-12-15 17:21:50,098 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:21:50,098 INFO L681 BuchiCegarLoop]: Abstraction has 5081 states and 7426 transitions. [2021-12-15 17:21:50,100 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5081 states and 7426 transitions. [2021-12-15 17:21:50,129 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5081 to 3555. [2021-12-15 17:21:50,133 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3555 states, 3555 states have (on average 1.4646976090014066) internal successors, (5207), 3554 states have internal predecessors, (5207), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:50,138 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3555 states to 3555 states and 5207 transitions. [2021-12-15 17:21:50,139 INFO L704 BuchiCegarLoop]: Abstraction has 3555 states and 5207 transitions. [2021-12-15 17:21:50,139 INFO L587 BuchiCegarLoop]: Abstraction has 3555 states and 5207 transitions. [2021-12-15 17:21:50,139 INFO L425 BuchiCegarLoop]: ======== Iteration 17============ [2021-12-15 17:21:50,139 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3555 states and 5207 transitions. [2021-12-15 17:21:50,145 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3382 [2021-12-15 17:21:50,145 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:21:50,145 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:21:50,146 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:50,146 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:50,147 INFO L791 eck$LassoCheckResult]: Stem: 73604#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 73605#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 73424#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 73139#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 73140#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 74318#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 74319#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 73276#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 73277#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 73731#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 73566#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 73567#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 73343#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 73344#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 73742#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 73919#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 74071#L936-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 74108#L941-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 73354#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 73355#L1258 assume !(0 == ~M_E~0); 74540#L1258-2 assume !(0 == ~T1_E~0); 73649#L1263-1 assume !(0 == ~T2_E~0); 73650#L1268-1 assume !(0 == ~T3_E~0); 73953#L1273-1 assume !(0 == ~T4_E~0); 74521#L1278-1 assume !(0 == ~T5_E~0); 74379#L1283-1 assume !(0 == ~T6_E~0); 74380#L1288-1 assume !(0 == ~T7_E~0); 74620#L1293-1 assume !(0 == ~T8_E~0); 74608#L1298-1 assume !(0 == ~T9_E~0); 74534#L1303-1 assume !(0 == ~T10_E~0); 73168#L1308-1 assume !(0 == ~T11_E~0); 73110#L1313-1 assume !(0 == ~T12_E~0); 73111#L1318-1 assume !(0 == ~T13_E~0); 73117#L1323-1 assume !(0 == ~E_1~0); 73118#L1328-1 assume !(0 == ~E_2~0); 73286#L1333-1 assume !(0 == ~E_3~0); 74245#L1338-1 assume !(0 == ~E_4~0); 74246#L1343-1 assume !(0 == ~E_5~0); 74351#L1348-1 assume !(0 == ~E_6~0); 74643#L1353-1 assume !(0 == ~E_7~0); 73972#L1358-1 assume !(0 == ~E_8~0); 73973#L1363-1 assume !(0 == ~E_9~0); 74263#L1368-1 assume !(0 == ~E_10~0); 72947#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 72948#L1378-1 assume !(0 == ~E_12~0); 73235#L1383-1 assume !(0 == ~E_13~0); 73236#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 73978#L607 assume !(1 == ~m_pc~0); 73305#L607-2 is_master_triggered_~__retres1~0#1 := 0; 73306#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 74349#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 73899#L1560 assume !(0 != activate_threads_~tmp~1#1); 73900#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 73130#L626 assume !(1 == ~t1_pc~0); 73131#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 73400#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 73401#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 73570#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 73030#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 73031#L645 assume 1 == ~t2_pc~0; 73147#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 73104#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 73782#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 73783#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 73875#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 73876#L664 assume 1 == ~t3_pc~0; 74642#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 72872#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 72873#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 73531#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 73532#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 74550#L683 assume !(1 == ~t4_pc~0); 74093#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 74045#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 74046#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 74080#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 74206#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 73825#L702 assume 1 == ~t5_pc~0; 73826#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 73751#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 74201#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 74508#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 74448#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 72919#L721 assume !(1 == ~t6_pc~0); 72894#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 72895#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 73057#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 73540#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 73541#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 74141#L740 assume 1 == ~t7_pc~0; 72968#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 72782#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 72783#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 72772#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 72773#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 73476#L759 assume !(1 == ~t8_pc~0); 73477#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 73506#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 74199#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 74200#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 74332#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 74619#L778 assume 1 == ~t9_pc~0; 74505#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 72946#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 72887#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 72816#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 72817#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 73143#L797 assume !(1 == ~t10_pc~0); 73144#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 73263#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 74404#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 73647#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 73648#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 73937#L816 assume 1 == ~t11_pc~0; 72852#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 72853#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 73608#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 73547#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 73548#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 74070#L835 assume 1 == ~t12_pc~0; 73950#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 73015#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 73037#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 73178#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 73704#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 73705#L854 assume !(1 == ~t13_pc~0); 73345#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 73346#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 73396#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 73055#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 73056#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 74443#L1401 assume !(1 == ~M_E~0); 73535#L1401-2 assume !(1 == ~T1_E~0); 73536#L1406-1 assume !(1 == ~T2_E~0); 74130#L1411-1 assume !(1 == ~T3_E~0); 74131#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 73798#L1421-1 assume !(1 == ~T5_E~0); 73341#L1426-1 assume !(1 == ~T6_E~0); 73342#L1431-1 assume !(1 == ~T7_E~0); 72890#L1436-1 assume !(1 == ~T8_E~0); 72891#L1441-1 assume !(1 == ~T9_E~0); 73638#L1446-1 assume !(1 == ~T10_E~0); 73639#L1451-1 assume !(1 == ~T11_E~0); 74348#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 73996#L1461-1 assume !(1 == ~T13_E~0); 73559#L1466-1 assume !(1 == ~E_1~0); 73560#L1471-1 assume !(1 == ~E_2~0); 74330#L1476-1 assume !(1 == ~E_3~0); 74331#L1481-1 assume !(1 == ~E_4~0); 74487#L1486-1 assume !(1 == ~E_5~0); 73183#L1491-1 assume !(1 == ~E_6~0); 72824#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 72825#L1501-1 assume !(1 == ~E_8~0); 73636#L1506-1 assume !(1 == ~E_9~0); 73637#L1511-1 assume !(1 == ~E_10~0); 73593#L1516-1 assume !(1 == ~E_11~0); 72768#L1521-1 assume !(1 == ~E_12~0); 72769#L1526-1 assume !(1 == ~E_13~0); 72823#L1531-1 assume { :end_inline_reset_delta_events } true; 73366#L1892-2 [2021-12-15 17:21:50,147 INFO L793 eck$LassoCheckResult]: Loop: 73366#L1892-2 assume !false; 74395#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 74597#L1233 assume !false; 74580#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 73902#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 73882#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 74038#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 72866#L1046 assume !(0 != eval_~tmp~0#1); 72868#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 72902#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 74072#L1258-3 assume !(0 == ~M_E~0); 74641#L1258-5 assume !(0 == ~T1_E~0); 73043#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 73044#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 74633#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 74639#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 74640#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 73268#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 73269#L1293-3 assume !(0 == ~T8_E~0); 74392#L1298-3 assume !(0 == ~T9_E~0); 74393#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 74556#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 74391#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 73886#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 73045#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 73046#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 74479#L1333-3 assume !(0 == ~E_3~0); 73188#L1338-3 assume !(0 == ~E_4~0); 73189#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 74303#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 74484#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 74485#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 73842#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 73402#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 73403#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 74160#L1378-3 assume !(0 == ~E_12~0); 74161#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 74345#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 74346#L607-42 assume !(1 == ~m_pc~0); 73956#L607-44 is_master_triggered_~__retres1~0#1 := 0; 73683#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 73684#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 73416#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 73417#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 73938#L626-42 assume 1 == ~t1_pc~0; 73500#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 73501#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 73805#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 73806#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 73079#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 73080#L645-42 assume 1 == ~t2_pc~0; 74549#L646-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 74281#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 74454#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 73287#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 72794#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 72795#L664-42 assume !(1 == ~t3_pc~0); 73321#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 73322#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 74583#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 74106#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 74107#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 74274#L683-42 assume 1 == ~t4_pc~0; 74649#L684-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 73982#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 74113#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 74545#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 74546#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 74386#L702-42 assume !(1 == ~t5_pc~0); 73492#L702-44 is_transmit5_triggered_~__retres1~5#1 := 0; 73493#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 73789#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 74471#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 72810#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 72811#L721-42 assume 1 == ~t6_pc~0; 72963#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 72983#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 73448#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 74625#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 73620#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 73466#L740-42 assume !(1 == ~t7_pc~0); 73203#L740-44 is_transmit7_triggered_~__retres1~7#1 := 0; 73204#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 73745#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 73600#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 73601#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 73874#L759-42 assume 1 == ~t8_pc~0; 73723#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 73655#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 73656#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 73734#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 73735#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 73830#L778-42 assume 1 == ~t9_pc~0; 73667#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 73669#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 74077#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 73983#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 73984#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 74040#L797-42 assume 1 == ~t10_pc~0; 73209#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 73210#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 74211#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 74530#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 74078#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 74079#L816-42 assume 1 == ~t11_pc~0; 72758#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 72759#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 73301#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 73302#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 73381#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 73382#L835-42 assume 1 == ~t12_pc~0; 73786#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 73679#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 73356#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 73357#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 74447#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 74223#L854-42 assume 1 == ~t13_pc~0; 74224#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 73300#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 72910#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 72911#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 73557#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 73558#L1401-3 assume !(1 == ~M_E~0); 74339#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 73146#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 73010#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 73011#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 73611#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 73612#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 73186#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 73187#L1436-3 assume !(1 == ~T8_E~0); 72774#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 72775#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 74368#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 73695#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 73348#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 73349#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 74636#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 73288#L1476-3 assume !(1 == ~E_3~0); 73289#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 73689#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 73316#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 73317#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 73729#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 73730#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 74157#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 74147#L1516-3 assume !(1 == ~E_11~0); 74148#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 73846#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 73847#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 74241#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 73122#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 74014#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 73657#L1911 assume !(0 == start_simulation_~tmp~3#1); 73658#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 74180#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 73248#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 74116#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 72951#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 72952#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 73181#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 73182#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 73366#L1892-2 [2021-12-15 17:21:50,147 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:50,147 INFO L85 PathProgramCache]: Analyzing trace with hash -250357577, now seen corresponding path program 1 times [2021-12-15 17:21:50,147 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:50,147 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [396787317] [2021-12-15 17:21:50,147 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:50,148 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:50,155 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:50,172 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:50,172 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:50,172 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [396787317] [2021-12-15 17:21:50,172 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [396787317] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:50,172 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:50,172 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:50,172 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [3863355] [2021-12-15 17:21:50,173 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:50,173 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:21:50,173 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:50,173 INFO L85 PathProgramCache]: Analyzing trace with hash 433336011, now seen corresponding path program 1 times [2021-12-15 17:21:50,173 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:50,173 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [572003603] [2021-12-15 17:21:50,173 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:50,173 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:50,181 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:50,196 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:50,196 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:50,196 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [572003603] [2021-12-15 17:21:50,196 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [572003603] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:50,196 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:50,197 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:50,197 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [721324144] [2021-12-15 17:21:50,197 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:50,197 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:21:50,197 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:21:50,197 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-15 17:21:50,197 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-15 17:21:50,197 INFO L87 Difference]: Start difference. First operand 3555 states and 5207 transitions. cyclomatic complexity: 1653 Second operand has 4 states, 4 states have (on average 39.75) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:50,332 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:21:50,332 INFO L93 Difference]: Finished difference Result 5073 states and 7406 transitions. [2021-12-15 17:21:50,332 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-15 17:21:50,332 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5073 states and 7406 transitions. [2021-12-15 17:21:50,346 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4896 [2021-12-15 17:21:50,356 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5073 states to 5073 states and 7406 transitions. [2021-12-15 17:21:50,356 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5073 [2021-12-15 17:21:50,360 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5073 [2021-12-15 17:21:50,360 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5073 states and 7406 transitions. [2021-12-15 17:21:50,364 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:21:50,364 INFO L681 BuchiCegarLoop]: Abstraction has 5073 states and 7406 transitions. [2021-12-15 17:21:50,366 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5073 states and 7406 transitions. [2021-12-15 17:21:50,430 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5073 to 3555. [2021-12-15 17:21:50,435 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3555 states, 3555 states have (on average 1.4638537271448664) internal successors, (5204), 3554 states have internal predecessors, (5204), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:50,441 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3555 states to 3555 states and 5204 transitions. [2021-12-15 17:21:50,441 INFO L704 BuchiCegarLoop]: Abstraction has 3555 states and 5204 transitions. [2021-12-15 17:21:50,441 INFO L587 BuchiCegarLoop]: Abstraction has 3555 states and 5204 transitions. [2021-12-15 17:21:50,441 INFO L425 BuchiCegarLoop]: ======== Iteration 18============ [2021-12-15 17:21:50,441 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3555 states and 5204 transitions. [2021-12-15 17:21:50,448 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3382 [2021-12-15 17:21:50,449 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:21:50,449 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:21:50,450 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:50,450 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:50,451 INFO L791 eck$LassoCheckResult]: Stem: 82243#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 82244#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 82063#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 81777#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 81778#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 82961#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 82962#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 81915#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 81916#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 82371#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 82205#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 82206#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 81982#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 81983#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 82382#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 82560#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 82712#L936-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 82749#L941-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 81993#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 81994#L1258 assume !(0 == ~M_E~0); 83179#L1258-2 assume !(0 == ~T1_E~0); 82288#L1263-1 assume !(0 == ~T2_E~0); 82289#L1268-1 assume !(0 == ~T3_E~0); 82594#L1273-1 assume !(0 == ~T4_E~0); 83161#L1278-1 assume !(0 == ~T5_E~0); 83018#L1283-1 assume !(0 == ~T6_E~0); 83019#L1288-1 assume !(0 == ~T7_E~0); 83261#L1293-1 assume !(0 == ~T8_E~0); 83249#L1298-1 assume !(0 == ~T9_E~0); 83173#L1303-1 assume !(0 == ~T10_E~0); 81806#L1308-1 assume !(0 == ~T11_E~0); 81748#L1313-1 assume !(0 == ~T12_E~0); 81749#L1318-1 assume !(0 == ~T13_E~0); 81755#L1323-1 assume !(0 == ~E_1~0); 81756#L1328-1 assume !(0 == ~E_2~0); 81925#L1333-1 assume !(0 == ~E_3~0); 82887#L1338-1 assume !(0 == ~E_4~0); 82888#L1343-1 assume !(0 == ~E_5~0); 82992#L1348-1 assume !(0 == ~E_6~0); 83286#L1353-1 assume !(0 == ~E_7~0); 82613#L1358-1 assume !(0 == ~E_8~0); 82614#L1363-1 assume !(0 == ~E_9~0); 82905#L1368-1 assume !(0 == ~E_10~0); 81585#L1373-1 assume !(0 == ~E_11~0); 81586#L1378-1 assume !(0 == ~E_12~0); 81874#L1383-1 assume !(0 == ~E_13~0); 81875#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 82619#L607 assume !(1 == ~m_pc~0); 81944#L607-2 is_master_triggered_~__retres1~0#1 := 0; 81945#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 82990#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 82539#L1560 assume !(0 != activate_threads_~tmp~1#1); 82540#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 81768#L626 assume !(1 == ~t1_pc~0); 81769#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 82039#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 82040#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 82209#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 81668#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 81669#L645 assume 1 == ~t2_pc~0; 81785#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 81742#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 82422#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 82423#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 82515#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 82516#L664 assume 1 == ~t3_pc~0; 83285#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 81510#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 81511#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 82170#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 82171#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 83189#L683 assume !(1 == ~t4_pc~0); 82734#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 82686#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 82687#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 82721#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 82848#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 82465#L702 assume 1 == ~t5_pc~0; 82466#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 82391#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 82843#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 83148#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 83087#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 81557#L721 assume !(1 == ~t6_pc~0); 81532#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 81533#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 81695#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 82179#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 82180#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 82783#L740 assume 1 == ~t7_pc~0; 81606#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 81420#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 81421#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 81410#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 81411#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 82115#L759 assume !(1 == ~t8_pc~0); 82116#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 82145#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 82841#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 82842#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 82975#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 83260#L778 assume 1 == ~t9_pc~0; 83145#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 81584#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 81525#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 81454#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 81455#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 81781#L797 assume !(1 == ~t10_pc~0); 81782#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 81902#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 83042#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 82286#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 82287#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 82578#L816 assume 1 == ~t11_pc~0; 81490#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 81491#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 82247#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 82186#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 82187#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 82711#L835 assume 1 == ~t12_pc~0; 82591#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 81653#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 81675#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 81817#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 82344#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 82345#L854 assume !(1 == ~t13_pc~0); 81984#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 81985#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 82035#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 81693#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 81694#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 83082#L1401 assume !(1 == ~M_E~0); 82174#L1401-2 assume !(1 == ~T1_E~0); 82175#L1406-1 assume !(1 == ~T2_E~0); 82771#L1411-1 assume !(1 == ~T3_E~0); 82772#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 82438#L1421-1 assume !(1 == ~T5_E~0); 81980#L1426-1 assume !(1 == ~T6_E~0); 81981#L1431-1 assume !(1 == ~T7_E~0); 81528#L1436-1 assume !(1 == ~T8_E~0); 81529#L1441-1 assume !(1 == ~T9_E~0); 82277#L1446-1 assume !(1 == ~T10_E~0); 82278#L1451-1 assume !(1 == ~T11_E~0); 82989#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 82637#L1461-1 assume !(1 == ~T13_E~0); 82198#L1466-1 assume !(1 == ~E_1~0); 82199#L1471-1 assume !(1 == ~E_2~0); 82973#L1476-1 assume !(1 == ~E_3~0); 82974#L1481-1 assume !(1 == ~E_4~0); 83127#L1486-1 assume !(1 == ~E_5~0); 81822#L1491-1 assume !(1 == ~E_6~0); 81462#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 81463#L1501-1 assume !(1 == ~E_8~0); 82275#L1506-1 assume !(1 == ~E_9~0); 82276#L1511-1 assume !(1 == ~E_10~0); 82232#L1516-1 assume !(1 == ~E_11~0); 81406#L1521-1 assume !(1 == ~E_12~0); 81407#L1526-1 assume !(1 == ~E_13~0); 81461#L1531-1 assume { :end_inline_reset_delta_events } true; 82005#L1892-2 [2021-12-15 17:21:50,451 INFO L793 eck$LassoCheckResult]: Loop: 82005#L1892-2 assume !false; 83034#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 83238#L1233 assume !false; 83220#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 82542#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 82522#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 82679#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 81504#L1046 assume !(0 != eval_~tmp~0#1); 81506#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 81540#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 82713#L1258-3 assume !(0 == ~M_E~0); 83284#L1258-5 assume !(0 == ~T1_E~0); 81681#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 81682#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 83276#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 83282#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 83283#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 81907#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 81908#L1293-3 assume !(0 == ~T8_E~0); 83031#L1298-3 assume !(0 == ~T9_E~0); 83032#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 83195#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 83196#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 84863#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 84862#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 83118#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 83119#L1333-3 assume !(0 == ~E_3~0); 81827#L1338-3 assume !(0 == ~E_4~0); 81828#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 82946#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 83124#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 83125#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 82482#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 82041#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 82042#L1373-3 assume !(0 == ~E_11~0); 82802#L1378-3 assume !(0 == ~E_12~0); 82803#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 82986#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 82987#L607-42 assume !(1 == ~m_pc~0); 82597#L607-44 is_master_triggered_~__retres1~0#1 := 0; 82323#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 82324#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 82055#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 82056#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 82579#L626-42 assume 1 == ~t1_pc~0; 82139#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 82140#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 82445#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 82446#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 81717#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 81718#L645-42 assume 1 == ~t2_pc~0; 83188#L646-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 82924#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 83093#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 81926#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 81432#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 81433#L664-42 assume !(1 == ~t3_pc~0); 81960#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 81961#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 83223#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 82747#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 82748#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 82917#L683-42 assume 1 == ~t4_pc~0; 83292#L684-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 82623#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 82754#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 83184#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 83185#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 83025#L702-42 assume !(1 == ~t5_pc~0); 82131#L702-44 is_transmit5_triggered_~__retres1~5#1 := 0; 82132#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 82429#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 83110#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 81448#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 81449#L721-42 assume 1 == ~t6_pc~0; 81601#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 81621#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 82087#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 83268#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 82259#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 82105#L740-42 assume !(1 == ~t7_pc~0); 81842#L740-44 is_transmit7_triggered_~__retres1~7#1 := 0; 81843#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 82385#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 82239#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 82240#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 82514#L759-42 assume 1 == ~t8_pc~0; 82363#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 82294#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 82295#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 82374#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 82375#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 82470#L778-42 assume 1 == ~t9_pc~0; 82307#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 82309#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 82718#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 82624#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 82625#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 82681#L797-42 assume 1 == ~t10_pc~0; 81848#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 81849#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 82853#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 83169#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 82719#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 82720#L816-42 assume 1 == ~t11_pc~0; 81396#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 81397#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 81940#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 81941#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 82020#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 82021#L835-42 assume 1 == ~t12_pc~0; 82426#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 82319#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 81995#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 81996#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 83086#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 82865#L854-42 assume 1 == ~t13_pc~0; 82866#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 81939#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 81548#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 81549#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 82196#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 82197#L1401-3 assume !(1 == ~M_E~0); 82980#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 81784#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 81648#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 81649#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 82250#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 82251#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 81825#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 81826#L1436-3 assume !(1 == ~T8_E~0); 81412#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 81413#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 83009#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 82335#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 81987#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 81988#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 83279#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 81927#L1476-3 assume !(1 == ~E_3~0); 81928#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 82329#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 81955#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 81956#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 82369#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 82370#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 82799#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 82788#L1516-3 assume !(1 == ~E_11~0); 82789#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 82486#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 82487#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 82883#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 81760#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 82655#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 82296#L1911 assume !(0 == start_simulation_~tmp~3#1); 82297#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 82822#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 81887#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 82757#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 81589#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 81590#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 81820#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 81821#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 82005#L1892-2 [2021-12-15 17:21:50,451 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:50,451 INFO L85 PathProgramCache]: Analyzing trace with hash -583000715, now seen corresponding path program 1 times [2021-12-15 17:21:50,451 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:50,451 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1033050176] [2021-12-15 17:21:50,451 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:50,451 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:50,462 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:50,479 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:50,480 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:50,480 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1033050176] [2021-12-15 17:21:50,480 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1033050176] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:50,480 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:50,480 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:50,480 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1311764665] [2021-12-15 17:21:50,480 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:50,480 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:21:50,480 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:50,481 INFO L85 PathProgramCache]: Analyzing trace with hash -151435639, now seen corresponding path program 1 times [2021-12-15 17:21:50,481 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:50,481 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [674566959] [2021-12-15 17:21:50,481 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:50,481 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:50,489 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:50,503 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:50,503 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:50,503 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [674566959] [2021-12-15 17:21:50,503 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [674566959] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:50,503 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:50,503 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:50,503 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2117517362] [2021-12-15 17:21:50,504 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:50,504 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:21:50,504 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:21:50,505 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-15 17:21:50,505 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-15 17:21:50,505 INFO L87 Difference]: Start difference. First operand 3555 states and 5204 transitions. cyclomatic complexity: 1650 Second operand has 4 states, 4 states have (on average 39.75) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:50,713 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:21:50,713 INFO L93 Difference]: Finished difference Result 9800 states and 14218 transitions. [2021-12-15 17:21:50,714 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-15 17:21:50,714 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9800 states and 14218 transitions. [2021-12-15 17:21:50,754 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 9611 [2021-12-15 17:21:50,780 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9800 states to 9800 states and 14218 transitions. [2021-12-15 17:21:50,780 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9800 [2021-12-15 17:21:50,789 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9800 [2021-12-15 17:21:50,789 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9800 states and 14218 transitions. [2021-12-15 17:21:50,799 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:21:50,799 INFO L681 BuchiCegarLoop]: Abstraction has 9800 states and 14218 transitions. [2021-12-15 17:21:50,806 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9800 states and 14218 transitions. [2021-12-15 17:21:50,882 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9800 to 9618. [2021-12-15 17:21:50,895 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 9618 states, 9618 states have (on average 1.4520690372218756) internal successors, (13966), 9617 states have internal predecessors, (13966), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:50,911 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9618 states to 9618 states and 13966 transitions. [2021-12-15 17:21:50,912 INFO L704 BuchiCegarLoop]: Abstraction has 9618 states and 13966 transitions. [2021-12-15 17:21:50,912 INFO L587 BuchiCegarLoop]: Abstraction has 9618 states and 13966 transitions. [2021-12-15 17:21:50,912 INFO L425 BuchiCegarLoop]: ======== Iteration 19============ [2021-12-15 17:21:50,912 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 9618 states and 13966 transitions. [2021-12-15 17:21:50,937 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 9441 [2021-12-15 17:21:50,937 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:21:50,937 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:21:50,938 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:50,939 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:50,939 INFO L791 eck$LassoCheckResult]: Stem: 95619#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 95620#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 95433#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 95146#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 95147#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 96414#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 96415#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 95283#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 95284#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 95749#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 95581#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 95582#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 95352#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 95353#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 95760#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 95946#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 96115#L936-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 96154#L941-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 95363#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 95364#L1258 assume !(0 == ~M_E~0); 96691#L1258-2 assume !(0 == ~T1_E~0); 95665#L1263-1 assume !(0 == ~T2_E~0); 95666#L1268-1 assume !(0 == ~T3_E~0); 95984#L1273-1 assume !(0 == ~T4_E~0); 96669#L1278-1 assume !(0 == ~T5_E~0); 96485#L1283-1 assume !(0 == ~T6_E~0); 96486#L1288-1 assume !(0 == ~T7_E~0); 96820#L1293-1 assume !(0 == ~T8_E~0); 96798#L1298-1 assume !(0 == ~T9_E~0); 96684#L1303-1 assume !(0 == ~T10_E~0); 95174#L1308-1 assume !(0 == ~T11_E~0); 95118#L1313-1 assume !(0 == ~T12_E~0); 95119#L1318-1 assume !(0 == ~T13_E~0); 95125#L1323-1 assume !(0 == ~E_1~0); 95126#L1328-1 assume !(0 == ~E_2~0); 95293#L1333-1 assume !(0 == ~E_3~0); 96315#L1338-1 assume !(0 == ~E_4~0); 96316#L1343-1 assume !(0 == ~E_5~0); 96452#L1348-1 assume !(0 == ~E_6~0); 96870#L1353-1 assume !(0 == ~E_7~0); 96004#L1358-1 assume !(0 == ~E_8~0); 96005#L1363-1 assume !(0 == ~E_9~0); 96341#L1368-1 assume !(0 == ~E_10~0); 94953#L1373-1 assume !(0 == ~E_11~0); 94954#L1378-1 assume !(0 == ~E_12~0); 95241#L1383-1 assume !(0 == ~E_13~0); 95242#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 96012#L607 assume !(1 == ~m_pc~0); 95312#L607-2 is_master_triggered_~__retres1~0#1 := 0; 95313#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 96449#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 95924#L1560 assume !(0 != activate_threads_~tmp~1#1); 95925#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 95138#L626 assume !(1 == ~t1_pc~0); 95139#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 95409#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 95410#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 95585#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 95037#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 95038#L645 assume !(1 == ~t2_pc~0); 95111#L645-2 is_transmit2_triggered_~__retres1~2#1 := 0; 95112#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 95800#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 95801#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 95898#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 95899#L664 assume 1 == ~t3_pc~0; 96865#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 94876#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 94877#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 95544#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 95545#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 96706#L683 assume !(1 == ~t4_pc~0); 96138#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 96088#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 96089#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 96124#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 96268#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 95845#L702 assume 1 == ~t5_pc~0; 95846#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 95769#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 96260#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 96650#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 96568#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 94925#L721 assume !(1 == ~t6_pc~0); 94898#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 94899#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 95064#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 95553#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 95554#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 96190#L740 assume 1 == ~t7_pc~0; 94975#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 94785#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 94786#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 94775#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 94776#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 95485#L759 assume !(1 == ~t8_pc~0); 95486#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 95514#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 96258#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 96259#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 96430#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 96819#L778 assume 1 == ~t9_pc~0; 96648#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 94952#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 94891#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 94819#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 94820#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 95150#L797 assume !(1 == ~t10_pc~0); 95151#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 95270#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 96514#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 95663#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 95664#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 95967#L816 assume 1 == ~t11_pc~0; 94856#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 94857#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 95623#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 95560#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 95561#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 96114#L835 assume 1 == ~t12_pc~0; 95981#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 95022#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 95044#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 95184#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 95721#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 95722#L854 assume !(1 == ~t13_pc~0); 95354#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 95355#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 95405#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 95062#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 95063#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 96564#L1401 assume !(1 == ~M_E~0); 95548#L1401-2 assume !(1 == ~T1_E~0); 95549#L1406-1 assume !(1 == ~T2_E~0); 96179#L1411-1 assume !(1 == ~T3_E~0); 96180#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 95816#L1421-1 assume !(1 == ~T5_E~0); 95350#L1426-1 assume !(1 == ~T6_E~0); 95351#L1431-1 assume !(1 == ~T7_E~0); 94894#L1436-1 assume !(1 == ~T8_E~0); 94895#L1441-1 assume !(1 == ~T9_E~0); 95654#L1446-1 assume !(1 == ~T10_E~0); 95655#L1451-1 assume !(1 == ~T11_E~0); 96448#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 96031#L1461-1 assume !(1 == ~T13_E~0); 95575#L1466-1 assume !(1 == ~E_1~0); 95576#L1471-1 assume !(1 == ~E_2~0); 96428#L1476-1 assume !(1 == ~E_3~0); 96429#L1481-1 assume !(1 == ~E_4~0); 96625#L1486-1 assume !(1 == ~E_5~0); 95189#L1491-1 assume !(1 == ~E_6~0); 94828#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 94829#L1501-1 assume !(1 == ~E_8~0); 95652#L1506-1 assume !(1 == ~E_9~0); 95653#L1511-1 assume !(1 == ~E_10~0); 95608#L1516-1 assume !(1 == ~E_11~0); 94771#L1521-1 assume !(1 == ~E_12~0); 94772#L1526-1 assume !(1 == ~E_13~0); 94827#L1531-1 assume { :end_inline_reset_delta_events } true; 95375#L1892-2 [2021-12-15 17:21:50,939 INFO L793 eck$LassoCheckResult]: Loop: 95375#L1892-2 assume !false; 102613#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 102610#L1233 assume !false; 102608#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 102592#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 102590#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 96077#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 94870#L1046 assume !(0 != eval_~tmp~0#1); 94872#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 104217#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 104216#L1258-3 assume !(0 == ~M_E~0); 104215#L1258-5 assume !(0 == ~T1_E~0); 104214#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 104213#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 104212#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 104211#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 104210#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 104209#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 104208#L1293-3 assume !(0 == ~T8_E~0); 104207#L1298-3 assume !(0 == ~T9_E~0); 104206#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 104205#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 104204#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 104203#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 104202#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 104201#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 104200#L1333-3 assume !(0 == ~E_3~0); 104199#L1338-3 assume !(0 == ~E_4~0); 104198#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 104197#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 104196#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 104194#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 103993#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 95411#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 95412#L1373-3 assume !(0 == ~E_11~0); 96212#L1378-3 assume !(0 == ~E_12~0); 96213#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 96444#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 96445#L607-42 assume !(1 == ~m_pc~0); 95987#L607-44 is_master_triggered_~__retres1~0#1 := 0; 103966#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 103964#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 103962#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 103959#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 103957#L626-42 assume !(1 == ~t1_pc~0); 103955#L626-44 is_transmit1_triggered_~__retres1~1#1 := 0; 103953#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 95823#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 95824#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 95086#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 95087#L645-42 assume !(1 == ~t2_pc~0); 96827#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 103976#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 103975#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 103974#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 103973#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 103972#L664-42 assume !(1 == ~t3_pc~0); 103971#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 103969#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 103968#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 103967#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 103965#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 103963#L683-42 assume 1 == ~t4_pc~0; 103961#L684-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 103958#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 103956#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 103954#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 103952#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 103951#L702-42 assume 1 == ~t5_pc~0; 103949#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 103947#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 103945#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 103943#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 103941#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 103939#L721-42 assume !(1 == ~t6_pc~0); 103937#L721-44 is_transmit6_triggered_~__retres1~6#1 := 0; 103934#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 103932#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 103930#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 103929#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 103926#L740-42 assume 1 == ~t7_pc~0; 103923#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 103921#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 103919#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 103917#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 103915#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 103912#L759-42 assume 1 == ~t8_pc~0; 103909#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 103907#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 103905#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 103903#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 103901#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 103898#L778-42 assume !(1 == ~t9_pc~0); 103895#L778-44 is_transmit9_triggered_~__retres1~9#1 := 0; 103893#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 103891#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 103889#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 103887#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 103884#L797-42 assume 1 == ~t10_pc~0; 103881#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 103879#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 103877#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 103875#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 103873#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 103870#L816-42 assume !(1 == ~t11_pc~0); 103867#L816-44 is_transmit11_triggered_~__retres1~11#1 := 0; 103865#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 103863#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 103861#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 103859#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 103856#L835-42 assume 1 == ~t12_pc~0; 103853#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 103851#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 103849#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 103847#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 103845#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 103842#L854-42 assume 1 == ~t13_pc~0; 103840#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 103837#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 103835#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 103833#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 103831#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 103785#L1401-3 assume !(1 == ~M_E~0); 103783#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 103780#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 103778#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 103776#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 103774#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 103772#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 103770#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 103767#L1436-3 assume !(1 == ~T8_E~0); 103765#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 103763#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 103761#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 103759#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 103757#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 103754#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 103752#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 103750#L1476-3 assume !(1 == ~E_3~0); 103748#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 103746#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 103744#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 103741#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 103739#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 103737#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 103735#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 103219#L1516-3 assume !(1 == ~E_11~0); 103220#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 103634#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 103631#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 96930#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 95130#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 96051#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 96052#L1911 assume !(0 == start_simulation_~tmp~3#1); 103225#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 102647#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 102632#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 102630#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 102628#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 102626#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 102624#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 102621#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 95375#L1892-2 [2021-12-15 17:21:50,939 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:50,939 INFO L85 PathProgramCache]: Analyzing trace with hash -1586057580, now seen corresponding path program 1 times [2021-12-15 17:21:50,939 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:50,940 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1490005630] [2021-12-15 17:21:50,940 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:50,940 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:50,948 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:50,965 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:50,965 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:50,965 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1490005630] [2021-12-15 17:21:50,966 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1490005630] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:50,966 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:50,966 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:50,966 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [447464532] [2021-12-15 17:21:50,966 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:50,967 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:21:50,968 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:50,968 INFO L85 PathProgramCache]: Analyzing trace with hash -1641895386, now seen corresponding path program 1 times [2021-12-15 17:21:50,968 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:50,968 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2095687513] [2021-12-15 17:21:50,968 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:50,968 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:50,979 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:51,000 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:51,001 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:51,001 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2095687513] [2021-12-15 17:21:51,001 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2095687513] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:51,001 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:51,001 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-15 17:21:51,001 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [35940853] [2021-12-15 17:21:51,001 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:51,002 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:21:51,002 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:21:51,002 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-15 17:21:51,002 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-15 17:21:51,002 INFO L87 Difference]: Start difference. First operand 9618 states and 13966 transitions. cyclomatic complexity: 4350 Second operand has 4 states, 4 states have (on average 39.75) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:51,285 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:21:51,286 INFO L93 Difference]: Finished difference Result 27171 states and 39183 transitions. [2021-12-15 17:21:51,287 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-15 17:21:51,287 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 27171 states and 39183 transitions. [2021-12-15 17:21:51,408 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 26939 [2021-12-15 17:21:51,492 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 27171 states to 27171 states and 39183 transitions. [2021-12-15 17:21:51,492 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 27171 [2021-12-15 17:21:51,515 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 27171 [2021-12-15 17:21:51,515 INFO L73 IsDeterministic]: Start isDeterministic. Operand 27171 states and 39183 transitions. [2021-12-15 17:21:51,539 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:21:51,539 INFO L681 BuchiCegarLoop]: Abstraction has 27171 states and 39183 transitions. [2021-12-15 17:21:51,556 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 27171 states and 39183 transitions. [2021-12-15 17:21:51,803 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 27171 to 26659. [2021-12-15 17:21:51,837 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 26659 states, 26659 states have (on average 1.443227427885517) internal successors, (38475), 26658 states have internal predecessors, (38475), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:51,892 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 26659 states to 26659 states and 38475 transitions. [2021-12-15 17:21:51,892 INFO L704 BuchiCegarLoop]: Abstraction has 26659 states and 38475 transitions. [2021-12-15 17:21:51,892 INFO L587 BuchiCegarLoop]: Abstraction has 26659 states and 38475 transitions. [2021-12-15 17:21:51,892 INFO L425 BuchiCegarLoop]: ======== Iteration 20============ [2021-12-15 17:21:51,892 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 26659 states and 38475 transitions. [2021-12-15 17:21:51,972 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 26471 [2021-12-15 17:21:51,972 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:21:51,972 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:21:51,974 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:51,974 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:51,975 INFO L791 eck$LassoCheckResult]: Stem: 132420#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 132421#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 132234#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 131947#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 131948#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 133188#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 133189#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 132083#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 132084#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 132552#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 132381#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 132382#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 132150#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 132151#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 132563#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 132745#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 132906#L936-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 132946#L941-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 132163#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 132164#L1258 assume !(0 == ~M_E~0); 133454#L1258-2 assume !(0 == ~T1_E~0); 132465#L1263-1 assume !(0 == ~T2_E~0); 132466#L1268-1 assume !(0 == ~T3_E~0); 132781#L1273-1 assume !(0 == ~T4_E~0); 133432#L1278-1 assume !(0 == ~T5_E~0); 133251#L1283-1 assume !(0 == ~T6_E~0); 133252#L1288-1 assume !(0 == ~T7_E~0); 133572#L1293-1 assume !(0 == ~T8_E~0); 133552#L1298-1 assume !(0 == ~T9_E~0); 133448#L1303-1 assume !(0 == ~T10_E~0); 131976#L1308-1 assume !(0 == ~T11_E~0); 131919#L1313-1 assume !(0 == ~T12_E~0); 131920#L1318-1 assume !(0 == ~T13_E~0); 131926#L1323-1 assume !(0 == ~E_1~0); 131927#L1328-1 assume !(0 == ~E_2~0); 132093#L1333-1 assume !(0 == ~E_3~0); 133101#L1338-1 assume !(0 == ~E_4~0); 133102#L1343-1 assume !(0 == ~E_5~0); 133224#L1348-1 assume !(0 == ~E_6~0); 133618#L1353-1 assume !(0 == ~E_7~0); 132800#L1358-1 assume !(0 == ~E_8~0); 132801#L1363-1 assume !(0 == ~E_9~0); 133127#L1368-1 assume !(0 == ~E_10~0); 131754#L1373-1 assume !(0 == ~E_11~0); 131755#L1378-1 assume !(0 == ~E_12~0); 132042#L1383-1 assume !(0 == ~E_13~0); 132043#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 132808#L607 assume !(1 == ~m_pc~0); 132112#L607-2 is_master_triggered_~__retres1~0#1 := 0; 132113#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 133219#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 132723#L1560 assume !(0 != activate_threads_~tmp~1#1); 132724#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 131939#L626 assume !(1 == ~t1_pc~0); 131940#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 132210#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 132211#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 132385#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 131837#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 131838#L645 assume !(1 == ~t2_pc~0); 131912#L645-2 is_transmit2_triggered_~__retres1~2#1 := 0; 131913#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 132604#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 132605#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 132698#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 132699#L664 assume !(1 == ~t3_pc~0); 133151#L664-2 is_transmit3_triggered_~__retres1~3#1 := 0; 131676#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 131677#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 132347#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 132348#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 133470#L683 assume !(1 == ~t4_pc~0); 132929#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 132880#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 132881#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 132916#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 133057#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 132646#L702 assume 1 == ~t5_pc~0; 132647#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 132572#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 133052#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 133413#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 133335#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 131726#L721 assume !(1 == ~t6_pc~0); 131698#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 131699#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 131865#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 132356#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 132357#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 132986#L740 assume 1 == ~t7_pc~0; 131775#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 131586#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 131587#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 131576#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 131577#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 132287#L759 assume !(1 == ~t8_pc~0); 132288#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 132318#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 133050#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 133051#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 133201#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 133571#L778 assume 1 == ~t9_pc~0; 133411#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 131753#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 131691#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 131619#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 131620#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 131953#L797 assume !(1 == ~t10_pc~0); 131954#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 132070#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 133278#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 132463#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 132464#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 132765#L816 assume 1 == ~t11_pc~0; 131656#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 131657#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 132424#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 132363#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 132364#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 132905#L835 assume 1 == ~t12_pc~0; 132778#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 131822#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 131845#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 131986#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 132523#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 132524#L854 assume !(1 == ~t13_pc~0); 132152#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 132153#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 132206#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 131863#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 131864#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 133327#L1401 assume !(1 == ~M_E~0); 132351#L1401-2 assume !(1 == ~T1_E~0); 132352#L1406-1 assume !(1 == ~T2_E~0); 132976#L1411-1 assume !(1 == ~T3_E~0); 132977#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 132619#L1421-1 assume !(1 == ~T5_E~0); 132148#L1426-1 assume !(1 == ~T6_E~0); 132149#L1431-1 assume !(1 == ~T7_E~0); 131694#L1436-1 assume !(1 == ~T8_E~0); 131695#L1441-1 assume !(1 == ~T9_E~0); 132454#L1446-1 assume !(1 == ~T10_E~0); 132455#L1451-1 assume !(1 == ~T11_E~0); 133218#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 132828#L1461-1 assume !(1 == ~T13_E~0); 132375#L1466-1 assume !(1 == ~E_1~0); 132376#L1471-1 assume !(1 == ~E_2~0); 133199#L1476-1 assume !(1 == ~E_3~0); 133200#L1481-1 assume !(1 == ~E_4~0); 133389#L1486-1 assume !(1 == ~E_5~0); 131991#L1491-1 assume !(1 == ~E_6~0); 131627#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 131628#L1501-1 assume !(1 == ~E_8~0); 132452#L1506-1 assume !(1 == ~E_9~0); 132453#L1511-1 assume !(1 == ~E_10~0); 132408#L1516-1 assume !(1 == ~E_11~0); 131572#L1521-1 assume !(1 == ~E_12~0); 131573#L1526-1 assume !(1 == ~E_13~0); 131626#L1531-1 assume { :end_inline_reset_delta_events } true; 132173#L1892-2 [2021-12-15 17:21:51,975 INFO L793 eck$LassoCheckResult]: Loop: 132173#L1892-2 assume !false; 156179#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 156178#L1233 assume !false; 156177#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 150998#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 150999#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 155054#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 150975#L1046 assume !(0 != eval_~tmp~0#1); 150976#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 157495#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 157494#L1258-3 assume !(0 == ~M_E~0); 157493#L1258-5 assume !(0 == ~T1_E~0); 157492#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 157491#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 157490#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 157489#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 157488#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 157487#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 157486#L1293-3 assume !(0 == ~T8_E~0); 157485#L1298-3 assume !(0 == ~T9_E~0); 157484#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 157483#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 157482#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 157481#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 157480#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 157479#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 157478#L1333-3 assume !(0 == ~E_3~0); 157477#L1338-3 assume !(0 == ~E_4~0); 157476#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 157475#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 157474#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 157473#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 157472#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 157471#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 157470#L1373-3 assume !(0 == ~E_11~0); 157469#L1378-3 assume !(0 == ~E_12~0); 157468#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 157467#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 157466#L607-42 assume !(1 == ~m_pc~0); 157464#L607-44 is_master_triggered_~__retres1~0#1 := 0; 157463#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 157462#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 157461#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 157460#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 157459#L626-42 assume !(1 == ~t1_pc~0); 157458#L626-44 is_transmit1_triggered_~__retres1~1#1 := 0; 157457#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 157456#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 157455#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 157454#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 157453#L645-42 assume !(1 == ~t2_pc~0); 157452#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 157451#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 157450#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 157449#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 157448#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 157447#L664-42 assume !(1 == ~t3_pc~0); 157446#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 157445#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 157444#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 157443#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 157442#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 157441#L683-42 assume 1 == ~t4_pc~0; 157440#L684-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 157438#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 157437#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 157436#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 157435#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 157434#L702-42 assume 1 == ~t5_pc~0; 157432#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 157431#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 157430#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 157429#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 157428#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 157427#L721-42 assume !(1 == ~t6_pc~0); 157426#L721-44 is_transmit6_triggered_~__retres1~6#1 := 0; 157424#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 157423#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 157422#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 157421#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 157420#L740-42 assume 1 == ~t7_pc~0; 157418#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 157417#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 157416#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 157415#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 157414#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 157413#L759-42 assume 1 == ~t8_pc~0; 157411#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 157410#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 157409#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 157408#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 157407#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 157406#L778-42 assume !(1 == ~t9_pc~0); 157404#L778-44 is_transmit9_triggered_~__retres1~9#1 := 0; 157403#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 157402#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 157401#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 157400#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 157399#L797-42 assume !(1 == ~t10_pc~0); 157398#L797-44 is_transmit10_triggered_~__retres1~10#1 := 0; 157396#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 157395#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 157394#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 157393#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 157392#L816-42 assume !(1 == ~t11_pc~0); 157390#L816-44 is_transmit11_triggered_~__retres1~11#1 := 0; 157389#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 157388#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 157387#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 157386#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 157385#L835-42 assume 1 == ~t12_pc~0; 157383#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 157382#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 157381#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 157380#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 157379#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 157378#L854-42 assume !(1 == ~t13_pc~0); 157376#L854-44 is_transmit13_triggered_~__retres1~13#1 := 0; 157375#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 157374#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 157373#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 157372#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 157371#L1401-3 assume !(1 == ~M_E~0); 156924#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 157370#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 157369#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 157368#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 157367#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 157366#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 157365#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 157364#L1436-3 assume !(1 == ~T8_E~0); 157363#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 157362#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 157361#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 157360#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 157359#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 157358#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 157357#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 157356#L1476-3 assume !(1 == ~E_3~0); 157355#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 157354#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 157353#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 157352#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 157351#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 157350#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 157349#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 157348#L1516-3 assume !(1 == ~E_11~0); 157347#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 157346#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 157345#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 156220#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 156213#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 156209#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 156207#L1911 assume !(0 == start_simulation_~tmp~3#1); 156206#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 156205#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 156191#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 156190#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 156189#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 156188#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 156187#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 156186#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 132173#L1892-2 [2021-12-15 17:21:51,975 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:51,975 INFO L85 PathProgramCache]: Analyzing trace with hash -1313062157, now seen corresponding path program 1 times [2021-12-15 17:21:51,975 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:51,975 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1008205930] [2021-12-15 17:21:51,975 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:51,975 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:51,989 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:52,010 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:52,011 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:52,011 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1008205930] [2021-12-15 17:21:52,011 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1008205930] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:52,011 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:52,011 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-15 17:21:52,011 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1039871251] [2021-12-15 17:21:52,011 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:52,011 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:21:52,011 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:52,012 INFO L85 PathProgramCache]: Analyzing trace with hash 2049985828, now seen corresponding path program 1 times [2021-12-15 17:21:52,012 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:52,012 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1202584245] [2021-12-15 17:21:52,012 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:52,012 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:52,019 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:52,038 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:52,038 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:52,038 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1202584245] [2021-12-15 17:21:52,038 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1202584245] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:52,038 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:52,038 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-15 17:21:52,038 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1113063047] [2021-12-15 17:21:52,038 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:52,039 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:21:52,039 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:21:52,039 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-15 17:21:52,039 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-15 17:21:52,039 INFO L87 Difference]: Start difference. First operand 26659 states and 38475 transitions. cyclomatic complexity: 11820 Second operand has 5 states, 5 states have (on average 31.8) internal successors, (159), 5 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:52,527 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:21:52,527 INFO L93 Difference]: Finished difference Result 71836 states and 104063 transitions. [2021-12-15 17:21:52,528 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-15 17:21:52,528 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 71836 states and 104063 transitions. [2021-12-15 17:21:52,822 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 71425 [2021-12-15 17:21:53,032 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 71836 states to 71836 states and 104063 transitions. [2021-12-15 17:21:53,032 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 71836 [2021-12-15 17:21:53,075 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 71836 [2021-12-15 17:21:53,075 INFO L73 IsDeterministic]: Start isDeterministic. Operand 71836 states and 104063 transitions. [2021-12-15 17:21:53,128 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:21:53,128 INFO L681 BuchiCegarLoop]: Abstraction has 71836 states and 104063 transitions. [2021-12-15 17:21:53,164 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 71836 states and 104063 transitions. [2021-12-15 17:21:53,718 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 71836 to 27343. [2021-12-15 17:21:53,744 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 27343 states, 27343 states have (on average 1.4321398529788245) internal successors, (39159), 27342 states have internal predecessors, (39159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:53,788 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 27343 states to 27343 states and 39159 transitions. [2021-12-15 17:21:53,789 INFO L704 BuchiCegarLoop]: Abstraction has 27343 states and 39159 transitions. [2021-12-15 17:21:53,789 INFO L587 BuchiCegarLoop]: Abstraction has 27343 states and 39159 transitions. [2021-12-15 17:21:53,789 INFO L425 BuchiCegarLoop]: ======== Iteration 21============ [2021-12-15 17:21:53,789 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 27343 states and 39159 transitions. [2021-12-15 17:21:53,861 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 27152 [2021-12-15 17:21:53,861 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:21:53,862 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:21:53,864 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:53,864 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:53,865 INFO L791 eck$LassoCheckResult]: Stem: 230924#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 230925#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 230738#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 230450#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 230451#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 231719#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 231720#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 230587#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 230588#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 231061#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 230884#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 230885#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 230654#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 230655#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 231073#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 231260#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 231426#L936-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 231466#L941-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 230667#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 230668#L1258 assume !(0 == ~M_E~0); 232009#L1258-2 assume !(0 == ~T1_E~0); 230971#L1263-1 assume !(0 == ~T2_E~0); 230972#L1268-1 assume !(0 == ~T3_E~0); 231297#L1273-1 assume !(0 == ~T4_E~0); 231986#L1278-1 assume !(0 == ~T5_E~0); 231786#L1283-1 assume !(0 == ~T6_E~0); 231787#L1288-1 assume !(0 == ~T7_E~0); 232140#L1293-1 assume !(0 == ~T8_E~0); 232121#L1298-1 assume !(0 == ~T9_E~0); 232001#L1303-1 assume !(0 == ~T10_E~0); 230479#L1308-1 assume !(0 == ~T11_E~0); 230422#L1313-1 assume !(0 == ~T12_E~0); 230423#L1318-1 assume !(0 == ~T13_E~0); 230429#L1323-1 assume !(0 == ~E_1~0); 230430#L1328-1 assume !(0 == ~E_2~0); 230597#L1333-1 assume !(0 == ~E_3~0); 231624#L1338-1 assume !(0 == ~E_4~0); 231625#L1343-1 assume !(0 == ~E_5~0); 231755#L1348-1 assume !(0 == ~E_6~0); 232191#L1353-1 assume !(0 == ~E_7~0); 231317#L1358-1 assume !(0 == ~E_8~0); 231318#L1363-1 assume !(0 == ~E_9~0); 231655#L1368-1 assume !(0 == ~E_10~0); 230260#L1373-1 assume !(0 == ~E_11~0); 230261#L1378-1 assume !(0 == ~E_12~0); 230546#L1383-1 assume !(0 == ~E_13~0); 230547#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 231324#L607 assume !(1 == ~m_pc~0); 230616#L607-2 is_master_triggered_~__retres1~0#1 := 0; 230617#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 231750#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 231240#L1560 assume !(0 != activate_threads_~tmp~1#1); 231241#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 230442#L626 assume !(1 == ~t1_pc~0); 230443#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 230714#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 230715#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 230888#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 230342#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 230343#L645 assume !(1 == ~t2_pc~0); 230415#L645-2 is_transmit2_triggered_~__retres1~2#1 := 0; 230416#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 231113#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 231114#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 231214#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 231215#L664 assume !(1 == ~t3_pc~0); 231679#L664-2 is_transmit3_triggered_~__retres1~3#1 := 0; 230185#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 230186#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 230848#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 230849#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 232027#L683 assume !(1 == ~t4_pc~0); 231451#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 231399#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 231400#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 232212#L1592 assume !(0 != activate_threads_~tmp___3~0#1); 231575#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 231158#L702 assume 1 == ~t5_pc~0; 231159#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 231082#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 231570#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 231966#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 231884#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 230232#L721 assume !(1 == ~t6_pc~0); 230207#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 230208#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 230369#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 230858#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 230859#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 231506#L740 assume 1 == ~t7_pc~0; 230281#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 230096#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 230097#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 230086#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 230087#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 230790#L759 assume !(1 == ~t8_pc~0); 230791#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 230819#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 231568#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 231569#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 231733#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 232139#L778 assume 1 == ~t9_pc~0; 231964#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 230259#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 230200#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 230129#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 230130#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 230454#L797 assume !(1 == ~t10_pc~0); 230455#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 230574#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 231817#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 230969#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 230970#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 231281#L816 assume 1 == ~t11_pc~0; 230165#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 230166#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 230928#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 230865#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 230866#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 231425#L835 assume 1 == ~t12_pc~0; 231294#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 230327#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 230349#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 230489#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 231030#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 231031#L854 assume !(1 == ~t13_pc~0); 230656#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 230657#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 230710#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 230367#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 230368#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 231873#L1401 assume !(1 == ~M_E~0); 230852#L1401-2 assume !(1 == ~T1_E~0); 230853#L1406-1 assume !(1 == ~T2_E~0); 231494#L1411-1 assume !(1 == ~T3_E~0); 231495#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 231130#L1421-1 assume !(1 == ~T5_E~0); 230652#L1426-1 assume !(1 == ~T6_E~0); 230653#L1431-1 assume !(1 == ~T7_E~0); 230203#L1436-1 assume !(1 == ~T8_E~0); 230204#L1441-1 assume !(1 == ~T9_E~0); 230960#L1446-1 assume !(1 == ~T10_E~0); 230961#L1451-1 assume !(1 == ~T11_E~0); 231749#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 231346#L1461-1 assume !(1 == ~T13_E~0); 230878#L1466-1 assume !(1 == ~E_1~0); 230879#L1471-1 assume !(1 == ~E_2~0); 231731#L1476-1 assume !(1 == ~E_3~0); 231732#L1481-1 assume !(1 == ~E_4~0); 231940#L1486-1 assume !(1 == ~E_5~0); 230494#L1491-1 assume !(1 == ~E_6~0); 230137#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 230138#L1501-1 assume !(1 == ~E_8~0); 230958#L1506-1 assume !(1 == ~E_9~0); 230959#L1511-1 assume !(1 == ~E_10~0); 230911#L1516-1 assume !(1 == ~E_11~0); 230082#L1521-1 assume !(1 == ~E_12~0); 230083#L1526-1 assume !(1 == ~E_13~0); 230136#L1531-1 assume { :end_inline_reset_delta_events } true; 230679#L1892-2 [2021-12-15 17:21:53,865 INFO L793 eck$LassoCheckResult]: Loop: 230679#L1892-2 assume !false; 231808#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 232106#L1233 assume !false; 232067#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 231243#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 231221#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 231390#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 230179#L1046 assume !(0 != eval_~tmp~0#1); 230181#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 230215#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 231427#L1258-3 assume !(0 == ~M_E~0); 232186#L1258-5 assume !(0 == ~T1_E~0); 230355#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 230356#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 232167#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 232180#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 232181#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 230579#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 230580#L1293-3 assume !(0 == ~T8_E~0); 231803#L1298-3 assume !(0 == ~T9_E~0); 231804#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 232036#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 231802#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 231225#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 230357#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 230358#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 231929#L1333-3 assume !(0 == ~E_3~0); 230499#L1338-3 assume !(0 == ~E_4~0); 230500#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 231700#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 231937#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 231938#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 231175#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 230716#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 230717#L1373-3 assume !(0 == ~E_11~0); 231527#L1378-3 assume !(0 == ~E_12~0); 231528#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 231746#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 231747#L607-42 assume !(1 == ~m_pc~0); 231300#L607-44 is_master_triggered_~__retres1~0#1 := 0; 231008#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 231009#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 230730#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 230731#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 231282#L626-42 assume !(1 == ~t1_pc~0); 230837#L626-44 is_transmit1_triggered_~__retres1~1#1 := 0; 230838#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 231137#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 231138#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 230391#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 230392#L645-42 assume !(1 == ~t2_pc~0); 231675#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 231676#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 231895#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 231896#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 257129#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 257127#L664-42 assume !(1 == ~t3_pc~0); 257125#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 257123#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 232075#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 231464#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 231465#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 231665#L683-42 assume !(1 == ~t4_pc~0); 231328#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 231329#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 257157#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 232017#L1592-42 assume !(0 != activate_threads_~tmp___3~0#1); 232018#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 257043#L702-42 assume !(1 == ~t5_pc~0); 257042#L702-44 is_transmit5_triggered_~__retres1~5#1 := 0; 231120#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 231121#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 231921#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 230123#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 230124#L721-42 assume !(1 == ~t6_pc~0); 230277#L721-44 is_transmit6_triggered_~__retres1~6#1 := 0; 230295#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 230762#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 232156#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 230940#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 230780#L740-42 assume !(1 == ~t7_pc~0); 230514#L740-44 is_transmit7_triggered_~__retres1~7#1 := 0; 230515#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 231076#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 230920#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 230921#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 231211#L759-42 assume !(1 == ~t8_pc~0); 231053#L759-44 is_transmit8_triggered_~__retres1~8#1 := 0; 230977#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 230978#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 231062#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 231063#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 231163#L778-42 assume !(1 == ~t9_pc~0); 230992#L778-44 is_transmit9_triggered_~__retres1~9#1 := 0; 230993#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 231432#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 231330#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 231331#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 231392#L797-42 assume !(1 == ~t10_pc~0); 230522#L797-44 is_transmit10_triggered_~__retres1~10#1 := 0; 230521#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 231583#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 231996#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 231433#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 231434#L816-42 assume !(1 == ~t11_pc~0); 230074#L816-44 is_transmit11_triggered_~__retres1~11#1 := 0; 230073#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 230612#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 230613#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 230695#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 230696#L835-42 assume !(1 == ~t12_pc~0); 231003#L835-44 is_transmit12_triggered_~__retres1~12#1 := 0; 231004#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 230669#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 230670#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 231883#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 231599#L854-42 assume !(1 == ~t13_pc~0); 230610#L854-44 is_transmit13_triggered_~__retres1~13#1 := 0; 230611#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 230223#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 230224#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 230876#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 230877#L1401-3 assume !(1 == ~M_E~0); 231739#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 230457#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 230322#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 230323#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 230931#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 230932#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 230497#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 230498#L1436-3 assume !(1 == ~T8_E~0); 230088#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 230089#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 231775#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 231021#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 230659#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 230660#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 232174#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 230599#L1476-3 assume !(1 == ~E_3~0); 230600#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 231014#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 230627#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 230628#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 231059#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 231060#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 231524#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 231514#L1516-3 assume !(1 == ~E_11~0); 231515#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 231179#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 231180#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 231620#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 230434#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 231366#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 230979#L1911 assume !(0 == start_simulation_~tmp~3#1); 230980#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 231548#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 230559#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 231479#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 230264#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 230265#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 230492#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 230493#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 230679#L1892-2 [2021-12-15 17:21:53,866 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:53,866 INFO L85 PathProgramCache]: Analyzing trace with hash 1102774193, now seen corresponding path program 1 times [2021-12-15 17:21:53,866 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:53,866 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [691784920] [2021-12-15 17:21:53,866 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:53,866 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:53,875 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:53,898 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:53,898 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:53,898 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [691784920] [2021-12-15 17:21:53,898 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [691784920] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:53,899 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:53,899 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:53,899 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1558121792] [2021-12-15 17:21:53,899 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:53,899 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:21:53,899 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:53,899 INFO L85 PathProgramCache]: Analyzing trace with hash 1950881405, now seen corresponding path program 1 times [2021-12-15 17:21:53,899 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:53,899 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [899563560] [2021-12-15 17:21:53,899 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:53,900 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:53,910 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:53,933 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:53,933 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:53,933 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [899563560] [2021-12-15 17:21:53,933 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [899563560] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:53,934 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:53,934 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-15 17:21:53,934 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1697544284] [2021-12-15 17:21:53,934 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:53,934 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:21:53,934 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:21:53,935 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-15 17:21:53,935 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-15 17:21:53,935 INFO L87 Difference]: Start difference. First operand 27343 states and 39159 transitions. cyclomatic complexity: 11820 Second operand has 4 states, 4 states have (on average 39.75) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:54,413 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:21:54,413 INFO L93 Difference]: Finished difference Result 77796 states and 110798 transitions. [2021-12-15 17:21:54,413 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-15 17:21:54,414 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 77796 states and 110798 transitions. [2021-12-15 17:21:54,974 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 77458 [2021-12-15 17:21:55,117 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 77796 states to 77796 states and 110798 transitions. [2021-12-15 17:21:55,118 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 77796 [2021-12-15 17:21:55,153 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 77796 [2021-12-15 17:21:55,154 INFO L73 IsDeterministic]: Start isDeterministic. Operand 77796 states and 110798 transitions. [2021-12-15 17:21:55,192 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:21:55,192 INFO L681 BuchiCegarLoop]: Abstraction has 77796 states and 110798 transitions. [2021-12-15 17:21:55,224 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 77796 states and 110798 transitions. [2021-12-15 17:21:55,903 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 77796 to 76520. [2021-12-15 17:21:55,969 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 76520 states, 76520 states have (on average 1.4250130684788291) internal successors, (109042), 76519 states have internal predecessors, (109042), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:56,260 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 76520 states to 76520 states and 109042 transitions. [2021-12-15 17:21:56,260 INFO L704 BuchiCegarLoop]: Abstraction has 76520 states and 109042 transitions. [2021-12-15 17:21:56,260 INFO L587 BuchiCegarLoop]: Abstraction has 76520 states and 109042 transitions. [2021-12-15 17:21:56,260 INFO L425 BuchiCegarLoop]: ======== Iteration 22============ [2021-12-15 17:21:56,261 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 76520 states and 109042 transitions. [2021-12-15 17:21:56,458 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 76306 [2021-12-15 17:21:56,459 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:21:56,459 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:21:56,461 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:56,461 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:21:56,462 INFO L791 eck$LassoCheckResult]: Stem: 336076#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 336077#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 335888#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 335601#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 335602#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 336870#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 336871#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 335739#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 335740#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 336212#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 336038#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 336039#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 335807#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 335808#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 336219#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 336405#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 336573#L936-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 336614#L941-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 335820#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 335821#L1258 assume !(0 == ~M_E~0); 337156#L1258-2 assume !(0 == ~T1_E~0); 336121#L1263-1 assume !(0 == ~T2_E~0); 336122#L1268-1 assume !(0 == ~T3_E~0); 336445#L1273-1 assume !(0 == ~T4_E~0); 337135#L1278-1 assume !(0 == ~T5_E~0); 336945#L1283-1 assume !(0 == ~T6_E~0); 336946#L1288-1 assume !(0 == ~T7_E~0); 337283#L1293-1 assume !(0 == ~T8_E~0); 337264#L1298-1 assume !(0 == ~T9_E~0); 337148#L1303-1 assume !(0 == ~T10_E~0); 335628#L1308-1 assume !(0 == ~T11_E~0); 335576#L1313-1 assume !(0 == ~T12_E~0); 335577#L1318-1 assume !(0 == ~T13_E~0); 335582#L1323-1 assume !(0 == ~E_1~0); 335583#L1328-1 assume !(0 == ~E_2~0); 335749#L1333-1 assume !(0 == ~E_3~0); 336775#L1338-1 assume !(0 == ~E_4~0); 336776#L1343-1 assume !(0 == ~E_5~0); 336908#L1348-1 assume !(0 == ~E_6~0); 337326#L1353-1 assume !(0 == ~E_7~0); 336466#L1358-1 assume !(0 == ~E_8~0); 336467#L1363-1 assume !(0 == ~E_9~0); 336803#L1368-1 assume !(0 == ~E_10~0); 335410#L1373-1 assume !(0 == ~E_11~0); 335411#L1378-1 assume !(0 == ~E_12~0); 335698#L1383-1 assume !(0 == ~E_13~0); 335699#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 336474#L607 assume !(1 == ~m_pc~0); 335769#L607-2 is_master_triggered_~__retres1~0#1 := 0; 335770#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 336903#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 336381#L1560 assume !(0 != activate_threads_~tmp~1#1); 336382#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 335593#L626 assume !(1 == ~t1_pc~0); 335594#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 335866#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 335867#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 336044#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 335496#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 335497#L645 assume !(1 == ~t2_pc~0); 335566#L645-2 is_transmit2_triggered_~__retres1~2#1 := 0; 335567#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 336263#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 336264#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 336357#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 336358#L664 assume !(1 == ~t3_pc~0); 336829#L664-2 is_transmit3_triggered_~__retres1~3#1 := 0; 335338#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 335339#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 336003#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 336004#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 337172#L683 assume !(1 == ~t4_pc~0); 336597#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 336546#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 336547#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 337343#L1592 assume !(0 != activate_threads_~tmp___3~0#1); 336726#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 336308#L702 assume !(1 == ~t5_pc~0); 336228#L702-2 is_transmit5_triggered_~__retres1~5#1 := 0; 336229#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 336721#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 337120#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 337035#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 335382#L721 assume !(1 == ~t6_pc~0); 335356#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 335357#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 335520#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 336012#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 336013#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 336655#L740 assume 1 == ~t7_pc~0; 335430#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 335247#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 335248#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 335237#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 335238#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 335944#L759 assume !(1 == ~t8_pc~0); 335945#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 335974#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 336719#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 336720#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 336885#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 337281#L778 assume 1 == ~t9_pc~0; 337118#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 335409#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 335349#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 335278#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 335279#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 335606#L797 assume !(1 == ~t10_pc~0); 335607#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 335726#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 336974#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 336119#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 336120#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 336426#L816 assume 1 == ~t11_pc~0; 335314#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 335315#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 336082#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 336019#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 336020#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 336571#L835 assume 1 == ~t12_pc~0; 336442#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 335476#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 335500#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 335639#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 336180#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 336181#L854 assume !(1 == ~t13_pc~0); 335809#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 335810#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 335862#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 335518#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 335519#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 337027#L1401 assume !(1 == ~M_E~0); 336007#L1401-2 assume !(1 == ~T1_E~0); 336008#L1406-1 assume !(1 == ~T2_E~0); 336643#L1411-1 assume !(1 == ~T3_E~0); 336644#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 336276#L1421-1 assume !(1 == ~T5_E~0); 335805#L1426-1 assume !(1 == ~T6_E~0); 335806#L1431-1 assume !(1 == ~T7_E~0); 335352#L1436-1 assume !(1 == ~T8_E~0); 335353#L1441-1 assume !(1 == ~T9_E~0); 336112#L1446-1 assume !(1 == ~T10_E~0); 336113#L1451-1 assume !(1 == ~T11_E~0); 336902#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 336494#L1461-1 assume !(1 == ~T13_E~0); 336032#L1466-1 assume !(1 == ~E_1~0); 336033#L1471-1 assume !(1 == ~E_2~0); 336883#L1476-1 assume !(1 == ~E_3~0); 336884#L1481-1 assume !(1 == ~E_4~0); 337094#L1486-1 assume !(1 == ~E_5~0); 335646#L1491-1 assume !(1 == ~E_6~0); 335286#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 335287#L1501-1 assume !(1 == ~E_8~0); 336108#L1506-1 assume !(1 == ~E_9~0); 336109#L1511-1 assume !(1 == ~E_10~0); 336064#L1516-1 assume !(1 == ~E_11~0); 335235#L1521-1 assume !(1 == ~E_12~0); 335236#L1526-1 assume !(1 == ~E_13~0); 335285#L1531-1 assume { :end_inline_reset_delta_events } true; 335831#L1892-2 [2021-12-15 17:21:56,462 INFO L793 eck$LassoCheckResult]: Loop: 335831#L1892-2 assume !false; 377410#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 377409#L1233 assume !false; 377407#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 377313#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 377310#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 377308#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 377305#L1046 assume !(0 != eval_~tmp~0#1); 377304#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 377303#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 377302#L1258-3 assume !(0 == ~M_E~0); 377301#L1258-5 assume !(0 == ~T1_E~0); 377300#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 377299#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 377298#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 377297#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 377296#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 377295#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 377294#L1293-3 assume !(0 == ~T8_E~0); 377293#L1298-3 assume !(0 == ~T9_E~0); 377292#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 377291#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 377290#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 377289#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 377288#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 377287#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 377286#L1333-3 assume !(0 == ~E_3~0); 377285#L1338-3 assume !(0 == ~E_4~0); 377284#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 377282#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 377281#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 377278#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 377276#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 377274#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 377272#L1373-3 assume !(0 == ~E_11~0); 377270#L1378-3 assume !(0 == ~E_12~0); 377268#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 377266#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 377264#L607-42 assume !(1 == ~m_pc~0); 377261#L607-44 is_master_triggered_~__retres1~0#1 := 0; 377259#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 377257#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 377255#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 377253#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 377251#L626-42 assume !(1 == ~t1_pc~0); 377249#L626-44 is_transmit1_triggered_~__retres1~1#1 := 0; 377247#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 377245#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 377166#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 376518#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 376517#L645-42 assume !(1 == ~t2_pc~0); 376515#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 376513#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 376511#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 376509#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 376507#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 376504#L664-42 assume !(1 == ~t3_pc~0); 376502#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 376500#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 376498#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 376496#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 376494#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 376491#L683-42 assume !(1 == ~t4_pc~0); 376487#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 376485#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 376483#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 376481#L1592-42 assume !(0 != activate_threads_~tmp___3~0#1); 376478#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 376475#L702-42 assume !(1 == ~t5_pc~0); 376473#L702-44 is_transmit5_triggered_~__retres1~5#1 := 0; 376471#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 376469#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 376467#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 376465#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 376462#L721-42 assume !(1 == ~t6_pc~0); 376460#L721-44 is_transmit6_triggered_~__retres1~6#1 := 0; 376457#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 376455#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 376453#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 376451#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 376448#L740-42 assume 1 == ~t7_pc~0; 376445#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 376443#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 376441#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 376439#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 376438#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 376437#L759-42 assume !(1 == ~t8_pc~0); 376436#L759-44 is_transmit8_triggered_~__retres1~8#1 := 0; 376434#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 376433#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 376432#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 376431#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 376430#L778-42 assume 1 == ~t9_pc~0; 376429#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 376427#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 376426#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 376425#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 376424#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 376423#L797-42 assume 1 == ~t10_pc~0; 376421#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 376420#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 376419#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 376418#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 376417#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 376416#L816-42 assume 1 == ~t11_pc~0; 376415#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 376413#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 376412#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 376411#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 376410#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 376409#L835-42 assume 1 == ~t12_pc~0; 376407#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 376405#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 376403#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 376402#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 376401#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 376400#L854-42 assume 1 == ~t13_pc~0; 376399#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 376397#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 376396#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 376395#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 376394#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 376393#L1401-3 assume !(1 == ~M_E~0); 362711#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 376392#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 376391#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 376390#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 376389#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 376388#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 376387#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 376386#L1436-3 assume !(1 == ~T8_E~0); 376385#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 376384#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 376383#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 376382#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 376381#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 376380#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 376379#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 376378#L1476-3 assume !(1 == ~E_3~0); 376377#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 376376#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 376375#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 376374#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 376373#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 376372#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 376371#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 376370#L1516-3 assume !(1 == ~E_11~0); 376369#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 376368#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 376367#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 376355#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 376352#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 376351#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 376349#L1911 assume !(0 == start_simulation_~tmp~3#1); 376350#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 378270#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 378255#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 378252#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 378250#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 378248#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 378246#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 378244#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 335831#L1892-2 [2021-12-15 17:21:56,463 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:56,463 INFO L85 PathProgramCache]: Analyzing trace with hash -882054512, now seen corresponding path program 1 times [2021-12-15 17:21:56,463 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:56,463 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [332141075] [2021-12-15 17:21:56,463 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:56,463 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:56,471 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:56,489 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:56,489 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:56,489 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [332141075] [2021-12-15 17:21:56,490 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [332141075] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:56,490 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:56,490 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:56,490 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [215694543] [2021-12-15 17:21:56,490 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:56,490 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:21:56,491 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:21:56,491 INFO L85 PathProgramCache]: Analyzing trace with hash 1180288067, now seen corresponding path program 1 times [2021-12-15 17:21:56,491 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:21:56,491 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1009796347] [2021-12-15 17:21:56,491 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:21:56,492 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:21:56,500 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:21:56,514 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:21:56,514 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:21:56,515 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1009796347] [2021-12-15 17:21:56,515 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1009796347] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:21:56,515 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:21:56,515 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:21:56,515 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1112493645] [2021-12-15 17:21:56,515 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:21:56,516 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:21:56,516 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:21:56,516 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-15 17:21:56,516 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-15 17:21:56,517 INFO L87 Difference]: Start difference. First operand 76520 states and 109042 transitions. cyclomatic complexity: 32530 Second operand has 4 states, 4 states have (on average 39.75) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:21:57,427 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:21:57,428 INFO L93 Difference]: Finished difference Result 217901 states and 309033 transitions. [2021-12-15 17:21:57,428 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-15 17:21:57,429 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 217901 states and 309033 transitions. [2021-12-15 17:21:58,593 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 217308 [2021-12-15 17:21:59,423 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 217901 states to 217901 states and 309033 transitions. [2021-12-15 17:21:59,423 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 217901 [2021-12-15 17:21:59,482 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 217901 [2021-12-15 17:21:59,482 INFO L73 IsDeterministic]: Start isDeterministic. Operand 217901 states and 309033 transitions. [2021-12-15 17:21:59,572 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:21:59,581 INFO L681 BuchiCegarLoop]: Abstraction has 217901 states and 309033 transitions. [2021-12-15 17:21:59,688 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 217901 states and 309033 transitions. [2021-12-15 17:22:01,710 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 217901 to 214869. [2021-12-15 17:22:01,848 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 214869 states, 214869 states have (on average 1.4189715594152716) internal successors, (304893), 214868 states have internal predecessors, (304893), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:22:02,472 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 214869 states to 214869 states and 304893 transitions. [2021-12-15 17:22:02,472 INFO L704 BuchiCegarLoop]: Abstraction has 214869 states and 304893 transitions. [2021-12-15 17:22:02,472 INFO L587 BuchiCegarLoop]: Abstraction has 214869 states and 304893 transitions. [2021-12-15 17:22:02,472 INFO L425 BuchiCegarLoop]: ======== Iteration 23============ [2021-12-15 17:22:02,472 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 214869 states and 304893 transitions. [2021-12-15 17:22:03,201 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 214608 [2021-12-15 17:22:03,202 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:22:03,202 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:22:03,616 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:22:03,616 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:22:03,617 INFO L791 eck$LassoCheckResult]: Stem: 630510#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 630511#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 630318#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 630030#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 630031#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 631326#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 631327#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 630168#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 630169#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 630644#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 630469#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 630470#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 630235#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 630236#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 630651#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 630845#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 631022#L936-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 631062#L941-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 630248#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 630249#L1258 assume !(0 == ~M_E~0); 631666#L1258-2 assume !(0 == ~T1_E~0); 630555#L1263-1 assume !(0 == ~T2_E~0); 630556#L1268-1 assume !(0 == ~T3_E~0); 630886#L1273-1 assume !(0 == ~T4_E~0); 631636#L1278-1 assume !(0 == ~T5_E~0); 631413#L1283-1 assume !(0 == ~T6_E~0); 631414#L1288-1 assume !(0 == ~T7_E~0); 631815#L1293-1 assume !(0 == ~T8_E~0); 631786#L1298-1 assume !(0 == ~T9_E~0); 631653#L1303-1 assume !(0 == ~T10_E~0); 630057#L1308-1 assume !(0 == ~T11_E~0); 630005#L1313-1 assume !(0 == ~T12_E~0); 630006#L1318-1 assume !(0 == ~T13_E~0); 630011#L1323-1 assume !(0 == ~E_1~0); 630012#L1328-1 assume !(0 == ~E_2~0); 630178#L1333-1 assume !(0 == ~E_3~0); 631223#L1338-1 assume !(0 == ~E_4~0); 631224#L1343-1 assume !(0 == ~E_5~0); 631370#L1348-1 assume !(0 == ~E_6~0); 631872#L1353-1 assume !(0 == ~E_7~0); 630906#L1358-1 assume !(0 == ~E_8~0); 630907#L1363-1 assume !(0 == ~E_9~0); 631253#L1368-1 assume !(0 == ~E_10~0); 629841#L1373-1 assume !(0 == ~E_11~0); 629842#L1378-1 assume !(0 == ~E_12~0); 630126#L1383-1 assume !(0 == ~E_13~0); 630127#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 630914#L607 assume !(1 == ~m_pc~0); 630197#L607-2 is_master_triggered_~__retres1~0#1 := 0; 630198#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 631364#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 630819#L1560 assume !(0 != activate_threads_~tmp~1#1); 630820#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 630022#L626 assume !(1 == ~t1_pc~0); 630023#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 630295#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 630296#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 630475#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 629925#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 629926#L645 assume !(1 == ~t2_pc~0); 629995#L645-2 is_transmit2_triggered_~__retres1~2#1 := 0; 629996#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 630698#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 630699#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 630794#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 630795#L664 assume !(1 == ~t3_pc~0); 631282#L664-2 is_transmit3_triggered_~__retres1~3#1 := 0; 629769#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 629770#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 630434#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 630435#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 631685#L683 assume !(1 == ~t4_pc~0); 631047#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 630994#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 630995#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 631901#L1592 assume !(0 != activate_threads_~tmp___3~0#1); 631175#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 630743#L702 assume !(1 == ~t5_pc~0); 630661#L702-2 is_transmit5_triggered_~__retres1~5#1 := 0; 630662#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 631170#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 631616#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 631515#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 629813#L721 assume !(1 == ~t6_pc~0); 629787#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 629788#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 629949#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 630443#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 630444#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 631101#L740 assume !(1 == ~t7_pc~0); 631102#L740-2 is_transmit7_triggered_~__retres1~7#1 := 0; 629678#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 629679#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 629668#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 629669#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 630373#L759 assume !(1 == ~t8_pc~0); 630374#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 630404#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 631166#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 631167#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 631341#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 631813#L778 assume 1 == ~t9_pc~0; 631614#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 629840#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 629780#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 629709#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 629710#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 630035#L797 assume !(1 == ~t10_pc~0); 630036#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 630155#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 631448#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 630553#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 630554#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 630867#L816 assume 1 == ~t11_pc~0; 629745#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 629746#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 630516#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 630450#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 630451#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 631019#L835 assume 1 == ~t12_pc~0; 630881#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 629905#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 629929#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 630069#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 630612#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 630613#L854 assume !(1 == ~t13_pc~0); 630237#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 630238#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 630291#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 629947#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 629948#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 631505#L1401 assume !(1 == ~M_E~0); 630438#L1401-2 assume !(1 == ~T1_E~0); 630439#L1406-1 assume !(1 == ~T2_E~0); 631089#L1411-1 assume !(1 == ~T3_E~0); 631090#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 630711#L1421-1 assume !(1 == ~T5_E~0); 630233#L1426-1 assume !(1 == ~T6_E~0); 630234#L1431-1 assume !(1 == ~T7_E~0); 629783#L1436-1 assume !(1 == ~T8_E~0); 629784#L1441-1 assume !(1 == ~T9_E~0); 630546#L1446-1 assume !(1 == ~T10_E~0); 630547#L1451-1 assume !(1 == ~T11_E~0); 631363#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 630935#L1461-1 assume !(1 == ~T13_E~0); 630463#L1466-1 assume !(1 == ~E_1~0); 630464#L1471-1 assume !(1 == ~E_2~0); 631339#L1476-1 assume !(1 == ~E_3~0); 631340#L1481-1 assume !(1 == ~E_4~0); 631585#L1486-1 assume !(1 == ~E_5~0); 630076#L1491-1 assume !(1 == ~E_6~0); 629717#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 629718#L1501-1 assume !(1 == ~E_8~0); 630542#L1506-1 assume !(1 == ~E_9~0); 630543#L1511-1 assume !(1 == ~E_10~0); 630498#L1516-1 assume !(1 == ~E_11~0); 629666#L1521-1 assume !(1 == ~E_12~0); 629667#L1526-1 assume !(1 == ~E_13~0); 629716#L1531-1 assume { :end_inline_reset_delta_events } true; 630259#L1892-2 [2021-12-15 17:22:03,617 INFO L793 eck$LassoCheckResult]: Loop: 630259#L1892-2 assume !false; 821919#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 821918#L1233 assume !false; 821917#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 820283#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 820282#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 820281#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 820279#L1046 assume !(0 != eval_~tmp~0#1); 820278#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 820277#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 820276#L1258-3 assume !(0 == ~M_E~0); 820275#L1258-5 assume !(0 == ~T1_E~0); 820274#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 820273#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 820272#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 820271#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 820270#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 820269#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 820268#L1293-3 assume !(0 == ~T8_E~0); 820267#L1298-3 assume !(0 == ~T9_E~0); 820266#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 820265#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 820264#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 820263#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 820262#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 820261#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 820260#L1333-3 assume !(0 == ~E_3~0); 820259#L1338-3 assume !(0 == ~E_4~0); 820258#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 820257#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 820256#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 820255#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 820254#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 820253#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 820252#L1373-3 assume !(0 == ~E_11~0); 820251#L1378-3 assume !(0 == ~E_12~0); 820250#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 820249#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 809558#L607-42 assume !(1 == ~m_pc~0); 809555#L607-44 is_master_triggered_~__retres1~0#1 := 0; 809553#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 809551#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 809549#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 809547#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 809545#L626-42 assume !(1 == ~t1_pc~0); 809543#L626-44 is_transmit1_triggered_~__retres1~1#1 := 0; 809540#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 809538#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 809536#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 809534#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 809532#L645-42 assume !(1 == ~t2_pc~0); 809530#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 809527#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 809525#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 809523#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 809521#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 809519#L664-42 assume !(1 == ~t3_pc~0); 809436#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 809424#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 809415#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 809406#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 809402#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 809398#L683-42 assume 1 == ~t4_pc~0; 809393#L684-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 809386#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 809381#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 809376#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 809372#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 809367#L702-42 assume !(1 == ~t5_pc~0); 809362#L702-44 is_transmit5_triggered_~__retres1~5#1 := 0; 809355#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 809351#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 809347#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 809343#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 809340#L721-42 assume 1 == ~t6_pc~0; 809333#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 809330#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 809328#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 809245#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 809217#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 809209#L740-42 assume !(1 == ~t7_pc~0); 809203#L740-44 is_transmit7_triggered_~__retres1~7#1 := 0; 809196#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 809188#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 809183#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 809178#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 809174#L759-42 assume 1 == ~t8_pc~0; 809168#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 809163#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 809159#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 809153#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 809148#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 809143#L778-42 assume !(1 == ~t9_pc~0); 809136#L778-44 is_transmit9_triggered_~__retres1~9#1 := 0; 809131#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 809126#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 809121#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 809116#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 809110#L797-42 assume 1 == ~t10_pc~0; 809101#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 809096#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 809090#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 809083#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 809078#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 809072#L816-42 assume !(1 == ~t11_pc~0); 809065#L816-44 is_transmit11_triggered_~__retres1~11#1 := 0; 809060#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 809055#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 809050#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 809045#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 809040#L835-42 assume 1 == ~t12_pc~0; 809032#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 809027#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 809021#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 809016#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 809010#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 809004#L854-42 assume 1 == ~t13_pc~0; 808996#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 808987#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 808981#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 808975#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 808969#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 808962#L1401-3 assume !(1 == ~M_E~0); 808956#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 808951#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 808945#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 808940#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 808934#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 808929#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 808923#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 808918#L1436-3 assume !(1 == ~T8_E~0); 808913#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 808908#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 808904#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 808806#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 808803#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 808801#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 808799#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 808797#L1476-3 assume !(1 == ~E_3~0); 808795#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 808793#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 808790#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 808788#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 808786#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 808784#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 808782#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 808778#L1516-3 assume !(1 == ~E_11~0); 808776#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 808774#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 808772#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 808704#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 808696#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 808690#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 808682#L1911 assume !(0 == start_simulation_~tmp~3#1); 808683#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 822796#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 822782#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 822781#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 822780#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 822779#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 822778#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 822777#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 630259#L1892-2 [2021-12-15 17:22:03,617 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:22:03,617 INFO L85 PathProgramCache]: Analyzing trace with hash 24701935, now seen corresponding path program 1 times [2021-12-15 17:22:03,617 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:22:03,617 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1866233896] [2021-12-15 17:22:03,617 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:22:03,618 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:22:03,625 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:22:03,659 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:22:03,660 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:22:03,660 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1866233896] [2021-12-15 17:22:03,660 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1866233896] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:22:03,660 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:22:03,660 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:22:03,660 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1451928918] [2021-12-15 17:22:03,660 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:22:03,661 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:22:03,661 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:22:03,661 INFO L85 PathProgramCache]: Analyzing trace with hash -260955707, now seen corresponding path program 1 times [2021-12-15 17:22:03,661 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:22:03,661 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1983770600] [2021-12-15 17:22:03,661 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:22:03,662 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:22:03,678 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:22:03,698 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:22:03,698 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:22:03,698 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1983770600] [2021-12-15 17:22:03,698 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1983770600] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:22:03,698 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:22:03,699 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-15 17:22:03,699 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1604393952] [2021-12-15 17:22:03,699 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:22:03,699 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:22:03,699 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:22:03,700 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-15 17:22:03,700 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-15 17:22:03,700 INFO L87 Difference]: Start difference. First operand 214869 states and 304893 transitions. cyclomatic complexity: 90040 Second operand has 4 states, 4 states have (on average 39.75) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:22:05,714 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-15 17:22:05,714 INFO L93 Difference]: Finished difference Result 610382 states and 862532 transitions. [2021-12-15 17:22:05,714 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-15 17:22:05,721 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 610382 states and 862532 transitions. [2021-12-15 17:22:09,378 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 609134 [2021-12-15 17:22:11,338 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 610382 states to 610382 states and 862532 transitions. [2021-12-15 17:22:11,338 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 610382 [2021-12-15 17:22:11,615 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 610382 [2021-12-15 17:22:11,616 INFO L73 IsDeterministic]: Start isDeterministic. Operand 610382 states and 862532 transitions. [2021-12-15 17:22:11,870 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-15 17:22:11,871 INFO L681 BuchiCegarLoop]: Abstraction has 610382 states and 862532 transitions. [2021-12-15 17:22:12,140 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 610382 states and 862532 transitions. [2021-12-15 17:22:17,992 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 610382 to 603658. [2021-12-15 17:22:18,446 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 603658 states, 603658 states have (on average 1.4138469133184683) internal successors, (853480), 603657 states have internal predecessors, (853480), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-15 17:22:20,427 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 603658 states to 603658 states and 853480 transitions. [2021-12-15 17:22:20,428 INFO L704 BuchiCegarLoop]: Abstraction has 603658 states and 853480 transitions. [2021-12-15 17:22:20,428 INFO L587 BuchiCegarLoop]: Abstraction has 603658 states and 853480 transitions. [2021-12-15 17:22:20,428 INFO L425 BuchiCegarLoop]: ======== Iteration 24============ [2021-12-15 17:22:20,428 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 603658 states and 853480 transitions. [2021-12-15 17:22:22,457 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 603302 [2021-12-15 17:22:22,457 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-15 17:22:22,457 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-15 17:22:22,460 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:22:22,460 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-15 17:22:22,461 INFO L791 eck$LassoCheckResult]: Stem: 1455772#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 1455773#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 1455581#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1455294#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1455295#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 1456618#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1456619#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1455429#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1455430#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1455910#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1455732#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1455733#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1455497#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1455498#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1455917#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 1456120#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 1456298#L936-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 1456338#L941-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 1455511#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1455512#L1258 assume !(0 == ~M_E~0); 1456965#L1258-2 assume !(0 == ~T1_E~0); 1455819#L1263-1 assume !(0 == ~T2_E~0); 1455820#L1268-1 assume !(0 == ~T3_E~0); 1456163#L1273-1 assume !(0 == ~T4_E~0); 1456932#L1278-1 assume !(0 == ~T5_E~0); 1456706#L1283-1 assume !(0 == ~T6_E~0); 1456707#L1288-1 assume !(0 == ~T7_E~0); 1457101#L1293-1 assume !(0 == ~T8_E~0); 1457075#L1298-1 assume !(0 == ~T9_E~0); 1456951#L1303-1 assume !(0 == ~T10_E~0); 1455322#L1308-1 assume !(0 == ~T11_E~0); 1455269#L1313-1 assume !(0 == ~T12_E~0); 1455270#L1318-1 assume !(0 == ~T13_E~0); 1455275#L1323-1 assume !(0 == ~E_1~0); 1455276#L1328-1 assume !(0 == ~E_2~0); 1455440#L1333-1 assume !(0 == ~E_3~0); 1456508#L1338-1 assume !(0 == ~E_4~0); 1456509#L1343-1 assume !(0 == ~E_5~0); 1456662#L1348-1 assume !(0 == ~E_6~0); 1457153#L1353-1 assume !(0 == ~E_7~0); 1456183#L1358-1 assume !(0 == ~E_8~0); 1456184#L1363-1 assume !(0 == ~E_9~0); 1456537#L1368-1 assume !(0 == ~E_10~0); 1455107#L1373-1 assume !(0 == ~E_11~0); 1455108#L1378-1 assume !(0 == ~E_12~0); 1455388#L1383-1 assume !(0 == ~E_13~0); 1455389#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1456190#L607 assume !(1 == ~m_pc~0); 1455460#L607-2 is_master_triggered_~__retres1~0#1 := 0; 1455461#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1456657#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1456093#L1560 assume !(0 != activate_threads_~tmp~1#1); 1456094#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1455286#L626 assume !(1 == ~t1_pc~0); 1455287#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1455558#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1455559#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1455738#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 1455189#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1455190#L645 assume !(1 == ~t2_pc~0); 1455259#L645-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1455260#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1455967#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1455968#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 1456068#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1456069#L664 assume !(1 == ~t3_pc~0); 1456567#L664-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1455032#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1455033#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1455696#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 1455697#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1456983#L683 assume !(1 == ~t4_pc~0); 1456323#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1456271#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1456272#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1457171#L1592 assume !(0 != activate_threads_~tmp___3~0#1); 1456457#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1456012#L702 assume !(1 == ~t5_pc~0); 1455929#L702-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1455930#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1456450#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1456912#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 1456814#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1455077#L721 assume !(1 == ~t6_pc~0); 1455050#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1455051#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1455213#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1455706#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 1455707#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1456380#L740 assume !(1 == ~t7_pc~0); 1456381#L740-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1454941#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1454942#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1454931#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 1454932#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1455636#L759 assume !(1 == ~t8_pc~0); 1455637#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1455666#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1456447#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1456448#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 1456634#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1457098#L778 assume !(1 == ~t9_pc~0); 1455105#L778-2 is_transmit9_triggered_~__retres1~9#1 := 0; 1455106#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1455043#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1454972#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 1454973#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1455299#L797 assume !(1 == ~t10_pc~0); 1455300#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 1455416#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1456745#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1455817#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 1455818#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1456144#L816 assume 1 == ~t11_pc~0; 1455008#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 1455009#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1455778#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1455713#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 1455714#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1456296#L835 assume 1 == ~t12_pc~0; 1456158#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 1455171#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1455193#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1455333#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 1455877#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 1455878#L854 assume !(1 == ~t13_pc~0); 1455499#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 1455500#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 1455554#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1455211#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 1455212#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1456803#L1401 assume !(1 == ~M_E~0); 1455700#L1401-2 assume !(1 == ~T1_E~0); 1455701#L1406-1 assume !(1 == ~T2_E~0); 1456367#L1411-1 assume !(1 == ~T3_E~0); 1456368#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1455981#L1421-1 assume !(1 == ~T5_E~0); 1455495#L1426-1 assume !(1 == ~T6_E~0); 1455496#L1431-1 assume !(1 == ~T7_E~0); 1455046#L1436-1 assume !(1 == ~T8_E~0); 1455047#L1441-1 assume !(1 == ~T9_E~0); 1455810#L1446-1 assume !(1 == ~T10_E~0); 1455811#L1451-1 assume !(1 == ~T11_E~0); 1456656#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 1456210#L1461-1 assume !(1 == ~T13_E~0); 1455726#L1466-1 assume !(1 == ~E_1~0); 1455727#L1471-1 assume !(1 == ~E_2~0); 1456632#L1476-1 assume !(1 == ~E_3~0); 1456633#L1481-1 assume !(1 == ~E_4~0); 1456882#L1486-1 assume !(1 == ~E_5~0); 1455340#L1491-1 assume !(1 == ~E_6~0); 1454980#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 1454981#L1501-1 assume !(1 == ~E_8~0); 1455806#L1506-1 assume !(1 == ~E_9~0); 1455807#L1511-1 assume !(1 == ~E_10~0); 1455759#L1516-1 assume !(1 == ~E_11~0); 1454929#L1521-1 assume !(1 == ~E_12~0); 1454930#L1526-1 assume !(1 == ~E_13~0); 1454979#L1531-1 assume { :end_inline_reset_delta_events } true; 1455523#L1892-2 [2021-12-15 17:22:22,461 INFO L793 eck$LassoCheckResult]: Loop: 1455523#L1892-2 assume !false; 1843545#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1843543#L1233 assume !false; 1843540#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 1843508#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 1843504#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 1843502#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1843499#L1046 assume !(0 != eval_~tmp~0#1); 1843498#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1843497#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1843496#L1258-3 assume !(0 == ~M_E~0); 1843495#L1258-5 assume !(0 == ~T1_E~0); 1843494#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1843493#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1843492#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1843491#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1843490#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1843489#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1843488#L1293-3 assume !(0 == ~T8_E~0); 1843487#L1298-3 assume !(0 == ~T9_E~0); 1843486#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 1843485#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 1843483#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 1843482#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 1843481#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1843480#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1843479#L1333-3 assume !(0 == ~E_3~0); 1843478#L1338-3 assume !(0 == ~E_4~0); 1843477#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1843476#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1843474#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1843473#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1843472#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 1843471#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 1843470#L1373-3 assume !(0 == ~E_11~0); 1843469#L1378-3 assume !(0 == ~E_12~0); 1843468#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 1843467#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1843466#L607-42 assume !(1 == ~m_pc~0); 1843464#L607-44 is_master_triggered_~__retres1~0#1 := 0; 1843463#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1843462#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1843461#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1843460#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1843459#L626-42 assume !(1 == ~t1_pc~0); 1843458#L626-44 is_transmit1_triggered_~__retres1~1#1 := 0; 1843457#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1843456#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1843455#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1843454#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1843453#L645-42 assume !(1 == ~t2_pc~0); 1843452#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 1843450#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1843447#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1843445#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1843443#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1843441#L664-42 assume !(1 == ~t3_pc~0); 1843439#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 1843437#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1843435#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1843433#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1843431#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1843429#L683-42 assume !(1 == ~t4_pc~0); 1843425#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 1843423#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1843421#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1843419#L1592-42 assume !(0 != activate_threads_~tmp___3~0#1); 1843416#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1843414#L702-42 assume !(1 == ~t5_pc~0); 1843412#L702-44 is_transmit5_triggered_~__retres1~5#1 := 0; 1843410#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1843409#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1843406#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 1843404#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1843402#L721-42 assume !(1 == ~t6_pc~0); 1843400#L721-44 is_transmit6_triggered_~__retres1~6#1 := 0; 1843397#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1843396#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1843392#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1843390#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1843388#L740-42 assume !(1 == ~t7_pc~0); 1843386#L740-44 is_transmit7_triggered_~__retres1~7#1 := 0; 1843383#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1843381#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1843379#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1843377#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1843375#L759-42 assume 1 == ~t8_pc~0; 1843372#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 1843370#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1843368#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1843366#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1843363#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1843361#L778-42 assume !(1 == ~t9_pc~0); 1843359#L778-44 is_transmit9_triggered_~__retres1~9#1 := 0; 1843357#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1843355#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1843353#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1843351#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1843349#L797-42 assume 1 == ~t10_pc~0; 1843346#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 1843344#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1843342#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1843340#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1843337#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1843335#L816-42 assume !(1 == ~t11_pc~0); 1843332#L816-44 is_transmit11_triggered_~__retres1~11#1 := 0; 1843330#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1843328#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1843326#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 1843324#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1843322#L835-42 assume !(1 == ~t12_pc~0); 1843320#L835-44 is_transmit12_triggered_~__retres1~12#1 := 0; 1843317#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1843315#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1843313#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 1843310#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 1843308#L854-42 assume !(1 == ~t13_pc~0); 1843305#L854-44 is_transmit13_triggered_~__retres1~13#1 := 0; 1843303#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 1843301#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1843299#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 1843296#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1843294#L1401-3 assume !(1 == ~M_E~0); 1842946#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1843291#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1843289#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1843287#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1843284#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1843282#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1843280#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1843278#L1436-3 assume !(1 == ~T8_E~0); 1843276#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1843274#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 1843271#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 1843269#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 1843267#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 1843265#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1843263#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1843261#L1476-3 assume !(1 == ~E_3~0); 1843260#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1843258#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1843256#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1843252#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1843246#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1843244#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1843242#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 1843241#L1516-3 assume !(1 == ~E_11~0); 1843240#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 1843239#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 1843238#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 1843226#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 1843223#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 1843222#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 1843220#L1911 assume !(0 == start_simulation_~tmp~3#1); 1843221#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 1844390#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 1844376#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 1844375#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 1844374#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1844373#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1844372#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 1844370#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 1455523#L1892-2 [2021-12-15 17:22:22,462 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:22:22,462 INFO L85 PathProgramCache]: Analyzing trace with hash -1116945458, now seen corresponding path program 1 times [2021-12-15 17:22:22,462 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:22:22,462 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1253882676] [2021-12-15 17:22:22,462 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:22:22,464 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:22:22,500 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:22:22,535 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:22:22,536 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:22:22,536 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1253882676] [2021-12-15 17:22:22,536 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1253882676] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:22:22,536 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:22:22,536 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-15 17:22:22,536 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1320896063] [2021-12-15 17:22:22,537 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:22:22,537 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-15 17:22:22,537 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-15 17:22:22,537 INFO L85 PathProgramCache]: Analyzing trace with hash 1166844863, now seen corresponding path program 1 times [2021-12-15 17:22:22,537 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-15 17:22:22,538 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1984185754] [2021-12-15 17:22:22,538 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-15 17:22:22,538 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-15 17:22:22,546 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-15 17:22:22,563 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-15 17:22:22,564 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-15 17:22:22,564 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1984185754] [2021-12-15 17:22:22,564 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1984185754] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-15 17:22:22,564 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-15 17:22:22,564 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-15 17:22:22,564 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [77709896] [2021-12-15 17:22:22,565 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-15 17:22:22,565 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-15 17:22:22,565 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-15 17:22:22,565 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-15 17:22:22,565 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-15 17:22:22,566 INFO L87 Difference]: Start difference. First operand 603658 states and 853480 transitions. cyclomatic complexity: 249854 Second operand has 4 states, 4 states have (on average 39.75) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)