./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/pc_sfifo_3.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version c3fed411 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/pc_sfifo_3.cil.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 677126e8d6773c92cc337bfe0a3ec155f49f784424155f33a8c9c24ee0a42113 --- Real Ultimate output --- This is Ultimate 0.2.2-tmp.no-commuhash-c3fed41 [2021-12-16 10:04:22,225 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-12-16 10:04:22,227 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-12-16 10:04:22,261 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-12-16 10:04:22,261 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-12-16 10:04:22,263 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-12-16 10:04:22,265 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-12-16 10:04:22,267 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-12-16 10:04:22,268 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-12-16 10:04:22,271 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-12-16 10:04:22,272 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-12-16 10:04:22,273 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-12-16 10:04:22,273 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-12-16 10:04:22,275 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-12-16 10:04:22,276 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-12-16 10:04:22,279 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-12-16 10:04:22,280 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-12-16 10:04:22,280 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-12-16 10:04:22,282 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-12-16 10:04:22,286 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-12-16 10:04:22,287 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-12-16 10:04:22,287 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-12-16 10:04:22,288 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-12-16 10:04:22,289 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-12-16 10:04:22,294 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-12-16 10:04:22,294 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-12-16 10:04:22,294 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-12-16 10:04:22,296 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-12-16 10:04:22,296 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-12-16 10:04:22,297 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-12-16 10:04:22,297 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-12-16 10:04:22,297 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-12-16 10:04:22,298 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-12-16 10:04:22,299 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-12-16 10:04:22,300 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-12-16 10:04:22,300 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-12-16 10:04:22,301 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-12-16 10:04:22,301 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-12-16 10:04:22,301 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-12-16 10:04:22,302 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-12-16 10:04:22,302 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-12-16 10:04:22,303 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2021-12-16 10:04:22,329 INFO L113 SettingsManager]: Loading preferences was successful [2021-12-16 10:04:22,329 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-12-16 10:04:22,329 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2021-12-16 10:04:22,330 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2021-12-16 10:04:22,330 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-12-16 10:04:22,331 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-12-16 10:04:22,331 INFO L138 SettingsManager]: * Use SBE=true [2021-12-16 10:04:22,331 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2021-12-16 10:04:22,331 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2021-12-16 10:04:22,331 INFO L138 SettingsManager]: * Use old map elimination=false [2021-12-16 10:04:22,332 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2021-12-16 10:04:22,332 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2021-12-16 10:04:22,332 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2021-12-16 10:04:22,332 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-12-16 10:04:22,332 INFO L138 SettingsManager]: * sizeof long=4 [2021-12-16 10:04:22,333 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2021-12-16 10:04:22,333 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-12-16 10:04:22,333 INFO L138 SettingsManager]: * sizeof POINTER=4 [2021-12-16 10:04:22,333 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-12-16 10:04:22,333 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2021-12-16 10:04:22,333 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2021-12-16 10:04:22,333 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2021-12-16 10:04:22,334 INFO L138 SettingsManager]: * sizeof long double=12 [2021-12-16 10:04:22,334 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-12-16 10:04:22,335 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2021-12-16 10:04:22,335 INFO L138 SettingsManager]: * Use constant arrays=true [2021-12-16 10:04:22,335 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2021-12-16 10:04:22,335 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-12-16 10:04:22,335 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-12-16 10:04:22,336 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-12-16 10:04:22,336 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-12-16 10:04:22,336 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2021-12-16 10:04:22,337 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2021-12-16 10:04:22,337 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 677126e8d6773c92cc337bfe0a3ec155f49f784424155f33a8c9c24ee0a42113 [2021-12-16 10:04:22,546 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-12-16 10:04:22,559 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-12-16 10:04:22,561 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-12-16 10:04:22,561 INFO L271 PluginConnector]: Initializing CDTParser... [2021-12-16 10:04:22,562 INFO L275 PluginConnector]: CDTParser initialized [2021-12-16 10:04:22,563 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/pc_sfifo_3.cil.c [2021-12-16 10:04:22,601 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/ba410438d/a485d2dedacb428384a5ee1165daa87e/FLAGefa109fed [2021-12-16 10:04:23,004 INFO L306 CDTParser]: Found 1 translation units. [2021-12-16 10:04:23,004 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/pc_sfifo_3.cil.c [2021-12-16 10:04:23,014 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/ba410438d/a485d2dedacb428384a5ee1165daa87e/FLAGefa109fed [2021-12-16 10:04:23,025 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/ba410438d/a485d2dedacb428384a5ee1165daa87e [2021-12-16 10:04:23,027 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-12-16 10:04:23,028 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-12-16 10:04:23,029 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-12-16 10:04:23,029 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-12-16 10:04:23,032 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-12-16 10:04:23,032 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 16.12 10:04:23" (1/1) ... [2021-12-16 10:04:23,033 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@88da01a and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:04:23, skipping insertion in model container [2021-12-16 10:04:23,033 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 16.12 10:04:23" (1/1) ... [2021-12-16 10:04:23,038 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-12-16 10:04:23,066 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-12-16 10:04:23,187 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/pc_sfifo_3.cil.c[640,653] [2021-12-16 10:04:23,224 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-16 10:04:23,232 INFO L203 MainTranslator]: Completed pre-run [2021-12-16 10:04:23,240 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/pc_sfifo_3.cil.c[640,653] [2021-12-16 10:04:23,255 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-16 10:04:23,265 INFO L208 MainTranslator]: Completed translation [2021-12-16 10:04:23,279 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:04:23 WrapperNode [2021-12-16 10:04:23,279 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-12-16 10:04:23,280 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-12-16 10:04:23,281 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-12-16 10:04:23,281 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-12-16 10:04:23,286 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:04:23" (1/1) ... [2021-12-16 10:04:23,291 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:04:23" (1/1) ... [2021-12-16 10:04:23,313 INFO L137 Inliner]: procedures = 31, calls = 35, calls flagged for inlining = 30, calls inlined = 33, statements flattened = 406 [2021-12-16 10:04:23,314 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-12-16 10:04:23,314 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-12-16 10:04:23,315 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-12-16 10:04:23,315 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-12-16 10:04:23,321 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:04:23" (1/1) ... [2021-12-16 10:04:23,321 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:04:23" (1/1) ... [2021-12-16 10:04:23,323 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:04:23" (1/1) ... [2021-12-16 10:04:23,323 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:04:23" (1/1) ... [2021-12-16 10:04:23,328 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:04:23" (1/1) ... [2021-12-16 10:04:23,336 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:04:23" (1/1) ... [2021-12-16 10:04:23,338 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:04:23" (1/1) ... [2021-12-16 10:04:23,340 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-12-16 10:04:23,340 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-12-16 10:04:23,341 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-12-16 10:04:23,341 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-12-16 10:04:23,341 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:04:23" (1/1) ... [2021-12-16 10:04:23,354 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-16 10:04:23,380 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-16 10:04:23,390 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-16 10:04:23,392 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2021-12-16 10:04:23,413 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2021-12-16 10:04:23,413 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2021-12-16 10:04:23,413 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-12-16 10:04:23,413 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-12-16 10:04:23,461 INFO L236 CfgBuilder]: Building ICFG [2021-12-16 10:04:23,462 INFO L262 CfgBuilder]: Building CFG for each procedure with an implementation [2021-12-16 10:04:23,684 INFO L768 $ProcedureCfgBuilder]: dead code at ProgramPoint $Ultimate##104: assume 1 == ~q_free~0;~c_dr_st~0 := 2;~c_dr_pc~0 := 2;~a_t~0 := do_read_c_~a~0#1; [2021-12-16 10:04:23,684 INFO L768 $ProcedureCfgBuilder]: dead code at ProgramPoint $Ultimate##105: assume !(1 == ~q_free~0); [2021-12-16 10:04:23,684 INFO L277 CfgBuilder]: Performing block encoding [2021-12-16 10:04:23,689 INFO L296 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-12-16 10:04:23,689 INFO L301 CfgBuilder]: Removed 4 assume(true) statements. [2021-12-16 10:04:23,691 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 16.12 10:04:23 BoogieIcfgContainer [2021-12-16 10:04:23,691 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-12-16 10:04:23,692 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2021-12-16 10:04:23,692 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2021-12-16 10:04:23,694 INFO L275 PluginConnector]: BuchiAutomizer initialized [2021-12-16 10:04:23,695 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-16 10:04:23,695 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 16.12 10:04:23" (1/3) ... [2021-12-16 10:04:23,695 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@53be339e and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 16.12 10:04:23, skipping insertion in model container [2021-12-16 10:04:23,696 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-16 10:04:23,696 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:04:23" (2/3) ... [2021-12-16 10:04:23,696 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@53be339e and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 16.12 10:04:23, skipping insertion in model container [2021-12-16 10:04:23,696 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-16 10:04:23,696 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 16.12 10:04:23" (3/3) ... [2021-12-16 10:04:23,697 INFO L388 chiAutomizerObserver]: Analyzing ICFG pc_sfifo_3.cil.c [2021-12-16 10:04:23,738 INFO L359 BuchiCegarLoop]: Interprodecural is true [2021-12-16 10:04:23,738 INFO L360 BuchiCegarLoop]: Hoare is false [2021-12-16 10:04:23,738 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2021-12-16 10:04:23,738 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2021-12-16 10:04:23,739 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2021-12-16 10:04:23,739 INFO L364 BuchiCegarLoop]: Difference is false [2021-12-16 10:04:23,739 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2021-12-16 10:04:23,739 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2021-12-16 10:04:23,751 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 142 states, 141 states have (on average 1.5602836879432624) internal successors, (220), 141 states have internal predecessors, (220), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:04:23,772 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 102 [2021-12-16 10:04:23,772 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:04:23,772 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:04:23,778 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:23,778 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:23,778 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2021-12-16 10:04:23,779 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 142 states, 141 states have (on average 1.5602836879432624) internal successors, (220), 141 states have internal predecessors, (220), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:04:23,787 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 102 [2021-12-16 10:04:23,787 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:04:23,787 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:04:23,788 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:23,788 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:23,792 INFO L791 eck$LassoCheckResult]: Stem: 131#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~fast_clk_edge~0 := 0;~slow_clk_edge~0 := 0;~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;~t~0 := 0; 39#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~fast_clk_edge~0 := 2;~slow_clk_edge~0 := 2;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 29#L551true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1, start_simulation_~tmp___0~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;havoc start_simulation_~tmp___0~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 31#L258true assume !(1 == ~q_req_up~0); 68#L258-2true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 60#L273true assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 109#L273-2true assume !(1 == ~c_dr_i~0);~c_dr_st~0 := 2; 97#L278-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 48#L311true assume !(0 == ~q_read_ev~0); 98#L311-2true assume !(0 == ~q_write_ev~0); 76#L316-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 35#L66true assume 1 == ~p_dw_pc~0; 130#L67true assume 1 == ~fast_clk_edge~0;is_do_write_p_triggered_~__retres1~0#1 := 1; 55#L87true is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 90#L88true activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 53#L387true assume !(0 != activate_threads_~tmp~1#1); 103#L387-2true assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 82#L95true assume 1 == ~c_dr_pc~0; 116#L96true assume 1 == ~slow_clk_edge~0;is_do_read_c_triggered_~__retres1~1#1 := 1; 27#L116true is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 7#L117true activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 77#L395true assume !(0 != activate_threads_~tmp___0~1#1); 14#L395-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 33#L329true assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; 56#L329-2true assume !(1 == ~q_write_ev~0); 37#L334-1true assume { :end_inline_reset_delta_events } true; 127#L491-2true [2021-12-16 10:04:23,793 INFO L793 eck$LassoCheckResult]: Loop: 127#L491-2true assume !false; 128#L492true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 94#L435true assume !true; 144#L451true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 59#L258-3true assume !(1 == ~q_req_up~0); 106#L258-5true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 132#L311-3true assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1; 110#L311-5true assume !(0 == ~q_write_ev~0); 69#L316-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 108#L66-3true assume 1 == ~p_dw_pc~0; 91#L67-1true assume 1 == ~fast_clk_edge~0;is_do_write_p_triggered_~__retres1~0#1 := 1; 11#L87-1true is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 126#L88-1true activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 121#L387-3true assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0; 36#L387-5true assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 124#L95-3true assume 1 == ~c_dr_pc~0; 64#L96-1true assume 1 == ~slow_clk_edge~0;is_do_read_c_triggered_~__retres1~1#1 := 1; 100#L116-1true is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 95#L117-1true activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 133#L395-3true assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 20#L395-5true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 44#L329-3true assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; 85#L329-5true assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 140#L334-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 51#L291-1true assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 101#L303-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 102#L304-1true start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 78#L510true assume !(0 == start_simulation_~tmp~4#1); 8#L510-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 73#L291-2true assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 89#L303-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 93#L304-2true stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 141#L465true assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 34#L472true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 137#L473true start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 75#L523true assume !(0 != start_simulation_~tmp___0~3#1); 127#L491-2true [2021-12-16 10:04:23,798 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:23,798 INFO L85 PathProgramCache]: Analyzing trace with hash 854607455, now seen corresponding path program 1 times [2021-12-16 10:04:23,804 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:23,805 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1170767761] [2021-12-16 10:04:23,805 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:23,806 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:23,869 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:04:23,914 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:04:23,915 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:04:23,915 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1170767761] [2021-12-16 10:04:23,916 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1170767761] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:04:23,916 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:04:23,916 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:04:23,918 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1717830587] [2021-12-16 10:04:23,918 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:04:23,921 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:04:23,921 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:23,921 INFO L85 PathProgramCache]: Analyzing trace with hash 784504738, now seen corresponding path program 1 times [2021-12-16 10:04:23,922 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:23,922 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [919464745] [2021-12-16 10:04:23,922 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:23,922 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:23,928 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:04:23,935 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:04:23,936 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:04:23,936 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [919464745] [2021-12-16 10:04:23,936 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [919464745] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:04:23,936 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:04:23,937 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-16 10:04:23,937 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1761537389] [2021-12-16 10:04:23,937 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:04:23,938 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:04:23,939 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:04:23,959 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-16 10:04:23,960 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-16 10:04:23,961 INFO L87 Difference]: Start difference. First operand has 142 states, 141 states have (on average 1.5602836879432624) internal successors, (220), 141 states have internal predecessors, (220), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 8.666666666666666) internal successors, (26), 3 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:04:23,998 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:04:23,999 INFO L93 Difference]: Finished difference Result 140 states and 207 transitions. [2021-12-16 10:04:24,001 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-16 10:04:24,004 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 140 states and 207 transitions. [2021-12-16 10:04:24,009 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 98 [2021-12-16 10:04:24,018 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 140 states to 134 states and 201 transitions. [2021-12-16 10:04:24,020 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 134 [2021-12-16 10:04:24,022 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 134 [2021-12-16 10:04:24,023 INFO L73 IsDeterministic]: Start isDeterministic. Operand 134 states and 201 transitions. [2021-12-16 10:04:24,023 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:04:24,024 INFO L681 BuchiCegarLoop]: Abstraction has 134 states and 201 transitions. [2021-12-16 10:04:24,035 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 134 states and 201 transitions. [2021-12-16 10:04:24,051 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 134 to 134. [2021-12-16 10:04:24,052 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 134 states, 134 states have (on average 1.5) internal successors, (201), 133 states have internal predecessors, (201), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:04:24,055 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 134 states to 134 states and 201 transitions. [2021-12-16 10:04:24,056 INFO L704 BuchiCegarLoop]: Abstraction has 134 states and 201 transitions. [2021-12-16 10:04:24,056 INFO L587 BuchiCegarLoop]: Abstraction has 134 states and 201 transitions. [2021-12-16 10:04:24,056 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2021-12-16 10:04:24,056 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 134 states and 201 transitions. [2021-12-16 10:04:24,058 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 98 [2021-12-16 10:04:24,058 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:04:24,058 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:04:24,059 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:24,059 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:24,059 INFO L791 eck$LassoCheckResult]: Stem: 424#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~fast_clk_edge~0 := 0;~slow_clk_edge~0 := 0;~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;~t~0 := 0; 354#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~fast_clk_edge~0 := 2;~slow_clk_edge~0 := 2;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 336#L551 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1, start_simulation_~tmp___0~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;havoc start_simulation_~tmp___0~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 337#L258 assume !(1 == ~q_req_up~0); 341#L258-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 386#L273 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 387#L273-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 410#L278-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 365#L311 assume !(0 == ~q_read_ev~0); 366#L311-2 assume !(0 == ~q_write_ev~0); 396#L316-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 345#L66 assume 1 == ~p_dw_pc~0; 347#L67 assume 1 == ~fast_clk_edge~0;is_do_write_p_triggered_~__retres1~0#1 := 1; 379#L87 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 380#L88 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 375#L387 assume !(0 != activate_threads_~tmp~1#1); 376#L387-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 400#L95 assume 1 == ~c_dr_pc~0; 402#L96 assume 1 == ~slow_clk_edge~0;is_do_read_c_triggered_~__retres1~1#1 := 1; 333#L116 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 298#L117 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 299#L395 assume !(0 != activate_threads_~tmp___0~1#1); 311#L395-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 312#L329 assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; 344#L329-2 assume !(1 == ~q_write_ev~0); 350#L334-1 assume { :end_inline_reset_delta_events } true; 351#L491-2 [2021-12-16 10:04:24,059 INFO L793 eck$LassoCheckResult]: Loop: 351#L491-2 assume !false; 423#L492 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 352#L435 assume !false; 381#L411 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 382#L291 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 297#L303 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 411#L304 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 412#L415 assume !(0 != eval_~tmp___1~0#1); 420#L451 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 383#L258-3 assume !(1 == ~q_req_up~0); 385#L258-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 415#L311-3 assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1; 418#L311-5 assume !(0 == ~q_write_ev~0); 393#L316-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 394#L66-3 assume 1 == ~p_dw_pc~0; 406#L67-1 assume 1 == ~fast_clk_edge~0;is_do_write_p_triggered_~__retres1~0#1 := 1; 303#L87-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 308#L88-1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 422#L387-3 assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0; 348#L387-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 349#L95-3 assume 1 == ~c_dr_pc~0; 389#L96-1 assume 1 == ~slow_clk_edge~0;is_do_read_c_triggered_~__retres1~1#1 := 1; 390#L116-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 408#L117-1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 409#L395-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 318#L395-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 319#L329-3 assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; 361#L329-5 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 403#L334-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 372#L291-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 373#L303-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 413#L304-1 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 397#L510 assume !(0 == start_simulation_~tmp~4#1); 300#L510-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 301#L291-2 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 335#L303-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 405#L304-2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 407#L465 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 342#L472 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 343#L473 start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 395#L523 assume !(0 != start_simulation_~tmp___0~3#1); 351#L491-2 [2021-12-16 10:04:24,060 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:24,060 INFO L85 PathProgramCache]: Analyzing trace with hash 1672255905, now seen corresponding path program 1 times [2021-12-16 10:04:24,060 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:24,061 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1709565764] [2021-12-16 10:04:24,061 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:24,061 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:24,073 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:04:24,113 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:04:24,114 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:04:24,114 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1709565764] [2021-12-16 10:04:24,114 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1709565764] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:04:24,114 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:04:24,115 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:04:24,115 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1692177296] [2021-12-16 10:04:24,116 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:04:24,116 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:04:24,117 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:24,118 INFO L85 PathProgramCache]: Analyzing trace with hash 2119142840, now seen corresponding path program 1 times [2021-12-16 10:04:24,118 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:24,119 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [34207166] [2021-12-16 10:04:24,119 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:24,119 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:24,133 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:04:24,156 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:04:24,156 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:04:24,156 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [34207166] [2021-12-16 10:04:24,156 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [34207166] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:04:24,156 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:04:24,157 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-16 10:04:24,157 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1049321002] [2021-12-16 10:04:24,157 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:04:24,157 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:04:24,157 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:04:24,158 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-16 10:04:24,158 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-16 10:04:24,158 INFO L87 Difference]: Start difference. First operand 134 states and 201 transitions. cyclomatic complexity: 68 Second operand has 3 states, 3 states have (on average 8.666666666666666) internal successors, (26), 3 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:04:24,200 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:04:24,200 INFO L93 Difference]: Finished difference Result 221 states and 321 transitions. [2021-12-16 10:04:24,200 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-16 10:04:24,201 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 221 states and 321 transitions. [2021-12-16 10:04:24,206 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 186 [2021-12-16 10:04:24,207 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 221 states to 221 states and 321 transitions. [2021-12-16 10:04:24,207 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 221 [2021-12-16 10:04:24,208 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 221 [2021-12-16 10:04:24,208 INFO L73 IsDeterministic]: Start isDeterministic. Operand 221 states and 321 transitions. [2021-12-16 10:04:24,209 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:04:24,209 INFO L681 BuchiCegarLoop]: Abstraction has 221 states and 321 transitions. [2021-12-16 10:04:24,209 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 221 states and 321 transitions. [2021-12-16 10:04:24,214 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 221 to 219. [2021-12-16 10:04:24,214 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 219 states, 219 states have (on average 1.45662100456621) internal successors, (319), 218 states have internal predecessors, (319), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:04:24,217 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 219 states to 219 states and 319 transitions. [2021-12-16 10:04:24,217 INFO L704 BuchiCegarLoop]: Abstraction has 219 states and 319 transitions. [2021-12-16 10:04:24,217 INFO L587 BuchiCegarLoop]: Abstraction has 219 states and 319 transitions. [2021-12-16 10:04:24,217 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2021-12-16 10:04:24,218 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 219 states and 319 transitions. [2021-12-16 10:04:24,219 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 184 [2021-12-16 10:04:24,219 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:04:24,219 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:04:24,220 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:24,220 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:24,220 INFO L791 eck$LassoCheckResult]: Stem: 793#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~fast_clk_edge~0 := 0;~slow_clk_edge~0 := 0;~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;~t~0 := 0; 719#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~fast_clk_edge~0 := 2;~slow_clk_edge~0 := 2;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 704#L551 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1, start_simulation_~tmp___0~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;havoc start_simulation_~tmp___0~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 705#L258 assume !(1 == ~q_req_up~0); 707#L258-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 751#L273 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 752#L273-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 779#L278-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 731#L311 assume !(0 == ~q_read_ev~0); 732#L311-2 assume !(0 == ~q_write_ev~0); 761#L316-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 713#L66 assume !(1 == ~p_dw_pc~0); 714#L66-2 assume !(2 == ~p_dw_pc~0); 725#L76-1 is_do_write_p_triggered_~__retres1~0#1 := 0; 744#L87 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 745#L88 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 740#L387 assume !(0 != activate_threads_~tmp~1#1); 741#L387-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 768#L95 assume 1 == ~c_dr_pc~0; 770#L96 assume 1 == ~slow_clk_edge~0;is_do_read_c_triggered_~__retres1~1#1 := 1; 699#L116 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 662#L117 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 663#L395 assume !(0 != activate_threads_~tmp___0~1#1); 676#L395-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 677#L329 assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; 710#L329-2 assume !(1 == ~q_write_ev~0); 715#L334-1 assume { :end_inline_reset_delta_events } true; 716#L491-2 [2021-12-16 10:04:24,220 INFO L793 eck$LassoCheckResult]: Loop: 716#L491-2 assume !false; 792#L492 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 717#L435 assume !false; 746#L411 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 747#L291 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 661#L303 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 780#L304 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 781#L415 assume !(0 != eval_~tmp___1~0#1); 789#L451 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 748#L258-3 assume !(1 == ~q_req_up~0); 750#L258-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 786#L311-3 assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1; 787#L311-5 assume !(0 == ~q_write_ev~0); 758#L316-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 759#L66-3 assume !(1 == ~p_dw_pc~0); 733#L66-5 assume !(2 == ~p_dw_pc~0); 666#L76-3 is_do_write_p_triggered_~__retres1~0#1 := 0; 667#L87-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 671#L88-1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 791#L387-3 assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0; 711#L387-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 712#L95-3 assume 1 == ~c_dr_pc~0; 754#L96-1 assume 1 == ~slow_clk_edge~0;is_do_read_c_triggered_~__retres1~1#1 := 1; 755#L116-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 777#L117-1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 778#L395-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 683#L395-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 684#L329-3 assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; 724#L329-5 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 771#L334-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 737#L291-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 738#L303-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 782#L304-1 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 762#L510 assume !(0 == start_simulation_~tmp~4#1); 664#L510-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 665#L291-2 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 701#L303-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 773#L304-2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 776#L465 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 708#L472 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 709#L473 start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 760#L523 assume !(0 != start_simulation_~tmp___0~3#1); 716#L491-2 [2021-12-16 10:04:24,221 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:24,221 INFO L85 PathProgramCache]: Analyzing trace with hash -841270075, now seen corresponding path program 1 times [2021-12-16 10:04:24,221 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:24,221 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1143864717] [2021-12-16 10:04:24,221 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:24,222 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:24,230 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:04:24,251 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:04:24,251 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:04:24,251 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1143864717] [2021-12-16 10:04:24,252 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1143864717] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:04:24,252 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:04:24,252 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2021-12-16 10:04:24,252 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [248019513] [2021-12-16 10:04:24,252 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:04:24,252 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:04:24,253 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:24,253 INFO L85 PathProgramCache]: Analyzing trace with hash 1851475893, now seen corresponding path program 1 times [2021-12-16 10:04:24,253 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:24,253 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1192703674] [2021-12-16 10:04:24,254 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:24,254 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:24,262 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:04:24,282 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:04:24,282 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:04:24,282 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1192703674] [2021-12-16 10:04:24,283 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1192703674] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:04:24,283 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:04:24,283 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-16 10:04:24,283 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1665789716] [2021-12-16 10:04:24,296 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:04:24,297 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:04:24,297 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:04:24,297 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-16 10:04:24,297 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-16 10:04:24,298 INFO L87 Difference]: Start difference. First operand 219 states and 319 transitions. cyclomatic complexity: 102 Second operand has 4 states, 4 states have (on average 6.75) internal successors, (27), 4 states have internal predecessors, (27), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:04:24,401 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:04:24,401 INFO L93 Difference]: Finished difference Result 471 states and 676 transitions. [2021-12-16 10:04:24,401 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-16 10:04:24,402 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 471 states and 676 transitions. [2021-12-16 10:04:24,405 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 425 [2021-12-16 10:04:24,407 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 471 states to 471 states and 676 transitions. [2021-12-16 10:04:24,407 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 471 [2021-12-16 10:04:24,408 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 471 [2021-12-16 10:04:24,408 INFO L73 IsDeterministic]: Start isDeterministic. Operand 471 states and 676 transitions. [2021-12-16 10:04:24,410 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:04:24,410 INFO L681 BuchiCegarLoop]: Abstraction has 471 states and 676 transitions. [2021-12-16 10:04:24,410 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 471 states and 676 transitions. [2021-12-16 10:04:24,424 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 471 to 377. [2021-12-16 10:04:24,425 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 377 states, 377 states have (on average 1.4456233421750664) internal successors, (545), 376 states have internal predecessors, (545), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:04:24,426 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 377 states to 377 states and 545 transitions. [2021-12-16 10:04:24,426 INFO L704 BuchiCegarLoop]: Abstraction has 377 states and 545 transitions. [2021-12-16 10:04:24,426 INFO L587 BuchiCegarLoop]: Abstraction has 377 states and 545 transitions. [2021-12-16 10:04:24,427 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2021-12-16 10:04:24,427 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 377 states and 545 transitions. [2021-12-16 10:04:24,428 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 342 [2021-12-16 10:04:24,428 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:04:24,429 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:04:24,430 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:24,430 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:24,430 INFO L791 eck$LassoCheckResult]: Stem: 1500#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~fast_clk_edge~0 := 0;~slow_clk_edge~0 := 0;~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;~t~0 := 0; 1424#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~fast_clk_edge~0 := 2;~slow_clk_edge~0 := 2;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 1409#L551 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1, start_simulation_~tmp___0~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;havoc start_simulation_~tmp___0~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1410#L258 assume !(1 == ~q_req_up~0); 1412#L258-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1457#L273 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 1458#L273-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 1485#L278-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1436#L311 assume !(0 == ~q_read_ev~0); 1437#L311-2 assume !(0 == ~q_write_ev~0); 1468#L316-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 1418#L66 assume !(1 == ~p_dw_pc~0); 1419#L66-2 assume !(2 == ~p_dw_pc~0); 1430#L76-1 is_do_write_p_triggered_~__retres1~0#1 := 0; 1452#L87 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 1453#L88 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 1446#L387 assume !(0 != activate_threads_~tmp~1#1); 1447#L387-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 1475#L95 assume !(1 == ~c_dr_pc~0); 1476#L95-2 assume 2 == ~c_dr_pc~0; 1490#L106 assume 1 == ~q_write_ev~0;is_do_read_c_triggered_~__retres1~1#1 := 1; 1404#L116 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 1365#L117 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 1366#L395 assume !(0 != activate_threads_~tmp___0~1#1); 1379#L395-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1380#L329 assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; 1415#L329-2 assume !(1 == ~q_write_ev~0); 1422#L334-1 assume { :end_inline_reset_delta_events } true; 1423#L491-2 [2021-12-16 10:04:24,430 INFO L793 eck$LassoCheckResult]: Loop: 1423#L491-2 assume !false; 1499#L492 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 1420#L435 assume !false; 1450#L411 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 1451#L291 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 1364#L303 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 1488#L304 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 1489#L415 assume !(0 != eval_~tmp___1~0#1); 1496#L451 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1454#L258-3 assume !(1 == ~q_req_up~0); 1456#L258-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1493#L311-3 assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1; 1494#L311-5 assume !(0 == ~q_write_ev~0); 1465#L316-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 1466#L66-3 assume !(1 == ~p_dw_pc~0); 1438#L66-5 assume !(2 == ~p_dw_pc~0); 1369#L76-3 is_do_write_p_triggered_~__retres1~0#1 := 0; 1370#L87-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 1374#L88-1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 1498#L387-3 assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0; 1416#L387-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 1417#L95-3 assume !(1 == ~c_dr_pc~0); 1358#L95-5 assume !(2 == ~c_dr_pc~0); 1360#L105-3 is_do_read_c_triggered_~__retres1~1#1 := 0; 1487#L116-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 1483#L117-1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 1484#L395-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 1387#L395-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1388#L329-3 assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; 1429#L329-5 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 1477#L334-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 1442#L291-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 1443#L303-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 1486#L304-1 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 1469#L510 assume !(0 == start_simulation_~tmp~4#1); 1367#L510-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 1368#L291-2 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 1406#L303-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 1479#L304-2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 1482#L465 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 1413#L472 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1414#L473 start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 1467#L523 assume !(0 != start_simulation_~tmp___0~3#1); 1423#L491-2 [2021-12-16 10:04:24,431 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:24,431 INFO L85 PathProgramCache]: Analyzing trace with hash -1943531092, now seen corresponding path program 1 times [2021-12-16 10:04:24,432 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:24,432 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1244832515] [2021-12-16 10:04:24,432 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:24,432 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:24,440 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:04:24,466 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:04:24,467 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:04:24,467 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1244832515] [2021-12-16 10:04:24,467 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1244832515] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:04:24,467 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:04:24,468 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2021-12-16 10:04:24,468 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [937071261] [2021-12-16 10:04:24,468 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:04:24,468 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:04:24,469 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:24,469 INFO L85 PathProgramCache]: Analyzing trace with hash 1021819368, now seen corresponding path program 1 times [2021-12-16 10:04:24,469 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:24,469 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1167321809] [2021-12-16 10:04:24,469 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:24,469 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:24,477 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:04:24,494 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:04:24,494 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:04:24,495 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1167321809] [2021-12-16 10:04:24,495 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1167321809] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:04:24,495 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:04:24,495 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-16 10:04:24,495 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [948015901] [2021-12-16 10:04:24,495 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:04:24,496 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:04:24,496 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:04:24,496 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-16 10:04:24,496 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2021-12-16 10:04:24,496 INFO L87 Difference]: Start difference. First operand 377 states and 545 transitions. cyclomatic complexity: 170 Second operand has 4 states, 4 states have (on average 7.0) internal successors, (28), 4 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:04:24,557 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:04:24,558 INFO L93 Difference]: Finished difference Result 555 states and 772 transitions. [2021-12-16 10:04:24,559 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-16 10:04:24,559 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 555 states and 772 transitions. [2021-12-16 10:04:24,562 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 488 [2021-12-16 10:04:24,565 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 555 states to 555 states and 772 transitions. [2021-12-16 10:04:24,565 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 555 [2021-12-16 10:04:24,565 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 555 [2021-12-16 10:04:24,566 INFO L73 IsDeterministic]: Start isDeterministic. Operand 555 states and 772 transitions. [2021-12-16 10:04:24,567 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:04:24,567 INFO L681 BuchiCegarLoop]: Abstraction has 555 states and 772 transitions. [2021-12-16 10:04:24,567 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 555 states and 772 transitions. [2021-12-16 10:04:24,593 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 555 to 551. [2021-12-16 10:04:24,594 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 551 states, 551 states have (on average 1.3938294010889292) internal successors, (768), 550 states have internal predecessors, (768), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:04:24,595 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 551 states to 551 states and 768 transitions. [2021-12-16 10:04:24,596 INFO L704 BuchiCegarLoop]: Abstraction has 551 states and 768 transitions. [2021-12-16 10:04:24,596 INFO L587 BuchiCegarLoop]: Abstraction has 551 states and 768 transitions. [2021-12-16 10:04:24,596 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2021-12-16 10:04:24,596 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 551 states and 768 transitions. [2021-12-16 10:04:24,598 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 488 [2021-12-16 10:04:24,598 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:04:24,598 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:04:24,599 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:24,599 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:24,600 INFO L791 eck$LassoCheckResult]: Stem: 2476#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~fast_clk_edge~0 := 0;~slow_clk_edge~0 := 0;~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;~t~0 := 0; 2362#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~fast_clk_edge~0 := 2;~slow_clk_edge~0 := 2;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 2344#L551 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1, start_simulation_~tmp___0~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;havoc start_simulation_~tmp___0~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2345#L258 assume !(1 == ~q_req_up~0); 2350#L258-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2397#L273 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 2398#L273-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 2460#L278-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2376#L311 assume !(0 == ~q_read_ev~0); 2377#L311-2 assume !(0 == ~q_write_ev~0); 2413#L316-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 2356#L66 assume !(1 == ~p_dw_pc~0); 2357#L66-2 assume !(2 == ~p_dw_pc~0); 2473#L76-1 is_do_write_p_triggered_~__retres1~0#1 := 0; 2474#L87 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 2433#L88 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 2434#L387 assume !(0 != activate_threads_~tmp~1#1); 2452#L387-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 2453#L95 assume !(1 == ~c_dr_pc~0); 2454#L95-2 assume !(2 == ~c_dr_pc~0); 2455#L105-1 is_do_read_c_triggered_~__retres1~1#1 := 0; 2341#L116 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 2306#L117 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 2307#L395 assume !(0 != activate_threads_~tmp___0~1#1); 2319#L395-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2320#L329 assume !(1 == ~q_read_ev~0); 2353#L329-2 assume !(1 == ~q_write_ev~0); 2523#L334-1 assume { :end_inline_reset_delta_events } true; 2521#L491-2 [2021-12-16 10:04:24,600 INFO L793 eck$LassoCheckResult]: Loop: 2521#L491-2 assume !false; 2519#L492 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 2518#L435 assume !false; 2517#L411 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 2514#L291 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 2512#L303 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 2509#L304 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 2507#L415 assume !(0 != eval_~tmp___1~0#1); 2508#L451 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2578#L258-3 assume !(1 == ~q_req_up~0); 2576#L258-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2575#L311-3 assume !(0 == ~q_read_ev~0); 2574#L311-5 assume !(0 == ~q_write_ev~0); 2573#L316-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 2572#L66-3 assume !(1 == ~p_dw_pc~0); 2571#L66-5 assume !(2 == ~p_dw_pc~0); 2570#L76-3 is_do_write_p_triggered_~__retres1~0#1 := 0; 2569#L87-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 2567#L88-1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 2565#L387-3 assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0; 2563#L387-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 2561#L95-3 assume !(1 == ~c_dr_pc~0); 2559#L95-5 assume !(2 == ~c_dr_pc~0); 2557#L105-3 is_do_read_c_triggered_~__retres1~1#1 := 0; 2555#L116-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 2553#L117-1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 2551#L395-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 2549#L395-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2547#L329-3 assume !(1 == ~q_read_ev~0); 2545#L329-5 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 2543#L334-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 2541#L291-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 2538#L303-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 2536#L304-1 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 2533#L510 assume !(0 == start_simulation_~tmp~4#1); 2531#L510-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 2530#L291-2 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 2528#L303-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 2527#L304-2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 2526#L465 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 2525#L472 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2524#L473 start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 2522#L523 assume !(0 != start_simulation_~tmp___0~3#1); 2521#L491-2 [2021-12-16 10:04:24,601 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:24,601 INFO L85 PathProgramCache]: Analyzing trace with hash 156118895, now seen corresponding path program 1 times [2021-12-16 10:04:24,601 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:24,601 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1143870549] [2021-12-16 10:04:24,601 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:24,601 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:24,609 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:04:24,609 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-16 10:04:24,614 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:04:24,631 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-16 10:04:24,632 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:24,632 INFO L85 PathProgramCache]: Analyzing trace with hash 16715304, now seen corresponding path program 1 times [2021-12-16 10:04:24,632 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:24,632 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [403751780] [2021-12-16 10:04:24,632 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:24,633 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:24,640 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:04:24,670 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:04:24,670 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:04:24,671 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [403751780] [2021-12-16 10:04:24,671 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [403751780] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:04:24,671 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:04:24,671 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-16 10:04:24,671 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [481960930] [2021-12-16 10:04:24,671 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:04:24,671 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:04:24,671 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:04:24,672 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-16 10:04:24,672 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-16 10:04:24,672 INFO L87 Difference]: Start difference. First operand 551 states and 768 transitions. cyclomatic complexity: 221 Second operand has 5 states, 5 states have (on average 8.6) internal successors, (43), 5 states have internal predecessors, (43), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:04:24,732 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:04:24,733 INFO L93 Difference]: Finished difference Result 886 states and 1210 transitions. [2021-12-16 10:04:24,733 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2021-12-16 10:04:24,734 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 886 states and 1210 transitions. [2021-12-16 10:04:24,738 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 818 [2021-12-16 10:04:24,741 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 886 states to 886 states and 1210 transitions. [2021-12-16 10:04:24,741 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 886 [2021-12-16 10:04:24,742 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 886 [2021-12-16 10:04:24,742 INFO L73 IsDeterministic]: Start isDeterministic. Operand 886 states and 1210 transitions. [2021-12-16 10:04:24,743 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:04:24,743 INFO L681 BuchiCegarLoop]: Abstraction has 886 states and 1210 transitions. [2021-12-16 10:04:24,743 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 886 states and 1210 transitions. [2021-12-16 10:04:24,749 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 886 to 569. [2021-12-16 10:04:24,749 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 569 states, 569 states have (on average 1.3813708260105448) internal successors, (786), 568 states have internal predecessors, (786), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:04:24,751 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 569 states to 569 states and 786 transitions. [2021-12-16 10:04:24,751 INFO L704 BuchiCegarLoop]: Abstraction has 569 states and 786 transitions. [2021-12-16 10:04:24,751 INFO L587 BuchiCegarLoop]: Abstraction has 569 states and 786 transitions. [2021-12-16 10:04:24,751 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2021-12-16 10:04:24,751 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 569 states and 786 transitions. [2021-12-16 10:04:24,753 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 506 [2021-12-16 10:04:24,753 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:04:24,753 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:04:24,754 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:24,754 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:24,754 INFO L791 eck$LassoCheckResult]: Stem: 3917#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~fast_clk_edge~0 := 0;~slow_clk_edge~0 := 0;~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;~t~0 := 0; 3814#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~fast_clk_edge~0 := 2;~slow_clk_edge~0 := 2;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 3797#L551 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1, start_simulation_~tmp___0~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;havoc start_simulation_~tmp___0~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3798#L258 assume !(1 == ~q_req_up~0); 3802#L258-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3848#L273 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 3849#L273-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 3905#L278-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3827#L311 assume !(0 == ~q_read_ev~0); 3828#L311-2 assume !(0 == ~q_write_ev~0); 3863#L316-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 3806#L66 assume !(1 == ~p_dw_pc~0); 3807#L66-2 assume !(2 == ~p_dw_pc~0); 3914#L76-1 is_do_write_p_triggered_~__retres1~0#1 := 0; 3915#L87 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 3878#L88 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 3879#L387 assume !(0 != activate_threads_~tmp~1#1); 3897#L387-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 3898#L95 assume !(1 == ~c_dr_pc~0); 3899#L95-2 assume !(2 == ~c_dr_pc~0); 3900#L105-1 is_do_read_c_triggered_~__retres1~1#1 := 0; 3794#L116 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 3760#L117 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 3761#L395 assume !(0 != activate_threads_~tmp___0~1#1); 3773#L395-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3774#L329 assume !(1 == ~q_read_ev~0); 3803#L329-2 assume !(1 == ~q_write_ev~0); 3810#L334-1 assume { :end_inline_reset_delta_events } true; 3811#L491-2 [2021-12-16 10:04:24,754 INFO L793 eck$LassoCheckResult]: Loop: 3811#L491-2 assume !false; 3916#L492 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 3885#L435 assume !false; 3886#L411 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 4156#L291 assume !(0 == ~p_dw_st~0); 4157#L295 assume !(0 == ~c_dr_st~0);exists_runnable_thread_~__retres1~2#1 := 0; 4151#L303 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 4117#L304 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 4118#L415 assume !(0 != eval_~tmp___1~0#1); 4147#L451 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3845#L258-3 assume !(1 == ~q_req_up~0); 3847#L258-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3901#L311-3 assume !(0 == ~q_read_ev~0); 3906#L311-5 assume !(0 == ~q_write_ev~0); 3858#L316-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 3859#L66-3 assume !(1 == ~p_dw_pc~0); 3904#L66-5 assume !(2 == ~p_dw_pc~0); 4269#L76-3 is_do_write_p_triggered_~__retres1~0#1 := 0; 4268#L87-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 4267#L88-1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 4266#L387-3 assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0; 4264#L387-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 4262#L95-3 assume !(1 == ~c_dr_pc~0); 4260#L95-5 assume !(2 == ~c_dr_pc~0); 4258#L105-3 is_do_read_c_triggered_~__retres1~1#1 := 0; 4257#L116-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 4256#L117-1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 4255#L395-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 3781#L395-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3782#L329-3 assume !(1 == ~q_read_ev~0); 3821#L329-5 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 3874#L334-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 3832#L291-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 3833#L303-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 3896#L304-1 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 3866#L510 assume !(0 == start_simulation_~tmp~4#1); 3762#L510-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 3763#L291-2 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 4298#L303-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 4297#L304-2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 4296#L465 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 4295#L472 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4294#L473 start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 3862#L523 assume !(0 != start_simulation_~tmp___0~3#1); 3811#L491-2 [2021-12-16 10:04:24,755 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:24,755 INFO L85 PathProgramCache]: Analyzing trace with hash 156118895, now seen corresponding path program 2 times [2021-12-16 10:04:24,755 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:24,755 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2046475406] [2021-12-16 10:04:24,756 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:24,756 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:24,762 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:04:24,762 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-16 10:04:24,766 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:04:24,770 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-16 10:04:24,771 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:24,771 INFO L85 PathProgramCache]: Analyzing trace with hash 526545300, now seen corresponding path program 1 times [2021-12-16 10:04:24,771 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:24,771 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1528634761] [2021-12-16 10:04:24,771 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:24,772 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:24,779 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:04:24,810 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:04:24,810 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:04:24,811 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1528634761] [2021-12-16 10:04:24,811 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1528634761] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:04:24,811 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:04:24,811 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-16 10:04:24,811 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2131734867] [2021-12-16 10:04:24,812 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:04:24,812 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:04:24,812 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:04:24,813 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-16 10:04:24,813 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-16 10:04:24,813 INFO L87 Difference]: Start difference. First operand 569 states and 786 transitions. cyclomatic complexity: 221 Second operand has 5 states, 5 states have (on average 8.8) internal successors, (44), 5 states have internal predecessors, (44), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:04:24,861 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:04:24,861 INFO L93 Difference]: Finished difference Result 1035 states and 1424 transitions. [2021-12-16 10:04:24,862 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-16 10:04:24,862 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1035 states and 1424 transitions. [2021-12-16 10:04:24,867 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 970 [2021-12-16 10:04:24,871 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1035 states to 1035 states and 1424 transitions. [2021-12-16 10:04:24,871 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1035 [2021-12-16 10:04:24,871 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1035 [2021-12-16 10:04:24,871 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1035 states and 1424 transitions. [2021-12-16 10:04:24,872 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:04:24,872 INFO L681 BuchiCegarLoop]: Abstraction has 1035 states and 1424 transitions. [2021-12-16 10:04:24,873 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1035 states and 1424 transitions. [2021-12-16 10:04:24,879 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1035 to 587. [2021-12-16 10:04:24,879 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 587 states, 587 states have (on average 1.3560477001703577) internal successors, (796), 586 states have internal predecessors, (796), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:04:24,881 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 587 states to 587 states and 796 transitions. [2021-12-16 10:04:24,881 INFO L704 BuchiCegarLoop]: Abstraction has 587 states and 796 transitions. [2021-12-16 10:04:24,881 INFO L587 BuchiCegarLoop]: Abstraction has 587 states and 796 transitions. [2021-12-16 10:04:24,881 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2021-12-16 10:04:24,881 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 587 states and 796 transitions. [2021-12-16 10:04:24,883 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 524 [2021-12-16 10:04:24,883 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:04:24,883 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:04:24,884 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:24,884 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:24,884 INFO L791 eck$LassoCheckResult]: Stem: 5540#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~fast_clk_edge~0 := 0;~slow_clk_edge~0 := 0;~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;~t~0 := 0; 5433#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~fast_clk_edge~0 := 2;~slow_clk_edge~0 := 2;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 5416#L551 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1, start_simulation_~tmp___0~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;havoc start_simulation_~tmp___0~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5417#L258 assume !(1 == ~q_req_up~0); 5421#L258-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5470#L273 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 5471#L273-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 5528#L278-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5448#L311 assume !(0 == ~q_read_ev~0); 5449#L311-2 assume !(0 == ~q_write_ev~0); 5514#L316-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 5425#L66 assume !(1 == ~p_dw_pc~0); 5426#L66-2 assume !(2 == ~p_dw_pc~0); 5536#L76-1 is_do_write_p_triggered_~__retres1~0#1 := 0; 5537#L87 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 5504#L88 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 5505#L387 assume !(0 != activate_threads_~tmp~1#1); 5519#L387-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 5520#L95 assume !(1 == ~c_dr_pc~0); 5521#L95-2 assume !(2 == ~c_dr_pc~0); 5522#L105-1 is_do_read_c_triggered_~__retres1~1#1 := 0; 5413#L116 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 5377#L117 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 5378#L395 assume !(0 != activate_threads_~tmp___0~1#1); 5391#L395-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5392#L329 assume !(1 == ~q_read_ev~0); 5422#L329-2 assume !(1 == ~q_write_ev~0); 5463#L334-1 assume { :end_inline_reset_delta_events } true; 5692#L491-2 [2021-12-16 10:04:24,885 INFO L793 eck$LassoCheckResult]: Loop: 5692#L491-2 assume !false; 5691#L492 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 5653#L435 assume !false; 5690#L411 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 5687#L291 assume !(0 == ~p_dw_st~0); 5688#L295 assume !(0 == ~c_dr_st~0);exists_runnable_thread_~__retres1~2#1 := 0; 5689#L303 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 5679#L304 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 5680#L415 assume !(0 != eval_~tmp___1~0#1); 5747#L451 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5744#L258-3 assume !(1 == ~q_req_up~0); 5742#L258-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5741#L311-3 assume !(0 == ~q_read_ev~0); 5740#L311-5 assume !(0 == ~q_write_ev~0); 5739#L316-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 5526#L66-3 assume !(1 == ~p_dw_pc~0); 5527#L66-5 assume !(2 == ~p_dw_pc~0); 5738#L76-3 is_do_write_p_triggered_~__retres1~0#1 := 0; 5737#L87-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 5735#L88-1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 5734#L387-3 assume !(0 != activate_threads_~tmp~1#1); 5733#L387-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 5731#L95-3 assume !(1 == ~c_dr_pc~0); 5729#L95-5 assume !(2 == ~c_dr_pc~0); 5727#L105-3 is_do_read_c_triggered_~__retres1~1#1 := 0; 5725#L116-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 5723#L117-1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 5721#L395-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 5719#L395-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5717#L329-3 assume !(1 == ~q_read_ev~0); 5715#L329-5 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 5713#L334-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 5711#L291-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 5708#L303-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 5706#L304-1 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 5703#L510 assume !(0 == start_simulation_~tmp~4#1); 5701#L510-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 5700#L291-2 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 5698#L303-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 5697#L304-2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 5696#L465 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 5695#L472 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5694#L473 start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 5693#L523 assume !(0 != start_simulation_~tmp___0~3#1); 5692#L491-2 [2021-12-16 10:04:24,885 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:24,885 INFO L85 PathProgramCache]: Analyzing trace with hash 156118895, now seen corresponding path program 3 times [2021-12-16 10:04:24,885 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:24,885 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [847732027] [2021-12-16 10:04:24,886 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:24,886 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:24,891 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:04:24,891 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-16 10:04:24,894 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:04:24,898 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-16 10:04:24,898 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:24,898 INFO L85 PathProgramCache]: Analyzing trace with hash 392531794, now seen corresponding path program 1 times [2021-12-16 10:04:24,898 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:24,899 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1789067507] [2021-12-16 10:04:24,899 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:24,899 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:24,916 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:04:24,937 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:04:24,938 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:04:24,938 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1789067507] [2021-12-16 10:04:24,938 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1789067507] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:04:24,938 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:04:24,938 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:04:24,938 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1590766048] [2021-12-16 10:04:24,939 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:04:24,939 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:04:24,939 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:04:24,939 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-16 10:04:24,939 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-16 10:04:24,940 INFO L87 Difference]: Start difference. First operand 587 states and 796 transitions. cyclomatic complexity: 213 Second operand has 3 states, 3 states have (on average 14.666666666666666) internal successors, (44), 3 states have internal predecessors, (44), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:04:24,963 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:04:24,964 INFO L93 Difference]: Finished difference Result 850 states and 1119 transitions. [2021-12-16 10:04:24,964 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-16 10:04:24,965 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 850 states and 1119 transitions. [2021-12-16 10:04:24,969 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 737 [2021-12-16 10:04:24,972 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 850 states to 850 states and 1119 transitions. [2021-12-16 10:04:24,973 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 850 [2021-12-16 10:04:24,973 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 850 [2021-12-16 10:04:24,973 INFO L73 IsDeterministic]: Start isDeterministic. Operand 850 states and 1119 transitions. [2021-12-16 10:04:24,974 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:04:24,974 INFO L681 BuchiCegarLoop]: Abstraction has 850 states and 1119 transitions. [2021-12-16 10:04:24,974 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 850 states and 1119 transitions. [2021-12-16 10:04:24,981 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 850 to 850. [2021-12-16 10:04:24,982 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 850 states, 850 states have (on average 1.316470588235294) internal successors, (1119), 849 states have internal predecessors, (1119), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:04:24,984 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 850 states to 850 states and 1119 transitions. [2021-12-16 10:04:24,984 INFO L704 BuchiCegarLoop]: Abstraction has 850 states and 1119 transitions. [2021-12-16 10:04:24,984 INFO L587 BuchiCegarLoop]: Abstraction has 850 states and 1119 transitions. [2021-12-16 10:04:24,984 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2021-12-16 10:04:24,984 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 850 states and 1119 transitions. [2021-12-16 10:04:24,987 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 737 [2021-12-16 10:04:24,987 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:04:24,987 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:04:24,988 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:24,988 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:24,988 INFO L791 eck$LassoCheckResult]: Stem: 6956#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~fast_clk_edge~0 := 0;~slow_clk_edge~0 := 0;~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;~t~0 := 0; 6875#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~fast_clk_edge~0 := 2;~slow_clk_edge~0 := 2;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 6860#L551 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1, start_simulation_~tmp___0~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;havoc start_simulation_~tmp___0~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6861#L258 assume !(1 == ~q_req_up~0); 6863#L258-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6904#L273 assume !(1 == ~p_dw_i~0);~p_dw_st~0 := 2; 6905#L273-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 7662#L278-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7661#L311 assume !(0 == ~q_read_ev~0); 7660#L311-2 assume !(0 == ~q_write_ev~0); 7659#L316-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 7658#L66 assume !(1 == ~p_dw_pc~0); 6880#L66-2 assume !(2 == ~p_dw_pc~0); 6881#L76-1 is_do_write_p_triggered_~__retres1~0#1 := 0; 6954#L87 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 7656#L88 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 7655#L387 assume !(0 != activate_threads_~tmp~1#1); 7654#L387-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 7653#L95 assume !(1 == ~c_dr_pc~0); 7652#L95-2 assume !(2 == ~c_dr_pc~0); 7651#L105-1 is_do_read_c_triggered_~__retres1~1#1 := 0; 7650#L116 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 6820#L117 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 6821#L395 assume !(0 != activate_threads_~tmp___0~1#1); 6834#L395-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6835#L329 assume !(1 == ~q_read_ev~0); 6866#L329-2 assume !(1 == ~q_write_ev~0); 6873#L334-1 assume { :end_inline_reset_delta_events } true; 6874#L491-2 [2021-12-16 10:04:24,988 INFO L793 eck$LassoCheckResult]: Loop: 6874#L491-2 assume !false; 6955#L492 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 6934#L435 assume !false; 6897#L411 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 6898#L291 assume !(0 == ~p_dw_st~0); 6817#L295 assume !(0 == ~c_dr_st~0);exists_runnable_thread_~__retres1~2#1 := 0; 6819#L303 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 7518#L304 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 7502#L415 assume !(0 != eval_~tmp___1~0#1); 6959#L451 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 6901#L258-3 assume !(1 == ~q_req_up~0); 6903#L258-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 6943#L311-3 assume !(0 == ~q_read_ev~0); 6946#L311-5 assume !(0 == ~q_write_ev~0); 6912#L316-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 6913#L66-3 assume !(1 == ~p_dw_pc~0); 6890#L66-5 assume !(2 == ~p_dw_pc~0); 6824#L76-3 is_do_write_p_triggered_~__retres1~0#1 := 0; 6825#L87-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 6829#L88-1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 6953#L387-3 assume !(0 != activate_threads_~tmp~1#1); 6867#L387-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 6868#L95-3 assume !(1 == ~c_dr_pc~0); 6813#L95-5 assume !(2 == ~c_dr_pc~0); 6814#L105-3 is_do_read_c_triggered_~__retres1~1#1 := 0; 6940#L116-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 6935#L117-1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 6936#L395-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 6841#L395-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6842#L329-3 assume !(1 == ~q_read_ev~0); 6879#L329-5 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 6926#L334-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 6891#L291-1 assume !(0 == ~p_dw_st~0); 6892#L295-1 assume !(0 == ~c_dr_st~0);exists_runnable_thread_~__retres1~2#1 := 0; 6941#L303-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 6942#L304-1 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 6917#L510 assume !(0 == start_simulation_~tmp~4#1); 6822#L510-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 6823#L291-2 assume !(0 == ~p_dw_st~0); 6856#L295-2 assume !(0 == ~c_dr_st~0);exists_runnable_thread_~__retres1~2#1 := 0; 6857#L303-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 6929#L304-2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 6933#L465 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 6864#L472 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6865#L473 start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 6915#L523 assume !(0 != start_simulation_~tmp___0~3#1); 6874#L491-2 [2021-12-16 10:04:24,989 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:24,989 INFO L85 PathProgramCache]: Analyzing trace with hash -1649319439, now seen corresponding path program 1 times [2021-12-16 10:04:24,989 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:24,989 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1009934907] [2021-12-16 10:04:24,989 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:24,989 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:24,998 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:04:25,015 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:04:25,015 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:04:25,015 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1009934907] [2021-12-16 10:04:25,016 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1009934907] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:04:25,016 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:04:25,016 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:04:25,016 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1093376329] [2021-12-16 10:04:25,016 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:04:25,016 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:04:25,017 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:25,017 INFO L85 PathProgramCache]: Analyzing trace with hash 2092921140, now seen corresponding path program 1 times [2021-12-16 10:04:25,017 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:25,017 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [373976500] [2021-12-16 10:04:25,018 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:25,018 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:25,029 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:04:25,053 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:04:25,053 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:04:25,054 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [373976500] [2021-12-16 10:04:25,054 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [373976500] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:04:25,080 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:04:25,080 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:04:25,081 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1835558262] [2021-12-16 10:04:25,082 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:04:25,082 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:04:25,082 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:04:25,083 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-16 10:04:25,083 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-16 10:04:25,083 INFO L87 Difference]: Start difference. First operand 850 states and 1119 transitions. cyclomatic complexity: 276 Second operand has 3 states, 3 states have (on average 9.333333333333334) internal successors, (28), 3 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:04:25,089 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:04:25,091 INFO L93 Difference]: Finished difference Result 806 states and 1065 transitions. [2021-12-16 10:04:25,091 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-16 10:04:25,093 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 806 states and 1065 transitions. [2021-12-16 10:04:25,097 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 737 [2021-12-16 10:04:25,100 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 806 states to 806 states and 1065 transitions. [2021-12-16 10:04:25,100 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 806 [2021-12-16 10:04:25,100 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 806 [2021-12-16 10:04:25,100 INFO L73 IsDeterministic]: Start isDeterministic. Operand 806 states and 1065 transitions. [2021-12-16 10:04:25,101 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:04:25,104 INFO L681 BuchiCegarLoop]: Abstraction has 806 states and 1065 transitions. [2021-12-16 10:04:25,104 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 806 states and 1065 transitions. [2021-12-16 10:04:25,110 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 806 to 806. [2021-12-16 10:04:25,111 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 806 states, 806 states have (on average 1.3213399503722085) internal successors, (1065), 805 states have internal predecessors, (1065), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:04:25,113 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 806 states to 806 states and 1065 transitions. [2021-12-16 10:04:25,113 INFO L704 BuchiCegarLoop]: Abstraction has 806 states and 1065 transitions. [2021-12-16 10:04:25,113 INFO L587 BuchiCegarLoop]: Abstraction has 806 states and 1065 transitions. [2021-12-16 10:04:25,113 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2021-12-16 10:04:25,113 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 806 states and 1065 transitions. [2021-12-16 10:04:25,116 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 737 [2021-12-16 10:04:25,116 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:04:25,116 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:04:25,117 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:25,117 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:25,118 INFO L791 eck$LassoCheckResult]: Stem: 8640#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~fast_clk_edge~0 := 0;~slow_clk_edge~0 := 0;~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;~t~0 := 0; 8538#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~fast_clk_edge~0 := 2;~slow_clk_edge~0 := 2;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 8523#L551 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1, start_simulation_~tmp___0~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;havoc start_simulation_~tmp___0~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8524#L258 assume !(1 == ~q_req_up~0); 8526#L258-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 8581#L273 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 8626#L273-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 8627#L278-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8551#L311 assume !(0 == ~q_read_ev~0); 8552#L311-2 assume !(0 == ~q_write_ev~0); 8614#L316-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 8648#L66 assume !(1 == ~p_dw_pc~0); 8542#L66-2 assume !(2 == ~p_dw_pc~0); 8543#L76-1 is_do_write_p_triggered_~__retres1~0#1 := 0; 8564#L87 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 8565#L88 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 8558#L387 assume !(0 != activate_threads_~tmp~1#1); 8559#L387-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 8593#L95 assume !(1 == ~c_dr_pc~0); 8594#L95-2 assume !(2 == ~c_dr_pc~0); 8575#L105-1 is_do_read_c_triggered_~__retres1~1#1 := 0; 8576#L116 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 8483#L117 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 8484#L395 assume !(0 != activate_threads_~tmp___0~1#1); 8496#L395-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8497#L329 assume !(1 == ~q_read_ev~0); 8529#L329-2 assume !(1 == ~q_write_ev~0); 8979#L334-1 assume { :end_inline_reset_delta_events } true; 8978#L491-2 assume !false; 8911#L492 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 8909#L435 [2021-12-16 10:04:25,118 INFO L793 eck$LassoCheckResult]: Loop: 8909#L435 assume !false; 8907#L411 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 8904#L291 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 8902#L303 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 8900#L304 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 8898#L415 assume 0 != eval_~tmp___1~0#1; 8896#L415-1 assume 0 == ~p_dw_st~0;eval_~tmp~2#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 8894#L424 assume !(0 != eval_~tmp~2#1); 8895#L420 assume !(0 == ~c_dr_st~0); 8909#L435 [2021-12-16 10:04:25,118 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:25,118 INFO L85 PathProgramCache]: Analyzing trace with hash -293592559, now seen corresponding path program 1 times [2021-12-16 10:04:25,119 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:25,119 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [90750131] [2021-12-16 10:04:25,119 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:25,120 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:25,131 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:04:25,131 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-16 10:04:25,142 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:04:25,146 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-16 10:04:25,155 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:25,155 INFO L85 PathProgramCache]: Analyzing trace with hash 1094877037, now seen corresponding path program 1 times [2021-12-16 10:04:25,156 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:25,156 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [176330493] [2021-12-16 10:04:25,156 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:25,156 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:25,158 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:04:25,158 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-16 10:04:25,160 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:04:25,161 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-16 10:04:25,161 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:25,162 INFO L85 PathProgramCache]: Analyzing trace with hash -1470124195, now seen corresponding path program 1 times [2021-12-16 10:04:25,162 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:25,162 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [464610255] [2021-12-16 10:04:25,162 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:25,162 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:25,171 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:04:25,182 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:04:25,183 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:04:25,183 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [464610255] [2021-12-16 10:04:25,183 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [464610255] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:04:25,183 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:04:25,183 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-16 10:04:25,183 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1375979362] [2021-12-16 10:04:25,184 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:04:25,236 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:04:25,236 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-16 10:04:25,236 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-16 10:04:25,237 INFO L87 Difference]: Start difference. First operand 806 states and 1065 transitions. cyclomatic complexity: 266 Second operand has 3 states, 2 states have (on average 19.5) internal successors, (39), 3 states have internal predecessors, (39), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:04:25,260 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:04:25,260 INFO L93 Difference]: Finished difference Result 922 states and 1209 transitions. [2021-12-16 10:04:25,260 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-16 10:04:25,261 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 922 states and 1209 transitions. [2021-12-16 10:04:25,264 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 850 [2021-12-16 10:04:25,267 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 922 states to 922 states and 1209 transitions. [2021-12-16 10:04:25,267 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 922 [2021-12-16 10:04:25,268 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 922 [2021-12-16 10:04:25,268 INFO L73 IsDeterministic]: Start isDeterministic. Operand 922 states and 1209 transitions. [2021-12-16 10:04:25,269 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:04:25,269 INFO L681 BuchiCegarLoop]: Abstraction has 922 states and 1209 transitions. [2021-12-16 10:04:25,269 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 922 states and 1209 transitions. [2021-12-16 10:04:25,276 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 922 to 814. [2021-12-16 10:04:25,277 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 814 states, 814 states have (on average 1.3194103194103195) internal successors, (1074), 813 states have internal predecessors, (1074), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:04:25,279 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 814 states to 814 states and 1074 transitions. [2021-12-16 10:04:25,279 INFO L704 BuchiCegarLoop]: Abstraction has 814 states and 1074 transitions. [2021-12-16 10:04:25,279 INFO L587 BuchiCegarLoop]: Abstraction has 814 states and 1074 transitions. [2021-12-16 10:04:25,279 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2021-12-16 10:04:25,279 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 814 states and 1074 transitions. [2021-12-16 10:04:25,281 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 743 [2021-12-16 10:04:25,282 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:04:25,282 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:04:25,282 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:25,282 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:25,282 INFO L791 eck$LassoCheckResult]: Stem: 10381#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~fast_clk_edge~0 := 0;~slow_clk_edge~0 := 0;~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;~t~0 := 0; 10270#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~fast_clk_edge~0 := 2;~slow_clk_edge~0 := 2;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 10254#L551 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1, start_simulation_~tmp___0~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;havoc start_simulation_~tmp___0~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 10255#L258 assume !(1 == ~q_req_up~0); 10259#L258-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 10306#L273 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 10307#L273-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 10365#L278-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10283#L311 assume !(0 == ~q_read_ev~0); 10284#L311-2 assume !(0 == ~q_write_ev~0); 10322#L316-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 10263#L66 assume !(1 == ~p_dw_pc~0); 10264#L66-2 assume !(2 == ~p_dw_pc~0); 10378#L76-1 is_do_write_p_triggered_~__retres1~0#1 := 0; 10379#L87 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 10336#L88 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 10337#L387 assume !(0 != activate_threads_~tmp~1#1); 10354#L387-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 10355#L95 assume !(1 == ~c_dr_pc~0); 10356#L95-2 assume !(2 == ~c_dr_pc~0); 10357#L105-1 is_do_read_c_triggered_~__retres1~1#1 := 0; 10251#L116 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 10218#L117 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 10219#L395 assume !(0 != activate_threads_~tmp___0~1#1); 10231#L395-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10232#L329 assume !(1 == ~q_read_ev~0); 10260#L329-2 assume !(1 == ~q_write_ev~0); 10602#L334-1 assume { :end_inline_reset_delta_events } true; 10600#L491-2 assume !false; 10596#L492 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 10594#L435 [2021-12-16 10:04:25,282 INFO L793 eck$LassoCheckResult]: Loop: 10594#L435 assume !false; 10591#L411 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 10588#L291 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 10586#L303 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 10582#L304 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 10580#L415 assume 0 != eval_~tmp___1~0#1; 10577#L415-1 assume 0 == ~p_dw_st~0;eval_~tmp~2#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 10574#L424 assume !(0 != eval_~tmp~2#1); 10575#L420 assume 0 == ~c_dr_st~0;eval_~tmp___0~2#1 := eval_#t~nondet11#1;havoc eval_#t~nondet11#1; 10597#L439 assume !(0 != eval_~tmp___0~2#1); 10594#L435 [2021-12-16 10:04:25,283 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:25,283 INFO L85 PathProgramCache]: Analyzing trace with hash -293592559, now seen corresponding path program 2 times [2021-12-16 10:04:25,283 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:25,283 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [602813795] [2021-12-16 10:04:25,283 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:25,283 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:25,287 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:04:25,287 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-16 10:04:25,289 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:04:25,292 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-16 10:04:25,293 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:25,293 INFO L85 PathProgramCache]: Analyzing trace with hash -418551849, now seen corresponding path program 1 times [2021-12-16 10:04:25,293 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:25,293 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2123608698] [2021-12-16 10:04:25,293 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:25,293 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:25,295 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:04:25,295 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-16 10:04:25,296 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:04:25,297 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-16 10:04:25,298 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:25,298 INFO L85 PathProgramCache]: Analyzing trace with hash 1670788583, now seen corresponding path program 1 times [2021-12-16 10:04:25,298 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:25,298 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [634495734] [2021-12-16 10:04:25,298 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:25,298 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:25,302 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:04:25,307 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-16 10:04:25,310 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:04:25,314 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-16 10:04:25,979 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 16.12 10:04:25 BoogieIcfgContainer [2021-12-16 10:04:25,979 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2021-12-16 10:04:25,979 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2021-12-16 10:04:25,980 INFO L271 PluginConnector]: Initializing Witness Printer... [2021-12-16 10:04:25,980 INFO L275 PluginConnector]: Witness Printer initialized [2021-12-16 10:04:25,980 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 16.12 10:04:23" (3/4) ... [2021-12-16 10:04:25,982 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2021-12-16 10:04:26,047 INFO L141 WitnessManager]: Wrote witness to /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/witness.graphml [2021-12-16 10:04:26,047 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2021-12-16 10:04:26,048 INFO L158 Benchmark]: Toolchain (without parser) took 3019.48ms. Allocated memory was 136.3MB in the beginning and 190.8MB in the end (delta: 54.5MB). Free memory was 104.7MB in the beginning and 138.6MB in the end (delta: -33.8MB). Peak memory consumption was 21.1MB. Max. memory is 16.1GB. [2021-12-16 10:04:26,048 INFO L158 Benchmark]: CDTParser took 0.14ms. Allocated memory is still 77.6MB. Free memory was 37.0MB in the beginning and 36.9MB in the end (delta: 70.0kB). There was no memory consumed. Max. memory is 16.1GB. [2021-12-16 10:04:26,048 INFO L158 Benchmark]: CACSL2BoogieTranslator took 250.56ms. Allocated memory is still 136.3MB. Free memory was 104.4MB in the beginning and 108.9MB in the end (delta: -4.6MB). Peak memory consumption was 10.5MB. Max. memory is 16.1GB. [2021-12-16 10:04:26,048 INFO L158 Benchmark]: Boogie Procedure Inliner took 33.53ms. Allocated memory is still 136.3MB. Free memory was 108.9MB in the beginning and 106.4MB in the end (delta: 2.5MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2021-12-16 10:04:26,049 INFO L158 Benchmark]: Boogie Preprocessor took 25.41ms. Allocated memory is still 136.3MB. Free memory was 106.4MB in the beginning and 104.3MB in the end (delta: 2.1MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2021-12-16 10:04:26,049 INFO L158 Benchmark]: RCFGBuilder took 350.46ms. Allocated memory is still 136.3MB. Free memory was 104.3MB in the beginning and 85.9MB in the end (delta: 18.4MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. [2021-12-16 10:04:26,049 INFO L158 Benchmark]: BuchiAutomizer took 2287.60ms. Allocated memory was 136.3MB in the beginning and 190.8MB in the end (delta: 54.5MB). Free memory was 85.4MB in the beginning and 141.7MB in the end (delta: -56.3MB). Peak memory consumption was 67.9MB. Max. memory is 16.1GB. [2021-12-16 10:04:26,049 INFO L158 Benchmark]: Witness Printer took 67.64ms. Allocated memory is still 190.8MB. Free memory was 141.7MB in the beginning and 138.6MB in the end (delta: 3.1MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2021-12-16 10:04:26,051 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.14ms. Allocated memory is still 77.6MB. Free memory was 37.0MB in the beginning and 36.9MB in the end (delta: 70.0kB). There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 250.56ms. Allocated memory is still 136.3MB. Free memory was 104.4MB in the beginning and 108.9MB in the end (delta: -4.6MB). Peak memory consumption was 10.5MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 33.53ms. Allocated memory is still 136.3MB. Free memory was 108.9MB in the beginning and 106.4MB in the end (delta: 2.5MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * Boogie Preprocessor took 25.41ms. Allocated memory is still 136.3MB. Free memory was 106.4MB in the beginning and 104.3MB in the end (delta: 2.1MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * RCFGBuilder took 350.46ms. Allocated memory is still 136.3MB. Free memory was 104.3MB in the beginning and 85.9MB in the end (delta: 18.4MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. * BuchiAutomizer took 2287.60ms. Allocated memory was 136.3MB in the beginning and 190.8MB in the end (delta: 54.5MB). Free memory was 85.4MB in the beginning and 141.7MB in the end (delta: -56.3MB). Peak memory consumption was 67.9MB. Max. memory is 16.1GB. * Witness Printer took 67.64ms. Allocated memory is still 190.8MB. Free memory was 141.7MB in the beginning and 138.6MB in the end (delta: 3.1MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 9 terminating modules (9 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.9 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 814 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 2.2s and 10 iterations. TraceHistogramMax:1. Analysis of lassos took 1.4s. Construction of modules took 0.1s. Büchi inclusion checks took 0.2s. Highest rank in rank-based complementation 0. Minimization of det autom 9. Minimization of nondet autom 0. Automata minimization 0.1s AutomataMinimizationTime, 9 MinimizatonAttempts, 973 StatesRemovedByMinimization, 6 NontrivialMinimizations. Non-live state removal took 0.0s Buchi closure took 0.0s. Biggest automaton had 850 states and ocurred in iteration 7. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 2188 SdHoareTripleChecker+Valid, 0.3s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 2188 mSDsluCounter, 3510 SdHoareTripleChecker+Invalid, 0.2s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 1901 mSDsCounter, 76 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 228 IncrementalHoareTripleChecker+Invalid, 304 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 76 mSolverCounterUnsat, 1609 mSDtfsCounter, 228 mSolverCounterSat, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI3 SFLT0 conc1 concLT0 SILN0 SILU0 SILI5 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - FixpointNonTerminationResult [Line: 410]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite execution State at position 0 is {NULL=1} State at position 1 is {p_last_write=0, c_dr_i=1, c_dr_pc=0, a_t=0, NULL=0, \result=0, NULL=1, tmp=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@39778237=0, __retres1=0, c_num_read=0, c_dr_st=0, tmp=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@e6352f5=0, q_read_ev=2, p_dw_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@63aa9820=0, q_req_up=0, q_write_ev=2, tmp___0=0, tmp___1=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@47a60fdb=0, t=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@24aa1e17=0, p_dw_pc=0, q_free=1, __retres1=1, fast_clk_edge=2, \result=0, p_dw_st=0, __retres1=0, q_ev=0, tmp___0=0, slow_clk_edge=2, tmp=0, c_last_read=0, NULL=0, \result=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@7fdcff6e=0, kernel_st=1, p_num_write=0, q_buf_0=0, tmp___0=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@62f768e4=0, __retres1=0, \result=1} - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 410]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L24] int fast_clk_edge ; [L25] int slow_clk_edge ; [L26] int q_buf_0 ; [L27] int q_free ; [L28] int q_read_ev ; [L29] int q_write_ev ; [L30] int q_req_up ; [L31] int q_ev ; [L52] int p_num_write ; [L53] int p_last_write ; [L54] int p_dw_st ; [L55] int p_dw_pc ; [L56] int p_dw_i ; [L57] int c_num_read ; [L58] int c_last_read ; [L59] int c_dr_st ; [L60] int c_dr_pc ; [L61] int c_dr_i ; [L194] static int a_t ; [L344] static int t = 0; [L555] int __retres1 ; [L559] CALL init_model() [L539] fast_clk_edge = 2 [L540] slow_clk_edge = 2 [L541] q_free = 1 [L542] q_write_ev = 2 [L543] q_read_ev = q_write_ev [L544] p_num_write = 0 [L545] p_dw_pc = 0 [L546] p_dw_i = 1 [L547] c_num_read = 0 [L548] c_dr_pc = 0 [L549] c_dr_i = 1 [L559] RET init_model() [L560] CALL start_simulation() [L477] int kernel_st ; [L478] int tmp ; [L479] int tmp___0 ; [L483] kernel_st = 0 [L484] CALL update_channels() [L258] COND FALSE !((int )q_req_up == 1) [L484] RET update_channels() [L485] CALL init_threads() [L273] COND TRUE (int )p_dw_i == 1 [L274] p_dw_st = 0 [L278] COND TRUE (int )c_dr_i == 1 [L279] c_dr_st = 0 [L485] RET init_threads() [L486] CALL fire_delta_events() [L311] COND FALSE !((int )q_read_ev == 0) [L316] COND FALSE !((int )q_write_ev == 0) [L486] RET fire_delta_events() [L487] CALL activate_threads() [L380] int tmp ; [L381] int tmp___0 ; [L385] CALL, EXPR is_do_write_p_triggered() [L63] int __retres1 ; [L66] COND FALSE !((int )p_dw_pc == 1) [L76] COND FALSE !((int )p_dw_pc == 2) [L86] __retres1 = 0 [L88] return (__retres1); [L385] RET, EXPR is_do_write_p_triggered() [L385] tmp = is_do_write_p_triggered() [L387] COND FALSE !(\read(tmp)) [L393] CALL, EXPR is_do_read_c_triggered() [L92] int __retres1 ; [L95] COND FALSE !((int )c_dr_pc == 1) [L105] COND FALSE !((int )c_dr_pc == 2) [L115] __retres1 = 0 [L117] return (__retres1); [L393] RET, EXPR is_do_read_c_triggered() [L393] tmp___0 = is_do_read_c_triggered() [L395] COND FALSE !(\read(tmp___0)) [L487] RET activate_threads() [L488] CALL reset_delta_events() [L329] COND FALSE !((int )q_read_ev == 1) [L334] COND FALSE !((int )q_write_ev == 1) [L488] RET reset_delta_events() [L491] COND TRUE 1 [L494] kernel_st = 1 [L495] CALL eval() [L405] int tmp ; [L406] int tmp___0 ; [L407] int tmp___1 ; Loop: [L410] COND TRUE 1 [L413] CALL, EXPR exists_runnable_thread() [L288] int __retres1 ; [L291] COND TRUE (int )p_dw_st == 0 [L292] __retres1 = 1 [L304] return (__retres1); [L413] RET, EXPR exists_runnable_thread() [L413] tmp___1 = exists_runnable_thread() [L415] COND TRUE \read(tmp___1) [L420] COND TRUE (int )p_dw_st == 0 [L422] tmp = __VERIFIER_nondet_int() [L424] COND FALSE !(\read(tmp)) [L435] COND TRUE (int )c_dr_st == 0 [L437] tmp___0 = __VERIFIER_nondet_int() [L439] COND FALSE !(\read(tmp___0)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2021-12-16 10:04:26,111 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Ended with exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)