./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/token_ring.03.cil-1.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version c3fed411 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/token_ring.03.cil-1.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash e96a4dadf08c19b3d92d901d7f9116f0323f4fb1660ac2537112df0afe321751 --- Real Ultimate output --- This is Ultimate 0.2.2-tmp.no-commuhash-c3fed41 [2021-12-16 10:04:32,198 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-12-16 10:04:32,228 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-12-16 10:04:32,260 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-12-16 10:04:32,261 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-12-16 10:04:32,264 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-12-16 10:04:32,265 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-12-16 10:04:32,267 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-12-16 10:04:32,268 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-12-16 10:04:32,271 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-12-16 10:04:32,272 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-12-16 10:04:32,273 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-12-16 10:04:32,273 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-12-16 10:04:32,275 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-12-16 10:04:32,276 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-12-16 10:04:32,280 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-12-16 10:04:32,281 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-12-16 10:04:32,282 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-12-16 10:04:32,283 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-12-16 10:04:32,287 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-12-16 10:04:32,288 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-12-16 10:04:32,289 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-12-16 10:04:32,290 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-12-16 10:04:32,291 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-12-16 10:04:32,296 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-12-16 10:04:32,296 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-12-16 10:04:32,296 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-12-16 10:04:32,297 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-12-16 10:04:32,297 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-12-16 10:04:32,298 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-12-16 10:04:32,298 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-12-16 10:04:32,299 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-12-16 10:04:32,300 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-12-16 10:04:32,301 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-12-16 10:04:32,301 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-12-16 10:04:32,301 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-12-16 10:04:32,302 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-12-16 10:04:32,302 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-12-16 10:04:32,302 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-12-16 10:04:32,303 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-12-16 10:04:32,303 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-12-16 10:04:32,304 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2021-12-16 10:04:32,330 INFO L113 SettingsManager]: Loading preferences was successful [2021-12-16 10:04:32,330 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-12-16 10:04:32,331 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2021-12-16 10:04:32,331 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2021-12-16 10:04:32,332 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-12-16 10:04:32,332 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-12-16 10:04:32,332 INFO L138 SettingsManager]: * Use SBE=true [2021-12-16 10:04:32,333 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2021-12-16 10:04:32,333 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2021-12-16 10:04:32,333 INFO L138 SettingsManager]: * Use old map elimination=false [2021-12-16 10:04:32,333 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2021-12-16 10:04:32,334 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2021-12-16 10:04:32,334 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2021-12-16 10:04:32,334 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-12-16 10:04:32,334 INFO L138 SettingsManager]: * sizeof long=4 [2021-12-16 10:04:32,334 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2021-12-16 10:04:32,334 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-12-16 10:04:32,335 INFO L138 SettingsManager]: * sizeof POINTER=4 [2021-12-16 10:04:32,335 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-12-16 10:04:32,335 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2021-12-16 10:04:32,335 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2021-12-16 10:04:32,335 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2021-12-16 10:04:32,335 INFO L138 SettingsManager]: * sizeof long double=12 [2021-12-16 10:04:32,336 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-12-16 10:04:32,336 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2021-12-16 10:04:32,336 INFO L138 SettingsManager]: * Use constant arrays=true [2021-12-16 10:04:32,336 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2021-12-16 10:04:32,336 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-12-16 10:04:32,336 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-12-16 10:04:32,337 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-12-16 10:04:32,337 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-12-16 10:04:32,337 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2021-12-16 10:04:32,338 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2021-12-16 10:04:32,338 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> e96a4dadf08c19b3d92d901d7f9116f0323f4fb1660ac2537112df0afe321751 [2021-12-16 10:04:32,546 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-12-16 10:04:32,560 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-12-16 10:04:32,562 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-12-16 10:04:32,563 INFO L271 PluginConnector]: Initializing CDTParser... [2021-12-16 10:04:32,563 INFO L275 PluginConnector]: CDTParser initialized [2021-12-16 10:04:32,564 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/token_ring.03.cil-1.c [2021-12-16 10:04:32,611 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/a4201cf35/d245c264bd9a47d19490928f8ce14996/FLAG850357dca [2021-12-16 10:04:32,970 INFO L306 CDTParser]: Found 1 translation units. [2021-12-16 10:04:32,971 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.03.cil-1.c [2021-12-16 10:04:32,995 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/a4201cf35/d245c264bd9a47d19490928f8ce14996/FLAG850357dca [2021-12-16 10:04:33,404 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/a4201cf35/d245c264bd9a47d19490928f8ce14996 [2021-12-16 10:04:33,405 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-12-16 10:04:33,406 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-12-16 10:04:33,408 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-12-16 10:04:33,411 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-12-16 10:04:33,413 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-12-16 10:04:33,415 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 16.12 10:04:33" (1/1) ... [2021-12-16 10:04:33,416 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@79bdc766 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:04:33, skipping insertion in model container [2021-12-16 10:04:33,417 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 16.12 10:04:33" (1/1) ... [2021-12-16 10:04:33,421 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-12-16 10:04:33,457 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-12-16 10:04:33,590 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.03.cil-1.c[671,684] [2021-12-16 10:04:33,656 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-16 10:04:33,666 INFO L203 MainTranslator]: Completed pre-run [2021-12-16 10:04:33,674 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.03.cil-1.c[671,684] [2021-12-16 10:04:33,705 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-16 10:04:33,723 INFO L208 MainTranslator]: Completed translation [2021-12-16 10:04:33,724 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:04:33 WrapperNode [2021-12-16 10:04:33,724 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-12-16 10:04:33,725 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-12-16 10:04:33,725 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-12-16 10:04:33,725 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-12-16 10:04:33,730 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:04:33" (1/1) ... [2021-12-16 10:04:33,747 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:04:33" (1/1) ... [2021-12-16 10:04:33,784 INFO L137 Inliner]: procedures = 34, calls = 41, calls flagged for inlining = 36, calls inlined = 63, statements flattened = 825 [2021-12-16 10:04:33,785 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-12-16 10:04:33,786 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-12-16 10:04:33,786 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-12-16 10:04:33,786 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-12-16 10:04:33,792 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:04:33" (1/1) ... [2021-12-16 10:04:33,792 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:04:33" (1/1) ... [2021-12-16 10:04:33,800 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:04:33" (1/1) ... [2021-12-16 10:04:33,800 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:04:33" (1/1) ... [2021-12-16 10:04:33,813 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:04:33" (1/1) ... [2021-12-16 10:04:33,826 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:04:33" (1/1) ... [2021-12-16 10:04:33,828 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:04:33" (1/1) ... [2021-12-16 10:04:33,830 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-12-16 10:04:33,831 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-12-16 10:04:33,831 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-12-16 10:04:33,831 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-12-16 10:04:33,832 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:04:33" (1/1) ... [2021-12-16 10:04:33,836 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-16 10:04:33,853 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-16 10:04:33,864 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-16 10:04:33,879 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2021-12-16 10:04:33,894 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2021-12-16 10:04:33,894 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2021-12-16 10:04:33,894 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-12-16 10:04:33,894 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-12-16 10:04:33,954 INFO L236 CfgBuilder]: Building ICFG [2021-12-16 10:04:33,955 INFO L262 CfgBuilder]: Building CFG for each procedure with an implementation [2021-12-16 10:04:34,380 INFO L277 CfgBuilder]: Performing block encoding [2021-12-16 10:04:34,387 INFO L296 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-12-16 10:04:34,390 INFO L301 CfgBuilder]: Removed 6 assume(true) statements. [2021-12-16 10:04:34,393 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 16.12 10:04:34 BoogieIcfgContainer [2021-12-16 10:04:34,393 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-12-16 10:04:34,394 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2021-12-16 10:04:34,394 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2021-12-16 10:04:34,396 INFO L275 PluginConnector]: BuchiAutomizer initialized [2021-12-16 10:04:34,396 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-16 10:04:34,397 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 16.12 10:04:33" (1/3) ... [2021-12-16 10:04:34,398 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@790dd04f and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 16.12 10:04:34, skipping insertion in model container [2021-12-16 10:04:34,398 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-16 10:04:34,398 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:04:33" (2/3) ... [2021-12-16 10:04:34,398 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@790dd04f and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 16.12 10:04:34, skipping insertion in model container [2021-12-16 10:04:34,398 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-16 10:04:34,398 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 16.12 10:04:34" (3/3) ... [2021-12-16 10:04:34,399 INFO L388 chiAutomizerObserver]: Analyzing ICFG token_ring.03.cil-1.c [2021-12-16 10:04:34,427 INFO L359 BuchiCegarLoop]: Interprodecural is true [2021-12-16 10:04:34,428 INFO L360 BuchiCegarLoop]: Hoare is false [2021-12-16 10:04:34,428 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2021-12-16 10:04:34,428 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2021-12-16 10:04:34,428 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2021-12-16 10:04:34,428 INFO L364 BuchiCegarLoop]: Difference is false [2021-12-16 10:04:34,428 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2021-12-16 10:04:34,428 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2021-12-16 10:04:34,445 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 331 states, 330 states have (on average 1.5393939393939393) internal successors, (508), 330 states have internal predecessors, (508), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:04:34,466 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 272 [2021-12-16 10:04:34,466 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:04:34,466 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:04:34,473 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:34,473 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:34,474 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2021-12-16 10:04:34,474 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 331 states, 330 states have (on average 1.5393939393939393) internal successors, (508), 330 states have internal predecessors, (508), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:04:34,482 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 272 [2021-12-16 10:04:34,485 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:04:34,485 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:04:34,491 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:34,491 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:34,497 INFO L791 eck$LassoCheckResult]: Stem: 311#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 217#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 65#L653true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 47#L297true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 282#L304true assume !(1 == ~m_i~0);~m_st~0 := 2; 123#L304-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 25#L309-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 235#L314-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 138#L319-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 31#L441true assume !(0 == ~M_E~0); 120#L441-2true assume !(0 == ~T1_E~0); 253#L446-1true assume 0 == ~T2_E~0;~T2_E~0 := 1; 96#L451-1true assume !(0 == ~T3_E~0); 275#L456-1true assume !(0 == ~E_M~0); 226#L461-1true assume !(0 == ~E_1~0); 248#L466-1true assume !(0 == ~E_2~0); 294#L471-1true assume !(0 == ~E_3~0); 51#L476-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 88#L220true assume 1 == ~m_pc~0; 264#L221true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 105#L231true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 179#L232true activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 68#L543true assume !(0 != activate_threads_~tmp~1#1); 323#L543-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 203#L239true assume !(1 == ~t1_pc~0); 223#L239-2true is_transmit1_triggered_~__retres1~1#1 := 0; 271#L250true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 261#L251true activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 208#L551true assume !(0 != activate_threads_~tmp___0~0#1); 327#L551-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 209#L258true assume 1 == ~t2_pc~0; 246#L259true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 87#L269true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12#L270true activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 221#L559true assume !(0 != activate_threads_~tmp___1~0#1); 130#L559-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 170#L277true assume !(1 == ~t3_pc~0); 324#L277-2true is_transmit3_triggered_~__retres1~3#1 := 0; 39#L288true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 214#L289true activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 64#L567true assume !(0 != activate_threads_~tmp___2~0#1); 93#L567-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 304#L489true assume !(1 == ~M_E~0); 224#L489-2true assume !(1 == ~T1_E~0); 150#L494-1true assume 1 == ~T2_E~0;~T2_E~0 := 2; 59#L499-1true assume !(1 == ~T3_E~0); 124#L504-1true assume !(1 == ~E_M~0); 263#L509-1true assume !(1 == ~E_1~0); 52#L514-1true assume !(1 == ~E_2~0); 178#L519-1true assume !(1 == ~E_3~0); 57#L524-1true assume { :end_inline_reset_delta_events } true; 38#L690-2true [2021-12-16 10:04:34,498 INFO L793 eck$LassoCheckResult]: Loop: 38#L690-2true assume !false; 53#L691true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 22#L416true assume false; 321#L431true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 210#L297-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 195#L441-3true assume 0 == ~M_E~0;~M_E~0 := 1; 9#L441-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 255#L446-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 191#L451-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 36#L456-3true assume 0 == ~E_M~0;~E_M~0 := 1; 73#L461-3true assume 0 == ~E_1~0;~E_1~0 := 1; 154#L466-3true assume 0 == ~E_2~0;~E_2~0 := 1; 258#L471-3true assume !(0 == ~E_3~0); 66#L476-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 106#L220-15true assume !(1 == ~m_pc~0); 160#L220-17true is_master_triggered_~__retres1~0#1 := 0; 207#L231-5true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 28#L232-5true activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 219#L543-15true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 131#L543-17true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 121#L239-15true assume 1 == ~t1_pc~0; 268#L240-5true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 281#L250-5true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 331#L251-5true activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 26#L551-15true assume !(0 != activate_threads_~tmp___0~0#1); 316#L551-17true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 315#L258-15true assume 1 == ~t2_pc~0; 153#L259-5true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 279#L269-5true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 122#L270-5true activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 332#L559-15true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 228#L559-17true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 300#L277-15true assume 1 == ~t3_pc~0; 72#L278-5true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 325#L288-5true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 242#L289-5true activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 270#L567-15true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 34#L567-17true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 27#L489-3true assume 1 == ~M_E~0;~M_E~0 := 2; 174#L489-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 220#L494-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 298#L499-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 107#L504-3true assume 1 == ~E_M~0;~E_M~0 := 2; 16#L509-3true assume 1 == ~E_1~0;~E_1~0 := 2; 296#L514-3true assume 1 == ~E_2~0;~E_2~0 := 2; 165#L519-3true assume !(1 == ~E_3~0); 46#L524-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 54#L332-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 58#L354-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 333#L355-1true start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 151#L709true assume !(0 == start_simulation_~tmp~3#1); 8#L709-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 116#L332-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 56#L354-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 113#L355-2true stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 55#L664true assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 155#L671true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 142#L672true start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 86#L722true assume !(0 != start_simulation_~tmp___0~1#1); 38#L690-2true [2021-12-16 10:04:34,523 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:34,524 INFO L85 PathProgramCache]: Analyzing trace with hash 1917692997, now seen corresponding path program 1 times [2021-12-16 10:04:34,529 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:34,530 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [415746734] [2021-12-16 10:04:34,530 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:34,530 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:34,586 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:04:34,652 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:04:34,652 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:04:34,655 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [415746734] [2021-12-16 10:04:34,655 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [415746734] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:04:34,655 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:04:34,656 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:04:34,657 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1435047969] [2021-12-16 10:04:34,657 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:04:34,660 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:04:34,660 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:34,660 INFO L85 PathProgramCache]: Analyzing trace with hash 1938644724, now seen corresponding path program 1 times [2021-12-16 10:04:34,661 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:34,661 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1002762788] [2021-12-16 10:04:34,661 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:34,661 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:34,667 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:04:34,697 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:04:34,697 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:04:34,698 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1002762788] [2021-12-16 10:04:34,698 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1002762788] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:04:34,698 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:04:34,698 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-16 10:04:34,699 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [940185574] [2021-12-16 10:04:34,699 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:04:34,700 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:04:34,701 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:04:34,722 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-16 10:04:34,723 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-16 10:04:34,725 INFO L87 Difference]: Start difference. First operand has 331 states, 330 states have (on average 1.5393939393939393) internal successors, (508), 330 states have internal predecessors, (508), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 17.0) internal successors, (51), 3 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:04:34,766 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:04:34,767 INFO L93 Difference]: Finished difference Result 329 states and 491 transitions. [2021-12-16 10:04:34,768 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-16 10:04:34,771 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 329 states and 491 transitions. [2021-12-16 10:04:34,777 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 268 [2021-12-16 10:04:34,781 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 329 states to 323 states and 485 transitions. [2021-12-16 10:04:34,782 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 323 [2021-12-16 10:04:34,783 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 323 [2021-12-16 10:04:34,783 INFO L73 IsDeterministic]: Start isDeterministic. Operand 323 states and 485 transitions. [2021-12-16 10:04:34,784 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:04:34,785 INFO L681 BuchiCegarLoop]: Abstraction has 323 states and 485 transitions. [2021-12-16 10:04:34,796 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 323 states and 485 transitions. [2021-12-16 10:04:34,812 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 323 to 323. [2021-12-16 10:04:34,813 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 323 states, 323 states have (on average 1.501547987616099) internal successors, (485), 322 states have internal predecessors, (485), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:04:34,814 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 323 states to 323 states and 485 transitions. [2021-12-16 10:04:34,815 INFO L704 BuchiCegarLoop]: Abstraction has 323 states and 485 transitions. [2021-12-16 10:04:34,815 INFO L587 BuchiCegarLoop]: Abstraction has 323 states and 485 transitions. [2021-12-16 10:04:34,815 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2021-12-16 10:04:34,815 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 323 states and 485 transitions. [2021-12-16 10:04:34,817 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 268 [2021-12-16 10:04:34,817 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:04:34,817 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:04:34,818 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:34,818 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:34,819 INFO L791 eck$LassoCheckResult]: Stem: 989#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 955#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 795#L653 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 762#L297 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 763#L304 assume 1 == ~m_i~0;~m_st~0 := 0; 869#L304-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 721#L309-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 722#L314-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 888#L319-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 732#L441 assume !(0 == ~M_E~0); 733#L441-2 assume !(0 == ~T1_E~0); 863#L446-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 836#L451-1 assume !(0 == ~T3_E~0); 837#L456-1 assume !(0 == ~E_M~0); 958#L461-1 assume !(0 == ~E_1~0); 959#L466-1 assume !(0 == ~E_2~0); 971#L471-1 assume !(0 == ~E_3~0); 770#L476-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 771#L220 assume 1 == ~m_pc~0; 829#L221 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 804#L231 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 851#L232 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 799#L543 assume !(0 != activate_threads_~tmp~1#1); 800#L543-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 942#L239 assume !(1 == ~t1_pc~0); 940#L239-2 is_transmit1_triggered_~__retres1~1#1 := 0; 941#L250 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 974#L251 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 944#L551 assume !(0 != activate_threads_~tmp___0~0#1); 945#L551-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 946#L258 assume 1 == ~t2_pc~0; 947#L259 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 828#L269 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 690#L270 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 691#L559 assume !(0 != activate_threads_~tmp___1~0#1); 875#L559-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 876#L277 assume !(1 == ~t3_pc~0); 915#L277-2 is_transmit3_triggered_~__retres1~3#1 := 0; 746#L288 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 747#L289 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 793#L567 assume !(0 != activate_threads_~tmp___2~0#1); 794#L567-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 833#L489 assume !(1 == ~M_E~0); 957#L489-2 assume !(1 == ~T1_E~0); 902#L494-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 784#L499-1 assume !(1 == ~T3_E~0); 785#L504-1 assume !(1 == ~E_M~0); 870#L509-1 assume !(1 == ~E_1~0); 772#L514-1 assume !(1 == ~E_2~0); 773#L519-1 assume !(1 == ~E_3~0); 780#L524-1 assume { :end_inline_reset_delta_events } true; 744#L690-2 [2021-12-16 10:04:34,819 INFO L793 eck$LassoCheckResult]: Loop: 744#L690-2 assume !false; 745#L691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 674#L416 assume !false; 713#L365 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 809#L332 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 757#L354 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 951#L355 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 952#L369 assume !(0 != eval_~tmp~0#1); 954#L431 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 949#L297-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 936#L441-3 assume 0 == ~M_E~0;~M_E~0 := 1; 683#L441-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 684#L446-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 930#L451-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 741#L456-3 assume 0 == ~E_M~0;~E_M~0 := 1; 742#L461-3 assume 0 == ~E_1~0;~E_1~0 := 1; 808#L466-3 assume 0 == ~E_2~0;~E_2~0 := 1; 904#L471-3 assume !(0 == ~E_3~0); 797#L476-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 798#L220-15 assume !(1 == ~m_pc~0); 689#L220-17 is_master_triggered_~__retres1~0#1 := 0; 688#L231-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 727#L232-5 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 728#L543-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 877#L543-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 864#L239-15 assume !(1 == ~t1_pc~0); 865#L239-17 is_transmit1_triggered_~__retres1~1#1 := 0; 973#L250-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 984#L251-5 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 719#L551-15 assume !(0 != activate_threads_~tmp___0~0#1); 720#L551-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 991#L258-15 assume !(1 == ~t2_pc~0); 834#L258-17 is_transmit2_triggered_~__retres1~2#1 := 0; 835#L269-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 867#L270-5 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 868#L559-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 960#L559-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 961#L277-15 assume !(1 == ~t3_pc~0); 695#L277-17 is_transmit3_triggered_~__retres1~3#1 := 0; 696#L288-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 967#L289-5 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 968#L567-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 738#L567-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 723#L489-3 assume 1 == ~M_E~0;~M_E~0 := 2; 724#L489-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 919#L494-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 956#L499-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 850#L504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 700#L509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 701#L514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 909#L519-3 assume !(1 == ~E_3~0); 760#L524-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 761#L332-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 774#L354-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 781#L355-1 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 901#L709 assume !(0 == start_simulation_~tmp~3#1); 681#L709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 682#L332-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 778#L354-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 779#L355-2 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 776#L664 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 777#L671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 892#L672 start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 826#L722 assume !(0 != start_simulation_~tmp___0~1#1); 744#L690-2 [2021-12-16 10:04:34,820 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:34,820 INFO L85 PathProgramCache]: Analyzing trace with hash -2024185917, now seen corresponding path program 1 times [2021-12-16 10:04:34,820 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:34,820 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2042268078] [2021-12-16 10:04:34,820 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:34,820 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:34,829 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:04:34,851 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:04:34,851 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:04:34,852 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2042268078] [2021-12-16 10:04:34,853 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2042268078] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:04:34,853 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:04:34,853 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:04:34,854 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2013240895] [2021-12-16 10:04:34,854 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:04:34,854 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:04:34,855 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:34,857 INFO L85 PathProgramCache]: Analyzing trace with hash -639658428, now seen corresponding path program 1 times [2021-12-16 10:04:34,858 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:34,858 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1962098246] [2021-12-16 10:04:34,858 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:34,859 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:34,875 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:04:34,916 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:04:34,917 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:04:34,917 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1962098246] [2021-12-16 10:04:34,917 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1962098246] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:04:34,917 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:04:34,917 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-16 10:04:34,917 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [689098696] [2021-12-16 10:04:34,917 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:04:34,917 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:04:34,917 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:04:34,918 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-16 10:04:34,918 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-16 10:04:34,918 INFO L87 Difference]: Start difference. First operand 323 states and 485 transitions. cyclomatic complexity: 163 Second operand has 3 states, 3 states have (on average 17.0) internal successors, (51), 3 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:04:34,934 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:04:34,934 INFO L93 Difference]: Finished difference Result 323 states and 484 transitions. [2021-12-16 10:04:34,937 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-16 10:04:34,938 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 323 states and 484 transitions. [2021-12-16 10:04:34,940 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 268 [2021-12-16 10:04:34,943 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 323 states to 323 states and 484 transitions. [2021-12-16 10:04:34,944 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 323 [2021-12-16 10:04:34,945 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 323 [2021-12-16 10:04:34,945 INFO L73 IsDeterministic]: Start isDeterministic. Operand 323 states and 484 transitions. [2021-12-16 10:04:34,946 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:04:34,949 INFO L681 BuchiCegarLoop]: Abstraction has 323 states and 484 transitions. [2021-12-16 10:04:34,949 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 323 states and 484 transitions. [2021-12-16 10:04:34,957 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 323 to 323. [2021-12-16 10:04:34,958 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 323 states, 323 states have (on average 1.498452012383901) internal successors, (484), 322 states have internal predecessors, (484), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:04:34,959 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 323 states to 323 states and 484 transitions. [2021-12-16 10:04:34,959 INFO L704 BuchiCegarLoop]: Abstraction has 323 states and 484 transitions. [2021-12-16 10:04:34,959 INFO L587 BuchiCegarLoop]: Abstraction has 323 states and 484 transitions. [2021-12-16 10:04:34,959 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2021-12-16 10:04:34,959 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 323 states and 484 transitions. [2021-12-16 10:04:34,969 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 268 [2021-12-16 10:04:34,970 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:04:34,970 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:04:34,972 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:34,972 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:34,972 INFO L791 eck$LassoCheckResult]: Stem: 1644#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 1610#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 1450#L653 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1417#L297 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1418#L304 assume 1 == ~m_i~0;~m_st~0 := 0; 1525#L304-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1376#L309-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1377#L314-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1543#L319-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1389#L441 assume !(0 == ~M_E~0); 1390#L441-2 assume !(0 == ~T1_E~0); 1518#L446-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1491#L451-1 assume !(0 == ~T3_E~0); 1492#L456-1 assume !(0 == ~E_M~0); 1613#L461-1 assume !(0 == ~E_1~0); 1614#L466-1 assume !(0 == ~E_2~0); 1626#L471-1 assume !(0 == ~E_3~0); 1425#L476-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1426#L220 assume 1 == ~m_pc~0; 1486#L221 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1459#L231 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1506#L232 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1454#L543 assume !(0 != activate_threads_~tmp~1#1); 1455#L543-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1597#L239 assume !(1 == ~t1_pc~0); 1595#L239-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1596#L250 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1628#L251 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1599#L551 assume !(0 != activate_threads_~tmp___0~0#1); 1600#L551-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1601#L258 assume 1 == ~t2_pc~0; 1602#L259 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1483#L269 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1345#L270 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1346#L559 assume !(0 != activate_threads_~tmp___1~0#1); 1530#L559-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1531#L277 assume !(1 == ~t3_pc~0); 1569#L277-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1401#L288 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1402#L289 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1448#L567 assume !(0 != activate_threads_~tmp___2~0#1); 1449#L567-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1488#L489 assume !(1 == ~M_E~0); 1612#L489-2 assume !(1 == ~T1_E~0); 1556#L494-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1437#L499-1 assume !(1 == ~T3_E~0); 1438#L504-1 assume !(1 == ~E_M~0); 1524#L509-1 assume !(1 == ~E_1~0); 1427#L514-1 assume !(1 == ~E_2~0); 1428#L519-1 assume !(1 == ~E_3~0); 1435#L524-1 assume { :end_inline_reset_delta_events } true; 1399#L690-2 [2021-12-16 10:04:34,972 INFO L793 eck$LassoCheckResult]: Loop: 1399#L690-2 assume !false; 1400#L691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1329#L416 assume !false; 1368#L365 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 1464#L332 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 1411#L354 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 1606#L355 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1607#L369 assume !(0 != eval_~tmp~0#1); 1609#L431 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1604#L297-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1589#L441-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1338#L441-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1339#L446-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1585#L451-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1396#L456-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1397#L461-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1463#L466-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1559#L471-3 assume !(0 == ~E_3~0); 1452#L476-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1453#L220-15 assume !(1 == ~m_pc~0); 1344#L220-17 is_master_triggered_~__retres1~0#1 := 0; 1343#L231-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1380#L232-5 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1381#L543-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1532#L543-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1519#L239-15 assume !(1 == ~t1_pc~0); 1520#L239-17 is_transmit1_triggered_~__retres1~1#1 := 0; 1629#L250-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1639#L251-5 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1374#L551-15 assume !(0 != activate_threads_~tmp___0~0#1); 1375#L551-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1646#L258-15 assume !(1 == ~t2_pc~0); 1489#L258-17 is_transmit2_triggered_~__retres1~2#1 := 0; 1490#L269-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1522#L270-5 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1523#L559-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1615#L559-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1616#L277-15 assume !(1 == ~t3_pc~0); 1350#L277-17 is_transmit3_triggered_~__retres1~3#1 := 0; 1351#L288-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1622#L289-5 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1623#L567-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1393#L567-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1378#L489-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1379#L489-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1574#L494-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1611#L499-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1505#L504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1355#L509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1356#L514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1564#L519-3 assume !(1 == ~E_3~0); 1415#L524-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 1416#L332-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 1429#L354-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 1436#L355-1 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 1557#L709 assume !(0 == start_simulation_~tmp~3#1); 1336#L709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 1337#L332-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 1433#L354-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 1434#L355-2 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 1431#L664 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 1432#L671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1547#L672 start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 1482#L722 assume !(0 != start_simulation_~tmp___0~1#1); 1399#L690-2 [2021-12-16 10:04:34,973 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:34,973 INFO L85 PathProgramCache]: Analyzing trace with hash 1377295041, now seen corresponding path program 1 times [2021-12-16 10:04:34,973 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:34,974 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [4372519] [2021-12-16 10:04:34,974 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:34,974 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:34,986 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:04:35,008 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:04:35,008 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:04:35,008 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [4372519] [2021-12-16 10:04:35,009 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [4372519] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:04:35,009 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:04:35,009 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:04:35,009 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1063564872] [2021-12-16 10:04:35,009 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:04:35,009 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:04:35,009 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:35,010 INFO L85 PathProgramCache]: Analyzing trace with hash -639658428, now seen corresponding path program 2 times [2021-12-16 10:04:35,010 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:35,010 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1554298970] [2021-12-16 10:04:35,010 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:35,010 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:35,034 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:04:35,069 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:04:35,070 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:04:35,071 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1554298970] [2021-12-16 10:04:35,071 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1554298970] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:04:35,071 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:04:35,071 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-16 10:04:35,071 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1918854428] [2021-12-16 10:04:35,074 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:04:35,074 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:04:35,075 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:04:35,075 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-16 10:04:35,075 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-16 10:04:35,075 INFO L87 Difference]: Start difference. First operand 323 states and 484 transitions. cyclomatic complexity: 162 Second operand has 3 states, 3 states have (on average 17.0) internal successors, (51), 3 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:04:35,082 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:04:35,083 INFO L93 Difference]: Finished difference Result 323 states and 483 transitions. [2021-12-16 10:04:35,083 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-16 10:04:35,084 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 323 states and 483 transitions. [2021-12-16 10:04:35,086 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 268 [2021-12-16 10:04:35,087 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 323 states to 323 states and 483 transitions. [2021-12-16 10:04:35,088 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 323 [2021-12-16 10:04:35,088 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 323 [2021-12-16 10:04:35,088 INFO L73 IsDeterministic]: Start isDeterministic. Operand 323 states and 483 transitions. [2021-12-16 10:04:35,089 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:04:35,089 INFO L681 BuchiCegarLoop]: Abstraction has 323 states and 483 transitions. [2021-12-16 10:04:35,089 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 323 states and 483 transitions. [2021-12-16 10:04:35,094 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 323 to 323. [2021-12-16 10:04:35,094 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 323 states, 323 states have (on average 1.4953560371517027) internal successors, (483), 322 states have internal predecessors, (483), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:04:35,095 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 323 states to 323 states and 483 transitions. [2021-12-16 10:04:35,095 INFO L704 BuchiCegarLoop]: Abstraction has 323 states and 483 transitions. [2021-12-16 10:04:35,095 INFO L587 BuchiCegarLoop]: Abstraction has 323 states and 483 transitions. [2021-12-16 10:04:35,096 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2021-12-16 10:04:35,096 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 323 states and 483 transitions. [2021-12-16 10:04:35,097 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 268 [2021-12-16 10:04:35,097 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:04:35,097 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:04:35,098 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:35,098 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:35,098 INFO L791 eck$LassoCheckResult]: Stem: 2299#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 2265#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 2105#L653 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2072#L297 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2073#L304 assume 1 == ~m_i~0;~m_st~0 := 0; 2179#L304-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2029#L309-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2030#L314-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2198#L319-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2042#L441 assume !(0 == ~M_E~0); 2043#L441-2 assume !(0 == ~T1_E~0); 2173#L446-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2146#L451-1 assume !(0 == ~T3_E~0); 2147#L456-1 assume !(0 == ~E_M~0); 2268#L461-1 assume !(0 == ~E_1~0); 2269#L466-1 assume !(0 == ~E_2~0); 2281#L471-1 assume !(0 == ~E_3~0); 2080#L476-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2081#L220 assume 1 == ~m_pc~0; 2139#L221 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2114#L231 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2160#L232 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 2109#L543 assume !(0 != activate_threads_~tmp~1#1); 2110#L543-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2252#L239 assume !(1 == ~t1_pc~0); 2250#L239-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2251#L250 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2283#L251 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2254#L551 assume !(0 != activate_threads_~tmp___0~0#1); 2255#L551-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2256#L258 assume 1 == ~t2_pc~0; 2257#L259 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2138#L269 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2000#L270 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2001#L559 assume !(0 != activate_threads_~tmp___1~0#1); 2185#L559-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2186#L277 assume !(1 == ~t3_pc~0); 2224#L277-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2056#L288 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2057#L289 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2103#L567 assume !(0 != activate_threads_~tmp___2~0#1); 2104#L567-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2143#L489 assume !(1 == ~M_E~0); 2267#L489-2 assume !(1 == ~T1_E~0); 2211#L494-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2092#L499-1 assume !(1 == ~T3_E~0); 2093#L504-1 assume !(1 == ~E_M~0); 2180#L509-1 assume !(1 == ~E_1~0); 2082#L514-1 assume !(1 == ~E_2~0); 2083#L519-1 assume !(1 == ~E_3~0); 2090#L524-1 assume { :end_inline_reset_delta_events } true; 2054#L690-2 [2021-12-16 10:04:35,099 INFO L793 eck$LassoCheckResult]: Loop: 2054#L690-2 assume !false; 2055#L691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1984#L416 assume !false; 2023#L365 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 2119#L332 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 2066#L354 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 2261#L355 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 2262#L369 assume !(0 != eval_~tmp~0#1); 2264#L431 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2259#L297-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2244#L441-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1993#L441-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1994#L446-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2240#L451-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2051#L456-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2052#L461-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2118#L466-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2214#L471-3 assume !(0 == ~E_3~0); 2107#L476-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2108#L220-15 assume 1 == ~m_pc~0; 1997#L221-5 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1998#L231-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2035#L232-5 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 2036#L543-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2187#L543-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2174#L239-15 assume 1 == ~t1_pc~0; 2176#L240-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2284#L250-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2294#L251-5 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2031#L551-15 assume !(0 != activate_threads_~tmp___0~0#1); 2032#L551-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2301#L258-15 assume !(1 == ~t2_pc~0); 2144#L258-17 is_transmit2_triggered_~__retres1~2#1 := 0; 2145#L269-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2177#L270-5 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2178#L559-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2270#L559-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2271#L277-15 assume !(1 == ~t3_pc~0); 2005#L277-17 is_transmit3_triggered_~__retres1~3#1 := 0; 2006#L288-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2277#L289-5 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2278#L567-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2048#L567-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2033#L489-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2034#L489-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2229#L494-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2266#L499-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2161#L504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2010#L509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2011#L514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2219#L519-3 assume !(1 == ~E_3~0); 2070#L524-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 2071#L332-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 2084#L354-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 2091#L355-1 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 2212#L709 assume !(0 == start_simulation_~tmp~3#1); 1991#L709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 1992#L332-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 2088#L354-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 2089#L355-2 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 2086#L664 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 2087#L671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2202#L672 start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 2137#L722 assume !(0 != start_simulation_~tmp___0~1#1); 2054#L690-2 [2021-12-16 10:04:35,099 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:35,099 INFO L85 PathProgramCache]: Analyzing trace with hash -868284413, now seen corresponding path program 1 times [2021-12-16 10:04:35,099 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:35,100 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [10683321] [2021-12-16 10:04:35,100 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:35,100 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:35,111 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:04:35,147 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:04:35,148 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:04:35,148 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [10683321] [2021-12-16 10:04:35,148 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [10683321] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:04:35,148 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:04:35,148 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:04:35,149 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1448641238] [2021-12-16 10:04:35,149 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:04:35,149 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:04:35,149 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:35,149 INFO L85 PathProgramCache]: Analyzing trace with hash 1190747650, now seen corresponding path program 1 times [2021-12-16 10:04:35,150 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:35,150 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1366163031] [2021-12-16 10:04:35,150 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:35,150 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:35,161 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:04:35,181 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:04:35,181 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:04:35,182 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1366163031] [2021-12-16 10:04:35,182 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1366163031] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:04:35,182 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:04:35,182 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-16 10:04:35,182 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [232910996] [2021-12-16 10:04:35,182 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:04:35,183 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:04:35,183 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:04:35,183 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-16 10:04:35,183 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-16 10:04:35,184 INFO L87 Difference]: Start difference. First operand 323 states and 483 transitions. cyclomatic complexity: 161 Second operand has 4 states, 4 states have (on average 12.75) internal successors, (51), 3 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:04:35,234 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:04:35,234 INFO L93 Difference]: Finished difference Result 561 states and 834 transitions. [2021-12-16 10:04:35,234 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-16 10:04:35,235 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 561 states and 834 transitions. [2021-12-16 10:04:35,238 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 498 [2021-12-16 10:04:35,240 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 561 states to 561 states and 834 transitions. [2021-12-16 10:04:35,240 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 561 [2021-12-16 10:04:35,241 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 561 [2021-12-16 10:04:35,241 INFO L73 IsDeterministic]: Start isDeterministic. Operand 561 states and 834 transitions. [2021-12-16 10:04:35,241 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:04:35,241 INFO L681 BuchiCegarLoop]: Abstraction has 561 states and 834 transitions. [2021-12-16 10:04:35,242 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 561 states and 834 transitions. [2021-12-16 10:04:35,258 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 561 to 561. [2021-12-16 10:04:35,259 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 561 states, 561 states have (on average 1.4866310160427807) internal successors, (834), 560 states have internal predecessors, (834), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:04:35,261 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 561 states to 561 states and 834 transitions. [2021-12-16 10:04:35,261 INFO L704 BuchiCegarLoop]: Abstraction has 561 states and 834 transitions. [2021-12-16 10:04:35,261 INFO L587 BuchiCegarLoop]: Abstraction has 561 states and 834 transitions. [2021-12-16 10:04:35,261 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2021-12-16 10:04:35,261 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 561 states and 834 transitions. [2021-12-16 10:04:35,264 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 498 [2021-12-16 10:04:35,264 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:04:35,264 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:04:35,266 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:35,266 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:35,271 INFO L791 eck$LassoCheckResult]: Stem: 3234#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 3183#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 3003#L653 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2970#L297 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2971#L304 assume 1 == ~m_i~0;~m_st~0 := 0; 3080#L304-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2926#L309-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2927#L314-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3099#L319-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2940#L441 assume !(0 == ~M_E~0); 2941#L441-2 assume !(0 == ~T1_E~0); 3074#L446-1 assume !(0 == ~T2_E~0); 3045#L451-1 assume !(0 == ~T3_E~0); 3046#L456-1 assume !(0 == ~E_M~0); 3189#L461-1 assume !(0 == ~E_1~0); 3190#L466-1 assume !(0 == ~E_2~0); 3210#L471-1 assume !(0 == ~E_3~0); 2978#L476-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2979#L220 assume 1 == ~m_pc~0; 3038#L221 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 3012#L231 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3059#L232 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 3007#L543 assume !(0 != activate_threads_~tmp~1#1); 3008#L543-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3164#L239 assume !(1 == ~t1_pc~0); 3162#L239-2 is_transmit1_triggered_~__retres1~1#1 := 0; 3163#L250 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3214#L251 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 3168#L551 assume !(0 != activate_threads_~tmp___0~0#1); 3169#L551-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3170#L258 assume 1 == ~t2_pc~0; 3171#L259 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3037#L269 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2896#L270 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2897#L559 assume !(0 != activate_threads_~tmp___1~0#1); 3086#L559-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3087#L277 assume !(1 == ~t3_pc~0); 3127#L277-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2954#L288 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2955#L289 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3001#L567 assume !(0 != activate_threads_~tmp___2~0#1); 3002#L567-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3042#L489 assume 1 == ~M_E~0;~M_E~0 := 2; 3186#L489-2 assume !(1 == ~T1_E~0); 3187#L494-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2990#L499-1 assume !(1 == ~T3_E~0); 2991#L504-1 assume !(1 == ~E_M~0); 3081#L509-1 assume !(1 == ~E_1~0); 2980#L514-1 assume !(1 == ~E_2~0); 2981#L519-1 assume !(1 == ~E_3~0); 3137#L524-1 assume { :end_inline_reset_delta_events } true; 3249#L690-2 [2021-12-16 10:04:35,271 INFO L793 eck$LassoCheckResult]: Loop: 3249#L690-2 assume !false; 3248#L691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2919#L416 assume !false; 2920#L365 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 3165#L332 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 2964#L354 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 3178#L355 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 3179#L369 assume !(0 != eval_~tmp~0#1); 3241#L431 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3173#L297-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3174#L441-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3240#L441-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3343#L446-3 assume !(0 == ~T2_E~0); 3342#L451-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3341#L456-3 assume 0 == ~E_M~0;~E_M~0 := 1; 3340#L461-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3339#L466-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3338#L471-3 assume !(0 == ~E_3~0); 3337#L476-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3336#L220-15 assume !(1 == ~m_pc~0); 3334#L220-17 is_master_triggered_~__retres1~0#1 := 0; 3333#L231-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3332#L232-5 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 3331#L543-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3330#L543-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3329#L239-15 assume !(1 == ~t1_pc~0); 3328#L239-17 is_transmit1_triggered_~__retres1~1#1 := 0; 3326#L250-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3325#L251-5 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 3324#L551-15 assume !(0 != activate_threads_~tmp___0~0#1); 3323#L551-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3322#L258-15 assume 1 == ~t2_pc~0; 3320#L259-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3319#L269-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3318#L270-5 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3317#L559-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3316#L559-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3315#L277-15 assume !(1 == ~t3_pc~0); 3313#L277-17 is_transmit3_triggered_~__retres1~3#1 := 0; 3312#L288-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3311#L289-5 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3310#L567-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3309#L567-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3308#L489-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2931#L489-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3307#L494-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3184#L499-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3306#L504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3305#L509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3304#L514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3303#L519-3 assume !(1 == ~E_3~0); 3302#L524-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 3300#L332-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 3297#L354-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 3296#L355-1 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 3295#L709 assume !(0 == start_simulation_~tmp~3#1); 3136#L709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 3068#L332-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 2986#L354-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 2987#L355-2 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 2984#L664 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 2985#L671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3103#L672 start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 3104#L722 assume !(0 != start_simulation_~tmp___0~1#1); 3249#L690-2 [2021-12-16 10:04:35,272 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:35,272 INFO L85 PathProgramCache]: Analyzing trace with hash 1374817215, now seen corresponding path program 1 times [2021-12-16 10:04:35,272 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:35,272 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2080992766] [2021-12-16 10:04:35,272 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:35,272 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:35,284 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:04:35,303 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:04:35,304 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:04:35,304 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2080992766] [2021-12-16 10:04:35,304 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2080992766] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:04:35,304 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:04:35,304 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-16 10:04:35,304 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1174267530] [2021-12-16 10:04:35,305 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:04:35,305 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:04:35,305 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:35,305 INFO L85 PathProgramCache]: Analyzing trace with hash -1819727935, now seen corresponding path program 1 times [2021-12-16 10:04:35,306 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:35,306 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2048335698] [2021-12-16 10:04:35,306 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:35,306 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:35,313 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:04:35,333 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:04:35,333 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:04:35,334 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2048335698] [2021-12-16 10:04:35,334 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2048335698] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:04:35,334 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:04:35,334 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-16 10:04:35,334 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [625486322] [2021-12-16 10:04:35,334 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:04:35,335 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:04:35,335 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:04:35,335 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-16 10:04:35,335 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-16 10:04:35,335 INFO L87 Difference]: Start difference. First operand 561 states and 834 transitions. cyclomatic complexity: 275 Second operand has 3 states, 3 states have (on average 17.0) internal successors, (51), 2 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:04:35,382 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:04:35,383 INFO L93 Difference]: Finished difference Result 1033 states and 1511 transitions. [2021-12-16 10:04:35,383 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-16 10:04:35,385 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1033 states and 1511 transitions. [2021-12-16 10:04:35,390 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 967 [2021-12-16 10:04:35,393 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1033 states to 1033 states and 1511 transitions. [2021-12-16 10:04:35,394 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1033 [2021-12-16 10:04:35,394 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1033 [2021-12-16 10:04:35,394 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1033 states and 1511 transitions. [2021-12-16 10:04:35,396 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:04:35,396 INFO L681 BuchiCegarLoop]: Abstraction has 1033 states and 1511 transitions. [2021-12-16 10:04:35,396 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1033 states and 1511 transitions. [2021-12-16 10:04:35,408 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1033 to 979. [2021-12-16 10:04:35,410 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 979 states, 979 states have (on average 1.4678243105209396) internal successors, (1437), 978 states have internal predecessors, (1437), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:04:35,412 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 979 states to 979 states and 1437 transitions. [2021-12-16 10:04:35,412 INFO L704 BuchiCegarLoop]: Abstraction has 979 states and 1437 transitions. [2021-12-16 10:04:35,412 INFO L587 BuchiCegarLoop]: Abstraction has 979 states and 1437 transitions. [2021-12-16 10:04:35,412 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2021-12-16 10:04:35,413 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 979 states and 1437 transitions. [2021-12-16 10:04:35,416 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 913 [2021-12-16 10:04:35,416 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:04:35,416 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:04:35,417 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:35,418 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:35,418 INFO L791 eck$LassoCheckResult]: Stem: 4836#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 4790#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 4606#L653 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4573#L297 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4574#L304 assume 1 == ~m_i~0;~m_st~0 := 0; 4686#L304-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4530#L309-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4531#L314-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4705#L319-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4542#L441 assume !(0 == ~M_E~0); 4543#L441-2 assume !(0 == ~T1_E~0); 4680#L446-1 assume !(0 == ~T2_E~0); 4648#L451-1 assume !(0 == ~T3_E~0); 4649#L456-1 assume !(0 == ~E_M~0); 4795#L461-1 assume !(0 == ~E_1~0); 4796#L466-1 assume !(0 == ~E_2~0); 4811#L471-1 assume !(0 == ~E_3~0); 4581#L476-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4582#L220 assume !(1 == ~m_pc~0); 4614#L220-2 is_master_triggered_~__retres1~0#1 := 0; 4615#L231 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4665#L232 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 4610#L543 assume !(0 != activate_threads_~tmp~1#1); 4611#L543-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4775#L239 assume !(1 == ~t1_pc~0); 4772#L239-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4773#L250 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4814#L251 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 4777#L551 assume !(0 != activate_threads_~tmp___0~0#1); 4778#L551-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4779#L258 assume 1 == ~t2_pc~0; 4780#L259 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4641#L269 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4499#L270 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4500#L559 assume !(0 != activate_threads_~tmp___1~0#1); 4694#L559-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4695#L277 assume !(1 == ~t3_pc~0); 4741#L277-2 is_transmit3_triggered_~__retres1~3#1 := 0; 4556#L288 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4557#L289 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4604#L567 assume !(0 != activate_threads_~tmp___2~0#1); 4605#L567-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4645#L489 assume 1 == ~M_E~0;~M_E~0 := 2; 4835#L489-2 assume !(1 == ~T1_E~0); 5322#L494-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4723#L499-1 assume !(1 == ~T3_E~0); 5321#L504-1 assume !(1 == ~E_M~0); 5320#L509-1 assume !(1 == ~E_1~0); 5319#L514-1 assume !(1 == ~E_2~0); 5318#L519-1 assume !(1 == ~E_3~0); 4591#L524-1 assume { :end_inline_reset_delta_events } true; 4554#L690-2 [2021-12-16 10:04:35,418 INFO L793 eck$LassoCheckResult]: Loop: 4554#L690-2 assume !false; 4555#L691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4483#L416 assume !false; 4524#L365 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 4620#L332 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 4568#L354 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 5258#L355 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 5256#L369 assume !(0 != eval_~tmp~0#1); 4842#L431 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4782#L297-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4783#L441-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5292#L441-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5374#L446-3 assume !(0 == ~T2_E~0); 5373#L451-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5372#L456-3 assume 0 == ~E_M~0;~E_M~0 := 1; 5369#L461-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5367#L466-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5366#L471-3 assume !(0 == ~E_3~0); 5365#L476-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5364#L220-15 assume !(1 == ~m_pc~0); 5363#L220-17 is_master_triggered_~__retres1~0#1 := 0; 5362#L231-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5361#L232-5 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 5360#L543-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 5359#L543-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5358#L239-15 assume 1 == ~t1_pc~0; 5356#L240-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5355#L250-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5354#L251-5 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 5353#L551-15 assume !(0 != activate_threads_~tmp___0~0#1); 5352#L551-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5351#L258-15 assume 1 == ~t2_pc~0; 5348#L259-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5347#L269-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5346#L270-5 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 5345#L559-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5344#L559-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5343#L277-15 assume !(1 == ~t3_pc~0); 5341#L277-17 is_transmit3_triggered_~__retres1~3#1 := 0; 5340#L288-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5339#L289-5 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5338#L567-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5337#L567-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5336#L489-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4958#L489-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5335#L494-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4937#L499-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5334#L504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 5333#L509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5332#L514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5331#L519-3 assume !(1 == ~E_3~0); 5330#L524-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 5328#L332-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 5325#L354-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 5324#L355-1 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 5323#L709 assume !(0 == start_simulation_~tmp~3#1); 4748#L709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 4673#L332-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 4589#L354-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 4590#L355-2 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 4585#L664 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 4586#L671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4709#L672 start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 4639#L722 assume !(0 != start_simulation_~tmp___0~1#1); 4554#L690-2 [2021-12-16 10:04:35,419 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:35,419 INFO L85 PathProgramCache]: Analyzing trace with hash -201740544, now seen corresponding path program 1 times [2021-12-16 10:04:35,419 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:35,420 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1973239095] [2021-12-16 10:04:35,420 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:35,420 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:35,428 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:04:35,471 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:04:35,471 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:04:35,472 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1973239095] [2021-12-16 10:04:35,472 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1973239095] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:04:35,472 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:04:35,472 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:04:35,473 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1108308651] [2021-12-16 10:04:35,473 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:04:35,474 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:04:35,474 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:35,476 INFO L85 PathProgramCache]: Analyzing trace with hash -862799552, now seen corresponding path program 1 times [2021-12-16 10:04:35,476 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:35,478 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [246708824] [2021-12-16 10:04:35,480 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:35,481 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:35,487 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:04:35,514 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:04:35,514 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:04:35,514 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [246708824] [2021-12-16 10:04:35,517 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [246708824] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:04:35,517 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:04:35,518 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-16 10:04:35,518 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [938200018] [2021-12-16 10:04:35,518 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:04:35,518 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:04:35,518 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:04:35,519 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-16 10:04:35,520 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-16 10:04:35,520 INFO L87 Difference]: Start difference. First operand 979 states and 1437 transitions. cyclomatic complexity: 462 Second operand has 4 states, 4 states have (on average 12.75) internal successors, (51), 3 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:04:35,602 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:04:35,602 INFO L93 Difference]: Finished difference Result 2457 states and 3555 transitions. [2021-12-16 10:04:35,603 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-16 10:04:35,604 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2457 states and 3555 transitions. [2021-12-16 10:04:35,615 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 2353 [2021-12-16 10:04:35,624 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2457 states to 2457 states and 3555 transitions. [2021-12-16 10:04:35,624 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2457 [2021-12-16 10:04:35,625 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2457 [2021-12-16 10:04:35,625 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2457 states and 3555 transitions. [2021-12-16 10:04:35,627 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:04:35,628 INFO L681 BuchiCegarLoop]: Abstraction has 2457 states and 3555 transitions. [2021-12-16 10:04:35,629 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2457 states and 3555 transitions. [2021-12-16 10:04:35,648 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2457 to 2373. [2021-12-16 10:04:35,650 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2373 states, 2373 states have (on average 1.4542772861356932) internal successors, (3451), 2372 states have internal predecessors, (3451), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:04:35,655 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2373 states to 2373 states and 3451 transitions. [2021-12-16 10:04:35,655 INFO L704 BuchiCegarLoop]: Abstraction has 2373 states and 3451 transitions. [2021-12-16 10:04:35,655 INFO L587 BuchiCegarLoop]: Abstraction has 2373 states and 3451 transitions. [2021-12-16 10:04:35,656 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2021-12-16 10:04:35,656 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2373 states and 3451 transitions. [2021-12-16 10:04:35,662 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 2293 [2021-12-16 10:04:35,662 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:04:35,663 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:04:35,663 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:35,663 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:35,664 INFO L791 eck$LassoCheckResult]: Stem: 8296#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 8242#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 8052#L653 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8018#L297 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 8019#L304 assume 1 == ~m_i~0;~m_st~0 := 0; 8143#L304-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7975#L309-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7976#L314-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 8162#L319-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7988#L441 assume !(0 == ~M_E~0); 7989#L441-2 assume !(0 == ~T1_E~0); 8138#L446-1 assume !(0 == ~T2_E~0); 8100#L451-1 assume !(0 == ~T3_E~0); 8101#L456-1 assume !(0 == ~E_M~0); 8246#L461-1 assume !(0 == ~E_1~0); 8247#L466-1 assume !(0 == ~E_2~0); 8265#L471-1 assume !(0 == ~E_3~0); 8026#L476-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8027#L220 assume !(1 == ~m_pc~0); 8060#L220-2 is_master_triggered_~__retres1~0#1 := 0; 8061#L231 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8117#L232 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 8056#L543 assume !(0 != activate_threads_~tmp~1#1); 8057#L543-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8228#L239 assume !(1 == ~t1_pc~0); 8229#L239-2 is_transmit1_triggered_~__retres1~1#1 := 0; 8244#L250 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8269#L251 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 8232#L551 assume !(0 != activate_threads_~tmp___0~0#1); 8233#L551-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8234#L258 assume !(1 == ~t2_pc~0); 8235#L258-2 is_transmit2_triggered_~__retres1~2#1 := 0; 8089#L269 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7947#L270 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 7948#L559 assume !(0 != activate_threads_~tmp___1~0#1); 8150#L559-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8151#L277 assume !(1 == ~t3_pc~0); 8201#L277-2 is_transmit3_triggered_~__retres1~3#1 := 0; 8002#L288 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8003#L289 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 8050#L567 assume !(0 != activate_threads_~tmp___2~0#1); 8051#L567-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8097#L489 assume 1 == ~M_E~0;~M_E~0 := 2; 8245#L489-2 assume !(1 == ~T1_E~0); 8180#L494-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 8039#L499-1 assume !(1 == ~T3_E~0); 8040#L504-1 assume !(1 == ~E_M~0); 8144#L509-1 assume !(1 == ~E_1~0); 9583#L514-1 assume !(1 == ~E_2~0); 9581#L519-1 assume !(1 == ~E_3~0); 9575#L524-1 assume { :end_inline_reset_delta_events } true; 9572#L690-2 [2021-12-16 10:04:35,664 INFO L793 eck$LassoCheckResult]: Loop: 9572#L690-2 assume !false; 9571#L691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 9566#L416 assume !false; 9565#L365 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 9542#L332 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 9538#L354 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 9537#L355 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 9536#L369 assume !(0 != eval_~tmp~0#1); 8303#L431 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8236#L297-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8223#L441-3 assume 0 == ~M_E~0;~M_E~0 := 1; 7940#L441-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 7941#L446-3 assume !(0 == ~T2_E~0); 9723#L451-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 9724#L456-3 assume 0 == ~E_M~0;~E_M~0 := 1; 9717#L461-3 assume 0 == ~E_1~0;~E_1~0 := 1; 9718#L466-3 assume 0 == ~E_2~0;~E_2~0 := 1; 9711#L471-3 assume !(0 == ~E_3~0); 9712#L476-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8118#L220-15 assume !(1 == ~m_pc~0); 8119#L220-17 is_master_triggered_~__retres1~0#1 := 0; 8193#L231-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7981#L232-5 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 7982#L543-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8152#L543-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8139#L239-15 assume !(1 == ~t1_pc~0); 8140#L239-17 is_transmit1_triggered_~__retres1~1#1 := 0; 8270#L250-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8284#L251-5 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 7977#L551-15 assume !(0 != activate_threads_~tmp___0~0#1); 7978#L551-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8300#L258-15 assume !(1 == ~t2_pc~0); 8098#L258-17 is_transmit2_triggered_~__retres1~2#1 := 0; 8099#L269-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8141#L270-5 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 8142#L559-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 8248#L559-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8249#L277-15 assume !(1 == ~t3_pc~0); 7952#L277-17 is_transmit3_triggered_~__retres1~3#1 := 0; 7953#L288-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8260#L289-5 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 8261#L567-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 7994#L567-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7979#L489-3 assume 1 == ~M_E~0;~M_E~0 := 2; 7980#L489-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8206#L494-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 8243#L499-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8120#L504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 7956#L509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 7957#L514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 9591#L519-3 assume !(1 == ~E_3~0); 9592#L524-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 9186#L332-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 9184#L354-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 9131#L355-1 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 9132#L709 assume !(0 == start_simulation_~tmp~3#1); 9603#L709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 9587#L332-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 9584#L354-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 9582#L355-2 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 9580#L664 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 9579#L671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 9578#L672 start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 9576#L722 assume !(0 != start_simulation_~tmp___0~1#1); 9572#L690-2 [2021-12-16 10:04:35,664 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:35,664 INFO L85 PathProgramCache]: Analyzing trace with hash -1175229503, now seen corresponding path program 1 times [2021-12-16 10:04:35,664 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:35,665 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [450688103] [2021-12-16 10:04:35,665 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:35,665 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:35,670 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:04:35,692 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:04:35,692 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:04:35,692 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [450688103] [2021-12-16 10:04:35,692 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [450688103] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:04:35,692 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:04:35,692 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-16 10:04:35,693 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [692964434] [2021-12-16 10:04:35,693 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:04:35,693 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:04:35,693 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:35,693 INFO L85 PathProgramCache]: Analyzing trace with hash 898681602, now seen corresponding path program 1 times [2021-12-16 10:04:35,694 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:35,694 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1991279708] [2021-12-16 10:04:35,694 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:35,694 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:35,699 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:04:35,716 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:04:35,716 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:04:35,716 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1991279708] [2021-12-16 10:04:35,716 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1991279708] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:04:35,716 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:04:35,717 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-16 10:04:35,717 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1037072712] [2021-12-16 10:04:35,717 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:04:35,717 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:04:35,717 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:04:35,717 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-16 10:04:35,718 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-16 10:04:35,718 INFO L87 Difference]: Start difference. First operand 2373 states and 3451 transitions. cyclomatic complexity: 1086 Second operand has 3 states, 3 states have (on average 17.0) internal successors, (51), 2 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:04:35,741 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:04:35,741 INFO L93 Difference]: Finished difference Result 3466 states and 5042 transitions. [2021-12-16 10:04:35,741 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-16 10:04:35,742 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3466 states and 5042 transitions. [2021-12-16 10:04:35,755 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 3378 [2021-12-16 10:04:35,767 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3466 states to 3466 states and 5042 transitions. [2021-12-16 10:04:35,768 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3466 [2021-12-16 10:04:35,770 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3466 [2021-12-16 10:04:35,770 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3466 states and 5042 transitions. [2021-12-16 10:04:35,773 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:04:35,773 INFO L681 BuchiCegarLoop]: Abstraction has 3466 states and 5042 transitions. [2021-12-16 10:04:35,775 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3466 states and 5042 transitions. [2021-12-16 10:04:35,799 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3466 to 2413. [2021-12-16 10:04:35,803 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2413 states, 2413 states have (on average 1.4583506009117282) internal successors, (3519), 2412 states have internal predecessors, (3519), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:04:35,810 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2413 states to 2413 states and 3519 transitions. [2021-12-16 10:04:35,810 INFO L704 BuchiCegarLoop]: Abstraction has 2413 states and 3519 transitions. [2021-12-16 10:04:35,810 INFO L587 BuchiCegarLoop]: Abstraction has 2413 states and 3519 transitions. [2021-12-16 10:04:35,811 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2021-12-16 10:04:35,811 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2413 states and 3519 transitions. [2021-12-16 10:04:35,820 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2341 [2021-12-16 10:04:35,820 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:04:35,820 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:04:35,821 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:35,821 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:35,822 INFO L791 eck$LassoCheckResult]: Stem: 14129#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 14077#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 13899#L653 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 13866#L297 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 13867#L304 assume 1 == ~m_i~0;~m_st~0 := 0; 13979#L304-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 13823#L309-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 13824#L314-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 13999#L319-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 13836#L441 assume !(0 == ~M_E~0); 13837#L441-2 assume !(0 == ~T1_E~0); 13974#L446-1 assume !(0 == ~T2_E~0); 13945#L451-1 assume !(0 == ~T3_E~0); 13946#L456-1 assume !(0 == ~E_M~0); 14081#L461-1 assume !(0 == ~E_1~0); 14082#L466-1 assume !(0 == ~E_2~0); 14098#L471-1 assume !(0 == ~E_3~0); 13874#L476-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13875#L220 assume !(1 == ~m_pc~0); 13907#L220-2 is_master_triggered_~__retres1~0#1 := 0; 13908#L231 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13960#L232 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 13903#L543 assume !(0 != activate_threads_~tmp~1#1); 13904#L543-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14063#L239 assume !(1 == ~t1_pc~0); 14064#L239-2 is_transmit1_triggered_~__retres1~1#1 := 0; 14079#L250 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14101#L251 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 14067#L551 assume !(0 != activate_threads_~tmp___0~0#1); 14068#L551-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14069#L258 assume !(1 == ~t2_pc~0); 14070#L258-2 is_transmit2_triggered_~__retres1~2#1 := 0; 13936#L269 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13795#L270 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 13796#L559 assume !(0 != activate_threads_~tmp___1~0#1); 13986#L559-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 13987#L277 assume !(1 == ~t3_pc~0); 14036#L277-2 is_transmit3_triggered_~__retres1~3#1 := 0; 13850#L288 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13851#L289 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 13897#L567 assume !(0 != activate_threads_~tmp___2~0#1); 13898#L567-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13942#L489 assume !(1 == ~M_E~0); 14080#L489-2 assume !(1 == ~T1_E~0); 14017#L494-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 13886#L499-1 assume !(1 == ~T3_E~0); 13887#L504-1 assume !(1 == ~E_M~0); 13980#L509-1 assume !(1 == ~E_1~0); 13876#L514-1 assume !(1 == ~E_2~0); 13877#L519-1 assume !(1 == ~E_3~0); 13884#L524-1 assume { :end_inline_reset_delta_events } true; 13848#L690-2 [2021-12-16 10:04:35,822 INFO L793 eck$LassoCheckResult]: Loop: 13848#L690-2 assume !false; 13849#L691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 13779#L416 assume !false; 13817#L365 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 13913#L332 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 13860#L354 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 14073#L355 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 14074#L369 assume !(0 != eval_~tmp~0#1); 14076#L431 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 16101#L297-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 16099#L441-3 assume !(0 == ~M_E~0); 16097#L441-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 16096#L446-3 assume !(0 == ~T2_E~0); 16095#L451-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 16094#L456-3 assume 0 == ~E_M~0;~E_M~0 := 1; 16093#L461-3 assume 0 == ~E_1~0;~E_1~0 := 1; 16092#L466-3 assume 0 == ~E_2~0;~E_2~0 := 1; 16091#L471-3 assume !(0 == ~E_3~0); 16061#L476-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16060#L220-15 assume !(1 == ~m_pc~0); 16059#L220-17 is_master_triggered_~__retres1~0#1 := 0; 16058#L231-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16056#L232-5 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 16054#L543-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 16052#L543-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16050#L239-15 assume !(1 == ~t1_pc~0); 16048#L239-17 is_transmit1_triggered_~__retres1~1#1 := 0; 16046#L250-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16044#L251-5 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 16042#L551-15 assume !(0 != activate_threads_~tmp___0~0#1); 16040#L551-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16038#L258-15 assume !(1 == ~t2_pc~0); 16036#L258-17 is_transmit2_triggered_~__retres1~2#1 := 0; 16034#L269-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16033#L270-5 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 16032#L559-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 16031#L559-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16030#L277-15 assume !(1 == ~t3_pc~0); 16028#L277-17 is_transmit3_triggered_~__retres1~3#1 := 0; 16027#L288-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16026#L289-5 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 16025#L567-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 16024#L567-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15446#L489-3 assume !(1 == ~M_E~0); 14257#L489-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 14255#L494-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 14253#L499-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 14251#L504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 14249#L509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 14247#L514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 14245#L519-3 assume !(1 == ~E_3~0); 14243#L524-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 14236#L332-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 14215#L354-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 14208#L355-1 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 14202#L709 assume !(0 == start_simulation_~tmp~3#1); 13786#L709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 13787#L332-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 13882#L354-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 13883#L355-2 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 13880#L664 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 13881#L671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 14004#L672 start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 13935#L722 assume !(0 != start_simulation_~tmp___0~1#1); 13848#L690-2 [2021-12-16 10:04:35,822 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:35,822 INFO L85 PathProgramCache]: Analyzing trace with hash -495171133, now seen corresponding path program 1 times [2021-12-16 10:04:35,823 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:35,823 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1305083928] [2021-12-16 10:04:35,823 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:35,823 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:35,829 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:04:35,845 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:04:35,845 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:04:35,846 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1305083928] [2021-12-16 10:04:35,846 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1305083928] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:04:35,846 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:04:35,846 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:04:35,846 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [529156123] [2021-12-16 10:04:35,846 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:04:35,847 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:04:35,847 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:35,847 INFO L85 PathProgramCache]: Analyzing trace with hash -2097564862, now seen corresponding path program 1 times [2021-12-16 10:04:35,847 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:35,848 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [767359681] [2021-12-16 10:04:35,848 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:35,848 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:35,853 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:04:35,877 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:04:35,878 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:04:35,878 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [767359681] [2021-12-16 10:04:35,878 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [767359681] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:04:35,878 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:04:35,878 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-16 10:04:35,879 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [186003281] [2021-12-16 10:04:35,879 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:04:35,879 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:04:35,879 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:04:35,880 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-16 10:04:35,880 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-16 10:04:35,880 INFO L87 Difference]: Start difference. First operand 2413 states and 3519 transitions. cyclomatic complexity: 1110 Second operand has 4 states, 4 states have (on average 12.75) internal successors, (51), 3 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:04:35,922 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:04:35,922 INFO L93 Difference]: Finished difference Result 3460 states and 5000 transitions. [2021-12-16 10:04:35,923 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-16 10:04:35,923 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3460 states and 5000 transitions. [2021-12-16 10:04:35,974 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 3378 [2021-12-16 10:04:36,002 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3460 states to 3460 states and 5000 transitions. [2021-12-16 10:04:36,002 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3460 [2021-12-16 10:04:36,004 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3460 [2021-12-16 10:04:36,004 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3460 states and 5000 transitions. [2021-12-16 10:04:36,007 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:04:36,007 INFO L681 BuchiCegarLoop]: Abstraction has 3460 states and 5000 transitions. [2021-12-16 10:04:36,008 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3460 states and 5000 transitions. [2021-12-16 10:04:36,044 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3460 to 2413. [2021-12-16 10:04:36,047 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2413 states, 2413 states have (on average 1.4479900538748447) internal successors, (3494), 2412 states have internal predecessors, (3494), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:04:36,051 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2413 states to 2413 states and 3494 transitions. [2021-12-16 10:04:36,051 INFO L704 BuchiCegarLoop]: Abstraction has 2413 states and 3494 transitions. [2021-12-16 10:04:36,051 INFO L587 BuchiCegarLoop]: Abstraction has 2413 states and 3494 transitions. [2021-12-16 10:04:36,052 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2021-12-16 10:04:36,052 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2413 states and 3494 transitions. [2021-12-16 10:04:36,057 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2341 [2021-12-16 10:04:36,058 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:04:36,058 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:04:36,059 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:36,059 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:36,059 INFO L791 eck$LassoCheckResult]: Stem: 20030#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 19968#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 19786#L653 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 19751#L297 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 19752#L304 assume 1 == ~m_i~0;~m_st~0 := 0; 19867#L304-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 19709#L309-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 19710#L314-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 19889#L319-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 19722#L441 assume !(0 == ~M_E~0); 19723#L441-2 assume !(0 == ~T1_E~0); 19862#L446-1 assume !(0 == ~T2_E~0); 19829#L451-1 assume !(0 == ~T3_E~0); 19830#L456-1 assume !(0 == ~E_M~0); 19972#L461-1 assume !(0 == ~E_1~0); 19973#L466-1 assume !(0 == ~E_2~0); 19992#L471-1 assume !(0 == ~E_3~0); 19759#L476-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 19760#L220 assume !(1 == ~m_pc~0); 19794#L220-2 is_master_triggered_~__retres1~0#1 := 0; 19795#L231 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19848#L232 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 19792#L543 assume !(0 != activate_threads_~tmp~1#1); 19793#L543-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19952#L239 assume !(1 == ~t1_pc~0); 19953#L239-2 is_transmit1_triggered_~__retres1~1#1 := 0; 19970#L250 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19998#L251 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 19957#L551 assume !(0 != activate_threads_~tmp___0~0#1); 19958#L551-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 19959#L258 assume !(1 == ~t2_pc~0); 19960#L258-2 is_transmit2_triggered_~__retres1~2#1 := 0; 19820#L269 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19680#L270 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 19681#L559 assume !(0 != activate_threads_~tmp___1~0#1); 19876#L559-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19877#L277 assume !(1 == ~t3_pc~0); 19926#L277-2 is_transmit3_triggered_~__retres1~3#1 := 0; 19735#L288 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19736#L289 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 19784#L567 assume !(0 != activate_threads_~tmp___2~0#1); 19785#L567-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19826#L489 assume !(1 == ~M_E~0); 19971#L489-2 assume !(1 == ~T1_E~0); 19905#L494-1 assume !(1 == ~T2_E~0); 19775#L499-1 assume !(1 == ~T3_E~0); 19776#L504-1 assume !(1 == ~E_M~0); 19868#L509-1 assume !(1 == ~E_1~0); 19762#L514-1 assume !(1 == ~E_2~0); 19763#L519-1 assume !(1 == ~E_3~0); 19770#L524-1 assume { :end_inline_reset_delta_events } true; 19771#L690-2 [2021-12-16 10:04:36,059 INFO L793 eck$LassoCheckResult]: Loop: 19771#L690-2 assume !false; 21754#L691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 21747#L416 assume !false; 21743#L365 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 21732#L332 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 21725#L354 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 21720#L355 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 21714#L369 assume !(0 != eval_~tmp~0#1); 21711#L431 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 21707#L297-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 21703#L441-3 assume !(0 == ~M_E~0); 21699#L441-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 21538#L446-3 assume !(0 == ~T2_E~0); 21535#L451-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 21511#L456-3 assume 0 == ~E_M~0;~E_M~0 := 1; 21507#L461-3 assume 0 == ~E_1~0;~E_1~0 := 1; 21299#L466-3 assume 0 == ~E_2~0;~E_2~0 := 1; 21297#L471-3 assume !(0 == ~E_3~0); 21296#L476-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 21295#L220-15 assume !(1 == ~m_pc~0); 21294#L220-17 is_master_triggered_~__retres1~0#1 := 0; 21293#L231-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21292#L232-5 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 21290#L543-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 21288#L543-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 21286#L239-15 assume !(1 == ~t1_pc~0); 21284#L239-17 is_transmit1_triggered_~__retres1~1#1 := 0; 21282#L250-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 21280#L251-5 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 21278#L551-15 assume !(0 != activate_threads_~tmp___0~0#1); 21276#L551-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 21274#L258-15 assume !(1 == ~t2_pc~0); 21272#L258-17 is_transmit2_triggered_~__retres1~2#1 := 0; 21270#L269-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 21268#L270-5 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 21266#L559-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 21264#L559-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 21262#L277-15 assume !(1 == ~t3_pc~0); 21259#L277-17 is_transmit3_triggered_~__retres1~3#1 := 0; 21257#L288-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 21254#L289-5 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 21253#L567-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 21252#L567-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21251#L489-3 assume !(1 == ~M_E~0); 20910#L489-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 21248#L494-3 assume !(1 == ~T2_E~0); 21246#L499-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 21244#L504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 21242#L509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 21240#L514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 21238#L519-3 assume !(1 == ~E_3~0); 21235#L524-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 20135#L332-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 20115#L354-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 20109#L355-1 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 20102#L709 assume !(0 == start_simulation_~tmp~3#1); 20103#L709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 21774#L332-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 21771#L354-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 21770#L355-2 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 21769#L664 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 21767#L671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 21765#L672 start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 21764#L722 assume !(0 != start_simulation_~tmp___0~1#1); 19771#L690-2 [2021-12-16 10:04:36,060 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:36,060 INFO L85 PathProgramCache]: Analyzing trace with hash 1279836229, now seen corresponding path program 1 times [2021-12-16 10:04:36,060 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:36,060 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1053582416] [2021-12-16 10:04:36,060 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:36,061 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:36,068 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:04:36,069 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-16 10:04:36,076 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:04:36,101 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-16 10:04:36,102 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:36,102 INFO L85 PathProgramCache]: Analyzing trace with hash 508458692, now seen corresponding path program 1 times [2021-12-16 10:04:36,102 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:36,102 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2398336] [2021-12-16 10:04:36,102 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:36,102 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:36,111 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:04:36,136 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:04:36,136 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:04:36,136 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2398336] [2021-12-16 10:04:36,137 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2398336] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:04:36,137 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:04:36,137 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-16 10:04:36,137 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1166939674] [2021-12-16 10:04:36,137 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:04:36,137 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:04:36,137 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:04:36,138 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-16 10:04:36,138 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-16 10:04:36,138 INFO L87 Difference]: Start difference. First operand 2413 states and 3494 transitions. cyclomatic complexity: 1085 Second operand has 5 states, 5 states have (on average 12.8) internal successors, (64), 5 states have internal predecessors, (64), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:04:36,209 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:04:36,209 INFO L93 Difference]: Finished difference Result 4192 states and 5963 transitions. [2021-12-16 10:04:36,210 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2021-12-16 10:04:36,210 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4192 states and 5963 transitions. [2021-12-16 10:04:36,223 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4100 [2021-12-16 10:04:36,236 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4192 states to 4192 states and 5963 transitions. [2021-12-16 10:04:36,237 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4192 [2021-12-16 10:04:36,239 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4192 [2021-12-16 10:04:36,240 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4192 states and 5963 transitions. [2021-12-16 10:04:36,244 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:04:36,244 INFO L681 BuchiCegarLoop]: Abstraction has 4192 states and 5963 transitions. [2021-12-16 10:04:36,246 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4192 states and 5963 transitions. [2021-12-16 10:04:36,285 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4192 to 2449. [2021-12-16 10:04:36,288 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2449 states, 2449 states have (on average 1.4414046549612087) internal successors, (3530), 2448 states have internal predecessors, (3530), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:04:36,297 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2449 states to 2449 states and 3530 transitions. [2021-12-16 10:04:36,298 INFO L704 BuchiCegarLoop]: Abstraction has 2449 states and 3530 transitions. [2021-12-16 10:04:36,298 INFO L587 BuchiCegarLoop]: Abstraction has 2449 states and 3530 transitions. [2021-12-16 10:04:36,298 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2021-12-16 10:04:36,298 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2449 states and 3530 transitions. [2021-12-16 10:04:36,303 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2377 [2021-12-16 10:04:36,303 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:04:36,304 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:04:36,304 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:36,304 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:36,305 INFO L791 eck$LassoCheckResult]: Stem: 26663#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 26599#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 26409#L653 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 26374#L297 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 26375#L304 assume 1 == ~m_i~0;~m_st~0 := 0; 26496#L304-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 26331#L309-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 26332#L314-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 26517#L319-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 26344#L441 assume !(0 == ~M_E~0); 26345#L441-2 assume !(0 == ~T1_E~0); 26491#L446-1 assume !(0 == ~T2_E~0); 26455#L451-1 assume !(0 == ~T3_E~0); 26456#L456-1 assume !(0 == ~E_M~0); 26605#L461-1 assume !(0 == ~E_1~0); 26606#L466-1 assume !(0 == ~E_2~0); 26621#L471-1 assume !(0 == ~E_3~0); 26382#L476-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 26383#L220 assume !(1 == ~m_pc~0); 26417#L220-2 is_master_triggered_~__retres1~0#1 := 0; 26418#L231 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 26475#L232 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 26415#L543 assume !(0 != activate_threads_~tmp~1#1); 26416#L543-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26584#L239 assume !(1 == ~t1_pc~0); 26585#L239-2 is_transmit1_triggered_~__retres1~1#1 := 0; 26603#L250 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 26630#L251 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 26588#L551 assume !(0 != activate_threads_~tmp___0~0#1); 26589#L551-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 26590#L258 assume !(1 == ~t2_pc~0); 26591#L258-2 is_transmit2_triggered_~__retres1~2#1 := 0; 26446#L269 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 26301#L270 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 26302#L559 assume !(0 != activate_threads_~tmp___1~0#1); 26505#L559-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 26506#L277 assume !(1 == ~t3_pc~0); 26558#L277-2 is_transmit3_triggered_~__retres1~3#1 := 0; 26357#L288 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 26358#L289 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 26407#L567 assume !(0 != activate_threads_~tmp___2~0#1); 26408#L567-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 26452#L489 assume !(1 == ~M_E~0); 26604#L489-2 assume !(1 == ~T1_E~0); 26537#L494-1 assume !(1 == ~T2_E~0); 26396#L499-1 assume !(1 == ~T3_E~0); 26397#L504-1 assume !(1 == ~E_M~0); 26497#L509-1 assume !(1 == ~E_1~0); 26384#L514-1 assume !(1 == ~E_2~0); 26385#L519-1 assume !(1 == ~E_3~0); 26393#L524-1 assume { :end_inline_reset_delta_events } true; 26394#L690-2 [2021-12-16 10:04:36,305 INFO L793 eck$LassoCheckResult]: Loop: 26394#L690-2 assume !false; 28620#L691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 28616#L416 assume !false; 28475#L365 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 28473#L332 assume !(0 == ~m_st~0); 28474#L336 assume !(0 == ~t1_st~0); 28472#L340 assume !(0 == ~t2_st~0); 28469#L344 assume !(0 == ~t3_st~0);exists_runnable_thread_~__retres1~4#1 := 0; 28468#L354 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 28467#L355 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 27863#L369 assume !(0 != eval_~tmp~0#1); 27864#L431 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 26592#L297-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 26593#L441-3 assume !(0 == ~M_E~0); 28518#L441-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 26623#L446-3 assume !(0 == ~T2_E~0); 26624#L451-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 26353#L456-3 assume 0 == ~E_M~0;~E_M~0 := 1; 26354#L461-3 assume 0 == ~E_1~0;~E_1~0 := 1; 26542#L466-3 assume 0 == ~E_2~0;~E_2~0 := 1; 26543#L471-3 assume !(0 == ~E_3~0); 26410#L476-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 26411#L220-15 assume !(1 == ~m_pc~0); 26472#L220-17 is_master_triggered_~__retres1~0#1 := 0; 28516#L231-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 28515#L232-5 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 28514#L543-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 26503#L543-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26504#L239-15 assume !(1 == ~t1_pc~0); 26628#L239-17 is_transmit1_triggered_~__retres1~1#1 := 0; 26629#L250-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 26650#L251-5 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 26329#L551-15 assume !(0 != activate_threads_~tmp___0~0#1); 26330#L551-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 26667#L258-15 assume !(1 == ~t2_pc~0); 26668#L258-17 is_transmit2_triggered_~__retres1~2#1 := 0; 26648#L269-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 26494#L270-5 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 26495#L559-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 26607#L559-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 26608#L277-15 assume !(1 == ~t3_pc~0); 26306#L277-17 is_transmit3_triggered_~__retres1~3#1 := 0; 26307#L288-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 28506#L289-5 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 26640#L567-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 26641#L567-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 26333#L489-3 assume !(1 == ~M_E~0); 26334#L489-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 26601#L494-3 assume !(1 == ~T2_E~0); 26602#L499-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 26473#L504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 26474#L509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 26656#L514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 26657#L519-3 assume !(1 == ~E_3~0); 26372#L524-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 26373#L332-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 28650#L354-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 28647#L355-1 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 28644#L709 assume !(0 == start_simulation_~tmp~3#1); 28642#L709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 28640#L332-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 28635#L354-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 28633#L355-2 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 28631#L664 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 28629#L671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 28627#L672 start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 28623#L722 assume !(0 != start_simulation_~tmp___0~1#1); 26394#L690-2 [2021-12-16 10:04:36,305 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:36,305 INFO L85 PathProgramCache]: Analyzing trace with hash 1279836229, now seen corresponding path program 2 times [2021-12-16 10:04:36,306 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:36,306 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [796568129] [2021-12-16 10:04:36,306 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:36,306 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:36,312 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:04:36,312 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-16 10:04:36,318 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:04:36,328 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-16 10:04:36,330 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:36,330 INFO L85 PathProgramCache]: Analyzing trace with hash -2116089398, now seen corresponding path program 1 times [2021-12-16 10:04:36,330 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:36,330 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1964880888] [2021-12-16 10:04:36,330 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:36,331 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:36,336 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:04:36,354 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:04:36,355 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:04:36,355 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1964880888] [2021-12-16 10:04:36,355 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1964880888] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:04:36,355 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:04:36,355 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-16 10:04:36,355 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [928991539] [2021-12-16 10:04:36,355 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:04:36,356 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:04:36,356 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:04:36,356 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-16 10:04:36,357 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-16 10:04:36,357 INFO L87 Difference]: Start difference. First operand 2449 states and 3530 transitions. cyclomatic complexity: 1085 Second operand has 5 states, 5 states have (on average 13.4) internal successors, (67), 5 states have internal predecessors, (67), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:04:36,454 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:04:36,455 INFO L93 Difference]: Finished difference Result 7852 states and 11195 transitions. [2021-12-16 10:04:36,455 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2021-12-16 10:04:36,456 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7852 states and 11195 transitions. [2021-12-16 10:04:36,531 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 7720 [2021-12-16 10:04:36,559 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7852 states to 7852 states and 11195 transitions. [2021-12-16 10:04:36,559 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7852 [2021-12-16 10:04:36,565 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7852 [2021-12-16 10:04:36,565 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7852 states and 11195 transitions. [2021-12-16 10:04:36,574 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:04:36,574 INFO L681 BuchiCegarLoop]: Abstraction has 7852 states and 11195 transitions. [2021-12-16 10:04:36,578 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7852 states and 11195 transitions. [2021-12-16 10:04:36,620 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7852 to 2485. [2021-12-16 10:04:36,624 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2485 states, 2485 states have (on average 1.435010060362173) internal successors, (3566), 2484 states have internal predecessors, (3566), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:04:36,628 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2485 states to 2485 states and 3566 transitions. [2021-12-16 10:04:36,628 INFO L704 BuchiCegarLoop]: Abstraction has 2485 states and 3566 transitions. [2021-12-16 10:04:36,628 INFO L587 BuchiCegarLoop]: Abstraction has 2485 states and 3566 transitions. [2021-12-16 10:04:36,628 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2021-12-16 10:04:36,629 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2485 states and 3566 transitions. [2021-12-16 10:04:36,633 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2413 [2021-12-16 10:04:36,633 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:04:36,633 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:04:36,634 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:36,634 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:36,634 INFO L791 eck$LassoCheckResult]: Stem: 36963#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 36903#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 36726#L653 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 36692#L297 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 36693#L304 assume 1 == ~m_i~0;~m_st~0 := 0; 36804#L304-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 36649#L309-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 36650#L314-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 36823#L319-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 36662#L441 assume !(0 == ~M_E~0); 36663#L441-2 assume !(0 == ~T1_E~0); 36799#L446-1 assume !(0 == ~T2_E~0); 36768#L451-1 assume !(0 == ~T3_E~0); 36769#L456-1 assume !(0 == ~E_M~0); 36908#L461-1 assume !(0 == ~E_1~0); 36909#L466-1 assume !(0 == ~E_2~0); 36927#L471-1 assume !(0 == ~E_3~0); 36700#L476-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 36701#L220 assume !(1 == ~m_pc~0); 36734#L220-2 is_master_triggered_~__retres1~0#1 := 0; 36735#L231 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 36785#L232 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 36732#L543 assume !(0 != activate_threads_~tmp~1#1); 36733#L543-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 36889#L239 assume !(1 == ~t1_pc~0); 36890#L239-2 is_transmit1_triggered_~__retres1~1#1 := 0; 36905#L250 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 36933#L251 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 36894#L551 assume !(0 != activate_threads_~tmp___0~0#1); 36895#L551-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 36896#L258 assume !(1 == ~t2_pc~0); 36897#L258-2 is_transmit2_triggered_~__retres1~2#1 := 0; 36759#L269 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 36619#L270 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 36620#L559 assume !(0 != activate_threads_~tmp___1~0#1); 36811#L559-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 36812#L277 assume !(1 == ~t3_pc~0); 36863#L277-2 is_transmit3_triggered_~__retres1~3#1 := 0; 36675#L288 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 36676#L289 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 36724#L567 assume !(0 != activate_threads_~tmp___2~0#1); 36725#L567-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 36765#L489 assume !(1 == ~M_E~0); 36906#L489-2 assume !(1 == ~T1_E~0); 36841#L494-1 assume !(1 == ~T2_E~0); 36715#L499-1 assume !(1 == ~T3_E~0); 36716#L504-1 assume !(1 == ~E_M~0); 36805#L509-1 assume !(1 == ~E_1~0); 36702#L514-1 assume !(1 == ~E_2~0); 36703#L519-1 assume !(1 == ~E_3~0); 36710#L524-1 assume { :end_inline_reset_delta_events } true; 36711#L690-2 [2021-12-16 10:04:36,635 INFO L793 eck$LassoCheckResult]: Loop: 36711#L690-2 assume !false; 37943#L691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 37938#L416 assume !false; 37937#L365 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 37935#L332 assume !(0 == ~m_st~0); 37936#L336 assume !(0 == ~t1_st~0); 37932#L340 assume !(0 == ~t2_st~0); 37933#L344 assume !(0 == ~t3_st~0);exists_runnable_thread_~__retres1~4#1 := 0; 37934#L354 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 37926#L355 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 37927#L369 assume !(0 != eval_~tmp~0#1); 36971#L431 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 36898#L297-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 36884#L441-3 assume !(0 == ~M_E~0); 36612#L441-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 36613#L446-3 assume !(0 == ~T2_E~0); 36879#L451-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 36880#L456-3 assume 0 == ~E_M~0;~E_M~0 := 1; 36739#L461-3 assume 0 == ~E_1~0;~E_1~0 := 1; 36740#L466-3 assume 0 == ~E_2~0;~E_2~0 := 1; 36846#L471-3 assume !(0 == ~E_3~0); 36728#L476-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 36729#L220-15 assume !(1 == ~m_pc~0); 36784#L220-17 is_master_triggered_~__retres1~0#1 := 0; 36852#L231-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 36653#L232-5 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 36654#L543-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 36810#L543-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 36800#L239-15 assume !(1 == ~t1_pc~0); 36801#L239-17 is_transmit1_triggered_~__retres1~1#1 := 0; 38014#L250-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 38012#L251-5 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 38010#L551-15 assume !(0 != activate_threads_~tmp___0~0#1); 38008#L551-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 38006#L258-15 assume !(1 == ~t2_pc~0); 38004#L258-17 is_transmit2_triggered_~__retres1~2#1 := 0; 38002#L269-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 38000#L270-5 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 37998#L559-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 37996#L559-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 37994#L277-15 assume !(1 == ~t3_pc~0); 37991#L277-17 is_transmit3_triggered_~__retres1~3#1 := 0; 37988#L288-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 37986#L289-5 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 37984#L567-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 37982#L567-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 37980#L489-3 assume !(1 == ~M_E~0); 37977#L489-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 37976#L494-3 assume !(1 == ~T2_E~0); 37975#L499-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 37974#L504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 37973#L509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 37972#L514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 37971#L519-3 assume !(1 == ~E_3~0); 37970#L524-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 37968#L332-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 37964#L354-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 37962#L355-1 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 37958#L709 assume !(0 == start_simulation_~tmp~3#1); 37957#L709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 37955#L332-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 37952#L354-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 37950#L355-2 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 37948#L664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 37946#L671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 37945#L672 start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 37944#L722 assume !(0 != start_simulation_~tmp___0~1#1); 36711#L690-2 [2021-12-16 10:04:36,635 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:36,635 INFO L85 PathProgramCache]: Analyzing trace with hash 1279836229, now seen corresponding path program 3 times [2021-12-16 10:04:36,635 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:36,635 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1882087995] [2021-12-16 10:04:36,635 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:36,635 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:36,640 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:04:36,640 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-16 10:04:36,643 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:04:36,648 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-16 10:04:36,649 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:36,649 INFO L85 PathProgramCache]: Analyzing trace with hash -2116148980, now seen corresponding path program 1 times [2021-12-16 10:04:36,649 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:36,649 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [625541658] [2021-12-16 10:04:36,649 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:36,649 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:36,656 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:04:36,687 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:04:36,687 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:04:36,688 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [625541658] [2021-12-16 10:04:36,688 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [625541658] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:04:36,688 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:04:36,688 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-16 10:04:36,688 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [209063111] [2021-12-16 10:04:36,688 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:04:36,688 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:04:36,688 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:04:36,689 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-16 10:04:36,689 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-16 10:04:36,689 INFO L87 Difference]: Start difference. First operand 2485 states and 3566 transitions. cyclomatic complexity: 1085 Second operand has 5 states, 5 states have (on average 13.4) internal successors, (67), 5 states have internal predecessors, (67), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:04:36,789 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:04:36,790 INFO L93 Difference]: Finished difference Result 4924 states and 7015 transitions. [2021-12-16 10:04:36,790 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-16 10:04:36,790 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4924 states and 7015 transitions. [2021-12-16 10:04:36,802 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4844 [2021-12-16 10:04:36,852 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4924 states to 4924 states and 7015 transitions. [2021-12-16 10:04:36,852 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4924 [2021-12-16 10:04:36,855 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4924 [2021-12-16 10:04:36,855 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4924 states and 7015 transitions. [2021-12-16 10:04:36,859 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:04:36,859 INFO L681 BuchiCegarLoop]: Abstraction has 4924 states and 7015 transitions. [2021-12-16 10:04:36,861 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4924 states and 7015 transitions. [2021-12-16 10:04:36,887 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4924 to 2566. [2021-12-16 10:04:36,890 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2566 states, 2566 states have (on average 1.4127045985970381) internal successors, (3625), 2565 states have internal predecessors, (3625), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:04:36,893 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2566 states to 2566 states and 3625 transitions. [2021-12-16 10:04:36,893 INFO L704 BuchiCegarLoop]: Abstraction has 2566 states and 3625 transitions. [2021-12-16 10:04:36,893 INFO L587 BuchiCegarLoop]: Abstraction has 2566 states and 3625 transitions. [2021-12-16 10:04:36,893 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2021-12-16 10:04:36,893 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2566 states and 3625 transitions. [2021-12-16 10:04:36,897 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2494 [2021-12-16 10:04:36,897 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:04:36,897 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:04:36,898 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:36,898 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:36,898 INFO L791 eck$LassoCheckResult]: Stem: 44415#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 44342#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 44148#L653 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 44113#L297 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 44114#L304 assume 1 == ~m_i~0;~m_st~0 := 0; 44233#L304-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 44070#L309-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 44071#L314-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 44254#L319-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 44083#L441 assume !(0 == ~M_E~0); 44084#L441-2 assume !(0 == ~T1_E~0); 44227#L446-1 assume !(0 == ~T2_E~0); 44192#L451-1 assume !(0 == ~T3_E~0); 44193#L456-1 assume !(0 == ~E_M~0); 44349#L461-1 assume !(0 == ~E_1~0); 44350#L466-1 assume !(0 == ~E_2~0); 44370#L471-1 assume !(0 == ~E_3~0); 44121#L476-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 44122#L220 assume !(1 == ~m_pc~0); 44156#L220-2 is_master_triggered_~__retres1~0#1 := 0; 44157#L231 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 44212#L232 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 44154#L543 assume !(0 != activate_threads_~tmp~1#1); 44155#L543-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 44327#L239 assume !(1 == ~t1_pc~0); 44328#L239-2 is_transmit1_triggered_~__retres1~1#1 := 0; 44346#L250 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 44382#L251 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 44332#L551 assume !(0 != activate_threads_~tmp___0~0#1); 44333#L551-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 44334#L258 assume !(1 == ~t2_pc~0); 44335#L258-2 is_transmit2_triggered_~__retres1~2#1 := 0; 44185#L269 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 44041#L270 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 44042#L559 assume !(0 != activate_threads_~tmp___1~0#1); 44240#L559-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 44241#L277 assume !(1 == ~t3_pc~0); 44299#L277-2 is_transmit3_triggered_~__retres1~3#1 := 0; 44096#L288 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 44097#L289 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 44146#L567 assume !(0 != activate_threads_~tmp___2~0#1); 44147#L567-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 44189#L489 assume !(1 == ~M_E~0); 44347#L489-2 assume !(1 == ~T1_E~0); 44275#L494-1 assume !(1 == ~T2_E~0); 44137#L499-1 assume !(1 == ~T3_E~0); 44138#L504-1 assume !(1 == ~E_M~0); 44234#L509-1 assume !(1 == ~E_1~0); 44123#L514-1 assume !(1 == ~E_2~0); 44124#L519-1 assume !(1 == ~E_3~0); 44132#L524-1 assume { :end_inline_reset_delta_events } true; 44133#L690-2 [2021-12-16 10:04:36,898 INFO L793 eck$LassoCheckResult]: Loop: 44133#L690-2 assume !false; 45333#L691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 45319#L416 assume !false; 45314#L365 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 45308#L332 assume !(0 == ~m_st~0); 45309#L336 assume !(0 == ~t1_st~0); 45305#L340 assume !(0 == ~t2_st~0); 45306#L344 assume !(0 == ~t3_st~0);exists_runnable_thread_~__retres1~4#1 := 0; 45307#L354 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 44986#L355 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 44987#L369 assume !(0 != eval_~tmp~0#1); 46391#L431 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 46390#L297-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 46389#L441-3 assume !(0 == ~M_E~0); 46388#L441-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 46387#L446-3 assume !(0 == ~T2_E~0); 46386#L451-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 46385#L456-3 assume 0 == ~E_M~0;~E_M~0 := 1; 46384#L461-3 assume 0 == ~E_1~0;~E_1~0 := 1; 46383#L466-3 assume 0 == ~E_2~0;~E_2~0 := 1; 46382#L471-3 assume !(0 == ~E_3~0); 44149#L476-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 44150#L220-15 assume !(1 == ~m_pc~0); 44211#L220-17 is_master_triggered_~__retres1~0#1 := 0; 45492#L231-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 45490#L232-5 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 45488#L543-15 assume !(0 != activate_threads_~tmp~1#1); 45486#L543-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 45484#L239-15 assume !(1 == ~t1_pc~0); 45482#L239-17 is_transmit1_triggered_~__retres1~1#1 := 0; 45480#L250-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 45478#L251-5 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 45476#L551-15 assume !(0 != activate_threads_~tmp___0~0#1); 45474#L551-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 45471#L258-15 assume !(1 == ~t2_pc~0); 45467#L258-17 is_transmit2_triggered_~__retres1~2#1 := 0; 45463#L269-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 45459#L270-5 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 45455#L559-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 45451#L559-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 45447#L277-15 assume !(1 == ~t3_pc~0); 45442#L277-17 is_transmit3_triggered_~__retres1~3#1 := 0; 45438#L288-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 45434#L289-5 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 45430#L567-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 45425#L567-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 45421#L489-3 assume !(1 == ~M_E~0); 45407#L489-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 45413#L494-3 assume !(1 == ~T2_E~0); 45351#L499-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 45345#L504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 45343#L509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 45341#L514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 45338#L519-3 assume !(1 == ~E_3~0); 45336#L524-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 45322#L332-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 45315#L354-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 45310#L355-1 start_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 45156#L709 assume !(0 == start_simulation_~tmp~3#1); 45157#L709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret15#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 45349#L332-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 45344#L354-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 45342#L355-2 stop_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret15#1;havoc stop_simulation_#t~ret15#1; 45340#L664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 45337#L671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 45335#L672 start_simulation_#t~ret17#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 45334#L722 assume !(0 != start_simulation_~tmp___0~1#1); 44133#L690-2 [2021-12-16 10:04:36,898 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:36,899 INFO L85 PathProgramCache]: Analyzing trace with hash 1279836229, now seen corresponding path program 4 times [2021-12-16 10:04:36,899 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:36,899 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1202127687] [2021-12-16 10:04:36,899 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:36,899 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:36,903 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:04:36,903 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-16 10:04:36,905 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:04:36,926 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-16 10:04:36,926 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:36,926 INFO L85 PathProgramCache]: Analyzing trace with hash -1692502258, now seen corresponding path program 1 times [2021-12-16 10:04:36,926 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:36,926 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [781387562] [2021-12-16 10:04:36,926 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:36,926 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:36,930 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:04:36,940 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:04:36,941 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:04:36,941 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [781387562] [2021-12-16 10:04:36,941 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [781387562] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:04:36,941 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:04:36,941 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:04:36,941 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [523525057] [2021-12-16 10:04:36,941 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:04:36,941 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:04:36,941 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:04:36,942 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-16 10:04:36,942 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-16 10:04:36,942 INFO L87 Difference]: Start difference. First operand 2566 states and 3625 transitions. cyclomatic complexity: 1063 Second operand has 3 states, 3 states have (on average 22.333333333333332) internal successors, (67), 3 states have internal predecessors, (67), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:04:36,970 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:04:36,970 INFO L93 Difference]: Finished difference Result 3876 states and 5379 transitions. [2021-12-16 10:04:36,970 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-16 10:04:36,971 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3876 states and 5379 transitions. [2021-12-16 10:04:36,980 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 3802 [2021-12-16 10:04:36,986 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3876 states to 3876 states and 5379 transitions. [2021-12-16 10:04:36,986 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3876 [2021-12-16 10:04:36,988 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3876 [2021-12-16 10:04:36,988 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3876 states and 5379 transitions. [2021-12-16 10:04:36,991 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:04:36,991 INFO L681 BuchiCegarLoop]: Abstraction has 3876 states and 5379 transitions. [2021-12-16 10:04:36,993 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3876 states and 5379 transitions. [2021-12-16 10:04:37,046 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3876 to 3744. [2021-12-16 10:04:37,050 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3744 states, 3744 states have (on average 1.390224358974359) internal successors, (5205), 3743 states have internal predecessors, (5205), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:04:37,055 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3744 states to 3744 states and 5205 transitions. [2021-12-16 10:04:37,055 INFO L704 BuchiCegarLoop]: Abstraction has 3744 states and 5205 transitions. [2021-12-16 10:04:37,055 INFO L587 BuchiCegarLoop]: Abstraction has 3744 states and 5205 transitions. [2021-12-16 10:04:37,055 INFO L425 BuchiCegarLoop]: ======== Iteration 13============ [2021-12-16 10:04:37,055 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3744 states and 5205 transitions. [2021-12-16 10:04:37,061 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 3670 [2021-12-16 10:04:37,062 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:04:37,062 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:04:37,063 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:37,063 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:37,063 INFO L791 eck$LassoCheckResult]: Stem: 50852#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 50791#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 50597#L653 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 50563#L297 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 50564#L304 assume 1 == ~m_i~0;~m_st~0 := 0; 50684#L304-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 50520#L309-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 50521#L314-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 50705#L319-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 50533#L441 assume !(0 == ~M_E~0); 50534#L441-2 assume !(0 == ~T1_E~0); 50677#L446-1 assume !(0 == ~T2_E~0); 50640#L451-1 assume !(0 == ~T3_E~0); 50641#L456-1 assume !(0 == ~E_M~0); 50795#L461-1 assume !(0 == ~E_1~0); 50796#L466-1 assume !(0 == ~E_2~0); 50817#L471-1 assume !(0 == ~E_3~0); 50571#L476-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 50572#L220 assume !(1 == ~m_pc~0); 50605#L220-2 is_master_triggered_~__retres1~0#1 := 0; 50606#L231 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 50658#L232 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 50603#L543 assume !(0 != activate_threads_~tmp~1#1); 50604#L543-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 50776#L239 assume !(1 == ~t1_pc~0); 50777#L239-2 is_transmit1_triggered_~__retres1~1#1 := 0; 50793#L250 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 50822#L251 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 50782#L551 assume !(0 != activate_threads_~tmp___0~0#1); 50783#L551-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 50784#L258 assume !(1 == ~t2_pc~0); 50785#L258-2 is_transmit2_triggered_~__retres1~2#1 := 0; 50631#L269 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 50489#L270 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 50490#L559 assume !(0 != activate_threads_~tmp___1~0#1); 50693#L559-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 50694#L277 assume !(1 == ~t3_pc~0); 50743#L277-2 is_transmit3_triggered_~__retres1~3#1 := 0; 50545#L288 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 50546#L289 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 50595#L567 assume !(0 != activate_threads_~tmp___2~0#1); 50596#L567-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 50637#L489 assume !(1 == ~M_E~0); 50794#L489-2 assume !(1 == ~T1_E~0); 50722#L494-1 assume !(1 == ~T2_E~0); 50584#L499-1 assume !(1 == ~T3_E~0); 50585#L504-1 assume !(1 == ~E_M~0); 50685#L509-1 assume !(1 == ~E_1~0); 50573#L514-1 assume !(1 == ~E_2~0); 50574#L519-1 assume !(1 == ~E_3~0); 50580#L524-1 assume { :end_inline_reset_delta_events } true; 50581#L690-2 assume !false; 51812#L691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 51806#L416 [2021-12-16 10:04:37,063 INFO L793 eck$LassoCheckResult]: Loop: 51806#L416 assume !false; 51803#L365 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 51800#L332 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 51797#L354 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 51791#L355 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 51788#L369 assume 0 != eval_~tmp~0#1; 51784#L369-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 51771#L377 assume !(0 != eval_~tmp_ndt_1~0#1); 51772#L374 assume !(0 == ~t1_st~0); 51735#L388 assume !(0 == ~t2_st~0); 51811#L402 assume !(0 == ~t3_st~0); 51806#L416 [2021-12-16 10:04:37,063 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:37,063 INFO L85 PathProgramCache]: Analyzing trace with hash 1561976903, now seen corresponding path program 1 times [2021-12-16 10:04:37,063 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:37,063 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1848239879] [2021-12-16 10:04:37,063 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:37,064 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:37,069 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:04:37,069 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-16 10:04:37,073 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:04:37,087 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-16 10:04:37,088 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:37,088 INFO L85 PathProgramCache]: Analyzing trace with hash 258292880, now seen corresponding path program 1 times [2021-12-16 10:04:37,088 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:37,088 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [401177235] [2021-12-16 10:04:37,088 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:37,090 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:37,093 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:04:37,093 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-16 10:04:37,095 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:04:37,097 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-16 10:04:37,097 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:37,097 INFO L85 PathProgramCache]: Analyzing trace with hash 1139971210, now seen corresponding path program 1 times [2021-12-16 10:04:37,097 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:37,097 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [849082842] [2021-12-16 10:04:37,097 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:37,097 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:37,102 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:04:37,119 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:04:37,119 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:04:37,119 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [849082842] [2021-12-16 10:04:37,119 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [849082842] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:04:37,119 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:04:37,119 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:04:37,120 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [732556830] [2021-12-16 10:04:37,120 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:04:37,174 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:04:37,175 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-16 10:04:37,175 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-16 10:04:37,175 INFO L87 Difference]: Start difference. First operand 3744 states and 5205 transitions. cyclomatic complexity: 1467 Second operand has 3 states, 3 states have (on average 21.333333333333332) internal successors, (64), 3 states have internal predecessors, (64), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:04:37,242 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:04:37,242 INFO L93 Difference]: Finished difference Result 6711 states and 9219 transitions. [2021-12-16 10:04:37,255 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-16 10:04:37,256 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6711 states and 9219 transitions. [2021-12-16 10:04:37,274 INFO L131 ngComponentsAnalysis]: Automaton has 11 accepting balls. 6216 [2021-12-16 10:04:37,320 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6711 states to 6711 states and 9219 transitions. [2021-12-16 10:04:37,320 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6711 [2021-12-16 10:04:37,324 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6711 [2021-12-16 10:04:37,324 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6711 states and 9219 transitions. [2021-12-16 10:04:37,328 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:04:37,328 INFO L681 BuchiCegarLoop]: Abstraction has 6711 states and 9219 transitions. [2021-12-16 10:04:37,330 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6711 states and 9219 transitions. [2021-12-16 10:04:37,374 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6711 to 6466. [2021-12-16 10:04:37,390 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6466 states, 6466 states have (on average 1.3770491803278688) internal successors, (8904), 6465 states have internal predecessors, (8904), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:04:37,401 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6466 states to 6466 states and 8904 transitions. [2021-12-16 10:04:37,402 INFO L704 BuchiCegarLoop]: Abstraction has 6466 states and 8904 transitions. [2021-12-16 10:04:37,402 INFO L587 BuchiCegarLoop]: Abstraction has 6466 states and 8904 transitions. [2021-12-16 10:04:37,402 INFO L425 BuchiCegarLoop]: ======== Iteration 14============ [2021-12-16 10:04:37,402 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6466 states and 8904 transitions. [2021-12-16 10:04:37,449 INFO L131 ngComponentsAnalysis]: Automaton has 11 accepting balls. 5971 [2021-12-16 10:04:37,450 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:04:37,450 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:04:37,458 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:37,458 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:37,459 INFO L791 eck$LassoCheckResult]: Stem: 61362#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 61279#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 61059#L653 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 61025#L297 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 61026#L304 assume 1 == ~m_i~0;~m_st~0 := 0; 61158#L304-2 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 61159#L309-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 61298#L314-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 61299#L319-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 60993#L441 assume !(0 == ~M_E~0); 60994#L441-2 assume !(0 == ~T1_E~0); 61318#L446-1 assume !(0 == ~T2_E~0); 61319#L451-1 assume !(0 == ~T3_E~0); 61340#L456-1 assume !(0 == ~E_M~0); 61341#L461-1 assume !(0 == ~E_1~0); 61312#L466-1 assume !(0 == ~E_2~0); 61313#L471-1 assume !(0 == ~E_3~0); 61033#L476-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 61034#L220 assume !(1 == ~m_pc~0); 61067#L220-2 is_master_triggered_~__retres1~0#1 := 0; 61068#L231 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 61239#L232 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 61240#L543 assume !(0 != activate_threads_~tmp~1#1); 61370#L543-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 61371#L239 assume !(1 == ~t1_pc~0); 61284#L239-2 is_transmit1_triggered_~__retres1~1#1 := 0; 61285#L250 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 61322#L251 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 61323#L551 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 61267#L551-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 61268#L258 assume !(1 == ~t2_pc~0); 61269#L258-2 is_transmit2_triggered_~__retres1~2#1 := 0; 61099#L269 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 61100#L270 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 61282#L559 assume !(0 != activate_threads_~tmp___1~0#1); 61283#L559-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 61224#L277 assume !(1 == ~t3_pc~0); 61225#L277-2 is_transmit3_triggered_~__retres1~3#1 := 0; 61008#L288 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 61009#L289 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 61057#L567 assume !(0 != activate_threads_~tmp___2~0#1); 61058#L567-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 61360#L489 assume !(1 == ~M_E~0); 61361#L489-2 assume !(1 == ~T1_E~0); 61202#L494-1 assume !(1 == ~T2_E~0); 61203#L499-1 assume !(1 == ~T3_E~0); 61160#L504-1 assume !(1 == ~E_M~0); 61161#L509-1 assume !(1 == ~E_1~0); 61035#L514-1 assume !(1 == ~E_2~0); 61036#L519-1 assume !(1 == ~E_3~0); 61042#L524-1 assume { :end_inline_reset_delta_events } true; 61043#L690-2 assume !false; 61698#L691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 61694#L416 [2021-12-16 10:04:37,459 INFO L793 eck$LassoCheckResult]: Loop: 61694#L416 assume !false; 61674#L365 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 61675#L332 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 61659#L354 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 61660#L355 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 61647#L369 assume 0 != eval_~tmp~0#1; 61648#L369-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 61629#L377 assume !(0 != eval_~tmp_ndt_1~0#1); 61630#L374 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 61615#L391 assume !(0 != eval_~tmp_ndt_2~0#1); 61616#L388 assume !(0 == ~t2_st~0); 61697#L402 assume !(0 == ~t3_st~0); 61694#L416 [2021-12-16 10:04:37,459 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:37,459 INFO L85 PathProgramCache]: Analyzing trace with hash -934376957, now seen corresponding path program 1 times [2021-12-16 10:04:37,459 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:37,460 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1417727508] [2021-12-16 10:04:37,460 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:37,460 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:37,465 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:04:37,474 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:04:37,474 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:04:37,474 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1417727508] [2021-12-16 10:04:37,475 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1417727508] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:04:37,475 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:04:37,475 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:04:37,475 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [496766201] [2021-12-16 10:04:37,475 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:04:37,476 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:04:37,476 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:37,476 INFO L85 PathProgramCache]: Analyzing trace with hash -586893878, now seen corresponding path program 1 times [2021-12-16 10:04:37,476 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:37,476 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1005011816] [2021-12-16 10:04:37,476 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:37,477 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:37,482 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:04:37,482 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-16 10:04:37,486 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:04:37,488 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-16 10:04:37,603 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:04:37,603 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-16 10:04:37,604 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-16 10:04:37,604 INFO L87 Difference]: Start difference. First operand 6466 states and 8904 transitions. cyclomatic complexity: 2449 Second operand has 3 states, 3 states have (on average 17.666666666666668) internal successors, (53), 3 states have internal predecessors, (53), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:04:37,616 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:04:37,617 INFO L93 Difference]: Finished difference Result 4911 states and 6787 transitions. [2021-12-16 10:04:37,617 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-16 10:04:37,617 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4911 states and 6787 transitions. [2021-12-16 10:04:37,631 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 4839 [2021-12-16 10:04:37,639 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4911 states to 4911 states and 6787 transitions. [2021-12-16 10:04:37,640 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4911 [2021-12-16 10:04:37,642 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4911 [2021-12-16 10:04:37,642 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4911 states and 6787 transitions. [2021-12-16 10:04:37,646 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:04:37,646 INFO L681 BuchiCegarLoop]: Abstraction has 4911 states and 6787 transitions. [2021-12-16 10:04:37,648 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4911 states and 6787 transitions. [2021-12-16 10:04:37,686 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4911 to 4911. [2021-12-16 10:04:37,691 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4911 states, 4911 states have (on average 1.3819995927509672) internal successors, (6787), 4910 states have internal predecessors, (6787), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:04:37,699 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4911 states to 4911 states and 6787 transitions. [2021-12-16 10:04:37,699 INFO L704 BuchiCegarLoop]: Abstraction has 4911 states and 6787 transitions. [2021-12-16 10:04:37,699 INFO L587 BuchiCegarLoop]: Abstraction has 4911 states and 6787 transitions. [2021-12-16 10:04:37,699 INFO L425 BuchiCegarLoop]: ======== Iteration 15============ [2021-12-16 10:04:37,700 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4911 states and 6787 transitions. [2021-12-16 10:04:37,708 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 4839 [2021-12-16 10:04:37,708 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:04:37,708 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:04:37,709 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:37,709 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:37,709 INFO L791 eck$LassoCheckResult]: Stem: 72693#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 72639#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 72444#L653 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 72409#L297 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 72410#L304 assume 1 == ~m_i~0;~m_st~0 := 0; 72533#L304-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 72363#L309-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 72364#L314-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 72553#L319-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 72377#L441 assume !(0 == ~M_E~0); 72378#L441-2 assume !(0 == ~T1_E~0); 72527#L446-1 assume !(0 == ~T2_E~0); 72491#L451-1 assume !(0 == ~T3_E~0); 72492#L456-1 assume !(0 == ~E_M~0); 72644#L461-1 assume !(0 == ~E_1~0); 72645#L466-1 assume !(0 == ~E_2~0); 72662#L471-1 assume !(0 == ~E_3~0); 72417#L476-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 72418#L220 assume !(1 == ~m_pc~0); 72452#L220-2 is_master_triggered_~__retres1~0#1 := 0; 72453#L231 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 72506#L232 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 72448#L543 assume !(0 != activate_threads_~tmp~1#1); 72449#L543-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 72623#L239 assume !(1 == ~t1_pc~0); 72624#L239-2 is_transmit1_triggered_~__retres1~1#1 := 0; 72642#L250 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 72668#L251 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 72629#L551 assume !(0 != activate_threads_~tmp___0~0#1); 72630#L551-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 72631#L258 assume !(1 == ~t2_pc~0); 72632#L258-2 is_transmit2_triggered_~__retres1~2#1 := 0; 72481#L269 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 72335#L270 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 72336#L559 assume !(0 != activate_threads_~tmp___1~0#1); 72540#L559-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 72541#L277 assume !(1 == ~t3_pc~0); 72589#L277-2 is_transmit3_triggered_~__retres1~3#1 := 0; 72391#L288 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 72392#L289 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 72442#L567 assume !(0 != activate_threads_~tmp___2~0#1); 72443#L567-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 72488#L489 assume !(1 == ~M_E~0); 72643#L489-2 assume !(1 == ~T1_E~0); 72570#L494-1 assume !(1 == ~T2_E~0); 72431#L499-1 assume !(1 == ~T3_E~0); 72432#L504-1 assume !(1 == ~E_M~0); 72534#L509-1 assume !(1 == ~E_1~0); 72419#L514-1 assume !(1 == ~E_2~0); 72420#L519-1 assume !(1 == ~E_3~0); 72427#L524-1 assume { :end_inline_reset_delta_events } true; 72428#L690-2 assume !false; 74347#L691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 74342#L416 [2021-12-16 10:04:37,709 INFO L793 eck$LassoCheckResult]: Loop: 74342#L416 assume !false; 74340#L365 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 74338#L332 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 74335#L354 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 74333#L355 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 74317#L369 assume 0 != eval_~tmp~0#1; 74301#L369-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 74291#L377 assume !(0 != eval_~tmp_ndt_1~0#1); 74286#L374 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 74280#L391 assume !(0 != eval_~tmp_ndt_2~0#1); 74281#L388 assume !(0 == ~t2_st~0); 74279#L402 assume !(0 == ~t3_st~0); 74342#L416 [2021-12-16 10:04:37,709 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:37,709 INFO L85 PathProgramCache]: Analyzing trace with hash 1561976903, now seen corresponding path program 2 times [2021-12-16 10:04:37,709 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:37,709 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [341626228] [2021-12-16 10:04:37,710 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:37,710 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:37,714 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:04:37,714 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-16 10:04:37,717 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:04:37,722 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-16 10:04:37,722 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:37,722 INFO L85 PathProgramCache]: Analyzing trace with hash -586893878, now seen corresponding path program 2 times [2021-12-16 10:04:37,722 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:37,722 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [878858029] [2021-12-16 10:04:37,722 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:37,723 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:37,725 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:04:37,725 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-16 10:04:37,726 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:04:37,727 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-16 10:04:37,727 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:37,727 INFO L85 PathProgramCache]: Analyzing trace with hash 975330576, now seen corresponding path program 1 times [2021-12-16 10:04:37,727 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:37,727 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1569196429] [2021-12-16 10:04:37,728 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:37,728 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:37,732 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:04:37,760 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:04:37,760 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:04:37,760 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1569196429] [2021-12-16 10:04:37,760 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1569196429] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:04:37,760 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:04:37,760 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:04:37,761 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [344742018] [2021-12-16 10:04:37,761 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:04:37,835 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:04:37,835 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-16 10:04:37,835 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-16 10:04:37,835 INFO L87 Difference]: Start difference. First operand 4911 states and 6787 transitions. cyclomatic complexity: 1882 Second operand has 3 states, 3 states have (on average 21.666666666666668) internal successors, (65), 3 states have internal predecessors, (65), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:04:37,902 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:04:37,902 INFO L93 Difference]: Finished difference Result 8656 states and 11890 transitions. [2021-12-16 10:04:37,902 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-16 10:04:37,903 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8656 states and 11890 transitions. [2021-12-16 10:04:37,924 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 8576 [2021-12-16 10:04:37,939 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8656 states to 8656 states and 11890 transitions. [2021-12-16 10:04:37,939 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8656 [2021-12-16 10:04:37,943 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8656 [2021-12-16 10:04:37,944 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8656 states and 11890 transitions. [2021-12-16 10:04:37,950 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:04:37,950 INFO L681 BuchiCegarLoop]: Abstraction has 8656 states and 11890 transitions. [2021-12-16 10:04:37,953 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8656 states and 11890 transitions. [2021-12-16 10:04:38,007 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8656 to 8502. [2021-12-16 10:04:38,016 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8502 states, 8502 states have (on average 1.3754410726887791) internal successors, (11694), 8501 states have internal predecessors, (11694), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:04:38,028 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8502 states to 8502 states and 11694 transitions. [2021-12-16 10:04:38,029 INFO L704 BuchiCegarLoop]: Abstraction has 8502 states and 11694 transitions. [2021-12-16 10:04:38,029 INFO L587 BuchiCegarLoop]: Abstraction has 8502 states and 11694 transitions. [2021-12-16 10:04:38,029 INFO L425 BuchiCegarLoop]: ======== Iteration 16============ [2021-12-16 10:04:38,029 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 8502 states and 11694 transitions. [2021-12-16 10:04:38,044 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 8422 [2021-12-16 10:04:38,044 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:04:38,044 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:04:38,045 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:38,045 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:38,045 INFO L791 eck$LassoCheckResult]: Stem: 86274#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 86210#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 86017#L653 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 85983#L297 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 85984#L304 assume 1 == ~m_i~0;~m_st~0 := 0; 86105#L304-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 85941#L309-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 85942#L314-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 86126#L319-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 85953#L441 assume !(0 == ~M_E~0); 85954#L441-2 assume !(0 == ~T1_E~0); 86098#L446-1 assume !(0 == ~T2_E~0); 86061#L451-1 assume !(0 == ~T3_E~0); 86062#L456-1 assume !(0 == ~E_M~0); 86214#L461-1 assume !(0 == ~E_1~0); 86215#L466-1 assume !(0 == ~E_2~0); 86233#L471-1 assume !(0 == ~E_3~0); 85991#L476-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 85992#L220 assume !(1 == ~m_pc~0); 86025#L220-2 is_master_triggered_~__retres1~0#1 := 0; 86026#L231 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 86081#L232 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 86023#L543 assume !(0 != activate_threads_~tmp~1#1); 86024#L543-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 86194#L239 assume !(1 == ~t1_pc~0); 86195#L239-2 is_transmit1_triggered_~__retres1~1#1 := 0; 86212#L250 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 86244#L251 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 86198#L551 assume !(0 != activate_threads_~tmp___0~0#1); 86199#L551-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 86200#L258 assume !(1 == ~t2_pc~0); 86201#L258-2 is_transmit2_triggered_~__retres1~2#1 := 0; 86054#L269 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 85910#L270 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 85911#L559 assume !(0 != activate_threads_~tmp___1~0#1); 86113#L559-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 86114#L277 assume !(1 == ~t3_pc~0); 86165#L277-2 is_transmit3_triggered_~__retres1~3#1 := 0; 85965#L288 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 85966#L289 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 86015#L567 assume !(0 != activate_threads_~tmp___2~0#1); 86016#L567-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 86058#L489 assume !(1 == ~M_E~0); 86213#L489-2 assume !(1 == ~T1_E~0); 86144#L494-1 assume !(1 == ~T2_E~0); 86006#L499-1 assume !(1 == ~T3_E~0); 86007#L504-1 assume !(1 == ~E_M~0); 86106#L509-1 assume !(1 == ~E_1~0); 85993#L514-1 assume !(1 == ~E_2~0); 85994#L519-1 assume !(1 == ~E_3~0); 86000#L524-1 assume { :end_inline_reset_delta_events } true; 86001#L690-2 assume !false; 88870#L691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 88865#L416 [2021-12-16 10:04:38,045 INFO L793 eck$LassoCheckResult]: Loop: 88865#L416 assume !false; 88863#L365 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 88860#L332 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 88858#L354 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 88856#L355 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 88854#L369 assume 0 != eval_~tmp~0#1; 88851#L369-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 88847#L377 assume !(0 != eval_~tmp_ndt_1~0#1); 88845#L374 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 88842#L391 assume !(0 != eval_~tmp_ndt_2~0#1); 88843#L388 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 88522#L405 assume !(0 != eval_~tmp_ndt_3~0#1); 88523#L402 assume !(0 == ~t3_st~0); 88865#L416 [2021-12-16 10:04:38,046 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:38,046 INFO L85 PathProgramCache]: Analyzing trace with hash 1561976903, now seen corresponding path program 3 times [2021-12-16 10:04:38,046 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:38,046 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1337906182] [2021-12-16 10:04:38,046 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:38,046 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:38,053 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:04:38,053 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-16 10:04:38,055 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:04:38,073 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-16 10:04:38,074 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:38,074 INFO L85 PathProgramCache]: Analyzing trace with hash -1013970345, now seen corresponding path program 1 times [2021-12-16 10:04:38,074 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:38,074 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1989935868] [2021-12-16 10:04:38,074 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:38,075 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:38,077 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:04:38,077 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-16 10:04:38,078 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:04:38,079 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-16 10:04:38,079 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:38,079 INFO L85 PathProgramCache]: Analyzing trace with hash 170347473, now seen corresponding path program 1 times [2021-12-16 10:04:38,079 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:38,079 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1530901956] [2021-12-16 10:04:38,080 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:38,080 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:38,084 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:04:38,093 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:04:38,094 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:04:38,094 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1530901956] [2021-12-16 10:04:38,094 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1530901956] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:04:38,094 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:04:38,094 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-16 10:04:38,094 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2101937740] [2021-12-16 10:04:38,095 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:04:38,169 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:04:38,170 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-16 10:04:38,170 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-16 10:04:38,170 INFO L87 Difference]: Start difference. First operand 8502 states and 11694 transitions. cyclomatic complexity: 3198 Second operand has 3 states, 2 states have (on average 33.0) internal successors, (66), 3 states have internal predecessors, (66), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:04:38,261 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:04:38,262 INFO L93 Difference]: Finished difference Result 14174 states and 19399 transitions. [2021-12-16 10:04:38,262 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-16 10:04:38,262 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 14174 states and 19399 transitions. [2021-12-16 10:04:38,308 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 14068 [2021-12-16 10:04:38,338 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 14174 states to 14174 states and 19399 transitions. [2021-12-16 10:04:38,339 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 14174 [2021-12-16 10:04:38,347 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 14174 [2021-12-16 10:04:38,347 INFO L73 IsDeterministic]: Start isDeterministic. Operand 14174 states and 19399 transitions. [2021-12-16 10:04:38,355 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:04:38,355 INFO L681 BuchiCegarLoop]: Abstraction has 14174 states and 19399 transitions. [2021-12-16 10:04:38,361 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14174 states and 19399 transitions. [2021-12-16 10:04:38,458 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14174 to 13934. [2021-12-16 10:04:38,475 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 13934 states, 13934 states have (on average 1.3749820582747236) internal successors, (19159), 13933 states have internal predecessors, (19159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:04:38,498 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13934 states to 13934 states and 19159 transitions. [2021-12-16 10:04:38,498 INFO L704 BuchiCegarLoop]: Abstraction has 13934 states and 19159 transitions. [2021-12-16 10:04:38,498 INFO L587 BuchiCegarLoop]: Abstraction has 13934 states and 19159 transitions. [2021-12-16 10:04:38,498 INFO L425 BuchiCegarLoop]: ======== Iteration 17============ [2021-12-16 10:04:38,498 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 13934 states and 19159 transitions. [2021-12-16 10:04:38,570 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 13828 [2021-12-16 10:04:38,570 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:04:38,571 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:04:38,571 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:38,571 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:38,571 INFO L791 eck$LassoCheckResult]: Stem: 108963#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 108901#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 108702#L653 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16#1, start_simulation_#t~ret17#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 108667#L297 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 108668#L304 assume 1 == ~m_i~0;~m_st~0 := 0; 108797#L304-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 108626#L309-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 108627#L314-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 108817#L319-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 108638#L441 assume !(0 == ~M_E~0); 108639#L441-2 assume !(0 == ~T1_E~0); 108791#L446-1 assume !(0 == ~T2_E~0); 108753#L451-1 assume !(0 == ~T3_E~0); 108754#L456-1 assume !(0 == ~E_M~0); 108905#L461-1 assume !(0 == ~E_1~0); 108906#L466-1 assume !(0 == ~E_2~0); 108924#L471-1 assume !(0 == ~E_3~0); 108675#L476-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 108676#L220 assume !(1 == ~m_pc~0); 108710#L220-2 is_master_triggered_~__retres1~0#1 := 0; 108711#L231 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 108773#L232 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 108708#L543 assume !(0 != activate_threads_~tmp~1#1); 108709#L543-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 108884#L239 assume !(1 == ~t1_pc~0); 108885#L239-2 is_transmit1_triggered_~__retres1~1#1 := 0; 108903#L250 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 108934#L251 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 108890#L551 assume !(0 != activate_threads_~tmp___0~0#1); 108891#L551-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 108892#L258 assume !(1 == ~t2_pc~0); 108893#L258-2 is_transmit2_triggered_~__retres1~2#1 := 0; 108743#L269 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 108594#L270 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 108595#L559 assume !(0 != activate_threads_~tmp___1~0#1); 108805#L559-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 108806#L277 assume !(1 == ~t3_pc~0); 108858#L277-2 is_transmit3_triggered_~__retres1~3#1 := 0; 108651#L288 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 108652#L289 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 108700#L567 assume !(0 != activate_threads_~tmp___2~0#1); 108701#L567-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 108750#L489 assume !(1 == ~M_E~0); 108904#L489-2 assume !(1 == ~T1_E~0); 108836#L494-1 assume !(1 == ~T2_E~0); 108691#L499-1 assume !(1 == ~T3_E~0); 108692#L504-1 assume !(1 == ~E_M~0); 108798#L509-1 assume !(1 == ~E_1~0); 108678#L514-1 assume !(1 == ~E_2~0); 108679#L519-1 assume !(1 == ~E_3~0); 108685#L524-1 assume { :end_inline_reset_delta_events } true; 108686#L690-2 assume !false; 112652#L691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 112477#L416 [2021-12-16 10:04:38,571 INFO L793 eck$LassoCheckResult]: Loop: 112477#L416 assume !false; 112648#L365 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 112645#L332 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 112643#L354 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 112640#L355 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 112637#L369 assume 0 != eval_~tmp~0#1; 112634#L369-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 112490#L377 assume !(0 != eval_~tmp_ndt_1~0#1); 112487#L374 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 112484#L391 assume !(0 != eval_~tmp_ndt_2~0#1); 112482#L388 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 112480#L405 assume !(0 != eval_~tmp_ndt_3~0#1); 112478#L402 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 112463#L419 assume !(0 != eval_~tmp_ndt_4~0#1); 112477#L416 [2021-12-16 10:04:38,572 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:38,572 INFO L85 PathProgramCache]: Analyzing trace with hash 1561976903, now seen corresponding path program 4 times [2021-12-16 10:04:38,572 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:38,572 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [407223637] [2021-12-16 10:04:38,572 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:38,572 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:38,577 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:04:38,577 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-16 10:04:38,580 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:04:38,584 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-16 10:04:38,585 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:38,585 INFO L85 PathProgramCache]: Analyzing trace with hash -1368312829, now seen corresponding path program 1 times [2021-12-16 10:04:38,585 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:38,585 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1540654008] [2021-12-16 10:04:38,585 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:38,585 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:38,587 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:04:38,587 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-16 10:04:38,589 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:04:38,589 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-16 10:04:38,590 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:38,590 INFO L85 PathProgramCache]: Analyzing trace with hash 985801161, now seen corresponding path program 1 times [2021-12-16 10:04:38,590 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:38,590 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [260333669] [2021-12-16 10:04:38,590 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:38,590 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:38,595 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:04:38,595 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-16 10:04:38,598 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:04:38,604 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-16 10:04:39,393 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 16.12 10:04:39 BoogieIcfgContainer [2021-12-16 10:04:39,394 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2021-12-16 10:04:39,394 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2021-12-16 10:04:39,394 INFO L271 PluginConnector]: Initializing Witness Printer... [2021-12-16 10:04:39,395 INFO L275 PluginConnector]: Witness Printer initialized [2021-12-16 10:04:39,395 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 16.12 10:04:34" (3/4) ... [2021-12-16 10:04:39,397 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2021-12-16 10:04:39,423 INFO L141 WitnessManager]: Wrote witness to /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/witness.graphml [2021-12-16 10:04:39,423 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2021-12-16 10:04:39,424 INFO L158 Benchmark]: Toolchain (without parser) took 6017.43ms. Allocated memory was 111.1MB in the beginning and 637.5MB in the end (delta: 526.4MB). Free memory was 77.2MB in the beginning and 413.7MB in the end (delta: -336.5MB). Peak memory consumption was 190.4MB. Max. memory is 16.1GB. [2021-12-16 10:04:39,424 INFO L158 Benchmark]: CDTParser took 0.14ms. Allocated memory is still 79.7MB. Free memory was 50.7MB in the beginning and 50.7MB in the end (delta: 18.4kB). There was no memory consumed. Max. memory is 16.1GB. [2021-12-16 10:04:39,424 INFO L158 Benchmark]: CACSL2BoogieTranslator took 316.64ms. Allocated memory is still 111.1MB. Free memory was 76.8MB in the beginning and 84.1MB in the end (delta: -7.2MB). Peak memory consumption was 10.5MB. Max. memory is 16.1GB. [2021-12-16 10:04:39,425 INFO L158 Benchmark]: Boogie Procedure Inliner took 60.64ms. Allocated memory is still 111.1MB. Free memory was 84.1MB in the beginning and 80.7MB in the end (delta: 3.4MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2021-12-16 10:04:39,425 INFO L158 Benchmark]: Boogie Preprocessor took 43.93ms. Allocated memory is still 111.1MB. Free memory was 80.7MB in the beginning and 77.2MB in the end (delta: 3.5MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2021-12-16 10:04:39,425 INFO L158 Benchmark]: RCFGBuilder took 562.55ms. Allocated memory is still 111.1MB. Free memory was 77.2MB in the beginning and 47.1MB in the end (delta: 30.1MB). Peak memory consumption was 31.5MB. Max. memory is 16.1GB. [2021-12-16 10:04:39,425 INFO L158 Benchmark]: BuchiAutomizer took 5000.02ms. Allocated memory was 111.1MB in the beginning and 637.5MB in the end (delta: 526.4MB). Free memory was 46.4MB in the beginning and 417.8MB in the end (delta: -371.4MB). Peak memory consumption was 157.3MB. Max. memory is 16.1GB. [2021-12-16 10:04:39,426 INFO L158 Benchmark]: Witness Printer took 29.18ms. Allocated memory is still 637.5MB. Free memory was 417.8MB in the beginning and 413.7MB in the end (delta: 4.1MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2021-12-16 10:04:39,427 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.14ms. Allocated memory is still 79.7MB. Free memory was 50.7MB in the beginning and 50.7MB in the end (delta: 18.4kB). There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 316.64ms. Allocated memory is still 111.1MB. Free memory was 76.8MB in the beginning and 84.1MB in the end (delta: -7.2MB). Peak memory consumption was 10.5MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 60.64ms. Allocated memory is still 111.1MB. Free memory was 84.1MB in the beginning and 80.7MB in the end (delta: 3.4MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * Boogie Preprocessor took 43.93ms. Allocated memory is still 111.1MB. Free memory was 80.7MB in the beginning and 77.2MB in the end (delta: 3.5MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * RCFGBuilder took 562.55ms. Allocated memory is still 111.1MB. Free memory was 77.2MB in the beginning and 47.1MB in the end (delta: 30.1MB). Peak memory consumption was 31.5MB. Max. memory is 16.1GB. * BuchiAutomizer took 5000.02ms. Allocated memory was 111.1MB in the beginning and 637.5MB in the end (delta: 526.4MB). Free memory was 46.4MB in the beginning and 417.8MB in the end (delta: -371.4MB). Peak memory consumption was 157.3MB. Max. memory is 16.1GB. * Witness Printer took 29.18ms. Allocated memory is still 637.5MB. Free memory was 417.8MB in the beginning and 413.7MB in the end (delta: 4.1MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 16 terminating modules (16 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.16 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 13934 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 4.9s and 17 iterations. TraceHistogramMax:1. Analysis of lassos took 2.3s. Construction of modules took 0.3s. Büchi inclusion checks took 0.5s. Highest rank in rank-based complementation 0. Minimization of det autom 16. Minimization of nondet autom 0. Automata minimization 0.7s AutomataMinimizationTime, 16 MinimizatonAttempts, 12477 StatesRemovedByMinimization, 11 NontrivialMinimizations. Non-live state removal took 0.5s Buchi closure took 0.0s. Biggest automaton had 13934 states and ocurred in iteration 16. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 10629 SdHoareTripleChecker+Valid, 0.4s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 10629 mSDsluCounter, 17608 SdHoareTripleChecker+Invalid, 0.3s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 9216 mSDsCounter, 169 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 395 IncrementalHoareTripleChecker+Invalid, 564 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 169 mSolverCounterUnsat, 8392 mSDtfsCounter, 395 mSolverCounterSat, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI4 SFLT0 conc3 concLT0 SILN1 SILU0 SILI8 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - FixpointNonTerminationResult [Line: 364]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite execution State at position 0 is {NULL=1} State at position 1 is {tmp_ndt_3=0, NULL=0, t3_st=0, token=0, NULL=1, tmp=0, __retres1=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@305ac1db=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@540c75d5=0, t2_st=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@cb4b5e9=0, tmp_ndt_2=0, E_3=2, E_1=2, tmp_ndt_1=0, tmp=1, \result=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@7fc82029=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@7f064017=0, m_st=0, NULL=0, t3_pc=0, __retres1=0, tmp___0=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@5a54762c=0, tmp___2=0, m_pc=0, \result=0, \result=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@36f650e3=0, \result=0, \result=0, tmp___1=0, T2_E=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@50724148=0, tmp=0, t1_pc=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@485b91b8=0, E_2=2, tmp___0=0, T1_E=2, __retres1=0, M_E=2, __retres1=1, t2_i=1, \result=0, t3_i=1, m_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@43f2407f=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@872902c=0, t1_st=0, __retres1=0, local=0, t2_pc=0, __retres1=0, tmp_ndt_4=0, E_M=2, kernel_st=1, T3_E=2, t1_i=1} - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 364]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L24] int m_pc = 0; [L25] int t1_pc = 0; [L26] int t2_pc = 0; [L27] int t3_pc = 0; [L28] int m_st ; [L29] int t1_st ; [L30] int t2_st ; [L31] int t3_st ; [L32] int m_i ; [L33] int t1_i ; [L34] int t2_i ; [L35] int t3_i ; [L36] int M_E = 2; [L37] int T1_E = 2; [L38] int T2_E = 2; [L39] int T3_E = 2; [L40] int E_M = 2; [L41] int E_1 = 2; [L42] int E_2 = 2; [L43] int E_3 = 2; [L49] int token ; [L51] int local ; [L735] int __retres1 ; [L739] CALL init_model() [L648] m_i = 1 [L649] t1_i = 1 [L650] t2_i = 1 [L651] t3_i = 1 [L739] RET init_model() [L740] CALL start_simulation() [L676] int kernel_st ; [L677] int tmp ; [L678] int tmp___0 ; [L682] kernel_st = 0 [L683] FCALL update_channels() [L684] CALL init_threads() [L304] COND TRUE m_i == 1 [L305] m_st = 0 [L309] COND TRUE t1_i == 1 [L310] t1_st = 0 [L314] COND TRUE t2_i == 1 [L315] t2_st = 0 [L319] COND TRUE t3_i == 1 [L320] t3_st = 0 [L684] RET init_threads() [L685] CALL fire_delta_events() [L441] COND FALSE !(M_E == 0) [L446] COND FALSE !(T1_E == 0) [L451] COND FALSE !(T2_E == 0) [L456] COND FALSE !(T3_E == 0) [L461] COND FALSE !(E_M == 0) [L466] COND FALSE !(E_1 == 0) [L471] COND FALSE !(E_2 == 0) [L476] COND FALSE !(E_3 == 0) [L685] RET fire_delta_events() [L686] CALL activate_threads() [L534] int tmp ; [L535] int tmp___0 ; [L536] int tmp___1 ; [L537] int tmp___2 ; [L541] CALL, EXPR is_master_triggered() [L217] int __retres1 ; [L220] COND FALSE !(m_pc == 1) [L230] __retres1 = 0 [L232] return (__retres1); [L541] RET, EXPR is_master_triggered() [L541] tmp = is_master_triggered() [L543] COND FALSE !(\read(tmp)) [L549] CALL, EXPR is_transmit1_triggered() [L236] int __retres1 ; [L239] COND FALSE !(t1_pc == 1) [L249] __retres1 = 0 [L251] return (__retres1); [L549] RET, EXPR is_transmit1_triggered() [L549] tmp___0 = is_transmit1_triggered() [L551] COND FALSE !(\read(tmp___0)) [L557] CALL, EXPR is_transmit2_triggered() [L255] int __retres1 ; [L258] COND FALSE !(t2_pc == 1) [L268] __retres1 = 0 [L270] return (__retres1); [L557] RET, EXPR is_transmit2_triggered() [L557] tmp___1 = is_transmit2_triggered() [L559] COND FALSE !(\read(tmp___1)) [L565] CALL, EXPR is_transmit3_triggered() [L274] int __retres1 ; [L277] COND FALSE !(t3_pc == 1) [L287] __retres1 = 0 [L289] return (__retres1); [L565] RET, EXPR is_transmit3_triggered() [L565] tmp___2 = is_transmit3_triggered() [L567] COND FALSE !(\read(tmp___2)) [L686] RET activate_threads() [L687] CALL reset_delta_events() [L489] COND FALSE !(M_E == 1) [L494] COND FALSE !(T1_E == 1) [L499] COND FALSE !(T2_E == 1) [L504] COND FALSE !(T3_E == 1) [L509] COND FALSE !(E_M == 1) [L514] COND FALSE !(E_1 == 1) [L519] COND FALSE !(E_2 == 1) [L524] COND FALSE !(E_3 == 1) [L687] RET reset_delta_events() [L690] COND TRUE 1 [L693] kernel_st = 1 [L694] CALL eval() [L360] int tmp ; Loop: [L364] COND TRUE 1 [L367] CALL, EXPR exists_runnable_thread() [L329] int __retres1 ; [L332] COND TRUE m_st == 0 [L333] __retres1 = 1 [L355] return (__retres1); [L367] RET, EXPR exists_runnable_thread() [L367] tmp = exists_runnable_thread() [L369] COND TRUE \read(tmp) [L374] COND TRUE m_st == 0 [L375] int tmp_ndt_1; [L376] tmp_ndt_1 = __VERIFIER_nondet_int() [L377] COND FALSE !(\read(tmp_ndt_1)) [L388] COND TRUE t1_st == 0 [L389] int tmp_ndt_2; [L390] tmp_ndt_2 = __VERIFIER_nondet_int() [L391] COND FALSE !(\read(tmp_ndt_2)) [L402] COND TRUE t2_st == 0 [L403] int tmp_ndt_3; [L404] tmp_ndt_3 = __VERIFIER_nondet_int() [L405] COND FALSE !(\read(tmp_ndt_3)) [L416] COND TRUE t3_st == 0 [L417] int tmp_ndt_4; [L418] tmp_ndt_4 = __VERIFIER_nondet_int() [L419] COND FALSE !(\read(tmp_ndt_4)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2021-12-16 10:04:39,465 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)