./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/token_ring.04.cil-1.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version c3fed411 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/token_ring.04.cil-1.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash d4710f8f3a918a0191222414f5c33a367ff98c09c2e8598fa3213223c4c35dba --- Real Ultimate output --- This is Ultimate 0.2.2-tmp.no-commuhash-c3fed41 [2021-12-16 10:04:33,218 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-12-16 10:04:33,220 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-12-16 10:04:33,247 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-12-16 10:04:33,249 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-12-16 10:04:33,256 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-12-16 10:04:33,257 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-12-16 10:04:33,258 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-12-16 10:04:33,260 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-12-16 10:04:33,260 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-12-16 10:04:33,261 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-12-16 10:04:33,264 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-12-16 10:04:33,265 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-12-16 10:04:33,265 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-12-16 10:04:33,266 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-12-16 10:04:33,267 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-12-16 10:04:33,269 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-12-16 10:04:33,272 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-12-16 10:04:33,273 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-12-16 10:04:33,274 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-12-16 10:04:33,281 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-12-16 10:04:33,283 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-12-16 10:04:33,284 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-12-16 10:04:33,284 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-12-16 10:04:33,286 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-12-16 10:04:33,286 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-12-16 10:04:33,287 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-12-16 10:04:33,287 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-12-16 10:04:33,288 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-12-16 10:04:33,288 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-12-16 10:04:33,289 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-12-16 10:04:33,289 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-12-16 10:04:33,290 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-12-16 10:04:33,301 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-12-16 10:04:33,302 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-12-16 10:04:33,302 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-12-16 10:04:33,302 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-12-16 10:04:33,303 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-12-16 10:04:33,303 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-12-16 10:04:33,304 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-12-16 10:04:33,304 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-12-16 10:04:33,305 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2021-12-16 10:04:33,345 INFO L113 SettingsManager]: Loading preferences was successful [2021-12-16 10:04:33,346 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-12-16 10:04:33,346 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2021-12-16 10:04:33,346 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2021-12-16 10:04:33,347 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-12-16 10:04:33,348 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-12-16 10:04:33,348 INFO L138 SettingsManager]: * Use SBE=true [2021-12-16 10:04:33,348 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2021-12-16 10:04:33,348 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2021-12-16 10:04:33,348 INFO L138 SettingsManager]: * Use old map elimination=false [2021-12-16 10:04:33,349 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2021-12-16 10:04:33,349 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2021-12-16 10:04:33,349 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2021-12-16 10:04:33,349 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-12-16 10:04:33,350 INFO L138 SettingsManager]: * sizeof long=4 [2021-12-16 10:04:33,350 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2021-12-16 10:04:33,350 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-12-16 10:04:33,350 INFO L138 SettingsManager]: * sizeof POINTER=4 [2021-12-16 10:04:33,350 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-12-16 10:04:33,350 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2021-12-16 10:04:33,350 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2021-12-16 10:04:33,351 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2021-12-16 10:04:33,351 INFO L138 SettingsManager]: * sizeof long double=12 [2021-12-16 10:04:33,351 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-12-16 10:04:33,352 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2021-12-16 10:04:33,352 INFO L138 SettingsManager]: * Use constant arrays=true [2021-12-16 10:04:33,352 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2021-12-16 10:04:33,352 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-12-16 10:04:33,352 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-12-16 10:04:33,353 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-12-16 10:04:33,353 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-12-16 10:04:33,353 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2021-12-16 10:04:33,354 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2021-12-16 10:04:33,354 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> d4710f8f3a918a0191222414f5c33a367ff98c09c2e8598fa3213223c4c35dba [2021-12-16 10:04:33,570 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-12-16 10:04:33,595 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-12-16 10:04:33,597 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-12-16 10:04:33,597 INFO L271 PluginConnector]: Initializing CDTParser... [2021-12-16 10:04:33,598 INFO L275 PluginConnector]: CDTParser initialized [2021-12-16 10:04:33,599 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/token_ring.04.cil-1.c [2021-12-16 10:04:33,644 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/4431d7898/9e49d2444c6f42b5bd08dfd73a823153/FLAG049e5922a [2021-12-16 10:04:34,037 INFO L306 CDTParser]: Found 1 translation units. [2021-12-16 10:04:34,038 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.04.cil-1.c [2021-12-16 10:04:34,045 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/4431d7898/9e49d2444c6f42b5bd08dfd73a823153/FLAG049e5922a [2021-12-16 10:04:34,055 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/4431d7898/9e49d2444c6f42b5bd08dfd73a823153 [2021-12-16 10:04:34,057 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-12-16 10:04:34,058 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-12-16 10:04:34,066 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-12-16 10:04:34,066 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-12-16 10:04:34,069 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-12-16 10:04:34,070 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 16.12 10:04:34" (1/1) ... [2021-12-16 10:04:34,070 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@3e4d09f2 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:04:34, skipping insertion in model container [2021-12-16 10:04:34,071 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 16.12 10:04:34" (1/1) ... [2021-12-16 10:04:34,075 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-12-16 10:04:34,114 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-12-16 10:04:34,221 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.04.cil-1.c[671,684] [2021-12-16 10:04:34,262 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-16 10:04:34,269 INFO L203 MainTranslator]: Completed pre-run [2021-12-16 10:04:34,276 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.04.cil-1.c[671,684] [2021-12-16 10:04:34,295 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-16 10:04:34,306 INFO L208 MainTranslator]: Completed translation [2021-12-16 10:04:34,306 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:04:34 WrapperNode [2021-12-16 10:04:34,307 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-12-16 10:04:34,307 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-12-16 10:04:34,307 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-12-16 10:04:34,308 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-12-16 10:04:34,312 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:04:34" (1/1) ... [2021-12-16 10:04:34,326 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:04:34" (1/1) ... [2021-12-16 10:04:34,373 INFO L137 Inliner]: procedures = 36, calls = 43, calls flagged for inlining = 38, calls inlined = 77, statements flattened = 1062 [2021-12-16 10:04:34,374 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-12-16 10:04:34,375 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-12-16 10:04:34,376 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-12-16 10:04:34,376 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-12-16 10:04:34,381 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:04:34" (1/1) ... [2021-12-16 10:04:34,381 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:04:34" (1/1) ... [2021-12-16 10:04:34,384 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:04:34" (1/1) ... [2021-12-16 10:04:34,384 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:04:34" (1/1) ... [2021-12-16 10:04:34,397 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:04:34" (1/1) ... [2021-12-16 10:04:34,405 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:04:34" (1/1) ... [2021-12-16 10:04:34,407 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:04:34" (1/1) ... [2021-12-16 10:04:34,412 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-12-16 10:04:34,413 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-12-16 10:04:34,413 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-12-16 10:04:34,413 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-12-16 10:04:34,414 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:04:34" (1/1) ... [2021-12-16 10:04:34,429 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-16 10:04:34,439 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-16 10:04:34,448 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-16 10:04:34,453 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2021-12-16 10:04:34,476 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2021-12-16 10:04:34,476 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2021-12-16 10:04:34,477 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-12-16 10:04:34,477 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-12-16 10:04:34,539 INFO L236 CfgBuilder]: Building ICFG [2021-12-16 10:04:34,540 INFO L262 CfgBuilder]: Building CFG for each procedure with an implementation [2021-12-16 10:04:35,209 INFO L277 CfgBuilder]: Performing block encoding [2021-12-16 10:04:35,221 INFO L296 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-12-16 10:04:35,221 INFO L301 CfgBuilder]: Removed 7 assume(true) statements. [2021-12-16 10:04:35,223 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 16.12 10:04:35 BoogieIcfgContainer [2021-12-16 10:04:35,223 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-12-16 10:04:35,224 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2021-12-16 10:04:35,224 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2021-12-16 10:04:35,227 INFO L275 PluginConnector]: BuchiAutomizer initialized [2021-12-16 10:04:35,227 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-16 10:04:35,227 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 16.12 10:04:34" (1/3) ... [2021-12-16 10:04:35,228 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@4549497f and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 16.12 10:04:35, skipping insertion in model container [2021-12-16 10:04:35,229 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-16 10:04:35,229 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:04:34" (2/3) ... [2021-12-16 10:04:35,229 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@4549497f and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 16.12 10:04:35, skipping insertion in model container [2021-12-16 10:04:35,229 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-16 10:04:35,229 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 16.12 10:04:35" (3/3) ... [2021-12-16 10:04:35,230 INFO L388 chiAutomizerObserver]: Analyzing ICFG token_ring.04.cil-1.c [2021-12-16 10:04:35,259 INFO L359 BuchiCegarLoop]: Interprodecural is true [2021-12-16 10:04:35,259 INFO L360 BuchiCegarLoop]: Hoare is false [2021-12-16 10:04:35,259 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2021-12-16 10:04:35,260 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2021-12-16 10:04:35,260 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2021-12-16 10:04:35,260 INFO L364 BuchiCegarLoop]: Difference is false [2021-12-16 10:04:35,260 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2021-12-16 10:04:35,260 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2021-12-16 10:04:35,278 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 431 states, 430 states have (on average 1.5325581395348837) internal successors, (659), 430 states have internal predecessors, (659), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:04:35,310 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 360 [2021-12-16 10:04:35,310 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:04:35,310 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:04:35,318 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:35,318 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:35,319 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2021-12-16 10:04:35,319 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 431 states, 430 states have (on average 1.5325581395348837) internal successors, (659), 430 states have internal predecessors, (659), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:04:35,327 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 360 [2021-12-16 10:04:35,327 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:04:35,327 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:04:35,329 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:35,330 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:35,335 INFO L791 eck$LassoCheckResult]: Stem: 425#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 363#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 219#L766true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 45#L346true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 76#L353true assume !(1 == ~m_i~0);~m_st~0 := 2; 298#L353-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 368#L358-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 48#L363-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 411#L368-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 123#L373-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 65#L514true assume !(0 == ~M_E~0); 382#L514-2true assume 0 == ~T1_E~0;~T1_E~0 := 1; 327#L519-1true assume !(0 == ~T2_E~0); 40#L524-1true assume !(0 == ~T3_E~0); 106#L529-1true assume !(0 == ~T4_E~0); 330#L534-1true assume !(0 == ~E_M~0); 267#L539-1true assume !(0 == ~E_1~0); 296#L544-1true assume !(0 == ~E_2~0); 297#L549-1true assume !(0 == ~E_3~0); 335#L554-1true assume 0 == ~E_4~0;~E_4~0 := 1; 38#L559-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 176#L250true assume 1 == ~m_pc~0; 396#L251true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 328#L261true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 149#L262true activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 300#L637true assume !(0 != activate_threads_~tmp~1#1); 41#L637-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 56#L269true assume !(1 == ~t1_pc~0); 103#L269-2true is_transmit1_triggered_~__retres1~1#1 := 0; 181#L280true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 120#L281true activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 329#L645true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 147#L645-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 238#L288true assume 1 == ~t2_pc~0; 359#L289true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 251#L299true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 157#L300true activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 260#L653true assume !(0 != activate_threads_~tmp___1~0#1); 313#L653-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 164#L307true assume !(1 == ~t3_pc~0); 226#L307-2true is_transmit3_triggered_~__retres1~3#1 := 0; 210#L318true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 432#L319true activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 308#L661true assume !(0 != activate_threads_~tmp___2~0#1); 130#L661-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 352#L326true assume 1 == ~t4_pc~0; 345#L327true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 162#L337true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 266#L338true activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 309#L669true assume !(0 != activate_threads_~tmp___3~0#1); 264#L669-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 304#L572true assume !(1 == ~M_E~0); 346#L572-2true assume !(1 == ~T1_E~0); 46#L577-1true assume !(1 == ~T2_E~0); 247#L582-1true assume !(1 == ~T3_E~0); 254#L587-1true assume !(1 == ~T4_E~0); 372#L592-1true assume !(1 == ~E_M~0); 14#L597-1true assume 1 == ~E_1~0;~E_1~0 := 2; 412#L602-1true assume !(1 == ~E_2~0); 141#L607-1true assume !(1 == ~E_3~0); 416#L612-1true assume !(1 == ~E_4~0); 105#L617-1true assume { :end_inline_reset_delta_events } true; 430#L803-2true [2021-12-16 10:04:35,336 INFO L793 eck$LassoCheckResult]: Loop: 430#L803-2true assume !false; 220#L804true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 201#L489true assume !true; 389#L504true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 232#L346-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 198#L514-3true assume 0 == ~M_E~0;~M_E~0 := 1; 153#L514-5true assume !(0 == ~T1_E~0); 318#L519-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 244#L524-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 86#L529-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 173#L534-3true assume 0 == ~E_M~0;~E_M~0 := 1; 9#L539-3true assume 0 == ~E_1~0;~E_1~0 := 1; 333#L544-3true assume 0 == ~E_2~0;~E_2~0 := 1; 400#L549-3true assume 0 == ~E_3~0;~E_3~0 := 1; 119#L554-3true assume !(0 == ~E_4~0); 194#L559-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 274#L250-18true assume 1 == ~m_pc~0; 231#L251-6true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 208#L261-6true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 54#L262-6true activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 272#L637-18true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 91#L637-20true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 32#L269-18true assume !(1 == ~t1_pc~0); 353#L269-20true is_transmit1_triggered_~__retres1~1#1 := 0; 72#L280-6true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 102#L281-6true activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 185#L645-18true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 290#L645-20true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 112#L288-18true assume !(1 == ~t2_pc~0); 397#L288-20true is_transmit2_triggered_~__retres1~2#1 := 0; 13#L299-6true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 62#L300-6true activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 171#L653-18true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 95#L653-20true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 316#L307-18true assume !(1 == ~t3_pc~0); 81#L307-20true is_transmit3_triggered_~__retres1~3#1 := 0; 122#L318-6true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 125#L319-6true activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 85#L661-18true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 348#L661-20true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 275#L326-18true assume !(1 == ~t4_pc~0); 361#L326-20true is_transmit4_triggered_~__retres1~4#1 := 0; 286#L337-6true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 246#L338-6true activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 7#L669-18true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 369#L669-20true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 420#L572-3true assume 1 == ~M_E~0;~M_E~0 := 2; 94#L572-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 111#L577-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 37#L582-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 371#L587-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 193#L592-3true assume 1 == ~E_M~0;~E_M~0 := 2; 252#L597-3true assume !(1 == ~E_1~0); 134#L602-3true assume 1 == ~E_2~0;~E_2~0 := 2; 324#L607-3true assume 1 == ~E_3~0;~E_3~0 := 2; 100#L612-3true assume 1 == ~E_4~0;~E_4~0 := 2; 196#L617-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 138#L386-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 128#L413-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 373#L414-1true start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 163#L822true assume !(0 == start_simulation_~tmp~3#1); 271#L822-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 395#L386-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 405#L413-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 165#L414-2true stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 24#L777true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 203#L784true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 213#L785true start_simulation_#t~ret18#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 317#L835true assume !(0 != start_simulation_~tmp___0~1#1); 430#L803-2true [2021-12-16 10:04:35,342 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:35,343 INFO L85 PathProgramCache]: Analyzing trace with hash 1553035642, now seen corresponding path program 1 times [2021-12-16 10:04:35,349 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:35,349 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1716325348] [2021-12-16 10:04:35,349 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:35,350 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:35,445 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:04:35,529 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:04:35,529 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:04:35,530 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1716325348] [2021-12-16 10:04:35,530 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1716325348] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:04:35,530 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:04:35,531 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:04:35,532 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [269693596] [2021-12-16 10:04:35,533 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:04:35,536 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:04:35,536 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:35,537 INFO L85 PathProgramCache]: Analyzing trace with hash -1756395876, now seen corresponding path program 1 times [2021-12-16 10:04:35,537 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:35,537 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1269148142] [2021-12-16 10:04:35,537 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:35,537 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:35,544 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:04:35,554 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:04:35,555 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:04:35,555 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1269148142] [2021-12-16 10:04:35,555 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1269148142] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:04:35,555 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:04:35,555 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-16 10:04:35,556 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [499476417] [2021-12-16 10:04:35,556 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:04:35,557 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:04:35,558 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:04:35,578 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-16 10:04:35,578 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-16 10:04:35,580 INFO L87 Difference]: Start difference. First operand has 431 states, 430 states have (on average 1.5325581395348837) internal successors, (659), 430 states have internal predecessors, (659), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:04:35,658 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:04:35,658 INFO L93 Difference]: Finished difference Result 430 states and 642 transitions. [2021-12-16 10:04:35,666 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-16 10:04:35,670 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 430 states and 642 transitions. [2021-12-16 10:04:35,682 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 358 [2021-12-16 10:04:35,688 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 430 states to 425 states and 637 transitions. [2021-12-16 10:04:35,688 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 425 [2021-12-16 10:04:35,689 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 425 [2021-12-16 10:04:35,690 INFO L73 IsDeterministic]: Start isDeterministic. Operand 425 states and 637 transitions. [2021-12-16 10:04:35,691 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:04:35,692 INFO L681 BuchiCegarLoop]: Abstraction has 425 states and 637 transitions. [2021-12-16 10:04:35,709 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 425 states and 637 transitions. [2021-12-16 10:04:35,734 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 425 to 425. [2021-12-16 10:04:35,736 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 425 states, 425 states have (on average 1.4988235294117647) internal successors, (637), 424 states have internal predecessors, (637), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:04:35,737 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 425 states to 425 states and 637 transitions. [2021-12-16 10:04:35,741 INFO L704 BuchiCegarLoop]: Abstraction has 425 states and 637 transitions. [2021-12-16 10:04:35,741 INFO L587 BuchiCegarLoop]: Abstraction has 425 states and 637 transitions. [2021-12-16 10:04:35,741 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2021-12-16 10:04:35,741 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 425 states and 637 transitions. [2021-12-16 10:04:35,743 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 358 [2021-12-16 10:04:35,744 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:04:35,744 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:04:35,747 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:35,748 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:35,748 INFO L791 eck$LassoCheckResult]: Stem: 1294#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 1287#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 1205#L766 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 958#L346 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 959#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 1014#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1260#L358-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 964#L363-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 965#L368-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1087#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 996#L514 assume !(0 == ~M_E~0); 997#L514-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1276#L519-1 assume !(0 == ~T2_E~0); 950#L524-1 assume !(0 == ~T3_E~0); 951#L529-1 assume !(0 == ~T4_E~0); 1066#L534-1 assume !(0 == ~E_M~0); 1242#L539-1 assume !(0 == ~E_1~0); 1243#L544-1 assume !(0 == ~E_2~0); 1258#L549-1 assume !(0 == ~E_3~0); 1259#L554-1 assume 0 == ~E_4~0;~E_4~0 := 1; 945#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 946#L250 assume 1 == ~m_pc~0; 1155#L251 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1264#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1120#L262 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1121#L637 assume !(0 != activate_threads_~tmp~1#1); 952#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 953#L269 assume !(1 == ~t1_pc~0); 890#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 889#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1084#L281 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1085#L645 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1117#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1118#L288 assume 1 == ~t2_pc~0; 1220#L289 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1114#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1130#L300 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1131#L653 assume !(0 != activate_threads_~tmp___1~0#1); 1237#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1144#L307 assume !(1 == ~t3_pc~0); 1078#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1079#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1195#L319 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1269#L661 assume !(0 != activate_threads_~tmp___2~0#1); 1093#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1094#L326 assume 1 == ~t4_pc~0; 1283#L327 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 904#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1140#L338 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1241#L669 assume !(0 != activate_threads_~tmp___3~0#1); 1238#L669-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1239#L572 assume !(1 == ~M_E~0); 1265#L572-2 assume !(1 == ~T1_E~0); 960#L577-1 assume !(1 == ~T2_E~0); 961#L582-1 assume !(1 == ~T3_E~0); 1226#L587-1 assume !(1 == ~T4_E~0); 1233#L592-1 assume !(1 == ~E_M~0); 895#L597-1 assume 1 == ~E_1~0;~E_1~0 := 2; 896#L602-1 assume !(1 == ~E_2~0); 1110#L607-1 assume !(1 == ~E_3~0); 1111#L612-1 assume !(1 == ~E_4~0); 1064#L617-1 assume { :end_inline_reset_delta_events } true; 1065#L803-2 [2021-12-16 10:04:35,749 INFO L793 eck$LassoCheckResult]: Loop: 1065#L803-2 assume !false; 1206#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 988#L489 assume !false; 1183#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 1146#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 1004#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 1060#L414 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1293#L428 assume !(0 != eval_~tmp~0#1); 1291#L504 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1216#L346-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1182#L514-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1124#L514-5 assume !(0 == ~T1_E~0); 1125#L519-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1224#L524-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1034#L529-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1035#L534-3 assume 0 == ~E_M~0;~E_M~0 := 1; 884#L539-3 assume 0 == ~E_1~0;~E_1~0 := 1; 885#L544-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1278#L549-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1082#L554-3 assume !(0 == ~E_4~0); 1083#L559-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1180#L250-18 assume 1 == ~m_pc~0; 1214#L251-6 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1192#L261-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 975#L262-6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 976#L637-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1044#L637-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 932#L269-18 assume !(1 == ~t1_pc~0); 933#L269-20 is_transmit1_triggered_~__retres1~1#1 := 0; 1006#L280-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1007#L281-6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1061#L645-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1168#L645-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1070#L288-18 assume 1 == ~t2_pc~0; 1056#L289-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 893#L299-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 894#L300-6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 991#L653-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1051#L653-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1052#L307-18 assume 1 == ~t3_pc~0; 1112#L308-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1024#L318-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1086#L319-6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1032#L661-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1033#L661-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1247#L326-18 assume 1 == ~t4_pc~0; 1248#L327-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1254#L337-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1225#L338-6 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 880#L669-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 881#L669-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1288#L572-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1049#L572-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1050#L577-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 943#L582-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 944#L587-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1178#L592-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1179#L597-3 assume !(1 == ~E_1~0); 1099#L602-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1100#L607-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1058#L612-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1059#L617-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 1105#L386-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 1074#L413-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 1091#L414-1 start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 1141#L822 assume !(0 == start_simulation_~tmp~3#1); 1143#L822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 1245#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 1187#L413-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 1145#L414-2 stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 916#L777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 917#L784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1185#L785 start_simulation_#t~ret18#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 1201#L835 assume !(0 != start_simulation_~tmp___0~1#1); 1065#L803-2 [2021-12-16 10:04:35,749 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:35,750 INFO L85 PathProgramCache]: Analyzing trace with hash 1119306556, now seen corresponding path program 1 times [2021-12-16 10:04:35,750 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:35,750 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1856200847] [2021-12-16 10:04:35,750 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:35,750 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:35,761 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:04:35,786 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:04:35,787 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:04:35,787 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1856200847] [2021-12-16 10:04:35,788 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1856200847] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:04:35,788 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:04:35,788 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:04:35,789 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [703242449] [2021-12-16 10:04:35,789 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:04:35,789 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:04:35,790 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:35,792 INFO L85 PathProgramCache]: Analyzing trace with hash -387617298, now seen corresponding path program 1 times [2021-12-16 10:04:35,792 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:35,792 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [159503522] [2021-12-16 10:04:35,792 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:35,793 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:35,823 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:04:35,859 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:04:35,861 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:04:35,861 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [159503522] [2021-12-16 10:04:35,861 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [159503522] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:04:35,862 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:04:35,862 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:04:35,862 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1117010808] [2021-12-16 10:04:35,862 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:04:35,863 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:04:35,863 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:04:35,864 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-16 10:04:35,865 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-16 10:04:35,866 INFO L87 Difference]: Start difference. First operand 425 states and 637 transitions. cyclomatic complexity: 213 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:04:35,916 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:04:35,923 INFO L93 Difference]: Finished difference Result 425 states and 636 transitions. [2021-12-16 10:04:35,924 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-16 10:04:35,925 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 425 states and 636 transitions. [2021-12-16 10:04:35,928 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 358 [2021-12-16 10:04:35,930 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 425 states to 425 states and 636 transitions. [2021-12-16 10:04:35,954 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 425 [2021-12-16 10:04:35,955 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 425 [2021-12-16 10:04:35,955 INFO L73 IsDeterministic]: Start isDeterministic. Operand 425 states and 636 transitions. [2021-12-16 10:04:35,956 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:04:35,956 INFO L681 BuchiCegarLoop]: Abstraction has 425 states and 636 transitions. [2021-12-16 10:04:35,957 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 425 states and 636 transitions. [2021-12-16 10:04:35,970 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 425 to 425. [2021-12-16 10:04:35,971 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 425 states, 425 states have (on average 1.4964705882352942) internal successors, (636), 424 states have internal predecessors, (636), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:04:35,972 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 425 states to 425 states and 636 transitions. [2021-12-16 10:04:35,972 INFO L704 BuchiCegarLoop]: Abstraction has 425 states and 636 transitions. [2021-12-16 10:04:35,972 INFO L587 BuchiCegarLoop]: Abstraction has 425 states and 636 transitions. [2021-12-16 10:04:35,972 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2021-12-16 10:04:35,972 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 425 states and 636 transitions. [2021-12-16 10:04:35,974 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 358 [2021-12-16 10:04:35,974 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:04:35,974 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:04:35,975 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:35,975 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:35,976 INFO L791 eck$LassoCheckResult]: Stem: 2151#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 2144#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 2062#L766 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1815#L346 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1816#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 1871#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2117#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1821#L363-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1822#L368-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1944#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1853#L514 assume !(0 == ~M_E~0); 1854#L514-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2133#L519-1 assume !(0 == ~T2_E~0); 1807#L524-1 assume !(0 == ~T3_E~0); 1808#L529-1 assume !(0 == ~T4_E~0); 1923#L534-1 assume !(0 == ~E_M~0); 2099#L539-1 assume !(0 == ~E_1~0); 2100#L544-1 assume !(0 == ~E_2~0); 2115#L549-1 assume !(0 == ~E_3~0); 2116#L554-1 assume 0 == ~E_4~0;~E_4~0 := 1; 1802#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1803#L250 assume 1 == ~m_pc~0; 2012#L251 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2121#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1977#L262 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1978#L637 assume !(0 != activate_threads_~tmp~1#1); 1809#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1810#L269 assume !(1 == ~t1_pc~0); 1747#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1746#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1941#L281 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1942#L645 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1974#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1975#L288 assume 1 == ~t2_pc~0; 2077#L289 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1971#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1987#L300 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1988#L653 assume !(0 != activate_threads_~tmp___1~0#1); 2094#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2001#L307 assume !(1 == ~t3_pc~0); 1935#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1936#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2052#L319 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2126#L661 assume !(0 != activate_threads_~tmp___2~0#1); 1950#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1951#L326 assume 1 == ~t4_pc~0; 2140#L327 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1761#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1997#L338 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2098#L669 assume !(0 != activate_threads_~tmp___3~0#1); 2095#L669-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2096#L572 assume !(1 == ~M_E~0); 2122#L572-2 assume !(1 == ~T1_E~0); 1817#L577-1 assume !(1 == ~T2_E~0); 1818#L582-1 assume !(1 == ~T3_E~0); 2083#L587-1 assume !(1 == ~T4_E~0); 2090#L592-1 assume !(1 == ~E_M~0); 1752#L597-1 assume 1 == ~E_1~0;~E_1~0 := 2; 1753#L602-1 assume !(1 == ~E_2~0); 1967#L607-1 assume !(1 == ~E_3~0); 1968#L612-1 assume !(1 == ~E_4~0); 1921#L617-1 assume { :end_inline_reset_delta_events } true; 1922#L803-2 [2021-12-16 10:04:35,976 INFO L793 eck$LassoCheckResult]: Loop: 1922#L803-2 assume !false; 2063#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1845#L489 assume !false; 2040#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 2003#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 1861#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 1917#L414 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 2150#L428 assume !(0 != eval_~tmp~0#1); 2148#L504 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2073#L346-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2039#L514-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1981#L514-5 assume !(0 == ~T1_E~0); 1982#L519-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2081#L524-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1891#L529-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1892#L534-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1741#L539-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1742#L544-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2135#L549-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1939#L554-3 assume !(0 == ~E_4~0); 1940#L559-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2037#L250-18 assume 1 == ~m_pc~0; 2071#L251-6 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2049#L261-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1832#L262-6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1833#L637-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1901#L637-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1789#L269-18 assume !(1 == ~t1_pc~0); 1790#L269-20 is_transmit1_triggered_~__retres1~1#1 := 0; 1863#L280-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1864#L281-6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1918#L645-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2025#L645-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1927#L288-18 assume 1 == ~t2_pc~0; 1913#L289-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1750#L299-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1751#L300-6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1848#L653-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1908#L653-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1909#L307-18 assume 1 == ~t3_pc~0; 1969#L308-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1881#L318-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1943#L319-6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1889#L661-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1890#L661-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2104#L326-18 assume 1 == ~t4_pc~0; 2105#L327-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2111#L337-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2082#L338-6 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1737#L669-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1738#L669-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2145#L572-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1906#L572-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1907#L577-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1800#L582-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1801#L587-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2035#L592-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2036#L597-3 assume !(1 == ~E_1~0); 1956#L602-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1957#L607-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1915#L612-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1916#L617-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 1962#L386-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 1931#L413-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 1948#L414-1 start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 1998#L822 assume !(0 == start_simulation_~tmp~3#1); 2000#L822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 2102#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 2044#L413-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 2002#L414-2 stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 1773#L777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1774#L784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2042#L785 start_simulation_#t~ret18#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 2058#L835 assume !(0 != start_simulation_~tmp___0~1#1); 1922#L803-2 [2021-12-16 10:04:35,976 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:35,977 INFO L85 PathProgramCache]: Analyzing trace with hash 1078631806, now seen corresponding path program 1 times [2021-12-16 10:04:35,977 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:35,977 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1266263687] [2021-12-16 10:04:35,977 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:35,977 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:35,989 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:04:36,021 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:04:36,021 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:04:36,022 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1266263687] [2021-12-16 10:04:36,022 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1266263687] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:04:36,022 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:04:36,022 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:04:36,022 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [278879163] [2021-12-16 10:04:36,023 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:04:36,023 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:04:36,023 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:36,024 INFO L85 PathProgramCache]: Analyzing trace with hash -387617298, now seen corresponding path program 2 times [2021-12-16 10:04:36,024 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:36,024 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [92132427] [2021-12-16 10:04:36,024 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:36,024 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:36,035 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:04:36,089 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:04:36,089 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:04:36,089 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [92132427] [2021-12-16 10:04:36,090 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [92132427] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:04:36,090 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:04:36,090 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:04:36,090 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [854132054] [2021-12-16 10:04:36,090 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:04:36,091 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:04:36,091 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:04:36,091 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-16 10:04:36,092 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-16 10:04:36,092 INFO L87 Difference]: Start difference. First operand 425 states and 636 transitions. cyclomatic complexity: 212 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:04:36,104 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:04:36,113 INFO L93 Difference]: Finished difference Result 425 states and 635 transitions. [2021-12-16 10:04:36,114 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-16 10:04:36,115 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 425 states and 635 transitions. [2021-12-16 10:04:36,118 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 358 [2021-12-16 10:04:36,120 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 425 states to 425 states and 635 transitions. [2021-12-16 10:04:36,124 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 425 [2021-12-16 10:04:36,124 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 425 [2021-12-16 10:04:36,124 INFO L73 IsDeterministic]: Start isDeterministic. Operand 425 states and 635 transitions. [2021-12-16 10:04:36,125 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:04:36,125 INFO L681 BuchiCegarLoop]: Abstraction has 425 states and 635 transitions. [2021-12-16 10:04:36,126 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 425 states and 635 transitions. [2021-12-16 10:04:36,145 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 425 to 425. [2021-12-16 10:04:36,146 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 425 states, 425 states have (on average 1.4941176470588236) internal successors, (635), 424 states have internal predecessors, (635), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:04:36,147 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 425 states to 425 states and 635 transitions. [2021-12-16 10:04:36,147 INFO L704 BuchiCegarLoop]: Abstraction has 425 states and 635 transitions. [2021-12-16 10:04:36,147 INFO L587 BuchiCegarLoop]: Abstraction has 425 states and 635 transitions. [2021-12-16 10:04:36,147 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2021-12-16 10:04:36,148 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 425 states and 635 transitions. [2021-12-16 10:04:36,149 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 358 [2021-12-16 10:04:36,150 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:04:36,150 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:04:36,151 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:36,151 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:36,151 INFO L791 eck$LassoCheckResult]: Stem: 3008#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 3001#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 2919#L766 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2672#L346 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2673#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 2728#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2974#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2678#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2679#L368-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2801#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2710#L514 assume !(0 == ~M_E~0); 2711#L514-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2990#L519-1 assume !(0 == ~T2_E~0); 2664#L524-1 assume !(0 == ~T3_E~0); 2665#L529-1 assume !(0 == ~T4_E~0); 2780#L534-1 assume !(0 == ~E_M~0); 2956#L539-1 assume !(0 == ~E_1~0); 2957#L544-1 assume !(0 == ~E_2~0); 2972#L549-1 assume !(0 == ~E_3~0); 2973#L554-1 assume 0 == ~E_4~0;~E_4~0 := 1; 2659#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2660#L250 assume 1 == ~m_pc~0; 2869#L251 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2978#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2834#L262 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 2835#L637 assume !(0 != activate_threads_~tmp~1#1); 2666#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2667#L269 assume !(1 == ~t1_pc~0); 2604#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2603#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2798#L281 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2799#L645 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2831#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2832#L288 assume 1 == ~t2_pc~0; 2934#L289 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2828#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2844#L300 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2845#L653 assume !(0 != activate_threads_~tmp___1~0#1); 2951#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2858#L307 assume !(1 == ~t3_pc~0); 2792#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2793#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2909#L319 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2983#L661 assume !(0 != activate_threads_~tmp___2~0#1); 2807#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2808#L326 assume 1 == ~t4_pc~0; 2997#L327 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2618#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2854#L338 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2955#L669 assume !(0 != activate_threads_~tmp___3~0#1); 2952#L669-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2953#L572 assume !(1 == ~M_E~0); 2979#L572-2 assume !(1 == ~T1_E~0); 2674#L577-1 assume !(1 == ~T2_E~0); 2675#L582-1 assume !(1 == ~T3_E~0); 2940#L587-1 assume !(1 == ~T4_E~0); 2947#L592-1 assume !(1 == ~E_M~0); 2609#L597-1 assume 1 == ~E_1~0;~E_1~0 := 2; 2610#L602-1 assume !(1 == ~E_2~0); 2824#L607-1 assume !(1 == ~E_3~0); 2825#L612-1 assume !(1 == ~E_4~0); 2778#L617-1 assume { :end_inline_reset_delta_events } true; 2779#L803-2 [2021-12-16 10:04:36,152 INFO L793 eck$LassoCheckResult]: Loop: 2779#L803-2 assume !false; 2920#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2702#L489 assume !false; 2897#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 2860#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 2718#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 2774#L414 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 3007#L428 assume !(0 != eval_~tmp~0#1); 3005#L504 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2930#L346-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2896#L514-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2838#L514-5 assume !(0 == ~T1_E~0); 2839#L519-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2938#L524-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2748#L529-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2749#L534-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2598#L539-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2599#L544-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2992#L549-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2796#L554-3 assume !(0 == ~E_4~0); 2797#L559-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2894#L250-18 assume 1 == ~m_pc~0; 2928#L251-6 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2906#L261-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2689#L262-6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 2690#L637-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2758#L637-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2646#L269-18 assume !(1 == ~t1_pc~0); 2647#L269-20 is_transmit1_triggered_~__retres1~1#1 := 0; 2720#L280-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2721#L281-6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2775#L645-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2882#L645-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2784#L288-18 assume 1 == ~t2_pc~0; 2770#L289-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2607#L299-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2608#L300-6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2705#L653-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2765#L653-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2766#L307-18 assume !(1 == ~t3_pc~0); 2737#L307-20 is_transmit3_triggered_~__retres1~3#1 := 0; 2738#L318-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2800#L319-6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2746#L661-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2747#L661-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2961#L326-18 assume 1 == ~t4_pc~0; 2962#L327-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2968#L337-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2939#L338-6 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2594#L669-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2595#L669-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3002#L572-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2763#L572-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2764#L577-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2657#L582-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2658#L587-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2892#L592-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2893#L597-3 assume !(1 == ~E_1~0); 2813#L602-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2814#L607-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2772#L612-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2773#L617-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 2819#L386-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 2788#L413-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 2805#L414-1 start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 2855#L822 assume !(0 == start_simulation_~tmp~3#1); 2857#L822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 2959#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 2901#L413-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 2859#L414-2 stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 2630#L777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2631#L784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2899#L785 start_simulation_#t~ret18#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 2915#L835 assume !(0 != start_simulation_~tmp___0~1#1); 2779#L803-2 [2021-12-16 10:04:36,152 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:36,152 INFO L85 PathProgramCache]: Analyzing trace with hash -308153604, now seen corresponding path program 1 times [2021-12-16 10:04:36,153 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:36,153 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [301877856] [2021-12-16 10:04:36,153 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:36,153 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:36,165 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:04:36,194 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:04:36,194 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:04:36,194 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [301877856] [2021-12-16 10:04:36,195 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [301877856] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:04:36,195 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:04:36,195 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:04:36,195 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2095190486] [2021-12-16 10:04:36,195 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:04:36,195 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:04:36,195 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:36,196 INFO L85 PathProgramCache]: Analyzing trace with hash 663831791, now seen corresponding path program 1 times [2021-12-16 10:04:36,196 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:36,196 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1203955720] [2021-12-16 10:04:36,196 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:36,196 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:36,203 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:04:36,223 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:04:36,223 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:04:36,223 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1203955720] [2021-12-16 10:04:36,223 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1203955720] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:04:36,223 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:04:36,223 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:04:36,223 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1590591571] [2021-12-16 10:04:36,223 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:04:36,224 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:04:36,224 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:04:36,224 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-16 10:04:36,224 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-16 10:04:36,224 INFO L87 Difference]: Start difference. First operand 425 states and 635 transitions. cyclomatic complexity: 211 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:04:36,231 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:04:36,231 INFO L93 Difference]: Finished difference Result 425 states and 634 transitions. [2021-12-16 10:04:36,232 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-16 10:04:36,232 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 425 states and 634 transitions. [2021-12-16 10:04:36,234 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 358 [2021-12-16 10:04:36,236 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 425 states to 425 states and 634 transitions. [2021-12-16 10:04:36,236 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 425 [2021-12-16 10:04:36,236 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 425 [2021-12-16 10:04:36,236 INFO L73 IsDeterministic]: Start isDeterministic. Operand 425 states and 634 transitions. [2021-12-16 10:04:36,237 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:04:36,237 INFO L681 BuchiCegarLoop]: Abstraction has 425 states and 634 transitions. [2021-12-16 10:04:36,237 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 425 states and 634 transitions. [2021-12-16 10:04:36,240 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 425 to 425. [2021-12-16 10:04:36,241 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 425 states, 425 states have (on average 1.4917647058823529) internal successors, (634), 424 states have internal predecessors, (634), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:04:36,242 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 425 states to 425 states and 634 transitions. [2021-12-16 10:04:36,242 INFO L704 BuchiCegarLoop]: Abstraction has 425 states and 634 transitions. [2021-12-16 10:04:36,242 INFO L587 BuchiCegarLoop]: Abstraction has 425 states and 634 transitions. [2021-12-16 10:04:36,242 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2021-12-16 10:04:36,242 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 425 states and 634 transitions. [2021-12-16 10:04:36,244 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 358 [2021-12-16 10:04:36,244 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:04:36,244 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:04:36,244 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:36,244 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:36,245 INFO L791 eck$LassoCheckResult]: Stem: 3865#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 3858#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 3776#L766 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3529#L346 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3530#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 3585#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3832#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3535#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3536#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 3659#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3567#L514 assume !(0 == ~M_E~0); 3568#L514-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3847#L519-1 assume !(0 == ~T2_E~0); 3521#L524-1 assume !(0 == ~T3_E~0); 3522#L529-1 assume !(0 == ~T4_E~0); 3637#L534-1 assume !(0 == ~E_M~0); 3813#L539-1 assume !(0 == ~E_1~0); 3814#L544-1 assume !(0 == ~E_2~0); 3829#L549-1 assume !(0 == ~E_3~0); 3830#L554-1 assume 0 == ~E_4~0;~E_4~0 := 1; 3516#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3517#L250 assume 1 == ~m_pc~0; 3729#L251 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 3836#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3691#L262 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 3692#L637 assume !(0 != activate_threads_~tmp~1#1); 3523#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3524#L269 assume !(1 == ~t1_pc~0); 3461#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 3460#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3655#L281 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 3656#L645 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3688#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3689#L288 assume 1 == ~t2_pc~0; 3792#L289 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3685#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3701#L300 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3702#L653 assume !(0 != activate_threads_~tmp___1~0#1); 3808#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3716#L307 assume !(1 == ~t3_pc~0); 3649#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 3650#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3771#L319 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3840#L661 assume !(0 != activate_threads_~tmp___2~0#1); 3664#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3665#L326 assume 1 == ~t4_pc~0; 3854#L327 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3475#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3714#L338 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3812#L669 assume !(0 != activate_threads_~tmp___3~0#1); 3809#L669-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3810#L572 assume !(1 == ~M_E~0); 3835#L572-2 assume !(1 == ~T1_E~0); 3531#L577-1 assume !(1 == ~T2_E~0); 3532#L582-1 assume !(1 == ~T3_E~0); 3797#L587-1 assume !(1 == ~T4_E~0); 3804#L592-1 assume !(1 == ~E_M~0); 3466#L597-1 assume 1 == ~E_1~0;~E_1~0 := 2; 3467#L602-1 assume !(1 == ~E_2~0); 3681#L607-1 assume !(1 == ~E_3~0); 3682#L612-1 assume !(1 == ~E_4~0); 3635#L617-1 assume { :end_inline_reset_delta_events } true; 3636#L803-2 [2021-12-16 10:04:36,245 INFO L793 eck$LassoCheckResult]: Loop: 3636#L803-2 assume !false; 3777#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3559#L489 assume !false; 3754#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 3717#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 3575#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 3631#L414 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 3864#L428 assume !(0 != eval_~tmp~0#1); 3862#L504 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3787#L346-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3753#L514-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3695#L514-5 assume !(0 == ~T1_E~0); 3696#L519-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3795#L524-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3605#L529-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3606#L534-3 assume 0 == ~E_M~0;~E_M~0 := 1; 3455#L539-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3456#L544-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3849#L549-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3653#L554-3 assume !(0 == ~E_4~0); 3654#L559-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3751#L250-18 assume 1 == ~m_pc~0; 3785#L251-6 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 3763#L261-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3546#L262-6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 3547#L637-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3615#L637-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3503#L269-18 assume !(1 == ~t1_pc~0); 3504#L269-20 is_transmit1_triggered_~__retres1~1#1 := 0; 3577#L280-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3578#L281-6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 3632#L645-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3739#L645-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3641#L288-18 assume 1 == ~t2_pc~0; 3627#L289-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3464#L299-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3465#L300-6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3562#L653-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3622#L653-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3623#L307-18 assume 1 == ~t3_pc~0; 3683#L308-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3595#L318-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3657#L319-6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3603#L661-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3604#L661-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3818#L326-18 assume 1 == ~t4_pc~0; 3819#L327-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3825#L337-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3796#L338-6 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3451#L669-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3452#L669-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3859#L572-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3620#L572-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3621#L577-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3514#L582-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3515#L587-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3749#L592-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3750#L597-3 assume !(1 == ~E_1~0); 3670#L602-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3671#L607-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3629#L612-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3630#L617-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 3676#L386-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 3645#L413-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 3662#L414-1 start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 3711#L822 assume !(0 == start_simulation_~tmp~3#1); 3713#L822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 3816#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 3758#L413-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 3715#L414-2 stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 3487#L777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3488#L784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3756#L785 start_simulation_#t~ret18#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 3772#L835 assume !(0 != start_simulation_~tmp___0~1#1); 3636#L803-2 [2021-12-16 10:04:36,245 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:36,245 INFO L85 PathProgramCache]: Analyzing trace with hash -1184172610, now seen corresponding path program 1 times [2021-12-16 10:04:36,245 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:36,246 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [884950441] [2021-12-16 10:04:36,246 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:36,246 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:36,253 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:04:36,270 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:04:36,271 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:04:36,271 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [884950441] [2021-12-16 10:04:36,271 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [884950441] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:04:36,271 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:04:36,271 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:04:36,271 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [804641238] [2021-12-16 10:04:36,271 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:04:36,271 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:04:36,272 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:36,272 INFO L85 PathProgramCache]: Analyzing trace with hash -387617298, now seen corresponding path program 3 times [2021-12-16 10:04:36,272 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:36,272 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1833415106] [2021-12-16 10:04:36,272 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:36,272 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:36,278 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:04:36,296 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:04:36,297 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:04:36,297 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1833415106] [2021-12-16 10:04:36,297 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1833415106] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:04:36,297 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:04:36,297 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:04:36,297 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2066840741] [2021-12-16 10:04:36,297 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:04:36,297 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:04:36,297 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:04:36,298 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-16 10:04:36,298 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-16 10:04:36,298 INFO L87 Difference]: Start difference. First operand 425 states and 634 transitions. cyclomatic complexity: 210 Second operand has 4 states, 4 states have (on average 15.5) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:04:36,357 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:04:36,357 INFO L93 Difference]: Finished difference Result 746 states and 1107 transitions. [2021-12-16 10:04:36,358 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-16 10:04:36,360 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 746 states and 1107 transitions. [2021-12-16 10:04:36,363 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 669 [2021-12-16 10:04:36,366 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 746 states to 746 states and 1107 transitions. [2021-12-16 10:04:36,367 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 746 [2021-12-16 10:04:36,367 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 746 [2021-12-16 10:04:36,367 INFO L73 IsDeterministic]: Start isDeterministic. Operand 746 states and 1107 transitions. [2021-12-16 10:04:36,368 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:04:36,368 INFO L681 BuchiCegarLoop]: Abstraction has 746 states and 1107 transitions. [2021-12-16 10:04:36,369 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 746 states and 1107 transitions. [2021-12-16 10:04:36,376 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 746 to 746. [2021-12-16 10:04:36,377 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 746 states, 746 states have (on average 1.4839142091152815) internal successors, (1107), 745 states have internal predecessors, (1107), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:04:36,379 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 746 states to 746 states and 1107 transitions. [2021-12-16 10:04:36,379 INFO L704 BuchiCegarLoop]: Abstraction has 746 states and 1107 transitions. [2021-12-16 10:04:36,379 INFO L587 BuchiCegarLoop]: Abstraction has 746 states and 1107 transitions. [2021-12-16 10:04:36,379 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2021-12-16 10:04:36,379 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 746 states and 1107 transitions. [2021-12-16 10:04:36,381 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 669 [2021-12-16 10:04:36,381 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:04:36,381 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:04:36,382 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:36,382 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:36,386 INFO L791 eck$LassoCheckResult]: Stem: 5056#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 5049#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 4960#L766 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4710#L346 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4711#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 4766#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5017#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4716#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4717#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 4840#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4748#L514 assume !(0 == ~M_E~0); 4749#L514-2 assume !(0 == ~T1_E~0); 5037#L519-1 assume !(0 == ~T2_E~0); 4702#L524-1 assume !(0 == ~T3_E~0); 4703#L529-1 assume !(0 == ~T4_E~0); 4818#L534-1 assume !(0 == ~E_M~0); 4997#L539-1 assume !(0 == ~E_1~0); 4998#L544-1 assume !(0 == ~E_2~0); 5014#L549-1 assume !(0 == ~E_3~0); 5015#L554-1 assume 0 == ~E_4~0;~E_4~0 := 1; 4697#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4698#L250 assume 1 == ~m_pc~0; 4912#L251 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 5020#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4873#L262 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 4874#L637 assume !(0 != activate_threads_~tmp~1#1); 4704#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4705#L269 assume !(1 == ~t1_pc~0); 4642#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4641#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4836#L281 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 4837#L645 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4870#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4871#L288 assume 1 == ~t2_pc~0; 4975#L289 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4866#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4883#L300 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4884#L653 assume !(0 != activate_threads_~tmp___1~0#1); 4992#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4898#L307 assume !(1 == ~t3_pc~0); 4830#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 4831#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4952#L319 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5026#L661 assume !(0 != activate_threads_~tmp___2~0#1); 4845#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4846#L326 assume 1 == ~t4_pc~0; 5044#L327 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4656#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4896#L338 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4996#L669 assume !(0 != activate_threads_~tmp___3~0#1); 4993#L669-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4994#L572 assume 1 == ~M_E~0;~M_E~0 := 2; 5021#L572-2 assume !(1 == ~T1_E~0); 5045#L577-1 assume !(1 == ~T2_E~0); 5302#L582-1 assume !(1 == ~T3_E~0); 5300#L587-1 assume !(1 == ~T4_E~0); 5298#L592-1 assume !(1 == ~E_M~0); 5296#L597-1 assume 1 == ~E_1~0;~E_1~0 := 2; 5108#L602-1 assume !(1 == ~E_2~0); 5091#L607-1 assume !(1 == ~E_3~0); 5090#L612-1 assume !(1 == ~E_4~0); 5083#L617-1 assume { :end_inline_reset_delta_events } true; 5077#L803-2 [2021-12-16 10:04:36,386 INFO L793 eck$LassoCheckResult]: Loop: 5077#L803-2 assume !false; 5072#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5071#L489 assume !false; 5070#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 5069#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 5064#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 5063#L414 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 5061#L428 assume !(0 != eval_~tmp~0#1); 5060#L504 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5059#L346-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5057#L514-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5058#L514-5 assume !(0 == ~T1_E~0); 5282#L519-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5281#L524-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5280#L529-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5279#L534-3 assume 0 == ~E_M~0;~E_M~0 := 1; 5278#L539-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5277#L544-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5276#L549-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5275#L554-3 assume !(0 == ~E_4~0); 5274#L559-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5273#L250-18 assume 1 == ~m_pc~0; 5271#L251-6 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 5270#L261-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5269#L262-6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 5268#L637-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 5267#L637-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5266#L269-18 assume 1 == ~t1_pc~0; 5264#L270-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5263#L280-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5262#L281-6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 5261#L645-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5260#L645-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5259#L288-18 assume 1 == ~t2_pc~0; 5257#L289-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5256#L299-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5255#L300-6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 5253#L653-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5250#L653-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5030#L307-18 assume 1 == ~t3_pc~0; 4864#L308-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4776#L318-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4838#L319-6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4784#L661-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4785#L661-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5002#L326-18 assume 1 == ~t4_pc~0; 5003#L327-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5009#L337-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4979#L338-6 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4632#L669-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4633#L669-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5050#L572-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4801#L572-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4802#L577-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4695#L582-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4696#L587-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4933#L592-3 assume 1 == ~E_M~0;~E_M~0 := 2; 4934#L597-3 assume !(1 == ~E_1~0); 4851#L602-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4852#L607-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4810#L612-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4811#L617-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 4857#L386-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 4826#L413-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 4843#L414-1 start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 4893#L822 assume !(0 == start_simulation_~tmp~3#1); 4895#L822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 4999#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 4942#L413-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 4897#L414-2 stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 4668#L777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4669#L784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4940#L785 start_simulation_#t~ret18#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 4956#L835 assume !(0 != start_simulation_~tmp___0~1#1); 5077#L803-2 [2021-12-16 10:04:36,387 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:36,387 INFO L85 PathProgramCache]: Analyzing trace with hash 381143998, now seen corresponding path program 1 times [2021-12-16 10:04:36,387 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:36,387 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1588134565] [2021-12-16 10:04:36,387 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:36,387 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:36,405 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:04:36,431 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:04:36,431 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:04:36,431 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1588134565] [2021-12-16 10:04:36,431 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1588134565] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:04:36,431 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:04:36,431 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-16 10:04:36,432 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [344377407] [2021-12-16 10:04:36,432 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:04:36,432 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:04:36,432 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:36,432 INFO L85 PathProgramCache]: Analyzing trace with hash 1505824877, now seen corresponding path program 1 times [2021-12-16 10:04:36,432 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:36,432 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1863523097] [2021-12-16 10:04:36,433 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:36,433 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:36,438 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:04:36,466 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:04:36,466 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:04:36,466 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1863523097] [2021-12-16 10:04:36,470 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1863523097] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:04:36,470 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:04:36,470 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:04:36,471 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [665858428] [2021-12-16 10:04:36,471 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:04:36,471 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:04:36,472 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:04:36,472 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-16 10:04:36,472 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-16 10:04:36,473 INFO L87 Difference]: Start difference. First operand 746 states and 1107 transitions. cyclomatic complexity: 363 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 2 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:04:36,499 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:04:36,499 INFO L93 Difference]: Finished difference Result 746 states and 1087 transitions. [2021-12-16 10:04:36,500 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-16 10:04:36,501 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 746 states and 1087 transitions. [2021-12-16 10:04:36,504 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 669 [2021-12-16 10:04:36,507 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 746 states to 746 states and 1087 transitions. [2021-12-16 10:04:36,507 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 746 [2021-12-16 10:04:36,507 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 746 [2021-12-16 10:04:36,507 INFO L73 IsDeterministic]: Start isDeterministic. Operand 746 states and 1087 transitions. [2021-12-16 10:04:36,508 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:04:36,508 INFO L681 BuchiCegarLoop]: Abstraction has 746 states and 1087 transitions. [2021-12-16 10:04:36,509 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 746 states and 1087 transitions. [2021-12-16 10:04:36,545 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 746 to 746. [2021-12-16 10:04:36,545 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 746 states, 746 states have (on average 1.4571045576407506) internal successors, (1087), 745 states have internal predecessors, (1087), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:04:36,547 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 746 states to 746 states and 1087 transitions. [2021-12-16 10:04:36,547 INFO L704 BuchiCegarLoop]: Abstraction has 746 states and 1087 transitions. [2021-12-16 10:04:36,547 INFO L587 BuchiCegarLoop]: Abstraction has 746 states and 1087 transitions. [2021-12-16 10:04:36,547 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2021-12-16 10:04:36,547 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 746 states and 1087 transitions. [2021-12-16 10:04:36,550 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 669 [2021-12-16 10:04:36,550 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:04:36,550 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:04:36,552 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:36,552 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:36,553 INFO L791 eck$LassoCheckResult]: Stem: 6584#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 6570#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 6468#L766 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6208#L346 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6209#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 6265#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6534#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6214#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 6215#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 6341#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6246#L514 assume !(0 == ~M_E~0); 6247#L514-2 assume !(0 == ~T1_E~0); 6555#L519-1 assume !(0 == ~T2_E~0); 6199#L524-1 assume !(0 == ~T3_E~0); 6200#L529-1 assume !(0 == ~T4_E~0); 6319#L534-1 assume !(0 == ~E_M~0); 6512#L539-1 assume !(0 == ~E_1~0); 6513#L544-1 assume !(0 == ~E_2~0); 6532#L549-1 assume !(0 == ~E_3~0); 6533#L554-1 assume !(0 == ~E_4~0); 6195#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6196#L250 assume 1 == ~m_pc~0; 6411#L251 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 6538#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6375#L262 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 6376#L637 assume !(0 != activate_threads_~tmp~1#1); 6201#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6202#L269 assume !(1 == ~t1_pc~0); 6141#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 6140#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6338#L281 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 6339#L645 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 6372#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6373#L288 assume 1 == ~t2_pc~0; 6487#L289 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 6369#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6386#L300 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 6387#L653 assume !(0 != activate_threads_~tmp___1~0#1); 6506#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6400#L307 assume !(1 == ~t3_pc~0); 6332#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 6333#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6455#L319 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 6544#L661 assume !(0 != activate_threads_~tmp___2~0#1); 6348#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6349#L326 assume !(1 == ~t4_pc~0); 6154#L326-2 is_transmit4_triggered_~__retres1~4#1 := 0; 6155#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6396#L338 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 6511#L669 assume !(0 != activate_threads_~tmp___3~0#1); 6508#L669-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6509#L572 assume 1 == ~M_E~0;~M_E~0 := 2; 6539#L572-2 assume !(1 == ~T1_E~0); 6210#L577-1 assume !(1 == ~T2_E~0); 6211#L582-1 assume !(1 == ~T3_E~0); 6493#L587-1 assume !(1 == ~T4_E~0); 6501#L592-1 assume !(1 == ~E_M~0); 6146#L597-1 assume 1 == ~E_1~0;~E_1~0 := 2; 6147#L602-1 assume !(1 == ~E_2~0); 6365#L607-1 assume !(1 == ~E_3~0); 6366#L612-1 assume !(1 == ~E_4~0); 6317#L617-1 assume { :end_inline_reset_delta_events } true; 6318#L803-2 [2021-12-16 10:04:36,553 INFO L793 eck$LassoCheckResult]: Loop: 6318#L803-2 assume !false; 6586#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 6442#L489 assume !false; 6443#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 6583#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 6312#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 6313#L414 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 6585#L428 assume !(0 != eval_~tmp~0#1); 6587#L504 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 6480#L346-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 6481#L514-3 assume 0 == ~M_E~0;~M_E~0 := 1; 6380#L514-5 assume !(0 == ~T1_E~0); 6381#L519-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 6491#L524-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 6285#L529-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 6286#L534-3 assume 0 == ~E_M~0;~E_M~0 := 1; 6135#L539-3 assume 0 == ~E_1~0;~E_1~0 := 1; 6136#L544-3 assume 0 == ~E_2~0;~E_2~0 := 1; 6557#L549-3 assume 0 == ~E_3~0;~E_3~0 := 1; 6336#L554-3 assume !(0 == ~E_4~0); 6337#L559-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6438#L250-18 assume 1 == ~m_pc~0; 6478#L251-6 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 6452#L261-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6225#L262-6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 6226#L637-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 6295#L637-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6183#L269-18 assume !(1 == ~t1_pc~0); 6184#L269-20 is_transmit1_triggered_~__retres1~1#1 := 0; 6257#L280-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6258#L281-6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 6314#L645-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 6426#L645-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6324#L288-18 assume 1 == ~t2_pc~0; 6307#L289-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 6144#L299-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6145#L300-6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 6241#L653-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 6302#L653-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6303#L307-18 assume !(1 == ~t3_pc~0); 6274#L307-20 is_transmit3_triggered_~__retres1~3#1 := 0; 6275#L318-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6340#L319-6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 6283#L661-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 6284#L661-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6517#L326-18 assume !(1 == ~t4_pc~0); 6519#L326-20 is_transmit4_triggered_~__retres1~4#1 := 0; 6526#L337-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6492#L338-6 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 6131#L669-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 6132#L669-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6571#L572-3 assume 1 == ~M_E~0;~M_E~0 := 2; 6300#L572-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 6301#L577-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 6193#L582-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 6194#L587-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 6436#L592-3 assume 1 == ~E_M~0;~E_M~0 := 2; 6437#L597-3 assume !(1 == ~E_1~0); 6354#L602-3 assume 1 == ~E_2~0;~E_2~0 := 2; 6355#L607-3 assume 1 == ~E_3~0;~E_3~0 := 2; 6310#L612-3 assume !(1 == ~E_4~0); 6311#L617-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 6360#L386-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 6328#L413-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 6743#L414-1 start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 6742#L822 assume !(0 == start_simulation_~tmp~3#1); 6507#L822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 6737#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 6736#L413-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 6401#L414-2 stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 6167#L777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 6168#L784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6445#L785 start_simulation_#t~ret18#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 6547#L835 assume !(0 != start_simulation_~tmp___0~1#1); 6318#L803-2 [2021-12-16 10:04:36,553 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:36,553 INFO L85 PathProgramCache]: Analyzing trace with hash 1598746241, now seen corresponding path program 1 times [2021-12-16 10:04:36,553 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:36,553 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [450043025] [2021-12-16 10:04:36,553 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:36,554 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:36,562 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:04:36,582 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:04:36,583 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:04:36,583 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [450043025] [2021-12-16 10:04:36,583 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [450043025] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:04:36,583 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:04:36,583 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-16 10:04:36,583 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1129994053] [2021-12-16 10:04:36,583 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:04:36,583 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:04:36,584 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:36,584 INFO L85 PathProgramCache]: Analyzing trace with hash -1318960146, now seen corresponding path program 1 times [2021-12-16 10:04:36,584 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:36,584 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2025758267] [2021-12-16 10:04:36,584 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:36,584 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:36,591 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:04:36,609 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:04:36,610 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:04:36,610 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2025758267] [2021-12-16 10:04:36,610 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2025758267] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:04:36,610 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:04:36,610 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:04:36,610 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1672169861] [2021-12-16 10:04:36,610 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:04:36,610 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:04:36,611 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:04:36,611 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-16 10:04:36,611 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-16 10:04:36,611 INFO L87 Difference]: Start difference. First operand 746 states and 1087 transitions. cyclomatic complexity: 343 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 2 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:04:36,654 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:04:36,654 INFO L93 Difference]: Finished difference Result 1397 states and 2010 transitions. [2021-12-16 10:04:36,654 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-16 10:04:36,656 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1397 states and 2010 transitions. [2021-12-16 10:04:36,662 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1317 [2021-12-16 10:04:36,668 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1397 states to 1397 states and 2010 transitions. [2021-12-16 10:04:36,668 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1397 [2021-12-16 10:04:36,669 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1397 [2021-12-16 10:04:36,669 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1397 states and 2010 transitions. [2021-12-16 10:04:36,670 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:04:36,670 INFO L681 BuchiCegarLoop]: Abstraction has 1397 states and 2010 transitions. [2021-12-16 10:04:36,671 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1397 states and 2010 transitions. [2021-12-16 10:04:36,686 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1397 to 1329. [2021-12-16 10:04:36,687 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1329 states, 1329 states have (on average 1.4431903686982694) internal successors, (1918), 1328 states have internal predecessors, (1918), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:04:36,690 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1329 states to 1329 states and 1918 transitions. [2021-12-16 10:04:36,690 INFO L704 BuchiCegarLoop]: Abstraction has 1329 states and 1918 transitions. [2021-12-16 10:04:36,690 INFO L587 BuchiCegarLoop]: Abstraction has 1329 states and 1918 transitions. [2021-12-16 10:04:36,690 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2021-12-16 10:04:36,691 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1329 states and 1918 transitions. [2021-12-16 10:04:36,695 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1249 [2021-12-16 10:04:36,695 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:04:36,695 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:04:36,696 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:36,696 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:36,696 INFO L791 eck$LassoCheckResult]: Stem: 8776#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 8754#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 8630#L766 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8358#L346 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 8359#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 8418#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8710#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8364#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 8365#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 8496#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8398#L514 assume !(0 == ~M_E~0); 8399#L514-2 assume !(0 == ~T1_E~0); 8734#L519-1 assume !(0 == ~T2_E~0); 8349#L524-1 assume !(0 == ~T3_E~0); 8350#L529-1 assume !(0 == ~T4_E~0); 8472#L534-1 assume !(0 == ~E_M~0); 8677#L539-1 assume !(0 == ~E_1~0); 8678#L544-1 assume !(0 == ~E_2~0); 8708#L549-1 assume !(0 == ~E_3~0); 8709#L554-1 assume !(0 == ~E_4~0); 8345#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8346#L250 assume !(1 == ~m_pc~0); 8575#L250-2 is_master_triggered_~__retres1~0#1 := 0; 8714#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8534#L262 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 8535#L637 assume !(0 != activate_threads_~tmp~1#1); 8351#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8352#L269 assume !(1 == ~t1_pc~0); 8291#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 8290#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8492#L281 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 8493#L645 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8531#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8532#L288 assume 1 == ~t2_pc~0; 8651#L289 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 8527#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8545#L300 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 8546#L653 assume !(0 != activate_threads_~tmp___1~0#1); 8671#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8560#L307 assume !(1 == ~t3_pc~0); 8486#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 8487#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8616#L319 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 8721#L661 assume !(0 != activate_threads_~tmp___2~0#1); 8503#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8504#L326 assume !(1 == ~t4_pc~0); 8304#L326-2 is_transmit4_triggered_~__retres1~4#1 := 0; 8305#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8558#L338 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 8676#L669 assume !(0 != activate_threads_~tmp___3~0#1); 8673#L669-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8674#L572 assume 1 == ~M_E~0;~M_E~0 := 2; 8715#L572-2 assume !(1 == ~T1_E~0); 8360#L577-1 assume !(1 == ~T2_E~0); 8361#L582-1 assume !(1 == ~T3_E~0); 8660#L587-1 assume !(1 == ~T4_E~0); 8666#L592-1 assume !(1 == ~E_M~0); 8296#L597-1 assume 1 == ~E_1~0;~E_1~0 := 2; 8297#L602-1 assume !(1 == ~E_2~0); 8523#L607-1 assume !(1 == ~E_3~0); 8524#L612-1 assume !(1 == ~E_4~0); 8470#L617-1 assume { :end_inline_reset_delta_events } true; 8471#L803-2 [2021-12-16 10:04:36,696 INFO L793 eck$LassoCheckResult]: Loop: 8471#L803-2 assume !false; 8631#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 8390#L489 assume !false; 8601#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 9190#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 8465#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 8466#L414 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 8777#L428 assume !(0 != eval_~tmp~0#1); 9046#L504 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 9047#L346-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 9042#L514-3 assume 0 == ~M_E~0;~M_E~0 := 1; 9043#L514-5 assume !(0 == ~T1_E~0); 9499#L519-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 9498#L524-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 9497#L529-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 9496#L534-3 assume 0 == ~E_M~0;~E_M~0 := 1; 8285#L539-3 assume 0 == ~E_1~0;~E_1~0 := 1; 8286#L544-3 assume 0 == ~E_2~0;~E_2~0 := 1; 8736#L549-3 assume 0 == ~E_3~0;~E_3~0 := 1; 8490#L554-3 assume !(0 == ~E_4~0); 8491#L559-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8597#L250-18 assume !(1 == ~m_pc~0); 8685#L250-20 is_master_triggered_~__retres1~0#1 := 0; 8612#L261-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8613#L262-6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 8682#L637-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8683#L637-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9540#L269-18 assume 1 == ~t1_pc~0; 9538#L270-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8409#L280-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8410#L281-6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 8467#L645-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8584#L645-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8478#L288-18 assume 1 == ~t2_pc~0; 8460#L289-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 8294#L299-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8295#L300-6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 8393#L653-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 8456#L653-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8457#L307-18 assume !(1 == ~t3_pc~0); 8427#L307-20 is_transmit3_triggered_~__retres1~3#1 := 0; 8428#L318-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8494#L319-6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 8497#L661-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9023#L661-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9021#L326-18 assume !(1 == ~t4_pc~0); 9018#L326-20 is_transmit4_triggered_~__retres1~4#1 := 0; 9016#L337-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9012#L338-6 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 9008#L669-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 9004#L669-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9002#L572-3 assume 1 == ~M_E~0;~M_E~0 := 2; 9001#L572-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8477#L577-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 8343#L582-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8344#L587-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8595#L592-3 assume 1 == ~E_M~0;~E_M~0 := 2; 8596#L597-3 assume !(1 == ~E_1~0); 8510#L602-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8511#L607-3 assume 1 == ~E_3~0;~E_3~0 := 2; 8463#L612-3 assume !(1 == ~E_4~0); 8464#L617-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 8517#L386-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 8482#L413-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 8500#L414-1 start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 8555#L822 assume !(0 == start_simulation_~tmp~3#1); 8557#L822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 8680#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 8605#L413-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 8559#L414-2 stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 8317#L777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 8318#L784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8602#L785 start_simulation_#t~ret18#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 8622#L835 assume !(0 != start_simulation_~tmp___0~1#1); 8471#L803-2 [2021-12-16 10:04:36,697 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:36,697 INFO L85 PathProgramCache]: Analyzing trace with hash 1113571522, now seen corresponding path program 1 times [2021-12-16 10:04:36,697 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:36,697 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1221124681] [2021-12-16 10:04:36,697 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:36,698 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:36,705 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:04:36,729 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:04:36,729 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:04:36,729 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1221124681] [2021-12-16 10:04:36,729 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1221124681] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:04:36,729 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:04:36,729 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-16 10:04:36,729 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1972128719] [2021-12-16 10:04:36,730 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:04:36,730 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:04:36,730 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:36,730 INFO L85 PathProgramCache]: Analyzing trace with hash 300703534, now seen corresponding path program 1 times [2021-12-16 10:04:36,730 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:36,743 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [467640617] [2021-12-16 10:04:36,743 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:36,743 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:36,750 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:04:36,780 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:04:36,781 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:04:36,782 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [467640617] [2021-12-16 10:04:36,783 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [467640617] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:04:36,786 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:04:36,786 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:04:36,787 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [840310215] [2021-12-16 10:04:36,787 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:04:36,788 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:04:36,788 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:04:36,788 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-16 10:04:36,789 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-16 10:04:36,789 INFO L87 Difference]: Start difference. First operand 1329 states and 1918 transitions. cyclomatic complexity: 593 Second operand has 5 states, 5 states have (on average 12.4) internal successors, (62), 5 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:04:36,958 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:04:36,958 INFO L93 Difference]: Finished difference Result 3549 states and 5098 transitions. [2021-12-16 10:04:36,958 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-16 10:04:36,960 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3549 states and 5098 transitions. [2021-12-16 10:04:37,008 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3372 [2021-12-16 10:04:37,022 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3549 states to 3549 states and 5098 transitions. [2021-12-16 10:04:37,026 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3549 [2021-12-16 10:04:37,044 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3549 [2021-12-16 10:04:37,044 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3549 states and 5098 transitions. [2021-12-16 10:04:37,049 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:04:37,049 INFO L681 BuchiCegarLoop]: Abstraction has 3549 states and 5098 transitions. [2021-12-16 10:04:37,051 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3549 states and 5098 transitions. [2021-12-16 10:04:37,111 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3549 to 1404. [2021-12-16 10:04:37,114 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1404 states, 1404 states have (on average 1.4195156695156694) internal successors, (1993), 1403 states have internal predecessors, (1993), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:04:37,118 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1404 states to 1404 states and 1993 transitions. [2021-12-16 10:04:37,126 INFO L704 BuchiCegarLoop]: Abstraction has 1404 states and 1993 transitions. [2021-12-16 10:04:37,127 INFO L587 BuchiCegarLoop]: Abstraction has 1404 states and 1993 transitions. [2021-12-16 10:04:37,127 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2021-12-16 10:04:37,127 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1404 states and 1993 transitions. [2021-12-16 10:04:37,133 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1321 [2021-12-16 10:04:37,133 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:04:37,133 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:04:37,134 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:37,147 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:37,147 INFO L791 eck$LassoCheckResult]: Stem: 13717#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 13688#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 13542#L766 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 13252#L346 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 13253#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 13310#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 13629#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 13258#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 13259#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 13390#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 13292#L514 assume !(0 == ~M_E~0); 13293#L514-2 assume !(0 == ~T1_E~0); 13661#L519-1 assume !(0 == ~T2_E~0); 13243#L524-1 assume !(0 == ~T3_E~0); 13244#L529-1 assume !(0 == ~T4_E~0); 13365#L534-1 assume !(0 == ~E_M~0); 13594#L539-1 assume !(0 == ~E_1~0); 13595#L544-1 assume !(0 == ~E_2~0); 13627#L549-1 assume !(0 == ~E_3~0); 13628#L554-1 assume !(0 == ~E_4~0); 13239#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13240#L250 assume !(1 == ~m_pc~0); 13468#L250-2 is_master_triggered_~__retres1~0#1 := 0; 13634#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13428#L262 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 13429#L637 assume !(0 != activate_threads_~tmp~1#1); 13245#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13246#L269 assume !(1 == ~t1_pc~0); 13182#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 13360#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13476#L281 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 13662#L645 assume !(0 != activate_threads_~tmp___0~0#1); 13425#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13426#L288 assume 1 == ~t2_pc~0; 13563#L289 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 13420#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13442#L300 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 13443#L653 assume !(0 != activate_threads_~tmp___1~0#1); 13587#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 13456#L307 assume !(1 == ~t3_pc~0); 13381#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 13382#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13526#L319 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 13640#L661 assume !(0 != activate_threads_~tmp___2~0#1); 13397#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13398#L326 assume !(1 == ~t4_pc~0); 13197#L326-2 is_transmit4_triggered_~__retres1~4#1 := 0; 13198#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13452#L338 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 13593#L669 assume !(0 != activate_threads_~tmp___3~0#1); 13590#L669-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13591#L572 assume 1 == ~M_E~0;~M_E~0 := 2; 13635#L572-2 assume !(1 == ~T1_E~0); 13677#L577-1 assume !(1 == ~T2_E~0); 14404#L582-1 assume !(1 == ~T3_E~0); 14403#L587-1 assume !(1 == ~T4_E~0); 14402#L592-1 assume !(1 == ~E_M~0); 14401#L597-1 assume 1 == ~E_1~0;~E_1~0 := 2; 14400#L602-1 assume !(1 == ~E_2~0); 14395#L607-1 assume !(1 == ~E_3~0); 14393#L612-1 assume !(1 == ~E_4~0); 14359#L617-1 assume { :end_inline_reset_delta_events } true; 14358#L803-2 [2021-12-16 10:04:37,148 INFO L793 eck$LassoCheckResult]: Loop: 14358#L803-2 assume !false; 14251#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 14250#L489 assume !false; 14249#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 14248#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 14243#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 14242#L414 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 14240#L428 assume !(0 != eval_~tmp~0#1); 14241#L504 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 14447#L346-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 14446#L514-3 assume 0 == ~M_E~0;~M_E~0 := 1; 14445#L514-5 assume !(0 == ~T1_E~0); 14444#L519-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 14443#L524-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 14442#L529-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 14441#L534-3 assume 0 == ~E_M~0;~E_M~0 := 1; 14440#L539-3 assume 0 == ~E_1~0;~E_1~0 := 1; 14439#L544-3 assume 0 == ~E_2~0;~E_2~0 := 1; 14438#L549-3 assume 0 == ~E_3~0;~E_3~0 := 1; 14437#L554-3 assume !(0 == ~E_4~0); 14436#L559-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13603#L250-18 assume !(1 == ~m_pc~0); 13604#L250-20 is_master_triggered_~__retres1~0#1 := 0; 14059#L261-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14060#L262-6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 14055#L637-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 14056#L637-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13226#L269-18 assume !(1 == ~t1_pc~0); 13227#L269-20 is_transmit1_triggered_~__retres1~1#1 := 0; 14044#L280-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14045#L281-6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 14037#L645-18 assume !(0 != activate_threads_~tmp___0~0#1); 14034#L645-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14031#L288-18 assume 1 == ~t2_pc~0; 13352#L289-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 13185#L299-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13186#L300-6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 13287#L653-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 13348#L653-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 13349#L307-18 assume !(1 == ~t3_pc~0); 13319#L307-20 is_transmit3_triggered_~__retres1~3#1 := 0; 13320#L318-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13389#L319-6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 13328#L661-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 13329#L661-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13605#L326-18 assume !(1 == ~t4_pc~0); 13607#L326-20 is_transmit4_triggered_~__retres1~4#1 := 0; 13620#L337-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13573#L338-6 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 13172#L669-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 13173#L669-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13691#L572-3 assume 1 == ~M_E~0;~M_E~0 := 2; 13346#L572-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 13347#L577-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 13237#L582-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 13238#L587-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 13496#L592-3 assume 1 == ~E_M~0;~E_M~0 := 2; 13497#L597-3 assume !(1 == ~E_1~0); 13403#L602-3 assume 1 == ~E_2~0;~E_2~0 := 2; 13404#L607-3 assume 1 == ~E_3~0;~E_3~0 := 2; 13655#L612-3 assume !(1 == ~E_4~0); 13502#L617-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 13503#L386-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 14394#L413-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 14392#L414-1 start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 14391#L822 assume !(0 == start_simulation_~tmp~3#1); 14017#L822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 14366#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 14365#L413-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 14364#L414-2 stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 14363#L777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 14362#L784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 14361#L785 start_simulation_#t~ret18#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 14360#L835 assume !(0 != start_simulation_~tmp___0~1#1); 14358#L803-2 [2021-12-16 10:04:37,148 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:37,148 INFO L85 PathProgramCache]: Analyzing trace with hash 1815171396, now seen corresponding path program 1 times [2021-12-16 10:04:37,149 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:37,149 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1857204837] [2021-12-16 10:04:37,149 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:37,149 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:37,158 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:04:37,186 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:04:37,186 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:04:37,186 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1857204837] [2021-12-16 10:04:37,186 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1857204837] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:04:37,186 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:04:37,186 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:04:37,187 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [249181725] [2021-12-16 10:04:37,187 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:04:37,187 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:04:37,187 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:37,187 INFO L85 PathProgramCache]: Analyzing trace with hash 1804835377, now seen corresponding path program 1 times [2021-12-16 10:04:37,188 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:37,188 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [937625716] [2021-12-16 10:04:37,188 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:37,188 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:37,197 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:04:37,221 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:04:37,222 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:04:37,222 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [937625716] [2021-12-16 10:04:37,222 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [937625716] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:04:37,222 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:04:37,222 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:04:37,223 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1641513077] [2021-12-16 10:04:37,223 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:04:37,223 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:04:37,223 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:04:37,223 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-16 10:04:37,223 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-16 10:04:37,224 INFO L87 Difference]: Start difference. First operand 1404 states and 1993 transitions. cyclomatic complexity: 593 Second operand has 4 states, 4 states have (on average 15.5) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:04:37,335 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:04:37,335 INFO L93 Difference]: Finished difference Result 3543 states and 4967 transitions. [2021-12-16 10:04:37,335 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-16 10:04:37,336 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3543 states and 4967 transitions. [2021-12-16 10:04:37,369 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 3425 [2021-12-16 10:04:37,399 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3543 states to 3543 states and 4967 transitions. [2021-12-16 10:04:37,399 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3543 [2021-12-16 10:04:37,401 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3543 [2021-12-16 10:04:37,401 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3543 states and 4967 transitions. [2021-12-16 10:04:37,405 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:04:37,419 INFO L681 BuchiCegarLoop]: Abstraction has 3543 states and 4967 transitions. [2021-12-16 10:04:37,422 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3543 states and 4967 transitions. [2021-12-16 10:04:37,490 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3543 to 3431. [2021-12-16 10:04:37,508 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3431 states, 3431 states have (on average 1.4068784610900613) internal successors, (4827), 3430 states have internal predecessors, (4827), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:04:37,544 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3431 states to 3431 states and 4827 transitions. [2021-12-16 10:04:37,545 INFO L704 BuchiCegarLoop]: Abstraction has 3431 states and 4827 transitions. [2021-12-16 10:04:37,545 INFO L587 BuchiCegarLoop]: Abstraction has 3431 states and 4827 transitions. [2021-12-16 10:04:37,545 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2021-12-16 10:04:37,545 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3431 states and 4827 transitions. [2021-12-16 10:04:37,553 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 3337 [2021-12-16 10:04:37,553 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:04:37,553 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:04:37,554 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:37,554 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:37,554 INFO L791 eck$LassoCheckResult]: Stem: 18646#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 18611#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 18484#L766 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 18204#L346 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 18205#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 18263#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 18560#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 18210#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 18211#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 18345#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 18242#L514 assume !(0 == ~M_E~0); 18243#L514-2 assume !(0 == ~T1_E~0); 18581#L519-1 assume !(0 == ~T2_E~0); 18195#L524-1 assume !(0 == ~T3_E~0); 18196#L529-1 assume !(0 == ~T4_E~0); 18320#L534-1 assume !(0 == ~E_M~0); 18530#L539-1 assume !(0 == ~E_1~0); 18531#L544-1 assume !(0 == ~E_2~0); 18557#L549-1 assume !(0 == ~E_3~0); 18558#L554-1 assume !(0 == ~E_4~0); 18191#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 18192#L250 assume !(1 == ~m_pc~0); 18425#L250-2 is_master_triggered_~__retres1~0#1 := 0; 18564#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 18387#L262 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 18388#L637 assume !(0 != activate_threads_~tmp~1#1); 18198#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 18199#L269 assume !(1 == ~t1_pc~0); 18229#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 18315#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18341#L281 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 18342#L645 assume !(0 != activate_threads_~tmp___0~0#1); 18384#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18385#L288 assume !(1 == ~t2_pc~0); 18377#L288-2 is_transmit2_triggered_~__retres1~2#1 := 0; 18378#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 18398#L300 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 18399#L653 assume !(0 != activate_threads_~tmp___1~0#1); 18525#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18413#L307 assume !(1 == ~t3_pc~0); 18334#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 18335#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18470#L319 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 18572#L661 assume !(0 != activate_threads_~tmp___2~0#1); 18353#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 18354#L326 assume !(1 == ~t4_pc~0); 18150#L326-2 is_transmit4_triggered_~__retres1~4#1 := 0; 18151#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 18411#L338 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 18529#L669 assume !(0 != activate_threads_~tmp___3~0#1); 18526#L669-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 18527#L572 assume 1 == ~M_E~0;~M_E~0 := 2; 18565#L572-2 assume !(1 == ~T1_E~0); 18597#L577-1 assume !(1 == ~T2_E~0); 20833#L582-1 assume !(1 == ~T3_E~0); 18520#L587-1 assume !(1 == ~T4_E~0); 18521#L592-1 assume !(1 == ~E_M~0); 18141#L597-1 assume 1 == ~E_1~0;~E_1~0 := 2; 18142#L602-1 assume !(1 == ~E_2~0); 18374#L607-1 assume !(1 == ~E_3~0); 18375#L612-1 assume !(1 == ~E_4~0); 18318#L617-1 assume { :end_inline_reset_delta_events } true; 18319#L803-2 [2021-12-16 10:04:37,555 INFO L793 eck$LassoCheckResult]: Loop: 18319#L803-2 assume !false; 18486#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 18234#L489 assume !false; 18453#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 18416#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 18251#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 18314#L414 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 18643#L428 assume !(0 != eval_~tmp~0#1); 18627#L504 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 18498#L346-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 18449#L514-3 assume 0 == ~M_E~0;~M_E~0 := 1; 18392#L514-5 assume !(0 == ~T1_E~0); 18393#L519-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 18510#L524-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 18284#L529-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 18285#L534-3 assume 0 == ~E_M~0;~E_M~0 := 1; 18133#L539-3 assume 0 == ~E_1~0;~E_1~0 := 1; 18134#L544-3 assume 0 == ~E_2~0;~E_2~0 := 1; 18583#L549-3 assume 0 == ~E_3~0;~E_3~0 := 1; 18339#L554-3 assume !(0 == ~E_4~0); 18340#L559-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 18447#L250-18 assume !(1 == ~m_pc~0); 18541#L250-20 is_master_triggered_~__retres1~0#1 := 0; 18464#L261-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 18222#L262-6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 18223#L637-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 18294#L637-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 18179#L269-18 assume !(1 == ~t1_pc~0); 18180#L269-20 is_transmit1_triggered_~__retres1~1#1 := 0; 18253#L280-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18254#L281-6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 18313#L645-18 assume !(0 != activate_threads_~tmp___0~0#1); 18435#L645-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18325#L288-18 assume !(1 == ~t2_pc~0); 18326#L288-20 is_transmit2_triggered_~__retres1~2#1 := 0; 18139#L299-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 18140#L300-6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 18237#L653-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 18301#L653-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18302#L307-18 assume !(1 == ~t3_pc~0); 18273#L307-20 is_transmit3_triggered_~__retres1~3#1 := 0; 18274#L318-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18343#L319-6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 18282#L661-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 18283#L661-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 18538#L326-18 assume !(1 == ~t4_pc~0); 18540#L326-20 is_transmit4_triggered_~__retres1~4#1 := 0; 18548#L337-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 18511#L338-6 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 18129#L669-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 18130#L669-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 18612#L572-3 assume 1 == ~M_E~0;~M_E~0 := 2; 18297#L572-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 18298#L577-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 18189#L582-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 18190#L587-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 18445#L592-3 assume 1 == ~E_M~0;~E_M~0 := 2; 18446#L597-3 assume !(1 == ~E_1~0); 18362#L602-3 assume 1 == ~E_2~0;~E_2~0 := 2; 18363#L607-3 assume 1 == ~E_3~0;~E_3~0 := 2; 18311#L612-3 assume !(1 == ~E_4~0); 18312#L617-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 18368#L386-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 18330#L413-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 21268#L414-1 start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 18408#L822 assume !(0 == start_simulation_~tmp~3#1); 18410#L822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 18536#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 18458#L413-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 18412#L414-2 stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 18163#L777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 18164#L784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 18454#L785 start_simulation_#t~ret18#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 18474#L835 assume !(0 != start_simulation_~tmp___0~1#1); 18319#L803-2 [2021-12-16 10:04:37,555 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:37,555 INFO L85 PathProgramCache]: Analyzing trace with hash 843496709, now seen corresponding path program 1 times [2021-12-16 10:04:37,555 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:37,555 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1446812112] [2021-12-16 10:04:37,556 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:37,556 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:37,563 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:04:37,581 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:04:37,581 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:04:37,581 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1446812112] [2021-12-16 10:04:37,582 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1446812112] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:04:37,582 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:04:37,582 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-16 10:04:37,582 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [352750056] [2021-12-16 10:04:37,582 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:04:37,582 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:04:37,582 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:37,583 INFO L85 PathProgramCache]: Analyzing trace with hash 1319660658, now seen corresponding path program 1 times [2021-12-16 10:04:37,583 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:37,583 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [330258357] [2021-12-16 10:04:37,583 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:37,583 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:37,588 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:04:37,602 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:04:37,602 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:04:37,603 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [330258357] [2021-12-16 10:04:37,603 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [330258357] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:04:37,603 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:04:37,603 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:04:37,603 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1407097655] [2021-12-16 10:04:37,603 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:04:37,603 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:04:37,604 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:04:37,604 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-16 10:04:37,604 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-16 10:04:37,604 INFO L87 Difference]: Start difference. First operand 3431 states and 4827 transitions. cyclomatic complexity: 1404 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 2 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:04:37,644 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:04:37,644 INFO L93 Difference]: Finished difference Result 5026 states and 7076 transitions. [2021-12-16 10:04:37,645 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-16 10:04:37,645 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5026 states and 7076 transitions. [2021-12-16 10:04:37,665 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 4923 [2021-12-16 10:04:37,681 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5026 states to 5026 states and 7076 transitions. [2021-12-16 10:04:37,682 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5026 [2021-12-16 10:04:37,685 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5026 [2021-12-16 10:04:37,685 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5026 states and 7076 transitions. [2021-12-16 10:04:37,690 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:04:37,690 INFO L681 BuchiCegarLoop]: Abstraction has 5026 states and 7076 transitions. [2021-12-16 10:04:37,692 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5026 states and 7076 transitions. [2021-12-16 10:04:37,729 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5026 to 3481. [2021-12-16 10:04:37,734 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3481 states, 3481 states have (on average 1.4105142200517093) internal successors, (4910), 3480 states have internal predecessors, (4910), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:04:37,744 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3481 states to 3481 states and 4910 transitions. [2021-12-16 10:04:37,745 INFO L704 BuchiCegarLoop]: Abstraction has 3481 states and 4910 transitions. [2021-12-16 10:04:37,745 INFO L587 BuchiCegarLoop]: Abstraction has 3481 states and 4910 transitions. [2021-12-16 10:04:37,745 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2021-12-16 10:04:37,745 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3481 states and 4910 transitions. [2021-12-16 10:04:37,755 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3397 [2021-12-16 10:04:37,755 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:04:37,755 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:04:37,756 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:37,756 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:37,757 INFO L791 eck$LassoCheckResult]: Stem: 27059#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 27038#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 26927#L766 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 26668#L346 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 26669#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 26725#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 26993#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 26674#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 26675#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 26802#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 26707#L514 assume !(0 == ~M_E~0); 26708#L514-2 assume !(0 == ~T1_E~0); 27017#L519-1 assume !(0 == ~T2_E~0); 26659#L524-1 assume !(0 == ~T3_E~0); 26660#L529-1 assume !(0 == ~T4_E~0); 26779#L534-1 assume !(0 == ~E_M~0); 26969#L539-1 assume !(0 == ~E_1~0); 26970#L544-1 assume !(0 == ~E_2~0); 26990#L549-1 assume !(0 == ~E_3~0); 26991#L554-1 assume !(0 == ~E_4~0); 26655#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 26656#L250 assume !(1 == ~m_pc~0); 26875#L250-2 is_master_triggered_~__retres1~0#1 := 0; 26997#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 26837#L262 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 26838#L637 assume !(0 != activate_threads_~tmp~1#1); 26662#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26663#L269 assume !(1 == ~t1_pc~0); 26693#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 26774#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 26798#L281 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 26799#L645 assume !(0 != activate_threads_~tmp___0~0#1); 26834#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 26835#L288 assume !(1 == ~t2_pc~0); 26830#L288-2 is_transmit2_triggered_~__retres1~2#1 := 0; 26831#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 26848#L300 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 26849#L653 assume !(0 != activate_threads_~tmp___1~0#1); 26962#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 26863#L307 assume !(1 == ~t3_pc~0); 26792#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 26793#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 26921#L319 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 27001#L661 assume !(0 != activate_threads_~tmp___2~0#1); 26810#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 26811#L326 assume !(1 == ~t4_pc~0); 26613#L326-2 is_transmit4_triggered_~__retres1~4#1 := 0; 26614#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 26861#L338 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 26968#L669 assume !(0 != activate_threads_~tmp___3~0#1); 26965#L669-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 26966#L572 assume !(1 == ~M_E~0); 26998#L572-2 assume !(1 == ~T1_E~0); 26670#L577-1 assume !(1 == ~T2_E~0); 26671#L582-1 assume !(1 == ~T3_E~0); 26952#L587-1 assume !(1 == ~T4_E~0); 26958#L592-1 assume !(1 == ~E_M~0); 26611#L597-1 assume 1 == ~E_1~0;~E_1~0 := 2; 26612#L602-1 assume !(1 == ~E_2~0); 26827#L607-1 assume !(1 == ~E_3~0); 26828#L612-1 assume !(1 == ~E_4~0); 26777#L617-1 assume { :end_inline_reset_delta_events } true; 26778#L803-2 [2021-12-16 10:04:37,757 INFO L793 eck$LassoCheckResult]: Loop: 26778#L803-2 assume !false; 29237#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 29235#L489 assume !false; 29233#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 29231#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 29225#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 29223#L414 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 29220#L428 assume !(0 != eval_~tmp~0#1); 29219#L504 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 29218#L346-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 29214#L514-3 assume !(0 == ~M_E~0); 29210#L514-5 assume !(0 == ~T1_E~0); 29209#L519-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 29206#L524-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 29201#L529-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 29195#L534-3 assume 0 == ~E_M~0;~E_M~0 := 1; 29193#L539-3 assume 0 == ~E_1~0;~E_1~0 := 1; 29191#L544-3 assume 0 == ~E_2~0;~E_2~0 := 1; 29185#L549-3 assume 0 == ~E_3~0;~E_3~0 := 1; 29183#L554-3 assume !(0 == ~E_4~0); 29181#L559-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 29178#L250-18 assume !(1 == ~m_pc~0); 29176#L250-20 is_master_triggered_~__retres1~0#1 := 0; 29174#L261-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 29172#L262-6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 29170#L637-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 29168#L637-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 29166#L269-18 assume !(1 == ~t1_pc~0); 29164#L269-20 is_transmit1_triggered_~__retres1~1#1 := 0; 29162#L280-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 29160#L281-6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 29158#L645-18 assume !(0 != activate_threads_~tmp___0~0#1); 29156#L645-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 29154#L288-18 assume !(1 == ~t2_pc~0); 29152#L288-20 is_transmit2_triggered_~__retres1~2#1 := 0; 29150#L299-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29147#L300-6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 29145#L653-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 29143#L653-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 29141#L307-18 assume !(1 == ~t3_pc~0); 29138#L307-20 is_transmit3_triggered_~__retres1~3#1 := 0; 29136#L318-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 29134#L319-6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 29132#L661-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 29130#L661-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 29128#L326-18 assume !(1 == ~t4_pc~0); 29125#L326-20 is_transmit4_triggered_~__retres1~4#1 := 0; 29123#L337-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 29121#L338-6 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 29119#L669-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 29117#L669-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 29115#L572-3 assume !(1 == ~M_E~0); 28797#L572-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 29112#L577-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 29109#L582-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 29107#L587-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 29105#L592-3 assume 1 == ~E_M~0;~E_M~0 := 2; 29103#L597-3 assume !(1 == ~E_1~0); 29101#L602-3 assume 1 == ~E_2~0;~E_2~0 := 2; 29098#L607-3 assume 1 == ~E_3~0;~E_3~0 := 2; 29096#L612-3 assume !(1 == ~E_4~0); 29094#L617-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 26821#L386-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 26788#L413-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 26806#L414-1 start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 26858#L822 assume !(0 == start_simulation_~tmp~3#1); 26860#L822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 29330#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 29328#L413-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 29326#L414-2 stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 29324#L777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 29322#L784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 29321#L785 start_simulation_#t~ret18#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 29317#L835 assume !(0 != start_simulation_~tmp___0~1#1); 26778#L803-2 [2021-12-16 10:04:37,757 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:37,757 INFO L85 PathProgramCache]: Analyzing trace with hash 1544561287, now seen corresponding path program 1 times [2021-12-16 10:04:37,758 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:37,758 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1506289902] [2021-12-16 10:04:37,758 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:37,758 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:37,765 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:04:37,781 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:04:37,781 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:04:37,781 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1506289902] [2021-12-16 10:04:37,781 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1506289902] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:04:37,781 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:04:37,781 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-16 10:04:37,782 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [797990964] [2021-12-16 10:04:37,782 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:04:37,782 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:04:37,782 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:37,782 INFO L85 PathProgramCache]: Analyzing trace with hash -540170574, now seen corresponding path program 1 times [2021-12-16 10:04:37,782 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:37,783 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [974632025] [2021-12-16 10:04:37,783 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:37,783 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:37,789 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:04:37,801 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:04:37,802 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:04:37,802 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [974632025] [2021-12-16 10:04:37,802 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [974632025] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:04:37,802 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:04:37,802 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:04:37,802 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [960879712] [2021-12-16 10:04:37,802 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:04:37,803 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:04:37,803 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:04:37,803 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-16 10:04:37,803 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-16 10:04:37,804 INFO L87 Difference]: Start difference. First operand 3481 states and 4910 transitions. cyclomatic complexity: 1433 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 2 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:04:37,837 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:04:37,838 INFO L93 Difference]: Finished difference Result 3361 states and 4672 transitions. [2021-12-16 10:04:37,838 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-16 10:04:37,838 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3361 states and 4672 transitions. [2021-12-16 10:04:37,848 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3277 [2021-12-16 10:04:37,862 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3361 states to 3361 states and 4672 transitions. [2021-12-16 10:04:37,863 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3361 [2021-12-16 10:04:37,864 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3361 [2021-12-16 10:04:37,865 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3361 states and 4672 transitions. [2021-12-16 10:04:37,867 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:04:37,867 INFO L681 BuchiCegarLoop]: Abstraction has 3361 states and 4672 transitions. [2021-12-16 10:04:37,869 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3361 states and 4672 transitions. [2021-12-16 10:04:37,896 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3361 to 3361. [2021-12-16 10:04:37,900 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3361 states, 3361 states have (on average 1.3900624814043439) internal successors, (4672), 3360 states have internal predecessors, (4672), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:04:37,905 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3361 states to 3361 states and 4672 transitions. [2021-12-16 10:04:37,905 INFO L704 BuchiCegarLoop]: Abstraction has 3361 states and 4672 transitions. [2021-12-16 10:04:37,905 INFO L587 BuchiCegarLoop]: Abstraction has 3361 states and 4672 transitions. [2021-12-16 10:04:37,905 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2021-12-16 10:04:37,905 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3361 states and 4672 transitions. [2021-12-16 10:04:37,912 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3277 [2021-12-16 10:04:37,912 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:04:37,912 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:04:37,913 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:37,913 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:37,913 INFO L791 eck$LassoCheckResult]: Stem: 33919#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 33889#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 33774#L766 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 33515#L346 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 33516#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 33571#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 33842#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 33521#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 33522#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 33647#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 33553#L514 assume !(0 == ~M_E~0); 33554#L514-2 assume !(0 == ~T1_E~0); 33867#L519-1 assume !(0 == ~T2_E~0); 33506#L524-1 assume !(0 == ~T3_E~0); 33507#L529-1 assume !(0 == ~T4_E~0); 33624#L534-1 assume !(0 == ~E_M~0); 33816#L539-1 assume !(0 == ~E_1~0); 33817#L544-1 assume !(0 == ~E_2~0); 33839#L549-1 assume !(0 == ~E_3~0); 33840#L554-1 assume !(0 == ~E_4~0); 33502#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 33503#L250 assume !(1 == ~m_pc~0); 33721#L250-2 is_master_triggered_~__retres1~0#1 := 0; 33845#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 33684#L262 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 33685#L637 assume !(0 != activate_threads_~tmp~1#1); 33509#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 33510#L269 assume !(1 == ~t1_pc~0); 33540#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 33619#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 33644#L281 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 33645#L645 assume !(0 != activate_threads_~tmp___0~0#1); 33680#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 33681#L288 assume !(1 == ~t2_pc~0); 33675#L288-2 is_transmit2_triggered_~__retres1~2#1 := 0; 33676#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 33695#L300 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 33696#L653 assume !(0 != activate_threads_~tmp___1~0#1); 33810#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 33709#L307 assume !(1 == ~t3_pc~0); 33637#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 33638#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 33764#L319 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 33852#L661 assume !(0 != activate_threads_~tmp___2~0#1); 33655#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 33656#L326 assume !(1 == ~t4_pc~0); 33462#L326-2 is_transmit4_triggered_~__retres1~4#1 := 0; 33463#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 33708#L338 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 33815#L669 assume !(0 != activate_threads_~tmp___3~0#1); 33811#L669-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 33812#L572 assume !(1 == ~M_E~0); 33846#L572-2 assume !(1 == ~T1_E~0); 33517#L577-1 assume !(1 == ~T2_E~0); 33518#L582-1 assume !(1 == ~T3_E~0); 33800#L587-1 assume !(1 == ~T4_E~0); 33806#L592-1 assume !(1 == ~E_M~0); 33456#L597-1 assume !(1 == ~E_1~0); 33457#L602-1 assume !(1 == ~E_2~0); 33672#L607-1 assume !(1 == ~E_3~0); 33673#L612-1 assume !(1 == ~E_4~0); 33622#L617-1 assume { :end_inline_reset_delta_events } true; 33623#L803-2 [2021-12-16 10:04:37,914 INFO L793 eck$LassoCheckResult]: Loop: 33623#L803-2 assume !false; 34425#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 34420#L489 assume !false; 34416#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 34395#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 34386#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 34380#L414 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 34374#L428 assume !(0 != eval_~tmp~0#1); 34375#L504 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 34900#L346-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 34898#L514-3 assume !(0 == ~M_E~0); 34896#L514-5 assume !(0 == ~T1_E~0); 34894#L519-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 34892#L524-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 34890#L529-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 34888#L534-3 assume 0 == ~E_M~0;~E_M~0 := 1; 34886#L539-3 assume !(0 == ~E_1~0); 34884#L544-3 assume 0 == ~E_2~0;~E_2~0 := 1; 34882#L549-3 assume 0 == ~E_3~0;~E_3~0 := 1; 34880#L554-3 assume !(0 == ~E_4~0); 34878#L559-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 34876#L250-18 assume !(1 == ~m_pc~0); 34874#L250-20 is_master_triggered_~__retres1~0#1 := 0; 34872#L261-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 34870#L262-6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 34868#L637-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 34866#L637-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 34864#L269-18 assume !(1 == ~t1_pc~0); 34862#L269-20 is_transmit1_triggered_~__retres1~1#1 := 0; 34860#L280-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 34858#L281-6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 34856#L645-18 assume !(0 != activate_threads_~tmp___0~0#1); 34854#L645-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 34852#L288-18 assume !(1 == ~t2_pc~0); 34849#L288-20 is_transmit2_triggered_~__retres1~2#1 := 0; 34846#L299-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 34843#L300-6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 34840#L653-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 34837#L653-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 34834#L307-18 assume !(1 == ~t3_pc~0); 34830#L307-20 is_transmit3_triggered_~__retres1~3#1 := 0; 34826#L318-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 34823#L319-6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 34820#L661-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 34817#L661-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 34814#L326-18 assume !(1 == ~t4_pc~0); 34809#L326-20 is_transmit4_triggered_~__retres1~4#1 := 0; 34806#L337-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 34803#L338-6 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 34800#L669-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 34797#L669-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 34794#L572-3 assume !(1 == ~M_E~0); 34790#L572-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 34786#L577-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 34783#L582-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 34780#L587-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 34777#L592-3 assume 1 == ~E_M~0;~E_M~0 := 2; 34774#L597-3 assume !(1 == ~E_1~0); 34771#L602-3 assume 1 == ~E_2~0;~E_2~0 := 2; 34767#L607-3 assume 1 == ~E_3~0;~E_3~0 := 2; 34764#L612-3 assume !(1 == ~E_4~0); 34760#L617-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 34752#L386-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 34747#L413-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 34548#L414-1 start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 34545#L822 assume !(0 == start_simulation_~tmp~3#1); 34542#L822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 34518#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 34513#L413-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 34507#L414-2 stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 34501#L777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 34479#L784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 34475#L785 start_simulation_#t~ret18#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 34473#L835 assume !(0 != start_simulation_~tmp___0~1#1); 33623#L803-2 [2021-12-16 10:04:37,914 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:37,914 INFO L85 PathProgramCache]: Analyzing trace with hash 1546408329, now seen corresponding path program 1 times [2021-12-16 10:04:37,914 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:37,914 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [154281690] [2021-12-16 10:04:37,914 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:37,915 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:37,921 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:04:37,921 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-16 10:04:37,937 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:04:37,962 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-16 10:04:37,963 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:37,963 INFO L85 PathProgramCache]: Analyzing trace with hash -106441488, now seen corresponding path program 1 times [2021-12-16 10:04:37,963 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:37,985 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1596263710] [2021-12-16 10:04:37,985 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:37,985 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:37,991 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:04:38,013 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:04:38,013 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:04:38,013 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1596263710] [2021-12-16 10:04:38,014 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1596263710] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:04:38,014 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:04:38,014 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-16 10:04:38,014 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1860903984] [2021-12-16 10:04:38,014 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:04:38,014 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:04:38,015 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:04:38,015 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-16 10:04:38,015 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-16 10:04:38,015 INFO L87 Difference]: Start difference. First operand 3361 states and 4672 transitions. cyclomatic complexity: 1315 Second operand has 5 states, 5 states have (on average 14.8) internal successors, (74), 5 states have internal predecessors, (74), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:04:38,085 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:04:38,085 INFO L93 Difference]: Finished difference Result 5920 states and 8109 transitions. [2021-12-16 10:04:38,086 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2021-12-16 10:04:38,086 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5920 states and 8109 transitions. [2021-12-16 10:04:38,104 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 5816 [2021-12-16 10:04:38,119 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5920 states to 5920 states and 8109 transitions. [2021-12-16 10:04:38,119 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5920 [2021-12-16 10:04:38,123 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5920 [2021-12-16 10:04:38,123 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5920 states and 8109 transitions. [2021-12-16 10:04:38,130 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:04:38,130 INFO L681 BuchiCegarLoop]: Abstraction has 5920 states and 8109 transitions. [2021-12-16 10:04:38,134 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5920 states and 8109 transitions. [2021-12-16 10:04:38,178 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5920 to 3397. [2021-12-16 10:04:38,182 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3397 states, 3397 states have (on average 1.3859287606711805) internal successors, (4708), 3396 states have internal predecessors, (4708), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:04:38,187 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3397 states to 3397 states and 4708 transitions. [2021-12-16 10:04:38,188 INFO L704 BuchiCegarLoop]: Abstraction has 3397 states and 4708 transitions. [2021-12-16 10:04:38,188 INFO L587 BuchiCegarLoop]: Abstraction has 3397 states and 4708 transitions. [2021-12-16 10:04:38,188 INFO L425 BuchiCegarLoop]: ======== Iteration 13============ [2021-12-16 10:04:38,188 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3397 states and 4708 transitions. [2021-12-16 10:04:38,195 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3313 [2021-12-16 10:04:38,195 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:04:38,195 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:04:38,196 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:38,196 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:38,196 INFO L791 eck$LassoCheckResult]: Stem: 43232#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 43205#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 43088#L766 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 42812#L346 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 42813#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 42871#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 43160#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 42818#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 42819#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 42950#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 42850#L514 assume !(0 == ~M_E~0); 42851#L514-2 assume !(0 == ~T1_E~0); 43181#L519-1 assume !(0 == ~T2_E~0); 42803#L524-1 assume !(0 == ~T3_E~0); 42804#L529-1 assume !(0 == ~T4_E~0); 42927#L534-1 assume !(0 == ~E_M~0); 43129#L539-1 assume !(0 == ~E_1~0); 43130#L544-1 assume !(0 == ~E_2~0); 43156#L549-1 assume !(0 == ~E_3~0); 43157#L554-1 assume !(0 == ~E_4~0); 42799#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 42800#L250 assume !(1 == ~m_pc~0); 43029#L250-2 is_master_triggered_~__retres1~0#1 := 0; 43163#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 42988#L262 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 42989#L637 assume !(0 != activate_threads_~tmp~1#1); 42806#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 42807#L269 assume !(1 == ~t1_pc~0); 42837#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 42922#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 42947#L281 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 42948#L645 assume !(0 != activate_threads_~tmp___0~0#1); 42985#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 42986#L288 assume !(1 == ~t2_pc~0); 42980#L288-2 is_transmit2_triggered_~__retres1~2#1 := 0; 42981#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 43001#L300 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 43002#L653 assume !(0 != activate_threads_~tmp___1~0#1); 43123#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 43017#L307 assume !(1 == ~t3_pc~0); 42941#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 42942#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 43078#L319 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 43167#L661 assume !(0 != activate_threads_~tmp___2~0#1); 42960#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 42961#L326 assume !(1 == ~t4_pc~0); 42760#L326-2 is_transmit4_triggered_~__retres1~4#1 := 0; 42761#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 43014#L338 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 43128#L669 assume !(0 != activate_threads_~tmp___3~0#1); 43125#L669-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 43126#L572 assume !(1 == ~M_E~0); 43164#L572-2 assume !(1 == ~T1_E~0); 42814#L577-1 assume !(1 == ~T2_E~0); 42815#L582-1 assume !(1 == ~T3_E~0); 43113#L587-1 assume !(1 == ~T4_E~0); 43119#L592-1 assume !(1 == ~E_M~0); 42753#L597-1 assume !(1 == ~E_1~0); 42754#L602-1 assume !(1 == ~E_2~0); 42977#L607-1 assume !(1 == ~E_3~0); 42978#L612-1 assume !(1 == ~E_4~0); 42925#L617-1 assume { :end_inline_reset_delta_events } true; 42926#L803-2 [2021-12-16 10:04:38,196 INFO L793 eck$LassoCheckResult]: Loop: 42926#L803-2 assume !false; 43089#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 42842#L489 assume !false; 43061#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 43018#L386 assume !(0 == ~m_st~0); 43019#L390 assume !(0 == ~t1_st~0); 43032#L394 assume !(0 == ~t2_st~0); 43192#L398 assume !(0 == ~t3_st~0); 42859#L402 assume !(0 == ~t4_st~0);exists_runnable_thread_~__retres1~5#1 := 0; 42861#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 44998#L414 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 44997#L428 assume !(0 != eval_~tmp~0#1); 44996#L504 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 44995#L346-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 44994#L514-3 assume !(0 == ~M_E~0); 44993#L514-5 assume !(0 == ~T1_E~0); 44992#L519-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 44991#L524-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 44990#L529-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 44989#L534-3 assume 0 == ~E_M~0;~E_M~0 := 1; 44988#L539-3 assume !(0 == ~E_1~0); 44987#L544-3 assume 0 == ~E_2~0;~E_2~0 := 1; 44986#L549-3 assume 0 == ~E_3~0;~E_3~0 := 1; 44985#L554-3 assume !(0 == ~E_4~0); 44984#L559-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 44983#L250-18 assume !(1 == ~m_pc~0); 44982#L250-20 is_master_triggered_~__retres1~0#1 := 0; 44981#L261-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 44980#L262-6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 44979#L637-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 44978#L637-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 44977#L269-18 assume !(1 == ~t1_pc~0); 44976#L269-20 is_transmit1_triggered_~__retres1~1#1 := 0; 44975#L280-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 44974#L281-6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 44973#L645-18 assume !(0 != activate_threads_~tmp___0~0#1); 44972#L645-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 44971#L288-18 assume !(1 == ~t2_pc~0); 44970#L288-20 is_transmit2_triggered_~__retres1~2#1 := 0; 44969#L299-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 44968#L300-6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 44967#L653-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 44966#L653-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 44965#L307-18 assume !(1 == ~t3_pc~0); 44963#L307-20 is_transmit3_triggered_~__retres1~3#1 := 0; 44962#L318-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 44961#L319-6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 44960#L661-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 44959#L661-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 44958#L326-18 assume !(1 == ~t4_pc~0); 44956#L326-20 is_transmit4_triggered_~__retres1~4#1 := 0; 44955#L337-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 44954#L338-6 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 44953#L669-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 44952#L669-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 44951#L572-3 assume !(1 == ~M_E~0); 44803#L572-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 44950#L577-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 44949#L582-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 44948#L587-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 44947#L592-3 assume 1 == ~E_M~0;~E_M~0 := 2; 44946#L597-3 assume !(1 == ~E_1~0); 44945#L602-3 assume 1 == ~E_2~0;~E_2~0 := 2; 44944#L607-3 assume 1 == ~E_3~0;~E_3~0 := 2; 44943#L612-3 assume !(1 == ~E_4~0); 44942#L617-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 44940#L386-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 44936#L413-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 44935#L414-1 start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 44934#L822 assume !(0 == start_simulation_~tmp~3#1); 43124#L822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 43134#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 46104#L413-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 46102#L414-2 stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 42772#L777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 42773#L784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 43062#L785 start_simulation_#t~ret18#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 43079#L835 assume !(0 != start_simulation_~tmp___0~1#1); 42926#L803-2 [2021-12-16 10:04:38,197 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:38,197 INFO L85 PathProgramCache]: Analyzing trace with hash 1546408329, now seen corresponding path program 2 times [2021-12-16 10:04:38,197 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:38,197 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1178463414] [2021-12-16 10:04:38,197 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:38,197 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:38,202 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:04:38,203 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-16 10:04:38,206 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:04:38,213 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-16 10:04:38,214 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:38,214 INFO L85 PathProgramCache]: Analyzing trace with hash -1218277148, now seen corresponding path program 1 times [2021-12-16 10:04:38,214 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:38,214 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [128990470] [2021-12-16 10:04:38,214 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:38,215 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:38,222 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:04:38,257 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:04:38,258 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:04:38,258 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [128990470] [2021-12-16 10:04:38,258 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [128990470] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:04:38,258 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:04:38,258 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-16 10:04:38,258 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [345173025] [2021-12-16 10:04:38,258 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:04:38,259 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:04:38,259 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:04:38,259 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-16 10:04:38,259 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-16 10:04:38,259 INFO L87 Difference]: Start difference. First operand 3397 states and 4708 transitions. cyclomatic complexity: 1315 Second operand has 5 states, 5 states have (on average 15.6) internal successors, (78), 5 states have internal predecessors, (78), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:04:38,386 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:04:38,386 INFO L93 Difference]: Finished difference Result 6712 states and 9217 transitions. [2021-12-16 10:04:38,386 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-16 10:04:38,387 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6712 states and 9217 transitions. [2021-12-16 10:04:38,410 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 6620 [2021-12-16 10:04:38,428 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6712 states to 6712 states and 9217 transitions. [2021-12-16 10:04:38,428 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6712 [2021-12-16 10:04:38,432 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6712 [2021-12-16 10:04:38,433 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6712 states and 9217 transitions. [2021-12-16 10:04:38,440 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:04:38,440 INFO L681 BuchiCegarLoop]: Abstraction has 6712 states and 9217 transitions. [2021-12-16 10:04:38,444 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6712 states and 9217 transitions. [2021-12-16 10:04:38,546 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6712 to 3496. [2021-12-16 10:04:38,552 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3496 states, 3496 states have (on average 1.3669908466819223) internal successors, (4779), 3495 states have internal predecessors, (4779), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:04:38,561 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3496 states to 3496 states and 4779 transitions. [2021-12-16 10:04:38,561 INFO L704 BuchiCegarLoop]: Abstraction has 3496 states and 4779 transitions. [2021-12-16 10:04:38,561 INFO L587 BuchiCegarLoop]: Abstraction has 3496 states and 4779 transitions. [2021-12-16 10:04:38,561 INFO L425 BuchiCegarLoop]: ======== Iteration 14============ [2021-12-16 10:04:38,562 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3496 states and 4779 transitions. [2021-12-16 10:04:38,572 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3412 [2021-12-16 10:04:38,572 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:04:38,572 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:04:38,573 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:38,573 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:38,574 INFO L791 eck$LassoCheckResult]: Stem: 53372#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 53334#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 53209#L766 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 52933#L346 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 52934#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 52991#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 53285#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 52939#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 52940#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 53069#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 52972#L514 assume !(0 == ~M_E~0); 52973#L514-2 assume !(0 == ~T1_E~0); 53307#L519-1 assume !(0 == ~T2_E~0); 52923#L524-1 assume !(0 == ~T3_E~0); 52924#L529-1 assume !(0 == ~T4_E~0); 53045#L534-1 assume !(0 == ~E_M~0); 53253#L539-1 assume !(0 == ~E_1~0); 53254#L544-1 assume !(0 == ~E_2~0); 53281#L549-1 assume !(0 == ~E_3~0); 53282#L554-1 assume !(0 == ~E_4~0); 52919#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 52920#L250 assume !(1 == ~m_pc~0); 53151#L250-2 is_master_triggered_~__retres1~0#1 := 0; 53288#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 53108#L262 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 53109#L637 assume !(0 != activate_threads_~tmp~1#1); 52927#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 52928#L269 assume !(1 == ~t1_pc~0); 52958#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 53040#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 53064#L281 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 53065#L645 assume !(0 != activate_threads_~tmp___0~0#1); 53105#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 53106#L288 assume !(1 == ~t2_pc~0); 53099#L288-2 is_transmit2_triggered_~__retres1~2#1 := 0; 53100#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 53121#L300 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 53122#L653 assume !(0 != activate_threads_~tmp___1~0#1); 53247#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 53136#L307 assume !(1 == ~t3_pc~0); 53058#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 53059#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 53199#L319 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 53292#L661 assume !(0 != activate_threads_~tmp___2~0#1); 53077#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 53078#L326 assume !(1 == ~t4_pc~0); 52881#L326-2 is_transmit4_triggered_~__retres1~4#1 := 0; 52882#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 53134#L338 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 53252#L669 assume !(0 != activate_threads_~tmp___3~0#1); 53249#L669-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 53250#L572 assume !(1 == ~M_E~0); 53289#L572-2 assume !(1 == ~T1_E~0); 52935#L577-1 assume !(1 == ~T2_E~0); 52936#L582-1 assume !(1 == ~T3_E~0); 53235#L587-1 assume !(1 == ~T4_E~0); 53243#L592-1 assume !(1 == ~E_M~0); 52879#L597-1 assume !(1 == ~E_1~0); 52880#L602-1 assume !(1 == ~E_2~0); 53096#L607-1 assume !(1 == ~E_3~0); 53097#L612-1 assume !(1 == ~E_4~0); 53043#L617-1 assume { :end_inline_reset_delta_events } true; 53044#L803-2 [2021-12-16 10:04:38,574 INFO L793 eck$LassoCheckResult]: Loop: 53044#L803-2 assume !false; 54731#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 54730#L489 assume !false; 54729#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 54728#L386 assume !(0 == ~m_st~0); 54725#L390 assume !(0 == ~t1_st~0); 54726#L394 assume !(0 == ~t2_st~0); 54727#L398 assume !(0 == ~t3_st~0); 54723#L402 assume !(0 == ~t4_st~0);exists_runnable_thread_~__retres1~5#1 := 0; 54724#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 54719#L414 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 54720#L428 assume !(0 != eval_~tmp~0#1); 54896#L504 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 54895#L346-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 54894#L514-3 assume !(0 == ~M_E~0); 54893#L514-5 assume !(0 == ~T1_E~0); 54892#L519-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 54891#L524-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 54890#L529-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 54889#L534-3 assume 0 == ~E_M~0;~E_M~0 := 1; 54888#L539-3 assume !(0 == ~E_1~0); 54887#L544-3 assume 0 == ~E_2~0;~E_2~0 := 1; 54886#L549-3 assume 0 == ~E_3~0;~E_3~0 := 1; 54885#L554-3 assume !(0 == ~E_4~0); 54884#L559-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 54883#L250-18 assume !(1 == ~m_pc~0); 54882#L250-20 is_master_triggered_~__retres1~0#1 := 0; 54881#L261-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 54880#L262-6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 54879#L637-18 assume !(0 != activate_threads_~tmp~1#1); 54878#L637-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 54877#L269-18 assume !(1 == ~t1_pc~0); 54876#L269-20 is_transmit1_triggered_~__retres1~1#1 := 0; 54875#L280-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 54874#L281-6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 54873#L645-18 assume !(0 != activate_threads_~tmp___0~0#1); 54872#L645-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 54871#L288-18 assume !(1 == ~t2_pc~0); 54870#L288-20 is_transmit2_triggered_~__retres1~2#1 := 0; 54869#L299-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 54868#L300-6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 54867#L653-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 54866#L653-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 54865#L307-18 assume 1 == ~t3_pc~0; 54864#L308-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 54861#L318-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 54858#L319-6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 54855#L661-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 54852#L661-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 54849#L326-18 assume !(1 == ~t4_pc~0); 54845#L326-20 is_transmit4_triggered_~__retres1~4#1 := 0; 54842#L337-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 54839#L338-6 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 54836#L669-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 54833#L669-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 54830#L572-3 assume !(1 == ~M_E~0); 54228#L572-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 54825#L577-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 54822#L582-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 54819#L587-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 54816#L592-3 assume 1 == ~E_M~0;~E_M~0 := 2; 54813#L597-3 assume !(1 == ~E_1~0); 54809#L602-3 assume 1 == ~E_2~0;~E_2~0 := 2; 54805#L607-3 assume 1 == ~E_3~0;~E_3~0 := 2; 54800#L612-3 assume !(1 == ~E_4~0); 54795#L617-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 54790#L386-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 54783#L413-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 54779#L414-1 start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 54775#L822 assume !(0 == start_simulation_~tmp~3#1); 54769#L822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 54762#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 54759#L413-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 54756#L414-2 stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 54753#L777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 54748#L784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 54743#L785 start_simulation_#t~ret18#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 54740#L835 assume !(0 != start_simulation_~tmp___0~1#1); 53044#L803-2 [2021-12-16 10:04:38,574 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:38,574 INFO L85 PathProgramCache]: Analyzing trace with hash 1546408329, now seen corresponding path program 3 times [2021-12-16 10:04:38,575 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:38,575 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [662462454] [2021-12-16 10:04:38,575 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:38,575 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:38,581 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:04:38,581 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-16 10:04:38,586 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:04:38,593 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-16 10:04:38,593 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:38,593 INFO L85 PathProgramCache]: Analyzing trace with hash 2009722341, now seen corresponding path program 1 times [2021-12-16 10:04:38,593 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:38,594 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [493386522] [2021-12-16 10:04:38,594 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:38,594 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:38,600 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:04:38,613 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:04:38,614 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:04:38,614 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [493386522] [2021-12-16 10:04:38,614 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [493386522] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:04:38,614 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:04:38,614 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:04:38,615 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1195878040] [2021-12-16 10:04:38,615 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:04:38,615 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:04:38,615 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:04:38,616 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-16 10:04:38,616 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-16 10:04:38,616 INFO L87 Difference]: Start difference. First operand 3496 states and 4779 transitions. cyclomatic complexity: 1287 Second operand has 3 states, 3 states have (on average 26.0) internal successors, (78), 3 states have internal predecessors, (78), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:04:38,658 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:04:38,658 INFO L93 Difference]: Finished difference Result 5475 states and 7365 transitions. [2021-12-16 10:04:38,659 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-16 10:04:38,659 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5475 states and 7365 transitions. [2021-12-16 10:04:38,677 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 5389 [2021-12-16 10:04:38,689 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5475 states to 5475 states and 7365 transitions. [2021-12-16 10:04:38,690 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5475 [2021-12-16 10:04:38,694 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5475 [2021-12-16 10:04:38,694 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5475 states and 7365 transitions. [2021-12-16 10:04:38,699 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:04:38,699 INFO L681 BuchiCegarLoop]: Abstraction has 5475 states and 7365 transitions. [2021-12-16 10:04:38,701 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5475 states and 7365 transitions. [2021-12-16 10:04:38,743 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5475 to 5289. [2021-12-16 10:04:38,750 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5289 states, 5289 states have (on average 1.3475137076952164) internal successors, (7127), 5288 states have internal predecessors, (7127), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:04:38,759 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5289 states to 5289 states and 7127 transitions. [2021-12-16 10:04:38,759 INFO L704 BuchiCegarLoop]: Abstraction has 5289 states and 7127 transitions. [2021-12-16 10:04:38,759 INFO L587 BuchiCegarLoop]: Abstraction has 5289 states and 7127 transitions. [2021-12-16 10:04:38,759 INFO L425 BuchiCegarLoop]: ======== Iteration 15============ [2021-12-16 10:04:38,759 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5289 states and 7127 transitions. [2021-12-16 10:04:38,770 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 5203 [2021-12-16 10:04:38,770 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:04:38,770 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:04:38,771 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:38,771 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:38,771 INFO L791 eck$LassoCheckResult]: Stem: 62338#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 62313#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 62189#L766 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 61911#L346 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 61912#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 61970#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 62263#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 61917#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 61918#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 62047#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 61949#L514 assume !(0 == ~M_E~0); 61950#L514-2 assume !(0 == ~T1_E~0); 62285#L519-1 assume !(0 == ~T2_E~0); 61901#L524-1 assume !(0 == ~T3_E~0); 61902#L529-1 assume !(0 == ~T4_E~0); 62024#L534-1 assume !(0 == ~E_M~0); 62234#L539-1 assume !(0 == ~E_1~0); 62235#L544-1 assume !(0 == ~E_2~0); 62260#L549-1 assume !(0 == ~E_3~0); 62261#L554-1 assume !(0 == ~E_4~0); 61897#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 61898#L250 assume !(1 == ~m_pc~0); 62129#L250-2 is_master_triggered_~__retres1~0#1 := 0; 62266#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 62088#L262 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 62089#L637 assume !(0 != activate_threads_~tmp~1#1); 61905#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 61906#L269 assume !(1 == ~t1_pc~0); 61936#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 62019#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 62043#L281 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 62044#L645 assume !(0 != activate_threads_~tmp___0~0#1); 62085#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 62086#L288 assume !(1 == ~t2_pc~0); 62077#L288-2 is_transmit2_triggered_~__retres1~2#1 := 0; 62078#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 62099#L300 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 62100#L653 assume !(0 != activate_threads_~tmp___1~0#1); 62227#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 62113#L307 assume !(1 == ~t3_pc~0); 62037#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 62038#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 62175#L319 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 62271#L661 assume !(0 != activate_threads_~tmp___2~0#1); 62056#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 62057#L326 assume !(1 == ~t4_pc~0); 61858#L326-2 is_transmit4_triggered_~__retres1~4#1 := 0; 61859#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 62111#L338 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 62233#L669 assume !(0 != activate_threads_~tmp___3~0#1); 62230#L669-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 62231#L572 assume !(1 == ~M_E~0); 62267#L572-2 assume !(1 == ~T1_E~0); 61913#L577-1 assume !(1 == ~T2_E~0); 61914#L582-1 assume !(1 == ~T3_E~0); 62217#L587-1 assume !(1 == ~T4_E~0); 62223#L592-1 assume !(1 == ~E_M~0); 61856#L597-1 assume !(1 == ~E_1~0); 61857#L602-1 assume !(1 == ~E_2~0); 62074#L607-1 assume !(1 == ~E_3~0); 62075#L612-1 assume !(1 == ~E_4~0); 62022#L617-1 assume { :end_inline_reset_delta_events } true; 62023#L803-2 assume !false; 65901#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 65897#L489 [2021-12-16 10:04:38,771 INFO L793 eck$LassoCheckResult]: Loop: 65897#L489 assume !false; 65890#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 65885#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 65878#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 65879#L414 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 65801#L428 assume 0 != eval_~tmp~0#1; 65802#L428-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 65793#L436 assume !(0 != eval_~tmp_ndt_1~0#1); 65794#L433 assume !(0 == ~t1_st~0); 65482#L447 assume !(0 == ~t2_st~0); 62333#L461 assume !(0 == ~t3_st~0); 65905#L475 assume !(0 == ~t4_st~0); 65897#L489 [2021-12-16 10:04:38,771 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:38,772 INFO L85 PathProgramCache]: Analyzing trace with hash 39728939, now seen corresponding path program 1 times [2021-12-16 10:04:38,772 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:38,772 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [439858913] [2021-12-16 10:04:38,772 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:38,772 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:38,779 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:04:38,779 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-16 10:04:38,783 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:04:38,791 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-16 10:04:38,791 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:38,791 INFO L85 PathProgramCache]: Analyzing trace with hash 1577382650, now seen corresponding path program 1 times [2021-12-16 10:04:38,791 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:38,792 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2125738612] [2021-12-16 10:04:38,792 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:38,792 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:38,794 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:04:38,794 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-16 10:04:38,795 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:04:38,797 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-16 10:04:38,797 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:38,797 INFO L85 PathProgramCache]: Analyzing trace with hash 189250340, now seen corresponding path program 1 times [2021-12-16 10:04:38,797 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:38,797 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1549313407] [2021-12-16 10:04:38,798 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:38,798 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:38,803 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:04:38,817 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:04:38,817 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:04:38,818 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1549313407] [2021-12-16 10:04:38,818 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1549313407] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:04:38,818 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:04:38,818 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:04:38,818 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2136435515] [2021-12-16 10:04:38,818 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:04:38,891 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:04:38,892 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-16 10:04:38,892 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-16 10:04:38,892 INFO L87 Difference]: Start difference. First operand 5289 states and 7127 transitions. cyclomatic complexity: 1844 Second operand has 3 states, 3 states have (on average 25.333333333333332) internal successors, (76), 3 states have internal predecessors, (76), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:04:38,977 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:04:38,978 INFO L93 Difference]: Finished difference Result 8774 states and 11696 transitions. [2021-12-16 10:04:38,978 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-16 10:04:38,979 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8774 states and 11696 transitions. [2021-12-16 10:04:39,002 INFO L131 ngComponentsAnalysis]: Automaton has 11 accepting balls. 8386 [2021-12-16 10:04:39,019 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8774 states to 8774 states and 11696 transitions. [2021-12-16 10:04:39,019 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8774 [2021-12-16 10:04:39,023 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8774 [2021-12-16 10:04:39,023 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8774 states and 11696 transitions. [2021-12-16 10:04:39,030 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:04:39,030 INFO L681 BuchiCegarLoop]: Abstraction has 8774 states and 11696 transitions. [2021-12-16 10:04:39,033 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8774 states and 11696 transitions. [2021-12-16 10:04:39,117 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8774 to 8774. [2021-12-16 10:04:39,129 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8774 states, 8774 states have (on average 1.3330294050604057) internal successors, (11696), 8773 states have internal predecessors, (11696), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:04:39,146 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8774 states to 8774 states and 11696 transitions. [2021-12-16 10:04:39,147 INFO L704 BuchiCegarLoop]: Abstraction has 8774 states and 11696 transitions. [2021-12-16 10:04:39,147 INFO L587 BuchiCegarLoop]: Abstraction has 8774 states and 11696 transitions. [2021-12-16 10:04:39,147 INFO L425 BuchiCegarLoop]: ======== Iteration 16============ [2021-12-16 10:04:39,147 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 8774 states and 11696 transitions. [2021-12-16 10:04:39,165 INFO L131 ngComponentsAnalysis]: Automaton has 11 accepting balls. 8386 [2021-12-16 10:04:39,166 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:04:39,166 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:04:39,166 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:39,167 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:39,167 INFO L791 eck$LassoCheckResult]: Stem: 76399#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 76370#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 76246#L766 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 75982#L346 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 75983#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 76040#L353-2 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 76318#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 75988#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 75989#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 76117#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 76021#L514 assume !(0 == ~M_E~0); 76022#L514-2 assume !(0 == ~T1_E~0); 76342#L519-1 assume !(0 == ~T2_E~0); 75973#L524-1 assume !(0 == ~T3_E~0); 75974#L529-1 assume !(0 == ~T4_E~0); 76095#L534-1 assume !(0 == ~E_M~0); 76291#L539-1 assume !(0 == ~E_1~0); 76292#L544-1 assume !(0 == ~E_2~0); 76316#L549-1 assume !(0 == ~E_3~0); 76317#L554-1 assume !(0 == ~E_4~0); 75969#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 75970#L250 assume !(1 == ~m_pc~0); 76191#L250-2 is_master_triggered_~__retres1~0#1 := 0; 76323#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 76156#L262 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 76157#L637 assume !(0 != activate_threads_~tmp~1#1); 75975#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 75976#L269 assume !(1 == ~t1_pc~0); 76004#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 76090#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 76114#L281 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 76115#L645 assume !(0 != activate_threads_~tmp___0~0#1); 76153#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 76154#L288 assume !(1 == ~t2_pc~0); 76146#L288-2 is_transmit2_triggered_~__retres1~2#1 := 0; 76147#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 76167#L300 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 76168#L653 assume !(0 != activate_threads_~tmp___1~0#1); 76285#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 76180#L307 assume !(1 == ~t3_pc~0); 76108#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 76109#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 76230#L319 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 76328#L661 assume !(0 != activate_threads_~tmp___2~0#1); 76127#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 76128#L326 assume !(1 == ~t4_pc~0); 75930#L326-2 is_transmit4_triggered_~__retres1~4#1 := 0; 75931#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 76176#L338 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 76290#L669 assume !(0 != activate_threads_~tmp___3~0#1); 76287#L669-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 76288#L572 assume !(1 == ~M_E~0); 76324#L572-2 assume !(1 == ~T1_E~0); 75984#L577-1 assume !(1 == ~T2_E~0); 75985#L582-1 assume !(1 == ~T3_E~0); 76280#L587-1 assume !(1 == ~T4_E~0); 76281#L592-1 assume !(1 == ~E_M~0); 75921#L597-1 assume !(1 == ~E_1~0); 75922#L602-1 assume !(1 == ~E_2~0); 76143#L607-1 assume !(1 == ~E_3~0); 76144#L612-1 assume !(1 == ~E_4~0); 76903#L617-1 assume { :end_inline_reset_delta_events } true; 76902#L803-2 assume !false; 76876#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 76869#L489 [2021-12-16 10:04:39,167 INFO L793 eck$LassoCheckResult]: Loop: 76869#L489 assume !false; 76865#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 76859#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 76854#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 76850#L414 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 76846#L428 assume 0 != eval_~tmp~0#1; 76840#L428-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 76834#L436 assume !(0 != eval_~tmp_ndt_1~0#1); 76830#L433 assume !(0 == ~t1_st~0); 76831#L447 assume !(0 == ~t2_st~0); 76889#L461 assume !(0 == ~t3_st~0); 76880#L475 assume !(0 == ~t4_st~0); 76869#L489 [2021-12-16 10:04:39,167 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:39,168 INFO L85 PathProgramCache]: Analyzing trace with hash 600428717, now seen corresponding path program 1 times [2021-12-16 10:04:39,168 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:39,168 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2066977260] [2021-12-16 10:04:39,168 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:39,168 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:39,174 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:04:39,183 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:04:39,183 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:04:39,183 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2066977260] [2021-12-16 10:04:39,183 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2066977260] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:04:39,184 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:04:39,184 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:04:39,184 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [544048835] [2021-12-16 10:04:39,184 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:04:39,184 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:04:39,184 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:39,185 INFO L85 PathProgramCache]: Analyzing trace with hash 1577382650, now seen corresponding path program 2 times [2021-12-16 10:04:39,185 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:39,185 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [464673629] [2021-12-16 10:04:39,185 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:39,185 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:39,188 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:04:39,188 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-16 10:04:39,189 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:04:39,190 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-16 10:04:39,255 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:04:39,256 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-16 10:04:39,256 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-16 10:04:39,256 INFO L87 Difference]: Start difference. First operand 8774 states and 11696 transitions. cyclomatic complexity: 2933 Second operand has 3 states, 3 states have (on average 21.333333333333332) internal successors, (64), 3 states have internal predecessors, (64), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:04:39,281 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:04:39,282 INFO L93 Difference]: Finished difference Result 6733 states and 8982 transitions. [2021-12-16 10:04:39,282 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-16 10:04:39,283 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6733 states and 8982 transitions. [2021-12-16 10:04:39,302 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 6649 [2021-12-16 10:04:39,321 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6733 states to 6733 states and 8982 transitions. [2021-12-16 10:04:39,322 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6733 [2021-12-16 10:04:39,326 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6733 [2021-12-16 10:04:39,326 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6733 states and 8982 transitions. [2021-12-16 10:04:39,334 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:04:39,334 INFO L681 BuchiCegarLoop]: Abstraction has 6733 states and 8982 transitions. [2021-12-16 10:04:39,338 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6733 states and 8982 transitions. [2021-12-16 10:04:39,404 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6733 to 6733. [2021-12-16 10:04:39,413 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6733 states, 6733 states have (on average 1.3340264369523245) internal successors, (8982), 6732 states have internal predecessors, (8982), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:04:39,429 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6733 states to 6733 states and 8982 transitions. [2021-12-16 10:04:39,429 INFO L704 BuchiCegarLoop]: Abstraction has 6733 states and 8982 transitions. [2021-12-16 10:04:39,429 INFO L587 BuchiCegarLoop]: Abstraction has 6733 states and 8982 transitions. [2021-12-16 10:04:39,429 INFO L425 BuchiCegarLoop]: ======== Iteration 17============ [2021-12-16 10:04:39,430 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6733 states and 8982 transitions. [2021-12-16 10:04:39,443 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 6649 [2021-12-16 10:04:39,444 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:04:39,444 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:04:39,444 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:39,444 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:39,445 INFO L791 eck$LassoCheckResult]: Stem: 91903#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 91879#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 91764#L766 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 91496#L346 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 91497#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 91554#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 91834#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 91502#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 91503#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 91630#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 91534#L514 assume !(0 == ~M_E~0); 91535#L514-2 assume !(0 == ~T1_E~0); 91855#L519-1 assume !(0 == ~T2_E~0); 91487#L524-1 assume !(0 == ~T3_E~0); 91488#L529-1 assume !(0 == ~T4_E~0); 91608#L534-1 assume !(0 == ~E_M~0); 91807#L539-1 assume !(0 == ~E_1~0); 91808#L544-1 assume !(0 == ~E_2~0); 91832#L549-1 assume !(0 == ~E_3~0); 91833#L554-1 assume !(0 == ~E_4~0); 91483#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 91484#L250 assume !(1 == ~m_pc~0); 91708#L250-2 is_master_triggered_~__retres1~0#1 := 0; 91839#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 91669#L262 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 91670#L637 assume !(0 != activate_threads_~tmp~1#1); 91489#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 91490#L269 assume !(1 == ~t1_pc~0); 91518#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 91603#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 91627#L281 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 91628#L645 assume !(0 != activate_threads_~tmp___0~0#1); 91666#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 91667#L288 assume !(1 == ~t2_pc~0); 91659#L288-2 is_transmit2_triggered_~__retres1~2#1 := 0; 91660#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 91681#L300 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 91682#L653 assume !(0 != activate_threads_~tmp___1~0#1); 91802#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 91694#L307 assume !(1 == ~t3_pc~0); 91621#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 91622#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 91749#L319 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 91843#L661 assume !(0 != activate_threads_~tmp___2~0#1); 91640#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 91641#L326 assume !(1 == ~t4_pc~0); 91443#L326-2 is_transmit4_triggered_~__retres1~4#1 := 0; 91444#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 91690#L338 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 91806#L669 assume !(0 != activate_threads_~tmp___3~0#1); 91803#L669-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 91804#L572 assume !(1 == ~M_E~0); 91840#L572-2 assume !(1 == ~T1_E~0); 91498#L577-1 assume !(1 == ~T2_E~0); 91499#L582-1 assume !(1 == ~T3_E~0); 91790#L587-1 assume !(1 == ~T4_E~0); 91797#L592-1 assume !(1 == ~E_M~0); 91434#L597-1 assume !(1 == ~E_1~0); 91435#L602-1 assume !(1 == ~E_2~0); 91656#L607-1 assume !(1 == ~E_3~0); 91657#L612-1 assume !(1 == ~E_4~0); 91606#L617-1 assume { :end_inline_reset_delta_events } true; 91607#L803-2 assume !false; 92509#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 92507#L489 [2021-12-16 10:04:39,445 INFO L793 eck$LassoCheckResult]: Loop: 92507#L489 assume !false; 92505#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 92502#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 92500#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 92497#L414 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 92493#L428 assume 0 != eval_~tmp~0#1; 92488#L428-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 92474#L436 assume !(0 != eval_~tmp_ndt_1~0#1); 92475#L433 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 92257#L450 assume !(0 != eval_~tmp_ndt_2~0#1); 92255#L447 assume !(0 == ~t2_st~0); 92253#L461 assume !(0 == ~t3_st~0); 92513#L475 assume !(0 == ~t4_st~0); 92507#L489 [2021-12-16 10:04:39,445 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:39,445 INFO L85 PathProgramCache]: Analyzing trace with hash 39728939, now seen corresponding path program 2 times [2021-12-16 10:04:39,445 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:39,445 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [923752628] [2021-12-16 10:04:39,446 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:39,446 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:39,451 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:04:39,451 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-16 10:04:39,454 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:04:39,459 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-16 10:04:39,459 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:39,459 INFO L85 PathProgramCache]: Analyzing trace with hash 1507047706, now seen corresponding path program 1 times [2021-12-16 10:04:39,459 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:39,460 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2118064106] [2021-12-16 10:04:39,460 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:39,460 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:39,462 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:04:39,462 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-16 10:04:39,463 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:04:39,464 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-16 10:04:39,464 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:39,464 INFO L85 PathProgramCache]: Analyzing trace with hash 1424619056, now seen corresponding path program 1 times [2021-12-16 10:04:39,464 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:39,465 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [680919654] [2021-12-16 10:04:39,465 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:39,465 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:39,469 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:04:39,482 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:04:39,482 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:04:39,482 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [680919654] [2021-12-16 10:04:39,482 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [680919654] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:04:39,483 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:04:39,483 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:04:39,483 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1397746428] [2021-12-16 10:04:39,483 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:04:39,561 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:04:39,561 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-16 10:04:39,561 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-16 10:04:39,562 INFO L87 Difference]: Start difference. First operand 6733 states and 8982 transitions. cyclomatic complexity: 2255 Second operand has 3 states, 3 states have (on average 25.666666666666668) internal successors, (77), 3 states have internal predecessors, (77), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:04:39,616 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:04:39,617 INFO L93 Difference]: Finished difference Result 12148 states and 16135 transitions. [2021-12-16 10:04:39,617 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-16 10:04:39,617 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 12148 states and 16135 transitions. [2021-12-16 10:04:39,700 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 12056 [2021-12-16 10:04:39,721 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 12148 states to 12148 states and 16135 transitions. [2021-12-16 10:04:39,722 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 12148 [2021-12-16 10:04:39,730 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 12148 [2021-12-16 10:04:39,730 INFO L73 IsDeterministic]: Start isDeterministic. Operand 12148 states and 16135 transitions. [2021-12-16 10:04:39,740 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:04:39,740 INFO L681 BuchiCegarLoop]: Abstraction has 12148 states and 16135 transitions. [2021-12-16 10:04:39,746 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12148 states and 16135 transitions. [2021-12-16 10:04:39,819 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12148 to 11896. [2021-12-16 10:04:39,832 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 11896 states, 11896 states have (on average 1.3292703429724277) internal successors, (15813), 11895 states have internal predecessors, (15813), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:04:39,850 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11896 states to 11896 states and 15813 transitions. [2021-12-16 10:04:39,850 INFO L704 BuchiCegarLoop]: Abstraction has 11896 states and 15813 transitions. [2021-12-16 10:04:39,850 INFO L587 BuchiCegarLoop]: Abstraction has 11896 states and 15813 transitions. [2021-12-16 10:04:39,850 INFO L425 BuchiCegarLoop]: ======== Iteration 18============ [2021-12-16 10:04:39,850 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 11896 states and 15813 transitions. [2021-12-16 10:04:39,876 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 11804 [2021-12-16 10:04:39,876 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:04:39,876 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:04:39,877 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:39,877 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:39,877 INFO L791 eck$LassoCheckResult]: Stem: 110820#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 110784#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 110651#L766 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 110385#L346 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 110386#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 110442#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 110737#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 110391#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 110392#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 110519#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 110422#L514 assume !(0 == ~M_E~0); 110423#L514-2 assume !(0 == ~T1_E~0); 110759#L519-1 assume !(0 == ~T2_E~0); 110376#L524-1 assume !(0 == ~T3_E~0); 110377#L529-1 assume !(0 == ~T4_E~0); 110496#L534-1 assume !(0 == ~E_M~0); 110701#L539-1 assume !(0 == ~E_1~0); 110702#L544-1 assume !(0 == ~E_2~0); 110733#L549-1 assume !(0 == ~E_3~0); 110734#L554-1 assume !(0 == ~E_4~0); 110372#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 110373#L250 assume !(1 == ~m_pc~0); 110600#L250-2 is_master_triggered_~__retres1~0#1 := 0; 110740#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 110558#L262 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 110559#L637 assume !(0 != activate_threads_~tmp~1#1); 110379#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 110380#L269 assume !(1 == ~t1_pc~0); 110409#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 110491#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 110515#L281 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 110516#L645 assume !(0 != activate_threads_~tmp___0~0#1); 110555#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 110556#L288 assume !(1 == ~t2_pc~0); 110549#L288-2 is_transmit2_triggered_~__retres1~2#1 := 0; 110550#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 110569#L300 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 110570#L653 assume !(0 != activate_threads_~tmp___1~0#1); 110695#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 110583#L307 assume !(1 == ~t3_pc~0); 110509#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 110510#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 110642#L319 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 110744#L661 assume !(0 != activate_threads_~tmp___2~0#1); 110529#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 110530#L326 assume !(1 == ~t4_pc~0); 110332#L326-2 is_transmit4_triggered_~__retres1~4#1 := 0; 110333#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 110581#L338 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 110700#L669 assume !(0 != activate_threads_~tmp___3~0#1); 110697#L669-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 110698#L572 assume !(1 == ~M_E~0); 110741#L572-2 assume !(1 == ~T1_E~0); 110387#L577-1 assume !(1 == ~T2_E~0); 110388#L582-1 assume !(1 == ~T3_E~0); 110683#L587-1 assume !(1 == ~T4_E~0); 110691#L592-1 assume !(1 == ~E_M~0); 110330#L597-1 assume !(1 == ~E_1~0); 110331#L602-1 assume !(1 == ~E_2~0); 110546#L607-1 assume !(1 == ~E_3~0); 110547#L612-1 assume !(1 == ~E_4~0); 110494#L617-1 assume { :end_inline_reset_delta_events } true; 110495#L803-2 assume !false; 114315#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 114316#L489 [2021-12-16 10:04:39,877 INFO L793 eck$LassoCheckResult]: Loop: 114316#L489 assume !false; 114493#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 114490#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 114488#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 114306#L414 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 114307#L428 assume 0 != eval_~tmp~0#1; 114298#L428-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 114295#L436 assume !(0 != eval_~tmp_ndt_1~0#1); 114296#L433 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 114288#L450 assume !(0 != eval_~tmp_ndt_2~0#1); 114289#L447 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 114474#L464 assume !(0 != eval_~tmp_ndt_3~0#1); 114505#L461 assume !(0 == ~t3_st~0); 114499#L475 assume !(0 == ~t4_st~0); 114316#L489 [2021-12-16 10:04:39,878 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:39,878 INFO L85 PathProgramCache]: Analyzing trace with hash 39728939, now seen corresponding path program 3 times [2021-12-16 10:04:39,878 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:39,878 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1305366905] [2021-12-16 10:04:39,878 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:39,878 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:39,886 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:04:39,886 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-16 10:04:39,890 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:04:39,898 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-16 10:04:39,899 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:39,899 INFO L85 PathProgramCache]: Analyzing trace with hash -530907670, now seen corresponding path program 1 times [2021-12-16 10:04:39,899 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:39,899 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1736369175] [2021-12-16 10:04:39,899 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:39,899 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:39,902 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:04:39,902 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-16 10:04:39,903 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:04:39,904 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-16 10:04:39,905 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:39,905 INFO L85 PathProgramCache]: Analyzing trace with hash 1208771476, now seen corresponding path program 1 times [2021-12-16 10:04:39,905 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:39,905 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [714975531] [2021-12-16 10:04:39,905 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:39,905 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:39,912 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:04:39,926 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:04:39,926 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:04:39,926 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [714975531] [2021-12-16 10:04:39,926 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [714975531] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:04:39,926 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:04:39,926 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:04:39,926 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [187189004] [2021-12-16 10:04:39,927 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:04:40,017 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:04:40,017 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-16 10:04:40,017 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-16 10:04:40,018 INFO L87 Difference]: Start difference. First operand 11896 states and 15813 transitions. cyclomatic complexity: 3923 Second operand has 3 states, 3 states have (on average 26.0) internal successors, (78), 3 states have internal predecessors, (78), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:04:40,101 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:04:40,102 INFO L93 Difference]: Finished difference Result 21228 states and 28121 transitions. [2021-12-16 10:04:40,102 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-16 10:04:40,102 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 21228 states and 28121 transitions. [2021-12-16 10:04:40,182 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 21110 [2021-12-16 10:04:40,253 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 21228 states to 21228 states and 28121 transitions. [2021-12-16 10:04:40,253 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 21228 [2021-12-16 10:04:40,272 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 21228 [2021-12-16 10:04:40,272 INFO L73 IsDeterministic]: Start isDeterministic. Operand 21228 states and 28121 transitions. [2021-12-16 10:04:40,292 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:04:40,293 INFO L681 BuchiCegarLoop]: Abstraction has 21228 states and 28121 transitions. [2021-12-16 10:04:40,308 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21228 states and 28121 transitions. [2021-12-16 10:04:40,555 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21228 to 20568. [2021-12-16 10:04:40,578 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 20568 states, 20568 states have (on average 1.3263807856865033) internal successors, (27281), 20567 states have internal predecessors, (27281), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:04:40,611 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20568 states to 20568 states and 27281 transitions. [2021-12-16 10:04:40,611 INFO L704 BuchiCegarLoop]: Abstraction has 20568 states and 27281 transitions. [2021-12-16 10:04:40,611 INFO L587 BuchiCegarLoop]: Abstraction has 20568 states and 27281 transitions. [2021-12-16 10:04:40,611 INFO L425 BuchiCegarLoop]: ======== Iteration 19============ [2021-12-16 10:04:40,611 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 20568 states and 27281 transitions. [2021-12-16 10:04:40,662 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 20450 [2021-12-16 10:04:40,663 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:04:40,663 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:04:40,663 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:40,663 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:40,664 INFO L791 eck$LassoCheckResult]: Stem: 143986#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 143935#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 143803#L766 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 143516#L346 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 143517#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 143573#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 143885#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 143522#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 143523#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 143654#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 143554#L514 assume !(0 == ~M_E~0); 143555#L514-2 assume !(0 == ~T1_E~0); 143907#L519-1 assume !(0 == ~T2_E~0); 143506#L524-1 assume !(0 == ~T3_E~0); 143507#L529-1 assume !(0 == ~T4_E~0); 143631#L534-1 assume !(0 == ~E_M~0); 143852#L539-1 assume !(0 == ~E_1~0); 143853#L544-1 assume !(0 == ~E_2~0); 143881#L549-1 assume !(0 == ~E_3~0); 143882#L554-1 assume !(0 == ~E_4~0); 143502#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 143503#L250 assume !(1 == ~m_pc~0); 143738#L250-2 is_master_triggered_~__retres1~0#1 := 0; 143888#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 143694#L262 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 143695#L637 assume !(0 != activate_threads_~tmp~1#1); 143510#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 143511#L269 assume !(1 == ~t1_pc~0); 143540#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 143626#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 143650#L281 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 143651#L645 assume !(0 != activate_threads_~tmp___0~0#1); 143691#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 143692#L288 assume !(1 == ~t2_pc~0); 143686#L288-2 is_transmit2_triggered_~__retres1~2#1 := 0; 143687#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 143708#L300 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 143709#L653 assume !(0 != activate_threads_~tmp___1~0#1); 143846#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 143722#L307 assume !(1 == ~t3_pc~0); 143644#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 143645#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 143790#L319 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 143893#L661 assume !(0 != activate_threads_~tmp___2~0#1); 143663#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 143664#L326 assume !(1 == ~t4_pc~0); 143462#L326-2 is_transmit4_triggered_~__retres1~4#1 := 0; 143463#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 143720#L338 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 143851#L669 assume !(0 != activate_threads_~tmp___3~0#1); 143848#L669-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 143849#L572 assume !(1 == ~M_E~0); 143889#L572-2 assume !(1 == ~T1_E~0); 143518#L577-1 assume !(1 == ~T2_E~0); 143519#L582-1 assume !(1 == ~T3_E~0); 143836#L587-1 assume !(1 == ~T4_E~0); 143842#L592-1 assume !(1 == ~E_M~0); 143460#L597-1 assume !(1 == ~E_1~0); 143461#L602-1 assume !(1 == ~E_2~0); 143683#L607-1 assume !(1 == ~E_3~0); 143684#L612-1 assume !(1 == ~E_4~0); 143629#L617-1 assume { :end_inline_reset_delta_events } true; 143630#L803-2 assume !false; 150018#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 150016#L489 [2021-12-16 10:04:40,664 INFO L793 eck$LassoCheckResult]: Loop: 150016#L489 assume !false; 150014#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 150012#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 150008#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 150009#L414 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 149945#L428 assume 0 != eval_~tmp~0#1; 149946#L428-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 150050#L436 assume !(0 != eval_~tmp_ndt_1~0#1); 150047#L433 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 150043#L450 assume !(0 != eval_~tmp_ndt_2~0#1); 150040#L447 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 150035#L464 assume !(0 != eval_~tmp_ndt_3~0#1); 150030#L461 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 149256#L478 assume !(0 != eval_~tmp_ndt_4~0#1); 150022#L475 assume !(0 == ~t4_st~0); 150016#L489 [2021-12-16 10:04:40,664 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:40,664 INFO L85 PathProgramCache]: Analyzing trace with hash 39728939, now seen corresponding path program 4 times [2021-12-16 10:04:40,664 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:40,665 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1633522616] [2021-12-16 10:04:40,665 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:40,665 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:40,672 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:04:40,672 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-16 10:04:40,676 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:04:40,686 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-16 10:04:40,687 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:40,687 INFO L85 PathProgramCache]: Analyzing trace with hash 721579562, now seen corresponding path program 1 times [2021-12-16 10:04:40,687 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:40,687 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1241112260] [2021-12-16 10:04:40,687 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:40,687 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:40,690 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:04:40,691 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-16 10:04:40,692 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:04:40,694 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-16 10:04:40,694 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:40,694 INFO L85 PathProgramCache]: Analyzing trace with hash -1182941760, now seen corresponding path program 1 times [2021-12-16 10:04:40,694 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:40,694 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [18342263] [2021-12-16 10:04:40,695 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:40,695 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:40,703 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:04:40,718 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:04:40,719 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:04:40,719 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [18342263] [2021-12-16 10:04:40,719 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [18342263] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:04:40,719 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:04:40,719 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-16 10:04:40,719 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [533266464] [2021-12-16 10:04:40,719 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:04:40,961 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:04:40,961 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-16 10:04:40,961 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-16 10:04:40,961 INFO L87 Difference]: Start difference. First operand 20568 states and 27281 transitions. cyclomatic complexity: 6719 Second operand has 3 states, 2 states have (on average 39.5) internal successors, (79), 3 states have internal predecessors, (79), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:04:41,070 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:04:41,071 INFO L93 Difference]: Finished difference Result 35436 states and 46915 transitions. [2021-12-16 10:04:41,071 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-16 10:04:41,072 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 35436 states and 46915 transitions. [2021-12-16 10:04:41,210 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 35266 [2021-12-16 10:04:41,458 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 35436 states to 35436 states and 46915 transitions. [2021-12-16 10:04:41,458 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 35436 [2021-12-16 10:04:41,495 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 35436 [2021-12-16 10:04:41,495 INFO L73 IsDeterministic]: Start isDeterministic. Operand 35436 states and 46915 transitions. [2021-12-16 10:04:41,512 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:04:41,513 INFO L681 BuchiCegarLoop]: Abstraction has 35436 states and 46915 transitions. [2021-12-16 10:04:41,524 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 35436 states and 46915 transitions. [2021-12-16 10:04:41,878 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 35436 to 34956. [2021-12-16 10:04:41,920 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 34956 states, 34956 states have (on average 1.3283842544913607) internal successors, (46435), 34955 states have internal predecessors, (46435), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:04:41,987 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 34956 states to 34956 states and 46435 transitions. [2021-12-16 10:04:41,988 INFO L704 BuchiCegarLoop]: Abstraction has 34956 states and 46435 transitions. [2021-12-16 10:04:41,988 INFO L587 BuchiCegarLoop]: Abstraction has 34956 states and 46435 transitions. [2021-12-16 10:04:41,988 INFO L425 BuchiCegarLoop]: ======== Iteration 20============ [2021-12-16 10:04:41,988 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 34956 states and 46435 transitions. [2021-12-16 10:04:42,082 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 34786 [2021-12-16 10:04:42,082 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:04:42,082 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:04:42,082 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:42,083 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:42,083 INFO L791 eck$LassoCheckResult]: Stem: 200007#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 199950#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 199802#L766 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 199528#L346 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 199529#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 199583#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 199886#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 199534#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 199535#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 199662#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 199565#L514 assume !(0 == ~M_E~0); 199566#L514-2 assume !(0 == ~T1_E~0); 199917#L519-1 assume !(0 == ~T2_E~0); 199519#L524-1 assume !(0 == ~T3_E~0); 199520#L529-1 assume !(0 == ~T4_E~0); 199639#L534-1 assume !(0 == ~E_M~0); 199854#L539-1 assume !(0 == ~E_1~0); 199855#L544-1 assume !(0 == ~E_2~0); 199884#L549-1 assume !(0 == ~E_3~0); 199885#L554-1 assume !(0 == ~E_4~0); 199515#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 199516#L250 assume !(1 == ~m_pc~0); 199742#L250-2 is_master_triggered_~__retres1~0#1 := 0; 199891#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 199703#L262 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 199704#L637 assume !(0 != activate_threads_~tmp~1#1); 199522#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 199523#L269 assume !(1 == ~t1_pc~0); 199549#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 199634#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 199659#L281 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 199660#L645 assume !(0 != activate_threads_~tmp___0~0#1); 199700#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 199701#L288 assume !(1 == ~t2_pc~0); 199695#L288-2 is_transmit2_triggered_~__retres1~2#1 := 0; 199696#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 199715#L300 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 199716#L653 assume !(0 != activate_threads_~tmp___1~0#1); 199846#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 199728#L307 assume !(1 == ~t3_pc~0); 199653#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 199654#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 199791#L319 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 199898#L661 assume !(0 != activate_threads_~tmp___2~0#1); 199672#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 199673#L326 assume !(1 == ~t4_pc~0); 199475#L326-2 is_transmit4_triggered_~__retres1~4#1 := 0; 199476#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 199727#L338 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 199853#L669 assume !(0 != activate_threads_~tmp___3~0#1); 199850#L669-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 199851#L572 assume !(1 == ~M_E~0); 199892#L572-2 assume !(1 == ~T1_E~0); 199530#L577-1 assume !(1 == ~T2_E~0); 199531#L582-1 assume !(1 == ~T3_E~0); 199834#L587-1 assume !(1 == ~T4_E~0); 199841#L592-1 assume !(1 == ~E_M~0); 199467#L597-1 assume !(1 == ~E_1~0); 199468#L602-1 assume !(1 == ~E_2~0); 199692#L607-1 assume !(1 == ~E_3~0); 199693#L612-1 assume !(1 == ~E_4~0); 199637#L617-1 assume { :end_inline_reset_delta_events } true; 199638#L803-2 assume !false; 208622#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 208620#L489 [2021-12-16 10:04:42,083 INFO L793 eck$LassoCheckResult]: Loop: 208620#L489 assume !false; 208618#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 208614#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 208611#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 208608#L414 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 208605#L428 assume 0 != eval_~tmp~0#1; 208600#L428-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 208596#L436 assume !(0 != eval_~tmp_ndt_1~0#1); 208594#L433 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 208589#L450 assume !(0 != eval_~tmp_ndt_2~0#1); 208590#L447 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 208861#L464 assume !(0 != eval_~tmp_ndt_3~0#1); 208862#L461 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 209415#L478 assume !(0 != eval_~tmp_ndt_4~0#1); 208626#L475 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0#1;eval_~tmp_ndt_5~0#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 208623#L492 assume !(0 != eval_~tmp_ndt_5~0#1); 208620#L489 [2021-12-16 10:04:42,083 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:42,083 INFO L85 PathProgramCache]: Analyzing trace with hash 39728939, now seen corresponding path program 5 times [2021-12-16 10:04:42,084 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:42,084 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [9266258] [2021-12-16 10:04:42,084 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:42,084 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:42,093 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:04:42,093 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-16 10:04:42,098 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:04:42,104 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-16 10:04:42,105 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:42,105 INFO L85 PathProgramCache]: Analyzing trace with hash 894126298, now seen corresponding path program 1 times [2021-12-16 10:04:42,105 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:42,105 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [558187323] [2021-12-16 10:04:42,105 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:42,105 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:42,109 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:04:42,109 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-16 10:04:42,110 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:04:42,111 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-16 10:04:42,112 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:42,112 INFO L85 PathProgramCache]: Analyzing trace with hash 1983507460, now seen corresponding path program 1 times [2021-12-16 10:04:42,112 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:42,112 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [481769989] [2021-12-16 10:04:42,112 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:42,112 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:42,117 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:04:42,118 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-16 10:04:42,121 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:04:42,129 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-16 10:04:43,380 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 16.12 10:04:43 BoogieIcfgContainer [2021-12-16 10:04:43,380 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2021-12-16 10:04:43,381 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2021-12-16 10:04:43,381 INFO L271 PluginConnector]: Initializing Witness Printer... [2021-12-16 10:04:43,381 INFO L275 PluginConnector]: Witness Printer initialized [2021-12-16 10:04:43,381 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 16.12 10:04:35" (3/4) ... [2021-12-16 10:04:43,383 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2021-12-16 10:04:43,410 INFO L141 WitnessManager]: Wrote witness to /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/witness.graphml [2021-12-16 10:04:43,411 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2021-12-16 10:04:43,411 INFO L158 Benchmark]: Toolchain (without parser) took 9353.46ms. Allocated memory was 125.8MB in the beginning and 872.4MB in the end (delta: 746.6MB). Free memory was 97.6MB in the beginning and 460.6MB in the end (delta: -363.0MB). Peak memory consumption was 382.3MB. Max. memory is 16.1GB. [2021-12-16 10:04:43,411 INFO L158 Benchmark]: CDTParser took 0.14ms. Allocated memory is still 125.8MB. Free memory is still 80.3MB. There was no memory consumed. Max. memory is 16.1GB. [2021-12-16 10:04:43,411 INFO L158 Benchmark]: CACSL2BoogieTranslator took 240.99ms. Allocated memory is still 125.8MB. Free memory was 97.3MB in the beginning and 94.1MB in the end (delta: 3.2MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2021-12-16 10:04:43,412 INFO L158 Benchmark]: Boogie Procedure Inliner took 66.35ms. Allocated memory is still 125.8MB. Free memory was 94.1MB in the beginning and 89.7MB in the end (delta: 4.4MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2021-12-16 10:04:43,412 INFO L158 Benchmark]: Boogie Preprocessor took 36.73ms. Allocated memory is still 125.8MB. Free memory was 89.7MB in the beginning and 86.1MB in the end (delta: 3.6MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2021-12-16 10:04:43,412 INFO L158 Benchmark]: RCFGBuilder took 810.69ms. Allocated memory was 125.8MB in the beginning and 178.3MB in the end (delta: 52.4MB). Free memory was 86.1MB in the beginning and 137.6MB in the end (delta: -51.5MB). Peak memory consumption was 36.9MB. Max. memory is 16.1GB. [2021-12-16 10:04:43,412 INFO L158 Benchmark]: BuchiAutomizer took 8156.33ms. Allocated memory was 178.3MB in the beginning and 872.4MB in the end (delta: 694.2MB). Free memory was 136.7MB in the beginning and 464.8MB in the end (delta: -328.1MB). Peak memory consumption was 372.0MB. Max. memory is 16.1GB. [2021-12-16 10:04:43,413 INFO L158 Benchmark]: Witness Printer took 29.86ms. Allocated memory is still 872.4MB. Free memory was 464.8MB in the beginning and 460.6MB in the end (delta: 4.2MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2021-12-16 10:04:43,414 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.14ms. Allocated memory is still 125.8MB. Free memory is still 80.3MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 240.99ms. Allocated memory is still 125.8MB. Free memory was 97.3MB in the beginning and 94.1MB in the end (delta: 3.2MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 66.35ms. Allocated memory is still 125.8MB. Free memory was 94.1MB in the beginning and 89.7MB in the end (delta: 4.4MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * Boogie Preprocessor took 36.73ms. Allocated memory is still 125.8MB. Free memory was 89.7MB in the beginning and 86.1MB in the end (delta: 3.6MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * RCFGBuilder took 810.69ms. Allocated memory was 125.8MB in the beginning and 178.3MB in the end (delta: 52.4MB). Free memory was 86.1MB in the beginning and 137.6MB in the end (delta: -51.5MB). Peak memory consumption was 36.9MB. Max. memory is 16.1GB. * BuchiAutomizer took 8156.33ms. Allocated memory was 178.3MB in the beginning and 872.4MB in the end (delta: 694.2MB). Free memory was 136.7MB in the beginning and 464.8MB in the end (delta: -328.1MB). Peak memory consumption was 372.0MB. Max. memory is 16.1GB. * Witness Printer took 29.86ms. Allocated memory is still 872.4MB. Free memory was 464.8MB in the beginning and 460.6MB in the end (delta: 4.2MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 19 terminating modules (19 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.19 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 34956 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 8.1s and 20 iterations. TraceHistogramMax:1. Analysis of lassos took 3.2s. Construction of modules took 0.3s. Büchi inclusion checks took 0.9s. Highest rank in rank-based complementation 0. Minimization of det autom 19. Minimization of nondet autom 0. Automata minimization 1.8s AutomataMinimizationTime, 19 MinimizatonAttempts, 11187 StatesRemovedByMinimization, 10 NontrivialMinimizations. Non-live state removal took 1.1s Buchi closure took 0.1s. Biggest automaton had 34956 states and ocurred in iteration 19. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 14555 SdHoareTripleChecker+Valid, 0.5s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 14555 mSDsluCounter, 24708 SdHoareTripleChecker+Invalid, 0.4s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 12051 mSDsCounter, 240 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 511 IncrementalHoareTripleChecker+Invalid, 751 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 240 mSolverCounterUnsat, 12657 mSDtfsCounter, 511 mSolverCounterSat, 0.1s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI3 SFLT0 conc4 concLT0 SILN1 SILU0 SILI11 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - FixpointNonTerminationResult [Line: 423]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite execution State at position 0 is {NULL=1} State at position 1 is {tmp_ndt_3=0, NULL=0, t3_st=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@45c17f5f=0, token=0, NULL=1, tmp=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@110e4d8f=0, t2_st=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@746f3be9=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@28927b0b=0, tmp_ndt_2=0, t4_i=1, \result=0, E_3=2, t4_pc=0, E_1=2, tmp_ndt_1=0, __retres1=1, tmp=1, \result=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@51be00a9=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@5b08c666=0, m_st=0, NULL=0, t3_pc=0, tmp___3=0, __retres1=0, tmp___0=0, __retres1=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@4d4539ae=0, tmp___2=0, m_pc=0, \result=0, \result=1, \result=0, \result=0, tmp___1=0, __retres1=0, T2_E=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@3bed8d51=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@26187552=0, tmp=0, t1_pc=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@48ceed6c=0, E_2=2, tmp___0=0, E_4=2, T1_E=2, __retres1=0, M_E=2, t2_i=1, T4_E=2, \result=0, t3_i=1, t4_st=0, m_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@5117fcfa=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@2e9b57a2=0, t1_st=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@489df7a8=0, __retres1=0, local=0, t2_pc=0, tmp_ndt_5=0, __retres1=0, tmp_ndt_4=0, E_M=2, kernel_st=1, T3_E=2, t1_i=1} - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 423]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L24] int m_pc = 0; [L25] int t1_pc = 0; [L26] int t2_pc = 0; [L27] int t3_pc = 0; [L28] int t4_pc = 0; [L29] int m_st ; [L30] int t1_st ; [L31] int t2_st ; [L32] int t3_st ; [L33] int t4_st ; [L34] int m_i ; [L35] int t1_i ; [L36] int t2_i ; [L37] int t3_i ; [L38] int t4_i ; [L39] int M_E = 2; [L40] int T1_E = 2; [L41] int T2_E = 2; [L42] int T3_E = 2; [L43] int T4_E = 2; [L44] int E_M = 2; [L45] int E_1 = 2; [L46] int E_2 = 2; [L47] int E_3 = 2; [L48] int E_4 = 2; [L55] int token ; [L57] int local ; [L848] int __retres1 ; [L852] CALL init_model() [L760] m_i = 1 [L761] t1_i = 1 [L762] t2_i = 1 [L763] t3_i = 1 [L764] t4_i = 1 [L852] RET init_model() [L853] CALL start_simulation() [L789] int kernel_st ; [L790] int tmp ; [L791] int tmp___0 ; [L795] kernel_st = 0 [L796] FCALL update_channels() [L797] CALL init_threads() [L353] COND TRUE m_i == 1 [L354] m_st = 0 [L358] COND TRUE t1_i == 1 [L359] t1_st = 0 [L363] COND TRUE t2_i == 1 [L364] t2_st = 0 [L368] COND TRUE t3_i == 1 [L369] t3_st = 0 [L373] COND TRUE t4_i == 1 [L374] t4_st = 0 [L797] RET init_threads() [L798] CALL fire_delta_events() [L514] COND FALSE !(M_E == 0) [L519] COND FALSE !(T1_E == 0) [L524] COND FALSE !(T2_E == 0) [L529] COND FALSE !(T3_E == 0) [L534] COND FALSE !(T4_E == 0) [L539] COND FALSE !(E_M == 0) [L544] COND FALSE !(E_1 == 0) [L549] COND FALSE !(E_2 == 0) [L554] COND FALSE !(E_3 == 0) [L559] COND FALSE !(E_4 == 0) [L798] RET fire_delta_events() [L799] CALL activate_threads() [L627] int tmp ; [L628] int tmp___0 ; [L629] int tmp___1 ; [L630] int tmp___2 ; [L631] int tmp___3 ; [L635] CALL, EXPR is_master_triggered() [L247] int __retres1 ; [L250] COND FALSE !(m_pc == 1) [L260] __retres1 = 0 [L262] return (__retres1); [L635] RET, EXPR is_master_triggered() [L635] tmp = is_master_triggered() [L637] COND FALSE !(\read(tmp)) [L643] CALL, EXPR is_transmit1_triggered() [L266] int __retres1 ; [L269] COND FALSE !(t1_pc == 1) [L279] __retres1 = 0 [L281] return (__retres1); [L643] RET, EXPR is_transmit1_triggered() [L643] tmp___0 = is_transmit1_triggered() [L645] COND FALSE !(\read(tmp___0)) [L651] CALL, EXPR is_transmit2_triggered() [L285] int __retres1 ; [L288] COND FALSE !(t2_pc == 1) [L298] __retres1 = 0 [L300] return (__retres1); [L651] RET, EXPR is_transmit2_triggered() [L651] tmp___1 = is_transmit2_triggered() [L653] COND FALSE !(\read(tmp___1)) [L659] CALL, EXPR is_transmit3_triggered() [L304] int __retres1 ; [L307] COND FALSE !(t3_pc == 1) [L317] __retres1 = 0 [L319] return (__retres1); [L659] RET, EXPR is_transmit3_triggered() [L659] tmp___2 = is_transmit3_triggered() [L661] COND FALSE !(\read(tmp___2)) [L667] CALL, EXPR is_transmit4_triggered() [L323] int __retres1 ; [L326] COND FALSE !(t4_pc == 1) [L336] __retres1 = 0 [L338] return (__retres1); [L667] RET, EXPR is_transmit4_triggered() [L667] tmp___3 = is_transmit4_triggered() [L669] COND FALSE !(\read(tmp___3)) [L799] RET activate_threads() [L800] CALL reset_delta_events() [L572] COND FALSE !(M_E == 1) [L577] COND FALSE !(T1_E == 1) [L582] COND FALSE !(T2_E == 1) [L587] COND FALSE !(T3_E == 1) [L592] COND FALSE !(T4_E == 1) [L597] COND FALSE !(E_M == 1) [L602] COND FALSE !(E_1 == 1) [L607] COND FALSE !(E_2 == 1) [L612] COND FALSE !(E_3 == 1) [L617] COND FALSE !(E_4 == 1) [L800] RET reset_delta_events() [L803] COND TRUE 1 [L806] kernel_st = 1 [L807] CALL eval() [L419] int tmp ; Loop: [L423] COND TRUE 1 [L426] CALL, EXPR exists_runnable_thread() [L383] int __retres1 ; [L386] COND TRUE m_st == 0 [L387] __retres1 = 1 [L414] return (__retres1); [L426] RET, EXPR exists_runnable_thread() [L426] tmp = exists_runnable_thread() [L428] COND TRUE \read(tmp) [L433] COND TRUE m_st == 0 [L434] int tmp_ndt_1; [L435] tmp_ndt_1 = __VERIFIER_nondet_int() [L436] COND FALSE !(\read(tmp_ndt_1)) [L447] COND TRUE t1_st == 0 [L448] int tmp_ndt_2; [L449] tmp_ndt_2 = __VERIFIER_nondet_int() [L450] COND FALSE !(\read(tmp_ndt_2)) [L461] COND TRUE t2_st == 0 [L462] int tmp_ndt_3; [L463] tmp_ndt_3 = __VERIFIER_nondet_int() [L464] COND FALSE !(\read(tmp_ndt_3)) [L475] COND TRUE t3_st == 0 [L476] int tmp_ndt_4; [L477] tmp_ndt_4 = __VERIFIER_nondet_int() [L478] COND FALSE !(\read(tmp_ndt_4)) [L489] COND TRUE t4_st == 0 [L490] int tmp_ndt_5; [L491] tmp_ndt_5 = __VERIFIER_nondet_int() [L492] COND FALSE !(\read(tmp_ndt_5)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2021-12-16 10:04:43,448 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Ended with exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)