./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/token_ring.04.cil-2.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version c3fed411 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/token_ring.04.cil-2.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 05d3b7d21cc48825b4a0189c75f03d768acc6241312029d3e223c1b9b2a509ea --- Real Ultimate output --- This is Ultimate 0.2.2-tmp.no-commuhash-c3fed41 [2021-12-16 10:04:33,330 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-12-16 10:04:33,353 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-12-16 10:04:33,390 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-12-16 10:04:33,392 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-12-16 10:04:33,394 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-12-16 10:04:33,395 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-12-16 10:04:33,398 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-12-16 10:04:33,399 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-12-16 10:04:33,400 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-12-16 10:04:33,400 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-12-16 10:04:33,401 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-12-16 10:04:33,401 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-12-16 10:04:33,403 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-12-16 10:04:33,405 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-12-16 10:04:33,406 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-12-16 10:04:33,409 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-12-16 10:04:33,412 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-12-16 10:04:33,413 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-12-16 10:04:33,419 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-12-16 10:04:33,420 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-12-16 10:04:33,424 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-12-16 10:04:33,425 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-12-16 10:04:33,426 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-12-16 10:04:33,428 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-12-16 10:04:33,430 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-12-16 10:04:33,431 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-12-16 10:04:33,431 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-12-16 10:04:33,432 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-12-16 10:04:33,433 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-12-16 10:04:33,434 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-12-16 10:04:33,434 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-12-16 10:04:33,435 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-12-16 10:04:33,436 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-12-16 10:04:33,437 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-12-16 10:04:33,437 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-12-16 10:04:33,438 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-12-16 10:04:33,438 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-12-16 10:04:33,438 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-12-16 10:04:33,439 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-12-16 10:04:33,439 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-12-16 10:04:33,440 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2021-12-16 10:04:33,463 INFO L113 SettingsManager]: Loading preferences was successful [2021-12-16 10:04:33,463 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-12-16 10:04:33,463 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2021-12-16 10:04:33,463 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2021-12-16 10:04:33,464 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-12-16 10:04:33,464 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-12-16 10:04:33,465 INFO L138 SettingsManager]: * Use SBE=true [2021-12-16 10:04:33,465 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2021-12-16 10:04:33,465 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2021-12-16 10:04:33,465 INFO L138 SettingsManager]: * Use old map elimination=false [2021-12-16 10:04:33,466 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2021-12-16 10:04:33,466 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2021-12-16 10:04:33,466 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2021-12-16 10:04:33,466 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-12-16 10:04:33,466 INFO L138 SettingsManager]: * sizeof long=4 [2021-12-16 10:04:33,466 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2021-12-16 10:04:33,467 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-12-16 10:04:33,467 INFO L138 SettingsManager]: * sizeof POINTER=4 [2021-12-16 10:04:33,467 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-12-16 10:04:33,467 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2021-12-16 10:04:33,467 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2021-12-16 10:04:33,467 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2021-12-16 10:04:33,467 INFO L138 SettingsManager]: * sizeof long double=12 [2021-12-16 10:04:33,468 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-12-16 10:04:33,469 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2021-12-16 10:04:33,469 INFO L138 SettingsManager]: * Use constant arrays=true [2021-12-16 10:04:33,469 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2021-12-16 10:04:33,469 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-12-16 10:04:33,469 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-12-16 10:04:33,470 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-12-16 10:04:33,470 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-12-16 10:04:33,470 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2021-12-16 10:04:33,471 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2021-12-16 10:04:33,471 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 05d3b7d21cc48825b4a0189c75f03d768acc6241312029d3e223c1b9b2a509ea [2021-12-16 10:04:33,673 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-12-16 10:04:33,693 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-12-16 10:04:33,695 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-12-16 10:04:33,696 INFO L271 PluginConnector]: Initializing CDTParser... [2021-12-16 10:04:33,696 INFO L275 PluginConnector]: CDTParser initialized [2021-12-16 10:04:33,697 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/token_ring.04.cil-2.c [2021-12-16 10:04:33,763 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/6f146300d/ebcd43af12c24b498c6ec8a0e7207909/FLAGdc63b88ee [2021-12-16 10:04:34,123 INFO L306 CDTParser]: Found 1 translation units. [2021-12-16 10:04:34,124 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.04.cil-2.c [2021-12-16 10:04:34,130 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/6f146300d/ebcd43af12c24b498c6ec8a0e7207909/FLAGdc63b88ee [2021-12-16 10:04:34,139 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/6f146300d/ebcd43af12c24b498c6ec8a0e7207909 [2021-12-16 10:04:34,141 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-12-16 10:04:34,142 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-12-16 10:04:34,143 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-12-16 10:04:34,143 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-12-16 10:04:34,145 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-12-16 10:04:34,145 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 16.12 10:04:34" (1/1) ... [2021-12-16 10:04:34,146 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@765f8db7 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:04:34, skipping insertion in model container [2021-12-16 10:04:34,146 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 16.12 10:04:34" (1/1) ... [2021-12-16 10:04:34,151 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-12-16 10:04:34,176 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-12-16 10:04:34,311 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.04.cil-2.c[671,684] [2021-12-16 10:04:34,363 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-16 10:04:34,370 INFO L203 MainTranslator]: Completed pre-run [2021-12-16 10:04:34,377 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.04.cil-2.c[671,684] [2021-12-16 10:04:34,399 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-16 10:04:34,410 INFO L208 MainTranslator]: Completed translation [2021-12-16 10:04:34,410 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:04:34 WrapperNode [2021-12-16 10:04:34,410 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-12-16 10:04:34,411 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-12-16 10:04:34,411 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-12-16 10:04:34,412 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-12-16 10:04:34,428 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:04:34" (1/1) ... [2021-12-16 10:04:34,441 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:04:34" (1/1) ... [2021-12-16 10:04:34,471 INFO L137 Inliner]: procedures = 36, calls = 44, calls flagged for inlining = 39, calls inlined = 78, statements flattened = 1074 [2021-12-16 10:04:34,471 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-12-16 10:04:34,472 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-12-16 10:04:34,472 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-12-16 10:04:34,472 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-12-16 10:04:34,478 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:04:34" (1/1) ... [2021-12-16 10:04:34,478 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:04:34" (1/1) ... [2021-12-16 10:04:34,487 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:04:34" (1/1) ... [2021-12-16 10:04:34,487 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:04:34" (1/1) ... [2021-12-16 10:04:34,503 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:04:34" (1/1) ... [2021-12-16 10:04:34,519 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:04:34" (1/1) ... [2021-12-16 10:04:34,521 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:04:34" (1/1) ... [2021-12-16 10:04:34,526 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-12-16 10:04:34,527 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-12-16 10:04:34,527 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-12-16 10:04:34,527 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-12-16 10:04:34,528 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:04:34" (1/1) ... [2021-12-16 10:04:34,547 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-16 10:04:34,556 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-16 10:04:34,568 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-16 10:04:34,571 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2021-12-16 10:04:34,592 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2021-12-16 10:04:34,592 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2021-12-16 10:04:34,592 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-12-16 10:04:34,592 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-12-16 10:04:34,650 INFO L236 CfgBuilder]: Building ICFG [2021-12-16 10:04:34,651 INFO L262 CfgBuilder]: Building CFG for each procedure with an implementation [2021-12-16 10:04:35,227 INFO L277 CfgBuilder]: Performing block encoding [2021-12-16 10:04:35,236 INFO L296 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-12-16 10:04:35,236 INFO L301 CfgBuilder]: Removed 7 assume(true) statements. [2021-12-16 10:04:35,238 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 16.12 10:04:35 BoogieIcfgContainer [2021-12-16 10:04:35,238 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-12-16 10:04:35,239 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2021-12-16 10:04:35,239 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2021-12-16 10:04:35,242 INFO L275 PluginConnector]: BuchiAutomizer initialized [2021-12-16 10:04:35,243 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-16 10:04:35,243 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 16.12 10:04:34" (1/3) ... [2021-12-16 10:04:35,244 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@7f6fcb9b and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 16.12 10:04:35, skipping insertion in model container [2021-12-16 10:04:35,244 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-16 10:04:35,244 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:04:34" (2/3) ... [2021-12-16 10:04:35,244 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@7f6fcb9b and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 16.12 10:04:35, skipping insertion in model container [2021-12-16 10:04:35,244 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-16 10:04:35,244 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 16.12 10:04:35" (3/3) ... [2021-12-16 10:04:35,246 INFO L388 chiAutomizerObserver]: Analyzing ICFG token_ring.04.cil-2.c [2021-12-16 10:04:35,273 INFO L359 BuchiCegarLoop]: Interprodecural is true [2021-12-16 10:04:35,273 INFO L360 BuchiCegarLoop]: Hoare is false [2021-12-16 10:04:35,273 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2021-12-16 10:04:35,273 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2021-12-16 10:04:35,273 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2021-12-16 10:04:35,273 INFO L364 BuchiCegarLoop]: Difference is false [2021-12-16 10:04:35,274 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2021-12-16 10:04:35,274 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2021-12-16 10:04:35,299 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 438 states, 437 states have (on average 1.5354691075514875) internal successors, (671), 437 states have internal predecessors, (671), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:04:35,330 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 367 [2021-12-16 10:04:35,332 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:04:35,332 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:04:35,340 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:35,340 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:35,340 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2021-12-16 10:04:35,342 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 438 states, 437 states have (on average 1.5354691075514875) internal successors, (671), 437 states have internal predecessors, (671), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:04:35,355 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 367 [2021-12-16 10:04:35,355 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:04:35,355 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:04:35,357 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:35,357 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:35,363 INFO L791 eck$LassoCheckResult]: Stem: 430#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 351#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 126#L778true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 12#L358true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 50#L365true assume !(1 == ~m_i~0);~m_st~0 := 2; 325#L365-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 229#L370-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 182#L375-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 333#L380-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 211#L385-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 191#L526true assume !(0 == ~M_E~0); 414#L526-2true assume 0 == ~T1_E~0;~T1_E~0 := 1; 232#L531-1true assume !(0 == ~T2_E~0); 180#L536-1true assume !(0 == ~T3_E~0); 287#L541-1true assume !(0 == ~T4_E~0); 178#L546-1true assume !(0 == ~E_M~0); 240#L551-1true assume !(0 == ~E_1~0); 161#L556-1true assume !(0 == ~E_2~0); 189#L561-1true assume !(0 == ~E_3~0); 167#L566-1true assume 0 == ~E_4~0;~E_4~0 := 1; 363#L571-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 164#L262true assume 1 == ~m_pc~0; 437#L263true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 369#L273true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 76#L274true activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 366#L649true assume !(0 != activate_threads_~tmp~1#1); 433#L649-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 128#L281true assume !(1 == ~t1_pc~0); 386#L281-2true is_transmit1_triggered_~__retres1~1#1 := 0; 78#L292true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 210#L293true activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 112#L657true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 349#L657-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 169#L300true assume 1 == ~t2_pc~0; 297#L301true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 269#L311true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 108#L312true activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 187#L665true assume !(0 != activate_threads_~tmp___1~0#1); 39#L665-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 439#L319true assume !(1 == ~t3_pc~0); 19#L319-2true is_transmit3_triggered_~__retres1~3#1 := 0; 272#L330true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 123#L331true activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 141#L673true assume !(0 != activate_threads_~tmp___2~0#1); 29#L673-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 273#L338true assume 1 == ~t4_pc~0; 109#L339true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 73#L349true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 86#L350true activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 373#L681true assume !(0 != activate_threads_~tmp___3~0#1); 3#L681-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 360#L584true assume !(1 == ~M_E~0); 110#L584-2true assume !(1 == ~T1_E~0); 85#L589-1true assume !(1 == ~T2_E~0); 257#L594-1true assume !(1 == ~T3_E~0); 143#L599-1true assume !(1 == ~T4_E~0); 18#L604-1true assume !(1 == ~E_M~0); 10#L609-1true assume 1 == ~E_1~0;~E_1~0 := 2; 72#L614-1true assume !(1 == ~E_2~0); 122#L619-1true assume !(1 == ~E_3~0); 183#L624-1true assume !(1 == ~E_4~0); 393#L629-1true assume { :end_inline_reset_delta_events } true; 201#L815-2true [2021-12-16 10:04:35,364 INFO L793 eck$LassoCheckResult]: Loop: 201#L815-2true assume !false; 378#L816true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 354#L501true assume !true; 396#L516true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 356#L358-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 144#L526-3true assume 0 == ~M_E~0;~M_E~0 := 1; 263#L526-5true assume !(0 == ~T1_E~0); 74#L531-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 387#L536-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 15#L541-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 186#L546-3true assume 0 == ~E_M~0;~E_M~0 := 1; 434#L551-3true assume 0 == ~E_1~0;~E_1~0 := 1; 150#L556-3true assume 0 == ~E_2~0;~E_2~0 := 1; 235#L561-3true assume 0 == ~E_3~0;~E_3~0 := 1; 307#L566-3true assume !(0 == ~E_4~0); 80#L571-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 262#L262-18true assume !(1 == ~m_pc~0); 137#L262-20true is_master_triggered_~__retres1~0#1 := 0; 283#L273-6true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 71#L274-6true activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 359#L649-18true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 22#L649-20true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 159#L281-18true assume !(1 == ~t1_pc~0); 266#L281-20true is_transmit1_triggered_~__retres1~1#1 := 0; 171#L292-6true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 289#L293-6true activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 411#L657-18true assume !(0 != activate_threads_~tmp___0~0#1); 284#L657-20true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 324#L300-18true assume 1 == ~t2_pc~0; 156#L301-6true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 47#L311-6true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 58#L312-6true activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 249#L665-18true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 308#L665-20true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 79#L319-18true assume !(1 == ~t3_pc~0); 239#L319-20true is_transmit3_triggered_~__retres1~3#1 := 0; 91#L330-6true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 114#L331-6true activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 217#L673-18true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 198#L673-20true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 127#L338-18true assume !(1 == ~t4_pc~0); 157#L338-20true is_transmit4_triggered_~__retres1~4#1 := 0; 102#L349-6true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 350#L350-6true activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 32#L681-18true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 173#L681-20true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 140#L584-3true assume 1 == ~M_E~0;~M_E~0 := 2; 281#L584-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 30#L589-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 135#L594-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 214#L599-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 152#L604-3true assume 1 == ~E_M~0;~E_M~0 := 2; 399#L609-3true assume !(1 == ~E_1~0); 197#L614-3true assume 1 == ~E_2~0;~E_2~0 := 2; 26#L619-3true assume 1 == ~E_3~0;~E_3~0 := 2; 212#L624-3true assume 1 == ~E_4~0;~E_4~0 := 2; 241#L629-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 251#L398-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 68#L425-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 294#L426-1true start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 96#L834true assume !(0 == start_simulation_~tmp~3#1); 220#L834-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 344#L398-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 216#L425-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 252#L426-2true stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 286#L789true assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 296#L796true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 184#L797true start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 199#L847true assume !(0 != start_simulation_~tmp___0~1#1); 201#L815-2true [2021-12-16 10:04:35,368 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:35,368 INFO L85 PathProgramCache]: Analyzing trace with hash 1553035642, now seen corresponding path program 1 times [2021-12-16 10:04:35,374 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:35,374 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1774681898] [2021-12-16 10:04:35,375 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:35,375 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:35,474 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:04:35,573 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:04:35,573 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:04:35,574 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1774681898] [2021-12-16 10:04:35,574 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1774681898] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:04:35,574 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:04:35,574 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:04:35,575 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [15228071] [2021-12-16 10:04:35,576 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:04:35,578 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:04:35,579 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:35,579 INFO L85 PathProgramCache]: Analyzing trace with hash 15069021, now seen corresponding path program 1 times [2021-12-16 10:04:35,579 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:35,579 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1796941581] [2021-12-16 10:04:35,580 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:35,580 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:35,591 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:04:35,609 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:04:35,610 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:04:35,610 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1796941581] [2021-12-16 10:04:35,611 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1796941581] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:04:35,611 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:04:35,612 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-16 10:04:35,612 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1200085744] [2021-12-16 10:04:35,612 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:04:35,614 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:04:35,615 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:04:35,641 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-16 10:04:35,641 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-16 10:04:35,644 INFO L87 Difference]: Start difference. First operand has 438 states, 437 states have (on average 1.5354691075514875) internal successors, (671), 437 states have internal predecessors, (671), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:04:35,717 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:04:35,717 INFO L93 Difference]: Finished difference Result 436 states and 652 transitions. [2021-12-16 10:04:35,720 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-16 10:04:35,724 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 436 states and 652 transitions. [2021-12-16 10:04:35,730 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 363 [2021-12-16 10:04:35,739 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 436 states to 430 states and 646 transitions. [2021-12-16 10:04:35,740 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 430 [2021-12-16 10:04:35,742 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 430 [2021-12-16 10:04:35,743 INFO L73 IsDeterministic]: Start isDeterministic. Operand 430 states and 646 transitions. [2021-12-16 10:04:35,748 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:04:35,749 INFO L681 BuchiCegarLoop]: Abstraction has 430 states and 646 transitions. [2021-12-16 10:04:35,762 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 430 states and 646 transitions. [2021-12-16 10:04:35,789 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 430 to 430. [2021-12-16 10:04:35,791 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 430 states, 430 states have (on average 1.5023255813953489) internal successors, (646), 429 states have internal predecessors, (646), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:04:35,792 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 430 states to 430 states and 646 transitions. [2021-12-16 10:04:35,793 INFO L704 BuchiCegarLoop]: Abstraction has 430 states and 646 transitions. [2021-12-16 10:04:35,793 INFO L587 BuchiCegarLoop]: Abstraction has 430 states and 646 transitions. [2021-12-16 10:04:35,793 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2021-12-16 10:04:35,793 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 430 states and 646 transitions. [2021-12-16 10:04:35,796 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 363 [2021-12-16 10:04:35,796 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:04:35,796 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:04:35,801 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:35,801 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:35,801 INFO L791 eck$LassoCheckResult]: Stem: 1312#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 1295#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 1107#L778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 905#L358 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 906#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 980#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1226#L370-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1184#L375-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1185#L380-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1212#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1194#L526 assume !(0 == ~M_E~0); 1195#L526-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1227#L531-1 assume !(0 == ~T2_E~0); 1180#L536-1 assume !(0 == ~T3_E~0); 1181#L541-1 assume !(0 == ~T4_E~0); 1176#L546-1 assume !(0 == ~E_M~0); 1177#L551-1 assume !(0 == ~E_1~0); 1153#L556-1 assume !(0 == ~E_2~0); 1154#L561-1 assume !(0 == ~E_3~0); 1164#L566-1 assume 0 == ~E_4~0;~E_4~0 := 1; 1165#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1158#L262 assume 1 == ~m_pc~0; 1159#L263 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1299#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1024#L274 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1025#L649 assume !(0 != activate_threads_~tmp~1#1); 1298#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1111#L281 assume !(1 == ~t1_pc~0); 1112#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1028#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1029#L293 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1087#L657 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1088#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1166#L300 assume 1 == ~t2_pc~0; 1167#L301 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1257#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1081#L312 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1082#L665 assume !(0 != activate_threads_~tmp___1~0#1); 960#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 961#L319 assume !(1 == ~t3_pc~0); 918#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 919#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1102#L331 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1103#L673 assume !(0 != activate_threads_~tmp___2~0#1); 939#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 940#L338 assume 1 == ~t4_pc~0; 1083#L339 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1004#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1018#L350 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1045#L681 assume !(0 != activate_threads_~tmp___3~0#1); 883#L681-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 884#L584 assume !(1 == ~M_E~0); 1084#L584-2 assume !(1 == ~T1_E~0); 1043#L589-1 assume !(1 == ~T2_E~0); 1044#L594-1 assume !(1 == ~T3_E~0); 1132#L599-1 assume !(1 == ~T4_E~0); 917#L604-1 assume !(1 == ~E_M~0); 901#L609-1 assume 1 == ~E_1~0;~E_1~0 := 2; 902#L614-1 assume !(1 == ~E_2~0); 1017#L619-1 assume !(1 == ~E_3~0); 1101#L624-1 assume !(1 == ~E_4~0); 1186#L629-1 assume { :end_inline_reset_delta_events } true; 1203#L815-2 [2021-12-16 10:04:35,802 INFO L793 eck$LassoCheckResult]: Loop: 1203#L815-2 assume !false; 1204#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1287#L501 assume !false; 1293#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 1294#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 1022#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 1207#L426 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1208#L440 assume !(0 != eval_~tmp~0#1); 1306#L516 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1296#L358-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1133#L526-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1134#L526-5 assume !(0 == ~T1_E~0); 1019#L531-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1020#L536-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 911#L541-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 912#L546-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1190#L551-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1139#L556-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1140#L561-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1233#L566-3 assume !(0 == ~E_4~0); 1033#L571-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1034#L262-18 assume 1 == ~m_pc~0; 1251#L263-6 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1124#L273-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1015#L274-6 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1016#L649-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 924#L649-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 925#L281-18 assume !(1 == ~t1_pc~0); 1150#L281-20 is_transmit1_triggered_~__retres1~1#1 := 0; 1169#L292-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1170#L293-6 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1269#L657-18 assume !(0 != activate_threads_~tmp___0~0#1); 1265#L657-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1266#L300-18 assume !(1 == ~t2_pc~0); 913#L300-20 is_transmit2_triggered_~__retres1~2#1 := 0; 914#L311-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 977#L312-6 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 994#L665-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1241#L665-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1030#L319-18 assume !(1 == ~t3_pc~0); 1031#L319-20 is_transmit3_triggered_~__retres1~3#1 := 0; 1037#L330-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1053#L331-6 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1090#L673-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1202#L673-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1108#L338-18 assume 1 == ~t4_pc~0; 1109#L339-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1072#L349-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1073#L350-6 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 945#L681-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 946#L681-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1128#L584-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1129#L584-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 941#L589-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 942#L594-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1121#L599-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1142#L604-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1143#L609-3 assume !(1 == ~E_1~0); 1201#L614-3 assume 1 == ~E_2~0;~E_2~0 := 2; 933#L619-3 assume 1 == ~E_3~0;~E_3~0 := 2; 934#L624-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1213#L629-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 1236#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 1011#L425-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 1012#L426-1 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 1059#L834 assume !(0 == start_simulation_~tmp~3#1); 1061#L834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 1220#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 1179#L425-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 1216#L426-2 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 1244#L789 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 1267#L796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1187#L797 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 1188#L847 assume !(0 != start_simulation_~tmp___0~1#1); 1203#L815-2 [2021-12-16 10:04:35,803 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:35,803 INFO L85 PathProgramCache]: Analyzing trace with hash 1119306556, now seen corresponding path program 1 times [2021-12-16 10:04:35,803 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:35,804 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [66120451] [2021-12-16 10:04:35,804 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:35,804 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:35,832 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:04:35,858 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:04:35,859 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:04:35,860 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [66120451] [2021-12-16 10:04:35,861 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [66120451] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:04:35,861 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:04:35,861 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:04:35,862 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [638653436] [2021-12-16 10:04:35,862 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:04:35,862 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:04:35,863 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:35,864 INFO L85 PathProgramCache]: Analyzing trace with hash 330425744, now seen corresponding path program 1 times [2021-12-16 10:04:35,864 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:35,865 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2015055316] [2021-12-16 10:04:35,865 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:35,865 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:35,889 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:04:35,931 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:04:35,932 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:04:35,932 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2015055316] [2021-12-16 10:04:35,932 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2015055316] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:04:35,932 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:04:35,932 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:04:35,932 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [483362781] [2021-12-16 10:04:35,933 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:04:35,933 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:04:35,933 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:04:35,933 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-16 10:04:35,934 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-16 10:04:35,934 INFO L87 Difference]: Start difference. First operand 430 states and 646 transitions. cyclomatic complexity: 217 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:04:35,943 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:04:35,944 INFO L93 Difference]: Finished difference Result 430 states and 645 transitions. [2021-12-16 10:04:35,944 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-16 10:04:35,945 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 430 states and 645 transitions. [2021-12-16 10:04:35,947 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 363 [2021-12-16 10:04:35,949 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 430 states to 430 states and 645 transitions. [2021-12-16 10:04:35,949 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 430 [2021-12-16 10:04:35,950 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 430 [2021-12-16 10:04:35,950 INFO L73 IsDeterministic]: Start isDeterministic. Operand 430 states and 645 transitions. [2021-12-16 10:04:35,950 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:04:35,950 INFO L681 BuchiCegarLoop]: Abstraction has 430 states and 645 transitions. [2021-12-16 10:04:35,951 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 430 states and 645 transitions. [2021-12-16 10:04:35,955 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 430 to 430. [2021-12-16 10:04:35,956 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 430 states, 430 states have (on average 1.5) internal successors, (645), 429 states have internal predecessors, (645), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:04:35,957 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 430 states to 430 states and 645 transitions. [2021-12-16 10:04:35,957 INFO L704 BuchiCegarLoop]: Abstraction has 430 states and 645 transitions. [2021-12-16 10:04:35,957 INFO L587 BuchiCegarLoop]: Abstraction has 430 states and 645 transitions. [2021-12-16 10:04:35,957 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2021-12-16 10:04:35,957 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 430 states and 645 transitions. [2021-12-16 10:04:35,959 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 363 [2021-12-16 10:04:35,959 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:04:35,959 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:04:35,960 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:35,960 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:35,961 INFO L791 eck$LassoCheckResult]: Stem: 2179#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 2162#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 1974#L778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1772#L358 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1773#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 1847#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2093#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2051#L375-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2052#L380-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2079#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2061#L526 assume !(0 == ~M_E~0); 2062#L526-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2094#L531-1 assume !(0 == ~T2_E~0); 2047#L536-1 assume !(0 == ~T3_E~0); 2048#L541-1 assume !(0 == ~T4_E~0); 2043#L546-1 assume !(0 == ~E_M~0); 2044#L551-1 assume !(0 == ~E_1~0); 2020#L556-1 assume !(0 == ~E_2~0); 2021#L561-1 assume !(0 == ~E_3~0); 2031#L566-1 assume 0 == ~E_4~0;~E_4~0 := 1; 2032#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2025#L262 assume 1 == ~m_pc~0; 2026#L263 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2166#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1891#L274 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1892#L649 assume !(0 != activate_threads_~tmp~1#1); 2165#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1978#L281 assume !(1 == ~t1_pc~0); 1979#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1895#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1896#L293 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1954#L657 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1955#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2033#L300 assume 1 == ~t2_pc~0; 2034#L301 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2124#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1948#L312 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1949#L665 assume !(0 != activate_threads_~tmp___1~0#1); 1827#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1828#L319 assume !(1 == ~t3_pc~0); 1785#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1786#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1969#L331 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1970#L673 assume !(0 != activate_threads_~tmp___2~0#1); 1806#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1807#L338 assume 1 == ~t4_pc~0; 1950#L339 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1871#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1885#L350 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1912#L681 assume !(0 != activate_threads_~tmp___3~0#1); 1750#L681-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1751#L584 assume !(1 == ~M_E~0); 1951#L584-2 assume !(1 == ~T1_E~0); 1910#L589-1 assume !(1 == ~T2_E~0); 1911#L594-1 assume !(1 == ~T3_E~0); 1999#L599-1 assume !(1 == ~T4_E~0); 1784#L604-1 assume !(1 == ~E_M~0); 1768#L609-1 assume 1 == ~E_1~0;~E_1~0 := 2; 1769#L614-1 assume !(1 == ~E_2~0); 1884#L619-1 assume !(1 == ~E_3~0); 1968#L624-1 assume !(1 == ~E_4~0); 2053#L629-1 assume { :end_inline_reset_delta_events } true; 2070#L815-2 [2021-12-16 10:04:35,961 INFO L793 eck$LassoCheckResult]: Loop: 2070#L815-2 assume !false; 2071#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2154#L501 assume !false; 2160#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 2161#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 1889#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 2074#L426 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 2075#L440 assume !(0 != eval_~tmp~0#1); 2173#L516 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2163#L358-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2000#L526-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2001#L526-5 assume !(0 == ~T1_E~0); 1886#L531-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1887#L536-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1778#L541-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1779#L546-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2057#L551-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2006#L556-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2007#L561-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2100#L566-3 assume !(0 == ~E_4~0); 1900#L571-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1901#L262-18 assume 1 == ~m_pc~0; 2118#L263-6 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1991#L273-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1882#L274-6 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1883#L649-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1791#L649-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1792#L281-18 assume !(1 == ~t1_pc~0); 2017#L281-20 is_transmit1_triggered_~__retres1~1#1 := 0; 2036#L292-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2037#L293-6 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2136#L657-18 assume !(0 != activate_threads_~tmp___0~0#1); 2132#L657-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2133#L300-18 assume !(1 == ~t2_pc~0); 1780#L300-20 is_transmit2_triggered_~__retres1~2#1 := 0; 1781#L311-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1844#L312-6 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1861#L665-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2108#L665-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1897#L319-18 assume !(1 == ~t3_pc~0); 1898#L319-20 is_transmit3_triggered_~__retres1~3#1 := 0; 1904#L330-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1920#L331-6 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1957#L673-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2069#L673-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1975#L338-18 assume 1 == ~t4_pc~0; 1976#L339-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1939#L349-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1940#L350-6 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1812#L681-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1813#L681-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1995#L584-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1996#L584-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1808#L589-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1809#L594-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1988#L599-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2009#L604-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2010#L609-3 assume !(1 == ~E_1~0); 2068#L614-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1800#L619-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1801#L624-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2080#L629-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 2103#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 1878#L425-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 1879#L426-1 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 1926#L834 assume !(0 == start_simulation_~tmp~3#1); 1928#L834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 2087#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 2046#L425-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 2083#L426-2 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 2111#L789 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 2134#L796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2054#L797 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 2055#L847 assume !(0 != start_simulation_~tmp___0~1#1); 2070#L815-2 [2021-12-16 10:04:35,961 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:35,962 INFO L85 PathProgramCache]: Analyzing trace with hash 1078631806, now seen corresponding path program 1 times [2021-12-16 10:04:35,962 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:35,962 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1652510919] [2021-12-16 10:04:35,962 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:35,962 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:35,969 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:04:35,984 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:04:35,984 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:04:35,985 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1652510919] [2021-12-16 10:04:35,985 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1652510919] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:04:35,985 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:04:35,985 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:04:35,985 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [782344523] [2021-12-16 10:04:35,985 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:04:35,986 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:04:35,986 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:35,986 INFO L85 PathProgramCache]: Analyzing trace with hash 330425744, now seen corresponding path program 2 times [2021-12-16 10:04:35,986 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:35,987 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1477283789] [2021-12-16 10:04:35,987 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:35,987 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:35,995 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:04:36,015 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:04:36,016 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:04:36,016 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1477283789] [2021-12-16 10:04:36,016 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1477283789] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:04:36,016 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:04:36,016 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:04:36,017 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [619158755] [2021-12-16 10:04:36,017 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:04:36,017 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:04:36,017 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:04:36,018 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-16 10:04:36,018 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-16 10:04:36,018 INFO L87 Difference]: Start difference. First operand 430 states and 645 transitions. cyclomatic complexity: 216 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:04:36,026 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:04:36,026 INFO L93 Difference]: Finished difference Result 430 states and 644 transitions. [2021-12-16 10:04:36,027 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-16 10:04:36,027 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 430 states and 644 transitions. [2021-12-16 10:04:36,030 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 363 [2021-12-16 10:04:36,031 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 430 states to 430 states and 644 transitions. [2021-12-16 10:04:36,032 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 430 [2021-12-16 10:04:36,032 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 430 [2021-12-16 10:04:36,032 INFO L73 IsDeterministic]: Start isDeterministic. Operand 430 states and 644 transitions. [2021-12-16 10:04:36,033 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:04:36,033 INFO L681 BuchiCegarLoop]: Abstraction has 430 states and 644 transitions. [2021-12-16 10:04:36,033 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 430 states and 644 transitions. [2021-12-16 10:04:36,037 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 430 to 430. [2021-12-16 10:04:36,073 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 430 states, 430 states have (on average 1.4976744186046511) internal successors, (644), 429 states have internal predecessors, (644), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:04:36,075 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 430 states to 430 states and 644 transitions. [2021-12-16 10:04:36,075 INFO L704 BuchiCegarLoop]: Abstraction has 430 states and 644 transitions. [2021-12-16 10:04:36,075 INFO L587 BuchiCegarLoop]: Abstraction has 430 states and 644 transitions. [2021-12-16 10:04:36,075 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2021-12-16 10:04:36,075 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 430 states and 644 transitions. [2021-12-16 10:04:36,077 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 363 [2021-12-16 10:04:36,077 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:04:36,077 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:04:36,078 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:36,078 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:36,078 INFO L791 eck$LassoCheckResult]: Stem: 3046#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 3029#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 2841#L778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2639#L358 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2640#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 2714#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2960#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2918#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2919#L380-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2946#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2928#L526 assume !(0 == ~M_E~0); 2929#L526-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2961#L531-1 assume !(0 == ~T2_E~0); 2914#L536-1 assume !(0 == ~T3_E~0); 2915#L541-1 assume !(0 == ~T4_E~0); 2910#L546-1 assume !(0 == ~E_M~0); 2911#L551-1 assume !(0 == ~E_1~0); 2887#L556-1 assume !(0 == ~E_2~0); 2888#L561-1 assume !(0 == ~E_3~0); 2898#L566-1 assume 0 == ~E_4~0;~E_4~0 := 1; 2899#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2892#L262 assume 1 == ~m_pc~0; 2893#L263 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 3033#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2758#L274 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2759#L649 assume !(0 != activate_threads_~tmp~1#1); 3032#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2845#L281 assume !(1 == ~t1_pc~0); 2846#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2762#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2763#L293 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2821#L657 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2822#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2900#L300 assume 1 == ~t2_pc~0; 2901#L301 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2991#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2815#L312 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2816#L665 assume !(0 != activate_threads_~tmp___1~0#1); 2694#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2695#L319 assume !(1 == ~t3_pc~0); 2652#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2653#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2836#L331 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2837#L673 assume !(0 != activate_threads_~tmp___2~0#1); 2673#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2674#L338 assume 1 == ~t4_pc~0; 2817#L339 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2738#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2752#L350 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2779#L681 assume !(0 != activate_threads_~tmp___3~0#1); 2617#L681-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2618#L584 assume !(1 == ~M_E~0); 2818#L584-2 assume !(1 == ~T1_E~0); 2777#L589-1 assume !(1 == ~T2_E~0); 2778#L594-1 assume !(1 == ~T3_E~0); 2866#L599-1 assume !(1 == ~T4_E~0); 2651#L604-1 assume !(1 == ~E_M~0); 2635#L609-1 assume 1 == ~E_1~0;~E_1~0 := 2; 2636#L614-1 assume !(1 == ~E_2~0); 2751#L619-1 assume !(1 == ~E_3~0); 2835#L624-1 assume !(1 == ~E_4~0); 2920#L629-1 assume { :end_inline_reset_delta_events } true; 2937#L815-2 [2021-12-16 10:04:36,079 INFO L793 eck$LassoCheckResult]: Loop: 2937#L815-2 assume !false; 2938#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3021#L501 assume !false; 3027#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 3028#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 2756#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 2941#L426 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 2942#L440 assume !(0 != eval_~tmp~0#1); 3040#L516 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3030#L358-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2867#L526-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2868#L526-5 assume !(0 == ~T1_E~0); 2753#L531-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2754#L536-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2645#L541-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2646#L546-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2924#L551-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2873#L556-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2874#L561-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2967#L566-3 assume !(0 == ~E_4~0); 2767#L571-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2768#L262-18 assume 1 == ~m_pc~0; 2985#L263-6 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2858#L273-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2749#L274-6 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2750#L649-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2658#L649-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2659#L281-18 assume !(1 == ~t1_pc~0); 2884#L281-20 is_transmit1_triggered_~__retres1~1#1 := 0; 2903#L292-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2904#L293-6 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3003#L657-18 assume !(0 != activate_threads_~tmp___0~0#1); 2999#L657-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3000#L300-18 assume 1 == ~t2_pc~0; 2882#L301-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2648#L311-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2711#L312-6 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2728#L665-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2975#L665-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2764#L319-18 assume !(1 == ~t3_pc~0); 2765#L319-20 is_transmit3_triggered_~__retres1~3#1 := 0; 2771#L330-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2787#L331-6 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2824#L673-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2936#L673-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2842#L338-18 assume 1 == ~t4_pc~0; 2843#L339-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2806#L349-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2807#L350-6 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2679#L681-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2680#L681-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2862#L584-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2863#L584-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2675#L589-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2676#L594-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2855#L599-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2876#L604-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2877#L609-3 assume !(1 == ~E_1~0); 2935#L614-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2667#L619-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2668#L624-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2947#L629-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 2970#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 2745#L425-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 2746#L426-1 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 2793#L834 assume !(0 == start_simulation_~tmp~3#1); 2795#L834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 2954#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 2913#L425-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 2950#L426-2 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 2978#L789 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 3001#L796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2921#L797 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 2922#L847 assume !(0 != start_simulation_~tmp___0~1#1); 2937#L815-2 [2021-12-16 10:04:36,082 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:36,083 INFO L85 PathProgramCache]: Analyzing trace with hash -308153604, now seen corresponding path program 1 times [2021-12-16 10:04:36,083 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:36,084 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [950074358] [2021-12-16 10:04:36,084 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:36,084 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:36,091 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:04:36,104 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:04:36,104 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:04:36,104 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [950074358] [2021-12-16 10:04:36,105 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [950074358] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:04:36,105 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:04:36,105 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:04:36,105 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1916275032] [2021-12-16 10:04:36,105 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:04:36,105 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:04:36,106 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:36,106 INFO L85 PathProgramCache]: Analyzing trace with hash 815600463, now seen corresponding path program 1 times [2021-12-16 10:04:36,106 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:36,106 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1278484928] [2021-12-16 10:04:36,106 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:36,107 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:36,114 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:04:36,133 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:04:36,134 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:04:36,134 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1278484928] [2021-12-16 10:04:36,134 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1278484928] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:04:36,134 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:04:36,134 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:04:36,134 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [255265608] [2021-12-16 10:04:36,135 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:04:36,135 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:04:36,135 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:04:36,135 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-16 10:04:36,136 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-16 10:04:36,136 INFO L87 Difference]: Start difference. First operand 430 states and 644 transitions. cyclomatic complexity: 215 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:04:36,146 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:04:36,147 INFO L93 Difference]: Finished difference Result 430 states and 643 transitions. [2021-12-16 10:04:36,147 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-16 10:04:36,149 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 430 states and 643 transitions. [2021-12-16 10:04:36,152 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 363 [2021-12-16 10:04:36,154 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 430 states to 430 states and 643 transitions. [2021-12-16 10:04:36,154 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 430 [2021-12-16 10:04:36,155 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 430 [2021-12-16 10:04:36,155 INFO L73 IsDeterministic]: Start isDeterministic. Operand 430 states and 643 transitions. [2021-12-16 10:04:36,156 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:04:36,156 INFO L681 BuchiCegarLoop]: Abstraction has 430 states and 643 transitions. [2021-12-16 10:04:36,156 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 430 states and 643 transitions. [2021-12-16 10:04:36,160 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 430 to 430. [2021-12-16 10:04:36,160 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 430 states, 430 states have (on average 1.4953488372093022) internal successors, (643), 429 states have internal predecessors, (643), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:04:36,161 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 430 states to 430 states and 643 transitions. [2021-12-16 10:04:36,162 INFO L704 BuchiCegarLoop]: Abstraction has 430 states and 643 transitions. [2021-12-16 10:04:36,162 INFO L587 BuchiCegarLoop]: Abstraction has 430 states and 643 transitions. [2021-12-16 10:04:36,162 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2021-12-16 10:04:36,162 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 430 states and 643 transitions. [2021-12-16 10:04:36,164 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 363 [2021-12-16 10:04:36,164 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:04:36,164 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:04:36,165 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:36,166 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:36,166 INFO L791 eck$LassoCheckResult]: Stem: 3913#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 3896#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 3711#L778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3506#L358 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3507#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 3581#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3827#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3786#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3787#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 3814#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3796#L526 assume !(0 == ~M_E~0); 3797#L526-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3829#L531-1 assume !(0 == ~T2_E~0); 3781#L536-1 assume !(0 == ~T3_E~0); 3782#L541-1 assume !(0 == ~T4_E~0); 3777#L546-1 assume !(0 == ~E_M~0); 3778#L551-1 assume !(0 == ~E_1~0); 3754#L556-1 assume !(0 == ~E_2~0); 3755#L561-1 assume !(0 == ~E_3~0); 3765#L566-1 assume 0 == ~E_4~0;~E_4~0 := 1; 3766#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3759#L262 assume 1 == ~m_pc~0; 3760#L263 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 3900#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3625#L274 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 3626#L649 assume !(0 != activate_threads_~tmp~1#1); 3899#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3712#L281 assume !(1 == ~t1_pc~0); 3713#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 3629#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3630#L293 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3688#L657 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3689#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3767#L300 assume 1 == ~t2_pc~0; 3768#L301 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3858#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3682#L312 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3683#L665 assume !(0 != activate_threads_~tmp___1~0#1); 3561#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3562#L319 assume !(1 == ~t3_pc~0); 3519#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 3520#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3703#L331 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3704#L673 assume !(0 != activate_threads_~tmp___2~0#1); 3540#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3541#L338 assume 1 == ~t4_pc~0; 3684#L339 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3605#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3619#L350 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3646#L681 assume !(0 != activate_threads_~tmp___3~0#1); 3484#L681-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3485#L584 assume !(1 == ~M_E~0); 3685#L584-2 assume !(1 == ~T1_E~0); 3644#L589-1 assume !(1 == ~T2_E~0); 3645#L594-1 assume !(1 == ~T3_E~0); 3733#L599-1 assume !(1 == ~T4_E~0); 3518#L604-1 assume !(1 == ~E_M~0); 3502#L609-1 assume 1 == ~E_1~0;~E_1~0 := 2; 3503#L614-1 assume !(1 == ~E_2~0); 3618#L619-1 assume !(1 == ~E_3~0); 3702#L624-1 assume !(1 == ~E_4~0); 3785#L629-1 assume { :end_inline_reset_delta_events } true; 3804#L815-2 [2021-12-16 10:04:36,166 INFO L793 eck$LassoCheckResult]: Loop: 3804#L815-2 assume !false; 3805#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3888#L501 assume !false; 3894#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 3895#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 3623#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 3808#L426 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 3809#L440 assume !(0 != eval_~tmp~0#1); 3907#L516 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3897#L358-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3734#L526-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3735#L526-5 assume !(0 == ~T1_E~0); 3620#L531-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3621#L536-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3512#L541-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3513#L546-3 assume 0 == ~E_M~0;~E_M~0 := 1; 3791#L551-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3740#L556-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3741#L561-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3834#L566-3 assume !(0 == ~E_4~0); 3634#L571-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3635#L262-18 assume 1 == ~m_pc~0; 3852#L263-6 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 3725#L273-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3616#L274-6 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 3617#L649-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3525#L649-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3526#L281-18 assume !(1 == ~t1_pc~0); 3751#L281-20 is_transmit1_triggered_~__retres1~1#1 := 0; 3770#L292-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3771#L293-6 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3870#L657-18 assume !(0 != activate_threads_~tmp___0~0#1); 3866#L657-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3867#L300-18 assume 1 == ~t2_pc~0; 3749#L301-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3515#L311-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3578#L312-6 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3595#L665-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3842#L665-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3631#L319-18 assume !(1 == ~t3_pc~0); 3632#L319-20 is_transmit3_triggered_~__retres1~3#1 := 0; 3638#L330-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3654#L331-6 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3691#L673-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3803#L673-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3708#L338-18 assume 1 == ~t4_pc~0; 3709#L339-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3673#L349-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3674#L350-6 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3546#L681-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3547#L681-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3729#L584-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3730#L584-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3542#L589-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3543#L594-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3722#L599-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3743#L604-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3744#L609-3 assume !(1 == ~E_1~0); 3802#L614-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3534#L619-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3535#L624-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3813#L629-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 3837#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 3612#L425-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 3613#L426-1 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 3660#L834 assume !(0 == start_simulation_~tmp~3#1); 3662#L834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 3821#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 3780#L425-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 3817#L426-2 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 3845#L789 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 3868#L796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3788#L797 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 3789#L847 assume !(0 != start_simulation_~tmp___0~1#1); 3804#L815-2 [2021-12-16 10:04:36,167 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:36,167 INFO L85 PathProgramCache]: Analyzing trace with hash -1184172610, now seen corresponding path program 1 times [2021-12-16 10:04:36,167 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:36,167 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1749429606] [2021-12-16 10:04:36,167 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:36,167 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:36,187 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:04:36,222 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:04:36,222 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:04:36,223 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1749429606] [2021-12-16 10:04:36,223 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1749429606] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:04:36,223 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:04:36,223 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:04:36,223 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1104804781] [2021-12-16 10:04:36,223 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:04:36,224 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:04:36,224 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:36,224 INFO L85 PathProgramCache]: Analyzing trace with hash 815600463, now seen corresponding path program 2 times [2021-12-16 10:04:36,224 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:36,224 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1690331226] [2021-12-16 10:04:36,224 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:36,225 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:36,235 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:04:36,256 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:04:36,256 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:04:36,257 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1690331226] [2021-12-16 10:04:36,257 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1690331226] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:04:36,257 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:04:36,257 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:04:36,257 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1104505350] [2021-12-16 10:04:36,257 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:04:36,258 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:04:36,258 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:04:36,258 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-16 10:04:36,258 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-16 10:04:36,258 INFO L87 Difference]: Start difference. First operand 430 states and 643 transitions. cyclomatic complexity: 214 Second operand has 4 states, 4 states have (on average 15.5) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:04:36,311 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:04:36,311 INFO L93 Difference]: Finished difference Result 756 states and 1125 transitions. [2021-12-16 10:04:36,311 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-16 10:04:36,313 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 756 states and 1125 transitions. [2021-12-16 10:04:36,317 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 679 [2021-12-16 10:04:36,320 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 756 states to 756 states and 1125 transitions. [2021-12-16 10:04:36,321 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 756 [2021-12-16 10:04:36,322 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 756 [2021-12-16 10:04:36,322 INFO L73 IsDeterministic]: Start isDeterministic. Operand 756 states and 1125 transitions. [2021-12-16 10:04:36,323 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:04:36,323 INFO L681 BuchiCegarLoop]: Abstraction has 756 states and 1125 transitions. [2021-12-16 10:04:36,323 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 756 states and 1125 transitions. [2021-12-16 10:04:36,330 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 756 to 756. [2021-12-16 10:04:36,332 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 756 states, 756 states have (on average 1.4880952380952381) internal successors, (1125), 755 states have internal predecessors, (1125), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:04:36,333 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 756 states to 756 states and 1125 transitions. [2021-12-16 10:04:36,333 INFO L704 BuchiCegarLoop]: Abstraction has 756 states and 1125 transitions. [2021-12-16 10:04:36,333 INFO L587 BuchiCegarLoop]: Abstraction has 756 states and 1125 transitions. [2021-12-16 10:04:36,333 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2021-12-16 10:04:36,334 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 756 states and 1125 transitions. [2021-12-16 10:04:36,336 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 679 [2021-12-16 10:04:36,336 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:04:36,336 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:04:36,338 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:36,338 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:36,339 INFO L791 eck$LassoCheckResult]: Stem: 5138#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 5113#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 4908#L778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4702#L358 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4703#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 4777#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5031#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4985#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4986#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 5016#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4996#L526 assume !(0 == ~M_E~0); 4997#L526-2 assume !(0 == ~T1_E~0); 5033#L531-1 assume !(0 == ~T2_E~0); 4981#L536-1 assume !(0 == ~T3_E~0); 4982#L541-1 assume !(0 == ~T4_E~0); 4977#L546-1 assume !(0 == ~E_M~0); 4978#L551-1 assume !(0 == ~E_1~0); 4953#L556-1 assume !(0 == ~E_2~0); 4954#L561-1 assume !(0 == ~E_3~0); 4964#L566-1 assume 0 == ~E_4~0;~E_4~0 := 1; 4965#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4958#L262 assume 1 == ~m_pc~0; 4959#L263 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 5119#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4824#L274 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 4825#L649 assume !(0 != activate_threads_~tmp~1#1); 5118#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4909#L281 assume !(1 == ~t1_pc~0); 4910#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4826#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4827#L293 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4885#L657 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4886#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4966#L300 assume 1 == ~t2_pc~0; 4967#L301 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5066#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4879#L312 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4880#L665 assume !(0 != activate_threads_~tmp___1~0#1); 4757#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4758#L319 assume !(1 == ~t3_pc~0); 4715#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 4716#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4900#L331 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4901#L673 assume !(0 != activate_threads_~tmp___2~0#1); 4736#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4737#L338 assume 1 == ~t4_pc~0; 4881#L339 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4802#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4816#L350 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4843#L681 assume !(0 != activate_threads_~tmp___3~0#1); 4680#L681-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4681#L584 assume 1 == ~M_E~0;~M_E~0 := 2; 4882#L584-2 assume !(1 == ~T1_E~0); 4841#L589-1 assume !(1 == ~T2_E~0); 4842#L594-1 assume !(1 == ~T3_E~0); 4932#L599-1 assume !(1 == ~T4_E~0); 4714#L604-1 assume !(1 == ~E_M~0); 4698#L609-1 assume 1 == ~E_1~0;~E_1~0 := 2; 4699#L614-1 assume !(1 == ~E_2~0); 4815#L619-1 assume !(1 == ~E_3~0); 4899#L624-1 assume !(1 == ~E_4~0); 4987#L629-1 assume { :end_inline_reset_delta_events } true; 5005#L815-2 [2021-12-16 10:04:36,339 INFO L793 eck$LassoCheckResult]: Loop: 5005#L815-2 assume !false; 5153#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5152#L501 assume !false; 5151#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 5150#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 5145#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 5144#L426 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 5143#L440 assume !(0 != eval_~tmp~0#1); 5142#L516 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5141#L358-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5140#L526-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5060#L526-5 assume !(0 == ~T1_E~0); 4817#L531-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4818#L536-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4708#L541-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4709#L546-3 assume 0 == ~E_M~0;~E_M~0 := 1; 4991#L551-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4939#L556-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4940#L561-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5037#L566-3 assume !(0 == ~E_4~0); 4831#L571-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4832#L262-18 assume 1 == ~m_pc~0; 5059#L263-6 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 4923#L273-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4813#L274-6 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 4814#L649-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4721#L649-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4722#L281-18 assume !(1 == ~t1_pc~0); 4950#L281-20 is_transmit1_triggered_~__retres1~1#1 := 0; 4969#L292-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4970#L293-6 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 5078#L657-18 assume !(0 != activate_threads_~tmp___0~0#1); 5132#L657-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5384#L300-18 assume 1 == ~t2_pc~0; 5381#L301-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5380#L311-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5379#L312-6 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5378#L665-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5377#L665-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5376#L319-18 assume !(1 == ~t3_pc~0); 5374#L319-20 is_transmit3_triggered_~__retres1~3#1 := 0; 5373#L330-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5372#L331-6 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5371#L673-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5370#L673-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5368#L338-18 assume 1 == ~t4_pc~0; 5365#L339-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5364#L349-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5363#L350-6 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5360#L681-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5358#L681-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4928#L584-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4929#L584-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4738#L589-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4739#L594-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5328#L599-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4942#L604-3 assume 1 == ~E_M~0;~E_M~0 := 2; 4943#L609-3 assume !(1 == ~E_1~0); 5002#L614-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4730#L619-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4731#L624-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5015#L629-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 5050#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 4809#L425-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 4810#L426-1 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 4857#L834 assume !(0 == start_simulation_~tmp~3#1); 4859#L834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 5024#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 4980#L425-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 5020#L426-2 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 5051#L789 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 5076#L796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5175#L797 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 5004#L847 assume !(0 != start_simulation_~tmp___0~1#1); 5005#L815-2 [2021-12-16 10:04:36,339 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:36,340 INFO L85 PathProgramCache]: Analyzing trace with hash 381143998, now seen corresponding path program 1 times [2021-12-16 10:04:36,356 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:36,356 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1738073578] [2021-12-16 10:04:36,356 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:36,356 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:36,365 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:04:36,388 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:04:36,389 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:04:36,389 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1738073578] [2021-12-16 10:04:36,389 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1738073578] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:04:36,390 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:04:36,390 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-16 10:04:36,390 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [606242306] [2021-12-16 10:04:36,391 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:04:36,391 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:04:36,392 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:36,392 INFO L85 PathProgramCache]: Analyzing trace with hash 815600463, now seen corresponding path program 3 times [2021-12-16 10:04:36,392 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:36,395 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1594894737] [2021-12-16 10:04:36,395 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:36,396 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:36,406 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:04:36,450 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:04:36,450 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:04:36,451 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1594894737] [2021-12-16 10:04:36,451 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1594894737] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:04:36,451 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:04:36,451 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:04:36,451 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1980963205] [2021-12-16 10:04:36,451 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:04:36,451 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:04:36,451 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:04:36,452 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-16 10:04:36,452 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-16 10:04:36,452 INFO L87 Difference]: Start difference. First operand 756 states and 1125 transitions. cyclomatic complexity: 371 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 2 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:04:36,481 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:04:36,481 INFO L93 Difference]: Finished difference Result 756 states and 1105 transitions. [2021-12-16 10:04:36,481 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-16 10:04:36,482 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 756 states and 1105 transitions. [2021-12-16 10:04:36,486 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 679 [2021-12-16 10:04:36,489 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 756 states to 756 states and 1105 transitions. [2021-12-16 10:04:36,489 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 756 [2021-12-16 10:04:36,489 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 756 [2021-12-16 10:04:36,489 INFO L73 IsDeterministic]: Start isDeterministic. Operand 756 states and 1105 transitions. [2021-12-16 10:04:36,490 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:04:36,490 INFO L681 BuchiCegarLoop]: Abstraction has 756 states and 1105 transitions. [2021-12-16 10:04:36,491 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 756 states and 1105 transitions. [2021-12-16 10:04:36,496 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 756 to 756. [2021-12-16 10:04:36,497 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 756 states, 756 states have (on average 1.4616402116402116) internal successors, (1105), 755 states have internal predecessors, (1105), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:04:36,503 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 756 states to 756 states and 1105 transitions. [2021-12-16 10:04:36,504 INFO L704 BuchiCegarLoop]: Abstraction has 756 states and 1105 transitions. [2021-12-16 10:04:36,504 INFO L587 BuchiCegarLoop]: Abstraction has 756 states and 1105 transitions. [2021-12-16 10:04:36,504 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2021-12-16 10:04:36,504 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 756 states and 1105 transitions. [2021-12-16 10:04:36,507 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 679 [2021-12-16 10:04:36,507 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:04:36,507 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:04:36,508 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:36,508 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:36,508 INFO L791 eck$LassoCheckResult]: Stem: 6650#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 6627#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 6423#L778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6221#L358 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6222#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 6295#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6546#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6503#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 6504#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 6531#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6513#L526 assume !(0 == ~M_E~0); 6514#L526-2 assume !(0 == ~T1_E~0); 6547#L531-1 assume !(0 == ~T2_E~0); 6499#L536-1 assume !(0 == ~T3_E~0); 6500#L541-1 assume !(0 == ~T4_E~0); 6495#L546-1 assume !(0 == ~E_M~0); 6496#L551-1 assume !(0 == ~E_1~0); 6472#L556-1 assume !(0 == ~E_2~0); 6473#L561-1 assume !(0 == ~E_3~0); 6483#L566-1 assume !(0 == ~E_4~0); 6484#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6477#L262 assume 1 == ~m_pc~0; 6478#L263 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 6633#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6340#L274 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 6341#L649 assume !(0 != activate_threads_~tmp~1#1); 6632#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6427#L281 assume !(1 == ~t1_pc~0); 6428#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 6344#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6345#L293 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 6403#L657 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 6404#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6485#L300 assume 1 == ~t2_pc~0; 6486#L301 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 6579#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6397#L312 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 6398#L665 assume !(0 != activate_threads_~tmp___1~0#1); 6275#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6276#L319 assume !(1 == ~t3_pc~0); 6234#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 6235#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6418#L331 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 6419#L673 assume !(0 != activate_threads_~tmp___2~0#1); 6255#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6256#L338 assume !(1 == ~t4_pc~0); 6318#L338-2 is_transmit4_triggered_~__retres1~4#1 := 0; 6319#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6334#L350 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6361#L681 assume !(0 != activate_threads_~tmp___3~0#1); 6199#L681-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6200#L584 assume 1 == ~M_E~0;~M_E~0 := 2; 6400#L584-2 assume !(1 == ~T1_E~0); 6359#L589-1 assume !(1 == ~T2_E~0); 6360#L594-1 assume !(1 == ~T3_E~0); 6570#L599-1 assume !(1 == ~T4_E~0); 6846#L604-1 assume !(1 == ~E_M~0); 6845#L609-1 assume 1 == ~E_1~0;~E_1~0 := 2; 6844#L614-1 assume !(1 == ~E_2~0); 6843#L619-1 assume !(1 == ~E_3~0); 6802#L624-1 assume !(1 == ~E_4~0); 6675#L629-1 assume { :end_inline_reset_delta_events } true; 6670#L815-2 [2021-12-16 10:04:36,509 INFO L793 eck$LassoCheckResult]: Loop: 6670#L815-2 assume !false; 6666#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 6665#L501 assume !false; 6664#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 6663#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 6658#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 6657#L426 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 6655#L440 assume !(0 != eval_~tmp~0#1); 6654#L516 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 6653#L358-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 6652#L526-3 assume 0 == ~M_E~0;~M_E~0 := 1; 6573#L526-5 assume !(0 == ~T1_E~0); 6335#L531-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 6336#L536-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 6227#L541-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 6228#L546-3 assume 0 == ~E_M~0;~E_M~0 := 1; 6509#L551-3 assume 0 == ~E_1~0;~E_1~0 := 1; 6458#L556-3 assume 0 == ~E_2~0;~E_2~0 := 1; 6459#L561-3 assume 0 == ~E_3~0;~E_3~0 := 1; 6553#L566-3 assume !(0 == ~E_4~0); 6349#L571-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6350#L262-18 assume !(1 == ~m_pc~0); 6440#L262-20 is_master_triggered_~__retres1~0#1 := 0; 6441#L273-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6331#L274-6 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 6332#L649-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 6240#L649-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6241#L281-18 assume !(1 == ~t1_pc~0); 6469#L281-20 is_transmit1_triggered_~__retres1~1#1 := 0; 6488#L292-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6489#L293-6 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 6593#L657-18 assume !(0 != activate_threads_~tmp___0~0#1); 6588#L657-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6589#L300-18 assume 1 == ~t2_pc~0; 6467#L301-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 6230#L311-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6292#L312-6 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 6309#L665-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 6561#L665-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6346#L319-18 assume !(1 == ~t3_pc~0); 6347#L319-20 is_transmit3_triggered_~__retres1~3#1 := 0; 6353#L330-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6369#L331-6 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 6406#L673-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 6521#L673-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6424#L338-18 assume !(1 == ~t4_pc~0); 6426#L338-20 is_transmit4_triggered_~__retres1~4#1 := 0; 6388#L349-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6389#L350-6 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6261#L681-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 6262#L681-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6446#L584-3 assume 1 == ~M_E~0;~M_E~0 := 2; 6447#L584-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 6257#L589-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 6258#L594-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 6438#L599-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 6461#L604-3 assume 1 == ~E_M~0;~E_M~0 := 2; 6462#L609-3 assume !(1 == ~E_1~0); 6520#L614-3 assume 1 == ~E_2~0;~E_2~0 := 2; 6251#L619-3 assume 1 == ~E_3~0;~E_3~0 := 2; 6252#L624-3 assume !(1 == ~E_4~0); 6532#L629-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 6556#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 6381#L425-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 6695#L426-1 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 6693#L834 assume !(0 == start_simulation_~tmp~3#1); 6431#L834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 6687#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 6684#L425-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 6682#L426-2 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 6590#L789 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 6591#L796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6678#L797 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 6676#L847 assume !(0 != start_simulation_~tmp___0~1#1); 6670#L815-2 [2021-12-16 10:04:36,509 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:36,509 INFO L85 PathProgramCache]: Analyzing trace with hash 1598746241, now seen corresponding path program 1 times [2021-12-16 10:04:36,509 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:36,510 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [277709483] [2021-12-16 10:04:36,510 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:36,510 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:36,517 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:04:36,532 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:04:36,532 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:04:36,532 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [277709483] [2021-12-16 10:04:36,533 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [277709483] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:04:36,533 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:04:36,533 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-16 10:04:36,533 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1825721531] [2021-12-16 10:04:36,533 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:04:36,533 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:04:36,534 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:36,534 INFO L85 PathProgramCache]: Analyzing trace with hash -1440969969, now seen corresponding path program 1 times [2021-12-16 10:04:36,534 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:36,534 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1756974828] [2021-12-16 10:04:36,534 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:36,535 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:36,541 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:04:36,563 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:04:36,563 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:04:36,563 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1756974828] [2021-12-16 10:04:36,564 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1756974828] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:04:36,564 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:04:36,564 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:04:36,564 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [619992945] [2021-12-16 10:04:36,564 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:04:36,564 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:04:36,565 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:04:36,565 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-16 10:04:36,565 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-16 10:04:36,565 INFO L87 Difference]: Start difference. First operand 756 states and 1105 transitions. cyclomatic complexity: 351 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 2 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:04:36,604 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:04:36,604 INFO L93 Difference]: Finished difference Result 1407 states and 2028 transitions. [2021-12-16 10:04:36,605 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-16 10:04:36,607 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1407 states and 2028 transitions. [2021-12-16 10:04:36,613 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1327 [2021-12-16 10:04:36,619 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1407 states to 1407 states and 2028 transitions. [2021-12-16 10:04:36,619 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1407 [2021-12-16 10:04:36,620 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1407 [2021-12-16 10:04:36,620 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1407 states and 2028 transitions. [2021-12-16 10:04:36,621 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:04:36,621 INFO L681 BuchiCegarLoop]: Abstraction has 1407 states and 2028 transitions. [2021-12-16 10:04:36,622 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1407 states and 2028 transitions. [2021-12-16 10:04:36,636 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1407 to 1339. [2021-12-16 10:04:36,638 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1339 states, 1339 states have (on average 1.4458551157580284) internal successors, (1936), 1338 states have internal predecessors, (1936), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:04:36,641 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1339 states to 1339 states and 1936 transitions. [2021-12-16 10:04:36,641 INFO L704 BuchiCegarLoop]: Abstraction has 1339 states and 1936 transitions. [2021-12-16 10:04:36,641 INFO L587 BuchiCegarLoop]: Abstraction has 1339 states and 1936 transitions. [2021-12-16 10:04:36,641 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2021-12-16 10:04:36,641 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1339 states and 1936 transitions. [2021-12-16 10:04:36,646 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1259 [2021-12-16 10:04:36,646 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:04:36,646 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:04:36,651 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:36,651 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:36,651 INFO L791 eck$LassoCheckResult]: Stem: 8867#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 8820#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 8604#L778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8391#L358 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 8392#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 8468#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8732#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8684#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 8685#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 8715#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8694#L526 assume !(0 == ~M_E~0); 8695#L526-2 assume !(0 == ~T1_E~0); 8733#L531-1 assume !(0 == ~T2_E~0); 8680#L536-1 assume !(0 == ~T3_E~0); 8681#L541-1 assume !(0 == ~T4_E~0); 8676#L546-1 assume !(0 == ~E_M~0); 8677#L551-1 assume !(0 == ~E_1~0); 8653#L556-1 assume !(0 == ~E_2~0); 8654#L561-1 assume !(0 == ~E_3~0); 8663#L566-1 assume !(0 == ~E_4~0); 8664#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8658#L262 assume !(1 == ~m_pc~0); 8659#L262-2 is_master_triggered_~__retres1~0#1 := 0; 8835#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8513#L274 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 8514#L649 assume !(0 != activate_threads_~tmp~1#1); 8831#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8605#L281 assume !(1 == ~t1_pc~0); 8606#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 8517#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8518#L293 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 8579#L657 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8580#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8665#L300 assume 1 == ~t2_pc~0; 8666#L301 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 8765#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8573#L312 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 8574#L665 assume !(0 != activate_threads_~tmp___1~0#1); 8446#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8447#L319 assume !(1 == ~t3_pc~0); 8404#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 8405#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8596#L331 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 8597#L673 assume !(0 != activate_threads_~tmp___2~0#1); 8426#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8427#L338 assume !(1 == ~t4_pc~0); 8490#L338-2 is_transmit4_triggered_~__retres1~4#1 := 0; 8491#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8507#L350 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8534#L681 assume !(0 != activate_threads_~tmp___3~0#1); 8369#L681-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8370#L584 assume 1 == ~M_E~0;~M_E~0 := 2; 8576#L584-2 assume !(1 == ~T1_E~0); 8532#L589-1 assume !(1 == ~T2_E~0); 8533#L594-1 assume !(1 == ~T3_E~0); 8631#L599-1 assume !(1 == ~T4_E~0); 8403#L604-1 assume !(1 == ~E_M~0); 8387#L609-1 assume 1 == ~E_1~0;~E_1~0 := 2; 8388#L614-1 assume !(1 == ~E_2~0); 8506#L619-1 assume !(1 == ~E_3~0); 8595#L624-1 assume !(1 == ~E_4~0); 8686#L629-1 assume { :end_inline_reset_delta_events } true; 8705#L815-2 [2021-12-16 10:04:36,651 INFO L793 eck$LassoCheckResult]: Loop: 8705#L815-2 assume !false; 8706#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 8821#L501 assume !false; 8818#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 8819#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 8861#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 8862#L426 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 8857#L440 assume !(0 != eval_~tmp~0#1); 8858#L516 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8825#L358-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8826#L526-3 assume 0 == ~M_E~0;~M_E~0 := 1; 9415#L526-5 assume !(0 == ~T1_E~0); 9637#L531-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 9636#L536-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 9635#L541-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 9634#L546-3 assume 0 == ~E_M~0;~E_M~0 := 1; 9633#L551-3 assume 0 == ~E_1~0;~E_1~0 := 1; 9632#L556-3 assume 0 == ~E_2~0;~E_2~0 := 1; 9631#L561-3 assume 0 == ~E_3~0;~E_3~0 := 1; 9630#L566-3 assume !(0 == ~E_4~0); 9629#L571-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9628#L262-18 assume !(1 == ~m_pc~0); 9627#L262-20 is_master_triggered_~__retres1~0#1 := 0; 9626#L273-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9625#L274-6 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 9624#L649-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 9623#L649-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9622#L281-18 assume 1 == ~t1_pc~0; 9620#L282-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 9619#L292-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9618#L293-6 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 9617#L657-18 assume !(0 != activate_threads_~tmp___0~0#1); 9616#L657-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9615#L300-18 assume 1 == ~t2_pc~0; 9613#L301-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 9612#L311-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9611#L312-6 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 9610#L665-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 9609#L665-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9608#L319-18 assume !(1 == ~t3_pc~0); 9606#L319-20 is_transmit3_triggered_~__retres1~3#1 := 0; 9605#L330-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9604#L331-6 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 9603#L673-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9602#L673-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9601#L338-18 assume !(1 == ~t4_pc~0); 9599#L338-20 is_transmit4_triggered_~__retres1~4#1 := 0; 9598#L349-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9597#L350-6 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 9596#L681-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 9595#L681-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9594#L584-3 assume 1 == ~M_E~0;~M_E~0 := 2; 8625#L584-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8775#L589-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9593#L594-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 9592#L599-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 9591#L604-3 assume 1 == ~E_M~0;~E_M~0 := 2; 9590#L609-3 assume !(1 == ~E_1~0); 9589#L614-3 assume 1 == ~E_2~0;~E_2~0 := 2; 9588#L619-3 assume 1 == ~E_3~0;~E_3~0 := 2; 9587#L624-3 assume !(1 == ~E_4~0); 9586#L629-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 9584#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 9580#L425-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 9579#L426-1 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 9578#L834 assume !(0 == start_simulation_~tmp~3#1); 8610#L834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 9484#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 9481#L425-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 9480#L426-2 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 9479#L789 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 9476#L796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 9474#L797 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 9473#L847 assume !(0 != start_simulation_~tmp___0~1#1); 8705#L815-2 [2021-12-16 10:04:36,652 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:36,652 INFO L85 PathProgramCache]: Analyzing trace with hash 1113571522, now seen corresponding path program 1 times [2021-12-16 10:04:36,652 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:36,652 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [917108904] [2021-12-16 10:04:36,652 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:36,653 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:36,658 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:04:36,681 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:04:36,681 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:04:36,681 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [917108904] [2021-12-16 10:04:36,681 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [917108904] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:04:36,682 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:04:36,682 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-16 10:04:36,683 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1147171906] [2021-12-16 10:04:36,683 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:04:36,683 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:04:36,683 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:36,684 INFO L85 PathProgramCache]: Analyzing trace with hash 452472206, now seen corresponding path program 1 times [2021-12-16 10:04:36,684 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:36,687 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2081163234] [2021-12-16 10:04:36,687 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:36,687 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:36,694 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:04:36,710 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:04:36,711 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:04:36,712 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2081163234] [2021-12-16 10:04:36,712 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2081163234] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:04:36,713 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:04:36,713 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:04:36,713 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1538187666] [2021-12-16 10:04:36,713 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:04:36,714 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:04:36,714 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:04:36,714 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-16 10:04:36,714 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-16 10:04:36,714 INFO L87 Difference]: Start difference. First operand 1339 states and 1936 transitions. cyclomatic complexity: 601 Second operand has 5 states, 5 states have (on average 12.4) internal successors, (62), 5 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:04:36,858 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:04:36,858 INFO L93 Difference]: Finished difference Result 3579 states and 5152 transitions. [2021-12-16 10:04:36,858 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-16 10:04:36,859 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3579 states and 5152 transitions. [2021-12-16 10:04:36,876 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3402 [2021-12-16 10:04:36,889 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3579 states to 3579 states and 5152 transitions. [2021-12-16 10:04:36,889 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3579 [2021-12-16 10:04:36,891 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3579 [2021-12-16 10:04:36,891 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3579 states and 5152 transitions. [2021-12-16 10:04:36,895 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:04:36,895 INFO L681 BuchiCegarLoop]: Abstraction has 3579 states and 5152 transitions. [2021-12-16 10:04:36,896 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3579 states and 5152 transitions. [2021-12-16 10:04:36,914 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3579 to 1414. [2021-12-16 10:04:36,916 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1414 states, 1414 states have (on average 1.4222065063649223) internal successors, (2011), 1413 states have internal predecessors, (2011), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:04:36,918 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1414 states to 1414 states and 2011 transitions. [2021-12-16 10:04:36,919 INFO L704 BuchiCegarLoop]: Abstraction has 1414 states and 2011 transitions. [2021-12-16 10:04:36,919 INFO L587 BuchiCegarLoop]: Abstraction has 1414 states and 2011 transitions. [2021-12-16 10:04:36,919 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2021-12-16 10:04:36,919 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1414 states and 2011 transitions. [2021-12-16 10:04:36,925 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1331 [2021-12-16 10:04:36,925 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:04:36,925 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:04:36,925 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:36,926 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:36,926 INFO L791 eck$LassoCheckResult]: Stem: 13853#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 13791#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 13535#L778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 13322#L358 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 13323#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 13398#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 13683#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 13625#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 13626#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 13660#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 13636#L526 assume !(0 == ~M_E~0); 13637#L526-2 assume !(0 == ~T1_E~0); 13684#L531-1 assume !(0 == ~T2_E~0); 13621#L536-1 assume !(0 == ~T3_E~0); 13622#L541-1 assume !(0 == ~T4_E~0); 13617#L546-1 assume !(0 == ~E_M~0); 13618#L551-1 assume !(0 == ~E_1~0); 13592#L556-1 assume !(0 == ~E_2~0); 13593#L561-1 assume !(0 == ~E_3~0); 13602#L566-1 assume !(0 == ~E_4~0); 13603#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13597#L262 assume !(1 == ~m_pc~0); 13598#L262-2 is_master_triggered_~__retres1~0#1 := 0; 13804#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13444#L274 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 13445#L649 assume !(0 != activate_threads_~tmp~1#1); 13801#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13539#L281 assume !(1 == ~t1_pc~0); 13540#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 13448#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13449#L293 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 13512#L657 assume !(0 != activate_threads_~tmp___0~0#1); 13513#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13604#L300 assume 1 == ~t2_pc~0; 13605#L301 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 13725#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13505#L312 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 13506#L665 assume !(0 != activate_threads_~tmp___1~0#1); 13377#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 13378#L319 assume !(1 == ~t3_pc~0); 13335#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 13336#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13529#L331 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 13530#L673 assume !(0 != activate_threads_~tmp___2~0#1); 13357#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13358#L338 assume !(1 == ~t4_pc~0); 13421#L338-2 is_transmit4_triggered_~__retres1~4#1 := 0; 13422#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13438#L350 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 13465#L681 assume !(0 != activate_threads_~tmp___3~0#1); 13300#L681-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13301#L584 assume 1 == ~M_E~0;~M_E~0 := 2; 13508#L584-2 assume !(1 == ~T1_E~0); 13509#L589-1 assume !(1 == ~T2_E~0); 13997#L594-1 assume !(1 == ~T3_E~0); 13995#L599-1 assume !(1 == ~T4_E~0); 13334#L604-1 assume !(1 == ~E_M~0); 13318#L609-1 assume 1 == ~E_1~0;~E_1~0 := 2; 13319#L614-1 assume !(1 == ~E_2~0); 13437#L619-1 assume !(1 == ~E_3~0); 13528#L624-1 assume !(1 == ~E_4~0); 13627#L629-1 assume { :end_inline_reset_delta_events } true; 13826#L815-2 [2021-12-16 10:04:36,926 INFO L793 eck$LassoCheckResult]: Loop: 13826#L815-2 assume !false; 13948#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 13946#L501 assume !false; 13944#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 13938#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 13932#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 13930#L426 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 13926#L440 assume !(0 != eval_~tmp~0#1); 13924#L516 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 13922#L358-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 13919#L526-3 assume 0 == ~M_E~0;~M_E~0 := 1; 13915#L526-5 assume !(0 == ~T1_E~0); 13916#L531-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 13907#L536-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 13908#L541-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 13897#L546-3 assume 0 == ~E_M~0;~E_M~0 := 1; 13898#L551-3 assume 0 == ~E_1~0;~E_1~0 := 1; 13887#L556-3 assume 0 == ~E_2~0;~E_2~0 := 1; 13888#L561-3 assume 0 == ~E_3~0;~E_3~0 := 1; 14353#L566-3 assume !(0 == ~E_4~0); 14331#L571-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13713#L262-18 assume !(1 == ~m_pc~0); 13714#L262-20 is_master_triggered_~__retres1~0#1 := 0; 14449#L273-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14448#L274-6 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 14447#L649-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 14446#L649-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14445#L281-18 assume !(1 == ~t1_pc~0); 14443#L281-20 is_transmit1_triggered_~__retres1~1#1 := 0; 14441#L292-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14439#L293-6 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 14437#L657-18 assume !(0 != activate_threads_~tmp___0~0#1); 14435#L657-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14432#L300-18 assume 1 == ~t2_pc~0; 14429#L301-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 14427#L311-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14425#L312-6 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 14423#L665-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 14421#L665-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14418#L319-18 assume 1 == ~t3_pc~0; 14416#L320-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 14413#L330-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14411#L331-6 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 14409#L673-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 14388#L673-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14298#L338-18 assume !(1 == ~t4_pc~0); 14290#L338-20 is_transmit4_triggered_~__retres1~4#1 := 0; 14285#L349-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14281#L350-6 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 14277#L681-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 14272#L681-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14266#L584-3 assume 1 == ~M_E~0;~M_E~0 := 2; 14193#L584-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 14190#L589-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 14257#L594-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 14251#L599-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 14245#L604-3 assume 1 == ~E_M~0;~E_M~0 := 2; 14241#L609-3 assume !(1 == ~E_1~0); 14236#L614-3 assume 1 == ~E_2~0;~E_2~0 := 2; 13917#L619-3 assume 1 == ~E_3~0;~E_3~0 := 2; 13913#L624-3 assume !(1 == ~E_4~0); 13909#L629-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 13910#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 14106#L425-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 14104#L426-1 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 14102#L834 assume !(0 == start_simulation_~tmp~3#1); 14099#L834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 14020#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 14016#L425-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 14014#L426-2 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 14012#L789 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 14011#L796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 14008#L797 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 13975#L847 assume !(0 != start_simulation_~tmp___0~1#1); 13826#L815-2 [2021-12-16 10:04:36,927 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:36,927 INFO L85 PathProgramCache]: Analyzing trace with hash 1815171396, now seen corresponding path program 1 times [2021-12-16 10:04:36,927 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:36,927 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [671741785] [2021-12-16 10:04:36,927 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:36,927 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:36,932 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:04:36,949 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:04:36,950 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:04:36,950 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [671741785] [2021-12-16 10:04:36,950 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [671741785] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:04:36,950 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:04:36,950 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:04:36,950 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [725842122] [2021-12-16 10:04:36,950 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:04:36,951 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:04:36,951 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:36,951 INFO L85 PathProgramCache]: Analyzing trace with hash 1802548238, now seen corresponding path program 1 times [2021-12-16 10:04:36,951 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:36,951 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1782473985] [2021-12-16 10:04:36,952 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:36,952 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:36,962 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:04:36,972 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:04:36,972 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:04:36,972 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1782473985] [2021-12-16 10:04:36,975 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1782473985] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:04:36,975 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:04:36,975 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:04:36,975 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [253574650] [2021-12-16 10:04:36,975 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:04:36,976 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:04:36,976 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:04:36,976 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-16 10:04:36,976 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-16 10:04:36,976 INFO L87 Difference]: Start difference. First operand 1414 states and 2011 transitions. cyclomatic complexity: 601 Second operand has 4 states, 4 states have (on average 15.5) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:04:37,086 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:04:37,087 INFO L93 Difference]: Finished difference Result 3573 states and 5021 transitions. [2021-12-16 10:04:37,087 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-16 10:04:37,088 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3573 states and 5021 transitions. [2021-12-16 10:04:37,108 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 3455 [2021-12-16 10:04:37,121 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3573 states to 3573 states and 5021 transitions. [2021-12-16 10:04:37,121 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3573 [2021-12-16 10:04:37,125 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3573 [2021-12-16 10:04:37,125 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3573 states and 5021 transitions. [2021-12-16 10:04:37,129 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:04:37,129 INFO L681 BuchiCegarLoop]: Abstraction has 3573 states and 5021 transitions. [2021-12-16 10:04:37,130 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3573 states and 5021 transitions. [2021-12-16 10:04:37,195 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3573 to 3461. [2021-12-16 10:04:37,200 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3461 states, 3461 states have (on average 1.4102860444958105) internal successors, (4881), 3460 states have internal predecessors, (4881), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:04:37,206 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3461 states to 3461 states and 4881 transitions. [2021-12-16 10:04:37,207 INFO L704 BuchiCegarLoop]: Abstraction has 3461 states and 4881 transitions. [2021-12-16 10:04:37,207 INFO L587 BuchiCegarLoop]: Abstraction has 3461 states and 4881 transitions. [2021-12-16 10:04:37,207 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2021-12-16 10:04:37,207 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3461 states and 4881 transitions. [2021-12-16 10:04:37,215 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 3367 [2021-12-16 10:04:37,215 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:04:37,215 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:04:37,216 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:37,216 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:37,216 INFO L791 eck$LassoCheckResult]: Stem: 18832#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 18780#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 18538#L778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 18317#L358 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 18318#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 18392#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 18676#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 18623#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 18624#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 18657#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 18634#L526 assume !(0 == ~M_E~0); 18635#L526-2 assume !(0 == ~T1_E~0); 18680#L531-1 assume !(0 == ~T2_E~0); 18619#L536-1 assume !(0 == ~T3_E~0); 18620#L541-1 assume !(0 == ~T4_E~0); 18615#L546-1 assume !(0 == ~E_M~0); 18616#L551-1 assume !(0 == ~E_1~0); 18589#L556-1 assume !(0 == ~E_2~0); 18590#L561-1 assume !(0 == ~E_3~0); 18599#L566-1 assume !(0 == ~E_4~0); 18600#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 18594#L262 assume !(1 == ~m_pc~0); 18595#L262-2 is_master_triggered_~__retres1~0#1 := 0; 18791#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 18440#L274 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 18441#L649 assume !(0 != activate_threads_~tmp~1#1); 18790#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 18539#L281 assume !(1 == ~t1_pc~0); 18540#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 18444#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18445#L293 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 18509#L657 assume !(0 != activate_threads_~tmp___0~0#1); 18510#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18603#L300 assume !(1 == ~t2_pc~0); 18604#L300-2 is_transmit2_triggered_~__retres1~2#1 := 0; 18719#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 18502#L312 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 18503#L665 assume !(0 != activate_threads_~tmp___1~0#1); 18371#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18372#L319 assume !(1 == ~t3_pc~0); 18331#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 18332#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18529#L331 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 18530#L673 assume !(0 != activate_threads_~tmp___2~0#1); 18351#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 18352#L338 assume !(1 == ~t4_pc~0); 18416#L338-2 is_transmit4_triggered_~__retres1~4#1 := 0; 18417#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 18436#L350 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 18461#L681 assume !(0 != activate_threads_~tmp___3~0#1); 18297#L681-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 18298#L584 assume 1 == ~M_E~0;~M_E~0 := 2; 18786#L584-2 assume !(1 == ~T1_E~0); 18459#L589-1 assume !(1 == ~T2_E~0); 18460#L594-1 assume !(1 == ~T3_E~0); 18707#L599-1 assume !(1 == ~T4_E~0); 18329#L604-1 assume !(1 == ~E_M~0); 18330#L609-1 assume 1 == ~E_1~0;~E_1~0 := 2; 18432#L614-1 assume !(1 == ~E_2~0); 18433#L619-1 assume !(1 == ~E_3~0); 18528#L624-1 assume !(1 == ~E_4~0); 18810#L629-1 assume { :end_inline_reset_delta_events } true; 18645#L815-2 [2021-12-16 10:04:37,216 INFO L793 eck$LassoCheckResult]: Loop: 18645#L815-2 assume !false; 18646#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 18765#L501 assume !false; 18777#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 18778#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 18438#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 18649#L426 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 18650#L440 assume !(0 != eval_~tmp~0#1); 18820#L516 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 20881#L358-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 20879#L526-3 assume 0 == ~M_E~0;~M_E~0 := 1; 20877#L526-5 assume !(0 == ~T1_E~0); 20876#L531-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 20874#L536-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 20872#L541-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 20870#L546-3 assume 0 == ~E_M~0;~E_M~0 := 1; 20868#L551-3 assume 0 == ~E_1~0;~E_1~0 := 1; 20866#L556-3 assume 0 == ~E_2~0;~E_2~0 := 1; 20863#L561-3 assume 0 == ~E_3~0;~E_3~0 := 1; 20861#L566-3 assume !(0 == ~E_4~0); 20859#L571-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20857#L262-18 assume !(1 == ~m_pc~0); 20855#L262-20 is_master_triggered_~__retres1~0#1 := 0; 20852#L273-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 20850#L274-6 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 20848#L649-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 20846#L649-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 20844#L281-18 assume !(1 == ~t1_pc~0); 20842#L281-20 is_transmit1_triggered_~__retres1~1#1 := 0; 20839#L292-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 20838#L293-6 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 20837#L657-18 assume !(0 != activate_threads_~tmp___0~0#1); 20836#L657-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18755#L300-18 assume !(1 == ~t2_pc~0); 18325#L300-20 is_transmit2_triggered_~__retres1~2#1 := 0; 18326#L311-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20922#L312-6 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 18696#L665-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 18697#L665-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18446#L319-18 assume 1 == ~t3_pc~0; 18448#L320-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 18453#L330-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18470#L331-6 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 18511#L673-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 18644#L673-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 18535#L338-18 assume !(1 == ~t4_pc~0); 18537#L338-20 is_transmit4_triggered_~__retres1~4#1 := 0; 18487#L349-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 18488#L350-6 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 18779#L681-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 18607#L681-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 18555#L584-3 assume 1 == ~M_E~0;~M_E~0 := 2; 18556#L584-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 18353#L589-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 18354#L594-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 18549#L599-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 18575#L604-3 assume 1 == ~E_M~0;~E_M~0 := 2; 18576#L609-3 assume !(1 == ~E_1~0); 18643#L614-3 assume 1 == ~E_2~0;~E_2~0 := 2; 18346#L619-3 assume 1 == ~E_3~0;~E_3~0 := 2; 18347#L624-3 assume !(1 == ~E_4~0); 18656#L629-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 18690#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 18424#L425-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 18425#L426-1 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 18477#L834 assume !(0 == start_simulation_~tmp~3#1); 18479#L834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 18666#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 18618#L425-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 18660#L426-2 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 18701#L789 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 18730#L796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 18627#L797 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 18628#L847 assume !(0 != start_simulation_~tmp___0~1#1); 18645#L815-2 [2021-12-16 10:04:37,217 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:37,217 INFO L85 PathProgramCache]: Analyzing trace with hash 843496709, now seen corresponding path program 1 times [2021-12-16 10:04:37,217 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:37,217 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [708264363] [2021-12-16 10:04:37,217 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:37,217 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:37,224 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:04:37,236 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:04:37,236 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:04:37,236 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [708264363] [2021-12-16 10:04:37,236 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [708264363] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:04:37,237 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:04:37,237 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-16 10:04:37,237 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [550087556] [2021-12-16 10:04:37,237 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:04:37,237 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:04:37,237 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:37,237 INFO L85 PathProgramCache]: Analyzing trace with hash 1317373519, now seen corresponding path program 1 times [2021-12-16 10:04:37,238 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:37,238 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [173461959] [2021-12-16 10:04:37,238 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:37,238 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:37,242 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:04:37,255 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:04:37,255 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:04:37,255 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [173461959] [2021-12-16 10:04:37,255 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [173461959] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:04:37,255 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:04:37,255 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:04:37,255 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1806995668] [2021-12-16 10:04:37,256 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:04:37,256 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:04:37,256 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:04:37,256 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-16 10:04:37,256 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-16 10:04:37,257 INFO L87 Difference]: Start difference. First operand 3461 states and 4881 transitions. cyclomatic complexity: 1428 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 2 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:04:37,286 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:04:37,287 INFO L93 Difference]: Finished difference Result 5071 states and 7157 transitions. [2021-12-16 10:04:37,287 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-16 10:04:37,287 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5071 states and 7157 transitions. [2021-12-16 10:04:37,306 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 4968 [2021-12-16 10:04:37,323 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5071 states to 5071 states and 7157 transitions. [2021-12-16 10:04:37,323 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5071 [2021-12-16 10:04:37,327 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5071 [2021-12-16 10:04:37,327 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5071 states and 7157 transitions. [2021-12-16 10:04:37,331 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:04:37,331 INFO L681 BuchiCegarLoop]: Abstraction has 5071 states and 7157 transitions. [2021-12-16 10:04:37,334 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5071 states and 7157 transitions. [2021-12-16 10:04:37,369 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5071 to 3511. [2021-12-16 10:04:37,373 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3511 states, 3511 states have (on average 1.4138422101965251) internal successors, (4964), 3510 states have internal predecessors, (4964), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:04:37,379 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3511 states to 3511 states and 4964 transitions. [2021-12-16 10:04:37,380 INFO L704 BuchiCegarLoop]: Abstraction has 3511 states and 4964 transitions. [2021-12-16 10:04:37,380 INFO L587 BuchiCegarLoop]: Abstraction has 3511 states and 4964 transitions. [2021-12-16 10:04:37,380 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2021-12-16 10:04:37,380 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3511 states and 4964 transitions. [2021-12-16 10:04:37,389 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3427 [2021-12-16 10:04:37,389 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:04:37,389 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:04:37,390 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:37,390 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:37,390 INFO L791 eck$LassoCheckResult]: Stem: 27320#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 27282#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 27065#L778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 26856#L358 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 26857#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 26929#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 27188#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 27139#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 27140#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 27171#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 27150#L526 assume !(0 == ~M_E~0); 27151#L526-2 assume !(0 == ~T1_E~0); 27190#L531-1 assume !(0 == ~T2_E~0); 27135#L536-1 assume !(0 == ~T3_E~0); 27136#L541-1 assume !(0 == ~T4_E~0); 27131#L546-1 assume !(0 == ~E_M~0); 27132#L551-1 assume !(0 == ~E_1~0); 27110#L556-1 assume !(0 == ~E_2~0); 27111#L561-1 assume !(0 == ~E_3~0); 27120#L566-1 assume !(0 == ~E_4~0); 27121#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 27115#L262 assume !(1 == ~m_pc~0); 27116#L262-2 is_master_triggered_~__retres1~0#1 := 0; 27288#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 26977#L274 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 26978#L649 assume !(0 != activate_threads_~tmp~1#1); 27287#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 27066#L281 assume !(1 == ~t1_pc~0); 27067#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 26979#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 26980#L293 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 27038#L657 assume !(0 != activate_threads_~tmp___0~0#1); 27039#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 27122#L300 assume !(1 == ~t2_pc~0); 27123#L300-2 is_transmit2_triggered_~__retres1~2#1 := 0; 27224#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 27032#L312 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 27033#L665 assume !(0 != activate_threads_~tmp___1~0#1); 26910#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 26911#L319 assume !(1 == ~t3_pc~0); 26869#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 26870#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 27056#L331 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 27057#L673 assume !(0 != activate_threads_~tmp___2~0#1); 26890#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 26891#L338 assume !(1 == ~t4_pc~0); 26953#L338-2 is_transmit4_triggered_~__retres1~4#1 := 0; 26954#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 26971#L350 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 26996#L681 assume !(0 != activate_threads_~tmp___3~0#1); 26836#L681-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 26837#L584 assume !(1 == ~M_E~0); 27035#L584-2 assume !(1 == ~T1_E~0); 26994#L589-1 assume !(1 == ~T2_E~0); 26995#L594-1 assume !(1 == ~T3_E~0); 27091#L599-1 assume !(1 == ~T4_E~0); 26868#L604-1 assume !(1 == ~E_M~0); 26852#L609-1 assume 1 == ~E_1~0;~E_1~0 := 2; 26853#L614-1 assume !(1 == ~E_2~0); 26968#L619-1 assume !(1 == ~E_3~0); 27055#L624-1 assume !(1 == ~E_4~0); 27141#L629-1 assume { :end_inline_reset_delta_events } true; 27302#L815-2 [2021-12-16 10:04:37,390 INFO L793 eck$LassoCheckResult]: Loop: 27302#L815-2 assume !false; 29272#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 29271#L501 assume !false; 29270#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 29269#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 29264#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 29263#L426 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 29262#L440 assume !(0 != eval_~tmp~0#1); 27303#L516 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 27285#L358-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 27089#L526-3 assume !(0 == ~M_E~0); 27090#L526-5 assume !(0 == ~T1_E~0); 26969#L531-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 26970#L536-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 26864#L541-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 26865#L546-3 assume 0 == ~E_M~0;~E_M~0 := 1; 27145#L551-3 assume 0 == ~E_1~0;~E_1~0 := 1; 27097#L556-3 assume 0 == ~E_2~0;~E_2~0 := 1; 27098#L561-3 assume 0 == ~E_3~0;~E_3~0 := 1; 27195#L566-3 assume !(0 == ~E_4~0); 26984#L571-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 26985#L262-18 assume !(1 == ~m_pc~0); 27079#L262-20 is_master_triggered_~__retres1~0#1 := 0; 27080#L273-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 26966#L274-6 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 26967#L649-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 26875#L649-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26876#L281-18 assume !(1 == ~t1_pc~0); 27108#L281-20 is_transmit1_triggered_~__retres1~1#1 := 0; 30343#L292-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 30342#L293-6 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 30340#L657-18 assume !(0 != activate_threads_~tmp___0~0#1); 27235#L657-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 27236#L300-18 assume !(1 == ~t2_pc~0); 27261#L300-20 is_transmit2_triggered_~__retres1~2#1 := 0; 30337#L311-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 30336#L312-6 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 30335#L665-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 30334#L665-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 30333#L319-18 assume !(1 == ~t3_pc~0); 30331#L319-20 is_transmit3_triggered_~__retres1~3#1 := 0; 30330#L330-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 30328#L331-6 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 30325#L673-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 30312#L673-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 30310#L338-18 assume !(1 == ~t4_pc~0); 30306#L338-20 is_transmit4_triggered_~__retres1~4#1 := 0; 30303#L349-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 27280#L350-6 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 27281#L681-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 30294#L681-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 30293#L584-3 assume !(1 == ~M_E~0); 28076#L584-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 30174#L589-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 30173#L594-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 30075#L599-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 30074#L604-3 assume 1 == ~E_M~0;~E_M~0 := 2; 27306#L609-3 assume !(1 == ~E_1~0); 27157#L614-3 assume 1 == ~E_2~0;~E_2~0 := 2; 26886#L619-3 assume 1 == ~E_3~0;~E_3~0 := 2; 26887#L624-3 assume !(1 == ~E_4~0); 27170#L629-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 27200#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 26961#L425-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 26962#L426-1 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 27010#L834 assume !(0 == start_simulation_~tmp~3#1); 27012#L834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 29309#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 29304#L425-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 29301#L426-2 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 29298#L789 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 29293#L796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 29287#L797 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 29282#L847 assume !(0 != start_simulation_~tmp___0~1#1); 27302#L815-2 [2021-12-16 10:04:37,391 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:37,391 INFO L85 PathProgramCache]: Analyzing trace with hash 1544561287, now seen corresponding path program 1 times [2021-12-16 10:04:37,391 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:37,391 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1326000807] [2021-12-16 10:04:37,391 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:37,391 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:37,395 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:04:37,451 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:04:37,451 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:04:37,451 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1326000807] [2021-12-16 10:04:37,451 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1326000807] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:04:37,452 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:04:37,452 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-16 10:04:37,452 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1190780245] [2021-12-16 10:04:37,452 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:04:37,452 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:04:37,452 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:37,452 INFO L85 PathProgramCache]: Analyzing trace with hash 508991376, now seen corresponding path program 1 times [2021-12-16 10:04:37,453 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:37,453 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1619583449] [2021-12-16 10:04:37,453 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:37,453 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:37,457 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:04:37,467 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:04:37,467 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:04:37,467 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1619583449] [2021-12-16 10:04:37,468 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1619583449] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:04:37,468 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:04:37,468 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:04:37,468 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [711972760] [2021-12-16 10:04:37,468 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:04:37,468 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:04:37,468 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:04:37,469 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-16 10:04:37,469 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-16 10:04:37,469 INFO L87 Difference]: Start difference. First operand 3511 states and 4964 transitions. cyclomatic complexity: 1457 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 2 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:04:37,497 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:04:37,497 INFO L93 Difference]: Finished difference Result 3391 states and 4726 transitions. [2021-12-16 10:04:37,497 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-16 10:04:37,498 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3391 states and 4726 transitions. [2021-12-16 10:04:37,510 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3307 [2021-12-16 10:04:37,521 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3391 states to 3391 states and 4726 transitions. [2021-12-16 10:04:37,521 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3391 [2021-12-16 10:04:37,523 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3391 [2021-12-16 10:04:37,524 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3391 states and 4726 transitions. [2021-12-16 10:04:37,526 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:04:37,527 INFO L681 BuchiCegarLoop]: Abstraction has 3391 states and 4726 transitions. [2021-12-16 10:04:37,528 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3391 states and 4726 transitions. [2021-12-16 10:04:37,556 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3391 to 3391. [2021-12-16 10:04:37,560 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3391 states, 3391 states have (on average 1.3936891772338542) internal successors, (4726), 3390 states have internal predecessors, (4726), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:04:37,566 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3391 states to 3391 states and 4726 transitions. [2021-12-16 10:04:37,566 INFO L704 BuchiCegarLoop]: Abstraction has 3391 states and 4726 transitions. [2021-12-16 10:04:37,566 INFO L587 BuchiCegarLoop]: Abstraction has 3391 states and 4726 transitions. [2021-12-16 10:04:37,566 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2021-12-16 10:04:37,566 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3391 states and 4726 transitions. [2021-12-16 10:04:37,574 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3307 [2021-12-16 10:04:37,574 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:04:37,574 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:04:37,575 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:37,575 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:37,575 INFO L791 eck$LassoCheckResult]: Stem: 34229#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 34190#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 33972#L778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 33765#L358 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 33766#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 33839#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 34101#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 34052#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 34053#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 34084#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 34063#L526 assume !(0 == ~M_E~0); 34064#L526-2 assume !(0 == ~T1_E~0); 34103#L531-1 assume !(0 == ~T2_E~0); 34048#L536-1 assume !(0 == ~T3_E~0); 34049#L541-1 assume !(0 == ~T4_E~0); 34044#L546-1 assume !(0 == ~E_M~0); 34045#L551-1 assume !(0 == ~E_1~0); 34022#L556-1 assume !(0 == ~E_2~0); 34023#L561-1 assume !(0 == ~E_3~0); 34032#L566-1 assume !(0 == ~E_4~0); 34033#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 34027#L262 assume !(1 == ~m_pc~0); 34028#L262-2 is_master_triggered_~__retres1~0#1 := 0; 34197#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 33885#L274 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 33886#L649 assume !(0 != activate_threads_~tmp~1#1); 34196#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 33973#L281 assume !(1 == ~t1_pc~0); 33974#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 33887#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 33888#L293 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 33947#L657 assume !(0 != activate_threads_~tmp___0~0#1); 33948#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 34034#L300 assume !(1 == ~t2_pc~0); 34035#L300-2 is_transmit2_triggered_~__retres1~2#1 := 0; 34138#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 33941#L312 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 33942#L665 assume !(0 != activate_threads_~tmp___1~0#1); 33818#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 33819#L319 assume !(1 == ~t3_pc~0); 33778#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 33779#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 33964#L331 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 33965#L673 assume !(0 != activate_threads_~tmp___2~0#1); 33798#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 33799#L338 assume !(1 == ~t4_pc~0); 33861#L338-2 is_transmit4_triggered_~__retres1~4#1 := 0; 33862#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 33879#L350 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 33906#L681 assume !(0 != activate_threads_~tmp___3~0#1); 33745#L681-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 33746#L584 assume !(1 == ~M_E~0); 33944#L584-2 assume !(1 == ~T1_E~0); 33904#L589-1 assume !(1 == ~T2_E~0); 33905#L594-1 assume !(1 == ~T3_E~0); 33997#L599-1 assume !(1 == ~T4_E~0); 33777#L604-1 assume !(1 == ~E_M~0); 33761#L609-1 assume !(1 == ~E_1~0); 33762#L614-1 assume !(1 == ~E_2~0); 33876#L619-1 assume !(1 == ~E_3~0); 33963#L624-1 assume !(1 == ~E_4~0); 34054#L629-1 assume { :end_inline_reset_delta_events } true; 34210#L815-2 [2021-12-16 10:04:37,576 INFO L793 eck$LassoCheckResult]: Loop: 34210#L815-2 assume !false; 36185#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 36180#L501 assume !false; 36176#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 36021#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 36015#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 36012#L426 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 36009#L440 assume !(0 != eval_~tmp~0#1); 36010#L516 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 36166#L358-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 36161#L526-3 assume !(0 == ~M_E~0); 36157#L526-5 assume !(0 == ~T1_E~0); 36153#L531-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 36149#L536-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 36144#L541-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 36139#L546-3 assume 0 == ~E_M~0;~E_M~0 := 1; 36134#L551-3 assume !(0 == ~E_1~0); 36128#L556-3 assume 0 == ~E_2~0;~E_2~0 := 1; 36124#L561-3 assume 0 == ~E_3~0;~E_3~0 := 1; 36122#L566-3 assume !(0 == ~E_4~0); 36121#L571-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 36120#L262-18 assume !(1 == ~m_pc~0); 36119#L262-20 is_master_triggered_~__retres1~0#1 := 0; 36118#L273-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 36117#L274-6 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 36115#L649-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 36113#L649-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 36111#L281-18 assume !(1 == ~t1_pc~0); 36109#L281-20 is_transmit1_triggered_~__retres1~1#1 := 0; 36107#L292-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 36105#L293-6 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 36102#L657-18 assume !(0 != activate_threads_~tmp___0~0#1); 36100#L657-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 36098#L300-18 assume !(1 == ~t2_pc~0); 36096#L300-20 is_transmit2_triggered_~__retres1~2#1 := 0; 36094#L311-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 36092#L312-6 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 36090#L665-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 36089#L665-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 36087#L319-18 assume !(1 == ~t3_pc~0); 36084#L319-20 is_transmit3_triggered_~__retres1~3#1 := 0; 36082#L330-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 36080#L331-6 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 36078#L673-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 36077#L673-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 36076#L338-18 assume !(1 == ~t4_pc~0); 36057#L338-20 is_transmit4_triggered_~__retres1~4#1 := 0; 36052#L349-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 36048#L350-6 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 36044#L681-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 36039#L681-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 35959#L584-3 assume !(1 == ~M_E~0); 35955#L584-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 35953#L589-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 35950#L594-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 35948#L599-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 35946#L604-3 assume 1 == ~E_M~0;~E_M~0 := 2; 35945#L609-3 assume !(1 == ~E_1~0); 35944#L614-3 assume 1 == ~E_2~0;~E_2~0 := 2; 35942#L619-3 assume 1 == ~E_3~0;~E_3~0 := 2; 35940#L624-3 assume !(1 == ~E_4~0); 35938#L629-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 35934#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 35929#L425-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 35927#L426-1 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 35924#L834 assume !(0 == start_simulation_~tmp~3#1); 35925#L834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 36236#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 36229#L425-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 36224#L426-2 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 36219#L789 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 36211#L796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 36204#L797 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 36199#L847 assume !(0 != start_simulation_~tmp___0~1#1); 34210#L815-2 [2021-12-16 10:04:37,576 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:37,576 INFO L85 PathProgramCache]: Analyzing trace with hash 1546408329, now seen corresponding path program 1 times [2021-12-16 10:04:37,576 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:37,576 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1339297367] [2021-12-16 10:04:37,576 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:37,577 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:37,581 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:04:37,581 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-16 10:04:37,585 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:04:37,604 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-16 10:04:37,605 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:37,605 INFO L85 PathProgramCache]: Analyzing trace with hash 942720462, now seen corresponding path program 1 times [2021-12-16 10:04:37,605 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:37,605 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [535138336] [2021-12-16 10:04:37,605 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:37,606 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:37,611 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:04:37,630 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:04:37,630 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:04:37,631 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [535138336] [2021-12-16 10:04:37,631 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [535138336] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:04:37,631 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:04:37,631 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-16 10:04:37,631 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2141396732] [2021-12-16 10:04:37,631 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:04:37,631 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:04:37,632 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:04:37,632 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-16 10:04:37,632 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-16 10:04:37,632 INFO L87 Difference]: Start difference. First operand 3391 states and 4726 transitions. cyclomatic complexity: 1339 Second operand has 5 states, 5 states have (on average 14.8) internal successors, (74), 5 states have internal predecessors, (74), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:04:37,699 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:04:37,699 INFO L93 Difference]: Finished difference Result 5980 states and 8217 transitions. [2021-12-16 10:04:37,699 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2021-12-16 10:04:37,700 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5980 states and 8217 transitions. [2021-12-16 10:04:37,748 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 5876 [2021-12-16 10:04:37,765 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5980 states to 5980 states and 8217 transitions. [2021-12-16 10:04:37,765 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5980 [2021-12-16 10:04:37,768 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5980 [2021-12-16 10:04:37,769 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5980 states and 8217 transitions. [2021-12-16 10:04:37,775 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:04:37,775 INFO L681 BuchiCegarLoop]: Abstraction has 5980 states and 8217 transitions. [2021-12-16 10:04:37,778 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5980 states and 8217 transitions. [2021-12-16 10:04:37,820 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5980 to 3427. [2021-12-16 10:04:37,824 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3427 states, 3427 states have (on average 1.3895535453749635) internal successors, (4762), 3426 states have internal predecessors, (4762), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:04:37,830 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3427 states to 3427 states and 4762 transitions. [2021-12-16 10:04:37,831 INFO L704 BuchiCegarLoop]: Abstraction has 3427 states and 4762 transitions. [2021-12-16 10:04:37,831 INFO L587 BuchiCegarLoop]: Abstraction has 3427 states and 4762 transitions. [2021-12-16 10:04:37,831 INFO L425 BuchiCegarLoop]: ======== Iteration 13============ [2021-12-16 10:04:37,831 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3427 states and 4762 transitions. [2021-12-16 10:04:37,839 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3343 [2021-12-16 10:04:37,839 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:04:37,839 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:04:37,840 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:37,840 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:37,840 INFO L791 eck$LassoCheckResult]: Stem: 43616#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 43582#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 43360#L778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 43152#L358 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 43153#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 43227#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 43494#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 43442#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 43443#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 43475#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 43453#L526 assume !(0 == ~M_E~0); 43454#L526-2 assume !(0 == ~T1_E~0); 43496#L531-1 assume !(0 == ~T2_E~0); 43438#L536-1 assume !(0 == ~T3_E~0); 43439#L541-1 assume !(0 == ~T4_E~0); 43434#L546-1 assume !(0 == ~E_M~0); 43435#L551-1 assume !(0 == ~E_1~0); 43411#L556-1 assume !(0 == ~E_2~0); 43412#L561-1 assume !(0 == ~E_3~0); 43421#L566-1 assume !(0 == ~E_4~0); 43422#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 43416#L262 assume !(1 == ~m_pc~0); 43417#L262-2 is_master_triggered_~__retres1~0#1 := 0; 43589#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 43273#L274 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 43274#L649 assume !(0 != activate_threads_~tmp~1#1); 43588#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 43361#L281 assume !(1 == ~t1_pc~0); 43362#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 43275#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 43276#L293 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 43334#L657 assume !(0 != activate_threads_~tmp___0~0#1); 43335#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 43423#L300 assume !(1 == ~t2_pc~0); 43424#L300-2 is_transmit2_triggered_~__retres1~2#1 := 0; 43531#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 43328#L312 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 43329#L665 assume !(0 != activate_threads_~tmp___1~0#1); 43206#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 43207#L319 assume !(1 == ~t3_pc~0); 43165#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 43166#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 43352#L331 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 43353#L673 assume !(0 != activate_threads_~tmp___2~0#1); 43186#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 43187#L338 assume !(1 == ~t4_pc~0); 43249#L338-2 is_transmit4_triggered_~__retres1~4#1 := 0; 43250#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 43267#L350 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 43292#L681 assume !(0 != activate_threads_~tmp___3~0#1); 43132#L681-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 43133#L584 assume !(1 == ~M_E~0); 43331#L584-2 assume !(1 == ~T1_E~0); 43290#L589-1 assume !(1 == ~T2_E~0); 43291#L594-1 assume !(1 == ~T3_E~0); 43386#L599-1 assume !(1 == ~T4_E~0); 43164#L604-1 assume !(1 == ~E_M~0); 43148#L609-1 assume !(1 == ~E_1~0); 43149#L614-1 assume !(1 == ~E_2~0); 43264#L619-1 assume !(1 == ~E_3~0); 43351#L624-1 assume !(1 == ~E_4~0); 43444#L629-1 assume { :end_inline_reset_delta_events } true; 43601#L815-2 [2021-12-16 10:04:37,841 INFO L793 eck$LassoCheckResult]: Loop: 43601#L815-2 assume !false; 45184#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 45182#L501 assume !false; 45124#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 45109#L398 assume !(0 == ~m_st~0); 45106#L402 assume !(0 == ~t1_st~0); 45107#L406 assume !(0 == ~t2_st~0); 45108#L410 assume !(0 == ~t3_st~0); 45104#L414 assume !(0 == ~t4_st~0);exists_runnable_thread_~__retres1~5#1 := 0; 45026#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 44990#L426 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 44991#L440 assume !(0 != eval_~tmp~0#1); 45634#L516 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 45632#L358-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 45630#L526-3 assume !(0 == ~M_E~0); 45628#L526-5 assume !(0 == ~T1_E~0); 45626#L531-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 45624#L536-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 45622#L541-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 45620#L546-3 assume 0 == ~E_M~0;~E_M~0 := 1; 45618#L551-3 assume !(0 == ~E_1~0); 45616#L556-3 assume 0 == ~E_2~0;~E_2~0 := 1; 45614#L561-3 assume 0 == ~E_3~0;~E_3~0 := 1; 45612#L566-3 assume !(0 == ~E_4~0); 45610#L571-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 45608#L262-18 assume !(1 == ~m_pc~0); 45606#L262-20 is_master_triggered_~__retres1~0#1 := 0; 45604#L273-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 45602#L274-6 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 45600#L649-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 45598#L649-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 45596#L281-18 assume !(1 == ~t1_pc~0); 45594#L281-20 is_transmit1_triggered_~__retres1~1#1 := 0; 45592#L292-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 45590#L293-6 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 45588#L657-18 assume !(0 != activate_threads_~tmp___0~0#1); 45586#L657-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 45584#L300-18 assume !(1 == ~t2_pc~0); 45582#L300-20 is_transmit2_triggered_~__retres1~2#1 := 0; 45580#L311-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 45578#L312-6 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 45576#L665-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 45574#L665-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 45572#L319-18 assume !(1 == ~t3_pc~0); 45569#L319-20 is_transmit3_triggered_~__retres1~3#1 := 0; 45566#L330-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 45564#L331-6 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 45562#L673-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 45560#L673-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 45558#L338-18 assume !(1 == ~t4_pc~0); 45554#L338-20 is_transmit4_triggered_~__retres1~4#1 := 0; 45552#L349-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 45550#L350-6 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 45548#L681-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 45546#L681-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 45544#L584-3 assume !(1 == ~M_E~0); 45541#L584-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 45540#L589-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 45539#L594-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 45538#L599-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 45537#L604-3 assume 1 == ~E_M~0;~E_M~0 := 2; 45536#L609-3 assume !(1 == ~E_1~0); 45535#L614-3 assume 1 == ~E_2~0;~E_2~0 := 2; 45534#L619-3 assume 1 == ~E_3~0;~E_3~0 := 2; 45533#L624-3 assume !(1 == ~E_4~0); 45532#L629-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 45530#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 45511#L425-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 45507#L426-1 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 45500#L834 assume !(0 == start_simulation_~tmp~3#1); 45497#L834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 45494#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 45490#L425-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 45488#L426-2 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 45486#L789 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 45484#L796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 45483#L797 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 45479#L847 assume !(0 != start_simulation_~tmp___0~1#1); 43601#L815-2 [2021-12-16 10:04:37,841 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:37,841 INFO L85 PathProgramCache]: Analyzing trace with hash 1546408329, now seen corresponding path program 2 times [2021-12-16 10:04:37,841 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:37,841 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2052203683] [2021-12-16 10:04:37,841 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:37,842 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:37,847 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:04:37,847 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-16 10:04:37,851 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:04:37,859 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-16 10:04:37,860 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:37,860 INFO L85 PathProgramCache]: Analyzing trace with hash -169115198, now seen corresponding path program 1 times [2021-12-16 10:04:37,860 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:37,860 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2140639379] [2021-12-16 10:04:37,860 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:37,860 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:37,866 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:04:37,884 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:04:37,884 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:04:37,884 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2140639379] [2021-12-16 10:04:37,884 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2140639379] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:04:37,885 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:04:37,885 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-16 10:04:37,885 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [849026833] [2021-12-16 10:04:37,885 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:04:37,885 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:04:37,885 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:04:37,886 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-16 10:04:37,886 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-16 10:04:37,886 INFO L87 Difference]: Start difference. First operand 3427 states and 4762 transitions. cyclomatic complexity: 1339 Second operand has 5 states, 5 states have (on average 15.6) internal successors, (78), 5 states have internal predecessors, (78), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:04:37,991 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:04:37,992 INFO L93 Difference]: Finished difference Result 11380 states and 15617 transitions. [2021-12-16 10:04:37,992 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2021-12-16 10:04:37,993 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 11380 states and 15617 transitions. [2021-12-16 10:04:38,039 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 11236 [2021-12-16 10:04:38,075 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 11380 states to 11380 states and 15617 transitions. [2021-12-16 10:04:38,075 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11380 [2021-12-16 10:04:38,085 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11380 [2021-12-16 10:04:38,085 INFO L73 IsDeterministic]: Start isDeterministic. Operand 11380 states and 15617 transitions. [2021-12-16 10:04:38,136 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:04:38,136 INFO L681 BuchiCegarLoop]: Abstraction has 11380 states and 15617 transitions. [2021-12-16 10:04:38,141 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11380 states and 15617 transitions. [2021-12-16 10:04:38,223 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11380 to 3463. [2021-12-16 10:04:38,227 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3463 states, 3463 states have (on average 1.3855038983540282) internal successors, (4798), 3462 states have internal predecessors, (4798), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:04:38,233 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3463 states to 3463 states and 4798 transitions. [2021-12-16 10:04:38,233 INFO L704 BuchiCegarLoop]: Abstraction has 3463 states and 4798 transitions. [2021-12-16 10:04:38,233 INFO L587 BuchiCegarLoop]: Abstraction has 3463 states and 4798 transitions. [2021-12-16 10:04:38,234 INFO L425 BuchiCegarLoop]: ======== Iteration 14============ [2021-12-16 10:04:38,234 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3463 states and 4798 transitions. [2021-12-16 10:04:38,240 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3379 [2021-12-16 10:04:38,241 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:04:38,241 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:04:38,241 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:38,241 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:38,242 INFO L791 eck$LassoCheckResult]: Stem: 58473#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 58428#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 58187#L778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 57976#L358 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 57977#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 58051#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 58320#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 58271#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 58272#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 58303#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 58282#L526 assume !(0 == ~M_E~0); 58283#L526-2 assume !(0 == ~T1_E~0); 58322#L531-1 assume !(0 == ~T2_E~0); 58267#L536-1 assume !(0 == ~T3_E~0); 58268#L541-1 assume !(0 == ~T4_E~0); 58262#L546-1 assume !(0 == ~E_M~0); 58263#L551-1 assume !(0 == ~E_1~0); 58239#L556-1 assume !(0 == ~E_2~0); 58240#L561-1 assume !(0 == ~E_3~0); 58249#L566-1 assume !(0 == ~E_4~0); 58250#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 58244#L262 assume !(1 == ~m_pc~0); 58245#L262-2 is_master_triggered_~__retres1~0#1 := 0; 58438#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 58097#L274 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 58098#L649 assume !(0 != activate_threads_~tmp~1#1); 58437#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 58188#L281 assume !(1 == ~t1_pc~0); 58189#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 58099#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 58100#L293 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 58162#L657 assume !(0 != activate_threads_~tmp___0~0#1); 58163#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 58251#L300 assume !(1 == ~t2_pc~0); 58252#L300-2 is_transmit2_triggered_~__retres1~2#1 := 0; 58359#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 58156#L312 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 58157#L665 assume !(0 != activate_threads_~tmp___1~0#1); 58029#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 58030#L319 assume !(1 == ~t3_pc~0); 57989#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 57990#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 58179#L331 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 58180#L673 assume !(0 != activate_threads_~tmp___2~0#1); 58009#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 58010#L338 assume !(1 == ~t4_pc~0); 58073#L338-2 is_transmit4_triggered_~__retres1~4#1 := 0; 58074#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 58091#L350 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 58116#L681 assume !(0 != activate_threads_~tmp___3~0#1); 57956#L681-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 57957#L584 assume !(1 == ~M_E~0); 58159#L584-2 assume !(1 == ~T1_E~0); 58114#L589-1 assume !(1 == ~T2_E~0); 58115#L594-1 assume !(1 == ~T3_E~0); 58215#L599-1 assume !(1 == ~T4_E~0); 57988#L604-1 assume !(1 == ~E_M~0); 57972#L609-1 assume !(1 == ~E_1~0); 57973#L614-1 assume !(1 == ~E_2~0); 58088#L619-1 assume !(1 == ~E_3~0); 58178#L624-1 assume !(1 == ~E_4~0); 58273#L629-1 assume { :end_inline_reset_delta_events } true; 58453#L815-2 [2021-12-16 10:04:38,242 INFO L793 eck$LassoCheckResult]: Loop: 58453#L815-2 assume !false; 59920#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 59898#L501 assume !false; 59896#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 59895#L398 assume !(0 == ~m_st~0); 59892#L402 assume !(0 == ~t1_st~0); 59893#L406 assume !(0 == ~t2_st~0); 59894#L410 assume !(0 == ~t3_st~0); 59890#L414 assume !(0 == ~t4_st~0);exists_runnable_thread_~__retres1~5#1 := 0; 59891#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 59857#L426 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 59858#L440 assume !(0 != eval_~tmp~0#1); 60072#L516 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 60070#L358-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 60068#L526-3 assume !(0 == ~M_E~0); 60066#L526-5 assume !(0 == ~T1_E~0); 60064#L531-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 60062#L536-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 60060#L541-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 60058#L546-3 assume 0 == ~E_M~0;~E_M~0 := 1; 60056#L551-3 assume !(0 == ~E_1~0); 60054#L556-3 assume 0 == ~E_2~0;~E_2~0 := 1; 60052#L561-3 assume 0 == ~E_3~0;~E_3~0 := 1; 60050#L566-3 assume !(0 == ~E_4~0); 60048#L571-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 60046#L262-18 assume !(1 == ~m_pc~0); 60044#L262-20 is_master_triggered_~__retres1~0#1 := 0; 60042#L273-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 60040#L274-6 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 60038#L649-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 60036#L649-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 60034#L281-18 assume !(1 == ~t1_pc~0); 60032#L281-20 is_transmit1_triggered_~__retres1~1#1 := 0; 60030#L292-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 60028#L293-6 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 60026#L657-18 assume !(0 != activate_threads_~tmp___0~0#1); 60024#L657-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 60022#L300-18 assume !(1 == ~t2_pc~0); 60020#L300-20 is_transmit2_triggered_~__retres1~2#1 := 0; 60018#L311-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 60016#L312-6 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 60014#L665-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 60012#L665-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 60010#L319-18 assume !(1 == ~t3_pc~0); 60007#L319-20 is_transmit3_triggered_~__retres1~3#1 := 0; 60004#L330-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 60002#L331-6 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 60000#L673-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 59998#L673-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 59996#L338-18 assume !(1 == ~t4_pc~0); 59992#L338-20 is_transmit4_triggered_~__retres1~4#1 := 0; 59990#L349-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 59988#L350-6 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 59986#L681-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 59984#L681-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 59982#L584-3 assume !(1 == ~M_E~0); 59979#L584-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 59978#L589-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 59977#L594-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 59976#L599-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 59975#L604-3 assume 1 == ~E_M~0;~E_M~0 := 2; 59974#L609-3 assume !(1 == ~E_1~0); 59973#L614-3 assume 1 == ~E_2~0;~E_2~0 := 2; 59972#L619-3 assume 1 == ~E_3~0;~E_3~0 := 2; 59971#L624-3 assume !(1 == ~E_4~0); 59970#L629-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 59968#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 59963#L425-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 59961#L426-1 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 59941#L834 assume !(0 == start_simulation_~tmp~3#1); 59939#L834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 59936#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 59933#L425-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 59931#L426-2 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 59929#L789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 59927#L796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 59926#L797 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 59925#L847 assume !(0 != start_simulation_~tmp___0~1#1); 58453#L815-2 [2021-12-16 10:04:38,243 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:38,243 INFO L85 PathProgramCache]: Analyzing trace with hash 1546408329, now seen corresponding path program 3 times [2021-12-16 10:04:38,243 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:38,243 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1995307787] [2021-12-16 10:04:38,243 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:38,243 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:38,248 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:04:38,248 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-16 10:04:38,254 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:04:38,263 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-16 10:04:38,264 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:38,265 INFO L85 PathProgramCache]: Analyzing trace with hash -169174780, now seen corresponding path program 1 times [2021-12-16 10:04:38,265 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:38,265 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [462212378] [2021-12-16 10:04:38,265 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:38,265 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:38,272 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:04:38,317 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:04:38,317 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:04:38,317 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [462212378] [2021-12-16 10:04:38,317 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [462212378] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:04:38,318 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:04:38,318 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-16 10:04:38,318 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1051643113] [2021-12-16 10:04:38,318 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:04:38,318 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:04:38,319 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:04:38,319 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-16 10:04:38,319 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-16 10:04:38,319 INFO L87 Difference]: Start difference. First operand 3463 states and 4798 transitions. cyclomatic complexity: 1339 Second operand has 5 states, 5 states have (on average 15.6) internal successors, (78), 5 states have internal predecessors, (78), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:04:38,442 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:04:38,442 INFO L93 Difference]: Finished difference Result 6874 states and 9451 transitions. [2021-12-16 10:04:38,442 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-16 10:04:38,443 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6874 states and 9451 transitions. [2021-12-16 10:04:38,466 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 6782 [2021-12-16 10:04:38,485 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6874 states to 6874 states and 9451 transitions. [2021-12-16 10:04:38,486 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6874 [2021-12-16 10:04:38,489 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6874 [2021-12-16 10:04:38,490 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6874 states and 9451 transitions. [2021-12-16 10:04:38,500 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:04:38,500 INFO L681 BuchiCegarLoop]: Abstraction has 6874 states and 9451 transitions. [2021-12-16 10:04:38,504 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6874 states and 9451 transitions. [2021-12-16 10:04:38,547 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6874 to 3562. [2021-12-16 10:04:38,560 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3562 states, 3562 states have (on average 1.36692869174621) internal successors, (4869), 3561 states have internal predecessors, (4869), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:04:38,566 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3562 states to 3562 states and 4869 transitions. [2021-12-16 10:04:38,567 INFO L704 BuchiCegarLoop]: Abstraction has 3562 states and 4869 transitions. [2021-12-16 10:04:38,567 INFO L587 BuchiCegarLoop]: Abstraction has 3562 states and 4869 transitions. [2021-12-16 10:04:38,567 INFO L425 BuchiCegarLoop]: ======== Iteration 15============ [2021-12-16 10:04:38,567 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3562 states and 4869 transitions. [2021-12-16 10:04:38,573 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3478 [2021-12-16 10:04:38,573 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:04:38,574 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:04:38,574 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:38,574 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:38,575 INFO L791 eck$LassoCheckResult]: Stem: 68836#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 68790#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 68542#L778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 68326#L358 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 68327#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 68400#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 68679#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 68625#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 68626#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 68661#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 68636#L526 assume !(0 == ~M_E~0); 68637#L526-2 assume !(0 == ~T1_E~0); 68681#L531-1 assume !(0 == ~T2_E~0); 68621#L536-1 assume !(0 == ~T3_E~0); 68622#L541-1 assume !(0 == ~T4_E~0); 68616#L546-1 assume !(0 == ~E_M~0); 68617#L551-1 assume !(0 == ~E_1~0); 68593#L556-1 assume !(0 == ~E_2~0); 68594#L561-1 assume !(0 == ~E_3~0); 68603#L566-1 assume !(0 == ~E_4~0); 68604#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 68598#L262 assume !(1 == ~m_pc~0); 68599#L262-2 is_master_triggered_~__retres1~0#1 := 0; 68800#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 68447#L274 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 68448#L649 assume !(0 != activate_threads_~tmp~1#1); 68799#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 68543#L281 assume !(1 == ~t1_pc~0); 68544#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 68449#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 68450#L293 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 68512#L657 assume !(0 != activate_threads_~tmp___0~0#1); 68513#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 68605#L300 assume !(1 == ~t2_pc~0); 68606#L300-2 is_transmit2_triggered_~__retres1~2#1 := 0; 68725#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 68506#L312 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 68507#L665 assume !(0 != activate_threads_~tmp___1~0#1); 68380#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 68381#L319 assume !(1 == ~t3_pc~0); 68339#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 68340#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 68534#L331 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 68535#L673 assume !(0 != activate_threads_~tmp___2~0#1); 68360#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 68361#L338 assume !(1 == ~t4_pc~0); 68423#L338-2 is_transmit4_triggered_~__retres1~4#1 := 0; 68424#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 68441#L350 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 68468#L681 assume !(0 != activate_threads_~tmp___3~0#1); 68306#L681-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 68307#L584 assume !(1 == ~M_E~0); 68509#L584-2 assume !(1 == ~T1_E~0); 68466#L589-1 assume !(1 == ~T2_E~0); 68467#L594-1 assume !(1 == ~T3_E~0); 68567#L599-1 assume !(1 == ~T4_E~0); 68338#L604-1 assume !(1 == ~E_M~0); 68322#L609-1 assume !(1 == ~E_1~0); 68323#L614-1 assume !(1 == ~E_2~0); 68438#L619-1 assume !(1 == ~E_3~0); 68533#L624-1 assume !(1 == ~E_4~0); 68627#L629-1 assume { :end_inline_reset_delta_events } true; 68815#L815-2 [2021-12-16 10:04:38,575 INFO L793 eck$LassoCheckResult]: Loop: 68815#L815-2 assume !false; 69556#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 69555#L501 assume !false; 69554#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 69553#L398 assume !(0 == ~m_st~0); 69550#L402 assume !(0 == ~t1_st~0); 69551#L406 assume !(0 == ~t2_st~0); 69552#L410 assume !(0 == ~t3_st~0); 69548#L414 assume !(0 == ~t4_st~0);exists_runnable_thread_~__retres1~5#1 := 0; 69549#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 69540#L426 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 69541#L440 assume !(0 != eval_~tmp~0#1); 69828#L516 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 69826#L358-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 69824#L526-3 assume !(0 == ~M_E~0); 69822#L526-5 assume !(0 == ~T1_E~0); 69819#L531-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 69816#L536-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 69813#L541-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 69810#L546-3 assume 0 == ~E_M~0;~E_M~0 := 1; 69807#L551-3 assume !(0 == ~E_1~0); 69804#L556-3 assume 0 == ~E_2~0;~E_2~0 := 1; 69801#L561-3 assume 0 == ~E_3~0;~E_3~0 := 1; 69798#L566-3 assume !(0 == ~E_4~0); 69795#L571-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 69788#L262-18 assume !(1 == ~m_pc~0); 69785#L262-20 is_master_triggered_~__retres1~0#1 := 0; 69782#L273-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 69778#L274-6 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 69776#L649-18 assume !(0 != activate_threads_~tmp~1#1); 69773#L649-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 69770#L281-18 assume !(1 == ~t1_pc~0); 69767#L281-20 is_transmit1_triggered_~__retres1~1#1 := 0; 69764#L292-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 69761#L293-6 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 69758#L657-18 assume !(0 != activate_threads_~tmp___0~0#1); 69755#L657-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 69752#L300-18 assume !(1 == ~t2_pc~0); 69749#L300-20 is_transmit2_triggered_~__retres1~2#1 := 0; 69746#L311-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 69743#L312-6 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 69740#L665-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 69737#L665-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 69734#L319-18 assume 1 == ~t3_pc~0; 69731#L320-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 69725#L330-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 69720#L331-6 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 69715#L673-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 69710#L673-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 69704#L338-18 assume !(1 == ~t4_pc~0); 69697#L338-20 is_transmit4_triggered_~__retres1~4#1 := 0; 69692#L349-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 69687#L350-6 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 69682#L681-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 69676#L681-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 69671#L584-3 assume !(1 == ~M_E~0); 69665#L584-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 69661#L589-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 69657#L594-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 69653#L599-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 69648#L604-3 assume 1 == ~E_M~0;~E_M~0 := 2; 69644#L609-3 assume !(1 == ~E_1~0); 69640#L614-3 assume 1 == ~E_2~0;~E_2~0 := 2; 69636#L619-3 assume 1 == ~E_3~0;~E_3~0 := 2; 69631#L624-3 assume !(1 == ~E_4~0); 69626#L629-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 69621#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 69614#L425-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 69610#L426-1 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 69605#L834 assume !(0 == start_simulation_~tmp~3#1); 69599#L834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 69594#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 69589#L425-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 69585#L426-2 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 69581#L789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 69575#L796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 69570#L797 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 69566#L847 assume !(0 != start_simulation_~tmp___0~1#1); 68815#L815-2 [2021-12-16 10:04:38,576 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:38,576 INFO L85 PathProgramCache]: Analyzing trace with hash 1546408329, now seen corresponding path program 4 times [2021-12-16 10:04:38,576 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:38,576 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [658941926] [2021-12-16 10:04:38,576 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:38,576 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:38,584 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:04:38,584 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-16 10:04:38,589 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:04:38,600 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-16 10:04:38,600 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:38,600 INFO L85 PathProgramCache]: Analyzing trace with hash -1236142587, now seen corresponding path program 1 times [2021-12-16 10:04:38,600 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:38,601 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1852598236] [2021-12-16 10:04:38,601 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:38,601 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:38,606 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:04:38,618 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:04:38,618 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:04:38,618 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1852598236] [2021-12-16 10:04:38,618 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1852598236] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:04:38,618 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:04:38,618 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:04:38,619 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [176366078] [2021-12-16 10:04:38,619 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:04:38,619 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:04:38,619 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:04:38,619 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-16 10:04:38,619 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-16 10:04:38,620 INFO L87 Difference]: Start difference. First operand 3562 states and 4869 transitions. cyclomatic complexity: 1311 Second operand has 3 states, 3 states have (on average 26.0) internal successors, (78), 3 states have internal predecessors, (78), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:04:38,652 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:04:38,653 INFO L93 Difference]: Finished difference Result 5541 states and 7449 transitions. [2021-12-16 10:04:38,653 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-16 10:04:38,654 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5541 states and 7449 transitions. [2021-12-16 10:04:38,700 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 5455 [2021-12-16 10:04:38,710 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5541 states to 5541 states and 7449 transitions. [2021-12-16 10:04:38,711 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5541 [2021-12-16 10:04:38,714 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5541 [2021-12-16 10:04:38,714 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5541 states and 7449 transitions. [2021-12-16 10:04:38,719 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:04:38,719 INFO L681 BuchiCegarLoop]: Abstraction has 5541 states and 7449 transitions. [2021-12-16 10:04:38,722 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5541 states and 7449 transitions. [2021-12-16 10:04:38,764 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5541 to 5355. [2021-12-16 10:04:38,770 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5355 states, 5355 states have (on average 1.346591970121382) internal successors, (7211), 5354 states have internal predecessors, (7211), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:04:38,778 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5355 states to 5355 states and 7211 transitions. [2021-12-16 10:04:38,778 INFO L704 BuchiCegarLoop]: Abstraction has 5355 states and 7211 transitions. [2021-12-16 10:04:38,778 INFO L587 BuchiCegarLoop]: Abstraction has 5355 states and 7211 transitions. [2021-12-16 10:04:38,779 INFO L425 BuchiCegarLoop]: ======== Iteration 16============ [2021-12-16 10:04:38,779 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5355 states and 7211 transitions. [2021-12-16 10:04:38,790 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 5269 [2021-12-16 10:04:38,790 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:04:38,790 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:04:38,791 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:38,791 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:38,791 INFO L791 eck$LassoCheckResult]: Stem: 77917#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 77880#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 77644#L778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 77435#L358 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 77436#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 77510#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 77779#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 77724#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 77725#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 77755#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 77735#L526 assume !(0 == ~M_E~0); 77736#L526-2 assume !(0 == ~T1_E~0); 77781#L531-1 assume !(0 == ~T2_E~0); 77720#L536-1 assume !(0 == ~T3_E~0); 77721#L541-1 assume !(0 == ~T4_E~0); 77715#L546-1 assume !(0 == ~E_M~0); 77716#L551-1 assume !(0 == ~E_1~0); 77694#L556-1 assume !(0 == ~E_2~0); 77695#L561-1 assume !(0 == ~E_3~0); 77704#L566-1 assume !(0 == ~E_4~0); 77705#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 77699#L262 assume !(1 == ~m_pc~0); 77700#L262-2 is_master_triggered_~__retres1~0#1 := 0; 77887#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 77557#L274 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 77558#L649 assume !(0 != activate_threads_~tmp~1#1); 77886#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 77645#L281 assume !(1 == ~t1_pc~0); 77646#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 77559#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 77560#L293 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 77619#L657 assume !(0 != activate_threads_~tmp___0~0#1); 77620#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 77706#L300 assume !(1 == ~t2_pc~0); 77707#L300-2 is_transmit2_triggered_~__retres1~2#1 := 0; 77814#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 77613#L312 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 77614#L665 assume !(0 != activate_threads_~tmp___1~0#1); 77489#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 77490#L319 assume !(1 == ~t3_pc~0); 77448#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 77449#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 77636#L331 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 77637#L673 assume !(0 != activate_threads_~tmp___2~0#1); 77469#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 77470#L338 assume !(1 == ~t4_pc~0); 77533#L338-2 is_transmit4_triggered_~__retres1~4#1 := 0; 77534#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 77551#L350 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 77576#L681 assume !(0 != activate_threads_~tmp___3~0#1); 77415#L681-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 77416#L584 assume !(1 == ~M_E~0); 77616#L584-2 assume !(1 == ~T1_E~0); 77574#L589-1 assume !(1 == ~T2_E~0); 77575#L594-1 assume !(1 == ~T3_E~0); 77670#L599-1 assume !(1 == ~T4_E~0); 77447#L604-1 assume !(1 == ~E_M~0); 77431#L609-1 assume !(1 == ~E_1~0); 77432#L614-1 assume !(1 == ~E_2~0); 77548#L619-1 assume !(1 == ~E_3~0); 77635#L624-1 assume !(1 == ~E_4~0); 77726#L629-1 assume { :end_inline_reset_delta_events } true; 77899#L815-2 assume !false; 79670#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 79671#L501 [2021-12-16 10:04:38,791 INFO L793 eck$LassoCheckResult]: Loop: 79671#L501 assume !false; 79446#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 79447#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 79700#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 79697#L426 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 79483#L440 assume 0 != eval_~tmp~0#1; 79484#L440-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 79651#L448 assume !(0 != eval_~tmp_ndt_1~0#1); 79523#L445 assume !(0 == ~t1_st~0); 79519#L459 assume !(0 == ~t2_st~0); 79517#L473 assume !(0 == ~t3_st~0); 79675#L487 assume !(0 == ~t4_st~0); 79671#L501 [2021-12-16 10:04:38,792 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:38,792 INFO L85 PathProgramCache]: Analyzing trace with hash 39728939, now seen corresponding path program 1 times [2021-12-16 10:04:38,792 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:38,792 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1333361177] [2021-12-16 10:04:38,792 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:38,792 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:38,801 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:04:38,801 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-16 10:04:38,806 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:04:38,817 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-16 10:04:38,818 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:38,818 INFO L85 PathProgramCache]: Analyzing trace with hash 1608874715, now seen corresponding path program 1 times [2021-12-16 10:04:38,818 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:38,818 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [807015401] [2021-12-16 10:04:38,818 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:38,818 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:38,821 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:04:38,821 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-16 10:04:38,823 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:04:38,824 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-16 10:04:38,825 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:38,825 INFO L85 PathProgramCache]: Analyzing trace with hash 220742405, now seen corresponding path program 1 times [2021-12-16 10:04:38,825 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:38,825 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [782090633] [2021-12-16 10:04:38,825 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:38,826 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:38,832 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:04:38,850 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:04:38,850 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:04:38,850 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [782090633] [2021-12-16 10:04:38,851 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [782090633] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:04:38,851 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:04:38,851 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:04:38,851 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [233204435] [2021-12-16 10:04:38,852 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:04:38,933 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:04:38,934 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-16 10:04:38,934 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-16 10:04:38,934 INFO L87 Difference]: Start difference. First operand 5355 states and 7211 transitions. cyclomatic complexity: 1862 Second operand has 3 states, 3 states have (on average 25.333333333333332) internal successors, (76), 3 states have internal predecessors, (76), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:04:38,967 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:04:38,967 INFO L93 Difference]: Finished difference Result 8870 states and 11816 transitions. [2021-12-16 10:04:38,967 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-16 10:04:38,968 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8870 states and 11816 transitions. [2021-12-16 10:04:38,999 INFO L131 ngComponentsAnalysis]: Automaton has 11 accepting balls. 8482 [2021-12-16 10:04:39,021 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8870 states to 8870 states and 11816 transitions. [2021-12-16 10:04:39,021 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8870 [2021-12-16 10:04:39,028 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8870 [2021-12-16 10:04:39,028 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8870 states and 11816 transitions. [2021-12-16 10:04:39,037 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:04:39,037 INFO L681 BuchiCegarLoop]: Abstraction has 8870 states and 11816 transitions. [2021-12-16 10:04:39,044 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8870 states and 11816 transitions. [2021-12-16 10:04:39,182 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8870 to 8870. [2021-12-16 10:04:39,191 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8870 states, 8870 states have (on average 1.332130777903044) internal successors, (11816), 8869 states have internal predecessors, (11816), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:04:39,207 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8870 states to 8870 states and 11816 transitions. [2021-12-16 10:04:39,207 INFO L704 BuchiCegarLoop]: Abstraction has 8870 states and 11816 transitions. [2021-12-16 10:04:39,207 INFO L587 BuchiCegarLoop]: Abstraction has 8870 states and 11816 transitions. [2021-12-16 10:04:39,207 INFO L425 BuchiCegarLoop]: ======== Iteration 17============ [2021-12-16 10:04:39,207 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 8870 states and 11816 transitions. [2021-12-16 10:04:39,228 INFO L131 ngComponentsAnalysis]: Automaton has 11 accepting balls. 8482 [2021-12-16 10:04:39,228 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:04:39,228 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:04:39,229 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:39,229 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:39,229 INFO L791 eck$LassoCheckResult]: Stem: 92197#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 92142#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 91884#L778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 91668#L358 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 91669#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 91743#L365-2 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 92027#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 92028#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 92128#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 92129#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 91985#L526 assume !(0 == ~M_E~0); 91986#L526-2 assume !(0 == ~T1_E~0); 92030#L531-1 assume !(0 == ~T2_E~0); 92031#L536-1 assume !(0 == ~T3_E~0); 92091#L541-1 assume !(0 == ~T4_E~0); 92092#L546-1 assume !(0 == ~E_M~0); 92042#L551-1 assume !(0 == ~E_1~0); 92043#L556-1 assume !(0 == ~E_2~0); 91982#L561-1 assume !(0 == ~E_3~0); 91983#L566-1 assume !(0 == ~E_4~0); 92147#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 92148#L262 assume !(1 == ~m_pc~0); 92165#L262-2 is_master_triggered_~__retres1~0#1 := 0; 92166#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 91788#L274 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 91789#L649 assume !(0 != activate_threads_~tmp~1#1); 92199#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 92200#L281 assume !(1 == ~t1_pc~0); 92173#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 92174#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 92004#L293 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 92005#L657 assume !(0 != activate_threads_~tmp___0~0#1); 92140#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 92141#L300 assume !(1 == ~t2_pc~0); 92110#L300-2 is_transmit2_triggered_~__retres1~2#1 := 0; 92111#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 91848#L312 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 91849#L665 assume !(0 != activate_threads_~tmp___1~0#1); 91723#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 91724#L319 assume !(1 == ~t3_pc~0); 91682#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 91683#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 91879#L331 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 91880#L673 assume !(0 != activate_threads_~tmp___2~0#1); 91703#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 91704#L338 assume !(1 == ~t4_pc~0); 91765#L338-2 is_transmit4_triggered_~__retres1~4#1 := 0; 91766#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 91809#L350 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 91810#L681 assume !(0 != activate_threads_~tmp___3~0#1); 91648#L681-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 91649#L584 assume !(1 == ~M_E~0); 91852#L584-2 assume !(1 == ~T1_E~0); 91853#L589-1 assume !(1 == ~T2_E~0); 92060#L594-1 assume !(1 == ~T3_E~0); 92061#L599-1 assume !(1 == ~T4_E~0); 91680#L604-1 assume !(1 == ~E_M~0); 91681#L609-1 assume !(1 == ~E_1~0); 91780#L614-1 assume !(1 == ~E_2~0); 91781#L619-1 assume !(1 == ~E_3~0); 91972#L624-1 assume !(1 == ~E_4~0); 91973#L629-1 assume { :end_inline_reset_delta_events } true; 92177#L815-2 assume !false; 92568#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 92569#L501 [2021-12-16 10:04:39,229 INFO L793 eck$LassoCheckResult]: Loop: 92569#L501 assume !false; 92549#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 92550#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 92523#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 92524#L426 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 92504#L440 assume 0 != eval_~tmp~0#1; 92505#L440-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 92480#L448 assume !(0 != eval_~tmp_ndt_1~0#1); 92481#L445 assume !(0 == ~t1_st~0); 92976#L459 assume !(0 == ~t2_st~0); 92621#L473 assume !(0 == ~t3_st~0); 92573#L487 assume !(0 == ~t4_st~0); 92569#L501 [2021-12-16 10:04:39,231 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:39,231 INFO L85 PathProgramCache]: Analyzing trace with hash 600428717, now seen corresponding path program 1 times [2021-12-16 10:04:39,231 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:39,231 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1568983890] [2021-12-16 10:04:39,231 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:39,231 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:39,238 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:04:39,246 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:04:39,246 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:04:39,246 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1568983890] [2021-12-16 10:04:39,246 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1568983890] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:04:39,246 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:04:39,246 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:04:39,247 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2081819296] [2021-12-16 10:04:39,247 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:04:39,247 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:04:39,247 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:39,247 INFO L85 PathProgramCache]: Analyzing trace with hash 1608874715, now seen corresponding path program 2 times [2021-12-16 10:04:39,247 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:39,247 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1202897755] [2021-12-16 10:04:39,248 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:39,248 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:39,252 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:04:39,253 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-16 10:04:39,254 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:04:39,255 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-16 10:04:39,302 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:04:39,303 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-16 10:04:39,303 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-16 10:04:39,303 INFO L87 Difference]: Start difference. First operand 8870 states and 11816 transitions. cyclomatic complexity: 2957 Second operand has 3 states, 3 states have (on average 21.333333333333332) internal successors, (64), 3 states have internal predecessors, (64), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:04:39,323 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:04:39,324 INFO L93 Difference]: Finished difference Result 6802 states and 9071 transitions. [2021-12-16 10:04:39,324 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-16 10:04:39,325 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6802 states and 9071 transitions. [2021-12-16 10:04:39,347 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 6718 [2021-12-16 10:04:39,362 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6802 states to 6802 states and 9071 transitions. [2021-12-16 10:04:39,363 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6802 [2021-12-16 10:04:39,371 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6802 [2021-12-16 10:04:39,371 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6802 states and 9071 transitions. [2021-12-16 10:04:39,378 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:04:39,378 INFO L681 BuchiCegarLoop]: Abstraction has 6802 states and 9071 transitions. [2021-12-16 10:04:39,381 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6802 states and 9071 transitions. [2021-12-16 10:04:39,435 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6802 to 6802. [2021-12-16 10:04:39,442 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6802 states, 6802 states have (on average 1.3335783593060864) internal successors, (9071), 6801 states have internal predecessors, (9071), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:04:39,453 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6802 states to 6802 states and 9071 transitions. [2021-12-16 10:04:39,453 INFO L704 BuchiCegarLoop]: Abstraction has 6802 states and 9071 transitions. [2021-12-16 10:04:39,453 INFO L587 BuchiCegarLoop]: Abstraction has 6802 states and 9071 transitions. [2021-12-16 10:04:39,453 INFO L425 BuchiCegarLoop]: ======== Iteration 18============ [2021-12-16 10:04:39,454 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6802 states and 9071 transitions. [2021-12-16 10:04:39,513 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 6718 [2021-12-16 10:04:39,513 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:04:39,513 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:04:39,514 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:39,514 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:39,514 INFO L791 eck$LassoCheckResult]: Stem: 107850#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 107794#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 107554#L778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 107346#L358 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 107347#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 107421#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 107693#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 107638#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 107639#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 107669#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 107649#L526 assume !(0 == ~M_E~0); 107650#L526-2 assume !(0 == ~T1_E~0); 107694#L531-1 assume !(0 == ~T2_E~0); 107634#L536-1 assume !(0 == ~T3_E~0); 107635#L541-1 assume !(0 == ~T4_E~0); 107629#L546-1 assume !(0 == ~E_M~0); 107630#L551-1 assume !(0 == ~E_1~0); 107608#L556-1 assume !(0 == ~E_2~0); 107609#L561-1 assume !(0 == ~E_3~0); 107618#L566-1 assume !(0 == ~E_4~0); 107619#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 107613#L262 assume !(1 == ~m_pc~0); 107614#L262-2 is_master_triggered_~__retres1~0#1 := 0; 107808#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 107465#L274 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 107466#L649 assume !(0 != activate_threads_~tmp~1#1); 107805#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 107558#L281 assume !(1 == ~t1_pc~0); 107559#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 107469#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 107470#L293 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 107530#L657 assume !(0 != activate_threads_~tmp___0~0#1); 107531#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 107620#L300 assume !(1 == ~t2_pc~0); 107621#L300-2 is_transmit2_triggered_~__retres1~2#1 := 0; 107731#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 107524#L312 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 107525#L665 assume !(0 != activate_threads_~tmp___1~0#1); 107400#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 107401#L319 assume !(1 == ~t3_pc~0); 107359#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 107360#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 107548#L331 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 107549#L673 assume !(0 != activate_threads_~tmp___2~0#1); 107380#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 107381#L338 assume !(1 == ~t4_pc~0); 107444#L338-2 is_transmit4_triggered_~__retres1~4#1 := 0; 107445#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 107460#L350 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 107486#L681 assume !(0 != activate_threads_~tmp___3~0#1); 107326#L681-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 107327#L584 assume !(1 == ~M_E~0); 107527#L584-2 assume !(1 == ~T1_E~0); 107484#L589-1 assume !(1 == ~T2_E~0); 107485#L594-1 assume !(1 == ~T3_E~0); 107580#L599-1 assume !(1 == ~T4_E~0); 107358#L604-1 assume !(1 == ~E_M~0); 107342#L609-1 assume !(1 == ~E_1~0); 107343#L614-1 assume !(1 == ~E_2~0); 107459#L619-1 assume !(1 == ~E_3~0); 107547#L624-1 assume !(1 == ~E_4~0); 107640#L629-1 assume { :end_inline_reset_delta_events } true; 107827#L815-2 assume !false; 109369#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 109370#L501 [2021-12-16 10:04:39,515 INFO L793 eck$LassoCheckResult]: Loop: 109370#L501 assume !false; 109629#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 109627#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 109625#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 109624#L426 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 109622#L440 assume 0 != eval_~tmp~0#1; 109620#L440-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 109619#L448 assume !(0 != eval_~tmp_ndt_1~0#1); 109618#L445 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 109336#L462 assume !(0 != eval_~tmp_ndt_2~0#1); 109337#L459 assume !(0 == ~t2_st~0); 109388#L473 assume !(0 == ~t3_st~0); 109374#L487 assume !(0 == ~t4_st~0); 109370#L501 [2021-12-16 10:04:39,515 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:39,515 INFO L85 PathProgramCache]: Analyzing trace with hash 39728939, now seen corresponding path program 2 times [2021-12-16 10:04:39,515 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:39,515 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [515266338] [2021-12-16 10:04:39,516 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:39,516 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:39,521 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:04:39,521 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-16 10:04:39,525 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:04:39,532 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-16 10:04:39,533 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:39,533 INFO L85 PathProgramCache]: Analyzing trace with hash -1811665542, now seen corresponding path program 1 times [2021-12-16 10:04:39,533 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:39,533 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [43056628] [2021-12-16 10:04:39,533 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:39,534 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:39,536 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:04:39,536 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-16 10:04:39,537 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:04:39,538 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-16 10:04:39,538 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:39,538 INFO L85 PathProgramCache]: Analyzing trace with hash -1894094192, now seen corresponding path program 1 times [2021-12-16 10:04:39,538 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:39,538 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [754031721] [2021-12-16 10:04:39,539 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:39,539 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:39,543 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:04:39,559 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:04:39,560 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:04:39,560 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [754031721] [2021-12-16 10:04:39,560 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [754031721] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:04:39,560 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:04:39,560 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:04:39,560 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1547476822] [2021-12-16 10:04:39,560 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:04:39,626 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:04:39,627 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-16 10:04:39,627 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-16 10:04:39,627 INFO L87 Difference]: Start difference. First operand 6802 states and 9071 transitions. cyclomatic complexity: 2275 Second operand has 3 states, 3 states have (on average 25.666666666666668) internal successors, (77), 3 states have internal predecessors, (77), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:04:39,676 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:04:39,677 INFO L93 Difference]: Finished difference Result 12257 states and 16272 transitions. [2021-12-16 10:04:39,677 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-16 10:04:39,677 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 12257 states and 16272 transitions. [2021-12-16 10:04:39,721 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 12165 [2021-12-16 10:04:39,749 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 12257 states to 12257 states and 16272 transitions. [2021-12-16 10:04:39,750 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 12257 [2021-12-16 10:04:39,757 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 12257 [2021-12-16 10:04:39,758 INFO L73 IsDeterministic]: Start isDeterministic. Operand 12257 states and 16272 transitions. [2021-12-16 10:04:39,770 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:04:39,770 INFO L681 BuchiCegarLoop]: Abstraction has 12257 states and 16272 transitions. [2021-12-16 10:04:39,776 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12257 states and 16272 transitions. [2021-12-16 10:04:39,876 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12257 to 12005. [2021-12-16 10:04:39,888 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 12005 states, 12005 states have (on average 1.328613077884215) internal successors, (15950), 12004 states have internal predecessors, (15950), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:04:39,905 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12005 states to 12005 states and 15950 transitions. [2021-12-16 10:04:39,906 INFO L704 BuchiCegarLoop]: Abstraction has 12005 states and 15950 transitions. [2021-12-16 10:04:39,906 INFO L587 BuchiCegarLoop]: Abstraction has 12005 states and 15950 transitions. [2021-12-16 10:04:39,906 INFO L425 BuchiCegarLoop]: ======== Iteration 19============ [2021-12-16 10:04:39,906 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 12005 states and 15950 transitions. [2021-12-16 10:04:39,939 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 11913 [2021-12-16 10:04:39,939 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:04:39,940 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:04:39,940 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:39,940 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:39,940 INFO L791 eck$LassoCheckResult]: Stem: 126920#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 126874#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 126627#L778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 126413#L358 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 126414#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 126488#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 126763#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 126707#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 126708#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 126741#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 126720#L526 assume !(0 == ~M_E~0); 126721#L526-2 assume !(0 == ~T1_E~0); 126765#L531-1 assume !(0 == ~T2_E~0); 126703#L536-1 assume !(0 == ~T3_E~0); 126704#L541-1 assume !(0 == ~T4_E~0); 126698#L546-1 assume !(0 == ~E_M~0); 126699#L551-1 assume !(0 == ~E_1~0); 126676#L556-1 assume !(0 == ~E_2~0); 126677#L561-1 assume !(0 == ~E_3~0); 126686#L566-1 assume !(0 == ~E_4~0); 126687#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 126681#L262 assume !(1 == ~m_pc~0); 126682#L262-2 is_master_triggered_~__retres1~0#1 := 0; 126884#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 126535#L274 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 126536#L649 assume !(0 != activate_threads_~tmp~1#1); 126883#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 126628#L281 assume !(1 == ~t1_pc~0); 126629#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 126537#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 126538#L293 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 126598#L657 assume !(0 != activate_threads_~tmp___0~0#1); 126599#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 126688#L300 assume !(1 == ~t2_pc~0); 126689#L300-2 is_transmit2_triggered_~__retres1~2#1 := 0; 126808#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 126592#L312 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 126593#L665 assume !(0 != activate_threads_~tmp___1~0#1); 126467#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 126468#L319 assume !(1 == ~t3_pc~0); 126426#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 126427#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 126619#L331 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 126620#L673 assume !(0 != activate_threads_~tmp___2~0#1); 126447#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 126448#L338 assume !(1 == ~t4_pc~0); 126512#L338-2 is_transmit4_triggered_~__retres1~4#1 := 0; 126513#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 126530#L350 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 126554#L681 assume !(0 != activate_threads_~tmp___3~0#1); 126393#L681-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 126394#L584 assume !(1 == ~M_E~0); 126595#L584-2 assume !(1 == ~T1_E~0); 126552#L589-1 assume !(1 == ~T2_E~0); 126553#L594-1 assume !(1 == ~T3_E~0); 126653#L599-1 assume !(1 == ~T4_E~0); 126425#L604-1 assume !(1 == ~E_M~0); 126409#L609-1 assume !(1 == ~E_1~0); 126410#L614-1 assume !(1 == ~E_2~0); 126527#L619-1 assume !(1 == ~E_3~0); 126618#L624-1 assume !(1 == ~E_4~0); 126709#L629-1 assume { :end_inline_reset_delta_events } true; 126898#L815-2 assume !false; 131013#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 131007#L501 [2021-12-16 10:04:39,941 INFO L793 eck$LassoCheckResult]: Loop: 131007#L501 assume !false; 131001#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 130726#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 130719#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 130720#L426 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 130712#L440 assume 0 != eval_~tmp~0#1; 130713#L440-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 130708#L448 assume !(0 != eval_~tmp_ndt_1~0#1); 129579#L445 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 129575#L462 assume !(0 != eval_~tmp_ndt_2~0#1); 129544#L459 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 129509#L476 assume !(0 != eval_~tmp_ndt_3~0#1); 129511#L473 assume !(0 == ~t3_st~0); 131017#L487 assume !(0 == ~t4_st~0); 131007#L501 [2021-12-16 10:04:39,941 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:39,941 INFO L85 PathProgramCache]: Analyzing trace with hash 39728939, now seen corresponding path program 3 times [2021-12-16 10:04:39,941 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:39,941 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1946364549] [2021-12-16 10:04:39,942 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:39,942 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:39,947 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:04:39,947 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-16 10:04:39,951 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:04:39,957 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-16 10:04:39,958 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:39,958 INFO L85 PathProgramCache]: Analyzing trace with hash -331803221, now seen corresponding path program 1 times [2021-12-16 10:04:39,958 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:39,958 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1818034707] [2021-12-16 10:04:39,958 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:39,958 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:39,961 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:04:39,961 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-16 10:04:39,962 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:04:39,963 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-16 10:04:39,963 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:39,963 INFO L85 PathProgramCache]: Analyzing trace with hash 1407875925, now seen corresponding path program 1 times [2021-12-16 10:04:39,964 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:39,964 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1390116971] [2021-12-16 10:04:39,964 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:39,964 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:39,969 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:04:39,981 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:04:39,981 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:04:39,982 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1390116971] [2021-12-16 10:04:39,982 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1390116971] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:04:39,982 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:04:39,982 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:04:39,982 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [969861707] [2021-12-16 10:04:39,982 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:04:40,064 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:04:40,064 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-16 10:04:40,065 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-16 10:04:40,065 INFO L87 Difference]: Start difference. First operand 12005 states and 15950 transitions. cyclomatic complexity: 3951 Second operand has 3 states, 3 states have (on average 26.0) internal successors, (78), 3 states have internal predecessors, (78), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:04:40,139 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:04:40,140 INFO L93 Difference]: Finished difference Result 21422 states and 28363 transitions. [2021-12-16 10:04:40,140 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-16 10:04:40,140 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 21422 states and 28363 transitions. [2021-12-16 10:04:40,269 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 21304 [2021-12-16 10:04:40,312 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 21422 states to 21422 states and 28363 transitions. [2021-12-16 10:04:40,313 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 21422 [2021-12-16 10:04:40,327 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 21422 [2021-12-16 10:04:40,327 INFO L73 IsDeterministic]: Start isDeterministic. Operand 21422 states and 28363 transitions. [2021-12-16 10:04:40,340 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:04:40,340 INFO L681 BuchiCegarLoop]: Abstraction has 21422 states and 28363 transitions. [2021-12-16 10:04:40,351 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21422 states and 28363 transitions. [2021-12-16 10:04:40,487 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21422 to 20762. [2021-12-16 10:04:40,506 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 20762 states, 20762 states have (on average 1.325643001637607) internal successors, (27523), 20761 states have internal predecessors, (27523), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:04:40,535 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20762 states to 20762 states and 27523 transitions. [2021-12-16 10:04:40,535 INFO L704 BuchiCegarLoop]: Abstraction has 20762 states and 27523 transitions. [2021-12-16 10:04:40,536 INFO L587 BuchiCegarLoop]: Abstraction has 20762 states and 27523 transitions. [2021-12-16 10:04:40,536 INFO L425 BuchiCegarLoop]: ======== Iteration 20============ [2021-12-16 10:04:40,536 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 20762 states and 27523 transitions. [2021-12-16 10:04:40,591 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 20644 [2021-12-16 10:04:40,592 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:04:40,592 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:04:40,592 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:40,593 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:40,593 INFO L791 eck$LassoCheckResult]: Stem: 160363#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 160310#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 160056#L778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 159848#L358 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 159849#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 159924#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 160200#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 160143#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 160144#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 160176#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 160155#L526 assume !(0 == ~M_E~0); 160156#L526-2 assume !(0 == ~T1_E~0); 160202#L531-1 assume !(0 == ~T2_E~0); 160139#L536-1 assume !(0 == ~T3_E~0); 160140#L541-1 assume !(0 == ~T4_E~0); 160134#L546-1 assume !(0 == ~E_M~0); 160135#L551-1 assume !(0 == ~E_1~0); 160111#L556-1 assume !(0 == ~E_2~0); 160112#L561-1 assume !(0 == ~E_3~0); 160121#L566-1 assume !(0 == ~E_4~0); 160122#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 160116#L262 assume !(1 == ~m_pc~0); 160117#L262-2 is_master_triggered_~__retres1~0#1 := 0; 160323#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 159968#L274 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 159969#L649 assume !(0 != activate_threads_~tmp~1#1); 160321#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 160060#L281 assume !(1 == ~t1_pc~0); 160061#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 159972#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 159973#L293 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 160031#L657 assume !(0 != activate_threads_~tmp___0~0#1); 160032#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 160123#L300 assume !(1 == ~t2_pc~0); 160124#L300-2 is_transmit2_triggered_~__retres1~2#1 := 0; 160245#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 160025#L312 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 160026#L665 assume !(0 != activate_threads_~tmp___1~0#1); 159902#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 159903#L319 assume !(1 == ~t3_pc~0); 159861#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 159862#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 160051#L331 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 160052#L673 assume !(0 != activate_threads_~tmp___2~0#1); 159882#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 159883#L338 assume !(1 == ~t4_pc~0); 159947#L338-2 is_transmit4_triggered_~__retres1~4#1 := 0; 159948#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 159963#L350 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 159989#L681 assume !(0 != activate_threads_~tmp___3~0#1); 159828#L681-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 159829#L584 assume !(1 == ~M_E~0); 160028#L584-2 assume !(1 == ~T1_E~0); 159987#L589-1 assume !(1 == ~T2_E~0); 159988#L594-1 assume !(1 == ~T3_E~0); 160082#L599-1 assume !(1 == ~T4_E~0); 159860#L604-1 assume !(1 == ~E_M~0); 159844#L609-1 assume !(1 == ~E_1~0); 159845#L614-1 assume !(1 == ~E_2~0); 159962#L619-1 assume !(1 == ~E_3~0); 160050#L624-1 assume !(1 == ~E_4~0); 160145#L629-1 assume { :end_inline_reset_delta_events } true; 160334#L815-2 assume !false; 166154#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 166153#L501 [2021-12-16 10:04:40,593 INFO L793 eck$LassoCheckResult]: Loop: 166153#L501 assume !false; 166152#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 166150#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 166149#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 166148#L426 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 166147#L440 assume 0 != eval_~tmp~0#1; 166145#L440-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 166143#L448 assume !(0 != eval_~tmp_ndt_1~0#1); 166142#L445 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 166140#L462 assume !(0 != eval_~tmp_ndt_2~0#1); 166139#L459 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 166138#L476 assume !(0 != eval_~tmp_ndt_3~0#1); 166137#L473 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 164266#L490 assume !(0 != eval_~tmp_ndt_4~0#1); 166136#L487 assume !(0 == ~t4_st~0); 166153#L501 [2021-12-16 10:04:40,593 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:40,593 INFO L85 PathProgramCache]: Analyzing trace with hash 39728939, now seen corresponding path program 4 times [2021-12-16 10:04:40,594 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:40,594 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1946760330] [2021-12-16 10:04:40,594 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:40,594 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:40,598 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:04:40,598 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-16 10:04:40,602 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:04:40,607 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-16 10:04:40,608 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:40,608 INFO L85 PathProgramCache]: Analyzing trace with hash -1696117078, now seen corresponding path program 1 times [2021-12-16 10:04:40,608 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:40,608 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [377527127] [2021-12-16 10:04:40,608 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:40,608 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:40,610 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:04:40,611 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-16 10:04:40,612 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:04:40,613 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-16 10:04:40,613 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:40,613 INFO L85 PathProgramCache]: Analyzing trace with hash 694328896, now seen corresponding path program 1 times [2021-12-16 10:04:40,613 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:40,613 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1722434337] [2021-12-16 10:04:40,613 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:40,614 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:40,618 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:04:40,628 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:04:40,628 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:04:40,628 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1722434337] [2021-12-16 10:04:40,628 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1722434337] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:04:40,628 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:04:40,628 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-16 10:04:40,629 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [858133653] [2021-12-16 10:04:40,629 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:04:40,720 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:04:40,721 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-16 10:04:40,721 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-16 10:04:40,721 INFO L87 Difference]: Start difference. First operand 20762 states and 27523 transitions. cyclomatic complexity: 6767 Second operand has 3 states, 2 states have (on average 39.5) internal successors, (79), 3 states have internal predecessors, (79), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:04:40,833 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:04:40,833 INFO L93 Difference]: Finished difference Result 35776 states and 47343 transitions. [2021-12-16 10:04:40,834 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-16 10:04:40,834 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 35776 states and 47343 transitions. [2021-12-16 10:04:40,996 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 35606 [2021-12-16 10:04:41,234 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 35776 states to 35776 states and 47343 transitions. [2021-12-16 10:04:41,234 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 35776 [2021-12-16 10:04:41,253 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 35776 [2021-12-16 10:04:41,253 INFO L73 IsDeterministic]: Start isDeterministic. Operand 35776 states and 47343 transitions. [2021-12-16 10:04:41,271 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:04:41,272 INFO L681 BuchiCegarLoop]: Abstraction has 35776 states and 47343 transitions. [2021-12-16 10:04:41,285 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 35776 states and 47343 transitions. [2021-12-16 10:04:41,582 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 35776 to 35296. [2021-12-16 10:04:41,613 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 35296 states, 35296 states have (on average 1.3277141885766093) internal successors, (46863), 35295 states have internal predecessors, (46863), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:04:41,671 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 35296 states to 35296 states and 46863 transitions. [2021-12-16 10:04:41,672 INFO L704 BuchiCegarLoop]: Abstraction has 35296 states and 46863 transitions. [2021-12-16 10:04:41,672 INFO L587 BuchiCegarLoop]: Abstraction has 35296 states and 46863 transitions. [2021-12-16 10:04:41,672 INFO L425 BuchiCegarLoop]: ======== Iteration 21============ [2021-12-16 10:04:41,672 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 35296 states and 46863 transitions. [2021-12-16 10:04:41,871 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 35126 [2021-12-16 10:04:41,871 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:04:41,871 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:04:41,872 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:41,872 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:04:41,872 INFO L791 eck$LassoCheckResult]: Stem: 216921#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 216875#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 216612#L778 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 216394#L358 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 216395#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 216472#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 216755#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 216695#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 216696#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 216732#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 216709#L526 assume !(0 == ~M_E~0); 216710#L526-2 assume !(0 == ~T1_E~0); 216757#L531-1 assume !(0 == ~T2_E~0); 216691#L536-1 assume !(0 == ~T3_E~0); 216692#L541-1 assume !(0 == ~T4_E~0); 216687#L546-1 assume !(0 == ~E_M~0); 216688#L551-1 assume !(0 == ~E_1~0); 216663#L556-1 assume !(0 == ~E_2~0); 216664#L561-1 assume !(0 == ~E_3~0); 216673#L566-1 assume !(0 == ~E_4~0); 216674#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 216668#L262 assume !(1 == ~m_pc~0); 216669#L262-2 is_master_triggered_~__retres1~0#1 := 0; 216885#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 216520#L274 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 216521#L649 assume !(0 != activate_threads_~tmp~1#1); 216884#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 216613#L281 assume !(1 == ~t1_pc~0); 216614#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 216522#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 216523#L293 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 216583#L657 assume !(0 != activate_threads_~tmp___0~0#1); 216584#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 216675#L300 assume !(1 == ~t2_pc~0); 216676#L300-2 is_transmit2_triggered_~__retres1~2#1 := 0; 216800#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 216577#L312 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 216578#L665 assume !(0 != activate_threads_~tmp___1~0#1); 216450#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 216451#L319 assume !(1 == ~t3_pc~0); 216407#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 216408#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 216604#L331 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 216605#L673 assume !(0 != activate_threads_~tmp___2~0#1); 216429#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 216430#L338 assume !(1 == ~t4_pc~0); 216496#L338-2 is_transmit4_triggered_~__retres1~4#1 := 0; 216497#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 216515#L350 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 216539#L681 assume !(0 != activate_threads_~tmp___3~0#1); 216374#L681-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 216375#L584 assume !(1 == ~M_E~0); 216580#L584-2 assume !(1 == ~T1_E~0); 216537#L589-1 assume !(1 == ~T2_E~0); 216538#L594-1 assume !(1 == ~T3_E~0); 216638#L599-1 assume !(1 == ~T4_E~0); 216406#L604-1 assume !(1 == ~E_M~0); 216390#L609-1 assume !(1 == ~E_1~0); 216391#L614-1 assume !(1 == ~E_2~0); 216512#L619-1 assume !(1 == ~E_3~0); 216603#L624-1 assume !(1 == ~E_4~0); 216697#L629-1 assume { :end_inline_reset_delta_events } true; 216900#L815-2 assume !false; 225997#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 225960#L501 [2021-12-16 10:04:41,873 INFO L793 eck$LassoCheckResult]: Loop: 225960#L501 assume !false; 225993#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 225989#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 225987#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 225986#L426 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 225985#L440 assume 0 != eval_~tmp~0#1; 225982#L440-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 225979#L448 assume !(0 != eval_~tmp_ndt_1~0#1); 225977#L445 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 225974#L462 assume !(0 != eval_~tmp_ndt_2~0#1); 225972#L459 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 225970#L476 assume !(0 != eval_~tmp_ndt_3~0#1); 225966#L473 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 225963#L490 assume !(0 != eval_~tmp_ndt_4~0#1); 225961#L487 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0#1;eval_~tmp_ndt_5~0#1 := eval_#t~nondet11#1;havoc eval_#t~nondet11#1; 224766#L504 assume !(0 != eval_~tmp_ndt_5~0#1); 225960#L501 [2021-12-16 10:04:41,873 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:41,873 INFO L85 PathProgramCache]: Analyzing trace with hash 39728939, now seen corresponding path program 5 times [2021-12-16 10:04:41,874 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:41,874 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [827315986] [2021-12-16 10:04:41,874 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:41,874 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:41,879 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:04:41,880 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-16 10:04:41,883 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:04:41,889 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-16 10:04:41,889 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:41,889 INFO L85 PathProgramCache]: Analyzing trace with hash -1040025477, now seen corresponding path program 1 times [2021-12-16 10:04:41,890 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:41,890 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [233384406] [2021-12-16 10:04:41,890 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:41,890 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:41,892 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:04:41,892 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-16 10:04:41,894 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:04:41,895 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-16 10:04:41,895 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:04:41,895 INFO L85 PathProgramCache]: Analyzing trace with hash 49355685, now seen corresponding path program 1 times [2021-12-16 10:04:41,895 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:04:41,895 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1431359848] [2021-12-16 10:04:41,895 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:04:41,896 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:04:41,900 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:04:41,901 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-16 10:04:41,904 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:04:41,913 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-16 10:04:43,029 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 16.12 10:04:43 BoogieIcfgContainer [2021-12-16 10:04:43,029 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2021-12-16 10:04:43,029 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2021-12-16 10:04:43,030 INFO L271 PluginConnector]: Initializing Witness Printer... [2021-12-16 10:04:43,030 INFO L275 PluginConnector]: Witness Printer initialized [2021-12-16 10:04:43,030 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 16.12 10:04:35" (3/4) ... [2021-12-16 10:04:43,032 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2021-12-16 10:04:43,084 INFO L141 WitnessManager]: Wrote witness to /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/witness.graphml [2021-12-16 10:04:43,085 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2021-12-16 10:04:43,085 INFO L158 Benchmark]: Toolchain (without parser) took 8943.64ms. Allocated memory was 102.8MB in the beginning and 1.5GB in the end (delta: 1.4GB). Free memory was 73.4MB in the beginning and 1.2GB in the end (delta: -1.1GB). Peak memory consumption was 296.7MB. Max. memory is 16.1GB. [2021-12-16 10:04:43,086 INFO L158 Benchmark]: CDTParser took 0.17ms. Allocated memory is still 102.8MB. Free memory is still 62.4MB. There was no memory consumed. Max. memory is 16.1GB. [2021-12-16 10:04:43,086 INFO L158 Benchmark]: CACSL2BoogieTranslator took 268.14ms. Allocated memory was 102.8MB in the beginning and 123.7MB in the end (delta: 21.0MB). Free memory was 73.1MB in the beginning and 95.2MB in the end (delta: -22.0MB). Peak memory consumption was 11.6MB. Max. memory is 16.1GB. [2021-12-16 10:04:43,086 INFO L158 Benchmark]: Boogie Procedure Inliner took 59.84ms. Allocated memory is still 123.7MB. Free memory was 95.2MB in the beginning and 90.7MB in the end (delta: 4.5MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2021-12-16 10:04:43,086 INFO L158 Benchmark]: Boogie Preprocessor took 54.62ms. Allocated memory is still 123.7MB. Free memory was 90.7MB in the beginning and 87.4MB in the end (delta: 3.3MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2021-12-16 10:04:43,087 INFO L158 Benchmark]: RCFGBuilder took 711.75ms. Allocated memory is still 123.7MB. Free memory was 86.9MB in the beginning and 83.3MB in the end (delta: 3.6MB). Peak memory consumption was 30.4MB. Max. memory is 16.1GB. [2021-12-16 10:04:43,087 INFO L158 Benchmark]: BuchiAutomizer took 7789.72ms. Allocated memory was 123.7MB in the beginning and 1.5GB in the end (delta: 1.4GB). Free memory was 83.3MB in the beginning and 1.2GB in the end (delta: -1.1GB). Peak memory consumption was 447.6MB. Max. memory is 16.1GB. [2021-12-16 10:04:43,087 INFO L158 Benchmark]: Witness Printer took 55.35ms. Allocated memory is still 1.5GB. Free memory was 1.2GB in the beginning and 1.2GB in the end (delta: 3.1MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2021-12-16 10:04:43,088 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.17ms. Allocated memory is still 102.8MB. Free memory is still 62.4MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 268.14ms. Allocated memory was 102.8MB in the beginning and 123.7MB in the end (delta: 21.0MB). Free memory was 73.1MB in the beginning and 95.2MB in the end (delta: -22.0MB). Peak memory consumption was 11.6MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 59.84ms. Allocated memory is still 123.7MB. Free memory was 95.2MB in the beginning and 90.7MB in the end (delta: 4.5MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * Boogie Preprocessor took 54.62ms. Allocated memory is still 123.7MB. Free memory was 90.7MB in the beginning and 87.4MB in the end (delta: 3.3MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * RCFGBuilder took 711.75ms. Allocated memory is still 123.7MB. Free memory was 86.9MB in the beginning and 83.3MB in the end (delta: 3.6MB). Peak memory consumption was 30.4MB. Max. memory is 16.1GB. * BuchiAutomizer took 7789.72ms. Allocated memory was 123.7MB in the beginning and 1.5GB in the end (delta: 1.4GB). Free memory was 83.3MB in the beginning and 1.2GB in the end (delta: -1.1GB). Peak memory consumption was 447.6MB. Max. memory is 16.1GB. * Witness Printer took 55.35ms. Allocated memory is still 1.5GB. Free memory was 1.2GB in the beginning and 1.2GB in the end (delta: 3.1MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 20 terminating modules (20 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.20 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 35296 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 7.7s and 21 iterations. TraceHistogramMax:1. Analysis of lassos took 2.9s. Construction of modules took 0.3s. Büchi inclusion checks took 0.8s. Highest rank in rank-based complementation 0. Minimization of det autom 20. Minimization of nondet autom 0. Automata minimization 1.6s AutomataMinimizationTime, 20 MinimizatonAttempts, 19265 StatesRemovedByMinimization, 11 NontrivialMinimizations. Non-live state removal took 1.1s Buchi closure took 0.0s. Biggest automaton had 35296 states and ocurred in iteration 20. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 16480 SdHoareTripleChecker+Valid, 0.5s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 16480 mSDsluCounter, 28670 SdHoareTripleChecker+Invalid, 0.4s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 14709 mSDsCounter, 256 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 566 IncrementalHoareTripleChecker+Invalid, 822 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 256 mSolverCounterUnsat, 13961 mSDtfsCounter, 566 mSolverCounterSat, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI4 SFLT0 conc4 concLT0 SILN1 SILU0 SILI11 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - FixpointNonTerminationResult [Line: 435]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite execution State at position 0 is {NULL=1} State at position 1 is {tmp_ndt_3=0, NULL=0, t3_st=0, token=0, NULL=1, tmp=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@1d91083=0, t2_st=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@3bbe1a10=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@3eeb2dde=0, tmp_ndt_2=0, t4_i=1, \result=0, E_3=2, t4_pc=0, E_1=2, tmp_ndt_1=0, __retres1=1, tmp=1, \result=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@5d18d16f=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@e2faec0=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@b33f715=0, m_st=0, NULL=0, t3_pc=0, tmp___3=0, __retres1=0, tmp___0=0, __retres1=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@737aadaf=0, tmp___2=0, m_pc=0, \result=0, \result=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@698d175=0, \result=0, \result=0, tmp___1=0, __retres1=0, T2_E=2, tmp=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@50472a70=0, t1_pc=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@19cbd87=0, E_2=2, tmp___0=0, E_4=2, T1_E=2, __retres1=0, M_E=2, t2_i=1, T4_E=2, \result=0, t3_i=1, t4_st=0, m_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@764291db=0, t1_st=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@374d67d7=0, __retres1=0, local=0, t2_pc=0, tmp_ndt_5=0, __retres1=0, tmp_ndt_4=0, E_M=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@3a6ee64b=0, kernel_st=1, T3_E=2, t1_i=1} - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 435]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L24] int m_pc = 0; [L25] int t1_pc = 0; [L26] int t2_pc = 0; [L27] int t3_pc = 0; [L28] int t4_pc = 0; [L29] int m_st ; [L30] int t1_st ; [L31] int t2_st ; [L32] int t3_st ; [L33] int t4_st ; [L34] int m_i ; [L35] int t1_i ; [L36] int t2_i ; [L37] int t3_i ; [L38] int t4_i ; [L39] int M_E = 2; [L40] int T1_E = 2; [L41] int T2_E = 2; [L42] int T3_E = 2; [L43] int T4_E = 2; [L44] int E_M = 2; [L45] int E_1 = 2; [L46] int E_2 = 2; [L47] int E_3 = 2; [L48] int E_4 = 2; [L55] int token ; [L57] int local ; [L860] int __retres1 ; [L864] CALL init_model() [L772] m_i = 1 [L773] t1_i = 1 [L774] t2_i = 1 [L775] t3_i = 1 [L776] t4_i = 1 [L864] RET init_model() [L865] CALL start_simulation() [L801] int kernel_st ; [L802] int tmp ; [L803] int tmp___0 ; [L807] kernel_st = 0 [L808] FCALL update_channels() [L809] CALL init_threads() [L365] COND TRUE m_i == 1 [L366] m_st = 0 [L370] COND TRUE t1_i == 1 [L371] t1_st = 0 [L375] COND TRUE t2_i == 1 [L376] t2_st = 0 [L380] COND TRUE t3_i == 1 [L381] t3_st = 0 [L385] COND TRUE t4_i == 1 [L386] t4_st = 0 [L809] RET init_threads() [L810] CALL fire_delta_events() [L526] COND FALSE !(M_E == 0) [L531] COND FALSE !(T1_E == 0) [L536] COND FALSE !(T2_E == 0) [L541] COND FALSE !(T3_E == 0) [L546] COND FALSE !(T4_E == 0) [L551] COND FALSE !(E_M == 0) [L556] COND FALSE !(E_1 == 0) [L561] COND FALSE !(E_2 == 0) [L566] COND FALSE !(E_3 == 0) [L571] COND FALSE !(E_4 == 0) [L810] RET fire_delta_events() [L811] CALL activate_threads() [L639] int tmp ; [L640] int tmp___0 ; [L641] int tmp___1 ; [L642] int tmp___2 ; [L643] int tmp___3 ; [L647] CALL, EXPR is_master_triggered() [L259] int __retres1 ; [L262] COND FALSE !(m_pc == 1) [L272] __retres1 = 0 [L274] return (__retres1); [L647] RET, EXPR is_master_triggered() [L647] tmp = is_master_triggered() [L649] COND FALSE !(\read(tmp)) [L655] CALL, EXPR is_transmit1_triggered() [L278] int __retres1 ; [L281] COND FALSE !(t1_pc == 1) [L291] __retres1 = 0 [L293] return (__retres1); [L655] RET, EXPR is_transmit1_triggered() [L655] tmp___0 = is_transmit1_triggered() [L657] COND FALSE !(\read(tmp___0)) [L663] CALL, EXPR is_transmit2_triggered() [L297] int __retres1 ; [L300] COND FALSE !(t2_pc == 1) [L310] __retres1 = 0 [L312] return (__retres1); [L663] RET, EXPR is_transmit2_triggered() [L663] tmp___1 = is_transmit2_triggered() [L665] COND FALSE !(\read(tmp___1)) [L671] CALL, EXPR is_transmit3_triggered() [L316] int __retres1 ; [L319] COND FALSE !(t3_pc == 1) [L329] __retres1 = 0 [L331] return (__retres1); [L671] RET, EXPR is_transmit3_triggered() [L671] tmp___2 = is_transmit3_triggered() [L673] COND FALSE !(\read(tmp___2)) [L679] CALL, EXPR is_transmit4_triggered() [L335] int __retres1 ; [L338] COND FALSE !(t4_pc == 1) [L348] __retres1 = 0 [L350] return (__retres1); [L679] RET, EXPR is_transmit4_triggered() [L679] tmp___3 = is_transmit4_triggered() [L681] COND FALSE !(\read(tmp___3)) [L811] RET activate_threads() [L812] CALL reset_delta_events() [L584] COND FALSE !(M_E == 1) [L589] COND FALSE !(T1_E == 1) [L594] COND FALSE !(T2_E == 1) [L599] COND FALSE !(T3_E == 1) [L604] COND FALSE !(T4_E == 1) [L609] COND FALSE !(E_M == 1) [L614] COND FALSE !(E_1 == 1) [L619] COND FALSE !(E_2 == 1) [L624] COND FALSE !(E_3 == 1) [L629] COND FALSE !(E_4 == 1) [L812] RET reset_delta_events() [L815] COND TRUE 1 [L818] kernel_st = 1 [L819] CALL eval() [L431] int tmp ; Loop: [L435] COND TRUE 1 [L438] CALL, EXPR exists_runnable_thread() [L395] int __retres1 ; [L398] COND TRUE m_st == 0 [L399] __retres1 = 1 [L426] return (__retres1); [L438] RET, EXPR exists_runnable_thread() [L438] tmp = exists_runnable_thread() [L440] COND TRUE \read(tmp) [L445] COND TRUE m_st == 0 [L446] int tmp_ndt_1; [L447] tmp_ndt_1 = __VERIFIER_nondet_int() [L448] COND FALSE !(\read(tmp_ndt_1)) [L459] COND TRUE t1_st == 0 [L460] int tmp_ndt_2; [L461] tmp_ndt_2 = __VERIFIER_nondet_int() [L462] COND FALSE !(\read(tmp_ndt_2)) [L473] COND TRUE t2_st == 0 [L474] int tmp_ndt_3; [L475] tmp_ndt_3 = __VERIFIER_nondet_int() [L476] COND FALSE !(\read(tmp_ndt_3)) [L487] COND TRUE t3_st == 0 [L488] int tmp_ndt_4; [L489] tmp_ndt_4 = __VERIFIER_nondet_int() [L490] COND FALSE !(\read(tmp_ndt_4)) [L501] COND TRUE t4_st == 0 [L502] int tmp_ndt_5; [L503] tmp_ndt_5 = __VERIFIER_nondet_int() [L504] COND FALSE !(\read(tmp_ndt_5)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2021-12-16 10:04:43,141 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Ended with exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)