./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/token_ring.11.cil-1.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version c3fed411 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/token_ring.11.cil-1.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 79f20a4b12634e812af836a5fe92e9d987e7766e2c28337c49504608346f2347 --- Real Ultimate output --- This is Ultimate 0.2.2-tmp.no-commuhash-c3fed41 [2021-12-16 10:05:11,024 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-12-16 10:05:11,025 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-12-16 10:05:11,051 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-12-16 10:05:11,051 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-12-16 10:05:11,055 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-12-16 10:05:11,057 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-12-16 10:05:11,062 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-12-16 10:05:11,063 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-12-16 10:05:11,068 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-12-16 10:05:11,069 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-12-16 10:05:11,070 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-12-16 10:05:11,070 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-12-16 10:05:11,072 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-12-16 10:05:11,074 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-12-16 10:05:11,075 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-12-16 10:05:11,076 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-12-16 10:05:11,077 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-12-16 10:05:11,081 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-12-16 10:05:11,084 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-12-16 10:05:11,086 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-12-16 10:05:11,086 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-12-16 10:05:11,088 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-12-16 10:05:11,088 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-12-16 10:05:11,091 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-12-16 10:05:11,091 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-12-16 10:05:11,091 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-12-16 10:05:11,092 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-12-16 10:05:11,093 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-12-16 10:05:11,093 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-12-16 10:05:11,094 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-12-16 10:05:11,094 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-12-16 10:05:11,095 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-12-16 10:05:11,096 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-12-16 10:05:11,097 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-12-16 10:05:11,097 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-12-16 10:05:11,098 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-12-16 10:05:11,098 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-12-16 10:05:11,098 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-12-16 10:05:11,098 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-12-16 10:05:11,099 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-12-16 10:05:11,100 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2021-12-16 10:05:11,131 INFO L113 SettingsManager]: Loading preferences was successful [2021-12-16 10:05:11,132 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-12-16 10:05:11,132 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2021-12-16 10:05:11,132 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2021-12-16 10:05:11,133 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-12-16 10:05:11,133 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-12-16 10:05:11,133 INFO L138 SettingsManager]: * Use SBE=true [2021-12-16 10:05:11,134 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2021-12-16 10:05:11,134 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2021-12-16 10:05:11,134 INFO L138 SettingsManager]: * Use old map elimination=false [2021-12-16 10:05:11,134 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2021-12-16 10:05:11,135 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2021-12-16 10:05:11,135 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2021-12-16 10:05:11,135 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-12-16 10:05:11,135 INFO L138 SettingsManager]: * sizeof long=4 [2021-12-16 10:05:11,135 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2021-12-16 10:05:11,135 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-12-16 10:05:11,135 INFO L138 SettingsManager]: * sizeof POINTER=4 [2021-12-16 10:05:11,136 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-12-16 10:05:11,136 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2021-12-16 10:05:11,136 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2021-12-16 10:05:11,136 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2021-12-16 10:05:11,136 INFO L138 SettingsManager]: * sizeof long double=12 [2021-12-16 10:05:11,136 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-12-16 10:05:11,136 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2021-12-16 10:05:11,137 INFO L138 SettingsManager]: * Use constant arrays=true [2021-12-16 10:05:11,137 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2021-12-16 10:05:11,137 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-12-16 10:05:11,137 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-12-16 10:05:11,137 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-12-16 10:05:11,137 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-12-16 10:05:11,138 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2021-12-16 10:05:11,138 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2021-12-16 10:05:11,139 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 79f20a4b12634e812af836a5fe92e9d987e7766e2c28337c49504608346f2347 [2021-12-16 10:05:11,359 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-12-16 10:05:11,391 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-12-16 10:05:11,393 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-12-16 10:05:11,394 INFO L271 PluginConnector]: Initializing CDTParser... [2021-12-16 10:05:11,394 INFO L275 PluginConnector]: CDTParser initialized [2021-12-16 10:05:11,396 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/token_ring.11.cil-1.c [2021-12-16 10:05:11,451 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/6ac327b2c/c42c1b5949b741aa95fb367b2e3d01da/FLAG2396100d3 [2021-12-16 10:05:11,798 INFO L306 CDTParser]: Found 1 translation units. [2021-12-16 10:05:11,799 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.11.cil-1.c [2021-12-16 10:05:11,808 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/6ac327b2c/c42c1b5949b741aa95fb367b2e3d01da/FLAG2396100d3 [2021-12-16 10:05:12,188 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/6ac327b2c/c42c1b5949b741aa95fb367b2e3d01da [2021-12-16 10:05:12,199 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-12-16 10:05:12,200 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-12-16 10:05:12,201 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-12-16 10:05:12,202 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-12-16 10:05:12,212 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-12-16 10:05:12,213 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 16.12 10:05:12" (1/1) ... [2021-12-16 10:05:12,214 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@43b09415 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:05:12, skipping insertion in model container [2021-12-16 10:05:12,214 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 16.12 10:05:12" (1/1) ... [2021-12-16 10:05:12,219 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-12-16 10:05:12,257 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-12-16 10:05:12,382 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.11.cil-1.c[671,684] [2021-12-16 10:05:12,500 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-16 10:05:12,509 INFO L203 MainTranslator]: Completed pre-run [2021-12-16 10:05:12,527 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.11.cil-1.c[671,684] [2021-12-16 10:05:12,577 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-16 10:05:12,602 INFO L208 MainTranslator]: Completed translation [2021-12-16 10:05:12,603 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:05:12 WrapperNode [2021-12-16 10:05:12,603 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-12-16 10:05:12,604 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-12-16 10:05:12,604 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-12-16 10:05:12,604 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-12-16 10:05:12,609 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:05:12" (1/1) ... [2021-12-16 10:05:12,628 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:05:12" (1/1) ... [2021-12-16 10:05:12,701 INFO L137 Inliner]: procedures = 50, calls = 65, calls flagged for inlining = 60, calls inlined = 239, statements flattened = 3657 [2021-12-16 10:05:12,702 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-12-16 10:05:12,702 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-12-16 10:05:12,703 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-12-16 10:05:12,703 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-12-16 10:05:12,709 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:05:12" (1/1) ... [2021-12-16 10:05:12,709 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:05:12" (1/1) ... [2021-12-16 10:05:12,719 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:05:12" (1/1) ... [2021-12-16 10:05:12,719 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:05:12" (1/1) ... [2021-12-16 10:05:12,758 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:05:12" (1/1) ... [2021-12-16 10:05:12,787 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:05:12" (1/1) ... [2021-12-16 10:05:12,795 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:05:12" (1/1) ... [2021-12-16 10:05:12,808 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-12-16 10:05:12,810 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-12-16 10:05:12,810 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-12-16 10:05:12,811 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-12-16 10:05:12,811 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:05:12" (1/1) ... [2021-12-16 10:05:12,817 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-16 10:05:12,824 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-16 10:05:12,849 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-16 10:05:12,867 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2021-12-16 10:05:12,877 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2021-12-16 10:05:12,877 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2021-12-16 10:05:12,878 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-12-16 10:05:12,878 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-12-16 10:05:12,950 INFO L236 CfgBuilder]: Building ICFG [2021-12-16 10:05:12,964 INFO L262 CfgBuilder]: Building CFG for each procedure with an implementation [2021-12-16 10:05:14,457 INFO L277 CfgBuilder]: Performing block encoding [2021-12-16 10:05:14,468 INFO L296 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-12-16 10:05:14,469 INFO L301 CfgBuilder]: Removed 14 assume(true) statements. [2021-12-16 10:05:14,471 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 16.12 10:05:14 BoogieIcfgContainer [2021-12-16 10:05:14,472 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-12-16 10:05:14,473 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2021-12-16 10:05:14,473 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2021-12-16 10:05:14,475 INFO L275 PluginConnector]: BuchiAutomizer initialized [2021-12-16 10:05:14,476 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-16 10:05:14,476 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 16.12 10:05:12" (1/3) ... [2021-12-16 10:05:14,477 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@1ba49d84 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 16.12 10:05:14, skipping insertion in model container [2021-12-16 10:05:14,478 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-16 10:05:14,478 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:05:12" (2/3) ... [2021-12-16 10:05:14,478 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@1ba49d84 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 16.12 10:05:14, skipping insertion in model container [2021-12-16 10:05:14,478 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-16 10:05:14,478 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 16.12 10:05:14" (3/3) ... [2021-12-16 10:05:14,479 INFO L388 chiAutomizerObserver]: Analyzing ICFG token_ring.11.cil-1.c [2021-12-16 10:05:14,508 INFO L359 BuchiCegarLoop]: Interprodecural is true [2021-12-16 10:05:14,509 INFO L360 BuchiCegarLoop]: Hoare is false [2021-12-16 10:05:14,509 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2021-12-16 10:05:14,509 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2021-12-16 10:05:14,509 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2021-12-16 10:05:14,509 INFO L364 BuchiCegarLoop]: Difference is false [2021-12-16 10:05:14,509 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2021-12-16 10:05:14,509 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2021-12-16 10:05:14,539 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1579 states, 1578 states have (on average 1.503168567807351) internal successors, (2372), 1578 states have internal predecessors, (2372), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:14,589 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1424 [2021-12-16 10:05:14,589 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:05:14,589 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:05:14,603 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:14,619 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:14,619 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2021-12-16 10:05:14,622 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1579 states, 1578 states have (on average 1.503168567807351) internal successors, (2372), 1578 states have internal predecessors, (2372), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:14,661 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1424 [2021-12-16 10:05:14,661 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:05:14,661 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:05:14,671 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:14,671 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:14,682 INFO L791 eck$LassoCheckResult]: Stem: 348#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 1498#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 780#L1653true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 968#L785true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 652#L792true assume !(1 == ~m_i~0);~m_st~0 := 2; 1000#L792-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 48#L797-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1412#L802-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1303#L807-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 629#L812-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 1135#L817-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 929#L822-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 1064#L827-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 1356#L832-1true assume 1 == ~t9_i~0;~t9_st~0 := 0; 1217#L837-1true assume !(1 == ~t10_i~0);~t10_st~0 := 2; 1224#L842-1true assume !(1 == ~t11_i~0);~t11_st~0 := 2; 1002#L847-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 795#L1121true assume !(0 == ~M_E~0); 575#L1121-2true assume !(0 == ~T1_E~0); 178#L1126-1true assume 0 == ~T2_E~0;~T2_E~0 := 1; 272#L1131-1true assume !(0 == ~T3_E~0); 327#L1136-1true assume !(0 == ~T4_E~0); 474#L1141-1true assume !(0 == ~T5_E~0); 1261#L1146-1true assume !(0 == ~T6_E~0); 728#L1151-1true assume !(0 == ~T7_E~0); 360#L1156-1true assume !(0 == ~T8_E~0); 41#L1161-1true assume !(0 == ~T9_E~0); 860#L1166-1true assume 0 == ~T10_E~0;~T10_E~0 := 1; 145#L1171-1true assume !(0 == ~T11_E~0); 742#L1176-1true assume !(0 == ~E_M~0); 886#L1181-1true assume !(0 == ~E_1~0); 1330#L1186-1true assume !(0 == ~E_2~0); 946#L1191-1true assume !(0 == ~E_3~0); 159#L1196-1true assume !(0 == ~E_4~0); 1340#L1201-1true assume !(0 == ~E_5~0); 1420#L1206-1true assume 0 == ~E_6~0;~E_6~0 := 1; 1003#L1211-1true assume !(0 == ~E_7~0); 1157#L1216-1true assume !(0 == ~E_8~0); 233#L1221-1true assume !(0 == ~E_9~0); 1086#L1226-1true assume !(0 == ~E_10~0); 87#L1231-1true assume !(0 == ~E_11~0); 1234#L1236-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 743#L556true assume 1 == ~m_pc~0; 757#L557true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 28#L567true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 538#L568true activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1136#L1391true assume !(0 != activate_threads_~tmp~1#1); 919#L1391-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1082#L575true assume !(1 == ~t1_pc~0); 6#L575-2true is_transmit1_triggered_~__retres1~1#1 := 0; 69#L586true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1075#L587true activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 240#L1399true assume !(0 != activate_threads_~tmp___0~0#1); 218#L1399-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 717#L594true assume 1 == ~t2_pc~0; 181#L595true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1521#L605true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 459#L606true activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 36#L1407true assume !(0 != activate_threads_~tmp___1~0#1); 64#L1407-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1209#L613true assume !(1 == ~t3_pc~0); 1543#L613-2true is_transmit3_triggered_~__retres1~3#1 := 0; 307#L624true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 85#L625true activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 473#L1415true assume !(0 != activate_threads_~tmp___2~0#1); 1078#L1415-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 294#L632true assume 1 == ~t4_pc~0; 638#L633true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 796#L643true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1342#L644true activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1496#L1423true assume !(0 != activate_threads_~tmp___3~0#1); 749#L1423-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 525#L651true assume 1 == ~t5_pc~0; 970#L652true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 124#L662true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 367#L663true activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 449#L1431true assume !(0 != activate_threads_~tmp___4~0#1); 132#L1431-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1111#L670true assume !(1 == ~t6_pc~0); 977#L670-2true is_transmit6_triggered_~__retres1~6#1 := 0; 321#L681true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1133#L682true activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1305#L1439true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 503#L1439-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1323#L689true assume 1 == ~t7_pc~0; 1516#L690true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 585#L700true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1573#L701true activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 999#L1447true assume !(0 != activate_threads_~tmp___6~0#1); 431#L1447-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1190#L708true assume !(1 == ~t8_pc~0); 176#L708-2true is_transmit8_triggered_~__retres1~8#1 := 0; 1131#L719true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1387#L720true activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1108#L1455true assume !(0 != activate_threads_~tmp___7~0#1); 209#L1455-2true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 280#L727true assume 1 == ~t9_pc~0; 1226#L728true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1409#L738true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1361#L739true activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1434#L1463true assume !(0 != activate_threads_~tmp___8~0#1); 1306#L1463-2true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 238#L746true assume !(1 == ~t10_pc~0); 706#L746-2true is_transmit10_triggered_~__retres1~10#1 := 0; 817#L757true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1435#L758true activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1123#L1471true assume !(0 != activate_threads_~tmp___9~0#1); 924#L1471-2true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 332#L765true assume 1 == ~t11_pc~0; 1364#L766true assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 1388#L776true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 12#L777true activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 975#L1479true assume !(0 != activate_threads_~tmp___10~0#1); 1166#L1479-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1105#L1249true assume !(1 == ~M_E~0); 642#L1249-2true assume !(1 == ~T1_E~0); 382#L1254-1true assume !(1 == ~T2_E~0); 34#L1259-1true assume !(1 == ~T3_E~0); 25#L1264-1true assume !(1 == ~T4_E~0); 1574#L1269-1true assume !(1 == ~T5_E~0); 1503#L1274-1true assume 1 == ~T6_E~0;~T6_E~0 := 2; 1245#L1279-1true assume !(1 == ~T7_E~0); 119#L1284-1true assume !(1 == ~T8_E~0); 1365#L1289-1true assume !(1 == ~T9_E~0); 414#L1294-1true assume !(1 == ~T10_E~0); 421#L1299-1true assume !(1 == ~T11_E~0); 1430#L1304-1true assume !(1 == ~E_M~0); 1461#L1309-1true assume !(1 == ~E_1~0); 1440#L1314-1true assume 1 == ~E_2~0;~E_2~0 := 2; 96#L1319-1true assume !(1 == ~E_3~0); 839#L1324-1true assume !(1 == ~E_4~0); 157#L1329-1true assume !(1 == ~E_5~0); 1043#L1334-1true assume !(1 == ~E_6~0); 1394#L1339-1true assume !(1 == ~E_7~0); 1170#L1344-1true assume !(1 == ~E_8~0); 1520#L1349-1true assume !(1 == ~E_9~0); 514#L1354-1true assume 1 == ~E_10~0;~E_10~0 := 2; 843#L1359-1true assume !(1 == ~E_11~0); 1369#L1364-1true assume { :end_inline_reset_delta_events } true; 202#L1690-2true [2021-12-16 10:05:14,689 INFO L793 eck$LassoCheckResult]: Loop: 202#L1690-2true assume !false; 871#L1691true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 857#L1096true assume !true; 680#L1111true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1378#L785-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 319#L1121-3true assume 0 == ~M_E~0;~M_E~0 := 1; 1515#L1121-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 1313#L1126-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 447#L1131-3true assume !(0 == ~T3_E~0); 1526#L1136-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 1508#L1141-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 751#L1146-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 175#L1151-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 1162#L1156-3true assume 0 == ~T8_E~0;~T8_E~0 := 1; 1380#L1161-3true assume 0 == ~T9_E~0;~T9_E~0 := 1; 576#L1166-3true assume 0 == ~T10_E~0;~T10_E~0 := 1; 1255#L1171-3true assume !(0 == ~T11_E~0); 609#L1176-3true assume 0 == ~E_M~0;~E_M~0 := 1; 200#L1181-3true assume 0 == ~E_1~0;~E_1~0 := 1; 1225#L1186-3true assume 0 == ~E_2~0;~E_2~0 := 1; 682#L1191-3true assume 0 == ~E_3~0;~E_3~0 := 1; 1213#L1196-3true assume 0 == ~E_4~0;~E_4~0 := 1; 898#L1201-3true assume 0 == ~E_5~0;~E_5~0 := 1; 1423#L1206-3true assume 0 == ~E_6~0;~E_6~0 := 1; 588#L1211-3true assume !(0 == ~E_7~0); 155#L1216-3true assume 0 == ~E_8~0;~E_8~0 := 1; 389#L1221-3true assume 0 == ~E_9~0;~E_9~0 := 1; 869#L1226-3true assume 0 == ~E_10~0;~E_10~0 := 1; 184#L1231-3true assume 0 == ~E_11~0;~E_11~0 := 1; 311#L1236-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1451#L556-39true assume 1 == ~m_pc~0; 691#L557-13true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 657#L567-13true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 237#L568-13true activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 336#L1391-39true assume !(0 != activate_threads_~tmp~1#1); 1296#L1391-41true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 621#L575-39true assume 1 == ~t1_pc~0; 1039#L576-13true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 904#L586-13true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 746#L587-13true activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1477#L1399-39true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 600#L1399-41true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 799#L594-39true assume !(1 == ~t2_pc~0); 1194#L594-41true is_transmit2_triggered_~__retres1~2#1 := 0; 602#L605-13true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1531#L606-13true activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1112#L1407-39true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 273#L1407-41true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1073#L613-39true assume 1 == ~t3_pc~0; 1468#L614-13true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 15#L624-13true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 418#L625-13true activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 807#L1415-39true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 61#L1415-41true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1493#L632-39true assume !(1 == ~t4_pc~0); 845#L632-41true is_transmit4_triggered_~__retres1~4#1 := 0; 368#L643-13true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 832#L644-13true activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1081#L1423-39true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1017#L1423-41true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 190#L651-39true assume 1 == ~t5_pc~0; 1557#L652-13true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 996#L662-13true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1180#L663-13true activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1271#L1431-39true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1500#L1431-41true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1367#L670-39true assume !(1 == ~t6_pc~0); 694#L670-41true is_transmit6_triggered_~__retres1~6#1 := 0; 37#L681-13true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 70#L682-13true activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 472#L1439-39true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 387#L1439-41true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 548#L689-39true assume 1 == ~t7_pc~0; 983#L690-13true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 488#L700-13true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 191#L701-13true activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1467#L1447-39true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 126#L1447-41true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 731#L708-39true assume !(1 == ~t8_pc~0); 486#L708-41true is_transmit8_triggered_~__retres1~8#1 := 0; 423#L719-13true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 147#L720-13true activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1177#L1455-39true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 758#L1455-41true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 353#L727-39true assume !(1 == ~t9_pc~0); 362#L727-41true is_transmit9_triggered_~__retres1~9#1 := 0; 225#L738-13true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1046#L739-13true activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1148#L1463-39true assume !(0 != activate_threads_~tmp___8~0#1); 801#L1463-41true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 960#L746-39true assume 1 == ~t10_pc~0; 775#L747-13true assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 1282#L757-13true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1151#L758-13true activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 534#L1471-39true assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 965#L1471-41true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1455#L765-39true assume !(1 == ~t11_pc~0); 283#L765-41true is_transmit11_triggered_~__retres1~11#1 := 0; 1197#L776-13true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 825#L777-13true activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 201#L1479-39true assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 712#L1479-41true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 571#L1249-3true assume 1 == ~M_E~0;~M_E~0 := 2; 107#L1249-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 1343#L1254-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 1160#L1259-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 674#L1264-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 89#L1269-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 1413#L1274-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 1241#L1279-3true assume !(1 == ~T7_E~0); 339#L1284-3true assume 1 == ~T8_E~0;~T8_E~0 := 2; 1284#L1289-3true assume 1 == ~T9_E~0;~T9_E~0 := 2; 335#L1294-3true assume 1 == ~T10_E~0;~T10_E~0 := 2; 1456#L1299-3true assume 1 == ~T11_E~0;~T11_E~0 := 2; 511#L1304-3true assume 1 == ~E_M~0;~E_M~0 := 2; 863#L1309-3true assume 1 == ~E_1~0;~E_1~0 := 2; 292#L1314-3true assume 1 == ~E_2~0;~E_2~0 := 2; 1530#L1319-3true assume !(1 == ~E_3~0); 912#L1324-3true assume 1 == ~E_4~0;~E_4~0 := 2; 138#L1329-3true assume 1 == ~E_5~0;~E_5~0 := 2; 1408#L1334-3true assume 1 == ~E_6~0;~E_6~0 := 2; 458#L1339-3true assume 1 == ~E_7~0;~E_7~0 := 2; 666#L1344-3true assume 1 == ~E_8~0;~E_8~0 := 2; 626#L1349-3true assume 1 == ~E_9~0;~E_9~0 := 2; 277#L1354-3true assume 1 == ~E_10~0;~E_10~0 := 2; 637#L1359-3true assume !(1 == ~E_11~0); 1429#L1364-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 71#L860-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 595#L922-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 408#L923-1true start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 837#L1709true assume !(0 == start_simulation_~tmp~3#1); 1294#L1709-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 938#L860-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 1524#L922-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 400#L923-2true stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 105#L1664true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 610#L1671true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1239#L1672true start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 1058#L1722true assume !(0 != start_simulation_~tmp___0~1#1); 202#L1690-2true [2021-12-16 10:05:14,696 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:14,696 INFO L85 PathProgramCache]: Analyzing trace with hash 430082112, now seen corresponding path program 1 times [2021-12-16 10:05:14,703 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:14,704 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1694341650] [2021-12-16 10:05:14,704 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:14,705 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:14,844 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:14,966 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:05:14,967 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:14,967 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1694341650] [2021-12-16 10:05:14,968 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1694341650] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:14,968 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:14,968 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:05:14,969 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1069488782] [2021-12-16 10:05:14,970 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:14,973 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:05:14,973 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:14,973 INFO L85 PathProgramCache]: Analyzing trace with hash -840324833, now seen corresponding path program 1 times [2021-12-16 10:05:14,974 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:14,974 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [937913303] [2021-12-16 10:05:14,974 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:14,974 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:14,985 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:15,006 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:05:15,006 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:15,006 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [937913303] [2021-12-16 10:05:15,007 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [937913303] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:15,007 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:15,007 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-16 10:05:15,007 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [59744563] [2021-12-16 10:05:15,022 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:15,023 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:05:15,024 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:05:15,058 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2021-12-16 10:05:15,058 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2021-12-16 10:05:15,062 INFO L87 Difference]: Start difference. First operand has 1579 states, 1578 states have (on average 1.503168567807351) internal successors, (2372), 1578 states have internal predecessors, (2372), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 2 states, 2 states have (on average 69.5) internal successors, (139), 2 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:15,121 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:05:15,121 INFO L93 Difference]: Finished difference Result 1577 states and 2340 transitions. [2021-12-16 10:05:15,124 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2021-12-16 10:05:15,131 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1577 states and 2340 transitions. [2021-12-16 10:05:15,144 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1420 [2021-12-16 10:05:15,161 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1577 states to 1571 states and 2334 transitions. [2021-12-16 10:05:15,162 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1571 [2021-12-16 10:05:15,164 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1571 [2021-12-16 10:05:15,165 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1571 states and 2334 transitions. [2021-12-16 10:05:15,173 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:05:15,173 INFO L681 BuchiCegarLoop]: Abstraction has 1571 states and 2334 transitions. [2021-12-16 10:05:15,188 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1571 states and 2334 transitions. [2021-12-16 10:05:15,246 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1571 to 1571. [2021-12-16 10:05:15,249 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1571 states, 1571 states have (on average 1.4856779121578612) internal successors, (2334), 1570 states have internal predecessors, (2334), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:15,254 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1571 states to 1571 states and 2334 transitions. [2021-12-16 10:05:15,255 INFO L704 BuchiCegarLoop]: Abstraction has 1571 states and 2334 transitions. [2021-12-16 10:05:15,256 INFO L587 BuchiCegarLoop]: Abstraction has 1571 states and 2334 transitions. [2021-12-16 10:05:15,256 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2021-12-16 10:05:15,256 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1571 states and 2334 transitions. [2021-12-16 10:05:15,262 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1420 [2021-12-16 10:05:15,263 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:05:15,263 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:05:15,268 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:15,269 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:15,270 INFO L791 eck$LassoCheckResult]: Stem: 3841#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 3842#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 4382#L1653 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4383#L785 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4252#L792 assume !(1 == ~m_i~0);~m_st~0 := 2; 4253#L792-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3260#L797-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 3261#L802-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 4699#L807-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 4226#L812-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 4227#L817-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 4504#L822-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 4505#L827-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 4588#L832-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 4670#L837-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 4671#L842-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 4552#L847-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4400#L1121 assume !(0 == ~M_E~0); 4155#L1121-2 assume !(0 == ~T1_E~0); 3536#L1126-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3537#L1131-1 assume !(0 == ~T3_E~0); 3707#L1136-1 assume !(0 == ~T4_E~0); 3803#L1141-1 assume !(0 == ~T5_E~0); 4023#L1146-1 assume !(0 == ~T6_E~0); 4323#L1151-1 assume !(0 == ~T7_E~0); 3863#L1156-1 assume !(0 == ~T8_E~0); 3246#L1161-1 assume !(0 == ~T9_E~0); 3247#L1166-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 3472#L1171-1 assume !(0 == ~T11_E~0); 3473#L1176-1 assume !(0 == ~E_M~0); 4337#L1181-1 assume !(0 == ~E_1~0); 4465#L1186-1 assume !(0 == ~E_2~0); 4515#L1191-1 assume !(0 == ~E_3~0); 3499#L1196-1 assume !(0 == ~E_4~0); 3500#L1201-1 assume !(0 == ~E_5~0); 4708#L1206-1 assume 0 == ~E_6~0;~E_6~0 := 1; 4553#L1211-1 assume !(0 == ~E_7~0); 4554#L1216-1 assume !(0 == ~E_8~0); 3642#L1221-1 assume !(0 == ~E_9~0); 3643#L1226-1 assume !(0 == ~E_10~0); 3342#L1231-1 assume !(0 == ~E_11~0); 3343#L1236-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4338#L556 assume 1 == ~m_pc~0; 4339#L557 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 3220#L567 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3221#L568 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4116#L1391 assume !(0 != activate_threads_~tmp~1#1); 4493#L1391-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4494#L575 assume !(1 == ~t1_pc~0); 3171#L575-2 is_transmit1_triggered_~__retres1~1#1 := 0; 3172#L586 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3305#L587 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3655#L1399 assume !(0 != activate_threads_~tmp___0~0#1); 3612#L1399-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3613#L594 assume 1 == ~t2_pc~0; 3541#L595 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3542#L605 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4008#L606 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3235#L1407 assume !(0 != activate_threads_~tmp___1~0#1); 3236#L1407-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3294#L613 assume !(1 == ~t3_pc~0); 3413#L613-2 is_transmit3_triggered_~__retres1~3#1 := 0; 3412#L624 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3338#L625 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3339#L1415 assume !(0 != activate_threads_~tmp___2~0#1); 4022#L1415-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3740#L632 assume 1 == ~t4_pc~0; 3741#L633 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4241#L643 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4401#L644 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4709#L1423 assume !(0 != activate_threads_~tmp___3~0#1); 4347#L1423-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4098#L651 assume 1 == ~t5_pc~0; 4099#L652 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 3426#L662 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3427#L663 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3875#L1431 assume !(0 != activate_threads_~tmp___4~0#1); 3443#L1431-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3444#L670 assume !(1 == ~t6_pc~0); 4535#L670-2 is_transmit6_triggered_~__retres1~6#1 := 0; 3789#L681 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3790#L682 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4631#L1439 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 4063#L1439-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4064#L689 assume 1 == ~t7_pc~0; 4705#L690 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 4174#L700 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4175#L701 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4550#L1447 assume !(0 != activate_threads_~tmp___6~0#1); 3966#L1447-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3967#L708 assume !(1 == ~t8_pc~0); 3532#L708-2 is_transmit8_triggered_~__retres1~8#1 := 0; 3533#L719 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4630#L720 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 4615#L1455 assume !(0 != activate_threads_~tmp___7~0#1); 3597#L1455-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3598#L727 assume 1 == ~t9_pc~0; 3720#L728 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 3296#L738 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4712#L739 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 4713#L1463 assume !(0 != activate_threads_~tmp___8~0#1); 4700#L1463-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 3651#L746 assume !(1 == ~t10_pc~0); 3652#L746-2 is_transmit10_triggered_~__retres1~10#1 := 0; 4300#L757 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 4416#L758 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 4624#L1471 assume !(0 != activate_threads_~tmp___9~0#1); 4497#L1471-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 3812#L765 assume 1 == ~t11_pc~0; 3813#L766 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 4018#L776 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 3185#L777 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 3186#L1479 assume !(0 != activate_threads_~tmp___10~0#1); 4534#L1479-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4612#L1249 assume !(1 == ~M_E~0); 4245#L1249-2 assume !(1 == ~T1_E~0); 3895#L1254-1 assume !(1 == ~T2_E~0); 3231#L1259-1 assume !(1 == ~T3_E~0); 3213#L1264-1 assume !(1 == ~T4_E~0); 3214#L1269-1 assume !(1 == ~T5_E~0); 4731#L1274-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 4679#L1279-1 assume !(1 == ~T7_E~0); 3414#L1284-1 assume !(1 == ~T8_E~0); 3415#L1289-1 assume !(1 == ~T9_E~0); 3945#L1294-1 assume !(1 == ~T10_E~0); 3946#L1299-1 assume !(1 == ~T11_E~0); 3955#L1304-1 assume !(1 == ~E_M~0); 4725#L1309-1 assume !(1 == ~E_1~0); 4728#L1314-1 assume 1 == ~E_2~0;~E_2~0 := 2; 3361#L1319-1 assume !(1 == ~E_3~0); 3362#L1324-1 assume !(1 == ~E_4~0); 3494#L1329-1 assume !(1 == ~E_5~0); 3495#L1334-1 assume !(1 == ~E_6~0); 4573#L1339-1 assume !(1 == ~E_7~0); 4650#L1344-1 assume !(1 == ~E_8~0); 4651#L1349-1 assume !(1 == ~E_9~0); 4078#L1354-1 assume 1 == ~E_10~0;~E_10~0 := 2; 4079#L1359-1 assume !(1 == ~E_11~0); 4438#L1364-1 assume { :end_inline_reset_delta_events } true; 3583#L1690-2 [2021-12-16 10:05:15,272 INFO L793 eck$LassoCheckResult]: Loop: 3583#L1690-2 assume !false; 3584#L1691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3469#L1096 assume !false; 4447#L933 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 3315#L860 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 3316#L922 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 4341#L923 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 3810#L937 assume !(0 != eval_~tmp~0#1); 3811#L1111 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4281#L785-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3785#L1121-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3786#L1121-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4701#L1126-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3993#L1131-3 assume !(0 == ~T3_E~0); 3994#L1136-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4732#L1141-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4348#L1146-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3530#L1151-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 3531#L1156-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 4645#L1161-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 4156#L1166-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 4157#L1171-3 assume !(0 == ~T11_E~0); 4202#L1176-3 assume 0 == ~E_M~0;~E_M~0 := 1; 3579#L1181-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3580#L1186-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4283#L1191-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4284#L1196-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4474#L1201-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4475#L1206-3 assume 0 == ~E_6~0;~E_6~0 := 1; 4180#L1211-3 assume !(0 == ~E_7~0); 3492#L1216-3 assume 0 == ~E_8~0;~E_8~0 := 1; 3493#L1221-3 assume 0 == ~E_9~0;~E_9~0 := 1; 3906#L1226-3 assume 0 == ~E_10~0;~E_10~0 := 1; 3549#L1231-3 assume 0 == ~E_11~0;~E_11~0 := 1; 3550#L1236-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3770#L556-39 assume 1 == ~m_pc~0; 4291#L557-13 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 4258#L567-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3649#L568-13 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3650#L1391-39 assume !(0 != activate_threads_~tmp~1#1); 3822#L1391-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4216#L575-39 assume 1 == ~t1_pc~0; 4217#L576-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4482#L586-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4343#L587-13 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4344#L1399-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4191#L1399-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4192#L594-39 assume !(1 == ~t2_pc~0); 4403#L594-41 is_transmit2_triggered_~__retres1~2#1 := 0; 4194#L605-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4195#L606-13 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4617#L1407-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3708#L1407-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3709#L613-39 assume 1 == ~t3_pc~0; 4594#L614-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3191#L624-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3192#L625-13 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3950#L1415-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3290#L1415-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3291#L632-39 assume 1 == ~t4_pc~0; 4562#L633-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3876#L643-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3877#L644-13 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4430#L1423-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4561#L1423-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3560#L651-39 assume 1 == ~t5_pc~0; 3561#L652-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 3323#L662-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4549#L663-13 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4656#L1431-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 4694#L1431-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4714#L670-39 assume !(1 == ~t6_pc~0); 4293#L670-41 is_transmit6_triggered_~__retres1~6#1 := 0; 3237#L681-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3238#L682-13 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3306#L1439-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 3903#L1439-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3904#L689-39 assume !(1 == ~t7_pc~0); 4027#L689-41 is_transmit7_triggered_~__retres1~7#1 := 0; 4028#L700-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3562#L701-13 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3563#L1447-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 3430#L1447-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3431#L708-39 assume 1 == ~t8_pc~0; 3367#L709-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 3368#L719-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3476#L720-13 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 3477#L1455-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 4357#L1455-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3849#L727-39 assume !(1 == ~t9_pc~0); 3850#L727-41 is_transmit9_triggered_~__retres1~9#1 := 0; 3627#L738-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3628#L739-13 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 4577#L1463-39 assume !(0 != activate_threads_~tmp___8~0#1); 4406#L1463-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4407#L746-39 assume 1 == ~t10_pc~0; 4376#L747-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 4377#L757-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 4642#L758-13 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 4112#L1471-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 4113#L1471-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 4525#L765-39 assume 1 == ~t11_pc~0; 3241#L766-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 3243#L776-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 4425#L777-13 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 3581#L1479-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 3582#L1479-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4149#L1249-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3387#L1249-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3388#L1254-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4644#L1259-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4272#L1264-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3346#L1269-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3347#L1274-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 4677#L1279-3 assume !(1 == ~T7_E~0); 3825#L1284-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 3826#L1289-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 3820#L1294-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 3821#L1299-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 4072#L1304-3 assume 1 == ~E_M~0;~E_M~0 := 2; 4073#L1309-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3737#L1314-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3738#L1319-3 assume !(1 == ~E_3~0); 4491#L1324-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3456#L1329-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3457#L1334-3 assume 1 == ~E_6~0;~E_6~0 := 2; 4006#L1339-3 assume 1 == ~E_7~0;~E_7~0 := 2; 4007#L1344-3 assume 1 == ~E_8~0;~E_8~0 := 2; 4225#L1349-3 assume 1 == ~E_9~0;~E_9~0 := 2; 3716#L1354-3 assume 1 == ~E_10~0;~E_10~0 := 2; 3717#L1359-3 assume !(1 == ~E_11~0); 4240#L1364-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 3307#L860-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 3308#L922-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 3934#L923-1 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 3935#L1709 assume !(0 == start_simulation_~tmp~3#1); 3745#L1709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 4511#L860-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 3421#L922-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 3923#L923-2 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 3384#L1664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3385#L1671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4203#L1672 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 4584#L1722 assume !(0 != start_simulation_~tmp___0~1#1); 3583#L1690-2 [2021-12-16 10:05:15,274 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:15,275 INFO L85 PathProgramCache]: Analyzing trace with hash 430082112, now seen corresponding path program 2 times [2021-12-16 10:05:15,275 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:15,276 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1909586518] [2021-12-16 10:05:15,276 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:15,276 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:15,342 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:15,400 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:05:15,401 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:15,403 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1909586518] [2021-12-16 10:05:15,404 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1909586518] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:15,404 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:15,404 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:05:15,404 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [436766215] [2021-12-16 10:05:15,404 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:15,405 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:05:15,405 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:15,405 INFO L85 PathProgramCache]: Analyzing trace with hash -1946660288, now seen corresponding path program 1 times [2021-12-16 10:05:15,406 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:15,408 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [181759467] [2021-12-16 10:05:15,408 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:15,409 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:15,442 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:15,534 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:05:15,537 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:15,537 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [181759467] [2021-12-16 10:05:15,537 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [181759467] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:15,537 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:15,538 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:05:15,538 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [281810590] [2021-12-16 10:05:15,538 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:15,539 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:05:15,539 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:05:15,540 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-16 10:05:15,541 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-16 10:05:15,541 INFO L87 Difference]: Start difference. First operand 1571 states and 2334 transitions. cyclomatic complexity: 764 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:15,574 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:05:15,574 INFO L93 Difference]: Finished difference Result 1571 states and 2333 transitions. [2021-12-16 10:05:15,575 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-16 10:05:15,575 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1571 states and 2333 transitions. [2021-12-16 10:05:15,583 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1420 [2021-12-16 10:05:15,588 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1571 states to 1571 states and 2333 transitions. [2021-12-16 10:05:15,589 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1571 [2021-12-16 10:05:15,591 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1571 [2021-12-16 10:05:15,591 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1571 states and 2333 transitions. [2021-12-16 10:05:15,593 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:05:15,593 INFO L681 BuchiCegarLoop]: Abstraction has 1571 states and 2333 transitions. [2021-12-16 10:05:15,595 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1571 states and 2333 transitions. [2021-12-16 10:05:15,607 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1571 to 1571. [2021-12-16 10:05:15,609 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1571 states, 1571 states have (on average 1.4850413749204328) internal successors, (2333), 1570 states have internal predecessors, (2333), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:15,613 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1571 states to 1571 states and 2333 transitions. [2021-12-16 10:05:15,613 INFO L704 BuchiCegarLoop]: Abstraction has 1571 states and 2333 transitions. [2021-12-16 10:05:15,613 INFO L587 BuchiCegarLoop]: Abstraction has 1571 states and 2333 transitions. [2021-12-16 10:05:15,613 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2021-12-16 10:05:15,613 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1571 states and 2333 transitions. [2021-12-16 10:05:15,618 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1420 [2021-12-16 10:05:15,618 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:05:15,618 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:05:15,619 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:15,620 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:15,620 INFO L791 eck$LassoCheckResult]: Stem: 6990#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 6991#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 7531#L1653 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7532#L785 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7401#L792 assume 1 == ~m_i~0;~m_st~0 := 0; 7402#L792-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6409#L797-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 6410#L802-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 7848#L807-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 7375#L812-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 7376#L817-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 7653#L822-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 7654#L827-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 7737#L832-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 7819#L837-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 7820#L842-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 7701#L847-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7549#L1121 assume !(0 == ~M_E~0); 7304#L1121-2 assume !(0 == ~T1_E~0); 6685#L1126-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 6686#L1131-1 assume !(0 == ~T3_E~0); 6856#L1136-1 assume !(0 == ~T4_E~0); 6952#L1141-1 assume !(0 == ~T5_E~0); 7172#L1146-1 assume !(0 == ~T6_E~0); 7472#L1151-1 assume !(0 == ~T7_E~0); 7012#L1156-1 assume !(0 == ~T8_E~0); 6395#L1161-1 assume !(0 == ~T9_E~0); 6396#L1166-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 6621#L1171-1 assume !(0 == ~T11_E~0); 6622#L1176-1 assume !(0 == ~E_M~0); 7486#L1181-1 assume !(0 == ~E_1~0); 7614#L1186-1 assume !(0 == ~E_2~0); 7664#L1191-1 assume !(0 == ~E_3~0); 6648#L1196-1 assume !(0 == ~E_4~0); 6649#L1201-1 assume !(0 == ~E_5~0); 7857#L1206-1 assume 0 == ~E_6~0;~E_6~0 := 1; 7702#L1211-1 assume !(0 == ~E_7~0); 7703#L1216-1 assume !(0 == ~E_8~0); 6791#L1221-1 assume !(0 == ~E_9~0); 6792#L1226-1 assume !(0 == ~E_10~0); 6491#L1231-1 assume !(0 == ~E_11~0); 6492#L1236-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7487#L556 assume 1 == ~m_pc~0; 7488#L557 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 6369#L567 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6370#L568 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7265#L1391 assume !(0 != activate_threads_~tmp~1#1); 7642#L1391-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7643#L575 assume !(1 == ~t1_pc~0); 6320#L575-2 is_transmit1_triggered_~__retres1~1#1 := 0; 6321#L586 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6454#L587 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 6804#L1399 assume !(0 != activate_threads_~tmp___0~0#1); 6761#L1399-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6762#L594 assume 1 == ~t2_pc~0; 6690#L595 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 6691#L605 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7157#L606 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 6384#L1407 assume !(0 != activate_threads_~tmp___1~0#1); 6385#L1407-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6443#L613 assume !(1 == ~t3_pc~0); 6562#L613-2 is_transmit3_triggered_~__retres1~3#1 := 0; 6561#L624 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6487#L625 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 6488#L1415 assume !(0 != activate_threads_~tmp___2~0#1); 7171#L1415-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6889#L632 assume 1 == ~t4_pc~0; 6890#L633 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 7390#L643 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7550#L644 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 7858#L1423 assume !(0 != activate_threads_~tmp___3~0#1); 7496#L1423-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7247#L651 assume 1 == ~t5_pc~0; 7248#L652 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 6575#L662 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6576#L663 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 7024#L1431 assume !(0 != activate_threads_~tmp___4~0#1); 6592#L1431-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6593#L670 assume !(1 == ~t6_pc~0); 7684#L670-2 is_transmit6_triggered_~__retres1~6#1 := 0; 6938#L681 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6939#L682 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 7780#L1439 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 7212#L1439-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 7213#L689 assume 1 == ~t7_pc~0; 7854#L690 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 7323#L700 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 7324#L701 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 7699#L1447 assume !(0 != activate_threads_~tmp___6~0#1); 7115#L1447-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 7116#L708 assume !(1 == ~t8_pc~0); 6681#L708-2 is_transmit8_triggered_~__retres1~8#1 := 0; 6682#L719 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 7779#L720 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 7764#L1455 assume !(0 != activate_threads_~tmp___7~0#1); 6746#L1455-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 6747#L727 assume 1 == ~t9_pc~0; 6869#L728 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 6445#L738 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 7861#L739 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 7862#L1463 assume !(0 != activate_threads_~tmp___8~0#1); 7849#L1463-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 6800#L746 assume !(1 == ~t10_pc~0); 6801#L746-2 is_transmit10_triggered_~__retres1~10#1 := 0; 7449#L757 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 7565#L758 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 7773#L1471 assume !(0 != activate_threads_~tmp___9~0#1); 7646#L1471-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 6961#L765 assume 1 == ~t11_pc~0; 6962#L766 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 7167#L776 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 6334#L777 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 6335#L1479 assume !(0 != activate_threads_~tmp___10~0#1); 7683#L1479-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7761#L1249 assume !(1 == ~M_E~0); 7394#L1249-2 assume !(1 == ~T1_E~0); 7044#L1254-1 assume !(1 == ~T2_E~0); 6380#L1259-1 assume !(1 == ~T3_E~0); 6362#L1264-1 assume !(1 == ~T4_E~0); 6363#L1269-1 assume !(1 == ~T5_E~0); 7880#L1274-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 7828#L1279-1 assume !(1 == ~T7_E~0); 6563#L1284-1 assume !(1 == ~T8_E~0); 6564#L1289-1 assume !(1 == ~T9_E~0); 7094#L1294-1 assume !(1 == ~T10_E~0); 7095#L1299-1 assume !(1 == ~T11_E~0); 7104#L1304-1 assume !(1 == ~E_M~0); 7874#L1309-1 assume !(1 == ~E_1~0); 7877#L1314-1 assume 1 == ~E_2~0;~E_2~0 := 2; 6510#L1319-1 assume !(1 == ~E_3~0); 6511#L1324-1 assume !(1 == ~E_4~0); 6643#L1329-1 assume !(1 == ~E_5~0); 6644#L1334-1 assume !(1 == ~E_6~0); 7722#L1339-1 assume !(1 == ~E_7~0); 7799#L1344-1 assume !(1 == ~E_8~0); 7800#L1349-1 assume !(1 == ~E_9~0); 7227#L1354-1 assume 1 == ~E_10~0;~E_10~0 := 2; 7228#L1359-1 assume !(1 == ~E_11~0); 7587#L1364-1 assume { :end_inline_reset_delta_events } true; 6732#L1690-2 [2021-12-16 10:05:15,620 INFO L793 eck$LassoCheckResult]: Loop: 6732#L1690-2 assume !false; 6733#L1691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 6618#L1096 assume !false; 7596#L933 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 6464#L860 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 6465#L922 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 7490#L923 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 6959#L937 assume !(0 != eval_~tmp~0#1); 6960#L1111 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 7430#L785-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 6934#L1121-3 assume 0 == ~M_E~0;~M_E~0 := 1; 6935#L1121-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 7850#L1126-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7142#L1131-3 assume !(0 == ~T3_E~0); 7143#L1136-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 7881#L1141-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 7497#L1146-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 6679#L1151-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 6680#L1156-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 7794#L1161-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 7305#L1166-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 7306#L1171-3 assume !(0 == ~T11_E~0); 7351#L1176-3 assume 0 == ~E_M~0;~E_M~0 := 1; 6728#L1181-3 assume 0 == ~E_1~0;~E_1~0 := 1; 6729#L1186-3 assume 0 == ~E_2~0;~E_2~0 := 1; 7432#L1191-3 assume 0 == ~E_3~0;~E_3~0 := 1; 7433#L1196-3 assume 0 == ~E_4~0;~E_4~0 := 1; 7623#L1201-3 assume 0 == ~E_5~0;~E_5~0 := 1; 7624#L1206-3 assume 0 == ~E_6~0;~E_6~0 := 1; 7329#L1211-3 assume !(0 == ~E_7~0); 6641#L1216-3 assume 0 == ~E_8~0;~E_8~0 := 1; 6642#L1221-3 assume 0 == ~E_9~0;~E_9~0 := 1; 7055#L1226-3 assume 0 == ~E_10~0;~E_10~0 := 1; 6698#L1231-3 assume 0 == ~E_11~0;~E_11~0 := 1; 6699#L1236-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6919#L556-39 assume 1 == ~m_pc~0; 7440#L557-13 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 7407#L567-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6798#L568-13 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 6799#L1391-39 assume !(0 != activate_threads_~tmp~1#1); 6971#L1391-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7365#L575-39 assume 1 == ~t1_pc~0; 7366#L576-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 7631#L586-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7492#L587-13 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7493#L1399-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7340#L1399-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7341#L594-39 assume !(1 == ~t2_pc~0); 7552#L594-41 is_transmit2_triggered_~__retres1~2#1 := 0; 7343#L605-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7344#L606-13 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 7766#L1407-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 6857#L1407-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6858#L613-39 assume !(1 == ~t3_pc~0); 7744#L613-41 is_transmit3_triggered_~__retres1~3#1 := 0; 6340#L624-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6341#L625-13 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 7099#L1415-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 6439#L1415-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6440#L632-39 assume !(1 == ~t4_pc~0); 7588#L632-41 is_transmit4_triggered_~__retres1~4#1 := 0; 7025#L643-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7026#L644-13 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 7579#L1423-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 7710#L1423-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6709#L651-39 assume 1 == ~t5_pc~0; 6710#L652-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 6472#L662-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7698#L663-13 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 7805#L1431-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 7843#L1431-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7863#L670-39 assume !(1 == ~t6_pc~0); 7442#L670-41 is_transmit6_triggered_~__retres1~6#1 := 0; 6386#L681-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6387#L682-13 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 6455#L1439-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 7052#L1439-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 7053#L689-39 assume !(1 == ~t7_pc~0); 7176#L689-41 is_transmit7_triggered_~__retres1~7#1 := 0; 7177#L700-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 6711#L701-13 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 6712#L1447-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 6579#L1447-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 6580#L708-39 assume 1 == ~t8_pc~0; 6516#L709-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 6517#L719-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 6625#L720-13 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 6626#L1455-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 7506#L1455-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 6998#L727-39 assume !(1 == ~t9_pc~0); 6999#L727-41 is_transmit9_triggered_~__retres1~9#1 := 0; 6776#L738-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 6777#L739-13 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 7726#L1463-39 assume !(0 != activate_threads_~tmp___8~0#1); 7555#L1463-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 7556#L746-39 assume 1 == ~t10_pc~0; 7525#L747-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 7526#L757-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 7791#L758-13 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 7261#L1471-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 7262#L1471-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 7674#L765-39 assume 1 == ~t11_pc~0; 6390#L766-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 6392#L776-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 7574#L777-13 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 6730#L1479-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 6731#L1479-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7298#L1249-3 assume 1 == ~M_E~0;~M_E~0 := 2; 6536#L1249-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 6537#L1254-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7793#L1259-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7421#L1264-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 6495#L1269-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 6496#L1274-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 7826#L1279-3 assume !(1 == ~T7_E~0); 6974#L1284-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 6975#L1289-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 6969#L1294-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 6970#L1299-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 7221#L1304-3 assume 1 == ~E_M~0;~E_M~0 := 2; 7222#L1309-3 assume 1 == ~E_1~0;~E_1~0 := 2; 6886#L1314-3 assume 1 == ~E_2~0;~E_2~0 := 2; 6887#L1319-3 assume !(1 == ~E_3~0); 7640#L1324-3 assume 1 == ~E_4~0;~E_4~0 := 2; 6605#L1329-3 assume 1 == ~E_5~0;~E_5~0 := 2; 6606#L1334-3 assume 1 == ~E_6~0;~E_6~0 := 2; 7155#L1339-3 assume 1 == ~E_7~0;~E_7~0 := 2; 7156#L1344-3 assume 1 == ~E_8~0;~E_8~0 := 2; 7374#L1349-3 assume 1 == ~E_9~0;~E_9~0 := 2; 6865#L1354-3 assume 1 == ~E_10~0;~E_10~0 := 2; 6866#L1359-3 assume !(1 == ~E_11~0); 7389#L1364-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 6456#L860-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 6457#L922-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 7083#L923-1 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 7084#L1709 assume !(0 == start_simulation_~tmp~3#1); 6894#L1709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 7660#L860-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 6570#L922-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 7072#L923-2 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 6533#L1664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 6534#L1671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 7352#L1672 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 7733#L1722 assume !(0 != start_simulation_~tmp___0~1#1); 6732#L1690-2 [2021-12-16 10:05:15,629 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:15,629 INFO L85 PathProgramCache]: Analyzing trace with hash -968871490, now seen corresponding path program 1 times [2021-12-16 10:05:15,629 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:15,630 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1274403783] [2021-12-16 10:05:15,630 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:15,630 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:15,660 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:15,681 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:05:15,682 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:15,682 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1274403783] [2021-12-16 10:05:15,682 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1274403783] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:15,682 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:15,682 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:05:15,682 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [266473102] [2021-12-16 10:05:15,683 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:15,683 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:05:15,683 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:15,683 INFO L85 PathProgramCache]: Analyzing trace with hash -29726974, now seen corresponding path program 1 times [2021-12-16 10:05:15,684 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:15,684 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1344847143] [2021-12-16 10:05:15,684 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:15,684 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:15,709 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:15,750 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:05:15,750 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:15,750 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1344847143] [2021-12-16 10:05:15,751 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1344847143] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:15,751 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:15,751 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:05:15,751 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1739541558] [2021-12-16 10:05:15,751 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:15,752 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:05:15,752 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:05:15,752 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-16 10:05:15,753 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-16 10:05:15,753 INFO L87 Difference]: Start difference. First operand 1571 states and 2333 transitions. cyclomatic complexity: 763 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:15,816 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:05:15,816 INFO L93 Difference]: Finished difference Result 1571 states and 2332 transitions. [2021-12-16 10:05:15,817 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-16 10:05:15,818 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1571 states and 2332 transitions. [2021-12-16 10:05:15,824 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1420 [2021-12-16 10:05:15,830 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1571 states to 1571 states and 2332 transitions. [2021-12-16 10:05:15,830 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1571 [2021-12-16 10:05:15,831 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1571 [2021-12-16 10:05:15,847 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1571 states and 2332 transitions. [2021-12-16 10:05:15,849 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:05:15,849 INFO L681 BuchiCegarLoop]: Abstraction has 1571 states and 2332 transitions. [2021-12-16 10:05:15,851 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1571 states and 2332 transitions. [2021-12-16 10:05:15,885 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1571 to 1571. [2021-12-16 10:05:15,887 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1571 states, 1571 states have (on average 1.4844048376830044) internal successors, (2332), 1570 states have internal predecessors, (2332), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:15,890 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1571 states to 1571 states and 2332 transitions. [2021-12-16 10:05:15,903 INFO L704 BuchiCegarLoop]: Abstraction has 1571 states and 2332 transitions. [2021-12-16 10:05:15,903 INFO L587 BuchiCegarLoop]: Abstraction has 1571 states and 2332 transitions. [2021-12-16 10:05:15,903 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2021-12-16 10:05:15,904 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1571 states and 2332 transitions. [2021-12-16 10:05:15,908 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1420 [2021-12-16 10:05:15,908 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:05:15,908 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:05:15,910 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:15,910 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:15,910 INFO L791 eck$LassoCheckResult]: Stem: 10143#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 10144#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 10680#L1653 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 10681#L785 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 10550#L792 assume 1 == ~m_i~0;~m_st~0 := 0; 10551#L792-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9558#L797-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 9559#L802-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 10997#L807-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 10524#L812-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 10525#L817-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 10802#L822-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 10803#L827-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 10886#L832-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 10968#L837-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 10969#L842-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 10850#L847-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10698#L1121 assume !(0 == ~M_E~0); 10453#L1121-2 assume !(0 == ~T1_E~0); 9835#L1126-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 9836#L1131-1 assume !(0 == ~T3_E~0); 10005#L1136-1 assume !(0 == ~T4_E~0); 10101#L1141-1 assume !(0 == ~T5_E~0); 10326#L1146-1 assume !(0 == ~T6_E~0); 10621#L1151-1 assume !(0 == ~T7_E~0); 10161#L1156-1 assume !(0 == ~T8_E~0); 9544#L1161-1 assume !(0 == ~T9_E~0); 9545#L1166-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 9770#L1171-1 assume !(0 == ~T11_E~0); 9771#L1176-1 assume !(0 == ~E_M~0); 10635#L1181-1 assume !(0 == ~E_1~0); 10763#L1186-1 assume !(0 == ~E_2~0); 10813#L1191-1 assume !(0 == ~E_3~0); 9797#L1196-1 assume !(0 == ~E_4~0); 9798#L1201-1 assume !(0 == ~E_5~0); 11006#L1206-1 assume 0 == ~E_6~0;~E_6~0 := 1; 10851#L1211-1 assume !(0 == ~E_7~0); 10852#L1216-1 assume !(0 == ~E_8~0); 9943#L1221-1 assume !(0 == ~E_9~0); 9944#L1226-1 assume !(0 == ~E_10~0); 9640#L1231-1 assume !(0 == ~E_11~0); 9641#L1236-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10637#L556 assume 1 == ~m_pc~0; 10638#L557 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 9518#L567 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9519#L568 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10415#L1391 assume !(0 != activate_threads_~tmp~1#1); 10791#L1391-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10792#L575 assume !(1 == ~t1_pc~0); 9469#L575-2 is_transmit1_triggered_~__retres1~1#1 := 0; 9470#L586 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9603#L587 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 9953#L1399 assume !(0 != activate_threads_~tmp___0~0#1); 9910#L1399-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9911#L594 assume 1 == ~t2_pc~0; 9839#L595 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 9840#L605 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10306#L606 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 9535#L1407 assume !(0 != activate_threads_~tmp___1~0#1); 9536#L1407-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9592#L613 assume !(1 == ~t3_pc~0); 9711#L613-2 is_transmit3_triggered_~__retres1~3#1 := 0; 9710#L624 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9636#L625 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9637#L1415 assume !(0 != activate_threads_~tmp___2~0#1); 10320#L1415-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10038#L632 assume 1 == ~t4_pc~0; 10039#L633 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 10539#L643 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10699#L644 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 11007#L1423 assume !(0 != activate_threads_~tmp___3~0#1); 10645#L1423-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10396#L651 assume 1 == ~t5_pc~0; 10397#L652 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 9724#L662 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9725#L663 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 10173#L1431 assume !(0 != activate_threads_~tmp___4~0#1); 9741#L1431-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9742#L670 assume !(1 == ~t6_pc~0); 10834#L670-2 is_transmit6_triggered_~__retres1~6#1 := 0; 10092#L681 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 10093#L682 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 10930#L1439 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 10363#L1439-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 10364#L689 assume 1 == ~t7_pc~0; 11003#L690 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 10472#L700 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10473#L701 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 10848#L1447 assume !(0 != activate_threads_~tmp___6~0#1); 10264#L1447-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 10265#L708 assume !(1 == ~t8_pc~0); 9830#L708-2 is_transmit8_triggered_~__retres1~8#1 := 0; 9831#L719 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 10928#L720 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 10913#L1455 assume !(0 != activate_threads_~tmp___7~0#1); 9895#L1455-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 9896#L727 assume 1 == ~t9_pc~0; 10018#L728 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 9594#L738 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 11010#L739 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 11011#L1463 assume !(0 != activate_threads_~tmp___8~0#1); 10998#L1463-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 9950#L746 assume !(1 == ~t10_pc~0); 9951#L746-2 is_transmit10_triggered_~__retres1~10#1 := 0; 10598#L757 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 10714#L758 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 10922#L1471 assume !(0 != activate_threads_~tmp___9~0#1); 10795#L1471-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 10113#L765 assume 1 == ~t11_pc~0; 10114#L766 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 10316#L776 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 9483#L777 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 9484#L1479 assume !(0 != activate_threads_~tmp___10~0#1); 10832#L1479-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10910#L1249 assume !(1 == ~M_E~0); 10544#L1249-2 assume !(1 == ~T1_E~0); 10193#L1254-1 assume !(1 == ~T2_E~0); 9529#L1259-1 assume !(1 == ~T3_E~0); 9511#L1264-1 assume !(1 == ~T4_E~0); 9512#L1269-1 assume !(1 == ~T5_E~0); 11029#L1274-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 10977#L1279-1 assume !(1 == ~T7_E~0); 9712#L1284-1 assume !(1 == ~T8_E~0); 9713#L1289-1 assume !(1 == ~T9_E~0); 10243#L1294-1 assume !(1 == ~T10_E~0); 10244#L1299-1 assume !(1 == ~T11_E~0); 10253#L1304-1 assume !(1 == ~E_M~0); 11023#L1309-1 assume !(1 == ~E_1~0); 11026#L1314-1 assume 1 == ~E_2~0;~E_2~0 := 2; 9659#L1319-1 assume !(1 == ~E_3~0); 9660#L1324-1 assume !(1 == ~E_4~0); 9792#L1329-1 assume !(1 == ~E_5~0); 9793#L1334-1 assume !(1 == ~E_6~0); 10871#L1339-1 assume !(1 == ~E_7~0); 10948#L1344-1 assume !(1 == ~E_8~0); 10949#L1349-1 assume !(1 == ~E_9~0); 10376#L1354-1 assume 1 == ~E_10~0;~E_10~0 := 2; 10377#L1359-1 assume !(1 == ~E_11~0); 10736#L1364-1 assume { :end_inline_reset_delta_events } true; 9881#L1690-2 [2021-12-16 10:05:15,910 INFO L793 eck$LassoCheckResult]: Loop: 9881#L1690-2 assume !false; 9882#L1691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 9767#L1096 assume !false; 10745#L933 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 9613#L860 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 9614#L922 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 10640#L923 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 10108#L937 assume !(0 != eval_~tmp~0#1); 10109#L1111 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 10579#L785-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 10085#L1121-3 assume 0 == ~M_E~0;~M_E~0 := 1; 10086#L1121-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 10999#L1126-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 10291#L1131-3 assume !(0 == ~T3_E~0); 10292#L1136-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 11030#L1141-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 10646#L1146-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 9828#L1151-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 9829#L1156-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 10943#L1161-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 10454#L1166-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 10455#L1171-3 assume !(0 == ~T11_E~0); 10500#L1176-3 assume 0 == ~E_M~0;~E_M~0 := 1; 9877#L1181-3 assume 0 == ~E_1~0;~E_1~0 := 1; 9878#L1186-3 assume 0 == ~E_2~0;~E_2~0 := 1; 10581#L1191-3 assume 0 == ~E_3~0;~E_3~0 := 1; 10582#L1196-3 assume 0 == ~E_4~0;~E_4~0 := 1; 10772#L1201-3 assume 0 == ~E_5~0;~E_5~0 := 1; 10773#L1206-3 assume 0 == ~E_6~0;~E_6~0 := 1; 10478#L1211-3 assume !(0 == ~E_7~0); 9790#L1216-3 assume 0 == ~E_8~0;~E_8~0 := 1; 9791#L1221-3 assume 0 == ~E_9~0;~E_9~0 := 1; 10204#L1226-3 assume 0 == ~E_10~0;~E_10~0 := 1; 9847#L1231-3 assume 0 == ~E_11~0;~E_11~0 := 1; 9848#L1236-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10068#L556-39 assume 1 == ~m_pc~0; 10589#L557-13 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 10556#L567-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9947#L568-13 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 9948#L1391-39 assume !(0 != activate_threads_~tmp~1#1); 10120#L1391-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10514#L575-39 assume 1 == ~t1_pc~0; 10515#L576-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 10780#L586-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10641#L587-13 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 10642#L1399-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 10489#L1399-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10490#L594-39 assume !(1 == ~t2_pc~0); 10701#L594-41 is_transmit2_triggered_~__retres1~2#1 := 0; 10492#L605-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10493#L606-13 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 10915#L1407-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 10006#L1407-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10007#L613-39 assume 1 == ~t3_pc~0; 10892#L614-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 9489#L624-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9490#L625-13 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 10248#L1415-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9588#L1415-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9589#L632-39 assume !(1 == ~t4_pc~0); 10737#L632-41 is_transmit4_triggered_~__retres1~4#1 := 0; 10174#L643-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10175#L644-13 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 10728#L1423-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 10859#L1423-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9858#L651-39 assume 1 == ~t5_pc~0; 9859#L652-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 9621#L662-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10847#L663-13 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 10954#L1431-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 10992#L1431-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11012#L670-39 assume 1 == ~t6_pc~0; 11013#L671-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 9533#L681-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9534#L682-13 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 9604#L1439-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 10201#L1439-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 10202#L689-39 assume !(1 == ~t7_pc~0); 10324#L689-41 is_transmit7_triggered_~__retres1~7#1 := 0; 10325#L700-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 9860#L701-13 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 9861#L1447-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 9728#L1447-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 9729#L708-39 assume 1 == ~t8_pc~0; 9665#L709-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 9666#L719-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 9772#L720-13 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 9773#L1455-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 10655#L1455-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 10147#L727-39 assume !(1 == ~t9_pc~0); 10148#L727-41 is_transmit9_triggered_~__retres1~9#1 := 0; 9925#L738-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 9926#L739-13 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 10875#L1463-39 assume !(0 != activate_threads_~tmp___8~0#1); 10704#L1463-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 10705#L746-39 assume 1 == ~t10_pc~0; 10674#L747-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 10675#L757-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 10940#L758-13 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 10410#L1471-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 10411#L1471-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 10823#L765-39 assume 1 == ~t11_pc~0; 9539#L766-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 9541#L776-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 10723#L777-13 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 9879#L1479-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 9880#L1479-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10447#L1249-3 assume 1 == ~M_E~0;~M_E~0 := 2; 9685#L1249-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9686#L1254-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 10942#L1259-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 10570#L1264-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 9644#L1269-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 9645#L1274-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 10975#L1279-3 assume !(1 == ~T7_E~0); 10123#L1284-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 10124#L1289-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 10118#L1294-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 10119#L1299-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 10370#L1304-3 assume 1 == ~E_M~0;~E_M~0 := 2; 10371#L1309-3 assume 1 == ~E_1~0;~E_1~0 := 2; 10032#L1314-3 assume 1 == ~E_2~0;~E_2~0 := 2; 10033#L1319-3 assume !(1 == ~E_3~0); 10789#L1324-3 assume 1 == ~E_4~0;~E_4~0 := 2; 9751#L1329-3 assume 1 == ~E_5~0;~E_5~0 := 2; 9752#L1334-3 assume 1 == ~E_6~0;~E_6~0 := 2; 10304#L1339-3 assume 1 == ~E_7~0;~E_7~0 := 2; 10305#L1344-3 assume 1 == ~E_8~0;~E_8~0 := 2; 10523#L1349-3 assume 1 == ~E_9~0;~E_9~0 := 2; 10014#L1354-3 assume 1 == ~E_10~0;~E_10~0 := 2; 10015#L1359-3 assume !(1 == ~E_11~0); 10538#L1364-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 9605#L860-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 9606#L922-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 10232#L923-1 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 10233#L1709 assume !(0 == start_simulation_~tmp~3#1); 10043#L1709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 10809#L860-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 9719#L922-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 10221#L923-2 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 9682#L1664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 9683#L1671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 10501#L1672 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 10882#L1722 assume !(0 != start_simulation_~tmp___0~1#1); 9881#L1690-2 [2021-12-16 10:05:15,911 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:15,911 INFO L85 PathProgramCache]: Analyzing trace with hash -1332337988, now seen corresponding path program 1 times [2021-12-16 10:05:15,911 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:15,911 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1765289642] [2021-12-16 10:05:15,912 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:15,912 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:15,935 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:15,948 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:05:15,949 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:15,949 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1765289642] [2021-12-16 10:05:15,949 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1765289642] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:15,949 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:15,949 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:05:15,949 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [912493477] [2021-12-16 10:05:15,950 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:15,950 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:05:15,950 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:15,950 INFO L85 PathProgramCache]: Analyzing trace with hash -1000867648, now seen corresponding path program 1 times [2021-12-16 10:05:15,951 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:15,951 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1298675489] [2021-12-16 10:05:15,951 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:15,951 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:15,960 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:15,978 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:05:15,979 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:15,979 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1298675489] [2021-12-16 10:05:15,979 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1298675489] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:15,979 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:15,979 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:05:15,979 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [376044261] [2021-12-16 10:05:15,979 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:15,980 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:05:15,980 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:05:15,980 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-16 10:05:15,980 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-16 10:05:15,981 INFO L87 Difference]: Start difference. First operand 1571 states and 2332 transitions. cyclomatic complexity: 762 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:16,000 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:05:16,000 INFO L93 Difference]: Finished difference Result 1571 states and 2331 transitions. [2021-12-16 10:05:16,001 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-16 10:05:16,001 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1571 states and 2331 transitions. [2021-12-16 10:05:16,007 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1420 [2021-12-16 10:05:16,012 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1571 states to 1571 states and 2331 transitions. [2021-12-16 10:05:16,012 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1571 [2021-12-16 10:05:16,013 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1571 [2021-12-16 10:05:16,013 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1571 states and 2331 transitions. [2021-12-16 10:05:16,014 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:05:16,014 INFO L681 BuchiCegarLoop]: Abstraction has 1571 states and 2331 transitions. [2021-12-16 10:05:16,016 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1571 states and 2331 transitions. [2021-12-16 10:05:16,025 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1571 to 1571. [2021-12-16 10:05:16,027 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1571 states, 1571 states have (on average 1.4837683004455762) internal successors, (2331), 1570 states have internal predecessors, (2331), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:16,030 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1571 states to 1571 states and 2331 transitions. [2021-12-16 10:05:16,030 INFO L704 BuchiCegarLoop]: Abstraction has 1571 states and 2331 transitions. [2021-12-16 10:05:16,030 INFO L587 BuchiCegarLoop]: Abstraction has 1571 states and 2331 transitions. [2021-12-16 10:05:16,030 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2021-12-16 10:05:16,031 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1571 states and 2331 transitions. [2021-12-16 10:05:16,035 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1420 [2021-12-16 10:05:16,035 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:05:16,035 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:05:16,036 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:16,036 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:16,036 INFO L791 eck$LassoCheckResult]: Stem: 13290#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 13291#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 13829#L1653 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 13830#L785 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 13699#L792 assume 1 == ~m_i~0;~m_st~0 := 0; 13700#L792-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12707#L797-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12708#L802-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 14146#L807-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 13673#L812-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 13674#L817-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 13951#L822-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 13952#L827-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 14035#L832-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 14117#L837-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 14118#L842-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 13999#L847-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 13847#L1121 assume !(0 == ~M_E~0); 13602#L1121-2 assume !(0 == ~T1_E~0); 12984#L1126-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 12985#L1131-1 assume !(0 == ~T3_E~0); 13154#L1136-1 assume !(0 == ~T4_E~0); 13250#L1141-1 assume !(0 == ~T5_E~0); 13470#L1146-1 assume !(0 == ~T6_E~0); 13770#L1151-1 assume !(0 == ~T7_E~0); 13310#L1156-1 assume !(0 == ~T8_E~0); 12693#L1161-1 assume !(0 == ~T9_E~0); 12694#L1166-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 12919#L1171-1 assume !(0 == ~T11_E~0); 12920#L1176-1 assume !(0 == ~E_M~0); 13784#L1181-1 assume !(0 == ~E_1~0); 13912#L1186-1 assume !(0 == ~E_2~0); 13962#L1191-1 assume !(0 == ~E_3~0); 12946#L1196-1 assume !(0 == ~E_4~0); 12947#L1201-1 assume !(0 == ~E_5~0); 14155#L1206-1 assume 0 == ~E_6~0;~E_6~0 := 1; 14000#L1211-1 assume !(0 == ~E_7~0); 14001#L1216-1 assume !(0 == ~E_8~0); 13089#L1221-1 assume !(0 == ~E_9~0); 13090#L1226-1 assume !(0 == ~E_10~0); 12789#L1231-1 assume !(0 == ~E_11~0); 12790#L1236-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13785#L556 assume 1 == ~m_pc~0; 13786#L557 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 12667#L567 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12668#L568 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 13564#L1391 assume !(0 != activate_threads_~tmp~1#1); 13940#L1391-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13941#L575 assume !(1 == ~t1_pc~0); 12618#L575-2 is_transmit1_triggered_~__retres1~1#1 := 0; 12619#L586 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12752#L587 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 13102#L1399 assume !(0 != activate_threads_~tmp___0~0#1); 13059#L1399-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13060#L594 assume 1 == ~t2_pc~0; 12988#L595 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 12989#L605 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13455#L606 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12682#L1407 assume !(0 != activate_threads_~tmp___1~0#1); 12683#L1407-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12741#L613 assume !(1 == ~t3_pc~0); 12860#L613-2 is_transmit3_triggered_~__retres1~3#1 := 0; 12859#L624 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12785#L625 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 12786#L1415 assume !(0 != activate_threads_~tmp___2~0#1); 13469#L1415-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13187#L632 assume 1 == ~t4_pc~0; 13188#L633 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 13688#L643 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13848#L644 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 14156#L1423 assume !(0 != activate_threads_~tmp___3~0#1); 13794#L1423-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13545#L651 assume 1 == ~t5_pc~0; 13546#L652 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12873#L662 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12874#L663 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 13322#L1431 assume !(0 != activate_threads_~tmp___4~0#1); 12890#L1431-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 12891#L670 assume !(1 == ~t6_pc~0); 13982#L670-2 is_transmit6_triggered_~__retres1~6#1 := 0; 13236#L681 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 13237#L682 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 14079#L1439 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 13510#L1439-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 13511#L689 assume 1 == ~t7_pc~0; 14152#L690 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 13621#L700 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 13622#L701 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 13997#L1447 assume !(0 != activate_threads_~tmp___6~0#1); 13413#L1447-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 13414#L708 assume !(1 == ~t8_pc~0); 12979#L708-2 is_transmit8_triggered_~__retres1~8#1 := 0; 12980#L719 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 14077#L720 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 14062#L1455 assume !(0 != activate_threads_~tmp___7~0#1); 13044#L1455-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 13045#L727 assume 1 == ~t9_pc~0; 13167#L728 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 12743#L738 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 14159#L739 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 14160#L1463 assume !(0 != activate_threads_~tmp___8~0#1); 14147#L1463-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 13098#L746 assume !(1 == ~t10_pc~0); 13099#L746-2 is_transmit10_triggered_~__retres1~10#1 := 0; 13747#L757 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 13863#L758 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 14071#L1471 assume !(0 != activate_threads_~tmp___9~0#1); 13944#L1471-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 13259#L765 assume 1 == ~t11_pc~0; 13260#L766 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 13465#L776 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 12632#L777 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 12633#L1479 assume !(0 != activate_threads_~tmp___10~0#1); 13981#L1479-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14059#L1249 assume !(1 == ~M_E~0); 13692#L1249-2 assume !(1 == ~T1_E~0); 13342#L1254-1 assume !(1 == ~T2_E~0); 12678#L1259-1 assume !(1 == ~T3_E~0); 12660#L1264-1 assume !(1 == ~T4_E~0); 12661#L1269-1 assume !(1 == ~T5_E~0); 14178#L1274-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 14126#L1279-1 assume !(1 == ~T7_E~0); 12861#L1284-1 assume !(1 == ~T8_E~0); 12862#L1289-1 assume !(1 == ~T9_E~0); 13392#L1294-1 assume !(1 == ~T10_E~0); 13393#L1299-1 assume !(1 == ~T11_E~0); 13402#L1304-1 assume !(1 == ~E_M~0); 14172#L1309-1 assume !(1 == ~E_1~0); 14175#L1314-1 assume 1 == ~E_2~0;~E_2~0 := 2; 12808#L1319-1 assume !(1 == ~E_3~0); 12809#L1324-1 assume !(1 == ~E_4~0); 12941#L1329-1 assume !(1 == ~E_5~0); 12942#L1334-1 assume !(1 == ~E_6~0); 14020#L1339-1 assume !(1 == ~E_7~0); 14097#L1344-1 assume !(1 == ~E_8~0); 14098#L1349-1 assume !(1 == ~E_9~0); 13525#L1354-1 assume 1 == ~E_10~0;~E_10~0 := 2; 13526#L1359-1 assume !(1 == ~E_11~0); 13885#L1364-1 assume { :end_inline_reset_delta_events } true; 13030#L1690-2 [2021-12-16 10:05:16,037 INFO L793 eck$LassoCheckResult]: Loop: 13030#L1690-2 assume !false; 13031#L1691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 12916#L1096 assume !false; 13894#L933 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 12762#L860 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 12763#L922 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 13788#L923 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 13257#L937 assume !(0 != eval_~tmp~0#1); 13258#L1111 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 13728#L785-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 13234#L1121-3 assume 0 == ~M_E~0;~M_E~0 := 1; 13235#L1121-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 14148#L1126-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 13440#L1131-3 assume !(0 == ~T3_E~0); 13441#L1136-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 14179#L1141-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 13795#L1146-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 12977#L1151-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 12978#L1156-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 14092#L1161-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 13603#L1166-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 13604#L1171-3 assume !(0 == ~T11_E~0); 13650#L1176-3 assume 0 == ~E_M~0;~E_M~0 := 1; 13026#L1181-3 assume 0 == ~E_1~0;~E_1~0 := 1; 13027#L1186-3 assume 0 == ~E_2~0;~E_2~0 := 1; 13730#L1191-3 assume 0 == ~E_3~0;~E_3~0 := 1; 13731#L1196-3 assume 0 == ~E_4~0;~E_4~0 := 1; 13921#L1201-3 assume 0 == ~E_5~0;~E_5~0 := 1; 13922#L1206-3 assume 0 == ~E_6~0;~E_6~0 := 1; 13627#L1211-3 assume !(0 == ~E_7~0); 12939#L1216-3 assume 0 == ~E_8~0;~E_8~0 := 1; 12940#L1221-3 assume 0 == ~E_9~0;~E_9~0 := 1; 13353#L1226-3 assume 0 == ~E_10~0;~E_10~0 := 1; 12996#L1231-3 assume 0 == ~E_11~0;~E_11~0 := 1; 12997#L1236-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13217#L556-39 assume 1 == ~m_pc~0; 13738#L557-13 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 13705#L567-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13096#L568-13 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 13097#L1391-39 assume !(0 != activate_threads_~tmp~1#1); 13269#L1391-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13663#L575-39 assume 1 == ~t1_pc~0; 13664#L576-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 13929#L586-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13790#L587-13 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 13791#L1399-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 13638#L1399-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13639#L594-39 assume !(1 == ~t2_pc~0); 13850#L594-41 is_transmit2_triggered_~__retres1~2#1 := 0; 13641#L605-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13642#L606-13 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 14064#L1407-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 13155#L1407-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 13156#L613-39 assume 1 == ~t3_pc~0; 14041#L614-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 12638#L624-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12639#L625-13 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 13398#L1415-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 12737#L1415-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12738#L632-39 assume 1 == ~t4_pc~0; 14009#L633-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 13323#L643-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13324#L644-13 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 13877#L1423-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 14008#L1423-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13007#L651-39 assume 1 == ~t5_pc~0; 13008#L652-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12770#L662-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13996#L663-13 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 14104#L1431-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 14141#L1431-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14161#L670-39 assume 1 == ~t6_pc~0; 14162#L671-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 12684#L681-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12685#L682-13 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 12756#L1439-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 13350#L1439-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 13351#L689-39 assume !(1 == ~t7_pc~0); 13474#L689-41 is_transmit7_triggered_~__retres1~7#1 := 0; 13475#L700-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 13009#L701-13 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 13010#L1447-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 12875#L1447-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12876#L708-39 assume !(1 == ~t8_pc~0); 12816#L708-41 is_transmit8_triggered_~__retres1~8#1 := 0; 12815#L719-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12921#L720-13 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 12922#L1455-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 13804#L1455-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 13295#L727-39 assume !(1 == ~t9_pc~0); 13296#L727-41 is_transmit9_triggered_~__retres1~9#1 := 0; 13074#L738-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 13075#L739-13 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 14024#L1463-39 assume !(0 != activate_threads_~tmp___8~0#1); 13852#L1463-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 13853#L746-39 assume !(1 == ~t10_pc~0); 13825#L746-41 is_transmit10_triggered_~__retres1~10#1 := 0; 13824#L757-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 14089#L758-13 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 13559#L1471-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 13560#L1471-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 13972#L765-39 assume 1 == ~t11_pc~0; 12688#L766-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 12690#L776-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 13872#L777-13 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 13028#L1479-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 13029#L1479-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13596#L1249-3 assume 1 == ~M_E~0;~M_E~0 := 2; 12833#L1249-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12834#L1254-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 14091#L1259-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 13719#L1264-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12793#L1269-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 12794#L1274-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 14124#L1279-3 assume !(1 == ~T7_E~0); 13272#L1284-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 13273#L1289-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 13265#L1294-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 13266#L1299-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 13519#L1304-3 assume 1 == ~E_M~0;~E_M~0 := 2; 13520#L1309-3 assume 1 == ~E_1~0;~E_1~0 := 2; 13180#L1314-3 assume 1 == ~E_2~0;~E_2~0 := 2; 13181#L1319-3 assume !(1 == ~E_3~0); 13938#L1324-3 assume 1 == ~E_4~0;~E_4~0 := 2; 12897#L1329-3 assume 1 == ~E_5~0;~E_5~0 := 2; 12898#L1334-3 assume 1 == ~E_6~0;~E_6~0 := 2; 13453#L1339-3 assume 1 == ~E_7~0;~E_7~0 := 2; 13454#L1344-3 assume 1 == ~E_8~0;~E_8~0 := 2; 13672#L1349-3 assume 1 == ~E_9~0;~E_9~0 := 2; 13163#L1354-3 assume 1 == ~E_10~0;~E_10~0 := 2; 13164#L1359-3 assume !(1 == ~E_11~0); 13686#L1364-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 12753#L860-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 12754#L922-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 13381#L923-1 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 13382#L1709 assume !(0 == start_simulation_~tmp~3#1); 13192#L1709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 13958#L860-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 12868#L922-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 13370#L923-2 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 12831#L1664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 12832#L1671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 13649#L1672 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 14031#L1722 assume !(0 != start_simulation_~tmp___0~1#1); 13030#L1690-2 [2021-12-16 10:05:16,037 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:16,037 INFO L85 PathProgramCache]: Analyzing trace with hash -1621157378, now seen corresponding path program 1 times [2021-12-16 10:05:16,038 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:16,038 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [470327355] [2021-12-16 10:05:16,038 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:16,038 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:16,045 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:16,057 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:05:16,057 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:16,057 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [470327355] [2021-12-16 10:05:16,057 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [470327355] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:16,057 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:16,058 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:05:16,058 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [903738008] [2021-12-16 10:05:16,058 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:16,058 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:05:16,058 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:16,059 INFO L85 PathProgramCache]: Analyzing trace with hash -1581912831, now seen corresponding path program 1 times [2021-12-16 10:05:16,059 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:16,059 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1807733721] [2021-12-16 10:05:16,059 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:16,059 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:16,091 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:16,109 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:05:16,109 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:16,110 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1807733721] [2021-12-16 10:05:16,110 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1807733721] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:16,110 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:16,110 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:05:16,110 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1775260866] [2021-12-16 10:05:16,110 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:16,111 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:05:16,111 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:05:16,111 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-16 10:05:16,111 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-16 10:05:16,111 INFO L87 Difference]: Start difference. First operand 1571 states and 2331 transitions. cyclomatic complexity: 761 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:16,131 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:05:16,132 INFO L93 Difference]: Finished difference Result 1571 states and 2330 transitions. [2021-12-16 10:05:16,132 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-16 10:05:16,133 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1571 states and 2330 transitions. [2021-12-16 10:05:16,139 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1420 [2021-12-16 10:05:16,144 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1571 states to 1571 states and 2330 transitions. [2021-12-16 10:05:16,144 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1571 [2021-12-16 10:05:16,145 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1571 [2021-12-16 10:05:16,145 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1571 states and 2330 transitions. [2021-12-16 10:05:16,147 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:05:16,147 INFO L681 BuchiCegarLoop]: Abstraction has 1571 states and 2330 transitions. [2021-12-16 10:05:16,148 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1571 states and 2330 transitions. [2021-12-16 10:05:16,159 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1571 to 1571. [2021-12-16 10:05:16,161 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1571 states, 1571 states have (on average 1.4831317632081478) internal successors, (2330), 1570 states have internal predecessors, (2330), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:16,164 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1571 states to 1571 states and 2330 transitions. [2021-12-16 10:05:16,165 INFO L704 BuchiCegarLoop]: Abstraction has 1571 states and 2330 transitions. [2021-12-16 10:05:16,165 INFO L587 BuchiCegarLoop]: Abstraction has 1571 states and 2330 transitions. [2021-12-16 10:05:16,165 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2021-12-16 10:05:16,165 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1571 states and 2330 transitions. [2021-12-16 10:05:16,169 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1420 [2021-12-16 10:05:16,170 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:05:16,170 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:05:16,171 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:16,171 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:16,171 INFO L791 eck$LassoCheckResult]: Stem: 16437#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 16438#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 16978#L1653 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 16979#L785 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 16848#L792 assume 1 == ~m_i~0;~m_st~0 := 0; 16849#L792-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 15856#L797-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 15857#L802-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 17295#L807-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 16822#L812-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 16823#L817-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 17100#L822-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 17101#L827-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 17184#L832-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 17266#L837-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 17267#L842-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 17148#L847-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 16996#L1121 assume !(0 == ~M_E~0); 16751#L1121-2 assume !(0 == ~T1_E~0); 16132#L1126-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 16133#L1131-1 assume !(0 == ~T3_E~0); 16303#L1136-1 assume !(0 == ~T4_E~0); 16399#L1141-1 assume !(0 == ~T5_E~0); 16619#L1146-1 assume !(0 == ~T6_E~0); 16919#L1151-1 assume !(0 == ~T7_E~0); 16459#L1156-1 assume !(0 == ~T8_E~0); 15842#L1161-1 assume !(0 == ~T9_E~0); 15843#L1166-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 16068#L1171-1 assume !(0 == ~T11_E~0); 16069#L1176-1 assume !(0 == ~E_M~0); 16933#L1181-1 assume !(0 == ~E_1~0); 17061#L1186-1 assume !(0 == ~E_2~0); 17111#L1191-1 assume !(0 == ~E_3~0); 16095#L1196-1 assume !(0 == ~E_4~0); 16096#L1201-1 assume !(0 == ~E_5~0); 17304#L1206-1 assume 0 == ~E_6~0;~E_6~0 := 1; 17149#L1211-1 assume !(0 == ~E_7~0); 17150#L1216-1 assume !(0 == ~E_8~0); 16238#L1221-1 assume !(0 == ~E_9~0); 16239#L1226-1 assume !(0 == ~E_10~0); 15938#L1231-1 assume !(0 == ~E_11~0); 15939#L1236-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16934#L556 assume 1 == ~m_pc~0; 16935#L557 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 15816#L567 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 15817#L568 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 16712#L1391 assume !(0 != activate_threads_~tmp~1#1); 17089#L1391-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17090#L575 assume !(1 == ~t1_pc~0); 15767#L575-2 is_transmit1_triggered_~__retres1~1#1 := 0; 15768#L586 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15901#L587 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 16251#L1399 assume !(0 != activate_threads_~tmp___0~0#1); 16208#L1399-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16209#L594 assume 1 == ~t2_pc~0; 16137#L595 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 16138#L605 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16604#L606 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 15831#L1407 assume !(0 != activate_threads_~tmp___1~0#1); 15832#L1407-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15890#L613 assume !(1 == ~t3_pc~0); 16009#L613-2 is_transmit3_triggered_~__retres1~3#1 := 0; 16008#L624 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15934#L625 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 15935#L1415 assume !(0 != activate_threads_~tmp___2~0#1); 16618#L1415-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16336#L632 assume 1 == ~t4_pc~0; 16337#L633 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 16837#L643 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 16997#L644 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 17305#L1423 assume !(0 != activate_threads_~tmp___3~0#1); 16943#L1423-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16694#L651 assume 1 == ~t5_pc~0; 16695#L652 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 16022#L662 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 16023#L663 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 16471#L1431 assume !(0 != activate_threads_~tmp___4~0#1); 16039#L1431-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 16040#L670 assume !(1 == ~t6_pc~0); 17131#L670-2 is_transmit6_triggered_~__retres1~6#1 := 0; 16385#L681 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 16386#L682 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 17227#L1439 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 16659#L1439-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 16660#L689 assume 1 == ~t7_pc~0; 17301#L690 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 16770#L700 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16771#L701 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 17146#L1447 assume !(0 != activate_threads_~tmp___6~0#1); 16562#L1447-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 16563#L708 assume !(1 == ~t8_pc~0); 16128#L708-2 is_transmit8_triggered_~__retres1~8#1 := 0; 16129#L719 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 17226#L720 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 17211#L1455 assume !(0 != activate_threads_~tmp___7~0#1); 16193#L1455-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 16194#L727 assume 1 == ~t9_pc~0; 16316#L728 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 15892#L738 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 17308#L739 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 17309#L1463 assume !(0 != activate_threads_~tmp___8~0#1); 17296#L1463-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 16247#L746 assume !(1 == ~t10_pc~0); 16248#L746-2 is_transmit10_triggered_~__retres1~10#1 := 0; 16896#L757 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 17012#L758 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 17220#L1471 assume !(0 != activate_threads_~tmp___9~0#1); 17093#L1471-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 16408#L765 assume 1 == ~t11_pc~0; 16409#L766 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 16614#L776 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 15781#L777 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 15782#L1479 assume !(0 != activate_threads_~tmp___10~0#1); 17130#L1479-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17208#L1249 assume !(1 == ~M_E~0); 16841#L1249-2 assume !(1 == ~T1_E~0); 16491#L1254-1 assume !(1 == ~T2_E~0); 15827#L1259-1 assume !(1 == ~T3_E~0); 15809#L1264-1 assume !(1 == ~T4_E~0); 15810#L1269-1 assume !(1 == ~T5_E~0); 17327#L1274-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 17275#L1279-1 assume !(1 == ~T7_E~0); 16010#L1284-1 assume !(1 == ~T8_E~0); 16011#L1289-1 assume !(1 == ~T9_E~0); 16541#L1294-1 assume !(1 == ~T10_E~0); 16542#L1299-1 assume !(1 == ~T11_E~0); 16551#L1304-1 assume !(1 == ~E_M~0); 17321#L1309-1 assume !(1 == ~E_1~0); 17324#L1314-1 assume 1 == ~E_2~0;~E_2~0 := 2; 15957#L1319-1 assume !(1 == ~E_3~0); 15958#L1324-1 assume !(1 == ~E_4~0); 16090#L1329-1 assume !(1 == ~E_5~0); 16091#L1334-1 assume !(1 == ~E_6~0); 17169#L1339-1 assume !(1 == ~E_7~0); 17246#L1344-1 assume !(1 == ~E_8~0); 17247#L1349-1 assume !(1 == ~E_9~0); 16674#L1354-1 assume 1 == ~E_10~0;~E_10~0 := 2; 16675#L1359-1 assume !(1 == ~E_11~0); 17034#L1364-1 assume { :end_inline_reset_delta_events } true; 16179#L1690-2 [2021-12-16 10:05:16,172 INFO L793 eck$LassoCheckResult]: Loop: 16179#L1690-2 assume !false; 16180#L1691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 16065#L1096 assume !false; 17043#L933 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 15911#L860 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 15912#L922 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 16937#L923 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 16406#L937 assume !(0 != eval_~tmp~0#1); 16407#L1111 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 16877#L785-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 16381#L1121-3 assume 0 == ~M_E~0;~M_E~0 := 1; 16382#L1121-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 17297#L1126-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 16589#L1131-3 assume !(0 == ~T3_E~0); 16590#L1136-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 17328#L1141-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 16944#L1146-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 16126#L1151-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 16127#L1156-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 17241#L1161-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 16752#L1166-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 16753#L1171-3 assume !(0 == ~T11_E~0); 16798#L1176-3 assume 0 == ~E_M~0;~E_M~0 := 1; 16175#L1181-3 assume 0 == ~E_1~0;~E_1~0 := 1; 16176#L1186-3 assume 0 == ~E_2~0;~E_2~0 := 1; 16879#L1191-3 assume 0 == ~E_3~0;~E_3~0 := 1; 16880#L1196-3 assume 0 == ~E_4~0;~E_4~0 := 1; 17070#L1201-3 assume 0 == ~E_5~0;~E_5~0 := 1; 17071#L1206-3 assume 0 == ~E_6~0;~E_6~0 := 1; 16776#L1211-3 assume !(0 == ~E_7~0); 16088#L1216-3 assume 0 == ~E_8~0;~E_8~0 := 1; 16089#L1221-3 assume 0 == ~E_9~0;~E_9~0 := 1; 16502#L1226-3 assume 0 == ~E_10~0;~E_10~0 := 1; 16145#L1231-3 assume 0 == ~E_11~0;~E_11~0 := 1; 16146#L1236-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16366#L556-39 assume 1 == ~m_pc~0; 16887#L557-13 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 16854#L567-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16245#L568-13 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 16246#L1391-39 assume !(0 != activate_threads_~tmp~1#1); 16418#L1391-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16812#L575-39 assume 1 == ~t1_pc~0; 16813#L576-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 17078#L586-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16939#L587-13 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 16940#L1399-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 16787#L1399-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16788#L594-39 assume !(1 == ~t2_pc~0); 16999#L594-41 is_transmit2_triggered_~__retres1~2#1 := 0; 16790#L605-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16791#L606-13 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 17213#L1407-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 16304#L1407-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16305#L613-39 assume 1 == ~t3_pc~0; 17190#L614-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 15787#L624-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15788#L625-13 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 16546#L1415-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 15886#L1415-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 15887#L632-39 assume 1 == ~t4_pc~0; 17158#L633-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 16472#L643-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 16473#L644-13 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 17026#L1423-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 17157#L1423-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16156#L651-39 assume 1 == ~t5_pc~0; 16157#L652-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 15919#L662-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 17145#L663-13 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 17252#L1431-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 17290#L1431-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 17310#L670-39 assume !(1 == ~t6_pc~0); 16889#L670-41 is_transmit6_triggered_~__retres1~6#1 := 0; 15833#L681-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 15834#L682-13 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 15902#L1439-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 16499#L1439-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 16500#L689-39 assume 1 == ~t7_pc~0; 16722#L690-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 16624#L700-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16158#L701-13 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 16159#L1447-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 16026#L1447-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 16027#L708-39 assume 1 == ~t8_pc~0; 15963#L709-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 15964#L719-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 16072#L720-13 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 16073#L1455-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 16953#L1455-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 16445#L727-39 assume !(1 == ~t9_pc~0); 16446#L727-41 is_transmit9_triggered_~__retres1~9#1 := 0; 16223#L738-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 16224#L739-13 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 17173#L1463-39 assume !(0 != activate_threads_~tmp___8~0#1); 17002#L1463-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 17003#L746-39 assume 1 == ~t10_pc~0; 16972#L747-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 16973#L757-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 17238#L758-13 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 16708#L1471-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 16709#L1471-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 17121#L765-39 assume 1 == ~t11_pc~0; 15837#L766-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 15839#L776-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 17021#L777-13 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 16177#L1479-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 16178#L1479-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16745#L1249-3 assume 1 == ~M_E~0;~M_E~0 := 2; 15983#L1249-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 15984#L1254-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 17240#L1259-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 16868#L1264-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 15942#L1269-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 15943#L1274-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 17273#L1279-3 assume !(1 == ~T7_E~0); 16421#L1284-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 16422#L1289-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 16416#L1294-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 16417#L1299-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 16668#L1304-3 assume 1 == ~E_M~0;~E_M~0 := 2; 16669#L1309-3 assume 1 == ~E_1~0;~E_1~0 := 2; 16333#L1314-3 assume 1 == ~E_2~0;~E_2~0 := 2; 16334#L1319-3 assume !(1 == ~E_3~0); 17087#L1324-3 assume 1 == ~E_4~0;~E_4~0 := 2; 16052#L1329-3 assume 1 == ~E_5~0;~E_5~0 := 2; 16053#L1334-3 assume 1 == ~E_6~0;~E_6~0 := 2; 16602#L1339-3 assume 1 == ~E_7~0;~E_7~0 := 2; 16603#L1344-3 assume 1 == ~E_8~0;~E_8~0 := 2; 16821#L1349-3 assume 1 == ~E_9~0;~E_9~0 := 2; 16312#L1354-3 assume 1 == ~E_10~0;~E_10~0 := 2; 16313#L1359-3 assume !(1 == ~E_11~0); 16836#L1364-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 15903#L860-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 15904#L922-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 16530#L923-1 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 16531#L1709 assume !(0 == start_simulation_~tmp~3#1); 16341#L1709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 17107#L860-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 16017#L922-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 16519#L923-2 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 15980#L1664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 15981#L1671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 16799#L1672 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 17180#L1722 assume !(0 != start_simulation_~tmp___0~1#1); 16179#L1690-2 [2021-12-16 10:05:16,172 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:16,172 INFO L85 PathProgramCache]: Analyzing trace with hash -1076284804, now seen corresponding path program 1 times [2021-12-16 10:05:16,173 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:16,173 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [436808061] [2021-12-16 10:05:16,173 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:16,173 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:16,180 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:16,192 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:05:16,192 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:16,192 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [436808061] [2021-12-16 10:05:16,192 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [436808061] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:16,192 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:16,193 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:05:16,193 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1612373627] [2021-12-16 10:05:16,193 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:16,193 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:05:16,193 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:16,194 INFO L85 PathProgramCache]: Analyzing trace with hash 210812735, now seen corresponding path program 1 times [2021-12-16 10:05:16,194 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:16,194 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [455973536] [2021-12-16 10:05:16,194 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:16,194 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:16,202 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:16,219 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:05:16,219 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:16,219 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [455973536] [2021-12-16 10:05:16,219 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [455973536] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:16,220 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:16,220 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:05:16,220 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [803279059] [2021-12-16 10:05:16,220 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:16,220 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:05:16,220 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:05:16,221 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-16 10:05:16,221 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-16 10:05:16,221 INFO L87 Difference]: Start difference. First operand 1571 states and 2330 transitions. cyclomatic complexity: 760 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:16,242 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:05:16,243 INFO L93 Difference]: Finished difference Result 1571 states and 2329 transitions. [2021-12-16 10:05:16,243 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-16 10:05:16,244 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1571 states and 2329 transitions. [2021-12-16 10:05:16,249 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1420 [2021-12-16 10:05:16,254 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1571 states to 1571 states and 2329 transitions. [2021-12-16 10:05:16,254 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1571 [2021-12-16 10:05:16,255 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1571 [2021-12-16 10:05:16,255 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1571 states and 2329 transitions. [2021-12-16 10:05:16,257 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:05:16,257 INFO L681 BuchiCegarLoop]: Abstraction has 1571 states and 2329 transitions. [2021-12-16 10:05:16,258 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1571 states and 2329 transitions. [2021-12-16 10:05:16,269 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1571 to 1571. [2021-12-16 10:05:16,271 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1571 states, 1571 states have (on average 1.4824952259707194) internal successors, (2329), 1570 states have internal predecessors, (2329), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:16,275 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1571 states to 1571 states and 2329 transitions. [2021-12-16 10:05:16,275 INFO L704 BuchiCegarLoop]: Abstraction has 1571 states and 2329 transitions. [2021-12-16 10:05:16,275 INFO L587 BuchiCegarLoop]: Abstraction has 1571 states and 2329 transitions. [2021-12-16 10:05:16,275 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2021-12-16 10:05:16,275 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1571 states and 2329 transitions. [2021-12-16 10:05:16,279 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1420 [2021-12-16 10:05:16,279 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:05:16,279 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:05:16,280 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:16,280 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:16,280 INFO L791 eck$LassoCheckResult]: Stem: 19586#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 19587#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 20127#L1653 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 20128#L785 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 19997#L792 assume 1 == ~m_i~0;~m_st~0 := 0; 19998#L792-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 19005#L797-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 19006#L802-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 20444#L807-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 19971#L812-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 19972#L817-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 20249#L822-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 20250#L827-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 20333#L832-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 20415#L837-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 20416#L842-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 20297#L847-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 20145#L1121 assume !(0 == ~M_E~0); 19900#L1121-2 assume !(0 == ~T1_E~0); 19281#L1126-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 19282#L1131-1 assume !(0 == ~T3_E~0); 19452#L1136-1 assume !(0 == ~T4_E~0); 19548#L1141-1 assume !(0 == ~T5_E~0); 19768#L1146-1 assume !(0 == ~T6_E~0); 20068#L1151-1 assume !(0 == ~T7_E~0); 19608#L1156-1 assume !(0 == ~T8_E~0); 18991#L1161-1 assume !(0 == ~T9_E~0); 18992#L1166-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 19217#L1171-1 assume !(0 == ~T11_E~0); 19218#L1176-1 assume !(0 == ~E_M~0); 20082#L1181-1 assume !(0 == ~E_1~0); 20210#L1186-1 assume !(0 == ~E_2~0); 20260#L1191-1 assume !(0 == ~E_3~0); 19244#L1196-1 assume !(0 == ~E_4~0); 19245#L1201-1 assume !(0 == ~E_5~0); 20453#L1206-1 assume 0 == ~E_6~0;~E_6~0 := 1; 20298#L1211-1 assume !(0 == ~E_7~0); 20299#L1216-1 assume !(0 == ~E_8~0); 19387#L1221-1 assume !(0 == ~E_9~0); 19388#L1226-1 assume !(0 == ~E_10~0); 19087#L1231-1 assume !(0 == ~E_11~0); 19088#L1236-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20083#L556 assume 1 == ~m_pc~0; 20084#L557 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 18965#L567 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 18966#L568 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 19861#L1391 assume !(0 != activate_threads_~tmp~1#1); 20238#L1391-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 20239#L575 assume !(1 == ~t1_pc~0); 18916#L575-2 is_transmit1_triggered_~__retres1~1#1 := 0; 18917#L586 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19050#L587 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 19400#L1399 assume !(0 != activate_threads_~tmp___0~0#1); 19357#L1399-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 19358#L594 assume 1 == ~t2_pc~0; 19286#L595 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 19287#L605 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19753#L606 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 18980#L1407 assume !(0 != activate_threads_~tmp___1~0#1); 18981#L1407-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19039#L613 assume !(1 == ~t3_pc~0); 19158#L613-2 is_transmit3_triggered_~__retres1~3#1 := 0; 19157#L624 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19083#L625 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 19084#L1415 assume !(0 != activate_threads_~tmp___2~0#1); 19767#L1415-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19485#L632 assume 1 == ~t4_pc~0; 19486#L633 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 19986#L643 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 20146#L644 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 20454#L1423 assume !(0 != activate_threads_~tmp___3~0#1); 20092#L1423-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 19843#L651 assume 1 == ~t5_pc~0; 19844#L652 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 19171#L662 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19172#L663 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 19620#L1431 assume !(0 != activate_threads_~tmp___4~0#1); 19188#L1431-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19189#L670 assume !(1 == ~t6_pc~0); 20280#L670-2 is_transmit6_triggered_~__retres1~6#1 := 0; 19534#L681 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19535#L682 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 20376#L1439 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 19808#L1439-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 19809#L689 assume 1 == ~t7_pc~0; 20450#L690 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 19919#L700 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19920#L701 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 20295#L1447 assume !(0 != activate_threads_~tmp___6~0#1); 19711#L1447-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 19712#L708 assume !(1 == ~t8_pc~0); 19277#L708-2 is_transmit8_triggered_~__retres1~8#1 := 0; 19278#L719 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 20375#L720 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 20360#L1455 assume !(0 != activate_threads_~tmp___7~0#1); 19342#L1455-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 19343#L727 assume 1 == ~t9_pc~0; 19465#L728 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 19041#L738 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 20457#L739 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 20458#L1463 assume !(0 != activate_threads_~tmp___8~0#1); 20445#L1463-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 19396#L746 assume !(1 == ~t10_pc~0); 19397#L746-2 is_transmit10_triggered_~__retres1~10#1 := 0; 20045#L757 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 20161#L758 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 20369#L1471 assume !(0 != activate_threads_~tmp___9~0#1); 20242#L1471-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 19557#L765 assume 1 == ~t11_pc~0; 19558#L766 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 19763#L776 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 18930#L777 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 18931#L1479 assume !(0 != activate_threads_~tmp___10~0#1); 20279#L1479-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 20357#L1249 assume !(1 == ~M_E~0); 19990#L1249-2 assume !(1 == ~T1_E~0); 19640#L1254-1 assume !(1 == ~T2_E~0); 18976#L1259-1 assume !(1 == ~T3_E~0); 18958#L1264-1 assume !(1 == ~T4_E~0); 18959#L1269-1 assume !(1 == ~T5_E~0); 20476#L1274-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 20424#L1279-1 assume !(1 == ~T7_E~0); 19159#L1284-1 assume !(1 == ~T8_E~0); 19160#L1289-1 assume !(1 == ~T9_E~0); 19690#L1294-1 assume !(1 == ~T10_E~0); 19691#L1299-1 assume !(1 == ~T11_E~0); 19700#L1304-1 assume !(1 == ~E_M~0); 20470#L1309-1 assume !(1 == ~E_1~0); 20473#L1314-1 assume 1 == ~E_2~0;~E_2~0 := 2; 19106#L1319-1 assume !(1 == ~E_3~0); 19107#L1324-1 assume !(1 == ~E_4~0); 19239#L1329-1 assume !(1 == ~E_5~0); 19240#L1334-1 assume !(1 == ~E_6~0); 20318#L1339-1 assume !(1 == ~E_7~0); 20395#L1344-1 assume !(1 == ~E_8~0); 20396#L1349-1 assume !(1 == ~E_9~0); 19823#L1354-1 assume 1 == ~E_10~0;~E_10~0 := 2; 19824#L1359-1 assume !(1 == ~E_11~0); 20183#L1364-1 assume { :end_inline_reset_delta_events } true; 19328#L1690-2 [2021-12-16 10:05:16,281 INFO L793 eck$LassoCheckResult]: Loop: 19328#L1690-2 assume !false; 19329#L1691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 19214#L1096 assume !false; 20192#L933 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 19060#L860 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 19061#L922 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 20086#L923 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 19555#L937 assume !(0 != eval_~tmp~0#1); 19556#L1111 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 20026#L785-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 19530#L1121-3 assume 0 == ~M_E~0;~M_E~0 := 1; 19531#L1121-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 20446#L1126-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 19738#L1131-3 assume !(0 == ~T3_E~0); 19739#L1136-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 20477#L1141-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 20093#L1146-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 19275#L1151-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 19276#L1156-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 20390#L1161-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 19901#L1166-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 19902#L1171-3 assume !(0 == ~T11_E~0); 19947#L1176-3 assume 0 == ~E_M~0;~E_M~0 := 1; 19324#L1181-3 assume 0 == ~E_1~0;~E_1~0 := 1; 19325#L1186-3 assume 0 == ~E_2~0;~E_2~0 := 1; 20028#L1191-3 assume 0 == ~E_3~0;~E_3~0 := 1; 20029#L1196-3 assume 0 == ~E_4~0;~E_4~0 := 1; 20219#L1201-3 assume 0 == ~E_5~0;~E_5~0 := 1; 20220#L1206-3 assume 0 == ~E_6~0;~E_6~0 := 1; 19925#L1211-3 assume !(0 == ~E_7~0); 19237#L1216-3 assume 0 == ~E_8~0;~E_8~0 := 1; 19238#L1221-3 assume 0 == ~E_9~0;~E_9~0 := 1; 19651#L1226-3 assume 0 == ~E_10~0;~E_10~0 := 1; 19294#L1231-3 assume 0 == ~E_11~0;~E_11~0 := 1; 19295#L1236-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 19515#L556-39 assume 1 == ~m_pc~0; 20036#L557-13 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 20003#L567-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19394#L568-13 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 19395#L1391-39 assume !(0 != activate_threads_~tmp~1#1); 19567#L1391-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19961#L575-39 assume 1 == ~t1_pc~0; 19962#L576-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 20227#L586-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 20088#L587-13 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 20089#L1399-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 19936#L1399-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 19937#L594-39 assume !(1 == ~t2_pc~0); 20148#L594-41 is_transmit2_triggered_~__retres1~2#1 := 0; 19939#L605-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19940#L606-13 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 20362#L1407-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 19453#L1407-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19454#L613-39 assume 1 == ~t3_pc~0; 20339#L614-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 18936#L624-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18937#L625-13 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 19695#L1415-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 19035#L1415-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19036#L632-39 assume 1 == ~t4_pc~0; 20307#L633-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 19621#L643-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19622#L644-13 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 20175#L1423-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 20306#L1423-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 19305#L651-39 assume 1 == ~t5_pc~0; 19306#L652-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 19068#L662-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 20294#L663-13 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 20401#L1431-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 20439#L1431-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 20459#L670-39 assume !(1 == ~t6_pc~0); 20038#L670-41 is_transmit6_triggered_~__retres1~6#1 := 0; 18982#L681-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 18983#L682-13 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 19051#L1439-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 19648#L1439-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 19649#L689-39 assume !(1 == ~t7_pc~0); 19772#L689-41 is_transmit7_triggered_~__retres1~7#1 := 0; 19773#L700-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19307#L701-13 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 19308#L1447-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 19175#L1447-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 19176#L708-39 assume 1 == ~t8_pc~0; 19112#L709-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 19113#L719-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 19221#L720-13 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 19222#L1455-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 20102#L1455-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 19594#L727-39 assume !(1 == ~t9_pc~0); 19595#L727-41 is_transmit9_triggered_~__retres1~9#1 := 0; 19372#L738-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 19373#L739-13 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 20322#L1463-39 assume !(0 != activate_threads_~tmp___8~0#1); 20151#L1463-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 20152#L746-39 assume 1 == ~t10_pc~0; 20121#L747-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 20122#L757-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 20387#L758-13 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 19857#L1471-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 19858#L1471-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 20270#L765-39 assume 1 == ~t11_pc~0; 18986#L766-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 18988#L776-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 20170#L777-13 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 19326#L1479-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 19327#L1479-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19894#L1249-3 assume 1 == ~M_E~0;~M_E~0 := 2; 19132#L1249-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 19133#L1254-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 20389#L1259-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 20017#L1264-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 19091#L1269-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 19092#L1274-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 20422#L1279-3 assume !(1 == ~T7_E~0); 19570#L1284-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 19571#L1289-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 19565#L1294-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 19566#L1299-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 19817#L1304-3 assume 1 == ~E_M~0;~E_M~0 := 2; 19818#L1309-3 assume 1 == ~E_1~0;~E_1~0 := 2; 19482#L1314-3 assume 1 == ~E_2~0;~E_2~0 := 2; 19483#L1319-3 assume !(1 == ~E_3~0); 20236#L1324-3 assume 1 == ~E_4~0;~E_4~0 := 2; 19201#L1329-3 assume 1 == ~E_5~0;~E_5~0 := 2; 19202#L1334-3 assume 1 == ~E_6~0;~E_6~0 := 2; 19751#L1339-3 assume 1 == ~E_7~0;~E_7~0 := 2; 19752#L1344-3 assume 1 == ~E_8~0;~E_8~0 := 2; 19970#L1349-3 assume 1 == ~E_9~0;~E_9~0 := 2; 19461#L1354-3 assume 1 == ~E_10~0;~E_10~0 := 2; 19462#L1359-3 assume !(1 == ~E_11~0); 19985#L1364-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 19052#L860-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 19053#L922-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 19679#L923-1 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 19680#L1709 assume !(0 == start_simulation_~tmp~3#1); 19490#L1709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 20256#L860-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 19166#L922-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 19668#L923-2 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 19129#L1664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 19130#L1671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 19948#L1672 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 20329#L1722 assume !(0 != start_simulation_~tmp___0~1#1); 19328#L1690-2 [2021-12-16 10:05:16,281 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:16,281 INFO L85 PathProgramCache]: Analyzing trace with hash -1751444930, now seen corresponding path program 1 times [2021-12-16 10:05:16,282 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:16,282 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1396590463] [2021-12-16 10:05:16,282 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:16,282 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:16,289 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:16,301 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:05:16,301 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:16,301 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1396590463] [2021-12-16 10:05:16,301 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1396590463] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:16,302 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:16,302 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:05:16,302 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2081058442] [2021-12-16 10:05:16,302 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:16,302 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:05:16,303 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:16,303 INFO L85 PathProgramCache]: Analyzing trace with hash -1946660288, now seen corresponding path program 2 times [2021-12-16 10:05:16,303 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:16,303 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1493562263] [2021-12-16 10:05:16,303 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:16,303 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:16,333 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:16,350 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:05:16,351 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:16,351 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1493562263] [2021-12-16 10:05:16,351 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1493562263] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:16,351 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:16,351 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:05:16,351 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [310005520] [2021-12-16 10:05:16,352 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:16,352 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:05:16,352 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:05:16,352 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-16 10:05:16,352 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-16 10:05:16,353 INFO L87 Difference]: Start difference. First operand 1571 states and 2329 transitions. cyclomatic complexity: 759 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:16,374 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:05:16,375 INFO L93 Difference]: Finished difference Result 1571 states and 2328 transitions. [2021-12-16 10:05:16,375 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-16 10:05:16,376 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1571 states and 2328 transitions. [2021-12-16 10:05:16,381 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1420 [2021-12-16 10:05:16,387 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1571 states to 1571 states and 2328 transitions. [2021-12-16 10:05:16,387 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1571 [2021-12-16 10:05:16,388 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1571 [2021-12-16 10:05:16,388 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1571 states and 2328 transitions. [2021-12-16 10:05:16,390 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:05:16,390 INFO L681 BuchiCegarLoop]: Abstraction has 1571 states and 2328 transitions. [2021-12-16 10:05:16,391 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1571 states and 2328 transitions. [2021-12-16 10:05:16,403 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1571 to 1571. [2021-12-16 10:05:16,405 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1571 states, 1571 states have (on average 1.481858688733291) internal successors, (2328), 1570 states have internal predecessors, (2328), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:16,409 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1571 states to 1571 states and 2328 transitions. [2021-12-16 10:05:16,410 INFO L704 BuchiCegarLoop]: Abstraction has 1571 states and 2328 transitions. [2021-12-16 10:05:16,410 INFO L587 BuchiCegarLoop]: Abstraction has 1571 states and 2328 transitions. [2021-12-16 10:05:16,410 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2021-12-16 10:05:16,410 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1571 states and 2328 transitions. [2021-12-16 10:05:16,414 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1420 [2021-12-16 10:05:16,414 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:05:16,414 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:05:16,415 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:16,415 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:16,416 INFO L791 eck$LassoCheckResult]: Stem: 22735#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 22736#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 23276#L1653 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 23277#L785 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 23146#L792 assume 1 == ~m_i~0;~m_st~0 := 0; 23147#L792-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 22154#L797-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 22155#L802-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 23593#L807-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 23120#L812-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 23121#L817-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 23398#L822-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 23399#L827-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 23482#L832-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 23564#L837-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 23565#L842-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 23446#L847-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 23294#L1121 assume !(0 == ~M_E~0); 23049#L1121-2 assume !(0 == ~T1_E~0); 22430#L1126-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 22431#L1131-1 assume !(0 == ~T3_E~0); 22601#L1136-1 assume !(0 == ~T4_E~0); 22697#L1141-1 assume !(0 == ~T5_E~0); 22917#L1146-1 assume !(0 == ~T6_E~0); 23217#L1151-1 assume !(0 == ~T7_E~0); 22757#L1156-1 assume !(0 == ~T8_E~0); 22140#L1161-1 assume !(0 == ~T9_E~0); 22141#L1166-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 22366#L1171-1 assume !(0 == ~T11_E~0); 22367#L1176-1 assume !(0 == ~E_M~0); 23231#L1181-1 assume !(0 == ~E_1~0); 23359#L1186-1 assume !(0 == ~E_2~0); 23409#L1191-1 assume !(0 == ~E_3~0); 22393#L1196-1 assume !(0 == ~E_4~0); 22394#L1201-1 assume !(0 == ~E_5~0); 23602#L1206-1 assume 0 == ~E_6~0;~E_6~0 := 1; 23447#L1211-1 assume !(0 == ~E_7~0); 23448#L1216-1 assume !(0 == ~E_8~0); 22536#L1221-1 assume !(0 == ~E_9~0); 22537#L1226-1 assume !(0 == ~E_10~0); 22236#L1231-1 assume !(0 == ~E_11~0); 22237#L1236-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 23232#L556 assume 1 == ~m_pc~0; 23233#L557 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 22114#L567 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 22115#L568 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 23010#L1391 assume !(0 != activate_threads_~tmp~1#1); 23387#L1391-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 23388#L575 assume !(1 == ~t1_pc~0); 22065#L575-2 is_transmit1_triggered_~__retres1~1#1 := 0; 22066#L586 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22199#L587 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 22549#L1399 assume !(0 != activate_threads_~tmp___0~0#1); 22506#L1399-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22507#L594 assume 1 == ~t2_pc~0; 22435#L595 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 22436#L605 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 22902#L606 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 22129#L1407 assume !(0 != activate_threads_~tmp___1~0#1); 22130#L1407-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22188#L613 assume !(1 == ~t3_pc~0); 22307#L613-2 is_transmit3_triggered_~__retres1~3#1 := 0; 22306#L624 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22232#L625 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 22233#L1415 assume !(0 != activate_threads_~tmp___2~0#1); 22916#L1415-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 22634#L632 assume 1 == ~t4_pc~0; 22635#L633 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 23135#L643 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 23295#L644 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 23603#L1423 assume !(0 != activate_threads_~tmp___3~0#1); 23241#L1423-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 22992#L651 assume 1 == ~t5_pc~0; 22993#L652 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 22320#L662 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 22321#L663 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 22769#L1431 assume !(0 != activate_threads_~tmp___4~0#1); 22337#L1431-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 22338#L670 assume !(1 == ~t6_pc~0); 23429#L670-2 is_transmit6_triggered_~__retres1~6#1 := 0; 22683#L681 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 22684#L682 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 23525#L1439 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 22957#L1439-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 22958#L689 assume 1 == ~t7_pc~0; 23599#L690 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 23068#L700 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 23069#L701 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 23444#L1447 assume !(0 != activate_threads_~tmp___6~0#1); 22860#L1447-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 22861#L708 assume !(1 == ~t8_pc~0); 22426#L708-2 is_transmit8_triggered_~__retres1~8#1 := 0; 22427#L719 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 23524#L720 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 23509#L1455 assume !(0 != activate_threads_~tmp___7~0#1); 22491#L1455-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 22492#L727 assume 1 == ~t9_pc~0; 22614#L728 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 22190#L738 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 23606#L739 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 23607#L1463 assume !(0 != activate_threads_~tmp___8~0#1); 23594#L1463-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 22545#L746 assume !(1 == ~t10_pc~0); 22546#L746-2 is_transmit10_triggered_~__retres1~10#1 := 0; 23194#L757 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 23310#L758 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 23518#L1471 assume !(0 != activate_threads_~tmp___9~0#1); 23391#L1471-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 22706#L765 assume 1 == ~t11_pc~0; 22707#L766 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 22912#L776 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 22079#L777 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 22080#L1479 assume !(0 != activate_threads_~tmp___10~0#1); 23428#L1479-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 23506#L1249 assume !(1 == ~M_E~0); 23139#L1249-2 assume !(1 == ~T1_E~0); 22789#L1254-1 assume !(1 == ~T2_E~0); 22125#L1259-1 assume !(1 == ~T3_E~0); 22107#L1264-1 assume !(1 == ~T4_E~0); 22108#L1269-1 assume !(1 == ~T5_E~0); 23625#L1274-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 23573#L1279-1 assume !(1 == ~T7_E~0); 22308#L1284-1 assume !(1 == ~T8_E~0); 22309#L1289-1 assume !(1 == ~T9_E~0); 22839#L1294-1 assume !(1 == ~T10_E~0); 22840#L1299-1 assume !(1 == ~T11_E~0); 22849#L1304-1 assume !(1 == ~E_M~0); 23619#L1309-1 assume !(1 == ~E_1~0); 23622#L1314-1 assume 1 == ~E_2~0;~E_2~0 := 2; 22255#L1319-1 assume !(1 == ~E_3~0); 22256#L1324-1 assume !(1 == ~E_4~0); 22388#L1329-1 assume !(1 == ~E_5~0); 22389#L1334-1 assume !(1 == ~E_6~0); 23467#L1339-1 assume !(1 == ~E_7~0); 23544#L1344-1 assume !(1 == ~E_8~0); 23545#L1349-1 assume !(1 == ~E_9~0); 22972#L1354-1 assume 1 == ~E_10~0;~E_10~0 := 2; 22973#L1359-1 assume !(1 == ~E_11~0); 23332#L1364-1 assume { :end_inline_reset_delta_events } true; 22477#L1690-2 [2021-12-16 10:05:16,416 INFO L793 eck$LassoCheckResult]: Loop: 22477#L1690-2 assume !false; 22478#L1691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 22363#L1096 assume !false; 23341#L933 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 22209#L860 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 22210#L922 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 23235#L923 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 22704#L937 assume !(0 != eval_~tmp~0#1); 22705#L1111 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 23175#L785-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 22679#L1121-3 assume 0 == ~M_E~0;~M_E~0 := 1; 22680#L1121-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 23595#L1126-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 22887#L1131-3 assume !(0 == ~T3_E~0); 22888#L1136-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 23626#L1141-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 23242#L1146-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 22424#L1151-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 22425#L1156-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 23539#L1161-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 23050#L1166-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 23051#L1171-3 assume !(0 == ~T11_E~0); 23096#L1176-3 assume 0 == ~E_M~0;~E_M~0 := 1; 22473#L1181-3 assume 0 == ~E_1~0;~E_1~0 := 1; 22474#L1186-3 assume 0 == ~E_2~0;~E_2~0 := 1; 23177#L1191-3 assume 0 == ~E_3~0;~E_3~0 := 1; 23178#L1196-3 assume 0 == ~E_4~0;~E_4~0 := 1; 23368#L1201-3 assume 0 == ~E_5~0;~E_5~0 := 1; 23369#L1206-3 assume 0 == ~E_6~0;~E_6~0 := 1; 23074#L1211-3 assume !(0 == ~E_7~0); 22386#L1216-3 assume 0 == ~E_8~0;~E_8~0 := 1; 22387#L1221-3 assume 0 == ~E_9~0;~E_9~0 := 1; 22800#L1226-3 assume 0 == ~E_10~0;~E_10~0 := 1; 22443#L1231-3 assume 0 == ~E_11~0;~E_11~0 := 1; 22444#L1236-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 22664#L556-39 assume 1 == ~m_pc~0; 23185#L557-13 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 23152#L567-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 22543#L568-13 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 22544#L1391-39 assume !(0 != activate_threads_~tmp~1#1); 22716#L1391-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 23110#L575-39 assume 1 == ~t1_pc~0; 23111#L576-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 23376#L586-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 23237#L587-13 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 23238#L1399-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 23085#L1399-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 23086#L594-39 assume !(1 == ~t2_pc~0); 23297#L594-41 is_transmit2_triggered_~__retres1~2#1 := 0; 23088#L605-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 23089#L606-13 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 23511#L1407-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 22602#L1407-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22603#L613-39 assume 1 == ~t3_pc~0; 23488#L614-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 22085#L624-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22086#L625-13 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 22844#L1415-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 22184#L1415-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 22185#L632-39 assume 1 == ~t4_pc~0; 23456#L633-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 22770#L643-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 22771#L644-13 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 23324#L1423-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 23455#L1423-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 22454#L651-39 assume 1 == ~t5_pc~0; 22455#L652-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 22217#L662-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 23443#L663-13 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 23550#L1431-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 23588#L1431-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 23608#L670-39 assume !(1 == ~t6_pc~0); 23187#L670-41 is_transmit6_triggered_~__retres1~6#1 := 0; 22131#L681-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 22132#L682-13 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 22200#L1439-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 22797#L1439-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 22798#L689-39 assume !(1 == ~t7_pc~0); 22921#L689-41 is_transmit7_triggered_~__retres1~7#1 := 0; 22922#L700-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 22456#L701-13 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 22457#L1447-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 22324#L1447-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 22325#L708-39 assume 1 == ~t8_pc~0; 22261#L709-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 22262#L719-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 22370#L720-13 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 22371#L1455-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 23251#L1455-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 22743#L727-39 assume !(1 == ~t9_pc~0); 22744#L727-41 is_transmit9_triggered_~__retres1~9#1 := 0; 22521#L738-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 22522#L739-13 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 23471#L1463-39 assume !(0 != activate_threads_~tmp___8~0#1); 23300#L1463-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 23301#L746-39 assume 1 == ~t10_pc~0; 23270#L747-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 23271#L757-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 23536#L758-13 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 23006#L1471-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 23007#L1471-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 23419#L765-39 assume 1 == ~t11_pc~0; 22135#L766-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 22137#L776-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 23319#L777-13 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 22475#L1479-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 22476#L1479-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 23043#L1249-3 assume 1 == ~M_E~0;~M_E~0 := 2; 22281#L1249-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 22282#L1254-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 23538#L1259-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 23166#L1264-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 22240#L1269-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 22241#L1274-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 23571#L1279-3 assume !(1 == ~T7_E~0); 22719#L1284-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 22720#L1289-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 22714#L1294-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 22715#L1299-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 22966#L1304-3 assume 1 == ~E_M~0;~E_M~0 := 2; 22967#L1309-3 assume 1 == ~E_1~0;~E_1~0 := 2; 22631#L1314-3 assume 1 == ~E_2~0;~E_2~0 := 2; 22632#L1319-3 assume !(1 == ~E_3~0); 23385#L1324-3 assume 1 == ~E_4~0;~E_4~0 := 2; 22350#L1329-3 assume 1 == ~E_5~0;~E_5~0 := 2; 22351#L1334-3 assume 1 == ~E_6~0;~E_6~0 := 2; 22900#L1339-3 assume 1 == ~E_7~0;~E_7~0 := 2; 22901#L1344-3 assume 1 == ~E_8~0;~E_8~0 := 2; 23119#L1349-3 assume 1 == ~E_9~0;~E_9~0 := 2; 22610#L1354-3 assume 1 == ~E_10~0;~E_10~0 := 2; 22611#L1359-3 assume !(1 == ~E_11~0); 23134#L1364-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 22201#L860-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 22202#L922-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 22828#L923-1 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 22829#L1709 assume !(0 == start_simulation_~tmp~3#1); 22639#L1709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 23405#L860-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 22315#L922-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 22817#L923-2 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 22278#L1664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 22279#L1671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 23097#L1672 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 23478#L1722 assume !(0 != start_simulation_~tmp___0~1#1); 22477#L1690-2 [2021-12-16 10:05:16,417 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:16,417 INFO L85 PathProgramCache]: Analyzing trace with hash -803392964, now seen corresponding path program 1 times [2021-12-16 10:05:16,417 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:16,417 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1846616477] [2021-12-16 10:05:16,417 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:16,417 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:16,425 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:16,439 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:05:16,440 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:16,440 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1846616477] [2021-12-16 10:05:16,440 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1846616477] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:16,440 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:16,440 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:05:16,440 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [895728561] [2021-12-16 10:05:16,441 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:16,441 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:05:16,441 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:16,441 INFO L85 PathProgramCache]: Analyzing trace with hash -1946660288, now seen corresponding path program 3 times [2021-12-16 10:05:16,442 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:16,442 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1555366697] [2021-12-16 10:05:16,442 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:16,442 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:16,451 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:16,469 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:05:16,470 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:16,470 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1555366697] [2021-12-16 10:05:16,470 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1555366697] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:16,470 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:16,470 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:05:16,470 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [809978082] [2021-12-16 10:05:16,471 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:16,471 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:05:16,471 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:05:16,471 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-16 10:05:16,472 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-16 10:05:16,472 INFO L87 Difference]: Start difference. First operand 1571 states and 2328 transitions. cyclomatic complexity: 758 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:16,495 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:05:16,495 INFO L93 Difference]: Finished difference Result 1571 states and 2327 transitions. [2021-12-16 10:05:16,495 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-16 10:05:16,496 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1571 states and 2327 transitions. [2021-12-16 10:05:16,501 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1420 [2021-12-16 10:05:16,507 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1571 states to 1571 states and 2327 transitions. [2021-12-16 10:05:16,507 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1571 [2021-12-16 10:05:16,508 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1571 [2021-12-16 10:05:16,509 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1571 states and 2327 transitions. [2021-12-16 10:05:16,510 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:05:16,510 INFO L681 BuchiCegarLoop]: Abstraction has 1571 states and 2327 transitions. [2021-12-16 10:05:16,512 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1571 states and 2327 transitions. [2021-12-16 10:05:16,524 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1571 to 1571. [2021-12-16 10:05:16,527 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1571 states, 1571 states have (on average 1.4812221514958626) internal successors, (2327), 1570 states have internal predecessors, (2327), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:16,531 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1571 states to 1571 states and 2327 transitions. [2021-12-16 10:05:16,531 INFO L704 BuchiCegarLoop]: Abstraction has 1571 states and 2327 transitions. [2021-12-16 10:05:16,531 INFO L587 BuchiCegarLoop]: Abstraction has 1571 states and 2327 transitions. [2021-12-16 10:05:16,531 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2021-12-16 10:05:16,531 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1571 states and 2327 transitions. [2021-12-16 10:05:16,535 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1420 [2021-12-16 10:05:16,536 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:05:16,536 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:05:16,537 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:16,537 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:16,537 INFO L791 eck$LassoCheckResult]: Stem: 25886#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 25887#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 26425#L1653 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 26426#L785 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 26295#L792 assume 1 == ~m_i~0;~m_st~0 := 0; 26296#L792-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 25303#L797-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 25304#L802-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 26742#L807-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 26269#L812-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 26270#L817-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 26547#L822-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 26548#L827-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 26631#L832-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 26713#L837-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 26714#L842-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 26595#L847-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 26443#L1121 assume !(0 == ~M_E~0); 26198#L1121-2 assume !(0 == ~T1_E~0); 25580#L1126-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 25581#L1131-1 assume !(0 == ~T3_E~0); 25750#L1136-1 assume !(0 == ~T4_E~0); 25846#L1141-1 assume !(0 == ~T5_E~0); 26071#L1146-1 assume !(0 == ~T6_E~0); 26366#L1151-1 assume !(0 == ~T7_E~0); 25906#L1156-1 assume !(0 == ~T8_E~0); 25289#L1161-1 assume !(0 == ~T9_E~0); 25290#L1166-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 25515#L1171-1 assume !(0 == ~T11_E~0); 25516#L1176-1 assume !(0 == ~E_M~0); 26380#L1181-1 assume !(0 == ~E_1~0); 26508#L1186-1 assume !(0 == ~E_2~0); 26558#L1191-1 assume !(0 == ~E_3~0); 25542#L1196-1 assume !(0 == ~E_4~0); 25543#L1201-1 assume !(0 == ~E_5~0); 26751#L1206-1 assume 0 == ~E_6~0;~E_6~0 := 1; 26596#L1211-1 assume !(0 == ~E_7~0); 26597#L1216-1 assume !(0 == ~E_8~0); 25685#L1221-1 assume !(0 == ~E_9~0); 25686#L1226-1 assume !(0 == ~E_10~0); 25385#L1231-1 assume !(0 == ~E_11~0); 25386#L1236-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 26381#L556 assume 1 == ~m_pc~0; 26382#L557 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 25263#L567 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 25264#L568 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 26160#L1391 assume !(0 != activate_threads_~tmp~1#1); 26536#L1391-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26537#L575 assume !(1 == ~t1_pc~0); 25214#L575-2 is_transmit1_triggered_~__retres1~1#1 := 0; 25215#L586 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 25348#L587 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 25698#L1399 assume !(0 != activate_threads_~tmp___0~0#1); 25655#L1399-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 25656#L594 assume 1 == ~t2_pc~0; 25584#L595 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 25585#L605 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 26051#L606 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 25280#L1407 assume !(0 != activate_threads_~tmp___1~0#1); 25281#L1407-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 25337#L613 assume !(1 == ~t3_pc~0); 25456#L613-2 is_transmit3_triggered_~__retres1~3#1 := 0; 25455#L624 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 25381#L625 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 25382#L1415 assume !(0 != activate_threads_~tmp___2~0#1); 26065#L1415-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 25783#L632 assume 1 == ~t4_pc~0; 25784#L633 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 26284#L643 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 26444#L644 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 26752#L1423 assume !(0 != activate_threads_~tmp___3~0#1); 26390#L1423-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 26141#L651 assume 1 == ~t5_pc~0; 26142#L652 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 25469#L662 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 25470#L663 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 25918#L1431 assume !(0 != activate_threads_~tmp___4~0#1); 25486#L1431-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 25487#L670 assume !(1 == ~t6_pc~0); 26578#L670-2 is_transmit6_triggered_~__retres1~6#1 := 0; 25834#L681 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 25835#L682 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 26675#L1439 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 26106#L1439-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 26107#L689 assume 1 == ~t7_pc~0; 26748#L690 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 26217#L700 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 26218#L701 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 26593#L1447 assume !(0 != activate_threads_~tmp___6~0#1); 26009#L1447-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 26010#L708 assume !(1 == ~t8_pc~0); 25575#L708-2 is_transmit8_triggered_~__retres1~8#1 := 0; 25576#L719 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 26673#L720 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 26658#L1455 assume !(0 != activate_threads_~tmp___7~0#1); 25640#L1455-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 25641#L727 assume 1 == ~t9_pc~0; 25763#L728 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 25339#L738 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 26755#L739 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 26756#L1463 assume !(0 != activate_threads_~tmp___8~0#1); 26743#L1463-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 25694#L746 assume !(1 == ~t10_pc~0); 25695#L746-2 is_transmit10_triggered_~__retres1~10#1 := 0; 26343#L757 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 26459#L758 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 26667#L1471 assume !(0 != activate_threads_~tmp___9~0#1); 26540#L1471-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 25855#L765 assume 1 == ~t11_pc~0; 25856#L766 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 26061#L776 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 25228#L777 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 25229#L1479 assume !(0 != activate_threads_~tmp___10~0#1); 26577#L1479-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 26655#L1249 assume !(1 == ~M_E~0); 26288#L1249-2 assume !(1 == ~T1_E~0); 25938#L1254-1 assume !(1 == ~T2_E~0); 25274#L1259-1 assume !(1 == ~T3_E~0); 25256#L1264-1 assume !(1 == ~T4_E~0); 25257#L1269-1 assume !(1 == ~T5_E~0); 26774#L1274-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 26722#L1279-1 assume !(1 == ~T7_E~0); 25457#L1284-1 assume !(1 == ~T8_E~0); 25458#L1289-1 assume !(1 == ~T9_E~0); 25988#L1294-1 assume !(1 == ~T10_E~0); 25989#L1299-1 assume !(1 == ~T11_E~0); 25998#L1304-1 assume !(1 == ~E_M~0); 26768#L1309-1 assume !(1 == ~E_1~0); 26771#L1314-1 assume 1 == ~E_2~0;~E_2~0 := 2; 25404#L1319-1 assume !(1 == ~E_3~0); 25405#L1324-1 assume !(1 == ~E_4~0); 25537#L1329-1 assume !(1 == ~E_5~0); 25538#L1334-1 assume !(1 == ~E_6~0); 26616#L1339-1 assume !(1 == ~E_7~0); 26693#L1344-1 assume !(1 == ~E_8~0); 26694#L1349-1 assume !(1 == ~E_9~0); 26121#L1354-1 assume 1 == ~E_10~0;~E_10~0 := 2; 26122#L1359-1 assume !(1 == ~E_11~0); 26481#L1364-1 assume { :end_inline_reset_delta_events } true; 25626#L1690-2 [2021-12-16 10:05:16,538 INFO L793 eck$LassoCheckResult]: Loop: 25626#L1690-2 assume !false; 25627#L1691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 25512#L1096 assume !false; 26490#L933 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 25358#L860 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 25359#L922 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 26384#L923 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 25853#L937 assume !(0 != eval_~tmp~0#1); 25854#L1111 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 26324#L785-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 25830#L1121-3 assume 0 == ~M_E~0;~M_E~0 := 1; 25831#L1121-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 26744#L1126-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 26036#L1131-3 assume !(0 == ~T3_E~0); 26037#L1136-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 26775#L1141-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 26391#L1146-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 25573#L1151-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 25574#L1156-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 26688#L1161-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 26199#L1166-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 26200#L1171-3 assume !(0 == ~T11_E~0); 26246#L1176-3 assume 0 == ~E_M~0;~E_M~0 := 1; 25622#L1181-3 assume 0 == ~E_1~0;~E_1~0 := 1; 25623#L1186-3 assume 0 == ~E_2~0;~E_2~0 := 1; 26326#L1191-3 assume 0 == ~E_3~0;~E_3~0 := 1; 26327#L1196-3 assume 0 == ~E_4~0;~E_4~0 := 1; 26517#L1201-3 assume 0 == ~E_5~0;~E_5~0 := 1; 26518#L1206-3 assume 0 == ~E_6~0;~E_6~0 := 1; 26223#L1211-3 assume !(0 == ~E_7~0); 25535#L1216-3 assume 0 == ~E_8~0;~E_8~0 := 1; 25536#L1221-3 assume 0 == ~E_9~0;~E_9~0 := 1; 25949#L1226-3 assume 0 == ~E_10~0;~E_10~0 := 1; 25592#L1231-3 assume 0 == ~E_11~0;~E_11~0 := 1; 25593#L1236-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 25813#L556-39 assume 1 == ~m_pc~0; 26334#L557-13 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 26301#L567-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 25692#L568-13 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 25693#L1391-39 assume !(0 != activate_threads_~tmp~1#1); 25865#L1391-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26259#L575-39 assume 1 == ~t1_pc~0; 26260#L576-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 26525#L586-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 26386#L587-13 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 26387#L1399-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 26234#L1399-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 26235#L594-39 assume !(1 == ~t2_pc~0); 26446#L594-41 is_transmit2_triggered_~__retres1~2#1 := 0; 26237#L605-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 26238#L606-13 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 26660#L1407-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 25751#L1407-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 25752#L613-39 assume 1 == ~t3_pc~0; 26637#L614-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 25234#L624-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 25235#L625-13 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 25997#L1415-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 25333#L1415-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 25334#L632-39 assume !(1 == ~t4_pc~0); 26482#L632-41 is_transmit4_triggered_~__retres1~4#1 := 0; 25919#L643-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 25920#L644-13 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 26473#L1423-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 26604#L1423-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 25600#L651-39 assume 1 == ~t5_pc~0; 25601#L652-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 25364#L662-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 26592#L663-13 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 26699#L1431-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 26737#L1431-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 26757#L670-39 assume !(1 == ~t6_pc~0); 26336#L670-41 is_transmit6_triggered_~__retres1~6#1 := 0; 25278#L681-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 25279#L682-13 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 25349#L1439-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 25946#L1439-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 25947#L689-39 assume !(1 == ~t7_pc~0); 26069#L689-41 is_transmit7_triggered_~__retres1~7#1 := 0; 26070#L700-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 25605#L701-13 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 25606#L1447-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 25473#L1447-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 25474#L708-39 assume 1 == ~t8_pc~0; 25410#L709-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 25411#L719-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 25517#L720-13 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 25518#L1455-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 26400#L1455-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 25892#L727-39 assume !(1 == ~t9_pc~0); 25893#L727-41 is_transmit9_triggered_~__retres1~9#1 := 0; 25670#L738-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 25671#L739-13 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 26620#L1463-39 assume !(0 != activate_threads_~tmp___8~0#1); 26448#L1463-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 26449#L746-39 assume 1 == ~t10_pc~0; 26419#L747-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 26420#L757-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 26685#L758-13 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 26155#L1471-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 26156#L1471-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 26568#L765-39 assume 1 == ~t11_pc~0; 25284#L766-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 25286#L776-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 26468#L777-13 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 25624#L1479-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 25625#L1479-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 26192#L1249-3 assume 1 == ~M_E~0;~M_E~0 := 2; 25430#L1249-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 25431#L1254-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 26687#L1259-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 26315#L1264-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 25389#L1269-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 25390#L1274-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 26720#L1279-3 assume !(1 == ~T7_E~0); 25868#L1284-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 25869#L1289-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 25861#L1294-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 25862#L1299-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 26115#L1304-3 assume 1 == ~E_M~0;~E_M~0 := 2; 26116#L1309-3 assume 1 == ~E_1~0;~E_1~0 := 2; 25776#L1314-3 assume 1 == ~E_2~0;~E_2~0 := 2; 25777#L1319-3 assume !(1 == ~E_3~0); 26534#L1324-3 assume 1 == ~E_4~0;~E_4~0 := 2; 25493#L1329-3 assume 1 == ~E_5~0;~E_5~0 := 2; 25494#L1334-3 assume 1 == ~E_6~0;~E_6~0 := 2; 26049#L1339-3 assume 1 == ~E_7~0;~E_7~0 := 2; 26050#L1344-3 assume 1 == ~E_8~0;~E_8~0 := 2; 26268#L1349-3 assume 1 == ~E_9~0;~E_9~0 := 2; 25759#L1354-3 assume 1 == ~E_10~0;~E_10~0 := 2; 25760#L1359-3 assume !(1 == ~E_11~0); 26282#L1364-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 25350#L860-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 25351#L922-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 25977#L923-1 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 25978#L1709 assume !(0 == start_simulation_~tmp~3#1); 25788#L1709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 26554#L860-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 25464#L922-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 25966#L923-2 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 25427#L1664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 25428#L1671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 26245#L1672 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 26627#L1722 assume !(0 != start_simulation_~tmp___0~1#1); 25626#L1690-2 [2021-12-16 10:05:16,538 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:16,539 INFO L85 PathProgramCache]: Analyzing trace with hash -218621314, now seen corresponding path program 1 times [2021-12-16 10:05:16,539 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:16,539 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1927733774] [2021-12-16 10:05:16,539 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:16,539 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:16,547 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:16,559 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:05:16,560 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:16,560 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1927733774] [2021-12-16 10:05:16,560 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1927733774] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:16,560 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:16,560 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:05:16,561 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [910067552] [2021-12-16 10:05:16,561 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:16,561 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:05:16,561 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:16,562 INFO L85 PathProgramCache]: Analyzing trace with hash 1131120385, now seen corresponding path program 1 times [2021-12-16 10:05:16,562 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:16,562 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1745445114] [2021-12-16 10:05:16,562 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:16,562 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:16,571 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:16,608 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:05:16,608 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:16,609 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1745445114] [2021-12-16 10:05:16,609 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1745445114] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:16,609 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:16,609 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:05:16,609 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1598696423] [2021-12-16 10:05:16,609 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:16,610 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:05:16,610 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:05:16,610 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-16 10:05:16,610 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-16 10:05:16,611 INFO L87 Difference]: Start difference. First operand 1571 states and 2327 transitions. cyclomatic complexity: 757 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:16,634 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:05:16,634 INFO L93 Difference]: Finished difference Result 1571 states and 2326 transitions. [2021-12-16 10:05:16,635 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-16 10:05:16,635 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1571 states and 2326 transitions. [2021-12-16 10:05:16,641 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1420 [2021-12-16 10:05:16,648 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1571 states to 1571 states and 2326 transitions. [2021-12-16 10:05:16,648 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1571 [2021-12-16 10:05:16,649 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1571 [2021-12-16 10:05:16,649 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1571 states and 2326 transitions. [2021-12-16 10:05:16,652 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:05:16,652 INFO L681 BuchiCegarLoop]: Abstraction has 1571 states and 2326 transitions. [2021-12-16 10:05:16,653 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1571 states and 2326 transitions. [2021-12-16 10:05:16,667 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1571 to 1571. [2021-12-16 10:05:16,669 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1571 states, 1571 states have (on average 1.4805856142584342) internal successors, (2326), 1570 states have internal predecessors, (2326), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:16,672 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1571 states to 1571 states and 2326 transitions. [2021-12-16 10:05:16,672 INFO L704 BuchiCegarLoop]: Abstraction has 1571 states and 2326 transitions. [2021-12-16 10:05:16,673 INFO L587 BuchiCegarLoop]: Abstraction has 1571 states and 2326 transitions. [2021-12-16 10:05:16,673 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2021-12-16 10:05:16,673 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1571 states and 2326 transitions. [2021-12-16 10:05:16,676 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1420 [2021-12-16 10:05:16,677 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:05:16,677 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:05:16,678 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:16,679 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:16,679 INFO L791 eck$LassoCheckResult]: Stem: 29033#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 29034#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 29574#L1653 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 29575#L785 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 29444#L792 assume 1 == ~m_i~0;~m_st~0 := 0; 29445#L792-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 28452#L797-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 28453#L802-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 29891#L807-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 29418#L812-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 29419#L817-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 29696#L822-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 29697#L827-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 29780#L832-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 29862#L837-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 29863#L842-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 29744#L847-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 29592#L1121 assume !(0 == ~M_E~0); 29347#L1121-2 assume !(0 == ~T1_E~0); 28728#L1126-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 28729#L1131-1 assume !(0 == ~T3_E~0); 28899#L1136-1 assume !(0 == ~T4_E~0); 28995#L1141-1 assume !(0 == ~T5_E~0); 29215#L1146-1 assume !(0 == ~T6_E~0); 29515#L1151-1 assume !(0 == ~T7_E~0); 29055#L1156-1 assume !(0 == ~T8_E~0); 28438#L1161-1 assume !(0 == ~T9_E~0); 28439#L1166-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 28664#L1171-1 assume !(0 == ~T11_E~0); 28665#L1176-1 assume !(0 == ~E_M~0); 29529#L1181-1 assume !(0 == ~E_1~0); 29657#L1186-1 assume !(0 == ~E_2~0); 29707#L1191-1 assume !(0 == ~E_3~0); 28691#L1196-1 assume !(0 == ~E_4~0); 28692#L1201-1 assume !(0 == ~E_5~0); 29900#L1206-1 assume 0 == ~E_6~0;~E_6~0 := 1; 29745#L1211-1 assume !(0 == ~E_7~0); 29746#L1216-1 assume !(0 == ~E_8~0); 28834#L1221-1 assume !(0 == ~E_9~0); 28835#L1226-1 assume !(0 == ~E_10~0); 28534#L1231-1 assume !(0 == ~E_11~0); 28535#L1236-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 29530#L556 assume 1 == ~m_pc~0; 29531#L557 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 28412#L567 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 28413#L568 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 29308#L1391 assume !(0 != activate_threads_~tmp~1#1); 29685#L1391-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 29686#L575 assume !(1 == ~t1_pc~0); 28363#L575-2 is_transmit1_triggered_~__retres1~1#1 := 0; 28364#L586 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 28497#L587 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 28847#L1399 assume !(0 != activate_threads_~tmp___0~0#1); 28804#L1399-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 28805#L594 assume 1 == ~t2_pc~0; 28733#L595 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 28734#L605 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29200#L606 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 28427#L1407 assume !(0 != activate_threads_~tmp___1~0#1); 28428#L1407-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 28486#L613 assume !(1 == ~t3_pc~0); 28605#L613-2 is_transmit3_triggered_~__retres1~3#1 := 0; 28604#L624 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 28530#L625 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 28531#L1415 assume !(0 != activate_threads_~tmp___2~0#1); 29214#L1415-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 28932#L632 assume 1 == ~t4_pc~0; 28933#L633 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 29433#L643 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 29593#L644 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 29901#L1423 assume !(0 != activate_threads_~tmp___3~0#1); 29539#L1423-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 29290#L651 assume 1 == ~t5_pc~0; 29291#L652 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 28618#L662 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 28619#L663 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 29067#L1431 assume !(0 != activate_threads_~tmp___4~0#1); 28635#L1431-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 28636#L670 assume !(1 == ~t6_pc~0); 29727#L670-2 is_transmit6_triggered_~__retres1~6#1 := 0; 28981#L681 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 28982#L682 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 29823#L1439 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 29255#L1439-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 29256#L689 assume 1 == ~t7_pc~0; 29897#L690 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 29366#L700 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 29367#L701 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 29742#L1447 assume !(0 != activate_threads_~tmp___6~0#1); 29158#L1447-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 29159#L708 assume !(1 == ~t8_pc~0); 28724#L708-2 is_transmit8_triggered_~__retres1~8#1 := 0; 28725#L719 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 29822#L720 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 29807#L1455 assume !(0 != activate_threads_~tmp___7~0#1); 28789#L1455-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 28790#L727 assume 1 == ~t9_pc~0; 28912#L728 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 28488#L738 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 29904#L739 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 29905#L1463 assume !(0 != activate_threads_~tmp___8~0#1); 29892#L1463-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 28843#L746 assume !(1 == ~t10_pc~0); 28844#L746-2 is_transmit10_triggered_~__retres1~10#1 := 0; 29492#L757 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 29608#L758 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 29816#L1471 assume !(0 != activate_threads_~tmp___9~0#1); 29689#L1471-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 29004#L765 assume 1 == ~t11_pc~0; 29005#L766 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 29210#L776 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 28377#L777 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 28378#L1479 assume !(0 != activate_threads_~tmp___10~0#1); 29726#L1479-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 29804#L1249 assume !(1 == ~M_E~0); 29437#L1249-2 assume !(1 == ~T1_E~0); 29087#L1254-1 assume !(1 == ~T2_E~0); 28423#L1259-1 assume !(1 == ~T3_E~0); 28405#L1264-1 assume !(1 == ~T4_E~0); 28406#L1269-1 assume !(1 == ~T5_E~0); 29923#L1274-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 29871#L1279-1 assume !(1 == ~T7_E~0); 28606#L1284-1 assume !(1 == ~T8_E~0); 28607#L1289-1 assume !(1 == ~T9_E~0); 29137#L1294-1 assume !(1 == ~T10_E~0); 29138#L1299-1 assume !(1 == ~T11_E~0); 29147#L1304-1 assume !(1 == ~E_M~0); 29917#L1309-1 assume !(1 == ~E_1~0); 29920#L1314-1 assume 1 == ~E_2~0;~E_2~0 := 2; 28553#L1319-1 assume !(1 == ~E_3~0); 28554#L1324-1 assume !(1 == ~E_4~0); 28686#L1329-1 assume !(1 == ~E_5~0); 28687#L1334-1 assume !(1 == ~E_6~0); 29765#L1339-1 assume !(1 == ~E_7~0); 29842#L1344-1 assume !(1 == ~E_8~0); 29843#L1349-1 assume !(1 == ~E_9~0); 29270#L1354-1 assume 1 == ~E_10~0;~E_10~0 := 2; 29271#L1359-1 assume !(1 == ~E_11~0); 29630#L1364-1 assume { :end_inline_reset_delta_events } true; 28775#L1690-2 [2021-12-16 10:05:16,679 INFO L793 eck$LassoCheckResult]: Loop: 28775#L1690-2 assume !false; 28776#L1691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 28661#L1096 assume !false; 29639#L933 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 28507#L860 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 28508#L922 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 29533#L923 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 29002#L937 assume !(0 != eval_~tmp~0#1); 29003#L1111 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 29473#L785-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 28977#L1121-3 assume 0 == ~M_E~0;~M_E~0 := 1; 28978#L1121-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 29893#L1126-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 29185#L1131-3 assume !(0 == ~T3_E~0); 29186#L1136-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 29924#L1141-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 29540#L1146-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 28722#L1151-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 28723#L1156-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 29837#L1161-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 29348#L1166-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 29349#L1171-3 assume !(0 == ~T11_E~0); 29394#L1176-3 assume 0 == ~E_M~0;~E_M~0 := 1; 28771#L1181-3 assume 0 == ~E_1~0;~E_1~0 := 1; 28772#L1186-3 assume 0 == ~E_2~0;~E_2~0 := 1; 29475#L1191-3 assume 0 == ~E_3~0;~E_3~0 := 1; 29476#L1196-3 assume 0 == ~E_4~0;~E_4~0 := 1; 29666#L1201-3 assume 0 == ~E_5~0;~E_5~0 := 1; 29667#L1206-3 assume 0 == ~E_6~0;~E_6~0 := 1; 29372#L1211-3 assume !(0 == ~E_7~0); 28684#L1216-3 assume 0 == ~E_8~0;~E_8~0 := 1; 28685#L1221-3 assume 0 == ~E_9~0;~E_9~0 := 1; 29098#L1226-3 assume 0 == ~E_10~0;~E_10~0 := 1; 28741#L1231-3 assume 0 == ~E_11~0;~E_11~0 := 1; 28742#L1236-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 28962#L556-39 assume 1 == ~m_pc~0; 29483#L557-13 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 29450#L567-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 28841#L568-13 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 28842#L1391-39 assume !(0 != activate_threads_~tmp~1#1); 29014#L1391-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 29408#L575-39 assume 1 == ~t1_pc~0; 29409#L576-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 29674#L586-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 29535#L587-13 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 29536#L1399-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 29383#L1399-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 29384#L594-39 assume !(1 == ~t2_pc~0); 29595#L594-41 is_transmit2_triggered_~__retres1~2#1 := 0; 29386#L605-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29387#L606-13 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 29809#L1407-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 28900#L1407-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 28901#L613-39 assume 1 == ~t3_pc~0; 29786#L614-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 28383#L624-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 28384#L625-13 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 29142#L1415-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 28482#L1415-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 28483#L632-39 assume 1 == ~t4_pc~0; 29754#L633-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 29068#L643-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 29069#L644-13 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 29622#L1423-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 29753#L1423-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 28752#L651-39 assume 1 == ~t5_pc~0; 28753#L652-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 28515#L662-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 29741#L663-13 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 29848#L1431-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 29886#L1431-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 29906#L670-39 assume 1 == ~t6_pc~0; 29907#L671-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 28429#L681-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 28430#L682-13 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 28498#L1439-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 29095#L1439-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 29096#L689-39 assume !(1 == ~t7_pc~0); 29219#L689-41 is_transmit7_triggered_~__retres1~7#1 := 0; 29220#L700-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 28754#L701-13 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 28755#L1447-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 28622#L1447-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 28623#L708-39 assume !(1 == ~t8_pc~0); 28561#L708-41 is_transmit8_triggered_~__retres1~8#1 := 0; 28560#L719-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 28668#L720-13 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 28669#L1455-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 29549#L1455-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 29041#L727-39 assume !(1 == ~t9_pc~0); 29042#L727-41 is_transmit9_triggered_~__retres1~9#1 := 0; 28819#L738-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 28820#L739-13 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 29769#L1463-39 assume !(0 != activate_threads_~tmp___8~0#1); 29598#L1463-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 29599#L746-39 assume 1 == ~t10_pc~0; 29568#L747-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 29569#L757-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 29834#L758-13 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 29304#L1471-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 29305#L1471-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 29717#L765-39 assume 1 == ~t11_pc~0; 28433#L766-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 28435#L776-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 29617#L777-13 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 28773#L1479-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 28774#L1479-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 29341#L1249-3 assume 1 == ~M_E~0;~M_E~0 := 2; 28579#L1249-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 28580#L1254-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 29836#L1259-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 29464#L1264-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 28538#L1269-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 28539#L1274-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 29869#L1279-3 assume !(1 == ~T7_E~0); 29017#L1284-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 29018#L1289-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 29012#L1294-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 29013#L1299-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 29264#L1304-3 assume 1 == ~E_M~0;~E_M~0 := 2; 29265#L1309-3 assume 1 == ~E_1~0;~E_1~0 := 2; 28929#L1314-3 assume 1 == ~E_2~0;~E_2~0 := 2; 28930#L1319-3 assume !(1 == ~E_3~0); 29683#L1324-3 assume 1 == ~E_4~0;~E_4~0 := 2; 28648#L1329-3 assume 1 == ~E_5~0;~E_5~0 := 2; 28649#L1334-3 assume 1 == ~E_6~0;~E_6~0 := 2; 29198#L1339-3 assume 1 == ~E_7~0;~E_7~0 := 2; 29199#L1344-3 assume 1 == ~E_8~0;~E_8~0 := 2; 29417#L1349-3 assume 1 == ~E_9~0;~E_9~0 := 2; 28908#L1354-3 assume 1 == ~E_10~0;~E_10~0 := 2; 28909#L1359-3 assume !(1 == ~E_11~0); 29432#L1364-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 28499#L860-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 28500#L922-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 29126#L923-1 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 29127#L1709 assume !(0 == start_simulation_~tmp~3#1); 28937#L1709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 29703#L860-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 28613#L922-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 29115#L923-2 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 28576#L1664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 28577#L1671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 29395#L1672 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 29776#L1722 assume !(0 != start_simulation_~tmp___0~1#1); 28775#L1690-2 [2021-12-16 10:05:16,680 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:16,680 INFO L85 PathProgramCache]: Analyzing trace with hash 215884284, now seen corresponding path program 1 times [2021-12-16 10:05:16,680 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:16,680 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [615670692] [2021-12-16 10:05:16,681 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:16,681 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:16,688 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:16,702 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:05:16,702 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:16,702 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [615670692] [2021-12-16 10:05:16,702 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [615670692] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:16,703 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:16,703 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:05:16,703 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [814394233] [2021-12-16 10:05:16,704 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:16,704 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:05:16,705 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:16,705 INFO L85 PathProgramCache]: Analyzing trace with hash 1244851136, now seen corresponding path program 1 times [2021-12-16 10:05:16,705 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:16,708 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1249698156] [2021-12-16 10:05:16,708 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:16,708 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:16,717 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:16,737 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:05:16,737 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:16,737 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1249698156] [2021-12-16 10:05:16,738 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1249698156] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:16,738 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:16,738 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:05:16,738 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [645280318] [2021-12-16 10:05:16,738 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:16,738 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:05:16,739 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:05:16,739 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-16 10:05:16,740 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-16 10:05:16,740 INFO L87 Difference]: Start difference. First operand 1571 states and 2326 transitions. cyclomatic complexity: 756 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:16,770 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:05:16,771 INFO L93 Difference]: Finished difference Result 1571 states and 2325 transitions. [2021-12-16 10:05:16,771 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-16 10:05:16,772 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1571 states and 2325 transitions. [2021-12-16 10:05:16,777 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1420 [2021-12-16 10:05:16,782 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1571 states to 1571 states and 2325 transitions. [2021-12-16 10:05:16,782 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1571 [2021-12-16 10:05:16,783 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1571 [2021-12-16 10:05:16,784 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1571 states and 2325 transitions. [2021-12-16 10:05:16,785 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:05:16,786 INFO L681 BuchiCegarLoop]: Abstraction has 1571 states and 2325 transitions. [2021-12-16 10:05:16,787 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1571 states and 2325 transitions. [2021-12-16 10:05:16,800 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1571 to 1571. [2021-12-16 10:05:16,802 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1571 states, 1571 states have (on average 1.4799490770210058) internal successors, (2325), 1570 states have internal predecessors, (2325), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:16,805 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1571 states to 1571 states and 2325 transitions. [2021-12-16 10:05:16,805 INFO L704 BuchiCegarLoop]: Abstraction has 1571 states and 2325 transitions. [2021-12-16 10:05:16,805 INFO L587 BuchiCegarLoop]: Abstraction has 1571 states and 2325 transitions. [2021-12-16 10:05:16,805 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2021-12-16 10:05:16,806 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1571 states and 2325 transitions. [2021-12-16 10:05:16,809 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1420 [2021-12-16 10:05:16,809 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:05:16,809 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:05:16,811 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:16,811 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:16,811 INFO L791 eck$LassoCheckResult]: Stem: 32182#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 32183#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 32723#L1653 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 32724#L785 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 32593#L792 assume 1 == ~m_i~0;~m_st~0 := 0; 32594#L792-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 31601#L797-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 31602#L802-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 33040#L807-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 32567#L812-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 32568#L817-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 32845#L822-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 32846#L827-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 32929#L832-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 33011#L837-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 33012#L842-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 32893#L847-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 32741#L1121 assume !(0 == ~M_E~0); 32496#L1121-2 assume !(0 == ~T1_E~0); 31877#L1126-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 31878#L1131-1 assume !(0 == ~T3_E~0); 32048#L1136-1 assume !(0 == ~T4_E~0); 32144#L1141-1 assume !(0 == ~T5_E~0); 32364#L1146-1 assume !(0 == ~T6_E~0); 32664#L1151-1 assume !(0 == ~T7_E~0); 32204#L1156-1 assume !(0 == ~T8_E~0); 31587#L1161-1 assume !(0 == ~T9_E~0); 31588#L1166-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 31813#L1171-1 assume !(0 == ~T11_E~0); 31814#L1176-1 assume !(0 == ~E_M~0); 32678#L1181-1 assume !(0 == ~E_1~0); 32806#L1186-1 assume !(0 == ~E_2~0); 32856#L1191-1 assume !(0 == ~E_3~0); 31840#L1196-1 assume !(0 == ~E_4~0); 31841#L1201-1 assume !(0 == ~E_5~0); 33049#L1206-1 assume 0 == ~E_6~0;~E_6~0 := 1; 32894#L1211-1 assume !(0 == ~E_7~0); 32895#L1216-1 assume !(0 == ~E_8~0); 31983#L1221-1 assume !(0 == ~E_9~0); 31984#L1226-1 assume !(0 == ~E_10~0); 31683#L1231-1 assume !(0 == ~E_11~0); 31684#L1236-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 32679#L556 assume 1 == ~m_pc~0; 32680#L557 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 31561#L567 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 31562#L568 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 32457#L1391 assume !(0 != activate_threads_~tmp~1#1); 32834#L1391-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 32835#L575 assume !(1 == ~t1_pc~0); 31512#L575-2 is_transmit1_triggered_~__retres1~1#1 := 0; 31513#L586 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 31646#L587 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 31996#L1399 assume !(0 != activate_threads_~tmp___0~0#1); 31953#L1399-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 31954#L594 assume 1 == ~t2_pc~0; 31882#L595 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 31883#L605 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 32349#L606 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 31576#L1407 assume !(0 != activate_threads_~tmp___1~0#1); 31577#L1407-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 31635#L613 assume !(1 == ~t3_pc~0); 31754#L613-2 is_transmit3_triggered_~__retres1~3#1 := 0; 31753#L624 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 31679#L625 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 31680#L1415 assume !(0 != activate_threads_~tmp___2~0#1); 32363#L1415-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 32081#L632 assume 1 == ~t4_pc~0; 32082#L633 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 32582#L643 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 32742#L644 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 33050#L1423 assume !(0 != activate_threads_~tmp___3~0#1); 32688#L1423-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 32439#L651 assume 1 == ~t5_pc~0; 32440#L652 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 31767#L662 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 31768#L663 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 32216#L1431 assume !(0 != activate_threads_~tmp___4~0#1); 31784#L1431-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 31785#L670 assume !(1 == ~t6_pc~0); 32876#L670-2 is_transmit6_triggered_~__retres1~6#1 := 0; 32130#L681 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 32131#L682 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 32972#L1439 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 32404#L1439-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 32405#L689 assume 1 == ~t7_pc~0; 33046#L690 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 32515#L700 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 32516#L701 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 32891#L1447 assume !(0 != activate_threads_~tmp___6~0#1); 32307#L1447-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 32308#L708 assume !(1 == ~t8_pc~0); 31873#L708-2 is_transmit8_triggered_~__retres1~8#1 := 0; 31874#L719 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 32971#L720 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 32956#L1455 assume !(0 != activate_threads_~tmp___7~0#1); 31938#L1455-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 31939#L727 assume 1 == ~t9_pc~0; 32061#L728 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 31637#L738 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 33053#L739 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 33054#L1463 assume !(0 != activate_threads_~tmp___8~0#1); 33041#L1463-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 31992#L746 assume !(1 == ~t10_pc~0); 31993#L746-2 is_transmit10_triggered_~__retres1~10#1 := 0; 32641#L757 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 32757#L758 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 32965#L1471 assume !(0 != activate_threads_~tmp___9~0#1); 32838#L1471-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 32153#L765 assume 1 == ~t11_pc~0; 32154#L766 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 32359#L776 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 31526#L777 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 31527#L1479 assume !(0 != activate_threads_~tmp___10~0#1); 32875#L1479-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 32953#L1249 assume !(1 == ~M_E~0); 32586#L1249-2 assume !(1 == ~T1_E~0); 32236#L1254-1 assume !(1 == ~T2_E~0); 31572#L1259-1 assume !(1 == ~T3_E~0); 31554#L1264-1 assume !(1 == ~T4_E~0); 31555#L1269-1 assume !(1 == ~T5_E~0); 33072#L1274-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 33020#L1279-1 assume !(1 == ~T7_E~0); 31755#L1284-1 assume !(1 == ~T8_E~0); 31756#L1289-1 assume !(1 == ~T9_E~0); 32286#L1294-1 assume !(1 == ~T10_E~0); 32287#L1299-1 assume !(1 == ~T11_E~0); 32296#L1304-1 assume !(1 == ~E_M~0); 33066#L1309-1 assume !(1 == ~E_1~0); 33069#L1314-1 assume 1 == ~E_2~0;~E_2~0 := 2; 31702#L1319-1 assume !(1 == ~E_3~0); 31703#L1324-1 assume !(1 == ~E_4~0); 31835#L1329-1 assume !(1 == ~E_5~0); 31836#L1334-1 assume !(1 == ~E_6~0); 32914#L1339-1 assume !(1 == ~E_7~0); 32991#L1344-1 assume !(1 == ~E_8~0); 32992#L1349-1 assume !(1 == ~E_9~0); 32419#L1354-1 assume 1 == ~E_10~0;~E_10~0 := 2; 32420#L1359-1 assume !(1 == ~E_11~0); 32779#L1364-1 assume { :end_inline_reset_delta_events } true; 31924#L1690-2 [2021-12-16 10:05:16,812 INFO L793 eck$LassoCheckResult]: Loop: 31924#L1690-2 assume !false; 31925#L1691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 31810#L1096 assume !false; 32788#L933 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 31656#L860 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 31657#L922 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 32682#L923 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 32151#L937 assume !(0 != eval_~tmp~0#1); 32152#L1111 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 32622#L785-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 32126#L1121-3 assume 0 == ~M_E~0;~M_E~0 := 1; 32127#L1121-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 33042#L1126-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 32334#L1131-3 assume !(0 == ~T3_E~0); 32335#L1136-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 33073#L1141-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 32689#L1146-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 31871#L1151-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 31872#L1156-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 32986#L1161-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 32497#L1166-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 32498#L1171-3 assume !(0 == ~T11_E~0); 32543#L1176-3 assume 0 == ~E_M~0;~E_M~0 := 1; 31920#L1181-3 assume 0 == ~E_1~0;~E_1~0 := 1; 31921#L1186-3 assume 0 == ~E_2~0;~E_2~0 := 1; 32624#L1191-3 assume 0 == ~E_3~0;~E_3~0 := 1; 32625#L1196-3 assume 0 == ~E_4~0;~E_4~0 := 1; 32815#L1201-3 assume 0 == ~E_5~0;~E_5~0 := 1; 32816#L1206-3 assume 0 == ~E_6~0;~E_6~0 := 1; 32521#L1211-3 assume !(0 == ~E_7~0); 31833#L1216-3 assume 0 == ~E_8~0;~E_8~0 := 1; 31834#L1221-3 assume 0 == ~E_9~0;~E_9~0 := 1; 32247#L1226-3 assume 0 == ~E_10~0;~E_10~0 := 1; 31890#L1231-3 assume 0 == ~E_11~0;~E_11~0 := 1; 31891#L1236-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 32111#L556-39 assume 1 == ~m_pc~0; 32632#L557-13 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 32599#L567-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 31990#L568-13 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 31991#L1391-39 assume !(0 != activate_threads_~tmp~1#1); 32163#L1391-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 32557#L575-39 assume 1 == ~t1_pc~0; 32558#L576-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 32823#L586-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 32684#L587-13 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 32685#L1399-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 32532#L1399-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 32533#L594-39 assume !(1 == ~t2_pc~0); 32744#L594-41 is_transmit2_triggered_~__retres1~2#1 := 0; 32535#L605-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 32536#L606-13 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 32958#L1407-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 32049#L1407-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 32050#L613-39 assume 1 == ~t3_pc~0; 32935#L614-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 31532#L624-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 31533#L625-13 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 32291#L1415-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 31631#L1415-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 31632#L632-39 assume 1 == ~t4_pc~0; 32903#L633-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 32217#L643-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 32218#L644-13 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 32771#L1423-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 32902#L1423-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 31901#L651-39 assume 1 == ~t5_pc~0; 31902#L652-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 31664#L662-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 32890#L663-13 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 32997#L1431-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 33035#L1431-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 33055#L670-39 assume 1 == ~t6_pc~0; 33056#L671-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 31578#L681-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 31579#L682-13 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 31647#L1439-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 32244#L1439-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 32245#L689-39 assume !(1 == ~t7_pc~0); 32368#L689-41 is_transmit7_triggered_~__retres1~7#1 := 0; 32369#L700-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 31903#L701-13 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 31904#L1447-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 31771#L1447-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 31772#L708-39 assume 1 == ~t8_pc~0; 31708#L709-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 31709#L719-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 31817#L720-13 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 31818#L1455-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 32698#L1455-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 32190#L727-39 assume 1 == ~t9_pc~0; 32192#L728-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 31968#L738-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 31969#L739-13 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 32918#L1463-39 assume !(0 != activate_threads_~tmp___8~0#1); 32747#L1463-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 32748#L746-39 assume 1 == ~t10_pc~0; 32717#L747-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 32718#L757-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 32983#L758-13 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 32453#L1471-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 32454#L1471-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 32866#L765-39 assume 1 == ~t11_pc~0; 31582#L766-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 31584#L776-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 32766#L777-13 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 31922#L1479-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 31923#L1479-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 32490#L1249-3 assume 1 == ~M_E~0;~M_E~0 := 2; 31728#L1249-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 31729#L1254-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 32985#L1259-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 32613#L1264-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 31687#L1269-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 31688#L1274-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 33018#L1279-3 assume !(1 == ~T7_E~0); 32166#L1284-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 32167#L1289-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 32161#L1294-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 32162#L1299-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 32413#L1304-3 assume 1 == ~E_M~0;~E_M~0 := 2; 32414#L1309-3 assume 1 == ~E_1~0;~E_1~0 := 2; 32078#L1314-3 assume 1 == ~E_2~0;~E_2~0 := 2; 32079#L1319-3 assume !(1 == ~E_3~0); 32832#L1324-3 assume 1 == ~E_4~0;~E_4~0 := 2; 31797#L1329-3 assume 1 == ~E_5~0;~E_5~0 := 2; 31798#L1334-3 assume 1 == ~E_6~0;~E_6~0 := 2; 32347#L1339-3 assume 1 == ~E_7~0;~E_7~0 := 2; 32348#L1344-3 assume 1 == ~E_8~0;~E_8~0 := 2; 32566#L1349-3 assume 1 == ~E_9~0;~E_9~0 := 2; 32057#L1354-3 assume 1 == ~E_10~0;~E_10~0 := 2; 32058#L1359-3 assume !(1 == ~E_11~0); 32581#L1364-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 31648#L860-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 31649#L922-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 32275#L923-1 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 32276#L1709 assume !(0 == start_simulation_~tmp~3#1); 32086#L1709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 32852#L860-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 31762#L922-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 32264#L923-2 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 31725#L1664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 31726#L1671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 32544#L1672 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 32925#L1722 assume !(0 != start_simulation_~tmp___0~1#1); 31924#L1690-2 [2021-12-16 10:05:16,812 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:16,812 INFO L85 PathProgramCache]: Analyzing trace with hash 922480890, now seen corresponding path program 1 times [2021-12-16 10:05:16,812 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:16,813 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1688498739] [2021-12-16 10:05:16,813 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:16,813 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:16,826 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:16,844 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:05:16,845 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:16,845 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1688498739] [2021-12-16 10:05:16,845 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1688498739] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:16,845 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:16,845 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:05:16,845 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [591930720] [2021-12-16 10:05:16,845 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:16,846 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:05:16,846 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:16,846 INFO L85 PathProgramCache]: Analyzing trace with hash 1324447614, now seen corresponding path program 1 times [2021-12-16 10:05:16,846 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:16,847 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1787699729] [2021-12-16 10:05:16,847 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:16,847 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:16,855 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:16,876 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:05:16,876 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:16,876 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1787699729] [2021-12-16 10:05:16,876 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1787699729] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:16,876 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:16,876 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:05:16,877 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [596785586] [2021-12-16 10:05:16,877 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:16,877 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:05:16,877 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:05:16,878 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-16 10:05:16,878 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-16 10:05:16,878 INFO L87 Difference]: Start difference. First operand 1571 states and 2325 transitions. cyclomatic complexity: 755 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:16,898 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:05:16,898 INFO L93 Difference]: Finished difference Result 1571 states and 2324 transitions. [2021-12-16 10:05:16,899 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-16 10:05:16,900 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1571 states and 2324 transitions. [2021-12-16 10:05:16,904 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1420 [2021-12-16 10:05:16,909 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1571 states to 1571 states and 2324 transitions. [2021-12-16 10:05:16,909 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1571 [2021-12-16 10:05:16,910 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1571 [2021-12-16 10:05:16,910 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1571 states and 2324 transitions. [2021-12-16 10:05:16,912 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:05:16,912 INFO L681 BuchiCegarLoop]: Abstraction has 1571 states and 2324 transitions. [2021-12-16 10:05:16,913 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1571 states and 2324 transitions. [2021-12-16 10:05:16,930 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1571 to 1571. [2021-12-16 10:05:16,932 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1571 states, 1571 states have (on average 1.4793125397835774) internal successors, (2324), 1570 states have internal predecessors, (2324), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:16,936 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1571 states to 1571 states and 2324 transitions. [2021-12-16 10:05:16,936 INFO L704 BuchiCegarLoop]: Abstraction has 1571 states and 2324 transitions. [2021-12-16 10:05:16,936 INFO L587 BuchiCegarLoop]: Abstraction has 1571 states and 2324 transitions. [2021-12-16 10:05:16,936 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2021-12-16 10:05:16,936 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1571 states and 2324 transitions. [2021-12-16 10:05:16,939 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1420 [2021-12-16 10:05:16,940 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:05:16,940 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:05:16,941 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:16,941 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:16,941 INFO L791 eck$LassoCheckResult]: Stem: 35331#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 35332#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 35872#L1653 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 35873#L785 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 35742#L792 assume 1 == ~m_i~0;~m_st~0 := 0; 35743#L792-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 34750#L797-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 34751#L802-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 36189#L807-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 35716#L812-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 35717#L817-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 35994#L822-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 35995#L827-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 36078#L832-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 36160#L837-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 36161#L842-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 36042#L847-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 35890#L1121 assume !(0 == ~M_E~0); 35645#L1121-2 assume !(0 == ~T1_E~0); 35026#L1126-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 35027#L1131-1 assume !(0 == ~T3_E~0); 35197#L1136-1 assume !(0 == ~T4_E~0); 35293#L1141-1 assume !(0 == ~T5_E~0); 35513#L1146-1 assume !(0 == ~T6_E~0); 35813#L1151-1 assume !(0 == ~T7_E~0); 35353#L1156-1 assume !(0 == ~T8_E~0); 34736#L1161-1 assume !(0 == ~T9_E~0); 34737#L1166-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 34962#L1171-1 assume !(0 == ~T11_E~0); 34963#L1176-1 assume !(0 == ~E_M~0); 35827#L1181-1 assume !(0 == ~E_1~0); 35955#L1186-1 assume !(0 == ~E_2~0); 36005#L1191-1 assume !(0 == ~E_3~0); 34989#L1196-1 assume !(0 == ~E_4~0); 34990#L1201-1 assume !(0 == ~E_5~0); 36198#L1206-1 assume 0 == ~E_6~0;~E_6~0 := 1; 36043#L1211-1 assume !(0 == ~E_7~0); 36044#L1216-1 assume !(0 == ~E_8~0); 35132#L1221-1 assume !(0 == ~E_9~0); 35133#L1226-1 assume !(0 == ~E_10~0); 34832#L1231-1 assume !(0 == ~E_11~0); 34833#L1236-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 35828#L556 assume 1 == ~m_pc~0; 35829#L557 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 34710#L567 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 34711#L568 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 35606#L1391 assume !(0 != activate_threads_~tmp~1#1); 35983#L1391-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 35984#L575 assume !(1 == ~t1_pc~0); 34661#L575-2 is_transmit1_triggered_~__retres1~1#1 := 0; 34662#L586 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 34795#L587 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 35145#L1399 assume !(0 != activate_threads_~tmp___0~0#1); 35102#L1399-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 35103#L594 assume 1 == ~t2_pc~0; 35031#L595 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 35032#L605 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 35498#L606 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 34725#L1407 assume !(0 != activate_threads_~tmp___1~0#1); 34726#L1407-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 34784#L613 assume !(1 == ~t3_pc~0); 34903#L613-2 is_transmit3_triggered_~__retres1~3#1 := 0; 34902#L624 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 34828#L625 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 34829#L1415 assume !(0 != activate_threads_~tmp___2~0#1); 35512#L1415-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 35230#L632 assume 1 == ~t4_pc~0; 35231#L633 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 35731#L643 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 35891#L644 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 36199#L1423 assume !(0 != activate_threads_~tmp___3~0#1); 35837#L1423-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 35588#L651 assume 1 == ~t5_pc~0; 35589#L652 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 34916#L662 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 34917#L663 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 35365#L1431 assume !(0 != activate_threads_~tmp___4~0#1); 34933#L1431-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 34934#L670 assume !(1 == ~t6_pc~0); 36025#L670-2 is_transmit6_triggered_~__retres1~6#1 := 0; 35279#L681 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 35280#L682 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 36121#L1439 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 35553#L1439-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 35554#L689 assume 1 == ~t7_pc~0; 36195#L690 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 35664#L700 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 35665#L701 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 36040#L1447 assume !(0 != activate_threads_~tmp___6~0#1); 35456#L1447-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 35457#L708 assume !(1 == ~t8_pc~0); 35022#L708-2 is_transmit8_triggered_~__retres1~8#1 := 0; 35023#L719 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 36120#L720 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 36105#L1455 assume !(0 != activate_threads_~tmp___7~0#1); 35087#L1455-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 35088#L727 assume 1 == ~t9_pc~0; 35210#L728 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 34786#L738 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 36202#L739 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 36203#L1463 assume !(0 != activate_threads_~tmp___8~0#1); 36190#L1463-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 35141#L746 assume !(1 == ~t10_pc~0); 35142#L746-2 is_transmit10_triggered_~__retres1~10#1 := 0; 35790#L757 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 35906#L758 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 36114#L1471 assume !(0 != activate_threads_~tmp___9~0#1); 35987#L1471-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 35302#L765 assume 1 == ~t11_pc~0; 35303#L766 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 35508#L776 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 34675#L777 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 34676#L1479 assume !(0 != activate_threads_~tmp___10~0#1); 36024#L1479-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 36102#L1249 assume !(1 == ~M_E~0); 35735#L1249-2 assume !(1 == ~T1_E~0); 35385#L1254-1 assume !(1 == ~T2_E~0); 34721#L1259-1 assume !(1 == ~T3_E~0); 34703#L1264-1 assume !(1 == ~T4_E~0); 34704#L1269-1 assume !(1 == ~T5_E~0); 36221#L1274-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 36169#L1279-1 assume !(1 == ~T7_E~0); 34904#L1284-1 assume !(1 == ~T8_E~0); 34905#L1289-1 assume !(1 == ~T9_E~0); 35435#L1294-1 assume !(1 == ~T10_E~0); 35436#L1299-1 assume !(1 == ~T11_E~0); 35445#L1304-1 assume !(1 == ~E_M~0); 36215#L1309-1 assume !(1 == ~E_1~0); 36218#L1314-1 assume 1 == ~E_2~0;~E_2~0 := 2; 34851#L1319-1 assume !(1 == ~E_3~0); 34852#L1324-1 assume !(1 == ~E_4~0); 34984#L1329-1 assume !(1 == ~E_5~0); 34985#L1334-1 assume !(1 == ~E_6~0); 36063#L1339-1 assume !(1 == ~E_7~0); 36140#L1344-1 assume !(1 == ~E_8~0); 36141#L1349-1 assume !(1 == ~E_9~0); 35568#L1354-1 assume 1 == ~E_10~0;~E_10~0 := 2; 35569#L1359-1 assume !(1 == ~E_11~0); 35928#L1364-1 assume { :end_inline_reset_delta_events } true; 35073#L1690-2 [2021-12-16 10:05:16,942 INFO L793 eck$LassoCheckResult]: Loop: 35073#L1690-2 assume !false; 35074#L1691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 34959#L1096 assume !false; 35937#L933 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 34805#L860 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 34806#L922 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 35831#L923 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 35300#L937 assume !(0 != eval_~tmp~0#1); 35301#L1111 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 35771#L785-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 35275#L1121-3 assume 0 == ~M_E~0;~M_E~0 := 1; 35276#L1121-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 36191#L1126-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 35483#L1131-3 assume !(0 == ~T3_E~0); 35484#L1136-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 36222#L1141-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 35838#L1146-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 35020#L1151-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 35021#L1156-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 36135#L1161-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 35646#L1166-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 35647#L1171-3 assume !(0 == ~T11_E~0); 35692#L1176-3 assume 0 == ~E_M~0;~E_M~0 := 1; 35069#L1181-3 assume 0 == ~E_1~0;~E_1~0 := 1; 35070#L1186-3 assume 0 == ~E_2~0;~E_2~0 := 1; 35773#L1191-3 assume 0 == ~E_3~0;~E_3~0 := 1; 35774#L1196-3 assume 0 == ~E_4~0;~E_4~0 := 1; 35964#L1201-3 assume 0 == ~E_5~0;~E_5~0 := 1; 35965#L1206-3 assume 0 == ~E_6~0;~E_6~0 := 1; 35670#L1211-3 assume !(0 == ~E_7~0); 34982#L1216-3 assume 0 == ~E_8~0;~E_8~0 := 1; 34983#L1221-3 assume 0 == ~E_9~0;~E_9~0 := 1; 35396#L1226-3 assume 0 == ~E_10~0;~E_10~0 := 1; 35039#L1231-3 assume 0 == ~E_11~0;~E_11~0 := 1; 35040#L1236-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 35260#L556-39 assume 1 == ~m_pc~0; 35781#L557-13 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 35748#L567-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 35139#L568-13 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 35140#L1391-39 assume !(0 != activate_threads_~tmp~1#1); 35312#L1391-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 35706#L575-39 assume 1 == ~t1_pc~0; 35707#L576-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 35972#L586-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 35833#L587-13 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 35834#L1399-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 35681#L1399-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 35682#L594-39 assume !(1 == ~t2_pc~0); 35893#L594-41 is_transmit2_triggered_~__retres1~2#1 := 0; 35684#L605-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 35685#L606-13 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 36107#L1407-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 35198#L1407-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 35199#L613-39 assume 1 == ~t3_pc~0; 36084#L614-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 34681#L624-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 34682#L625-13 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 35440#L1415-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 34780#L1415-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 34781#L632-39 assume 1 == ~t4_pc~0; 36052#L633-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 35366#L643-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 35367#L644-13 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 35920#L1423-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 36051#L1423-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 35050#L651-39 assume 1 == ~t5_pc~0; 35051#L652-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 34813#L662-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 36039#L663-13 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 36146#L1431-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 36184#L1431-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 36204#L670-39 assume !(1 == ~t6_pc~0); 35783#L670-41 is_transmit6_triggered_~__retres1~6#1 := 0; 34727#L681-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 34728#L682-13 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 34796#L1439-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 35393#L1439-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 35394#L689-39 assume 1 == ~t7_pc~0; 35616#L690-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 35518#L700-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 35052#L701-13 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 35053#L1447-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 34920#L1447-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 34921#L708-39 assume 1 == ~t8_pc~0; 34857#L709-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 34858#L719-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 34966#L720-13 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 34967#L1455-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 35847#L1455-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 35339#L727-39 assume !(1 == ~t9_pc~0); 35340#L727-41 is_transmit9_triggered_~__retres1~9#1 := 0; 35117#L738-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 35118#L739-13 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 36067#L1463-39 assume !(0 != activate_threads_~tmp___8~0#1); 35896#L1463-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 35897#L746-39 assume 1 == ~t10_pc~0; 35866#L747-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 35867#L757-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 36132#L758-13 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 35602#L1471-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 35603#L1471-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 36015#L765-39 assume 1 == ~t11_pc~0; 34731#L766-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 34733#L776-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 35915#L777-13 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 35071#L1479-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 35072#L1479-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 35639#L1249-3 assume 1 == ~M_E~0;~M_E~0 := 2; 34877#L1249-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 34878#L1254-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 36134#L1259-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 35762#L1264-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 34836#L1269-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 34837#L1274-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 36167#L1279-3 assume !(1 == ~T7_E~0); 35315#L1284-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 35316#L1289-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 35310#L1294-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 35311#L1299-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 35562#L1304-3 assume 1 == ~E_M~0;~E_M~0 := 2; 35563#L1309-3 assume 1 == ~E_1~0;~E_1~0 := 2; 35227#L1314-3 assume 1 == ~E_2~0;~E_2~0 := 2; 35228#L1319-3 assume !(1 == ~E_3~0); 35981#L1324-3 assume 1 == ~E_4~0;~E_4~0 := 2; 34946#L1329-3 assume 1 == ~E_5~0;~E_5~0 := 2; 34947#L1334-3 assume 1 == ~E_6~0;~E_6~0 := 2; 35496#L1339-3 assume 1 == ~E_7~0;~E_7~0 := 2; 35497#L1344-3 assume 1 == ~E_8~0;~E_8~0 := 2; 35715#L1349-3 assume 1 == ~E_9~0;~E_9~0 := 2; 35206#L1354-3 assume 1 == ~E_10~0;~E_10~0 := 2; 35207#L1359-3 assume !(1 == ~E_11~0); 35730#L1364-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 34797#L860-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 34798#L922-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 35424#L923-1 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 35425#L1709 assume !(0 == start_simulation_~tmp~3#1); 35235#L1709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 36001#L860-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 34911#L922-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 35413#L923-2 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 34874#L1664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 34875#L1671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 35693#L1672 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 36074#L1722 assume !(0 != start_simulation_~tmp___0~1#1); 35073#L1690-2 [2021-12-16 10:05:16,942 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:16,942 INFO L85 PathProgramCache]: Analyzing trace with hash -24556996, now seen corresponding path program 1 times [2021-12-16 10:05:16,943 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:16,943 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1187790213] [2021-12-16 10:05:16,943 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:16,943 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:16,954 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:17,000 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:05:17,000 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:17,000 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1187790213] [2021-12-16 10:05:17,001 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1187790213] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:17,001 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:17,001 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:05:17,001 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1846565007] [2021-12-16 10:05:17,001 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:17,001 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:05:17,001 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:17,002 INFO L85 PathProgramCache]: Analyzing trace with hash 210812735, now seen corresponding path program 2 times [2021-12-16 10:05:17,002 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:17,002 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [269934269] [2021-12-16 10:05:17,002 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:17,002 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:17,011 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:17,052 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:05:17,053 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:17,053 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [269934269] [2021-12-16 10:05:17,053 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [269934269] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:17,053 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:17,053 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:05:17,053 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1997525388] [2021-12-16 10:05:17,053 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:17,053 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:05:17,053 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:05:17,054 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-16 10:05:17,054 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-16 10:05:17,054 INFO L87 Difference]: Start difference. First operand 1571 states and 2324 transitions. cyclomatic complexity: 754 Second operand has 4 states, 4 states have (on average 34.75) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:17,138 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:05:17,138 INFO L93 Difference]: Finished difference Result 2905 states and 4283 transitions. [2021-12-16 10:05:17,139 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-16 10:05:17,139 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2905 states and 4283 transitions. [2021-12-16 10:05:17,148 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2730 [2021-12-16 10:05:17,171 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2905 states to 2905 states and 4283 transitions. [2021-12-16 10:05:17,171 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2905 [2021-12-16 10:05:17,173 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2905 [2021-12-16 10:05:17,173 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2905 states and 4283 transitions. [2021-12-16 10:05:17,176 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:05:17,176 INFO L681 BuchiCegarLoop]: Abstraction has 2905 states and 4283 transitions. [2021-12-16 10:05:17,178 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2905 states and 4283 transitions. [2021-12-16 10:05:17,231 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2905 to 2905. [2021-12-16 10:05:17,235 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2905 states, 2905 states have (on average 1.474354561101549) internal successors, (4283), 2904 states have internal predecessors, (4283), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:17,241 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2905 states to 2905 states and 4283 transitions. [2021-12-16 10:05:17,241 INFO L704 BuchiCegarLoop]: Abstraction has 2905 states and 4283 transitions. [2021-12-16 10:05:17,241 INFO L587 BuchiCegarLoop]: Abstraction has 2905 states and 4283 transitions. [2021-12-16 10:05:17,242 INFO L425 BuchiCegarLoop]: ======== Iteration 13============ [2021-12-16 10:05:17,242 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2905 states and 4283 transitions. [2021-12-16 10:05:17,247 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2730 [2021-12-16 10:05:17,247 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:05:17,247 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:05:17,248 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:17,248 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:17,249 INFO L791 eck$LassoCheckResult]: Stem: 39823#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 39824#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 40376#L1653 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 40377#L785 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 40239#L792 assume 1 == ~m_i~0;~m_st~0 := 0; 40240#L792-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 39236#L797-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 39237#L802-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 40718#L807-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 40213#L812-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 40214#L817-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 40509#L822-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 40510#L827-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 40593#L832-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 40683#L837-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 40684#L842-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 40557#L847-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 40395#L1121 assume !(0 == ~M_E~0); 40140#L1121-2 assume !(0 == ~T1_E~0); 39513#L1126-1 assume !(0 == ~T2_E~0); 39514#L1131-1 assume !(0 == ~T3_E~0); 39683#L1136-1 assume !(0 == ~T4_E~0); 39780#L1141-1 assume !(0 == ~T5_E~0); 40009#L1146-1 assume !(0 == ~T6_E~0); 40314#L1151-1 assume !(0 == ~T7_E~0); 39841#L1156-1 assume !(0 == ~T8_E~0); 39222#L1161-1 assume !(0 == ~T9_E~0); 39223#L1166-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 39448#L1171-1 assume !(0 == ~T11_E~0); 39449#L1176-1 assume !(0 == ~E_M~0); 40328#L1181-1 assume !(0 == ~E_1~0); 40467#L1186-1 assume !(0 == ~E_2~0); 40520#L1191-1 assume !(0 == ~E_3~0); 39475#L1196-1 assume !(0 == ~E_4~0); 39476#L1201-1 assume !(0 == ~E_5~0); 40731#L1206-1 assume 0 == ~E_6~0;~E_6~0 := 1; 40558#L1211-1 assume !(0 == ~E_7~0); 40559#L1216-1 assume !(0 == ~E_8~0); 39621#L1221-1 assume !(0 == ~E_9~0); 39622#L1226-1 assume !(0 == ~E_10~0); 39318#L1231-1 assume !(0 == ~E_11~0); 39319#L1236-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 40330#L556 assume 1 == ~m_pc~0; 40331#L557 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 39196#L567 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 39197#L568 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 40099#L1391 assume !(0 != activate_threads_~tmp~1#1); 40498#L1391-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 40499#L575 assume !(1 == ~t1_pc~0); 39147#L575-2 is_transmit1_triggered_~__retres1~1#1 := 0; 39148#L586 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 39281#L587 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 39631#L1399 assume !(0 != activate_threads_~tmp___0~0#1); 39588#L1399-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 39589#L594 assume 1 == ~t2_pc~0; 39517#L595 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 39518#L605 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 39989#L606 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 39213#L1407 assume !(0 != activate_threads_~tmp___1~0#1); 39214#L1407-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 39270#L613 assume !(1 == ~t3_pc~0); 39389#L613-2 is_transmit3_triggered_~__retres1~3#1 := 0; 39388#L624 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 39314#L625 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 39315#L1415 assume !(0 != activate_threads_~tmp___2~0#1); 40003#L1415-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 39716#L632 assume 1 == ~t4_pc~0; 39717#L633 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 40228#L643 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 40396#L644 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 40732#L1423 assume !(0 != activate_threads_~tmp___3~0#1); 40339#L1423-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 40080#L651 assume 1 == ~t5_pc~0; 40081#L652 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 39402#L662 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 39403#L663 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 39853#L1431 assume !(0 != activate_threads_~tmp___4~0#1); 39419#L1431-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 39420#L670 assume !(1 == ~t6_pc~0); 40541#L670-2 is_transmit6_triggered_~__retres1~6#1 := 0; 39771#L681 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 39772#L682 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 40642#L1439 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 40046#L1439-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 40047#L689 assume 1 == ~t7_pc~0; 40728#L690 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 40159#L700 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 40160#L701 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 40555#L1447 assume !(0 != activate_threads_~tmp___6~0#1); 39946#L1447-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 39947#L708 assume !(1 == ~t8_pc~0); 39508#L708-2 is_transmit8_triggered_~__retres1~8#1 := 0; 39509#L719 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 40640#L720 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 40625#L1455 assume !(0 != activate_threads_~tmp___7~0#1); 39573#L1455-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 39574#L727 assume 1 == ~t9_pc~0; 39696#L728 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 39272#L738 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 40736#L739 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 40737#L1463 assume !(0 != activate_threads_~tmp___8~0#1); 40719#L1463-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 39628#L746 assume !(1 == ~t10_pc~0); 39629#L746-2 is_transmit10_triggered_~__retres1~10#1 := 0; 40290#L757 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 40411#L758 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 40634#L1471 assume !(0 != activate_threads_~tmp___9~0#1); 40502#L1471-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 39793#L765 assume 1 == ~t11_pc~0; 39794#L766 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 39999#L776 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 39161#L777 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 39162#L1479 assume !(0 != activate_threads_~tmp___10~0#1); 40539#L1479-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 40619#L1249 assume 1 == ~M_E~0;~M_E~0 := 2; 40233#L1249-2 assume !(1 == ~T1_E~0); 39873#L1254-1 assume !(1 == ~T2_E~0); 39207#L1259-1 assume !(1 == ~T3_E~0); 39189#L1264-1 assume !(1 == ~T4_E~0); 39190#L1269-1 assume !(1 == ~T5_E~0); 40761#L1274-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 40693#L1279-1 assume !(1 == ~T7_E~0); 39390#L1284-1 assume !(1 == ~T8_E~0); 39391#L1289-1 assume !(1 == ~T9_E~0); 39925#L1294-1 assume !(1 == ~T10_E~0); 39926#L1299-1 assume !(1 == ~T11_E~0); 39935#L1304-1 assume !(1 == ~E_M~0); 40754#L1309-1 assume !(1 == ~E_1~0); 40757#L1314-1 assume 1 == ~E_2~0;~E_2~0 := 2; 39337#L1319-1 assume !(1 == ~E_3~0); 39338#L1324-1 assume !(1 == ~E_4~0); 39470#L1329-1 assume !(1 == ~E_5~0); 39471#L1334-1 assume !(1 == ~E_6~0); 40578#L1339-1 assume !(1 == ~E_7~0); 40660#L1344-1 assume !(1 == ~E_8~0); 40661#L1349-1 assume !(1 == ~E_9~0); 40059#L1354-1 assume 1 == ~E_10~0;~E_10~0 := 2; 40060#L1359-1 assume !(1 == ~E_11~0); 40436#L1364-1 assume { :end_inline_reset_delta_events } true; 39559#L1690-2 [2021-12-16 10:05:17,249 INFO L793 eck$LassoCheckResult]: Loop: 39559#L1690-2 assume !false; 39560#L1691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 39445#L1096 assume !false; 40449#L933 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 40760#L860 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 40333#L922 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 40334#L923 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 40768#L937 assume !(0 != eval_~tmp~0#1); 40268#L1111 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 40269#L785-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 40743#L1121-3 assume 0 == ~M_E~0;~M_E~0 := 1; 40769#L1121-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 41680#L1126-3 assume !(0 == ~T2_E~0); 41679#L1131-3 assume !(0 == ~T3_E~0); 41678#L1136-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 41677#L1141-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 41676#L1146-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 41675#L1151-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 41674#L1156-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 41673#L1161-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 41672#L1166-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 41671#L1171-3 assume !(0 == ~T11_E~0); 41670#L1176-3 assume 0 == ~E_M~0;~E_M~0 := 1; 41669#L1181-3 assume 0 == ~E_1~0;~E_1~0 := 1; 41668#L1186-3 assume 0 == ~E_2~0;~E_2~0 := 1; 41667#L1191-3 assume 0 == ~E_3~0;~E_3~0 := 1; 41666#L1196-3 assume 0 == ~E_4~0;~E_4~0 := 1; 41665#L1201-3 assume 0 == ~E_5~0;~E_5~0 := 1; 41664#L1206-3 assume 0 == ~E_6~0;~E_6~0 := 1; 41663#L1211-3 assume !(0 == ~E_7~0); 41662#L1216-3 assume 0 == ~E_8~0;~E_8~0 := 1; 41661#L1221-3 assume 0 == ~E_9~0;~E_9~0 := 1; 41660#L1226-3 assume 0 == ~E_10~0;~E_10~0 := 1; 41659#L1231-3 assume 0 == ~E_11~0;~E_11~0 := 1; 41658#L1236-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 41657#L556-39 assume 1 == ~m_pc~0; 41655#L557-13 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 41654#L567-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 41653#L568-13 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 41652#L1391-39 assume !(0 != activate_threads_~tmp~1#1); 41651#L1391-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 41650#L575-39 assume 1 == ~t1_pc~0; 41648#L576-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 41647#L586-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 41646#L587-13 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 41645#L1399-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 41644#L1399-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 41643#L594-39 assume 1 == ~t2_pc~0; 41641#L595-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 41640#L605-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 41639#L606-13 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 41638#L1407-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 41637#L1407-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 41636#L613-39 assume 1 == ~t3_pc~0; 41634#L614-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 41633#L624-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 41632#L625-13 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 41631#L1415-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 41630#L1415-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 41629#L632-39 assume !(1 == ~t4_pc~0); 41627#L632-41 is_transmit4_triggered_~__retres1~4#1 := 0; 41626#L643-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 41625#L644-13 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 41624#L1423-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 41623#L1423-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 41622#L651-39 assume 1 == ~t5_pc~0; 41620#L652-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 41619#L662-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 41618#L663-13 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 41617#L1431-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 41616#L1431-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 41615#L670-39 assume !(1 == ~t6_pc~0); 41613#L670-41 is_transmit6_triggered_~__retres1~6#1 := 0; 41612#L681-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 41611#L682-13 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 41610#L1439-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 41609#L1439-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 41608#L689-39 assume 1 == ~t7_pc~0; 41606#L690-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 41605#L700-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 41604#L701-13 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 41603#L1447-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 41602#L1447-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 41601#L708-39 assume 1 == ~t8_pc~0; 41600#L709-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 41598#L719-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 41597#L720-13 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 41596#L1455-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 41595#L1455-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 41594#L727-39 assume 1 == ~t9_pc~0; 41592#L728-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 41591#L738-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 41590#L739-13 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 41589#L1463-39 assume !(0 != activate_threads_~tmp___8~0#1); 41588#L1463-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 41587#L746-39 assume 1 == ~t10_pc~0; 41585#L747-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 41584#L757-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 41583#L758-13 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 41582#L1471-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 41581#L1471-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 41580#L765-39 assume !(1 == ~t11_pc~0); 41578#L765-41 is_transmit11_triggered_~__retres1~11#1 := 0; 41577#L776-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 41576#L777-13 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 41575#L1479-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 41574#L1479-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 41573#L1249-3 assume 1 == ~M_E~0;~M_E~0 := 2; 40134#L1249-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 41572#L1254-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 40733#L1259-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 41571#L1264-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 41570#L1269-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 41569#L1274-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 41568#L1279-3 assume !(1 == ~T7_E~0); 41567#L1284-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 41566#L1289-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 41565#L1294-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 41564#L1299-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 41563#L1304-3 assume 1 == ~E_M~0;~E_M~0 := 2; 41562#L1309-3 assume 1 == ~E_1~0;~E_1~0 := 2; 41561#L1314-3 assume 1 == ~E_2~0;~E_2~0 := 2; 41560#L1319-3 assume !(1 == ~E_3~0); 41559#L1324-3 assume 1 == ~E_4~0;~E_4~0 := 2; 41558#L1329-3 assume 1 == ~E_5~0;~E_5~0 := 2; 41557#L1334-3 assume 1 == ~E_6~0;~E_6~0 := 2; 41556#L1339-3 assume 1 == ~E_7~0;~E_7~0 := 2; 41555#L1344-3 assume 1 == ~E_8~0;~E_8~0 := 2; 41554#L1349-3 assume 1 == ~E_9~0;~E_9~0 := 2; 41553#L1354-3 assume 1 == ~E_10~0;~E_10~0 := 2; 41552#L1359-3 assume !(1 == ~E_11~0); 41551#L1364-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 41541#L860-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 41538#L922-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 41537#L923-1 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 41536#L1709 assume !(0 == start_simulation_~tmp~3#1); 39721#L1709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 40516#L860-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 39397#L922-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 39901#L923-2 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 39360#L1664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 39361#L1671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 40188#L1672 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 40589#L1722 assume !(0 != start_simulation_~tmp___0~1#1); 39559#L1690-2 [2021-12-16 10:05:17,250 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:17,250 INFO L85 PathProgramCache]: Analyzing trace with hash -1257740808, now seen corresponding path program 1 times [2021-12-16 10:05:17,250 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:17,250 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1962357091] [2021-12-16 10:05:17,250 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:17,250 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:17,257 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:17,271 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:05:17,272 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:17,272 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1962357091] [2021-12-16 10:05:17,272 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1962357091] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:17,272 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:17,272 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:05:17,272 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [111163635] [2021-12-16 10:05:17,272 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:17,273 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:05:17,273 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:17,273 INFO L85 PathProgramCache]: Analyzing trace with hash -144450819, now seen corresponding path program 1 times [2021-12-16 10:05:17,273 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:17,273 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [879020872] [2021-12-16 10:05:17,274 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:17,274 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:17,281 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:17,297 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:05:17,298 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:17,298 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [879020872] [2021-12-16 10:05:17,298 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [879020872] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:17,298 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:17,298 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:05:17,298 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [472339709] [2021-12-16 10:05:17,298 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:17,299 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:05:17,299 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:05:17,299 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-16 10:05:17,299 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-16 10:05:17,300 INFO L87 Difference]: Start difference. First operand 2905 states and 4283 transitions. cyclomatic complexity: 1380 Second operand has 4 states, 4 states have (on average 34.75) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:17,381 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:05:17,381 INFO L93 Difference]: Finished difference Result 5561 states and 8178 transitions. [2021-12-16 10:05:17,381 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-16 10:05:17,382 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5561 states and 8178 transitions. [2021-12-16 10:05:17,399 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 5350 [2021-12-16 10:05:17,411 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5561 states to 5561 states and 8178 transitions. [2021-12-16 10:05:17,411 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5561 [2021-12-16 10:05:17,414 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5561 [2021-12-16 10:05:17,414 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5561 states and 8178 transitions. [2021-12-16 10:05:17,418 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:05:17,418 INFO L681 BuchiCegarLoop]: Abstraction has 5561 states and 8178 transitions. [2021-12-16 10:05:17,421 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5561 states and 8178 transitions. [2021-12-16 10:05:17,490 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5561 to 5561. [2021-12-16 10:05:17,495 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5561 states, 5561 states have (on average 1.4705988131631003) internal successors, (8178), 5560 states have internal predecessors, (8178), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:17,504 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5561 states to 5561 states and 8178 transitions. [2021-12-16 10:05:17,504 INFO L704 BuchiCegarLoop]: Abstraction has 5561 states and 8178 transitions. [2021-12-16 10:05:17,504 INFO L587 BuchiCegarLoop]: Abstraction has 5561 states and 8178 transitions. [2021-12-16 10:05:17,504 INFO L425 BuchiCegarLoop]: ======== Iteration 14============ [2021-12-16 10:05:17,505 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5561 states and 8178 transitions. [2021-12-16 10:05:17,515 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 5350 [2021-12-16 10:05:17,515 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:05:17,515 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:05:17,516 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:17,517 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:17,517 INFO L791 eck$LassoCheckResult]: Stem: 48296#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 48297#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 48846#L1653 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 48847#L785 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 48713#L792 assume 1 == ~m_i~0;~m_st~0 := 0; 48714#L792-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 47712#L797-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 47713#L802-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 49174#L807-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 48686#L812-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 48687#L817-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 48970#L822-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 48971#L827-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 49056#L832-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 49141#L837-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 49142#L842-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 49019#L847-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 48864#L1121 assume !(0 == ~M_E~0); 48615#L1121-2 assume !(0 == ~T1_E~0); 47988#L1126-1 assume !(0 == ~T2_E~0); 47989#L1131-1 assume !(0 == ~T3_E~0); 48160#L1136-1 assume !(0 == ~T4_E~0); 48257#L1141-1 assume !(0 == ~T5_E~0); 48481#L1146-1 assume !(0 == ~T6_E~0); 48785#L1151-1 assume !(0 == ~T7_E~0); 48318#L1156-1 assume !(0 == ~T8_E~0); 47698#L1161-1 assume !(0 == ~T9_E~0); 47699#L1166-1 assume !(0 == ~T10_E~0); 47924#L1171-1 assume !(0 == ~T11_E~0); 47925#L1176-1 assume !(0 == ~E_M~0); 48801#L1181-1 assume !(0 == ~E_1~0); 48931#L1186-1 assume !(0 == ~E_2~0); 48981#L1191-1 assume !(0 == ~E_3~0); 47951#L1196-1 assume !(0 == ~E_4~0); 47952#L1201-1 assume !(0 == ~E_5~0); 49184#L1206-1 assume 0 == ~E_6~0;~E_6~0 := 1; 49020#L1211-1 assume !(0 == ~E_7~0); 49021#L1216-1 assume !(0 == ~E_8~0); 48094#L1221-1 assume !(0 == ~E_9~0); 48095#L1226-1 assume !(0 == ~E_10~0); 47794#L1231-1 assume !(0 == ~E_11~0); 47795#L1236-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 48802#L556 assume 1 == ~m_pc~0; 48803#L557 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 47672#L567 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 47673#L568 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 48574#L1391 assume !(0 != activate_threads_~tmp~1#1); 48959#L1391-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 48960#L575 assume !(1 == ~t1_pc~0); 47623#L575-2 is_transmit1_triggered_~__retres1~1#1 := 0; 47624#L586 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 47757#L587 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 48108#L1399 assume !(0 != activate_threads_~tmp___0~0#1); 48064#L1399-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 48065#L594 assume 1 == ~t2_pc~0; 47993#L595 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 47994#L605 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 48466#L606 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 47687#L1407 assume !(0 != activate_threads_~tmp___1~0#1); 47688#L1407-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 47746#L613 assume !(1 == ~t3_pc~0); 47865#L613-2 is_transmit3_triggered_~__retres1~3#1 := 0; 47864#L624 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 47790#L625 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 47791#L1415 assume !(0 != activate_threads_~tmp___2~0#1); 48480#L1415-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 48193#L632 assume 1 == ~t4_pc~0; 48194#L633 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 48701#L643 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 48865#L644 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 49185#L1423 assume !(0 != activate_threads_~tmp___3~0#1); 48811#L1423-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 48556#L651 assume 1 == ~t5_pc~0; 48557#L652 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 47878#L662 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 47879#L663 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 48331#L1431 assume !(0 != activate_threads_~tmp___4~0#1); 47895#L1431-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 47896#L670 assume !(1 == ~t6_pc~0); 49002#L670-2 is_transmit6_triggered_~__retres1~6#1 := 0; 48243#L681 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 48244#L682 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 49101#L1439 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 48521#L1439-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 48522#L689 assume 1 == ~t7_pc~0; 49181#L690 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 48634#L700 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 48635#L701 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 49017#L1447 assume !(0 != activate_threads_~tmp___6~0#1); 48424#L1447-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 48425#L708 assume !(1 == ~t8_pc~0); 47984#L708-2 is_transmit8_triggered_~__retres1~8#1 := 0; 47985#L719 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 49100#L720 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 49085#L1455 assume !(0 != activate_threads_~tmp___7~0#1); 48049#L1455-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 48050#L727 assume 1 == ~t9_pc~0; 48173#L728 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 47748#L738 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 49189#L739 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 49190#L1463 assume !(0 != activate_threads_~tmp___8~0#1); 49175#L1463-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 48104#L746 assume !(1 == ~t10_pc~0); 48105#L746-2 is_transmit10_triggered_~__retres1~10#1 := 0; 48761#L757 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 48880#L758 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 49094#L1471 assume !(0 != activate_threads_~tmp___9~0#1); 48963#L1471-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 48266#L765 assume 1 == ~t11_pc~0; 48267#L766 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 48476#L776 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 47637#L777 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 47638#L1479 assume !(0 != activate_threads_~tmp___10~0#1); 49001#L1479-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 49081#L1249 assume 1 == ~M_E~0;~M_E~0 := 2; 48705#L1249-2 assume !(1 == ~T1_E~0); 48351#L1254-1 assume !(1 == ~T2_E~0); 48352#L1259-1 assume !(1 == ~T3_E~0); 50017#L1264-1 assume !(1 == ~T4_E~0); 50011#L1269-1 assume !(1 == ~T5_E~0); 49217#L1274-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 49151#L1279-1 assume !(1 == ~T7_E~0); 47866#L1284-1 assume !(1 == ~T8_E~0); 47867#L1289-1 assume !(1 == ~T9_E~0); 49191#L1294-1 assume !(1 == ~T10_E~0); 49431#L1299-1 assume !(1 == ~T11_E~0); 49430#L1304-1 assume !(1 == ~E_M~0); 49429#L1309-1 assume !(1 == ~E_1~0); 49426#L1314-1 assume 1 == ~E_2~0;~E_2~0 := 2; 49383#L1319-1 assume !(1 == ~E_3~0); 49350#L1324-1 assume !(1 == ~E_4~0); 49331#L1329-1 assume !(1 == ~E_5~0); 49329#L1334-1 assume !(1 == ~E_6~0); 49314#L1339-1 assume !(1 == ~E_7~0); 49313#L1344-1 assume !(1 == ~E_8~0); 49312#L1349-1 assume !(1 == ~E_9~0); 49288#L1354-1 assume 1 == ~E_10~0;~E_10~0 := 2; 49271#L1359-1 assume !(1 == ~E_11~0); 49262#L1364-1 assume { :end_inline_reset_delta_events } true; 49254#L1690-2 [2021-12-16 10:05:17,517 INFO L793 eck$LassoCheckResult]: Loop: 49254#L1690-2 assume !false; 49247#L1691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 49244#L1096 assume !false; 49243#L933 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 49233#L860 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 49230#L922 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 49229#L923 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 49227#L937 assume !(0 != eval_~tmp~0#1); 49226#L1111 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 49225#L785-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 49224#L1121-3 assume 0 == ~M_E~0;~M_E~0 := 1; 49219#L1121-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 49176#L1126-3 assume !(0 == ~T2_E~0); 48451#L1131-3 assume !(0 == ~T3_E~0); 48452#L1136-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 49218#L1141-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 48812#L1146-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 47982#L1151-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 47983#L1156-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 49116#L1161-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 49196#L1166-3 assume !(0 == ~T10_E~0); 51576#L1171-3 assume !(0 == ~T11_E~0); 51574#L1176-3 assume 0 == ~E_M~0;~E_M~0 := 1; 51572#L1181-3 assume 0 == ~E_1~0;~E_1~0 := 1; 51570#L1186-3 assume 0 == ~E_2~0;~E_2~0 := 1; 51568#L1191-3 assume 0 == ~E_3~0;~E_3~0 := 1; 51566#L1196-3 assume 0 == ~E_4~0;~E_4~0 := 1; 51565#L1201-3 assume 0 == ~E_5~0;~E_5~0 := 1; 51564#L1206-3 assume 0 == ~E_6~0;~E_6~0 := 1; 51563#L1211-3 assume !(0 == ~E_7~0); 51562#L1216-3 assume 0 == ~E_8~0;~E_8~0 := 1; 51561#L1221-3 assume 0 == ~E_9~0;~E_9~0 := 1; 51560#L1226-3 assume 0 == ~E_10~0;~E_10~0 := 1; 51559#L1231-3 assume 0 == ~E_11~0;~E_11~0 := 1; 51558#L1236-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 51557#L556-39 assume 1 == ~m_pc~0; 48752#L557-13 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 48719#L567-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 48102#L568-13 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 48103#L1391-39 assume !(0 != activate_threads_~tmp~1#1); 48277#L1391-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 48676#L575-39 assume 1 == ~t1_pc~0; 48677#L576-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 49037#L586-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 50682#L587-13 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 50679#L1399-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 50676#L1399-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 50672#L594-39 assume 1 == ~t2_pc~0; 50668#L595-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 50664#L605-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 50661#L606-13 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 50659#L1407-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 50656#L1407-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 49062#L613-39 assume 1 == ~t3_pc~0; 49063#L614-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 47643#L624-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 47644#L625-13 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 48408#L1415-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 47742#L1415-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 47743#L632-39 assume 1 == ~t4_pc~0; 49029#L633-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 48332#L643-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 48333#L644-13 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 48894#L1423-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 49028#L1423-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 48012#L651-39 assume 1 == ~t5_pc~0; 48013#L652-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 47775#L662-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 49016#L663-13 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 49127#L1431-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 49167#L1431-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 49192#L670-39 assume !(1 == ~t6_pc~0); 48754#L670-41 is_transmit6_triggered_~__retres1~6#1 := 0; 47689#L681-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 47690#L682-13 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 47758#L1439-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 48360#L1439-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 48361#L689-39 assume !(1 == ~t7_pc~0); 48485#L689-41 is_transmit7_triggered_~__retres1~7#1 := 0; 48486#L700-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 48014#L701-13 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 48015#L1447-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 47882#L1447-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 47883#L708-39 assume 1 == ~t8_pc~0; 48787#L709-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 50450#L719-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 50442#L720-13 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 50432#L1455-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 50423#L1455-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 50406#L727-39 assume 1 == ~t9_pc~0; 49216#L728-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 48079#L738-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 48080#L739-13 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 49045#L1463-39 assume !(0 != activate_threads_~tmp___8~0#1); 48870#L1463-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 48871#L746-39 assume 1 == ~t10_pc~0; 50340#L747-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 50331#L757-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 50323#L758-13 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 50314#L1471-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 50305#L1471-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 50298#L765-39 assume !(1 == ~t11_pc~0); 50284#L765-41 is_transmit11_triggered_~__retres1~11#1 := 0; 50274#L776-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 50265#L777-13 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 50257#L1479-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 50246#L1479-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 50236#L1249-3 assume 1 == ~M_E~0;~M_E~0 := 2; 48609#L1249-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 50219#L1254-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 50211#L1259-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 50204#L1264-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 50196#L1269-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 50187#L1274-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 50179#L1279-3 assume !(1 == ~T7_E~0); 50171#L1284-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 49170#L1289-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 49171#L1294-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 50156#L1299-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 50154#L1304-3 assume 1 == ~E_M~0;~E_M~0 := 2; 50146#L1309-3 assume 1 == ~E_1~0;~E_1~0 := 2; 50138#L1314-3 assume 1 == ~E_2~0;~E_2~0 := 2; 50131#L1319-3 assume !(1 == ~E_3~0); 50128#L1324-3 assume 1 == ~E_4~0;~E_4~0 := 2; 50126#L1329-3 assume 1 == ~E_5~0;~E_5~0 := 2; 50115#L1334-3 assume 1 == ~E_6~0;~E_6~0 := 2; 49472#L1339-3 assume 1 == ~E_7~0;~E_7~0 := 2; 49470#L1344-3 assume 1 == ~E_8~0;~E_8~0 := 2; 49468#L1349-3 assume 1 == ~E_9~0;~E_9~0 := 2; 49466#L1354-3 assume 1 == ~E_10~0;~E_10~0 := 2; 49465#L1359-3 assume !(1 == ~E_11~0); 49425#L1364-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 49392#L860-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 49389#L922-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 49388#L923-1 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 49387#L1709 assume !(0 == start_simulation_~tmp~3#1); 48198#L1709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 49363#L860-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 49352#L922-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 49333#L923-2 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 49311#L1664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 49287#L1671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 49270#L1672 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 49261#L1722 assume !(0 != start_simulation_~tmp___0~1#1); 49254#L1690-2 [2021-12-16 10:05:17,518 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:17,518 INFO L85 PathProgramCache]: Analyzing trace with hash -786384458, now seen corresponding path program 1 times [2021-12-16 10:05:17,518 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:17,518 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1424106034] [2021-12-16 10:05:17,518 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:17,518 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:17,526 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:17,544 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:05:17,544 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:17,544 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1424106034] [2021-12-16 10:05:17,544 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1424106034] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:17,544 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:17,544 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:05:17,545 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1556439925] [2021-12-16 10:05:17,545 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:17,545 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:05:17,545 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:17,545 INFO L85 PathProgramCache]: Analyzing trace with hash -137699333, now seen corresponding path program 1 times [2021-12-16 10:05:17,546 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:17,546 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [327400415] [2021-12-16 10:05:17,546 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:17,546 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:17,554 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:17,569 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:05:17,569 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:17,569 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [327400415] [2021-12-16 10:05:17,569 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [327400415] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:17,570 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:17,570 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:05:17,570 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1840573573] [2021-12-16 10:05:17,570 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:17,570 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:05:17,571 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:05:17,571 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-16 10:05:17,571 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-16 10:05:17,572 INFO L87 Difference]: Start difference. First operand 5561 states and 8178 transitions. cyclomatic complexity: 2621 Second operand has 4 states, 4 states have (on average 34.75) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:17,729 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:05:17,730 INFO L93 Difference]: Finished difference Result 10493 states and 15401 transitions. [2021-12-16 10:05:17,730 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-16 10:05:17,730 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 10493 states and 15401 transitions. [2021-12-16 10:05:17,771 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 10246 [2021-12-16 10:05:17,798 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 10493 states to 10493 states and 15401 transitions. [2021-12-16 10:05:17,799 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10493 [2021-12-16 10:05:17,807 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10493 [2021-12-16 10:05:17,807 INFO L73 IsDeterministic]: Start isDeterministic. Operand 10493 states and 15401 transitions. [2021-12-16 10:05:17,817 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:05:17,818 INFO L681 BuchiCegarLoop]: Abstraction has 10493 states and 15401 transitions. [2021-12-16 10:05:17,825 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10493 states and 15401 transitions. [2021-12-16 10:05:17,973 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10493 to 10489. [2021-12-16 10:05:17,986 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10489 states, 10489 states have (on average 1.4679187720469062) internal successors, (15397), 10488 states have internal predecessors, (15397), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:18,005 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10489 states to 10489 states and 15397 transitions. [2021-12-16 10:05:18,006 INFO L704 BuchiCegarLoop]: Abstraction has 10489 states and 15397 transitions. [2021-12-16 10:05:18,006 INFO L587 BuchiCegarLoop]: Abstraction has 10489 states and 15397 transitions. [2021-12-16 10:05:18,006 INFO L425 BuchiCegarLoop]: ======== Iteration 15============ [2021-12-16 10:05:18,006 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 10489 states and 15397 transitions. [2021-12-16 10:05:18,033 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 10246 [2021-12-16 10:05:18,034 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:05:18,034 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:05:18,035 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:18,035 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:18,036 INFO L791 eck$LassoCheckResult]: Stem: 64358#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 64359#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 64921#L1653 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 64922#L785 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 64784#L792 assume 1 == ~m_i~0;~m_st~0 := 0; 64785#L792-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 63776#L797-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 63777#L802-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 65270#L807-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 64755#L812-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 64756#L817-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 65049#L822-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 65050#L827-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 65140#L832-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 65233#L837-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 65234#L842-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 65101#L847-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 64939#L1121 assume !(0 == ~M_E~0); 64683#L1121-2 assume !(0 == ~T1_E~0); 64052#L1126-1 assume !(0 == ~T2_E~0); 64053#L1131-1 assume !(0 == ~T3_E~0); 64223#L1136-1 assume !(0 == ~T4_E~0); 64319#L1141-1 assume !(0 == ~T5_E~0); 64547#L1146-1 assume !(0 == ~T6_E~0); 64860#L1151-1 assume !(0 == ~T7_E~0); 64381#L1156-1 assume !(0 == ~T8_E~0); 63762#L1161-1 assume !(0 == ~T9_E~0); 63763#L1166-1 assume !(0 == ~T10_E~0); 63988#L1171-1 assume !(0 == ~T11_E~0); 63989#L1176-1 assume !(0 == ~E_M~0); 64874#L1181-1 assume !(0 == ~E_1~0); 65009#L1186-1 assume !(0 == ~E_2~0); 65061#L1191-1 assume !(0 == ~E_3~0); 64015#L1196-1 assume !(0 == ~E_4~0); 64016#L1201-1 assume !(0 == ~E_5~0); 65281#L1206-1 assume !(0 == ~E_6~0); 65102#L1211-1 assume !(0 == ~E_7~0); 65103#L1216-1 assume !(0 == ~E_8~0); 64158#L1221-1 assume !(0 == ~E_9~0); 64159#L1226-1 assume !(0 == ~E_10~0); 63858#L1231-1 assume !(0 == ~E_11~0); 63859#L1236-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 64875#L556 assume 1 == ~m_pc~0; 64876#L557 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 63736#L567 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 63737#L568 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 64643#L1391 assume !(0 != activate_threads_~tmp~1#1); 65038#L1391-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 65039#L575 assume !(1 == ~t1_pc~0); 63687#L575-2 is_transmit1_triggered_~__retres1~1#1 := 0; 63688#L586 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 63821#L587 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 64171#L1399 assume !(0 != activate_threads_~tmp___0~0#1); 64128#L1399-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 64129#L594 assume 1 == ~t2_pc~0; 64057#L595 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 64058#L605 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 64531#L606 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 63751#L1407 assume !(0 != activate_threads_~tmp___1~0#1); 63752#L1407-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 63810#L613 assume !(1 == ~t3_pc~0); 63929#L613-2 is_transmit3_triggered_~__retres1~3#1 := 0; 63928#L624 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 63854#L625 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 63855#L1415 assume !(0 != activate_threads_~tmp___2~0#1); 64546#L1415-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 64256#L632 assume 1 == ~t4_pc~0; 64257#L633 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 64772#L643 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 64940#L644 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 65282#L1423 assume !(0 != activate_threads_~tmp___3~0#1); 64884#L1423-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 64624#L651 assume 1 == ~t5_pc~0; 64625#L652 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 63942#L662 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 63943#L663 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 64393#L1431 assume !(0 != activate_threads_~tmp___4~0#1); 63959#L1431-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 63960#L670 assume !(1 == ~t6_pc~0); 65084#L670-2 is_transmit6_triggered_~__retres1~6#1 := 0; 64305#L681 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 64306#L682 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 65186#L1439 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 64588#L1439-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 64589#L689 assume 1 == ~t7_pc~0; 65276#L690 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 64702#L700 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 64703#L701 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 65099#L1447 assume !(0 != activate_threads_~tmp___6~0#1); 64489#L1447-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 64490#L708 assume !(1 == ~t8_pc~0); 64048#L708-2 is_transmit8_triggered_~__retres1~8#1 := 0; 64049#L719 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 65185#L720 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 65168#L1455 assume !(0 != activate_threads_~tmp___7~0#1); 64113#L1455-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 64114#L727 assume 1 == ~t9_pc~0; 64236#L728 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 63812#L738 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 65287#L739 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 65288#L1463 assume !(0 != activate_threads_~tmp___8~0#1); 65271#L1463-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 64167#L746 assume !(1 == ~t10_pc~0); 64168#L746-2 is_transmit10_triggered_~__retres1~10#1 := 0; 64833#L757 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 64957#L758 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 65178#L1471 assume !(0 != activate_threads_~tmp___9~0#1); 65042#L1471-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 64329#L765 assume 1 == ~t11_pc~0; 64330#L766 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 64541#L776 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 63701#L777 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 63702#L1479 assume !(0 != activate_threads_~tmp___10~0#1); 65083#L1479-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 65164#L1249 assume 1 == ~M_E~0;~M_E~0 := 2; 65165#L1249-2 assume !(1 == ~T1_E~0); 64413#L1254-1 assume !(1 == ~T2_E~0); 64414#L1259-1 assume !(1 == ~T3_E~0); 65814#L1264-1 assume !(1 == ~T4_E~0); 65324#L1269-1 assume !(1 == ~T5_E~0); 65314#L1274-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 65246#L1279-1 assume !(1 == ~T7_E~0); 65247#L1284-1 assume !(1 == ~T8_E~0); 65758#L1289-1 assume !(1 == ~T9_E~0); 65756#L1294-1 assume !(1 == ~T10_E~0); 65753#L1299-1 assume !(1 == ~T11_E~0); 65751#L1304-1 assume !(1 == ~E_M~0); 65749#L1309-1 assume !(1 == ~E_1~0); 65528#L1314-1 assume 1 == ~E_2~0;~E_2~0 := 2; 65525#L1319-1 assume !(1 == ~E_3~0); 65482#L1324-1 assume !(1 == ~E_4~0); 65450#L1329-1 assume !(1 == ~E_5~0); 65447#L1334-1 assume !(1 == ~E_6~0); 65425#L1339-1 assume !(1 == ~E_7~0); 65423#L1344-1 assume !(1 == ~E_8~0); 65405#L1349-1 assume !(1 == ~E_9~0); 65388#L1354-1 assume 1 == ~E_10~0;~E_10~0 := 2; 65374#L1359-1 assume !(1 == ~E_11~0); 65365#L1364-1 assume { :end_inline_reset_delta_events } true; 65357#L1690-2 [2021-12-16 10:05:18,036 INFO L793 eck$LassoCheckResult]: Loop: 65357#L1690-2 assume !false; 65350#L1691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 65347#L1096 assume !false; 65346#L933 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 65336#L860 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 65333#L922 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 65332#L923 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 65330#L937 assume !(0 != eval_~tmp~0#1); 65329#L1111 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 65328#L785-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 65326#L1121-3 assume 0 == ~M_E~0;~M_E~0 := 1; 65327#L1121-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 69340#L1126-3 assume !(0 == ~T2_E~0); 69338#L1131-3 assume !(0 == ~T3_E~0); 69336#L1136-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 69333#L1141-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 69331#L1146-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 69329#L1151-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 69327#L1156-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 69325#L1161-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 69323#L1166-3 assume !(0 == ~T10_E~0); 69320#L1171-3 assume !(0 == ~T11_E~0); 69318#L1176-3 assume 0 == ~E_M~0;~E_M~0 := 1; 69316#L1181-3 assume 0 == ~E_1~0;~E_1~0 := 1; 69314#L1186-3 assume 0 == ~E_2~0;~E_2~0 := 1; 69312#L1191-3 assume 0 == ~E_3~0;~E_3~0 := 1; 69310#L1196-3 assume 0 == ~E_4~0;~E_4~0 := 1; 69307#L1201-3 assume 0 == ~E_5~0;~E_5~0 := 1; 69305#L1206-3 assume !(0 == ~E_6~0); 69303#L1211-3 assume !(0 == ~E_7~0); 69301#L1216-3 assume 0 == ~E_8~0;~E_8~0 := 1; 69299#L1221-3 assume 0 == ~E_9~0;~E_9~0 := 1; 69297#L1226-3 assume 0 == ~E_10~0;~E_10~0 := 1; 69294#L1231-3 assume 0 == ~E_11~0;~E_11~0 := 1; 69293#L1236-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 69292#L556-39 assume 1 == ~m_pc~0; 69289#L557-13 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 69286#L567-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 69284#L568-13 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 69282#L1391-39 assume !(0 != activate_threads_~tmp~1#1); 69280#L1391-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 69278#L575-39 assume 1 == ~t1_pc~0; 69275#L576-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 69272#L586-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 69270#L587-13 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 69268#L1399-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 69266#L1399-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 69264#L594-39 assume 1 == ~t2_pc~0; 69261#L595-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 69258#L605-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 69256#L606-13 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 69254#L1407-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 66630#L1407-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 66628#L613-39 assume 1 == ~t3_pc~0; 66573#L614-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 66571#L624-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 66510#L625-13 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 66473#L1415-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 66471#L1415-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 66469#L632-39 assume !(1 == ~t4_pc~0); 66465#L632-41 is_transmit4_triggered_~__retres1~4#1 := 0; 66422#L643-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 66420#L644-13 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 66418#L1423-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 66416#L1423-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 66360#L651-39 assume !(1 == ~t5_pc~0); 66357#L651-41 is_transmit5_triggered_~__retres1~5#1 := 0; 66354#L662-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 66351#L663-13 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 66349#L1431-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 66347#L1431-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 66345#L670-39 assume 1 == ~t6_pc~0; 66343#L671-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 66340#L681-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 66337#L682-13 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 66335#L1439-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 66333#L1439-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 66331#L689-39 assume !(1 == ~t7_pc~0); 66329#L689-41 is_transmit7_triggered_~__retres1~7#1 := 0; 66327#L700-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 66326#L701-13 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 66325#L1447-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 66324#L1447-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 66323#L708-39 assume 1 == ~t8_pc~0; 66259#L709-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 66256#L719-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 66254#L720-13 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 66252#L1455-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 66250#L1455-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 66247#L727-39 assume !(1 == ~t9_pc~0); 66245#L727-41 is_transmit9_triggered_~__retres1~9#1 := 0; 66242#L738-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 66240#L739-13 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 66238#L1463-39 assume !(0 != activate_threads_~tmp___8~0#1); 66236#L1463-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 65069#L746-39 assume 1 == ~t10_pc~0; 65070#L747-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 66228#L757-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 66226#L758-13 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 66224#L1471-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 66166#L1471-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 66118#L765-39 assume !(1 == ~t11_pc~0); 66057#L765-41 is_transmit11_triggered_~__retres1~11#1 := 0; 66054#L776-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 66052#L777-13 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 66050#L1479-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 66048#L1479-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 66014#L1249-3 assume 1 == ~M_E~0;~M_E~0 := 2; 64677#L1249-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 66010#L1254-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 65283#L1259-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 65942#L1264-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 65940#L1269-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 65938#L1274-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 65894#L1279-3 assume !(1 == ~T7_E~0); 65868#L1284-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 65841#L1289-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 65839#L1294-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 65817#L1299-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 65815#L1304-3 assume 1 == ~E_M~0;~E_M~0 := 2; 65795#L1309-3 assume 1 == ~E_1~0;~E_1~0 := 2; 65794#L1314-3 assume 1 == ~E_2~0;~E_2~0 := 2; 65792#L1319-3 assume !(1 == ~E_3~0); 65790#L1324-3 assume 1 == ~E_4~0;~E_4~0 := 2; 65789#L1329-3 assume 1 == ~E_5~0;~E_5~0 := 2; 65787#L1334-3 assume 1 == ~E_6~0;~E_6~0 := 2; 65784#L1339-3 assume 1 == ~E_7~0;~E_7~0 := 2; 65783#L1344-3 assume 1 == ~E_8~0;~E_8~0 := 2; 65782#L1349-3 assume 1 == ~E_9~0;~E_9~0 := 2; 65781#L1354-3 assume 1 == ~E_10~0;~E_10~0 := 2; 65779#L1359-3 assume !(1 == ~E_11~0); 65548#L1364-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 65513#L860-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 65510#L922-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 65508#L923-1 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 65506#L1709 assume !(0 == start_simulation_~tmp~3#1); 64261#L1709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 65477#L860-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 65443#L922-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 65422#L923-2 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 65404#L1664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 65387#L1671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 65373#L1672 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 65364#L1722 assume !(0 != start_simulation_~tmp___0~1#1); 65357#L1690-2 [2021-12-16 10:05:18,036 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:18,036 INFO L85 PathProgramCache]: Analyzing trace with hash 602909556, now seen corresponding path program 1 times [2021-12-16 10:05:18,037 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:18,037 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [416769011] [2021-12-16 10:05:18,037 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:18,037 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:18,046 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:18,064 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:05:18,065 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:18,065 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [416769011] [2021-12-16 10:05:18,065 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [416769011] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:18,065 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:18,065 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-16 10:05:18,065 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [788383547] [2021-12-16 10:05:18,066 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:18,066 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:05:18,066 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:18,066 INFO L85 PathProgramCache]: Analyzing trace with hash -1569705669, now seen corresponding path program 1 times [2021-12-16 10:05:18,066 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:18,066 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [545338526] [2021-12-16 10:05:18,067 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:18,067 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:18,074 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:18,090 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:05:18,090 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:18,090 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [545338526] [2021-12-16 10:05:18,091 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [545338526] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:18,091 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:18,091 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:05:18,091 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [676196945] [2021-12-16 10:05:18,091 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:18,091 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:05:18,092 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:05:18,092 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-16 10:05:18,092 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-16 10:05:18,092 INFO L87 Difference]: Start difference. First operand 10489 states and 15397 transitions. cyclomatic complexity: 4916 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 2 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:18,221 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:05:18,221 INFO L93 Difference]: Finished difference Result 20577 states and 29982 transitions. [2021-12-16 10:05:18,222 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-16 10:05:18,222 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 20577 states and 29982 transitions. [2021-12-16 10:05:18,381 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 20319 [2021-12-16 10:05:18,438 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 20577 states to 20577 states and 29982 transitions. [2021-12-16 10:05:18,439 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 20577 [2021-12-16 10:05:18,458 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 20577 [2021-12-16 10:05:18,458 INFO L73 IsDeterministic]: Start isDeterministic. Operand 20577 states and 29982 transitions. [2021-12-16 10:05:18,478 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:05:18,478 INFO L681 BuchiCegarLoop]: Abstraction has 20577 states and 29982 transitions. [2021-12-16 10:05:18,492 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 20577 states and 29982 transitions. [2021-12-16 10:05:18,722 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 20577 to 19913. [2021-12-16 10:05:18,747 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 19913 states, 19913 states have (on average 1.4586451062120223) internal successors, (29046), 19912 states have internal predecessors, (29046), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:18,787 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19913 states to 19913 states and 29046 transitions. [2021-12-16 10:05:18,787 INFO L704 BuchiCegarLoop]: Abstraction has 19913 states and 29046 transitions. [2021-12-16 10:05:18,788 INFO L587 BuchiCegarLoop]: Abstraction has 19913 states and 29046 transitions. [2021-12-16 10:05:18,788 INFO L425 BuchiCegarLoop]: ======== Iteration 16============ [2021-12-16 10:05:18,788 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 19913 states and 29046 transitions. [2021-12-16 10:05:18,846 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 19655 [2021-12-16 10:05:18,846 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:05:18,846 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:05:18,848 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:18,848 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:18,848 INFO L791 eck$LassoCheckResult]: Stem: 95435#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 95436#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 96033#L1653 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 96034#L785 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 95878#L792 assume 1 == ~m_i~0;~m_st~0 := 0; 95879#L792-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 94849#L797-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 94850#L802-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 96476#L807-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 95849#L812-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 95850#L817-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 96182#L822-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 96183#L827-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 96299#L832-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 96410#L837-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 96411#L842-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 96248#L847-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 96052#L1121 assume !(0 == ~M_E~0); 95771#L1121-2 assume !(0 == ~T1_E~0); 95124#L1126-1 assume !(0 == ~T2_E~0); 95125#L1131-1 assume !(0 == ~T3_E~0); 95299#L1136-1 assume !(0 == ~T4_E~0); 95395#L1141-1 assume !(0 == ~T5_E~0); 95625#L1146-1 assume !(0 == ~T6_E~0); 95969#L1151-1 assume !(0 == ~T7_E~0); 95457#L1156-1 assume !(0 == ~T8_E~0); 94835#L1161-1 assume !(0 == ~T9_E~0); 94836#L1166-1 assume !(0 == ~T10_E~0); 95059#L1171-1 assume !(0 == ~T11_E~0); 95060#L1176-1 assume !(0 == ~E_M~0); 95985#L1181-1 assume !(0 == ~E_1~0); 96134#L1186-1 assume !(0 == ~E_2~0); 96198#L1191-1 assume !(0 == ~E_3~0); 95086#L1196-1 assume !(0 == ~E_4~0); 95087#L1201-1 assume !(0 == ~E_5~0); 96496#L1206-1 assume !(0 == ~E_6~0); 96249#L1211-1 assume !(0 == ~E_7~0); 96250#L1216-1 assume !(0 == ~E_8~0); 95231#L1221-1 assume !(0 == ~E_9~0); 95232#L1226-1 assume !(0 == ~E_10~0); 94931#L1231-1 assume !(0 == ~E_11~0); 94932#L1236-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 95986#L556 assume !(1 == ~m_pc~0); 95987#L556-2 is_master_triggered_~__retres1~0#1 := 0; 94808#L567 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 94809#L568 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 95724#L1391 assume !(0 != activate_threads_~tmp~1#1); 96170#L1391-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 96171#L575 assume !(1 == ~t1_pc~0); 94760#L575-2 is_transmit1_triggered_~__retres1~1#1 := 0; 94761#L586 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 94894#L587 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 95244#L1399 assume !(0 != activate_threads_~tmp___0~0#1); 95201#L1399-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 95202#L594 assume 1 == ~t2_pc~0; 95129#L595 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 95130#L605 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 95609#L606 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 94824#L1407 assume !(0 != activate_threads_~tmp___1~0#1); 94825#L1407-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 94883#L613 assume !(1 == ~t3_pc~0); 95002#L613-2 is_transmit3_triggered_~__retres1~3#1 := 0; 95001#L624 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 94927#L625 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 94928#L1415 assume !(0 != activate_threads_~tmp___2~0#1); 95624#L1415-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 95332#L632 assume 1 == ~t4_pc~0; 95333#L633 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 95864#L643 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 96053#L644 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 96499#L1423 assume !(0 != activate_threads_~tmp___3~0#1); 95995#L1423-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 95704#L651 assume 1 == ~t5_pc~0; 95705#L652 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 95014#L662 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 95015#L663 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 95470#L1431 assume !(0 != activate_threads_~tmp___4~0#1); 95031#L1431-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 95032#L670 assume !(1 == ~t6_pc~0); 96226#L670-2 is_transmit6_triggered_~__retres1~6#1 := 0; 95381#L681 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 95382#L682 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 96355#L1439 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 95669#L1439-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 95670#L689 assume 1 == ~t7_pc~0; 96485#L690 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 95791#L700 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 95792#L701 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 96246#L1447 assume !(0 != activate_threads_~tmp___6~0#1); 95566#L1447-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 95567#L708 assume !(1 == ~t8_pc~0); 95120#L708-2 is_transmit8_triggered_~__retres1~8#1 := 0; 95121#L719 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 96354#L720 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 96338#L1455 assume !(0 != activate_threads_~tmp___7~0#1); 95186#L1455-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 95187#L727 assume 1 == ~t9_pc~0; 95312#L728 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 94885#L738 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 96513#L739 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 96514#L1463 assume !(0 != activate_threads_~tmp___8~0#1); 96477#L1463-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 95240#L746 assume !(1 == ~t10_pc~0); 95241#L746-2 is_transmit10_triggered_~__retres1~10#1 := 0; 95943#L757 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 96069#L758 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 96348#L1471 assume !(0 != activate_threads_~tmp___9~0#1); 96175#L1471-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 95404#L765 assume 1 == ~t11_pc~0; 95405#L766 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 95620#L776 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 94773#L777 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 94774#L1479 assume !(0 != activate_threads_~tmp___10~0#1); 96225#L1479-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 96334#L1249 assume 1 == ~M_E~0;~M_E~0 := 2; 96335#L1249-2 assume !(1 == ~T1_E~0); 95491#L1254-1 assume !(1 == ~T2_E~0); 94819#L1259-1 assume !(1 == ~T3_E~0); 94820#L1264-1 assume !(1 == ~T4_E~0); 111850#L1269-1 assume !(1 == ~T5_E~0); 111849#L1274-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 111848#L1279-1 assume !(1 == ~T7_E~0); 95003#L1284-1 assume !(1 == ~T8_E~0); 95004#L1289-1 assume !(1 == ~T9_E~0); 95544#L1294-1 assume !(1 == ~T10_E~0); 95545#L1299-1 assume !(1 == ~T11_E~0); 95554#L1304-1 assume !(1 == ~E_M~0); 96548#L1309-1 assume !(1 == ~E_1~0); 96551#L1314-1 assume 1 == ~E_2~0;~E_2~0 := 2; 96552#L1319-1 assume !(1 == ~E_3~0); 111467#L1324-1 assume !(1 == ~E_4~0); 111462#L1329-1 assume !(1 == ~E_5~0); 111265#L1334-1 assume !(1 == ~E_6~0); 111250#L1339-1 assume !(1 == ~E_7~0); 111248#L1344-1 assume !(1 == ~E_8~0); 111246#L1349-1 assume !(1 == ~E_9~0); 111244#L1354-1 assume 1 == ~E_10~0;~E_10~0 := 2; 111227#L1359-1 assume !(1 == ~E_11~0); 111218#L1364-1 assume { :end_inline_reset_delta_events } true; 111210#L1690-2 [2021-12-16 10:05:18,849 INFO L793 eck$LassoCheckResult]: Loop: 111210#L1690-2 assume !false; 111203#L1691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 111200#L1096 assume !false; 111199#L933 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 111189#L860 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 111186#L922 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 111185#L923 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 111183#L937 assume !(0 != eval_~tmp~0#1); 111184#L1111 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 113379#L785-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 113373#L1121-3 assume 0 == ~M_E~0;~M_E~0 := 1; 113369#L1121-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 113364#L1126-3 assume !(0 == ~T2_E~0); 113359#L1131-3 assume !(0 == ~T3_E~0); 113354#L1136-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 113350#L1141-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 113344#L1146-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 113340#L1151-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 113336#L1156-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 113330#L1161-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 113326#L1166-3 assume !(0 == ~T10_E~0); 113321#L1171-3 assume !(0 == ~T11_E~0); 113315#L1176-3 assume 0 == ~E_M~0;~E_M~0 := 1; 113309#L1181-3 assume 0 == ~E_1~0;~E_1~0 := 1; 113302#L1186-3 assume 0 == ~E_2~0;~E_2~0 := 1; 113295#L1191-3 assume 0 == ~E_3~0;~E_3~0 := 1; 113289#L1196-3 assume 0 == ~E_4~0;~E_4~0 := 1; 113284#L1201-3 assume 0 == ~E_5~0;~E_5~0 := 1; 113278#L1206-3 assume !(0 == ~E_6~0); 113271#L1211-3 assume !(0 == ~E_7~0); 113263#L1216-3 assume 0 == ~E_8~0;~E_8~0 := 1; 113257#L1221-3 assume 0 == ~E_9~0;~E_9~0 := 1; 113252#L1226-3 assume 0 == ~E_10~0;~E_10~0 := 1; 113246#L1231-3 assume 0 == ~E_11~0;~E_11~0 := 1; 113239#L1236-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 113232#L556-39 assume !(1 == ~m_pc~0); 113226#L556-41 is_master_triggered_~__retres1~0#1 := 0; 113221#L567-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 113217#L568-13 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 113212#L1391-39 assume !(0 != activate_threads_~tmp~1#1); 113206#L1391-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 113199#L575-39 assume 1 == ~t1_pc~0; 113191#L576-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 113185#L586-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 113181#L587-13 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 113178#L1399-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 113177#L1399-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 113176#L594-39 assume !(1 == ~t2_pc~0); 113175#L594-41 is_transmit2_triggered_~__retres1~2#1 := 0; 113173#L605-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 113172#L606-13 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 113171#L1407-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 113170#L1407-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 113169#L613-39 assume !(1 == ~t3_pc~0); 113168#L613-41 is_transmit3_triggered_~__retres1~3#1 := 0; 113166#L624-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 113164#L625-13 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 113162#L1415-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 113160#L1415-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 113158#L632-39 assume !(1 == ~t4_pc~0); 113153#L632-41 is_transmit4_triggered_~__retres1~4#1 := 0; 113150#L643-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 113148#L644-13 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 113146#L1423-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 113144#L1423-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 113142#L651-39 assume 1 == ~t5_pc~0; 113139#L652-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 113136#L662-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 113134#L663-13 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 113132#L1431-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 113130#L1431-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 113128#L670-39 assume !(1 == ~t6_pc~0); 113125#L670-41 is_transmit6_triggered_~__retres1~6#1 := 0; 113122#L681-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 113120#L682-13 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 113119#L1439-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 113118#L1439-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 113117#L689-39 assume !(1 == ~t7_pc~0); 113115#L689-41 is_transmit7_triggered_~__retres1~7#1 := 0; 113112#L700-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 113110#L701-13 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 113108#L1447-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 113106#L1447-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 113104#L708-39 assume !(1 == ~t8_pc~0); 113101#L708-41 is_transmit8_triggered_~__retres1~8#1 := 0; 113098#L719-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 113096#L720-13 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 113094#L1455-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 113092#L1455-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 113090#L727-39 assume !(1 == ~t9_pc~0); 113087#L727-41 is_transmit9_triggered_~__retres1~9#1 := 0; 113084#L738-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 113065#L739-13 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 113059#L1463-39 assume !(0 != activate_threads_~tmp___8~0#1); 113052#L1463-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 113047#L746-39 assume !(1 == ~t10_pc~0); 113041#L746-41 is_transmit10_triggered_~__retres1~10#1 := 0; 112322#L757-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 112319#L758-13 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 112317#L1471-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 112315#L1471-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 112313#L765-39 assume 1 == ~t11_pc~0; 112311#L766-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 112287#L776-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 112281#L777-13 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 112275#L1479-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 112269#L1479-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 112266#L1249-3 assume 1 == ~M_E~0;~M_E~0 := 2; 97633#L1249-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 111976#L1254-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 109509#L1259-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 111973#L1264-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 111971#L1269-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 111969#L1274-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 111967#L1279-3 assume !(1 == ~T7_E~0); 111964#L1284-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 111962#L1289-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 111960#L1294-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 95413#L1299-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 111957#L1304-3 assume 1 == ~E_M~0;~E_M~0 := 2; 111955#L1309-3 assume 1 == ~E_1~0;~E_1~0 := 2; 111953#L1314-3 assume 1 == ~E_2~0;~E_2~0 := 2; 111951#L1319-3 assume !(1 == ~E_3~0); 111950#L1324-3 assume 1 == ~E_4~0;~E_4~0 := 2; 111948#L1329-3 assume 1 == ~E_5~0;~E_5~0 := 2; 111880#L1334-3 assume 1 == ~E_6~0;~E_6~0 := 2; 111866#L1339-3 assume 1 == ~E_7~0;~E_7~0 := 2; 111858#L1344-3 assume 1 == ~E_8~0;~E_8~0 := 2; 111855#L1349-3 assume 1 == ~E_9~0;~E_9~0 := 2; 111853#L1354-3 assume 1 == ~E_10~0;~E_10~0 := 2; 111852#L1359-3 assume !(1 == ~E_11~0); 111851#L1364-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 111835#L860-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 111472#L922-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 111469#L923-1 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 111464#L1709 assume !(0 == start_simulation_~tmp~3#1); 95337#L1709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 111260#L860-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 111249#L922-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 111247#L923-2 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 111245#L1664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 111243#L1671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 111226#L1672 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 111217#L1722 assume !(0 != start_simulation_~tmp___0~1#1); 111210#L1690-2 [2021-12-16 10:05:18,849 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:18,849 INFO L85 PathProgramCache]: Analyzing trace with hash -1258502475, now seen corresponding path program 1 times [2021-12-16 10:05:18,850 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:18,850 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [496375241] [2021-12-16 10:05:18,850 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:18,850 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:18,947 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:18,963 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:05:18,963 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:18,963 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [496375241] [2021-12-16 10:05:18,963 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [496375241] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:18,963 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:18,963 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:05:18,964 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1613035235] [2021-12-16 10:05:18,964 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:18,964 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:05:18,964 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:18,964 INFO L85 PathProgramCache]: Analyzing trace with hash -1889352193, now seen corresponding path program 1 times [2021-12-16 10:05:18,964 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:18,965 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2040541445] [2021-12-16 10:05:18,965 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:18,965 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:18,972 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:18,989 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:05:18,989 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:18,989 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2040541445] [2021-12-16 10:05:18,989 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2040541445] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:18,989 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:18,989 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:05:18,990 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [562373324] [2021-12-16 10:05:18,990 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:18,990 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:05:18,990 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:05:18,990 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-16 10:05:18,990 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-16 10:05:18,991 INFO L87 Difference]: Start difference. First operand 19913 states and 29046 transitions. cyclomatic complexity: 9149 Second operand has 4 states, 4 states have (on average 34.75) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:19,336 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:05:19,336 INFO L93 Difference]: Finished difference Result 55703 states and 80484 transitions. [2021-12-16 10:05:19,336 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-16 10:05:19,337 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 55703 states and 80484 transitions. [2021-12-16 10:05:19,741 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 55287 [2021-12-16 10:05:19,919 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 55703 states to 55703 states and 80484 transitions. [2021-12-16 10:05:19,920 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 55703 [2021-12-16 10:05:19,972 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 55703 [2021-12-16 10:05:19,972 INFO L73 IsDeterministic]: Start isDeterministic. Operand 55703 states and 80484 transitions. [2021-12-16 10:05:20,021 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:05:20,022 INFO L681 BuchiCegarLoop]: Abstraction has 55703 states and 80484 transitions. [2021-12-16 10:05:20,061 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 55703 states and 80484 transitions. [2021-12-16 10:05:20,742 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 55703 to 54471. [2021-12-16 10:05:20,808 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 54471 states, 54471 states have (on average 1.446421031374493) internal successors, (78788), 54470 states have internal predecessors, (78788), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:20,917 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 54471 states to 54471 states and 78788 transitions. [2021-12-16 10:05:20,917 INFO L704 BuchiCegarLoop]: Abstraction has 54471 states and 78788 transitions. [2021-12-16 10:05:20,917 INFO L587 BuchiCegarLoop]: Abstraction has 54471 states and 78788 transitions. [2021-12-16 10:05:20,917 INFO L425 BuchiCegarLoop]: ======== Iteration 17============ [2021-12-16 10:05:20,917 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 54471 states and 78788 transitions. [2021-12-16 10:05:21,087 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 54151 [2021-12-16 10:05:21,087 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:05:21,087 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:05:21,089 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:21,089 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:21,089 INFO L791 eck$LassoCheckResult]: Stem: 171061#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 171062#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 171686#L1653 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 171687#L785 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 171518#L792 assume 1 == ~m_i~0;~m_st~0 := 0; 171519#L792-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 170475#L797-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 170476#L802-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 172149#L807-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 171488#L812-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 171489#L817-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 171845#L822-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 171846#L827-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 171973#L832-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 172088#L837-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 172089#L842-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 171915#L847-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 171705#L1121 assume !(0 == ~M_E~0); 171405#L1121-2 assume !(0 == ~T1_E~0); 170748#L1126-1 assume !(0 == ~T2_E~0); 170749#L1131-1 assume !(0 == ~T3_E~0); 170920#L1136-1 assume !(0 == ~T4_E~0); 171017#L1141-1 assume !(0 == ~T5_E~0); 171256#L1146-1 assume !(0 == ~T6_E~0); 171620#L1151-1 assume !(0 == ~T7_E~0); 171079#L1156-1 assume !(0 == ~T8_E~0); 170461#L1161-1 assume !(0 == ~T9_E~0); 170462#L1166-1 assume !(0 == ~T10_E~0); 170683#L1171-1 assume !(0 == ~T11_E~0); 170684#L1176-1 assume !(0 == ~E_M~0); 171635#L1181-1 assume !(0 == ~E_1~0); 171793#L1186-1 assume !(0 == ~E_2~0); 171867#L1191-1 assume !(0 == ~E_3~0); 170710#L1196-1 assume !(0 == ~E_4~0); 170711#L1201-1 assume !(0 == ~E_5~0); 172170#L1206-1 assume !(0 == ~E_6~0); 171916#L1211-1 assume !(0 == ~E_7~0); 171917#L1216-1 assume !(0 == ~E_8~0); 170856#L1221-1 assume !(0 == ~E_9~0); 170857#L1226-1 assume !(0 == ~E_10~0); 170557#L1231-1 assume !(0 == ~E_11~0); 170558#L1236-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 171640#L556 assume !(1 == ~m_pc~0); 171641#L556-2 is_master_triggered_~__retres1~0#1 := 0; 170434#L567 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 170435#L568 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 171355#L1391 assume !(0 != activate_threads_~tmp~1#1); 171832#L1391-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 171833#L575 assume !(1 == ~t1_pc~0); 170386#L575-2 is_transmit1_triggered_~__retres1~1#1 := 0; 170387#L586 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 170520#L587 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 170866#L1399 assume !(0 != activate_threads_~tmp___0~0#1); 170823#L1399-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 170824#L594 assume !(1 == ~t2_pc~0); 171605#L594-2 is_transmit2_triggered_~__retres1~2#1 := 0; 171721#L605 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 171234#L606 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 170452#L1407 assume !(0 != activate_threads_~tmp___1~0#1); 170453#L1407-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 170509#L613 assume !(1 == ~t3_pc~0); 170626#L613-2 is_transmit3_triggered_~__retres1~3#1 := 0; 170625#L624 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 170553#L625 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 170554#L1415 assume !(0 != activate_threads_~tmp___2~0#1); 171250#L1415-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 170953#L632 assume 1 == ~t4_pc~0; 170954#L633 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 171505#L643 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 171706#L644 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 172173#L1423 assume !(0 != activate_threads_~tmp___3~0#1); 171648#L1423-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 171334#L651 assume 1 == ~t5_pc~0; 171335#L652 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 170638#L662 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 170639#L663 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 171091#L1431 assume !(0 != activate_threads_~tmp___4~0#1); 170656#L1431-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 170657#L670 assume !(1 == ~t6_pc~0); 171895#L670-2 is_transmit6_triggered_~__retres1~6#1 := 0; 171008#L681 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 171009#L682 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 172031#L1439 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 171296#L1439-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 171297#L689 assume 1 == ~t7_pc~0; 172159#L690 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 171424#L700 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 171425#L701 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 171913#L1447 assume !(0 != activate_threads_~tmp___6~0#1); 171191#L1447-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 171192#L708 assume !(1 == ~t8_pc~0); 170743#L708-2 is_transmit8_triggered_~__retres1~8#1 := 0; 170744#L719 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 172028#L720 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 172008#L1455 assume !(0 != activate_threads_~tmp___7~0#1); 170806#L1455-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 170807#L727 assume 1 == ~t9_pc~0; 170933#L728 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 170511#L738 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 172187#L739 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 172188#L1463 assume !(0 != activate_threads_~tmp___8~0#1); 172152#L1463-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 170863#L746 assume !(1 == ~t10_pc~0); 170864#L746-2 is_transmit10_triggered_~__retres1~10#1 := 0; 171586#L757 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 171727#L758 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 172021#L1471 assume !(0 != activate_threads_~tmp___9~0#1); 171837#L1471-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 171029#L765 assume 1 == ~t11_pc~0; 171030#L766 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 171245#L776 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 170399#L777 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 170400#L1479 assume !(0 != activate_threads_~tmp___10~0#1); 171893#L1479-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 172004#L1249 assume 1 == ~M_E~0;~M_E~0 := 2; 172005#L1249-2 assume !(1 == ~T1_E~0); 171114#L1254-1 assume !(1 == ~T2_E~0); 170445#L1259-1 assume !(1 == ~T3_E~0); 170446#L1264-1 assume !(1 == ~T4_E~0); 172281#L1269-1 assume !(1 == ~T5_E~0); 172282#L1274-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 172106#L1279-1 assume !(1 == ~T7_E~0); 172107#L1284-1 assume !(1 == ~T8_E~0); 172190#L1289-1 assume !(1 == ~T9_E~0); 172191#L1294-1 assume !(1 == ~T10_E~0); 178056#L1299-1 assume !(1 == ~T11_E~0); 178053#L1304-1 assume !(1 == ~E_M~0); 178050#L1309-1 assume !(1 == ~E_1~0); 178047#L1314-1 assume 1 == ~E_2~0;~E_2~0 := 2; 178043#L1319-1 assume !(1 == ~E_3~0); 178040#L1324-1 assume !(1 == ~E_4~0); 178037#L1329-1 assume !(1 == ~E_5~0); 178034#L1334-1 assume !(1 == ~E_6~0); 178030#L1339-1 assume !(1 == ~E_7~0); 178028#L1344-1 assume !(1 == ~E_8~0); 178026#L1349-1 assume !(1 == ~E_9~0); 178024#L1354-1 assume 1 == ~E_10~0;~E_10~0 := 2; 178022#L1359-1 assume !(1 == ~E_11~0); 177891#L1364-1 assume { :end_inline_reset_delta_events } true; 177776#L1690-2 [2021-12-16 10:05:21,090 INFO L793 eck$LassoCheckResult]: Loop: 177776#L1690-2 assume !false; 177724#L1691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 177656#L1096 assume !false; 177655#L933 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 177605#L860 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 177600#L922 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 177598#L923 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 177595#L937 assume !(0 != eval_~tmp~0#1); 177596#L1111 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 180972#L785-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 180970#L1121-3 assume 0 == ~M_E~0;~M_E~0 := 1; 180968#L1121-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 180966#L1126-3 assume !(0 == ~T2_E~0); 180963#L1131-3 assume !(0 == ~T3_E~0); 180961#L1136-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 180959#L1141-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 180957#L1146-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 180955#L1151-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 180953#L1156-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 180950#L1161-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 180948#L1166-3 assume !(0 == ~T10_E~0); 180946#L1171-3 assume !(0 == ~T11_E~0); 180944#L1176-3 assume 0 == ~E_M~0;~E_M~0 := 1; 180942#L1181-3 assume 0 == ~E_1~0;~E_1~0 := 1; 180940#L1186-3 assume 0 == ~E_2~0;~E_2~0 := 1; 180937#L1191-3 assume 0 == ~E_3~0;~E_3~0 := 1; 180935#L1196-3 assume 0 == ~E_4~0;~E_4~0 := 1; 180933#L1201-3 assume 0 == ~E_5~0;~E_5~0 := 1; 180931#L1206-3 assume !(0 == ~E_6~0); 180929#L1211-3 assume !(0 == ~E_7~0); 180927#L1216-3 assume 0 == ~E_8~0;~E_8~0 := 1; 180924#L1221-3 assume 0 == ~E_9~0;~E_9~0 := 1; 180922#L1226-3 assume 0 == ~E_10~0;~E_10~0 := 1; 180920#L1231-3 assume 0 == ~E_11~0;~E_11~0 := 1; 180918#L1236-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 180916#L556-39 assume !(1 == ~m_pc~0); 180914#L556-41 is_master_triggered_~__retres1~0#1 := 0; 180911#L567-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 180909#L568-13 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 180907#L1391-39 assume !(0 != activate_threads_~tmp~1#1); 180905#L1391-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 180903#L575-39 assume !(1 == ~t1_pc~0); 180901#L575-41 is_transmit1_triggered_~__retres1~1#1 := 0; 180899#L586-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 180897#L587-13 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 180896#L1399-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 180895#L1399-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 180894#L594-39 assume !(1 == ~t2_pc~0); 180893#L594-41 is_transmit2_triggered_~__retres1~2#1 := 0; 180892#L605-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 180891#L606-13 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 180890#L1407-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 180889#L1407-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 180888#L613-39 assume 1 == ~t3_pc~0; 180886#L614-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 180885#L624-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 180884#L625-13 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 180883#L1415-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 180882#L1415-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 180881#L632-39 assume 1 == ~t4_pc~0; 180880#L633-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 180878#L643-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 180877#L644-13 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 180876#L1423-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 180875#L1423-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 180873#L651-39 assume 1 == ~t5_pc~0; 180870#L652-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 180868#L662-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 180866#L663-13 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 180864#L1431-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 180862#L1431-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 180860#L670-39 assume 1 == ~t6_pc~0; 180858#L671-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 180855#L681-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 180853#L682-13 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 180851#L1439-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 180849#L1439-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 180847#L689-39 assume 1 == ~t7_pc~0; 180844#L690-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 180842#L700-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 180840#L701-13 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 180838#L1447-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 180836#L1447-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 180834#L708-39 assume !(1 == ~t8_pc~0); 180830#L708-41 is_transmit8_triggered_~__retres1~8#1 := 0; 180828#L719-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 180826#L720-13 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 180824#L1455-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 180822#L1455-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 180820#L727-39 assume 1 == ~t9_pc~0; 180816#L728-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 180814#L738-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 180812#L739-13 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 180810#L1463-39 assume !(0 != activate_threads_~tmp___8~0#1); 180808#L1463-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 180806#L746-39 assume 1 == ~t10_pc~0; 180802#L747-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 180800#L757-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 180798#L758-13 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 180796#L1471-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 180794#L1471-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 180792#L765-39 assume !(1 == ~t11_pc~0); 180788#L765-41 is_transmit11_triggered_~__retres1~11#1 := 0; 180786#L776-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 180784#L777-13 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 180782#L1479-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 180780#L1479-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 180778#L1249-3 assume 1 == ~M_E~0;~M_E~0 := 2; 178273#L1249-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 178774#L1254-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 178770#L1259-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 178768#L1264-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 178766#L1269-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 178762#L1274-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 178760#L1279-3 assume !(1 == ~T7_E~0); 178758#L1284-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 178756#L1289-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 178234#L1294-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 178230#L1299-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 178228#L1304-3 assume 1 == ~E_M~0;~E_M~0 := 2; 178226#L1309-3 assume 1 == ~E_1~0;~E_1~0 := 2; 178222#L1314-3 assume 1 == ~E_2~0;~E_2~0 := 2; 178220#L1319-3 assume !(1 == ~E_3~0); 178177#L1324-3 assume 1 == ~E_4~0;~E_4~0 := 2; 178163#L1329-3 assume 1 == ~E_5~0;~E_5~0 := 2; 178153#L1334-3 assume 1 == ~E_6~0;~E_6~0 := 2; 178143#L1339-3 assume 1 == ~E_7~0;~E_7~0 := 2; 178132#L1344-3 assume 1 == ~E_8~0;~E_8~0 := 2; 178119#L1349-3 assume 1 == ~E_9~0;~E_9~0 := 2; 178117#L1354-3 assume 1 == ~E_10~0;~E_10~0 := 2; 178115#L1359-3 assume !(1 == ~E_11~0); 178112#L1364-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 178099#L860-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 178094#L922-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 178091#L923-1 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 178088#L1709 assume !(0 == start_simulation_~tmp~3#1); 178086#L1709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 177914#L860-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 177903#L922-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 177900#L923-2 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 177898#L1664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 177896#L1671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 177894#L1672 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 177890#L1722 assume !(0 != start_simulation_~tmp___0~1#1); 177776#L1690-2 [2021-12-16 10:05:21,090 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:21,090 INFO L85 PathProgramCache]: Analyzing trace with hash 1819278198, now seen corresponding path program 1 times [2021-12-16 10:05:21,091 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:21,091 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [499681945] [2021-12-16 10:05:21,091 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:21,091 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:21,103 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:21,328 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:05:21,328 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:21,328 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [499681945] [2021-12-16 10:05:21,328 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [499681945] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:21,329 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:21,329 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:05:21,329 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1639811580] [2021-12-16 10:05:21,329 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:21,329 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:05:21,329 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:21,329 INFO L85 PathProgramCache]: Analyzing trace with hash 73035451, now seen corresponding path program 1 times [2021-12-16 10:05:21,329 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:21,329 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [221327815] [2021-12-16 10:05:21,330 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:21,330 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:21,338 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:21,354 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:05:21,354 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:21,354 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [221327815] [2021-12-16 10:05:21,354 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [221327815] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:21,354 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:21,354 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:05:21,354 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1276344160] [2021-12-16 10:05:21,355 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:21,355 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:05:21,355 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:05:21,355 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-16 10:05:21,355 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-16 10:05:21,356 INFO L87 Difference]: Start difference. First operand 54471 states and 78788 transitions. cyclomatic complexity: 24349 Second operand has 4 states, 4 states have (on average 34.75) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:22,057 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:05:22,057 INFO L93 Difference]: Finished difference Result 153364 states and 220167 transitions. [2021-12-16 10:05:22,058 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-16 10:05:22,058 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 153364 states and 220167 transitions. [2021-12-16 10:05:22,969 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 152565 [2021-12-16 10:05:23,415 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 153364 states to 153364 states and 220167 transitions. [2021-12-16 10:05:23,415 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 153364 [2021-12-16 10:05:23,609 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 153364 [2021-12-16 10:05:23,609 INFO L73 IsDeterministic]: Start isDeterministic. Operand 153364 states and 220167 transitions. [2021-12-16 10:05:23,732 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:05:23,751 INFO L681 BuchiCegarLoop]: Abstraction has 153364 states and 220167 transitions. [2021-12-16 10:05:23,858 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 153364 states and 220167 transitions. [2021-12-16 10:05:25,575 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 153364 to 150308. [2021-12-16 10:05:25,779 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 150308 states, 150308 states have (on average 1.43688293370945) internal successors, (215975), 150307 states have internal predecessors, (215975), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:26,160 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 150308 states to 150308 states and 215975 transitions. [2021-12-16 10:05:26,160 INFO L704 BuchiCegarLoop]: Abstraction has 150308 states and 215975 transitions. [2021-12-16 10:05:26,160 INFO L587 BuchiCegarLoop]: Abstraction has 150308 states and 215975 transitions. [2021-12-16 10:05:26,160 INFO L425 BuchiCegarLoop]: ======== Iteration 18============ [2021-12-16 10:05:26,160 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 150308 states and 215975 transitions. [2021-12-16 10:05:26,880 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 149829 [2021-12-16 10:05:26,880 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:05:26,891 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:05:26,902 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:26,902 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:26,902 INFO L791 eck$LassoCheckResult]: Stem: 378904#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 378905#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 379502#L1653 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 379503#L785 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 379339#L792 assume 1 == ~m_i~0;~m_st~0 := 0; 379340#L792-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 378320#L797-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 378321#L802-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 379929#L807-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 379313#L812-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 379314#L817-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 379658#L822-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 379659#L827-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 379763#L832-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 379878#L837-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 379879#L842-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 379720#L847-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 379521#L1121 assume !(0 == ~M_E~0); 379232#L1121-2 assume !(0 == ~T1_E~0); 378593#L1126-1 assume !(0 == ~T2_E~0); 378594#L1131-1 assume !(0 == ~T3_E~0); 378763#L1136-1 assume !(0 == ~T4_E~0); 378861#L1141-1 assume !(0 == ~T5_E~0); 379097#L1146-1 assume !(0 == ~T6_E~0); 379430#L1151-1 assume !(0 == ~T7_E~0); 378921#L1156-1 assume !(0 == ~T8_E~0); 378305#L1161-1 assume !(0 == ~T9_E~0); 378306#L1166-1 assume !(0 == ~T10_E~0); 378527#L1171-1 assume !(0 == ~T11_E~0); 378528#L1176-1 assume !(0 == ~E_M~0); 379446#L1181-1 assume !(0 == ~E_1~0); 379613#L1186-1 assume !(0 == ~E_2~0); 379678#L1191-1 assume !(0 == ~E_3~0); 378554#L1196-1 assume !(0 == ~E_4~0); 378555#L1201-1 assume !(0 == ~E_5~0); 379953#L1206-1 assume !(0 == ~E_6~0); 379721#L1211-1 assume !(0 == ~E_7~0); 379722#L1216-1 assume !(0 == ~E_8~0); 378700#L1221-1 assume !(0 == ~E_9~0); 378701#L1226-1 assume !(0 == ~E_10~0); 378400#L1231-1 assume !(0 == ~E_11~0); 378401#L1236-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 379448#L556 assume !(1 == ~m_pc~0); 379449#L556-2 is_master_triggered_~__retres1~0#1 := 0; 378279#L567 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 378280#L568 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 379191#L1391 assume !(0 != activate_threads_~tmp~1#1); 379646#L1391-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 379647#L575 assume !(1 == ~t1_pc~0); 378231#L575-2 is_transmit1_triggered_~__retres1~1#1 := 0; 378232#L586 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 378364#L587 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 378710#L1399 assume !(0 != activate_threads_~tmp___0~0#1); 378667#L1399-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 378668#L594 assume !(1 == ~t2_pc~0); 379417#L594-2 is_transmit2_triggered_~__retres1~2#1 := 0; 379537#L605 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 379076#L606 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 378296#L1407 assume !(0 != activate_threads_~tmp___1~0#1); 378297#L1407-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 378354#L613 assume !(1 == ~t3_pc~0); 378470#L613-2 is_transmit3_triggered_~__retres1~3#1 := 0; 378469#L624 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 378396#L625 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 378397#L1415 assume !(0 != activate_threads_~tmp___2~0#1); 379091#L1415-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 378801#L632 assume !(1 == ~t4_pc~0); 378802#L632-2 is_transmit4_triggered_~__retres1~4#1 := 0; 379522#L643 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 379523#L644 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 379954#L1423 assume !(0 != activate_threads_~tmp___3~0#1); 379456#L1423-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 379173#L651 assume 1 == ~t5_pc~0; 379174#L652 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 378482#L662 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 378483#L663 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 378933#L1431 assume !(0 != activate_threads_~tmp___4~0#1); 378499#L1431-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 378500#L670 assume !(1 == ~t6_pc~0); 379703#L670-2 is_transmit6_triggered_~__retres1~6#1 := 0; 378852#L681 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 378853#L682 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 379820#L1439 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 379138#L1439-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 379139#L689 assume 1 == ~t7_pc~0; 379945#L690 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 379251#L700 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 379252#L701 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 379718#L1447 assume !(0 != activate_threads_~tmp___6~0#1); 379030#L1447-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 379031#L708 assume !(1 == ~t8_pc~0); 378588#L708-2 is_transmit8_triggered_~__retres1~8#1 := 0; 378589#L719 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 379818#L720 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 379797#L1455 assume !(0 != activate_threads_~tmp___7~0#1); 378651#L1455-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 378652#L727 assume 1 == ~t9_pc~0; 378778#L728 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 378356#L738 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 379960#L739 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 379961#L1463 assume !(0 != activate_threads_~tmp___8~0#1); 379934#L1463-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 378707#L746 assume !(1 == ~t10_pc~0); 378708#L746-2 is_transmit10_triggered_~__retres1~10#1 := 0; 379401#L757 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 379544#L758 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 379810#L1471 assume !(0 != activate_threads_~tmp___9~0#1); 379649#L1471-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 378874#L765 assume 1 == ~t11_pc~0; 378875#L766 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 379086#L776 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 378244#L777 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 378245#L1479 assume !(0 != activate_threads_~tmp___10~0#1); 379701#L1479-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 379793#L1249 assume 1 == ~M_E~0;~M_E~0 := 2; 379332#L1249-2 assume !(1 == ~T1_E~0); 378954#L1254-1 assume !(1 == ~T2_E~0); 378290#L1259-1 assume !(1 == ~T3_E~0); 378272#L1264-1 assume !(1 == ~T4_E~0); 378273#L1269-1 assume !(1 == ~T5_E~0); 380015#L1274-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 379892#L1279-1 assume !(1 == ~T7_E~0); 378471#L1284-1 assume !(1 == ~T8_E~0); 378472#L1289-1 assume !(1 == ~T9_E~0); 379008#L1294-1 assume !(1 == ~T10_E~0); 379009#L1299-1 assume !(1 == ~T11_E~0); 379018#L1304-1 assume !(1 == ~E_M~0); 379993#L1309-1 assume !(1 == ~E_1~0); 379999#L1314-1 assume 1 == ~E_2~0;~E_2~0 := 2; 378419#L1319-1 assume !(1 == ~E_3~0); 378420#L1324-1 assume !(1 == ~E_4~0); 378549#L1329-1 assume !(1 == ~E_5~0); 378550#L1334-1 assume !(1 == ~E_6~0); 379748#L1339-1 assume !(1 == ~E_7~0); 483955#L1344-1 assume !(1 == ~E_8~0); 483952#L1349-1 assume !(1 == ~E_9~0); 483949#L1354-1 assume 1 == ~E_10~0;~E_10~0 := 2; 483946#L1359-1 assume !(1 == ~E_11~0); 483942#L1364-1 assume { :end_inline_reset_delta_events } true; 483943#L1690-2 [2021-12-16 10:05:26,903 INFO L793 eck$LassoCheckResult]: Loop: 483943#L1690-2 assume !false; 524524#L1691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 524521#L1096 assume !false; 524520#L933 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 524510#L860 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 524507#L922 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 524506#L923 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 524504#L937 assume !(0 != eval_~tmp~0#1); 524505#L1111 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 524721#L785-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 524720#L1121-3 assume 0 == ~M_E~0;~M_E~0 := 1; 524719#L1121-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 524718#L1126-3 assume !(0 == ~T2_E~0); 524717#L1131-3 assume !(0 == ~T3_E~0); 524716#L1136-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 524715#L1141-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 524714#L1146-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 524713#L1151-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 524712#L1156-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 524711#L1161-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 524710#L1166-3 assume !(0 == ~T10_E~0); 524709#L1171-3 assume !(0 == ~T11_E~0); 524708#L1176-3 assume 0 == ~E_M~0;~E_M~0 := 1; 524707#L1181-3 assume 0 == ~E_1~0;~E_1~0 := 1; 524706#L1186-3 assume 0 == ~E_2~0;~E_2~0 := 1; 524705#L1191-3 assume 0 == ~E_3~0;~E_3~0 := 1; 524704#L1196-3 assume 0 == ~E_4~0;~E_4~0 := 1; 524703#L1201-3 assume 0 == ~E_5~0;~E_5~0 := 1; 524702#L1206-3 assume !(0 == ~E_6~0); 524701#L1211-3 assume !(0 == ~E_7~0); 524700#L1216-3 assume 0 == ~E_8~0;~E_8~0 := 1; 524699#L1221-3 assume 0 == ~E_9~0;~E_9~0 := 1; 524698#L1226-3 assume 0 == ~E_10~0;~E_10~0 := 1; 524697#L1231-3 assume 0 == ~E_11~0;~E_11~0 := 1; 524696#L1236-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 524695#L556-39 assume !(1 == ~m_pc~0); 524694#L556-41 is_master_triggered_~__retres1~0#1 := 0; 524693#L567-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 524692#L568-13 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 524691#L1391-39 assume !(0 != activate_threads_~tmp~1#1); 524690#L1391-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 524689#L575-39 assume !(1 == ~t1_pc~0); 524688#L575-41 is_transmit1_triggered_~__retres1~1#1 := 0; 524687#L586-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 524686#L587-13 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 524685#L1399-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 524684#L1399-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 524683#L594-39 assume !(1 == ~t2_pc~0); 524682#L594-41 is_transmit2_triggered_~__retres1~2#1 := 0; 524681#L605-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 524680#L606-13 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 524679#L1407-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 524678#L1407-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 524677#L613-39 assume 1 == ~t3_pc~0; 524675#L614-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 524674#L624-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 524673#L625-13 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 524672#L1415-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 524671#L1415-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 524670#L632-39 assume !(1 == ~t4_pc~0); 524669#L632-41 is_transmit4_triggered_~__retres1~4#1 := 0; 524668#L643-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 524667#L644-13 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 524666#L1423-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 524665#L1423-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 524664#L651-39 assume 1 == ~t5_pc~0; 524662#L652-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 524661#L662-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 524660#L663-13 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 524659#L1431-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 524658#L1431-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 524657#L670-39 assume !(1 == ~t6_pc~0); 524655#L670-41 is_transmit6_triggered_~__retres1~6#1 := 0; 524654#L681-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 524653#L682-13 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 524652#L1439-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 524651#L1439-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 524650#L689-39 assume 1 == ~t7_pc~0; 524648#L690-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 524647#L700-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 524646#L701-13 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 524645#L1447-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 524644#L1447-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 524643#L708-39 assume !(1 == ~t8_pc~0); 524641#L708-41 is_transmit8_triggered_~__retres1~8#1 := 0; 524640#L719-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 524639#L720-13 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 524638#L1455-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 524637#L1455-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 524636#L727-39 assume 1 == ~t9_pc~0; 524634#L728-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 524633#L738-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 524632#L739-13 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 524631#L1463-39 assume !(0 != activate_threads_~tmp___8~0#1); 524630#L1463-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 524629#L746-39 assume 1 == ~t10_pc~0; 524627#L747-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 524626#L757-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 524625#L758-13 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 524624#L1471-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 524623#L1471-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 524622#L765-39 assume !(1 == ~t11_pc~0); 524620#L765-41 is_transmit11_triggered_~__retres1~11#1 := 0; 524619#L776-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 524618#L777-13 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 524617#L1479-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 524616#L1479-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 524615#L1249-3 assume 1 == ~M_E~0;~M_E~0 := 2; 473746#L1249-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 524614#L1254-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 524234#L1259-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 524613#L1264-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 524612#L1269-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 524611#L1274-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 524610#L1279-3 assume !(1 == ~T7_E~0); 524609#L1284-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 524608#L1289-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 524607#L1294-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 484055#L1299-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 524606#L1304-3 assume 1 == ~E_M~0;~E_M~0 := 2; 524605#L1309-3 assume 1 == ~E_1~0;~E_1~0 := 2; 524604#L1314-3 assume 1 == ~E_2~0;~E_2~0 := 2; 524603#L1319-3 assume !(1 == ~E_3~0); 524602#L1324-3 assume 1 == ~E_4~0;~E_4~0 := 2; 524601#L1329-3 assume 1 == ~E_5~0;~E_5~0 := 2; 524600#L1334-3 assume 1 == ~E_6~0;~E_6~0 := 2; 473706#L1339-3 assume 1 == ~E_7~0;~E_7~0 := 2; 524599#L1344-3 assume 1 == ~E_8~0;~E_8~0 := 2; 524598#L1349-3 assume 1 == ~E_9~0;~E_9~0 := 2; 524597#L1354-3 assume 1 == ~E_10~0;~E_10~0 := 2; 524596#L1359-3 assume !(1 == ~E_11~0); 524595#L1364-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 484005#L860-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 484003#L922-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 483994#L923-1 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 483995#L1709 assume !(0 == start_simulation_~tmp~3#1); 483987#L1709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 483988#L860-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 524537#L922-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 524536#L923-2 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 524535#L1664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 524534#L1671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 524533#L1672 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 524532#L1722 assume !(0 != start_simulation_~tmp___0~1#1); 483943#L1690-2 [2021-12-16 10:05:26,903 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:26,903 INFO L85 PathProgramCache]: Analyzing trace with hash -343701065, now seen corresponding path program 1 times [2021-12-16 10:05:26,903 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:26,904 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2094001170] [2021-12-16 10:05:26,904 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:26,904 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:26,912 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:26,950 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:05:26,951 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:26,951 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2094001170] [2021-12-16 10:05:26,951 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2094001170] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:26,951 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:26,951 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:05:26,951 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [197321260] [2021-12-16 10:05:26,951 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:26,952 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:05:26,952 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:26,952 INFO L85 PathProgramCache]: Analyzing trace with hash 987836861, now seen corresponding path program 1 times [2021-12-16 10:05:26,952 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:26,952 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [737078697] [2021-12-16 10:05:26,953 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:26,953 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:26,961 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:26,976 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:05:26,976 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:26,976 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [737078697] [2021-12-16 10:05:26,977 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [737078697] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:26,977 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:26,977 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:05:26,977 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [288700124] [2021-12-16 10:05:26,977 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:26,977 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:05:26,978 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:05:26,978 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-16 10:05:26,978 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-16 10:05:26,978 INFO L87 Difference]: Start difference. First operand 150308 states and 215975 transitions. cyclomatic complexity: 65731 Second operand has 4 states, 4 states have (on average 34.75) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:29,110 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:05:29,111 INFO L93 Difference]: Finished difference Result 432601 states and 616978 transitions. [2021-12-16 10:05:29,111 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-16 10:05:29,112 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 432601 states and 616978 transitions. [2021-12-16 10:05:31,472 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 430811 [2021-12-16 10:05:33,086 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 432601 states to 432601 states and 616978 transitions. [2021-12-16 10:05:33,087 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 432601 [2021-12-16 10:05:33,335 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 432601 [2021-12-16 10:05:33,336 INFO L73 IsDeterministic]: Start isDeterministic. Operand 432601 states and 616978 transitions. [2021-12-16 10:05:33,542 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:05:33,542 INFO L681 BuchiCegarLoop]: Abstraction has 432601 states and 616978 transitions. [2021-12-16 10:05:33,875 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 432601 states and 616978 transitions. [2021-12-16 10:05:38,231 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 432601 to 428105. [2021-12-16 10:05:38,703 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 428105 states, 428105 states have (on average 1.4269256374020391) internal successors, (610874), 428104 states have internal predecessors, (610874), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:40,599 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 428105 states to 428105 states and 610874 transitions. [2021-12-16 10:05:40,600 INFO L704 BuchiCegarLoop]: Abstraction has 428105 states and 610874 transitions. [2021-12-16 10:05:40,600 INFO L587 BuchiCegarLoop]: Abstraction has 428105 states and 610874 transitions. [2021-12-16 10:05:40,600 INFO L425 BuchiCegarLoop]: ======== Iteration 19============ [2021-12-16 10:05:40,600 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 428105 states and 610874 transitions. [2021-12-16 10:05:42,163 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 427211 [2021-12-16 10:05:42,163 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:05:42,163 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:05:42,165 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:42,165 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:42,165 INFO L791 eck$LassoCheckResult]: Stem: 961817#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 961818#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 962414#L1653 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 962415#L785 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 962257#L792 assume 1 == ~m_i~0;~m_st~0 := 0; 962258#L792-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 961240#L797-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 961241#L802-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 962831#L807-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 962232#L812-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 962233#L817-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 962564#L822-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 962565#L827-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 962672#L832-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 962780#L837-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 962781#L842-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 962623#L847-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 962432#L1121 assume !(0 == ~M_E~0); 962155#L1121-2 assume !(0 == ~T1_E~0); 961512#L1126-1 assume !(0 == ~T2_E~0); 961513#L1131-1 assume !(0 == ~T3_E~0); 961683#L1136-1 assume !(0 == ~T4_E~0); 961777#L1141-1 assume !(0 == ~T5_E~0); 962017#L1146-1 assume !(0 == ~T6_E~0); 962345#L1151-1 assume !(0 == ~T7_E~0); 961838#L1156-1 assume !(0 == ~T8_E~0); 961226#L1161-1 assume !(0 == ~T9_E~0); 961227#L1166-1 assume !(0 == ~T10_E~0); 961448#L1171-1 assume !(0 == ~T11_E~0); 961449#L1176-1 assume !(0 == ~E_M~0); 962363#L1181-1 assume !(0 == ~E_1~0); 962516#L1186-1 assume !(0 == ~E_2~0); 962578#L1191-1 assume !(0 == ~E_3~0); 961475#L1196-1 assume !(0 == ~E_4~0); 961476#L1201-1 assume !(0 == ~E_5~0); 962844#L1206-1 assume !(0 == ~E_6~0); 962624#L1211-1 assume !(0 == ~E_7~0); 962625#L1216-1 assume !(0 == ~E_8~0); 961615#L1221-1 assume !(0 == ~E_9~0); 961616#L1226-1 assume !(0 == ~E_10~0); 961322#L1231-1 assume !(0 == ~E_11~0); 961323#L1236-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 962364#L556 assume !(1 == ~m_pc~0); 962365#L556-2 is_master_triggered_~__retres1~0#1 := 0; 961199#L567 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 961200#L568 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 962112#L1391 assume !(0 != activate_threads_~tmp~1#1); 962551#L1391-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 962552#L575 assume !(1 == ~t1_pc~0); 961150#L575-2 is_transmit1_triggered_~__retres1~1#1 := 0; 961151#L586 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 961284#L587 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 961630#L1399 assume !(0 != activate_threads_~tmp___0~0#1); 961585#L1399-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 961586#L594 assume !(1 == ~t2_pc~0); 962326#L594-2 is_transmit2_triggered_~__retres1~2#1 := 0; 962446#L605 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 962000#L606 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 961215#L1407 assume !(0 != activate_threads_~tmp___1~0#1); 961216#L1407-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 961274#L613 assume !(1 == ~t3_pc~0); 961390#L613-2 is_transmit3_triggered_~__retres1~3#1 := 0; 961389#L624 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 961318#L625 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 961319#L1415 assume !(0 != activate_threads_~tmp___2~0#1); 962016#L1415-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 961716#L632 assume !(1 == ~t4_pc~0); 961717#L632-2 is_transmit4_triggered_~__retres1~4#1 := 0; 962433#L643 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 962434#L644 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 962846#L1423 assume !(0 != activate_threads_~tmp___3~0#1); 962372#L1423-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 962095#L651 assume !(1 == ~t5_pc~0); 962096#L651-2 is_transmit5_triggered_~__retres1~5#1 := 0; 961402#L662 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 961403#L663 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 961850#L1431 assume !(0 != activate_threads_~tmp___4~0#1); 961420#L1431-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 961421#L670 assume !(1 == ~t6_pc~0); 962601#L670-2 is_transmit6_triggered_~__retres1~6#1 := 0; 961763#L681 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 961764#L682 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 962721#L1439 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 962059#L1439-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 962060#L689 assume 1 == ~t7_pc~0; 962838#L690 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 962173#L700 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 962174#L701 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 962621#L1447 assume !(0 != activate_threads_~tmp___6~0#1); 961953#L1447-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 961954#L708 assume !(1 == ~t8_pc~0); 961508#L708-2 is_transmit8_triggered_~__retres1~8#1 := 0; 961509#L719 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 962720#L720 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 962706#L1455 assume !(0 != activate_threads_~tmp___7~0#1); 961570#L1455-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 961571#L727 assume 1 == ~t9_pc~0; 961696#L728 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 961276#L738 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 962856#L739 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 962857#L1463 assume !(0 != activate_threads_~tmp___8~0#1); 962832#L1463-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 961626#L746 assume !(1 == ~t10_pc~0); 961627#L746-2 is_transmit10_triggered_~__retres1~10#1 := 0; 962314#L757 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 962452#L758 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 962714#L1471 assume !(0 != activate_threads_~tmp___9~0#1); 962557#L1471-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 961787#L765 assume 1 == ~t11_pc~0; 961788#L766 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 962010#L776 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 961164#L777 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 961165#L1479 assume !(0 != activate_threads_~tmp___10~0#1); 962600#L1479-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 962702#L1249 assume 1 == ~M_E~0;~M_E~0 := 2; 962703#L1249-2 assume !(1 == ~T1_E~0); 961872#L1254-1 assume !(1 == ~T2_E~0); 961873#L1259-1 assume !(1 == ~T3_E~0); 961192#L1264-1 assume !(1 == ~T4_E~0); 961193#L1269-1 assume !(1 == ~T5_E~0); 962913#L1274-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 962914#L1279-1 assume !(1 == ~T7_E~0); 961391#L1284-1 assume !(1 == ~T8_E~0); 961392#L1289-1 assume !(1 == ~T9_E~0); 961929#L1294-1 assume !(1 == ~T10_E~0); 961930#L1299-1 assume !(1 == ~T11_E~0); 962887#L1304-1 assume !(1 == ~E_M~0); 962888#L1309-1 assume !(1 == ~E_1~0); 962893#L1314-1 assume 1 == ~E_2~0;~E_2~0 := 2; 962894#L1319-1 assume !(1 == ~E_3~0); 962477#L1324-1 assume !(1 == ~E_4~0); 962478#L1329-1 assume !(1 == ~E_5~0); 962653#L1334-1 assume !(1 == ~E_6~0); 962654#L1339-1 assume !(1 == ~E_7~0); 962876#L1344-1 assume !(1 == ~E_8~0); 962919#L1349-1 assume !(1 == ~E_9~0); 962920#L1354-1 assume 1 == ~E_10~0;~E_10~0 := 2; 962483#L1359-1 assume !(1 == ~E_11~0); 962484#L1364-1 assume { :end_inline_reset_delta_events } true; 1026349#L1690-2 [2021-12-16 10:05:42,165 INFO L793 eck$LassoCheckResult]: Loop: 1026349#L1690-2 assume !false; 1026317#L1691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1026306#L1096 assume !false; 1026307#L933 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1102111#L860 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 1025955#L922 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 1025956#L923 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1025948#L937 assume !(0 != eval_~tmp~0#1); 1025950#L1111 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1118093#L785-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1118092#L1121-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1118091#L1121-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1118090#L1126-3 assume !(0 == ~T2_E~0); 1118089#L1131-3 assume !(0 == ~T3_E~0); 1118088#L1136-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1118087#L1141-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1118086#L1146-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1118085#L1151-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1118084#L1156-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1118083#L1161-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1118082#L1166-3 assume !(0 == ~T10_E~0); 1118081#L1171-3 assume !(0 == ~T11_E~0); 1118080#L1176-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1118079#L1181-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1118078#L1186-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1118077#L1191-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1118076#L1196-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1118075#L1201-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1118074#L1206-3 assume !(0 == ~E_6~0); 1118073#L1211-3 assume !(0 == ~E_7~0); 1118072#L1216-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1118071#L1221-3 assume 0 == ~E_9~0;~E_9~0 := 1; 1118070#L1226-3 assume 0 == ~E_10~0;~E_10~0 := 1; 1118069#L1231-3 assume 0 == ~E_11~0;~E_11~0 := 1; 1118068#L1236-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1118067#L556-39 assume !(1 == ~m_pc~0); 1118066#L556-41 is_master_triggered_~__retres1~0#1 := 0; 1118065#L567-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1118064#L568-13 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1118063#L1391-39 assume !(0 != activate_threads_~tmp~1#1); 1118062#L1391-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1118061#L575-39 assume !(1 == ~t1_pc~0); 1118060#L575-41 is_transmit1_triggered_~__retres1~1#1 := 0; 1118059#L586-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1118058#L587-13 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1118057#L1399-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1118056#L1399-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1118055#L594-39 assume !(1 == ~t2_pc~0); 1118054#L594-41 is_transmit2_triggered_~__retres1~2#1 := 0; 1118053#L605-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1118052#L606-13 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1118051#L1407-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1118050#L1407-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1118049#L613-39 assume !(1 == ~t3_pc~0); 1118048#L613-41 is_transmit3_triggered_~__retres1~3#1 := 0; 1118046#L624-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1118045#L625-13 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1118044#L1415-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1118043#L1415-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1118042#L632-39 assume !(1 == ~t4_pc~0); 1118041#L632-41 is_transmit4_triggered_~__retres1~4#1 := 0; 1118040#L643-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1118039#L644-13 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1118038#L1423-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1118037#L1423-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1118036#L651-39 assume !(1 == ~t5_pc~0); 1118035#L651-41 is_transmit5_triggered_~__retres1~5#1 := 0; 1118034#L662-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1118033#L663-13 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1118032#L1431-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1118031#L1431-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1118030#L670-39 assume 1 == ~t6_pc~0; 1118029#L671-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1118027#L681-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1118026#L682-13 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1118025#L1439-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1118024#L1439-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1118023#L689-39 assume 1 == ~t7_pc~0; 1118021#L690-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1118020#L700-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1118019#L701-13 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1118018#L1447-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1118017#L1447-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1118016#L708-39 assume 1 == ~t8_pc~0; 1028061#L709-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 1028055#L719-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1028050#L720-13 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1028045#L1455-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1028040#L1455-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1028034#L727-39 assume !(1 == ~t9_pc~0); 1028028#L727-41 is_transmit9_triggered_~__retres1~9#1 := 0; 1028021#L738-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1028016#L739-13 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1028011#L1463-39 assume !(0 != activate_threads_~tmp___8~0#1); 1028006#L1463-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1028001#L746-39 assume !(1 == ~t10_pc~0); 1027995#L746-41 is_transmit10_triggered_~__retres1~10#1 := 0; 1027988#L757-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1027983#L758-13 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1027978#L1471-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1027973#L1471-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1027966#L765-39 assume 1 == ~t11_pc~0; 1027960#L766-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 1027953#L776-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1027948#L777-13 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1027943#L1479-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 1027938#L1479-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1027932#L1249-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1017134#L1249-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1027923#L1254-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1025641#L1259-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1027916#L1264-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1027912#L1269-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1027907#L1274-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1027901#L1279-3 assume !(1 == ~T7_E~0); 1027895#L1284-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1027890#L1289-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1027885#L1294-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 1026642#L1299-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 1027873#L1304-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1027866#L1309-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1027860#L1314-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1027855#L1319-3 assume !(1 == ~E_3~0); 1027850#L1324-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1027843#L1329-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1027836#L1334-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1017094#L1339-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1027825#L1344-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1027817#L1349-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1027809#L1354-3 assume 1 == ~E_10~0;~E_10~0 := 2; 1027803#L1359-3 assume !(1 == ~E_11~0); 1027804#L1364-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1027674#L860-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 1027664#L922-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 1027656#L923-1 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 1027648#L1709 assume !(0 == start_simulation_~tmp~3#1); 1027643#L1709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1027592#L860-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 1027576#L922-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 1027568#L923-2 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 1027561#L1664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1026508#L1671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1026353#L1672 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 1026354#L1722 assume !(0 != start_simulation_~tmp___0~1#1); 1026349#L1690-2 [2021-12-16 10:05:42,166 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:42,166 INFO L85 PathProgramCache]: Analyzing trace with hash 1793793208, now seen corresponding path program 1 times [2021-12-16 10:05:42,166 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:42,166 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [41813731] [2021-12-16 10:05:42,166 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:42,167 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:42,174 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:42,195 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:05:42,196 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:42,196 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [41813731] [2021-12-16 10:05:42,196 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [41813731] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:42,196 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:42,196 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-16 10:05:42,196 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1056155063] [2021-12-16 10:05:42,197 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:42,197 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:05:42,197 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:42,197 INFO L85 PathProgramCache]: Analyzing trace with hash -1514046210, now seen corresponding path program 1 times [2021-12-16 10:05:42,198 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:42,198 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1686143850] [2021-12-16 10:05:42,198 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:42,198 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:42,204 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:42,218 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:05:42,218 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:42,218 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1686143850] [2021-12-16 10:05:42,219 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1686143850] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:42,219 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:42,219 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:05:42,219 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [220492573] [2021-12-16 10:05:42,219 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:42,219 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:05:42,220 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:05:42,220 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-16 10:05:42,220 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-16 10:05:42,220 INFO L87 Difference]: Start difference. First operand 428105 states and 610874 transitions. cyclomatic complexity: 182897 Second operand has 5 states, 5 states have (on average 27.8) internal successors, (139), 5 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:46,169 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:05:46,169 INFO L93 Difference]: Finished difference Result 1081963 states and 1554958 transitions. [2021-12-16 10:05:46,170 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-16 10:05:46,171 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1081963 states and 1554958 transitions. [2021-12-16 10:05:52,071 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 1079448