./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/token_ring.13.cil-1.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version c3fed411 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/token_ring.13.cil-1.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 1b2c6a3c4af8091017033117c21d8fbc40cee2009788b890a114045d77587077 --- Real Ultimate output --- This is Ultimate 0.2.2-tmp.no-commuhash-c3fed41 [2021-12-16 10:05:27,185 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-12-16 10:05:27,188 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-12-16 10:05:27,231 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-12-16 10:05:27,231 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-12-16 10:05:27,234 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-12-16 10:05:27,237 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-12-16 10:05:27,240 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-12-16 10:05:27,242 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-12-16 10:05:27,246 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-12-16 10:05:27,247 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-12-16 10:05:27,248 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-12-16 10:05:27,249 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-12-16 10:05:27,251 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-12-16 10:05:27,252 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-12-16 10:05:27,258 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-12-16 10:05:27,260 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-12-16 10:05:27,261 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-12-16 10:05:27,263 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-12-16 10:05:27,269 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-12-16 10:05:27,270 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-12-16 10:05:27,271 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-12-16 10:05:27,273 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-12-16 10:05:27,273 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-12-16 10:05:27,279 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-12-16 10:05:27,280 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-12-16 10:05:27,280 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-12-16 10:05:27,282 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-12-16 10:05:27,283 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-12-16 10:05:27,283 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-12-16 10:05:27,284 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-12-16 10:05:27,285 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-12-16 10:05:27,286 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-12-16 10:05:27,287 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-12-16 10:05:27,288 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-12-16 10:05:27,289 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-12-16 10:05:27,289 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-12-16 10:05:27,290 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-12-16 10:05:27,290 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-12-16 10:05:27,291 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-12-16 10:05:27,291 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-12-16 10:05:27,292 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2021-12-16 10:05:27,324 INFO L113 SettingsManager]: Loading preferences was successful [2021-12-16 10:05:27,325 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-12-16 10:05:27,325 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2021-12-16 10:05:27,326 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2021-12-16 10:05:27,327 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-12-16 10:05:27,327 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-12-16 10:05:27,327 INFO L138 SettingsManager]: * Use SBE=true [2021-12-16 10:05:27,328 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2021-12-16 10:05:27,328 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2021-12-16 10:05:27,328 INFO L138 SettingsManager]: * Use old map elimination=false [2021-12-16 10:05:27,329 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2021-12-16 10:05:27,329 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2021-12-16 10:05:27,330 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2021-12-16 10:05:27,330 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-12-16 10:05:27,330 INFO L138 SettingsManager]: * sizeof long=4 [2021-12-16 10:05:27,330 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2021-12-16 10:05:27,330 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-12-16 10:05:27,330 INFO L138 SettingsManager]: * sizeof POINTER=4 [2021-12-16 10:05:27,331 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-12-16 10:05:27,331 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2021-12-16 10:05:27,331 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2021-12-16 10:05:27,331 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2021-12-16 10:05:27,331 INFO L138 SettingsManager]: * sizeof long double=12 [2021-12-16 10:05:27,332 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-12-16 10:05:27,333 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2021-12-16 10:05:27,333 INFO L138 SettingsManager]: * Use constant arrays=true [2021-12-16 10:05:27,333 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2021-12-16 10:05:27,333 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-12-16 10:05:27,334 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-12-16 10:05:27,334 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-12-16 10:05:27,334 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-12-16 10:05:27,334 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2021-12-16 10:05:27,335 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2021-12-16 10:05:27,336 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 1b2c6a3c4af8091017033117c21d8fbc40cee2009788b890a114045d77587077 [2021-12-16 10:05:27,564 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-12-16 10:05:27,584 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-12-16 10:05:27,587 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-12-16 10:05:27,588 INFO L271 PluginConnector]: Initializing CDTParser... [2021-12-16 10:05:27,588 INFO L275 PluginConnector]: CDTParser initialized [2021-12-16 10:05:27,589 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/token_ring.13.cil-1.c [2021-12-16 10:05:27,655 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/72e9dbd1a/a5fa1d50ab1049d2950da3cce992a13a/FLAG99f118527 [2021-12-16 10:05:28,064 INFO L306 CDTParser]: Found 1 translation units. [2021-12-16 10:05:28,065 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.13.cil-1.c [2021-12-16 10:05:28,079 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/72e9dbd1a/a5fa1d50ab1049d2950da3cce992a13a/FLAG99f118527 [2021-12-16 10:05:28,444 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/72e9dbd1a/a5fa1d50ab1049d2950da3cce992a13a [2021-12-16 10:05:28,447 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-12-16 10:05:28,450 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-12-16 10:05:28,452 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-12-16 10:05:28,452 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-12-16 10:05:28,454 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-12-16 10:05:28,455 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 16.12 10:05:28" (1/1) ... [2021-12-16 10:05:28,456 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@4cdc7bdf and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:05:28, skipping insertion in model container [2021-12-16 10:05:28,456 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 16.12 10:05:28" (1/1) ... [2021-12-16 10:05:28,461 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-12-16 10:05:28,509 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-12-16 10:05:28,638 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.13.cil-1.c[671,684] [2021-12-16 10:05:28,734 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-16 10:05:28,743 INFO L203 MainTranslator]: Completed pre-run [2021-12-16 10:05:28,753 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.13.cil-1.c[671,684] [2021-12-16 10:05:28,811 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-16 10:05:28,828 INFO L208 MainTranslator]: Completed translation [2021-12-16 10:05:28,836 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:05:28 WrapperNode [2021-12-16 10:05:28,837 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-12-16 10:05:28,838 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-12-16 10:05:28,838 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-12-16 10:05:28,839 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-12-16 10:05:28,851 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:05:28" (1/1) ... [2021-12-16 10:05:28,865 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:05:28" (1/1) ... [2021-12-16 10:05:28,987 INFO L137 Inliner]: procedures = 54, calls = 71, calls flagged for inlining = 66, calls inlined = 303, statements flattened = 4665 [2021-12-16 10:05:28,987 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-12-16 10:05:28,988 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-12-16 10:05:28,988 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-12-16 10:05:28,988 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-12-16 10:05:28,997 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:05:28" (1/1) ... [2021-12-16 10:05:28,997 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:05:28" (1/1) ... [2021-12-16 10:05:29,022 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:05:28" (1/1) ... [2021-12-16 10:05:29,023 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:05:28" (1/1) ... [2021-12-16 10:05:29,107 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:05:28" (1/1) ... [2021-12-16 10:05:29,171 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:05:28" (1/1) ... [2021-12-16 10:05:29,181 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:05:28" (1/1) ... [2021-12-16 10:05:29,197 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-12-16 10:05:29,199 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-12-16 10:05:29,199 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-12-16 10:05:29,200 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-12-16 10:05:29,201 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:05:28" (1/1) ... [2021-12-16 10:05:29,207 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-16 10:05:29,217 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-16 10:05:29,233 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-16 10:05:29,248 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2021-12-16 10:05:29,280 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2021-12-16 10:05:29,280 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2021-12-16 10:05:29,280 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-12-16 10:05:29,280 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-12-16 10:05:29,439 INFO L236 CfgBuilder]: Building ICFG [2021-12-16 10:05:29,440 INFO L262 CfgBuilder]: Building CFG for each procedure with an implementation [2021-12-16 10:05:31,405 INFO L277 CfgBuilder]: Performing block encoding [2021-12-16 10:05:31,427 INFO L296 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-12-16 10:05:31,427 INFO L301 CfgBuilder]: Removed 16 assume(true) statements. [2021-12-16 10:05:31,431 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 16.12 10:05:31 BoogieIcfgContainer [2021-12-16 10:05:31,431 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-12-16 10:05:31,432 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2021-12-16 10:05:31,432 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2021-12-16 10:05:31,434 INFO L275 PluginConnector]: BuchiAutomizer initialized [2021-12-16 10:05:31,435 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-16 10:05:31,435 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 16.12 10:05:28" (1/3) ... [2021-12-16 10:05:31,436 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@10054b7d and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 16.12 10:05:31, skipping insertion in model container [2021-12-16 10:05:31,436 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-16 10:05:31,436 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:05:28" (2/3) ... [2021-12-16 10:05:31,437 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@10054b7d and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 16.12 10:05:31, skipping insertion in model container [2021-12-16 10:05:31,437 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-16 10:05:31,437 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 16.12 10:05:31" (3/3) ... [2021-12-16 10:05:31,438 INFO L388 chiAutomizerObserver]: Analyzing ICFG token_ring.13.cil-1.c [2021-12-16 10:05:31,495 INFO L359 BuchiCegarLoop]: Interprodecural is true [2021-12-16 10:05:31,495 INFO L360 BuchiCegarLoop]: Hoare is false [2021-12-16 10:05:31,495 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2021-12-16 10:05:31,495 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2021-12-16 10:05:31,495 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2021-12-16 10:05:31,495 INFO L364 BuchiCegarLoop]: Difference is false [2021-12-16 10:05:31,496 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2021-12-16 10:05:31,496 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2021-12-16 10:05:31,548 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 2031 states, 2030 states have (on average 1.4965517241379311) internal successors, (3038), 2030 states have internal predecessors, (3038), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:31,642 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1852 [2021-12-16 10:05:31,642 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:05:31,643 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:05:31,664 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:31,665 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:31,665 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2021-12-16 10:05:31,669 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 2031 states, 2030 states have (on average 1.4965517241379311) internal successors, (3038), 2030 states have internal predecessors, (3038), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:31,692 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1852 [2021-12-16 10:05:31,693 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:05:31,693 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:05:31,700 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:31,700 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:31,719 INFO L791 eck$LassoCheckResult]: Stem: 484#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 1951#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 1565#L1903true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1977#L907true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1850#L914true assume !(1 == ~m_i~0);~m_st~0 := 2; 836#L914-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 443#L919-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1245#L924-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1128#L929-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1855#L934-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 1285#L939-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 1654#L944-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 313#L949-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 1328#L954-1true assume 1 == ~t9_i~0;~t9_st~0 := 0; 1963#L959-1true assume !(1 == ~t10_i~0);~t10_st~0 := 2; 648#L964-1true assume !(1 == ~t11_i~0);~t11_st~0 := 2; 1195#L969-1true assume !(1 == ~t12_i~0);~t12_st~0 := 2; 1764#L974-1true assume !(1 == ~t13_i~0);~t13_st~0 := 2; 583#L979-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1887#L1291true assume 0 == ~M_E~0;~M_E~0 := 1; 1852#L1291-2true assume !(0 == ~T1_E~0); 1844#L1296-1true assume !(0 == ~T2_E~0); 694#L1301-1true assume !(0 == ~T3_E~0); 1240#L1306-1true assume !(0 == ~T4_E~0); 1212#L1311-1true assume !(0 == ~T5_E~0); 232#L1316-1true assume !(0 == ~T6_E~0); 1658#L1321-1true assume !(0 == ~T7_E~0); 703#L1326-1true assume 0 == ~T8_E~0;~T8_E~0 := 1; 142#L1331-1true assume !(0 == ~T9_E~0); 4#L1336-1true assume !(0 == ~T10_E~0); 1090#L1341-1true assume !(0 == ~T11_E~0); 37#L1346-1true assume !(0 == ~T12_E~0); 1453#L1351-1true assume !(0 == ~T13_E~0); 205#L1356-1true assume !(0 == ~E_M~0); 1971#L1361-1true assume !(0 == ~E_1~0); 1631#L1366-1true assume 0 == ~E_2~0;~E_2~0 := 1; 226#L1371-1true assume !(0 == ~E_3~0); 1433#L1376-1true assume !(0 == ~E_4~0); 755#L1381-1true assume !(0 == ~E_5~0); 1725#L1386-1true assume !(0 == ~E_6~0); 1884#L1391-1true assume !(0 == ~E_7~0); 1795#L1396-1true assume !(0 == ~E_8~0); 667#L1401-1true assume !(0 == ~E_9~0); 1302#L1406-1true assume 0 == ~E_10~0;~E_10~0 := 1; 908#L1411-1true assume !(0 == ~E_11~0); 1686#L1416-1true assume !(0 == ~E_12~0); 614#L1421-1true assume !(0 == ~E_13~0); 324#L1426-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 760#L640true assume !(1 == ~m_pc~0); 1799#L640-2true is_master_triggered_~__retres1~0#1 := 0; 719#L651true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1261#L652true activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 638#L1603true assume !(0 != activate_threads_~tmp~1#1); 1286#L1603-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 402#L659true assume 1 == ~t1_pc~0; 461#L660true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1416#L670true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1368#L671true activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 473#L1611true assume !(0 != activate_threads_~tmp___0~0#1); 481#L1611-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1599#L678true assume 1 == ~t2_pc~0; 1454#L679true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1703#L689true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1973#L690true activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 548#L1619true assume !(0 != activate_threads_~tmp___1~0#1); 691#L1619-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 636#L697true assume !(1 == ~t3_pc~0); 737#L697-2true is_transmit3_triggered_~__retres1~3#1 := 0; 1501#L708true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 588#L709true activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 574#L1627true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1914#L1627-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1534#L716true assume 1 == ~t4_pc~0; 1510#L717true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 389#L727true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1556#L728true activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 121#L1635true assume !(0 != activate_threads_~tmp___3~0#1); 984#L1635-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1478#L735true assume !(1 == ~t5_pc~0); 104#L735-2true is_transmit5_triggered_~__retres1~5#1 := 0; 338#L746true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1646#L747true activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1015#L1643true assume !(0 != activate_threads_~tmp___4~0#1); 687#L1643-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 873#L754true assume 1 == ~t6_pc~0; 521#L755true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 452#L765true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1771#L766true activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 436#L1651true assume !(0 != activate_threads_~tmp___5~0#1); 1119#L1651-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1960#L773true assume !(1 == ~t7_pc~0); 897#L773-2true is_transmit7_triggered_~__retres1~7#1 := 0; 721#L784true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1258#L785true activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 695#L1659true assume !(0 != activate_threads_~tmp___6~0#1); 747#L1659-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 882#L792true assume 1 == ~t8_pc~0; 1953#L793true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 1288#L803true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 742#L804true activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 689#L1667true assume !(0 != activate_threads_~tmp___7~0#1); 637#L1667-2true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 802#L811true assume 1 == ~t9_pc~0; 1340#L812true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1697#L822true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1146#L823true activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 799#L1675true assume !(0 != activate_threads_~tmp___8~0#1); 644#L1675-2true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1728#L830true assume !(1 == ~t10_pc~0); 2019#L830-2true is_transmit10_triggered_~__retres1~10#1 := 0; 196#L841true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 45#L842true activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 185#L1683true assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1791#L1683-2true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1140#L849true assume 1 == ~t11_pc~0; 1627#L850true assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 91#L860true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 407#L861true activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1160#L1691true assume !(0 != activate_threads_~tmp___10~0#1); 1023#L1691-2true assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1797#L868true assume !(1 == ~t12_pc~0); 1394#L868-2true is_transmit12_triggered_~__retres1~12#1 := 0; 568#L879true is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 411#L880true activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 1716#L1699true assume !(0 != activate_threads_~tmp___11~0#1); 213#L1699-2true assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 1629#L887true assume 1 == ~t13_pc~0; 1037#L888true assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 569#L898true is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 913#L899true activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 1106#L1707true assume !(0 != activate_threads_~tmp___12~0#1); 63#L1707-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1680#L1439true assume !(1 == ~M_E~0); 684#L1439-2true assume !(1 == ~T1_E~0); 149#L1444-1true assume !(1 == ~T2_E~0); 914#L1449-1true assume 1 == ~T3_E~0;~T3_E~0 := 2; 404#L1454-1true assume !(1 == ~T4_E~0); 1452#L1459-1true assume !(1 == ~T5_E~0); 796#L1464-1true assume !(1 == ~T6_E~0); 858#L1469-1true assume !(1 == ~T7_E~0); 1706#L1474-1true assume !(1 == ~T8_E~0); 615#L1479-1true assume !(1 == ~T9_E~0); 800#L1484-1true assume !(1 == ~T10_E~0); 1262#L1489-1true assume 1 == ~T11_E~0;~T11_E~0 := 2; 535#L1494-1true assume !(1 == ~T12_E~0); 1835#L1499-1true assume !(1 == ~T13_E~0); 660#L1504-1true assume !(1 == ~E_M~0); 1509#L1509-1true assume !(1 == ~E_1~0); 1259#L1514-1true assume !(1 == ~E_2~0); 883#L1519-1true assume !(1 == ~E_3~0); 1952#L1524-1true assume !(1 == ~E_4~0); 1670#L1529-1true assume 1 == ~E_5~0;~E_5~0 := 2; 1765#L1534-1true assume !(1 == ~E_6~0); 60#L1539-1true assume !(1 == ~E_7~0); 270#L1544-1true assume !(1 == ~E_8~0); 1591#L1549-1true assume !(1 == ~E_9~0); 1614#L1554-1true assume !(1 == ~E_10~0); 1587#L1559-1true assume !(1 == ~E_11~0); 1320#L1564-1true assume !(1 == ~E_12~0); 1655#L1569-1true assume 1 == ~E_13~0;~E_13~0 := 2; 1743#L1574-1true assume { :end_inline_reset_delta_events } true; 148#L1940-2true [2021-12-16 10:05:31,721 INFO L793 eck$LassoCheckResult]: Loop: 148#L1940-2true assume !false; 1557#L1941true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1044#L1266true assume false; 486#L1281true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1604#L907-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 965#L1291-3true assume 0 == ~M_E~0;~M_E~0 := 1; 859#L1291-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 1860#L1296-3true assume !(0 == ~T2_E~0); 1768#L1301-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 1612#L1306-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 590#L1311-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 169#L1316-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 221#L1321-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 679#L1326-3true assume 0 == ~T8_E~0;~T8_E~0 := 1; 1575#L1331-3true assume 0 == ~T9_E~0;~T9_E~0 := 1; 889#L1336-3true assume !(0 == ~T10_E~0); 1494#L1341-3true assume 0 == ~T11_E~0;~T11_E~0 := 1; 400#L1346-3true assume 0 == ~T12_E~0;~T12_E~0 := 1; 386#L1351-3true assume 0 == ~T13_E~0;~T13_E~0 := 1; 355#L1356-3true assume 0 == ~E_M~0;~E_M~0 := 1; 738#L1361-3true assume 0 == ~E_1~0;~E_1~0 := 1; 769#L1366-3true assume 0 == ~E_2~0;~E_2~0 := 1; 27#L1371-3true assume 0 == ~E_3~0;~E_3~0 := 1; 1296#L1376-3true assume !(0 == ~E_4~0); 1545#L1381-3true assume 0 == ~E_5~0;~E_5~0 := 1; 1092#L1386-3true assume 0 == ~E_6~0;~E_6~0 := 1; 1678#L1391-3true assume 0 == ~E_7~0;~E_7~0 := 1; 1332#L1396-3true assume 0 == ~E_8~0;~E_8~0 := 1; 1975#L1401-3true assume 0 == ~E_9~0;~E_9~0 := 1; 203#L1406-3true assume 0 == ~E_10~0;~E_10~0 := 1; 125#L1411-3true assume 0 == ~E_11~0;~E_11~0 := 1; 1767#L1416-3true assume !(0 == ~E_12~0); 491#L1421-3true assume 0 == ~E_13~0;~E_13~0 := 1; 1127#L1426-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 566#L640-45true assume !(1 == ~m_pc~0); 1945#L640-47true is_master_triggered_~__retres1~0#1 := 0; 250#L651-15true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 523#L652-15true activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 24#L1603-45true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1854#L1603-47true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 66#L659-45true assume 1 == ~t1_pc~0; 1919#L660-15true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1780#L670-15true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 980#L671-15true activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1552#L1611-45true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 997#L1611-47true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1521#L678-45true assume 1 == ~t2_pc~0; 946#L679-15true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 571#L689-15true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 671#L690-15true activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1360#L1619-45true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1666#L1619-47true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1607#L697-45true assume !(1 == ~t3_pc~0); 1253#L697-47true is_transmit3_triggered_~__retres1~3#1 := 0; 1849#L708-15true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1502#L709-15true activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 898#L1627-45true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 931#L1627-47true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2013#L716-45true assume 1 == ~t4_pc~0; 625#L717-15true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2007#L727-15true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1133#L728-15true activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 629#L1635-45true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1505#L1635-47true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 410#L735-45true assume !(1 == ~t5_pc~0); 1197#L735-47true is_transmit5_triggered_~__retres1~5#1 := 0; 1660#L746-15true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1515#L747-15true activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1829#L1643-45true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1664#L1643-47true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1651#L754-45true assume !(1 == ~t6_pc~0); 1490#L754-47true is_transmit6_triggered_~__retres1~6#1 := 0; 1990#L765-15true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 363#L766-15true activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1966#L1651-45true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 761#L1651-47true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 552#L773-45true assume !(1 == ~t7_pc~0); 286#L773-47true is_transmit7_triggered_~__retres1~7#1 := 0; 937#L784-15true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1294#L785-15true activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1397#L1659-45true assume !(0 != activate_threads_~tmp___6~0#1); 559#L1659-47true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 353#L792-45true assume 1 == ~t8_pc~0; 1504#L793-15true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 1205#L803-15true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 144#L804-15true activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 73#L1667-45true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 720#L1667-47true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 329#L811-45true assume !(1 == ~t9_pc~0); 283#L811-47true is_transmit9_triggered_~__retres1~9#1 := 0; 1107#L822-15true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1699#L823-15true activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 924#L1675-45true assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 609#L1675-47true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 465#L830-45true assume 1 == ~t10_pc~0; 1341#L831-15true assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 683#L841-15true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1597#L842-15true activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 155#L1683-45true assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1374#L1683-47true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 33#L849-45true assume !(1 == ~t11_pc~0); 1523#L849-47true is_transmit11_triggered_~__retres1~11#1 := 0; 260#L860-15true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 71#L861-15true activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 28#L1691-45true assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 187#L1691-47true assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 152#L868-45true assume 1 == ~t12_pc~0; 398#L869-15true assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 118#L879-15true is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1026#L880-15true activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 1916#L1699-45true assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 1388#L1699-47true assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 1936#L887-45true assume !(1 == ~t13_pc~0); 156#L887-47true is_transmit13_triggered_~__retres1~13#1 := 0; 1041#L898-15true is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 1645#L899-15true activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 1944#L1707-45true assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 136#L1707-47true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1057#L1439-3true assume 1 == ~M_E~0;~M_E~0 := 2; 1028#L1439-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 147#L1444-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 228#L1449-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 1611#L1454-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 847#L1459-3true assume !(1 == ~T5_E~0); 2011#L1464-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 1396#L1469-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 1301#L1474-3true assume 1 == ~T8_E~0;~T8_E~0 := 2; 1622#L1479-3true assume 1 == ~T9_E~0;~T9_E~0 := 2; 1398#L1484-3true assume 1 == ~T10_E~0;~T10_E~0 := 2; 594#L1489-3true assume 1 == ~T11_E~0;~T11_E~0 := 2; 1186#L1494-3true assume 1 == ~T12_E~0;~T12_E~0 := 2; 1792#L1499-3true assume !(1 == ~T13_E~0); 809#L1504-3true assume 1 == ~E_M~0;~E_M~0 := 2; 1316#L1509-3true assume 1 == ~E_1~0;~E_1~0 := 2; 1361#L1514-3true assume 1 == ~E_2~0;~E_2~0 := 2; 1891#L1519-3true assume 1 == ~E_3~0;~E_3~0 := 2; 539#L1524-3true assume 1 == ~E_4~0;~E_4~0 := 2; 1438#L1529-3true assume 1 == ~E_5~0;~E_5~0 := 2; 1669#L1534-3true assume 1 == ~E_6~0;~E_6~0 := 2; 743#L1539-3true assume !(1 == ~E_7~0); 379#L1544-3true assume 1 == ~E_8~0;~E_8~0 := 2; 1406#L1549-3true assume 1 == ~E_9~0;~E_9~0 := 2; 706#L1554-3true assume 1 == ~E_10~0;~E_10~0 := 2; 174#L1559-3true assume 1 == ~E_11~0;~E_11~0 := 2; 1216#L1564-3true assume 1 == ~E_12~0;~E_12~0 := 2; 932#L1569-3true assume 1 == ~E_13~0;~E_13~0 := 2; 1179#L1574-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 111#L992-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 168#L1064-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 134#L1065-1true start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 114#L1959true assume !(0 == start_simulation_~tmp~3#1); 130#L1959-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 892#L992-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 974#L1064-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 1114#L1065-2true stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 1426#L1914true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1598#L1921true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1469#L1922true start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 1613#L1972true assume !(0 != start_simulation_~tmp___0~1#1); 148#L1940-2true [2021-12-16 10:05:31,726 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:31,726 INFO L85 PathProgramCache]: Analyzing trace with hash 1878318605, now seen corresponding path program 1 times [2021-12-16 10:05:31,747 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:31,748 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [847868234] [2021-12-16 10:05:31,748 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:31,749 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:31,860 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:31,982 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:05:31,983 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:31,983 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [847868234] [2021-12-16 10:05:31,984 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [847868234] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:31,984 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:31,993 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:05:31,995 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [438854338] [2021-12-16 10:05:31,996 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:32,000 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:05:32,001 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:32,001 INFO L85 PathProgramCache]: Analyzing trace with hash 1120841461, now seen corresponding path program 1 times [2021-12-16 10:05:32,001 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:32,002 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [645369735] [2021-12-16 10:05:32,002 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:32,002 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:32,019 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:32,043 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:05:32,044 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:32,044 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [645369735] [2021-12-16 10:05:32,044 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [645369735] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:32,044 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:32,044 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-16 10:05:32,045 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2085968241] [2021-12-16 10:05:32,045 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:32,046 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:05:32,047 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:05:32,076 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2021-12-16 10:05:32,076 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2021-12-16 10:05:32,082 INFO L87 Difference]: Start difference. First operand has 2031 states, 2030 states have (on average 1.4965517241379311) internal successors, (3038), 2030 states have internal predecessors, (3038), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 2 states, 2 states have (on average 79.5) internal successors, (159), 2 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:32,245 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:05:32,246 INFO L93 Difference]: Finished difference Result 2029 states and 3002 transitions. [2021-12-16 10:05:32,247 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2021-12-16 10:05:32,251 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2029 states and 3002 transitions. [2021-12-16 10:05:32,272 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1848 [2021-12-16 10:05:32,290 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2029 states to 2023 states and 2996 transitions. [2021-12-16 10:05:32,291 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2023 [2021-12-16 10:05:32,294 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2023 [2021-12-16 10:05:32,295 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2023 states and 2996 transitions. [2021-12-16 10:05:32,306 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:05:32,307 INFO L681 BuchiCegarLoop]: Abstraction has 2023 states and 2996 transitions. [2021-12-16 10:05:32,326 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2023 states and 2996 transitions. [2021-12-16 10:05:32,392 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2023 to 2023. [2021-12-16 10:05:32,398 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2023 states, 2023 states have (on average 1.480968858131488) internal successors, (2996), 2022 states have internal predecessors, (2996), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:32,406 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2023 states to 2023 states and 2996 transitions. [2021-12-16 10:05:32,407 INFO L704 BuchiCegarLoop]: Abstraction has 2023 states and 2996 transitions. [2021-12-16 10:05:32,408 INFO L587 BuchiCegarLoop]: Abstraction has 2023 states and 2996 transitions. [2021-12-16 10:05:32,408 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2021-12-16 10:05:32,408 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2023 states and 2996 transitions. [2021-12-16 10:05:32,421 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1848 [2021-12-16 10:05:32,421 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:05:32,421 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:05:32,426 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:32,427 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:32,428 INFO L791 eck$LassoCheckResult]: Stem: 4996#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 4997#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 5995#L1903 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5996#L907 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6081#L914 assume !(1 == ~m_i~0);~m_st~0 := 2; 5460#L914-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4929#L919-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 4930#L924-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 5746#L929-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 5747#L934-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 5847#L939-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 5848#L944-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 4701#L949-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 4702#L954-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 5877#L959-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 5237#L964-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 5238#L969-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 5798#L974-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 5139#L979-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5140#L1291 assume 0 == ~M_E~0;~M_E~0 := 1; 6082#L1291-2 assume !(0 == ~T1_E~0); 6080#L1296-1 assume !(0 == ~T2_E~0); 5296#L1301-1 assume !(0 == ~T3_E~0); 5297#L1306-1 assume !(0 == ~T4_E~0); 5806#L1311-1 assume !(0 == ~T5_E~0); 4544#L1316-1 assume !(0 == ~T6_E~0); 4545#L1321-1 assume !(0 == ~T7_E~0); 5309#L1326-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 4372#L1331-1 assume !(0 == ~T9_E~0); 4071#L1336-1 assume !(0 == ~T10_E~0); 4072#L1341-1 assume !(0 == ~T11_E~0); 4152#L1346-1 assume !(0 == ~T12_E~0); 4153#L1351-1 assume !(0 == ~T13_E~0); 4493#L1356-1 assume !(0 == ~E_M~0); 4494#L1361-1 assume !(0 == ~E_1~0); 6021#L1366-1 assume 0 == ~E_2~0;~E_2~0 := 1; 4534#L1371-1 assume !(0 == ~E_3~0); 4535#L1376-1 assume !(0 == ~E_4~0); 5356#L1381-1 assume !(0 == ~E_5~0); 5357#L1386-1 assume !(0 == ~E_6~0); 6051#L1391-1 assume !(0 == ~E_7~0); 6069#L1396-1 assume !(0 == ~E_8~0); 5269#L1401-1 assume !(0 == ~E_9~0); 5270#L1406-1 assume 0 == ~E_10~0;~E_10~0 := 1; 5548#L1411-1 assume !(0 == ~E_11~0); 5549#L1416-1 assume !(0 == ~E_12~0); 5181#L1421-1 assume !(0 == ~E_13~0); 4724#L1426-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4725#L640 assume !(1 == ~m_pc~0); 5234#L640-2 is_master_triggered_~__retres1~0#1 := 0; 5233#L651 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5325#L652 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 5219#L1603 assume !(0 != activate_threads_~tmp~1#1); 5220#L1603-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4854#L659 assume 1 == ~t1_pc~0; 4855#L660 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4960#L670 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5906#L671 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4980#L1611 assume !(0 != activate_threads_~tmp___0~0#1); 4981#L1611-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4994#L678 assume 1 == ~t2_pc~0; 5948#L679 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5949#L689 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6048#L690 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 5092#L1619 assume !(0 != activate_threads_~tmp___1~0#1); 5093#L1619-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5214#L697 assume !(1 == ~t3_pc~0); 5215#L697-2 is_transmit3_triggered_~__retres1~3#1 := 0; 5337#L708 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5145#L709 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 5124#L1627 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5125#L1627-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5985#L716 assume 1 == ~t4_pc~0; 5971#L717 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4835#L727 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4836#L728 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4335#L1635 assume !(0 != activate_threads_~tmp___3~0#1); 4336#L1635-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5627#L735 assume !(1 == ~t5_pc~0); 4296#L735-2 is_transmit5_triggered_~__retres1~5#1 := 0; 4297#L746 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4747#L747 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 5654#L1643 assume !(0 != activate_threads_~tmp___4~0#1); 5290#L1643-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5291#L754 assume 1 == ~t6_pc~0; 5044#L755 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4942#L765 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4943#L766 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 4916#L1651 assume !(0 != activate_threads_~tmp___5~0#1); 4917#L1651-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5737#L773 assume !(1 == ~t7_pc~0); 4497#L773-2 is_transmit7_triggered_~__retres1~7#1 := 0; 4496#L784 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5326#L785 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 5298#L1659 assume !(0 != activate_threads_~tmp___6~0#1); 5299#L1659-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 5346#L792 assume 1 == ~t8_pc~0; 5519#L793 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 5851#L803 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 5340#L804 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 5293#L1667 assume !(0 != activate_threads_~tmp___7~0#1); 5217#L1667-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 5218#L811 assume 1 == ~t9_pc~0; 5422#L812 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 5888#L822 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 5764#L823 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 5418#L1675 assume !(0 != activate_threads_~tmp___8~0#1); 5230#L1675-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 5231#L830 assume !(1 == ~t10_pc~0); 4952#L830-2 is_transmit10_triggered_~__retres1~10#1 := 0; 4476#L841 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 4169#L842 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 4170#L1683 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 4457#L1683-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 5755#L849 assume 1 == ~t11_pc~0; 5756#L850 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 4272#L860 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 4273#L861 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 4862#L1691 assume !(0 != activate_threads_~tmp___10~0#1); 5661#L1691-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 5662#L868 assume !(1 == ~t12_pc~0); 5077#L868-2 is_transmit12_triggered_~__retres1~12#1 := 0; 5076#L879 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 4871#L880 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 4872#L1699 assume !(0 != activate_threads_~tmp___11~0#1); 4508#L1699-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 4509#L887 assume 1 == ~t13_pc~0; 5676#L888 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 5118#L898 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 5119#L899 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 5555#L1707 assume !(0 != activate_threads_~tmp___12~0#1); 4212#L1707-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4213#L1439 assume !(1 == ~M_E~0); 5286#L1439-2 assume !(1 == ~T1_E~0); 4384#L1444-1 assume !(1 == ~T2_E~0); 4385#L1449-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4858#L1454-1 assume !(1 == ~T4_E~0); 4859#L1459-1 assume !(1 == ~T5_E~0); 5415#L1464-1 assume !(1 == ~T6_E~0); 5416#L1469-1 assume !(1 == ~T7_E~0); 5488#L1474-1 assume !(1 == ~T8_E~0); 5182#L1479-1 assume !(1 == ~T9_E~0); 5183#L1484-1 assume !(1 == ~T10_E~0); 5419#L1489-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 5065#L1494-1 assume !(1 == ~T12_E~0); 5066#L1499-1 assume !(1 == ~T13_E~0); 5258#L1504-1 assume !(1 == ~E_M~0); 5259#L1509-1 assume !(1 == ~E_1~0); 5834#L1514-1 assume !(1 == ~E_2~0); 5521#L1519-1 assume !(1 == ~E_3~0); 5522#L1524-1 assume !(1 == ~E_4~0); 6034#L1529-1 assume 1 == ~E_5~0;~E_5~0 := 2; 6035#L1534-1 assume !(1 == ~E_6~0); 4205#L1539-1 assume !(1 == ~E_7~0); 4206#L1544-1 assume !(1 == ~E_8~0); 4620#L1549-1 assume !(1 == ~E_9~0); 6009#L1554-1 assume !(1 == ~E_10~0); 6005#L1559-1 assume !(1 == ~E_11~0); 5872#L1564-1 assume !(1 == ~E_12~0); 5873#L1569-1 assume 1 == ~E_13~0;~E_13~0 := 2; 6030#L1574-1 assume { :end_inline_reset_delta_events } true; 4382#L1940-2 [2021-12-16 10:05:32,431 INFO L793 eck$LassoCheckResult]: Loop: 4382#L1940-2 assume !false; 4383#L1941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4665#L1266 assume !false; 5684#L1075 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 4913#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 4646#L1064 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 5037#L1065 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 5038#L1079 assume !(0 != eval_~tmp~0#1); 4999#L1281 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5000#L907-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5604#L1291-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5489#L1291-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5490#L1296-3 assume !(0 == ~T2_E~0); 6062#L1301-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 6016#L1306-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5147#L1311-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4423#L1316-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4424#L1321-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 4524#L1326-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 5281#L1331-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 5530#L1336-3 assume !(0 == ~T10_E~0); 5531#L1341-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 4851#L1346-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 4831#L1351-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 4776#L1356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 4777#L1361-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5338#L1366-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4127#L1371-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4128#L1376-3 assume !(0 == ~E_4~0); 5857#L1381-3 assume 0 == ~E_5~0;~E_5~0 := 1; 5717#L1386-3 assume 0 == ~E_6~0;~E_6~0 := 1; 5718#L1391-3 assume 0 == ~E_7~0;~E_7~0 := 1; 5880#L1396-3 assume 0 == ~E_8~0;~E_8~0 := 1; 5881#L1401-3 assume 0 == ~E_9~0;~E_9~0 := 1; 4490#L1406-3 assume 0 == ~E_10~0;~E_10~0 := 1; 4344#L1411-3 assume 0 == ~E_11~0;~E_11~0 := 1; 4345#L1416-3 assume !(0 == ~E_12~0); 5006#L1421-3 assume 0 == ~E_13~0;~E_13~0 := 1; 5007#L1426-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5114#L640-45 assume !(1 == ~m_pc~0); 5115#L640-47 is_master_triggered_~__retres1~0#1 := 0; 4581#L651-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4582#L652-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4121#L1603-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4122#L1603-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4220#L659-45 assume 1 == ~t1_pc~0; 4221#L660-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4660#L670-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5619#L671-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5620#L1611-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5641#L1611-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5642#L678-45 assume 1 == ~t2_pc~0; 5585#L679-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5120#L689-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5121#L690-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 5273#L1619-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5898#L1619-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6015#L697-45 assume 1 == ~t3_pc~0; 5378#L698-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5379#L708-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5967#L709-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 5537#L1627-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5538#L1627-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5568#L716-45 assume !(1 == ~t4_pc~0); 5201#L716-47 is_transmit4_triggered_~__retres1~4#1 := 0; 5200#L727-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5750#L728-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 5205#L1635-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5206#L1635-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4868#L735-45 assume 1 == ~t5_pc~0; 4869#L736-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5412#L746-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5974#L747-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 5975#L1643-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 6033#L1643-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6028#L754-45 assume 1 == ~t6_pc~0; 5360#L755-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 5361#L765-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4790#L766-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 4791#L1651-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 5364#L1651-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5096#L773-45 assume 1 == ~t7_pc~0; 5097#L774-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 4654#L784-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5574#L785-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 5856#L1659-45 assume !(0 != activate_threads_~tmp___6~0#1); 5102#L1659-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4772#L792-45 assume 1 == ~t8_pc~0; 4773#L793-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 5802#L803-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4375#L804-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 4234#L1667-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 4235#L1667-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4730#L811-45 assume 1 == ~t9_pc~0; 4519#L812-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 4521#L822-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 5729#L823-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 5564#L1675-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 5173#L1675-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4965#L830-45 assume !(1 == ~t10_pc~0); 4162#L830-47 is_transmit10_triggered_~__retres1~10#1 := 0; 4163#L841-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 5285#L842-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 4395#L1683-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 4396#L1683-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 4141#L849-45 assume !(1 == ~t11_pc~0); 4142#L849-47 is_transmit11_triggered_~__retres1~11#1 := 0; 4601#L860-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 4232#L861-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 4129#L1691-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 4130#L1691-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 4388#L868-45 assume 1 == ~t12_pc~0; 4389#L869-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 4328#L879-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 4329#L880-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 5667#L1699-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 5918#L1699-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 5919#L887-45 assume 1 == ~t13_pc~0; 5749#L888-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 4398#L898-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 5680#L899-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 6025#L1707-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 4360#L1707-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4361#L1439-3 assume 1 == ~M_E~0;~M_E~0 := 2; 5668#L1439-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4380#L1444-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4381#L1449-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4538#L1454-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5469#L1459-3 assume !(1 == ~T5_E~0); 5470#L1464-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 5921#L1469-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 5860#L1474-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 5861#L1479-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 5922#L1484-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 5154#L1489-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 5155#L1494-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 5791#L1499-3 assume !(1 == ~T13_E~0); 5430#L1504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 5431#L1509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5869#L1514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5899#L1519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5073#L1524-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5074#L1529-3 assume 1 == ~E_5~0;~E_5~0 := 2; 5941#L1534-3 assume 1 == ~E_6~0;~E_6~0 := 2; 5341#L1539-3 assume !(1 == ~E_7~0); 4817#L1544-3 assume 1 == ~E_8~0;~E_8~0 := 2; 4818#L1549-3 assume 1 == ~E_9~0;~E_9~0 := 2; 5313#L1554-3 assume 1 == ~E_10~0;~E_10~0 := 2; 4434#L1559-3 assume 1 == ~E_11~0;~E_11~0 := 2; 4435#L1564-3 assume 1 == ~E_12~0;~E_12~0 := 2; 5569#L1569-3 assume 1 == ~E_13~0;~E_13~0 := 2; 5570#L1574-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 4311#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 4082#L1064-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 4357#L1065-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 4318#L1959 assume !(0 == start_simulation_~tmp~3#1); 4320#L1959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 4352#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 4302#L1064-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 5611#L1065-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 5732#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5939#L1921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5953#L1922 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 5954#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 4382#L1940-2 [2021-12-16 10:05:32,433 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:32,433 INFO L85 PathProgramCache]: Analyzing trace with hash 1878318605, now seen corresponding path program 2 times [2021-12-16 10:05:32,433 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:32,434 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1830628761] [2021-12-16 10:05:32,435 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:32,435 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:32,479 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:32,534 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:05:32,538 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:32,538 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1830628761] [2021-12-16 10:05:32,539 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1830628761] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:32,539 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:32,539 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:05:32,539 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [773000890] [2021-12-16 10:05:32,540 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:32,540 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:05:32,541 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:32,548 INFO L85 PathProgramCache]: Analyzing trace with hash -1800844194, now seen corresponding path program 1 times [2021-12-16 10:05:32,548 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:32,549 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [359399011] [2021-12-16 10:05:32,549 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:32,549 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:32,603 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:32,720 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:05:32,723 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:32,723 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [359399011] [2021-12-16 10:05:32,724 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [359399011] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:32,724 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:32,724 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:05:32,724 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1536949635] [2021-12-16 10:05:32,724 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:32,725 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:05:32,726 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:05:32,727 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-16 10:05:32,729 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-16 10:05:32,729 INFO L87 Difference]: Start difference. First operand 2023 states and 2996 transitions. cyclomatic complexity: 974 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:32,814 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:05:32,815 INFO L93 Difference]: Finished difference Result 2023 states and 2995 transitions. [2021-12-16 10:05:32,815 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-16 10:05:32,816 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2023 states and 2995 transitions. [2021-12-16 10:05:32,828 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1848 [2021-12-16 10:05:32,841 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2023 states to 2023 states and 2995 transitions. [2021-12-16 10:05:32,841 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2023 [2021-12-16 10:05:32,843 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2023 [2021-12-16 10:05:32,844 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2023 states and 2995 transitions. [2021-12-16 10:05:32,846 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:05:32,847 INFO L681 BuchiCegarLoop]: Abstraction has 2023 states and 2995 transitions. [2021-12-16 10:05:32,850 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2023 states and 2995 transitions. [2021-12-16 10:05:32,872 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2023 to 2023. [2021-12-16 10:05:32,875 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2023 states, 2023 states have (on average 1.4804745427582797) internal successors, (2995), 2022 states have internal predecessors, (2995), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:32,881 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2023 states to 2023 states and 2995 transitions. [2021-12-16 10:05:32,881 INFO L704 BuchiCegarLoop]: Abstraction has 2023 states and 2995 transitions. [2021-12-16 10:05:32,881 INFO L587 BuchiCegarLoop]: Abstraction has 2023 states and 2995 transitions. [2021-12-16 10:05:32,882 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2021-12-16 10:05:32,882 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2023 states and 2995 transitions. [2021-12-16 10:05:32,893 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1848 [2021-12-16 10:05:32,893 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:05:32,893 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:05:32,900 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:32,900 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:32,900 INFO L791 eck$LassoCheckResult]: Stem: 9049#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 9050#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 10048#L1903 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 10049#L907 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 10134#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 9513#L914-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8982#L919-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 8983#L924-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 9799#L929-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 9800#L934-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 9900#L939-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 9901#L944-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 8754#L949-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 8755#L954-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 9930#L959-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 9290#L964-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 9291#L969-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 9851#L974-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 9192#L979-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 9193#L1291 assume 0 == ~M_E~0;~M_E~0 := 1; 10135#L1291-2 assume !(0 == ~T1_E~0); 10133#L1296-1 assume !(0 == ~T2_E~0); 9349#L1301-1 assume !(0 == ~T3_E~0); 9350#L1306-1 assume !(0 == ~T4_E~0); 9859#L1311-1 assume !(0 == ~T5_E~0); 8597#L1316-1 assume !(0 == ~T6_E~0); 8598#L1321-1 assume !(0 == ~T7_E~0); 9362#L1326-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 8425#L1331-1 assume !(0 == ~T9_E~0); 8124#L1336-1 assume !(0 == ~T10_E~0); 8125#L1341-1 assume !(0 == ~T11_E~0); 8205#L1346-1 assume !(0 == ~T12_E~0); 8206#L1351-1 assume !(0 == ~T13_E~0); 8546#L1356-1 assume !(0 == ~E_M~0); 8547#L1361-1 assume !(0 == ~E_1~0); 10074#L1366-1 assume 0 == ~E_2~0;~E_2~0 := 1; 8587#L1371-1 assume !(0 == ~E_3~0); 8588#L1376-1 assume !(0 == ~E_4~0); 9409#L1381-1 assume !(0 == ~E_5~0); 9410#L1386-1 assume !(0 == ~E_6~0); 10104#L1391-1 assume !(0 == ~E_7~0); 10122#L1396-1 assume !(0 == ~E_8~0); 9322#L1401-1 assume !(0 == ~E_9~0); 9323#L1406-1 assume 0 == ~E_10~0;~E_10~0 := 1; 9601#L1411-1 assume !(0 == ~E_11~0); 9602#L1416-1 assume !(0 == ~E_12~0); 9234#L1421-1 assume !(0 == ~E_13~0); 8777#L1426-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8778#L640 assume !(1 == ~m_pc~0); 9287#L640-2 is_master_triggered_~__retres1~0#1 := 0; 9286#L651 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9378#L652 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 9272#L1603 assume !(0 != activate_threads_~tmp~1#1); 9273#L1603-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8907#L659 assume 1 == ~t1_pc~0; 8908#L660 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 9013#L670 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9959#L671 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9033#L1611 assume !(0 != activate_threads_~tmp___0~0#1); 9034#L1611-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9047#L678 assume 1 == ~t2_pc~0; 10001#L679 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 10002#L689 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10101#L690 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 9145#L1619 assume !(0 != activate_threads_~tmp___1~0#1); 9146#L1619-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9267#L697 assume !(1 == ~t3_pc~0); 9268#L697-2 is_transmit3_triggered_~__retres1~3#1 := 0; 9390#L708 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9198#L709 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 9177#L1627 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9178#L1627-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10038#L716 assume 1 == ~t4_pc~0; 10024#L717 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 8888#L727 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8889#L728 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 8388#L1635 assume !(0 != activate_threads_~tmp___3~0#1); 8389#L1635-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9680#L735 assume !(1 == ~t5_pc~0); 8349#L735-2 is_transmit5_triggered_~__retres1~5#1 := 0; 8350#L746 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8800#L747 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 9707#L1643 assume !(0 != activate_threads_~tmp___4~0#1); 9343#L1643-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9344#L754 assume 1 == ~t6_pc~0; 9097#L755 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 8995#L765 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8996#L766 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 8969#L1651 assume !(0 != activate_threads_~tmp___5~0#1); 8970#L1651-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9790#L773 assume !(1 == ~t7_pc~0); 8550#L773-2 is_transmit7_triggered_~__retres1~7#1 := 0; 8549#L784 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 9379#L785 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 9351#L1659 assume !(0 != activate_threads_~tmp___6~0#1); 9352#L1659-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 9399#L792 assume 1 == ~t8_pc~0; 9572#L793 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 9904#L803 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 9393#L804 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 9346#L1667 assume !(0 != activate_threads_~tmp___7~0#1); 9270#L1667-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 9271#L811 assume 1 == ~t9_pc~0; 9475#L812 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 9941#L822 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 9817#L823 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 9471#L1675 assume !(0 != activate_threads_~tmp___8~0#1); 9283#L1675-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 9284#L830 assume !(1 == ~t10_pc~0); 9005#L830-2 is_transmit10_triggered_~__retres1~10#1 := 0; 8529#L841 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 8222#L842 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 8223#L1683 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 8510#L1683-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 9808#L849 assume 1 == ~t11_pc~0; 9809#L850 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 8325#L860 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 8326#L861 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 8915#L1691 assume !(0 != activate_threads_~tmp___10~0#1); 9714#L1691-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 9715#L868 assume !(1 == ~t12_pc~0); 9130#L868-2 is_transmit12_triggered_~__retres1~12#1 := 0; 9129#L879 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 8924#L880 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 8925#L1699 assume !(0 != activate_threads_~tmp___11~0#1); 8561#L1699-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 8562#L887 assume 1 == ~t13_pc~0; 9729#L888 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 9171#L898 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 9172#L899 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 9608#L1707 assume !(0 != activate_threads_~tmp___12~0#1); 8265#L1707-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8266#L1439 assume !(1 == ~M_E~0); 9339#L1439-2 assume !(1 == ~T1_E~0); 8437#L1444-1 assume !(1 == ~T2_E~0); 8438#L1449-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8911#L1454-1 assume !(1 == ~T4_E~0); 8912#L1459-1 assume !(1 == ~T5_E~0); 9468#L1464-1 assume !(1 == ~T6_E~0); 9469#L1469-1 assume !(1 == ~T7_E~0); 9541#L1474-1 assume !(1 == ~T8_E~0); 9235#L1479-1 assume !(1 == ~T9_E~0); 9236#L1484-1 assume !(1 == ~T10_E~0); 9472#L1489-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 9118#L1494-1 assume !(1 == ~T12_E~0); 9119#L1499-1 assume !(1 == ~T13_E~0); 9311#L1504-1 assume !(1 == ~E_M~0); 9312#L1509-1 assume !(1 == ~E_1~0); 9887#L1514-1 assume !(1 == ~E_2~0); 9574#L1519-1 assume !(1 == ~E_3~0); 9575#L1524-1 assume !(1 == ~E_4~0); 10087#L1529-1 assume 1 == ~E_5~0;~E_5~0 := 2; 10088#L1534-1 assume !(1 == ~E_6~0); 8258#L1539-1 assume !(1 == ~E_7~0); 8259#L1544-1 assume !(1 == ~E_8~0); 8673#L1549-1 assume !(1 == ~E_9~0); 10062#L1554-1 assume !(1 == ~E_10~0); 10058#L1559-1 assume !(1 == ~E_11~0); 9925#L1564-1 assume !(1 == ~E_12~0); 9926#L1569-1 assume 1 == ~E_13~0;~E_13~0 := 2; 10083#L1574-1 assume { :end_inline_reset_delta_events } true; 8435#L1940-2 [2021-12-16 10:05:32,901 INFO L793 eck$LassoCheckResult]: Loop: 8435#L1940-2 assume !false; 8436#L1941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 8718#L1266 assume !false; 9737#L1075 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 8966#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 8699#L1064 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 9090#L1065 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 9091#L1079 assume !(0 != eval_~tmp~0#1); 9052#L1281 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 9053#L907-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 9657#L1291-3 assume 0 == ~M_E~0;~M_E~0 := 1; 9542#L1291-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 9543#L1296-3 assume !(0 == ~T2_E~0); 10115#L1301-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 10069#L1306-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 9200#L1311-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 8476#L1316-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 8477#L1321-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 8577#L1326-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 9334#L1331-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 9583#L1336-3 assume !(0 == ~T10_E~0); 9584#L1341-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 8904#L1346-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 8884#L1351-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 8829#L1356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 8830#L1361-3 assume 0 == ~E_1~0;~E_1~0 := 1; 9391#L1366-3 assume 0 == ~E_2~0;~E_2~0 := 1; 8180#L1371-3 assume 0 == ~E_3~0;~E_3~0 := 1; 8181#L1376-3 assume !(0 == ~E_4~0); 9910#L1381-3 assume 0 == ~E_5~0;~E_5~0 := 1; 9770#L1386-3 assume 0 == ~E_6~0;~E_6~0 := 1; 9771#L1391-3 assume 0 == ~E_7~0;~E_7~0 := 1; 9933#L1396-3 assume 0 == ~E_8~0;~E_8~0 := 1; 9934#L1401-3 assume 0 == ~E_9~0;~E_9~0 := 1; 8543#L1406-3 assume 0 == ~E_10~0;~E_10~0 := 1; 8397#L1411-3 assume 0 == ~E_11~0;~E_11~0 := 1; 8398#L1416-3 assume !(0 == ~E_12~0); 9059#L1421-3 assume 0 == ~E_13~0;~E_13~0 := 1; 9060#L1426-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9167#L640-45 assume !(1 == ~m_pc~0); 9168#L640-47 is_master_triggered_~__retres1~0#1 := 0; 8634#L651-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8635#L652-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8174#L1603-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8175#L1603-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8273#L659-45 assume 1 == ~t1_pc~0; 8274#L660-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8713#L670-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9672#L671-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9673#L1611-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 9694#L1611-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9695#L678-45 assume 1 == ~t2_pc~0; 9638#L679-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 9173#L689-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9174#L690-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 9326#L1619-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 9951#L1619-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10068#L697-45 assume 1 == ~t3_pc~0; 9431#L698-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 9432#L708-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10020#L709-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 9590#L1627-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9591#L1627-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9621#L716-45 assume 1 == ~t4_pc~0; 9252#L717-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 9253#L727-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9803#L728-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 9258#L1635-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 9259#L1635-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8921#L735-45 assume 1 == ~t5_pc~0; 8922#L736-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 9465#L746-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10027#L747-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 10028#L1643-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 10086#L1643-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10081#L754-45 assume 1 == ~t6_pc~0; 9413#L755-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 9414#L765-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8843#L766-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 8844#L1651-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 9417#L1651-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9149#L773-45 assume !(1 == ~t7_pc~0); 8706#L773-47 is_transmit7_triggered_~__retres1~7#1 := 0; 8707#L784-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 9627#L785-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 9909#L1659-45 assume !(0 != activate_threads_~tmp___6~0#1); 9155#L1659-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 8825#L792-45 assume 1 == ~t8_pc~0; 8826#L793-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 9855#L803-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 8428#L804-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 8287#L1667-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 8288#L1667-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 8783#L811-45 assume 1 == ~t9_pc~0; 8572#L812-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 8574#L822-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 9782#L823-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 9617#L1675-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 9226#L1675-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 9018#L830-45 assume !(1 == ~t10_pc~0); 8215#L830-47 is_transmit10_triggered_~__retres1~10#1 := 0; 8216#L841-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 9338#L842-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 8448#L1683-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 8449#L1683-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 8194#L849-45 assume !(1 == ~t11_pc~0); 8195#L849-47 is_transmit11_triggered_~__retres1~11#1 := 0; 8654#L860-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 8285#L861-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 8182#L1691-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 8183#L1691-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 8441#L868-45 assume 1 == ~t12_pc~0; 8442#L869-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 8381#L879-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 8382#L880-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 9720#L1699-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 9971#L1699-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 9972#L887-45 assume !(1 == ~t13_pc~0); 8450#L887-47 is_transmit13_triggered_~__retres1~13#1 := 0; 8451#L898-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 9733#L899-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 10078#L1707-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 8413#L1707-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8414#L1439-3 assume 1 == ~M_E~0;~M_E~0 := 2; 9721#L1439-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8433#L1444-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 8434#L1449-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8591#L1454-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 9522#L1459-3 assume !(1 == ~T5_E~0); 9523#L1464-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 9974#L1469-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 9913#L1474-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 9914#L1479-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 9975#L1484-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 9207#L1489-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 9208#L1494-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 9844#L1499-3 assume !(1 == ~T13_E~0); 9483#L1504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 9484#L1509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 9922#L1514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 9952#L1519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 9126#L1524-3 assume 1 == ~E_4~0;~E_4~0 := 2; 9127#L1529-3 assume 1 == ~E_5~0;~E_5~0 := 2; 9994#L1534-3 assume 1 == ~E_6~0;~E_6~0 := 2; 9394#L1539-3 assume !(1 == ~E_7~0); 8870#L1544-3 assume 1 == ~E_8~0;~E_8~0 := 2; 8871#L1549-3 assume 1 == ~E_9~0;~E_9~0 := 2; 9366#L1554-3 assume 1 == ~E_10~0;~E_10~0 := 2; 8487#L1559-3 assume 1 == ~E_11~0;~E_11~0 := 2; 8488#L1564-3 assume 1 == ~E_12~0;~E_12~0 := 2; 9622#L1569-3 assume 1 == ~E_13~0;~E_13~0 := 2; 9623#L1574-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 8364#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 8135#L1064-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 8410#L1065-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 8371#L1959 assume !(0 == start_simulation_~tmp~3#1); 8373#L1959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 8405#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 8355#L1064-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 9664#L1065-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 9785#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 9992#L1921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 10006#L1922 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 10007#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 8435#L1940-2 [2021-12-16 10:05:32,904 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:32,904 INFO L85 PathProgramCache]: Analyzing trace with hash 1533490443, now seen corresponding path program 1 times [2021-12-16 10:05:32,904 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:32,905 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1464811425] [2021-12-16 10:05:32,905 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:32,905 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:32,928 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:32,975 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:05:32,977 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:32,977 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1464811425] [2021-12-16 10:05:32,977 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1464811425] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:32,977 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:32,977 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:05:32,978 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [77321291] [2021-12-16 10:05:32,978 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:32,978 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:05:32,979 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:32,979 INFO L85 PathProgramCache]: Analyzing trace with hash 230524959, now seen corresponding path program 1 times [2021-12-16 10:05:32,980 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:32,980 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [544197515] [2021-12-16 10:05:32,980 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:32,981 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:33,005 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:33,065 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:05:33,066 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:33,066 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [544197515] [2021-12-16 10:05:33,066 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [544197515] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:33,067 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:33,067 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:05:33,067 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1714425175] [2021-12-16 10:05:33,067 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:33,068 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:05:33,068 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:05:33,069 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-16 10:05:33,069 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-16 10:05:33,069 INFO L87 Difference]: Start difference. First operand 2023 states and 2995 transitions. cyclomatic complexity: 973 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:33,106 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:05:33,107 INFO L93 Difference]: Finished difference Result 2023 states and 2994 transitions. [2021-12-16 10:05:33,107 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-16 10:05:33,109 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2023 states and 2994 transitions. [2021-12-16 10:05:33,122 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1848 [2021-12-16 10:05:33,132 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2023 states to 2023 states and 2994 transitions. [2021-12-16 10:05:33,132 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2023 [2021-12-16 10:05:33,134 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2023 [2021-12-16 10:05:33,134 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2023 states and 2994 transitions. [2021-12-16 10:05:33,138 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:05:33,138 INFO L681 BuchiCegarLoop]: Abstraction has 2023 states and 2994 transitions. [2021-12-16 10:05:33,140 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2023 states and 2994 transitions. [2021-12-16 10:05:33,162 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2023 to 2023. [2021-12-16 10:05:33,166 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2023 states, 2023 states have (on average 1.4799802273850717) internal successors, (2994), 2022 states have internal predecessors, (2994), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:33,172 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2023 states to 2023 states and 2994 transitions. [2021-12-16 10:05:33,172 INFO L704 BuchiCegarLoop]: Abstraction has 2023 states and 2994 transitions. [2021-12-16 10:05:33,173 INFO L587 BuchiCegarLoop]: Abstraction has 2023 states and 2994 transitions. [2021-12-16 10:05:33,173 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2021-12-16 10:05:33,173 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2023 states and 2994 transitions. [2021-12-16 10:05:33,181 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1848 [2021-12-16 10:05:33,182 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:05:33,182 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:05:33,184 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:33,184 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:33,185 INFO L791 eck$LassoCheckResult]: Stem: 13102#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 13103#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 14101#L1903 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 14102#L907 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 14187#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 13566#L914-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 13035#L919-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 13036#L924-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 13852#L929-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 13853#L934-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 13953#L939-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 13954#L944-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 12807#L949-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 12808#L954-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 13983#L959-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 13343#L964-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 13344#L969-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 13904#L974-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 13245#L979-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 13246#L1291 assume 0 == ~M_E~0;~M_E~0 := 1; 14188#L1291-2 assume !(0 == ~T1_E~0); 14186#L1296-1 assume !(0 == ~T2_E~0); 13402#L1301-1 assume !(0 == ~T3_E~0); 13403#L1306-1 assume !(0 == ~T4_E~0); 13912#L1311-1 assume !(0 == ~T5_E~0); 12650#L1316-1 assume !(0 == ~T6_E~0); 12651#L1321-1 assume !(0 == ~T7_E~0); 13415#L1326-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 12478#L1331-1 assume !(0 == ~T9_E~0); 12177#L1336-1 assume !(0 == ~T10_E~0); 12178#L1341-1 assume !(0 == ~T11_E~0); 12258#L1346-1 assume !(0 == ~T12_E~0); 12259#L1351-1 assume !(0 == ~T13_E~0); 12599#L1356-1 assume !(0 == ~E_M~0); 12600#L1361-1 assume !(0 == ~E_1~0); 14127#L1366-1 assume 0 == ~E_2~0;~E_2~0 := 1; 12640#L1371-1 assume !(0 == ~E_3~0); 12641#L1376-1 assume !(0 == ~E_4~0); 13462#L1381-1 assume !(0 == ~E_5~0); 13463#L1386-1 assume !(0 == ~E_6~0); 14157#L1391-1 assume !(0 == ~E_7~0); 14175#L1396-1 assume !(0 == ~E_8~0); 13375#L1401-1 assume !(0 == ~E_9~0); 13376#L1406-1 assume 0 == ~E_10~0;~E_10~0 := 1; 13654#L1411-1 assume !(0 == ~E_11~0); 13655#L1416-1 assume !(0 == ~E_12~0); 13287#L1421-1 assume !(0 == ~E_13~0); 12830#L1426-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12831#L640 assume !(1 == ~m_pc~0); 13340#L640-2 is_master_triggered_~__retres1~0#1 := 0; 13339#L651 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13431#L652 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 13325#L1603 assume !(0 != activate_threads_~tmp~1#1); 13326#L1603-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12960#L659 assume 1 == ~t1_pc~0; 12961#L660 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 13066#L670 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14012#L671 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 13086#L1611 assume !(0 != activate_threads_~tmp___0~0#1); 13087#L1611-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13100#L678 assume 1 == ~t2_pc~0; 14054#L679 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 14055#L689 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14154#L690 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 13198#L1619 assume !(0 != activate_threads_~tmp___1~0#1); 13199#L1619-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 13320#L697 assume !(1 == ~t3_pc~0); 13321#L697-2 is_transmit3_triggered_~__retres1~3#1 := 0; 13443#L708 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13251#L709 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 13230#L1627 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 13231#L1627-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14091#L716 assume 1 == ~t4_pc~0; 14077#L717 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 12941#L727 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12942#L728 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 12441#L1635 assume !(0 != activate_threads_~tmp___3~0#1); 12442#L1635-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13733#L735 assume !(1 == ~t5_pc~0); 12402#L735-2 is_transmit5_triggered_~__retres1~5#1 := 0; 12403#L746 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12853#L747 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 13760#L1643 assume !(0 != activate_threads_~tmp___4~0#1); 13396#L1643-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 13397#L754 assume 1 == ~t6_pc~0; 13150#L755 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 13048#L765 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 13049#L766 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 13022#L1651 assume !(0 != activate_threads_~tmp___5~0#1); 13023#L1651-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 13843#L773 assume !(1 == ~t7_pc~0); 12603#L773-2 is_transmit7_triggered_~__retres1~7#1 := 0; 12602#L784 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 13432#L785 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 13404#L1659 assume !(0 != activate_threads_~tmp___6~0#1); 13405#L1659-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 13452#L792 assume 1 == ~t8_pc~0; 13625#L793 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 13957#L803 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 13446#L804 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 13399#L1667 assume !(0 != activate_threads_~tmp___7~0#1); 13323#L1667-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 13324#L811 assume 1 == ~t9_pc~0; 13528#L812 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 13994#L822 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 13870#L823 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 13524#L1675 assume !(0 != activate_threads_~tmp___8~0#1); 13336#L1675-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 13337#L830 assume !(1 == ~t10_pc~0); 13058#L830-2 is_transmit10_triggered_~__retres1~10#1 := 0; 12582#L841 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 12275#L842 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 12276#L1683 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 12563#L1683-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 13861#L849 assume 1 == ~t11_pc~0; 13862#L850 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 12378#L860 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 12379#L861 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 12968#L1691 assume !(0 != activate_threads_~tmp___10~0#1); 13767#L1691-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 13768#L868 assume !(1 == ~t12_pc~0); 13183#L868-2 is_transmit12_triggered_~__retres1~12#1 := 0; 13182#L879 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 12977#L880 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 12978#L1699 assume !(0 != activate_threads_~tmp___11~0#1); 12614#L1699-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 12615#L887 assume 1 == ~t13_pc~0; 13782#L888 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 13224#L898 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 13225#L899 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 13661#L1707 assume !(0 != activate_threads_~tmp___12~0#1); 12318#L1707-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12319#L1439 assume !(1 == ~M_E~0); 13392#L1439-2 assume !(1 == ~T1_E~0); 12490#L1444-1 assume !(1 == ~T2_E~0); 12491#L1449-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 12964#L1454-1 assume !(1 == ~T4_E~0); 12965#L1459-1 assume !(1 == ~T5_E~0); 13521#L1464-1 assume !(1 == ~T6_E~0); 13522#L1469-1 assume !(1 == ~T7_E~0); 13594#L1474-1 assume !(1 == ~T8_E~0); 13288#L1479-1 assume !(1 == ~T9_E~0); 13289#L1484-1 assume !(1 == ~T10_E~0); 13525#L1489-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 13171#L1494-1 assume !(1 == ~T12_E~0); 13172#L1499-1 assume !(1 == ~T13_E~0); 13364#L1504-1 assume !(1 == ~E_M~0); 13365#L1509-1 assume !(1 == ~E_1~0); 13940#L1514-1 assume !(1 == ~E_2~0); 13627#L1519-1 assume !(1 == ~E_3~0); 13628#L1524-1 assume !(1 == ~E_4~0); 14140#L1529-1 assume 1 == ~E_5~0;~E_5~0 := 2; 14141#L1534-1 assume !(1 == ~E_6~0); 12311#L1539-1 assume !(1 == ~E_7~0); 12312#L1544-1 assume !(1 == ~E_8~0); 12726#L1549-1 assume !(1 == ~E_9~0); 14115#L1554-1 assume !(1 == ~E_10~0); 14111#L1559-1 assume !(1 == ~E_11~0); 13978#L1564-1 assume !(1 == ~E_12~0); 13979#L1569-1 assume 1 == ~E_13~0;~E_13~0 := 2; 14136#L1574-1 assume { :end_inline_reset_delta_events } true; 12488#L1940-2 [2021-12-16 10:05:33,185 INFO L793 eck$LassoCheckResult]: Loop: 12488#L1940-2 assume !false; 12489#L1941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 12771#L1266 assume !false; 13790#L1075 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 13019#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 12752#L1064 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 13143#L1065 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 13144#L1079 assume !(0 != eval_~tmp~0#1); 13105#L1281 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 13106#L907-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 13710#L1291-3 assume 0 == ~M_E~0;~M_E~0 := 1; 13595#L1291-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 13596#L1296-3 assume !(0 == ~T2_E~0); 14168#L1301-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 14122#L1306-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 13253#L1311-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 12529#L1316-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 12530#L1321-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 12630#L1326-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 13387#L1331-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 13636#L1336-3 assume !(0 == ~T10_E~0); 13637#L1341-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 12957#L1346-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 12937#L1351-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 12882#L1356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 12883#L1361-3 assume 0 == ~E_1~0;~E_1~0 := 1; 13444#L1366-3 assume 0 == ~E_2~0;~E_2~0 := 1; 12233#L1371-3 assume 0 == ~E_3~0;~E_3~0 := 1; 12234#L1376-3 assume !(0 == ~E_4~0); 13963#L1381-3 assume 0 == ~E_5~0;~E_5~0 := 1; 13823#L1386-3 assume 0 == ~E_6~0;~E_6~0 := 1; 13824#L1391-3 assume 0 == ~E_7~0;~E_7~0 := 1; 13986#L1396-3 assume 0 == ~E_8~0;~E_8~0 := 1; 13987#L1401-3 assume 0 == ~E_9~0;~E_9~0 := 1; 12596#L1406-3 assume 0 == ~E_10~0;~E_10~0 := 1; 12450#L1411-3 assume 0 == ~E_11~0;~E_11~0 := 1; 12451#L1416-3 assume !(0 == ~E_12~0); 13112#L1421-3 assume 0 == ~E_13~0;~E_13~0 := 1; 13113#L1426-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13220#L640-45 assume !(1 == ~m_pc~0); 13221#L640-47 is_master_triggered_~__retres1~0#1 := 0; 12687#L651-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12688#L652-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12227#L1603-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12228#L1603-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12326#L659-45 assume 1 == ~t1_pc~0; 12327#L660-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 12766#L670-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13725#L671-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 13726#L1611-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 13747#L1611-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13748#L678-45 assume 1 == ~t2_pc~0; 13691#L679-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 13226#L689-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13227#L690-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 13379#L1619-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 14004#L1619-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14121#L697-45 assume 1 == ~t3_pc~0; 13484#L698-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 13485#L708-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14073#L709-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 13643#L1627-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 13644#L1627-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13674#L716-45 assume 1 == ~t4_pc~0; 13305#L717-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 13306#L727-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13856#L728-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 13311#L1635-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 13312#L1635-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12974#L735-45 assume !(1 == ~t5_pc~0); 12976#L735-47 is_transmit5_triggered_~__retres1~5#1 := 0; 13518#L746-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 14080#L747-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 14081#L1643-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 14139#L1643-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14134#L754-45 assume 1 == ~t6_pc~0; 13466#L755-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 13467#L765-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12896#L766-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 12897#L1651-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 13470#L1651-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 13202#L773-45 assume 1 == ~t7_pc~0; 13203#L774-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 12760#L784-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 13680#L785-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 13962#L1659-45 assume !(0 != activate_threads_~tmp___6~0#1); 13208#L1659-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12878#L792-45 assume !(1 == ~t8_pc~0); 12880#L792-47 is_transmit8_triggered_~__retres1~8#1 := 0; 13908#L803-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12481#L804-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 12340#L1667-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 12341#L1667-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 12836#L811-45 assume 1 == ~t9_pc~0; 12625#L812-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 12627#L822-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 13835#L823-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 13670#L1675-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 13279#L1675-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 13071#L830-45 assume 1 == ~t10_pc~0; 13072#L831-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 12269#L841-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 13391#L842-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 12501#L1683-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 12502#L1683-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 12247#L849-45 assume !(1 == ~t11_pc~0); 12248#L849-47 is_transmit11_triggered_~__retres1~11#1 := 0; 12707#L860-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 12338#L861-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 12235#L1691-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 12236#L1691-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 12494#L868-45 assume !(1 == ~t12_pc~0); 12496#L868-47 is_transmit12_triggered_~__retres1~12#1 := 0; 12434#L879-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 12435#L880-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 13773#L1699-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 14024#L1699-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 14025#L887-45 assume !(1 == ~t13_pc~0); 12503#L887-47 is_transmit13_triggered_~__retres1~13#1 := 0; 12504#L898-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 13786#L899-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 14131#L1707-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 12466#L1707-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12467#L1439-3 assume 1 == ~M_E~0;~M_E~0 := 2; 13774#L1439-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12486#L1444-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12487#L1449-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 12644#L1454-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 13575#L1459-3 assume !(1 == ~T5_E~0); 13576#L1464-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 14027#L1469-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 13966#L1474-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 13967#L1479-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 14028#L1484-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 13260#L1489-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 13261#L1494-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 13897#L1499-3 assume !(1 == ~T13_E~0); 13536#L1504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 13537#L1509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 13975#L1514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 14005#L1519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 13179#L1524-3 assume 1 == ~E_4~0;~E_4~0 := 2; 13180#L1529-3 assume 1 == ~E_5~0;~E_5~0 := 2; 14047#L1534-3 assume 1 == ~E_6~0;~E_6~0 := 2; 13447#L1539-3 assume !(1 == ~E_7~0); 12923#L1544-3 assume 1 == ~E_8~0;~E_8~0 := 2; 12924#L1549-3 assume 1 == ~E_9~0;~E_9~0 := 2; 13419#L1554-3 assume 1 == ~E_10~0;~E_10~0 := 2; 12540#L1559-3 assume 1 == ~E_11~0;~E_11~0 := 2; 12541#L1564-3 assume 1 == ~E_12~0;~E_12~0 := 2; 13675#L1569-3 assume 1 == ~E_13~0;~E_13~0 := 2; 13676#L1574-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 12417#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 12188#L1064-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 12463#L1065-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 12424#L1959 assume !(0 == start_simulation_~tmp~3#1); 12426#L1959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 12458#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 12408#L1064-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 13717#L1065-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 13838#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 14045#L1921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 14059#L1922 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 14060#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 12488#L1940-2 [2021-12-16 10:05:33,187 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:33,187 INFO L85 PathProgramCache]: Analyzing trace with hash -992005239, now seen corresponding path program 1 times [2021-12-16 10:05:33,188 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:33,188 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [418960990] [2021-12-16 10:05:33,188 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:33,188 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:33,200 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:33,222 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:05:33,222 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:33,222 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [418960990] [2021-12-16 10:05:33,223 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [418960990] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:33,223 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:33,224 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:05:33,226 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [463037616] [2021-12-16 10:05:33,226 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:33,226 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:05:33,227 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:33,228 INFO L85 PathProgramCache]: Analyzing trace with hash -990138912, now seen corresponding path program 1 times [2021-12-16 10:05:33,228 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:33,231 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1508698509] [2021-12-16 10:05:33,232 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:33,233 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:33,254 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:33,310 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:05:33,310 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:33,311 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1508698509] [2021-12-16 10:05:33,312 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1508698509] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:33,312 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:33,312 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:05:33,312 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [375248877] [2021-12-16 10:05:33,313 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:33,313 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:05:33,314 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:05:33,315 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-16 10:05:33,315 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-16 10:05:33,315 INFO L87 Difference]: Start difference. First operand 2023 states and 2994 transitions. cyclomatic complexity: 972 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:33,352 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:05:33,352 INFO L93 Difference]: Finished difference Result 2023 states and 2993 transitions. [2021-12-16 10:05:33,353 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-16 10:05:33,354 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2023 states and 2993 transitions. [2021-12-16 10:05:33,366 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1848 [2021-12-16 10:05:33,376 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2023 states to 2023 states and 2993 transitions. [2021-12-16 10:05:33,377 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2023 [2021-12-16 10:05:33,378 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2023 [2021-12-16 10:05:33,378 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2023 states and 2993 transitions. [2021-12-16 10:05:33,381 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:05:33,381 INFO L681 BuchiCegarLoop]: Abstraction has 2023 states and 2993 transitions. [2021-12-16 10:05:33,384 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2023 states and 2993 transitions. [2021-12-16 10:05:33,408 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2023 to 2023. [2021-12-16 10:05:33,411 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2023 states, 2023 states have (on average 1.4794859120118635) internal successors, (2993), 2022 states have internal predecessors, (2993), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:33,417 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2023 states to 2023 states and 2993 transitions. [2021-12-16 10:05:33,418 INFO L704 BuchiCegarLoop]: Abstraction has 2023 states and 2993 transitions. [2021-12-16 10:05:33,418 INFO L587 BuchiCegarLoop]: Abstraction has 2023 states and 2993 transitions. [2021-12-16 10:05:33,418 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2021-12-16 10:05:33,418 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2023 states and 2993 transitions. [2021-12-16 10:05:33,430 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1848 [2021-12-16 10:05:33,430 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:05:33,430 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:05:33,432 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:33,433 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:33,433 INFO L791 eck$LassoCheckResult]: Stem: 17155#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 17156#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 18154#L1903 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 18155#L907 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 18240#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 17619#L914-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 17088#L919-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 17089#L924-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 17905#L929-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 17906#L934-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 18006#L939-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 18007#L944-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 16860#L949-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 16861#L954-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 18036#L959-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 17396#L964-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 17397#L969-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 17957#L974-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 17298#L979-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 17299#L1291 assume 0 == ~M_E~0;~M_E~0 := 1; 18241#L1291-2 assume !(0 == ~T1_E~0); 18239#L1296-1 assume !(0 == ~T2_E~0); 17455#L1301-1 assume !(0 == ~T3_E~0); 17456#L1306-1 assume !(0 == ~T4_E~0); 17965#L1311-1 assume !(0 == ~T5_E~0); 16703#L1316-1 assume !(0 == ~T6_E~0); 16704#L1321-1 assume !(0 == ~T7_E~0); 17468#L1326-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 16531#L1331-1 assume !(0 == ~T9_E~0); 16230#L1336-1 assume !(0 == ~T10_E~0); 16231#L1341-1 assume !(0 == ~T11_E~0); 16311#L1346-1 assume !(0 == ~T12_E~0); 16312#L1351-1 assume !(0 == ~T13_E~0); 16652#L1356-1 assume !(0 == ~E_M~0); 16653#L1361-1 assume !(0 == ~E_1~0); 18180#L1366-1 assume 0 == ~E_2~0;~E_2~0 := 1; 16693#L1371-1 assume !(0 == ~E_3~0); 16694#L1376-1 assume !(0 == ~E_4~0); 17515#L1381-1 assume !(0 == ~E_5~0); 17516#L1386-1 assume !(0 == ~E_6~0); 18210#L1391-1 assume !(0 == ~E_7~0); 18228#L1396-1 assume !(0 == ~E_8~0); 17428#L1401-1 assume !(0 == ~E_9~0); 17429#L1406-1 assume 0 == ~E_10~0;~E_10~0 := 1; 17707#L1411-1 assume !(0 == ~E_11~0); 17708#L1416-1 assume !(0 == ~E_12~0); 17340#L1421-1 assume !(0 == ~E_13~0); 16883#L1426-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16884#L640 assume !(1 == ~m_pc~0); 17393#L640-2 is_master_triggered_~__retres1~0#1 := 0; 17392#L651 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 17484#L652 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 17378#L1603 assume !(0 != activate_threads_~tmp~1#1); 17379#L1603-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17013#L659 assume 1 == ~t1_pc~0; 17014#L660 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 17119#L670 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18065#L671 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 17139#L1611 assume !(0 != activate_threads_~tmp___0~0#1); 17140#L1611-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 17153#L678 assume 1 == ~t2_pc~0; 18107#L679 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 18108#L689 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 18207#L690 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 17251#L1619 assume !(0 != activate_threads_~tmp___1~0#1); 17252#L1619-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 17373#L697 assume !(1 == ~t3_pc~0); 17374#L697-2 is_transmit3_triggered_~__retres1~3#1 := 0; 17496#L708 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 17304#L709 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 17283#L1627 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 17284#L1627-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 18144#L716 assume 1 == ~t4_pc~0; 18130#L717 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 16994#L727 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 16995#L728 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 16494#L1635 assume !(0 != activate_threads_~tmp___3~0#1); 16495#L1635-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 17786#L735 assume !(1 == ~t5_pc~0); 16455#L735-2 is_transmit5_triggered_~__retres1~5#1 := 0; 16456#L746 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 16906#L747 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 17813#L1643 assume !(0 != activate_threads_~tmp___4~0#1); 17449#L1643-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 17450#L754 assume 1 == ~t6_pc~0; 17203#L755 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 17101#L765 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 17102#L766 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 17075#L1651 assume !(0 != activate_threads_~tmp___5~0#1); 17076#L1651-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 17896#L773 assume !(1 == ~t7_pc~0); 16656#L773-2 is_transmit7_triggered_~__retres1~7#1 := 0; 16655#L784 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 17485#L785 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 17457#L1659 assume !(0 != activate_threads_~tmp___6~0#1); 17458#L1659-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 17505#L792 assume 1 == ~t8_pc~0; 17678#L793 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 18010#L803 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 17499#L804 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 17452#L1667 assume !(0 != activate_threads_~tmp___7~0#1); 17376#L1667-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 17377#L811 assume 1 == ~t9_pc~0; 17581#L812 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 18047#L822 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 17923#L823 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 17577#L1675 assume !(0 != activate_threads_~tmp___8~0#1); 17389#L1675-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 17390#L830 assume !(1 == ~t10_pc~0); 17111#L830-2 is_transmit10_triggered_~__retres1~10#1 := 0; 16635#L841 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 16328#L842 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 16329#L1683 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 16616#L1683-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 17914#L849 assume 1 == ~t11_pc~0; 17915#L850 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 16431#L860 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 16432#L861 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 17021#L1691 assume !(0 != activate_threads_~tmp___10~0#1); 17820#L1691-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 17821#L868 assume !(1 == ~t12_pc~0); 17236#L868-2 is_transmit12_triggered_~__retres1~12#1 := 0; 17235#L879 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 17030#L880 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 17031#L1699 assume !(0 != activate_threads_~tmp___11~0#1); 16667#L1699-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 16668#L887 assume 1 == ~t13_pc~0; 17835#L888 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 17277#L898 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 17278#L899 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 17714#L1707 assume !(0 != activate_threads_~tmp___12~0#1); 16371#L1707-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16372#L1439 assume !(1 == ~M_E~0); 17445#L1439-2 assume !(1 == ~T1_E~0); 16543#L1444-1 assume !(1 == ~T2_E~0); 16544#L1449-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 17017#L1454-1 assume !(1 == ~T4_E~0); 17018#L1459-1 assume !(1 == ~T5_E~0); 17574#L1464-1 assume !(1 == ~T6_E~0); 17575#L1469-1 assume !(1 == ~T7_E~0); 17647#L1474-1 assume !(1 == ~T8_E~0); 17341#L1479-1 assume !(1 == ~T9_E~0); 17342#L1484-1 assume !(1 == ~T10_E~0); 17578#L1489-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 17224#L1494-1 assume !(1 == ~T12_E~0); 17225#L1499-1 assume !(1 == ~T13_E~0); 17417#L1504-1 assume !(1 == ~E_M~0); 17418#L1509-1 assume !(1 == ~E_1~0); 17993#L1514-1 assume !(1 == ~E_2~0); 17680#L1519-1 assume !(1 == ~E_3~0); 17681#L1524-1 assume !(1 == ~E_4~0); 18193#L1529-1 assume 1 == ~E_5~0;~E_5~0 := 2; 18194#L1534-1 assume !(1 == ~E_6~0); 16364#L1539-1 assume !(1 == ~E_7~0); 16365#L1544-1 assume !(1 == ~E_8~0); 16779#L1549-1 assume !(1 == ~E_9~0); 18168#L1554-1 assume !(1 == ~E_10~0); 18164#L1559-1 assume !(1 == ~E_11~0); 18031#L1564-1 assume !(1 == ~E_12~0); 18032#L1569-1 assume 1 == ~E_13~0;~E_13~0 := 2; 18189#L1574-1 assume { :end_inline_reset_delta_events } true; 16541#L1940-2 [2021-12-16 10:05:33,434 INFO L793 eck$LassoCheckResult]: Loop: 16541#L1940-2 assume !false; 16542#L1941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 16824#L1266 assume !false; 17843#L1075 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 17072#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 16805#L1064 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 17196#L1065 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 17197#L1079 assume !(0 != eval_~tmp~0#1); 17158#L1281 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 17159#L907-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 17763#L1291-3 assume 0 == ~M_E~0;~M_E~0 := 1; 17648#L1291-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 17649#L1296-3 assume !(0 == ~T2_E~0); 18221#L1301-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 18175#L1306-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 17306#L1311-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 16582#L1316-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 16583#L1321-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 16683#L1326-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 17440#L1331-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 17689#L1336-3 assume !(0 == ~T10_E~0); 17690#L1341-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 17010#L1346-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 16990#L1351-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 16935#L1356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 16936#L1361-3 assume 0 == ~E_1~0;~E_1~0 := 1; 17497#L1366-3 assume 0 == ~E_2~0;~E_2~0 := 1; 16286#L1371-3 assume 0 == ~E_3~0;~E_3~0 := 1; 16287#L1376-3 assume !(0 == ~E_4~0); 18016#L1381-3 assume 0 == ~E_5~0;~E_5~0 := 1; 17876#L1386-3 assume 0 == ~E_6~0;~E_6~0 := 1; 17877#L1391-3 assume 0 == ~E_7~0;~E_7~0 := 1; 18039#L1396-3 assume 0 == ~E_8~0;~E_8~0 := 1; 18040#L1401-3 assume 0 == ~E_9~0;~E_9~0 := 1; 16649#L1406-3 assume 0 == ~E_10~0;~E_10~0 := 1; 16503#L1411-3 assume 0 == ~E_11~0;~E_11~0 := 1; 16504#L1416-3 assume !(0 == ~E_12~0); 17165#L1421-3 assume 0 == ~E_13~0;~E_13~0 := 1; 17166#L1426-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17273#L640-45 assume !(1 == ~m_pc~0); 17274#L640-47 is_master_triggered_~__retres1~0#1 := 0; 16740#L651-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16741#L652-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 16280#L1603-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 16281#L1603-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16379#L659-45 assume 1 == ~t1_pc~0; 16380#L660-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 16819#L670-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17778#L671-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 17779#L1611-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 17800#L1611-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 17801#L678-45 assume 1 == ~t2_pc~0; 17744#L679-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 17279#L689-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17280#L690-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 17432#L1619-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 18057#L1619-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18174#L697-45 assume 1 == ~t3_pc~0; 17537#L698-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 17538#L708-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18126#L709-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 17696#L1627-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 17697#L1627-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 17727#L716-45 assume !(1 == ~t4_pc~0); 17360#L716-47 is_transmit4_triggered_~__retres1~4#1 := 0; 17359#L727-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 17909#L728-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 17364#L1635-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 17365#L1635-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 17027#L735-45 assume 1 == ~t5_pc~0; 17028#L736-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 17571#L746-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 18133#L747-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 18134#L1643-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 18192#L1643-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 18187#L754-45 assume !(1 == ~t6_pc~0); 17521#L754-47 is_transmit6_triggered_~__retres1~6#1 := 0; 17520#L765-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 16949#L766-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 16950#L1651-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 17523#L1651-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 17255#L773-45 assume 1 == ~t7_pc~0; 17256#L774-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 16813#L784-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 17733#L785-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 18015#L1659-45 assume !(0 != activate_threads_~tmp___6~0#1); 17261#L1659-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 16931#L792-45 assume 1 == ~t8_pc~0; 16932#L793-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 17961#L803-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 16534#L804-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 16393#L1667-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 16394#L1667-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 16889#L811-45 assume 1 == ~t9_pc~0; 16678#L812-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 16680#L822-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 17888#L823-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 17723#L1675-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 17332#L1675-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 17124#L830-45 assume !(1 == ~t10_pc~0); 16321#L830-47 is_transmit10_triggered_~__retres1~10#1 := 0; 16322#L841-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 17444#L842-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 16554#L1683-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 16555#L1683-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 16300#L849-45 assume !(1 == ~t11_pc~0); 16301#L849-47 is_transmit11_triggered_~__retres1~11#1 := 0; 16760#L860-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 16391#L861-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 16288#L1691-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 16289#L1691-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 16547#L868-45 assume 1 == ~t12_pc~0; 16548#L869-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 16487#L879-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 16488#L880-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 17826#L1699-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 18077#L1699-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 18078#L887-45 assume 1 == ~t13_pc~0; 17908#L888-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 16557#L898-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 17839#L899-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 18184#L1707-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 16519#L1707-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16520#L1439-3 assume 1 == ~M_E~0;~M_E~0 := 2; 17827#L1439-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 16539#L1444-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 16540#L1449-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 16697#L1454-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 17628#L1459-3 assume !(1 == ~T5_E~0); 17629#L1464-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 18080#L1469-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 18019#L1474-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 18020#L1479-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 18081#L1484-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 17313#L1489-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 17314#L1494-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 17950#L1499-3 assume !(1 == ~T13_E~0); 17589#L1504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 17590#L1509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 18028#L1514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 18058#L1519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 17232#L1524-3 assume 1 == ~E_4~0;~E_4~0 := 2; 17233#L1529-3 assume 1 == ~E_5~0;~E_5~0 := 2; 18100#L1534-3 assume 1 == ~E_6~0;~E_6~0 := 2; 17500#L1539-3 assume !(1 == ~E_7~0); 16976#L1544-3 assume 1 == ~E_8~0;~E_8~0 := 2; 16977#L1549-3 assume 1 == ~E_9~0;~E_9~0 := 2; 17472#L1554-3 assume 1 == ~E_10~0;~E_10~0 := 2; 16593#L1559-3 assume 1 == ~E_11~0;~E_11~0 := 2; 16594#L1564-3 assume 1 == ~E_12~0;~E_12~0 := 2; 17728#L1569-3 assume 1 == ~E_13~0;~E_13~0 := 2; 17729#L1574-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 16470#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 16241#L1064-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 16516#L1065-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 16477#L1959 assume !(0 == start_simulation_~tmp~3#1); 16479#L1959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 16511#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 16461#L1064-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 17770#L1065-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 17891#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 18098#L1921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 18112#L1922 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 18113#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 16541#L1940-2 [2021-12-16 10:05:33,434 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:33,435 INFO L85 PathProgramCache]: Analyzing trace with hash -380736181, now seen corresponding path program 1 times [2021-12-16 10:05:33,435 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:33,435 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1343009029] [2021-12-16 10:05:33,435 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:33,436 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:33,450 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:33,470 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:05:33,471 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:33,471 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1343009029] [2021-12-16 10:05:33,471 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1343009029] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:33,471 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:33,472 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:05:33,472 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [898146912] [2021-12-16 10:05:33,472 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:33,472 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:05:33,473 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:33,473 INFO L85 PathProgramCache]: Analyzing trace with hash 1107441823, now seen corresponding path program 1 times [2021-12-16 10:05:33,473 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:33,473 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1131086277] [2021-12-16 10:05:33,474 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:33,474 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:33,489 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:33,524 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:05:33,525 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:33,525 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1131086277] [2021-12-16 10:05:33,526 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1131086277] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:33,526 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:33,526 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:05:33,526 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [732655417] [2021-12-16 10:05:33,527 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:33,527 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:05:33,527 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:05:33,528 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-16 10:05:33,528 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-16 10:05:33,528 INFO L87 Difference]: Start difference. First operand 2023 states and 2993 transitions. cyclomatic complexity: 971 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:33,563 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:05:33,563 INFO L93 Difference]: Finished difference Result 2023 states and 2992 transitions. [2021-12-16 10:05:33,564 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-16 10:05:33,566 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2023 states and 2992 transitions. [2021-12-16 10:05:33,604 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1848 [2021-12-16 10:05:33,613 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2023 states to 2023 states and 2992 transitions. [2021-12-16 10:05:33,613 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2023 [2021-12-16 10:05:33,615 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2023 [2021-12-16 10:05:33,615 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2023 states and 2992 transitions. [2021-12-16 10:05:33,617 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:05:33,618 INFO L681 BuchiCegarLoop]: Abstraction has 2023 states and 2992 transitions. [2021-12-16 10:05:33,620 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2023 states and 2992 transitions. [2021-12-16 10:05:33,644 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2023 to 2023. [2021-12-16 10:05:33,648 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2023 states, 2023 states have (on average 1.4789915966386555) internal successors, (2992), 2022 states have internal predecessors, (2992), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:33,653 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2023 states to 2023 states and 2992 transitions. [2021-12-16 10:05:33,654 INFO L704 BuchiCegarLoop]: Abstraction has 2023 states and 2992 transitions. [2021-12-16 10:05:33,654 INFO L587 BuchiCegarLoop]: Abstraction has 2023 states and 2992 transitions. [2021-12-16 10:05:33,654 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2021-12-16 10:05:33,654 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2023 states and 2992 transitions. [2021-12-16 10:05:33,661 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1848 [2021-12-16 10:05:33,661 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:05:33,661 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:05:33,663 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:33,663 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:33,664 INFO L791 eck$LassoCheckResult]: Stem: 21208#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 21209#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 22207#L1903 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 22208#L907 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 22293#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 21672#L914-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 21141#L919-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 21142#L924-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 21958#L929-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 21959#L934-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 22059#L939-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 22060#L944-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 20913#L949-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 20914#L954-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 22089#L959-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 21449#L964-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 21450#L969-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 22010#L974-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 21351#L979-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 21352#L1291 assume 0 == ~M_E~0;~M_E~0 := 1; 22294#L1291-2 assume !(0 == ~T1_E~0); 22292#L1296-1 assume !(0 == ~T2_E~0); 21508#L1301-1 assume !(0 == ~T3_E~0); 21509#L1306-1 assume !(0 == ~T4_E~0); 22018#L1311-1 assume !(0 == ~T5_E~0); 20756#L1316-1 assume !(0 == ~T6_E~0); 20757#L1321-1 assume !(0 == ~T7_E~0); 21521#L1326-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 20584#L1331-1 assume !(0 == ~T9_E~0); 20283#L1336-1 assume !(0 == ~T10_E~0); 20284#L1341-1 assume !(0 == ~T11_E~0); 20364#L1346-1 assume !(0 == ~T12_E~0); 20365#L1351-1 assume !(0 == ~T13_E~0); 20705#L1356-1 assume !(0 == ~E_M~0); 20706#L1361-1 assume !(0 == ~E_1~0); 22233#L1366-1 assume 0 == ~E_2~0;~E_2~0 := 1; 20746#L1371-1 assume !(0 == ~E_3~0); 20747#L1376-1 assume !(0 == ~E_4~0); 21568#L1381-1 assume !(0 == ~E_5~0); 21569#L1386-1 assume !(0 == ~E_6~0); 22263#L1391-1 assume !(0 == ~E_7~0); 22281#L1396-1 assume !(0 == ~E_8~0); 21481#L1401-1 assume !(0 == ~E_9~0); 21482#L1406-1 assume 0 == ~E_10~0;~E_10~0 := 1; 21760#L1411-1 assume !(0 == ~E_11~0); 21761#L1416-1 assume !(0 == ~E_12~0); 21393#L1421-1 assume !(0 == ~E_13~0); 20936#L1426-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20937#L640 assume !(1 == ~m_pc~0); 21446#L640-2 is_master_triggered_~__retres1~0#1 := 0; 21445#L651 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21537#L652 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 21431#L1603 assume !(0 != activate_threads_~tmp~1#1); 21432#L1603-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 21066#L659 assume 1 == ~t1_pc~0; 21067#L660 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 21172#L670 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22118#L671 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 21192#L1611 assume !(0 != activate_threads_~tmp___0~0#1); 21193#L1611-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 21206#L678 assume 1 == ~t2_pc~0; 22160#L679 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 22161#L689 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 22260#L690 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 21304#L1619 assume !(0 != activate_threads_~tmp___1~0#1); 21305#L1619-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 21426#L697 assume !(1 == ~t3_pc~0); 21427#L697-2 is_transmit3_triggered_~__retres1~3#1 := 0; 21549#L708 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 21357#L709 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 21336#L1627 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 21337#L1627-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 22197#L716 assume 1 == ~t4_pc~0; 22183#L717 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 21047#L727 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 21048#L728 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 20547#L1635 assume !(0 != activate_threads_~tmp___3~0#1); 20548#L1635-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 21839#L735 assume !(1 == ~t5_pc~0); 20508#L735-2 is_transmit5_triggered_~__retres1~5#1 := 0; 20509#L746 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 20959#L747 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 21866#L1643 assume !(0 != activate_threads_~tmp___4~0#1); 21502#L1643-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 21503#L754 assume 1 == ~t6_pc~0; 21256#L755 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 21154#L765 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 21155#L766 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 21128#L1651 assume !(0 != activate_threads_~tmp___5~0#1); 21129#L1651-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 21949#L773 assume !(1 == ~t7_pc~0); 20709#L773-2 is_transmit7_triggered_~__retres1~7#1 := 0; 20708#L784 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 21538#L785 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 21510#L1659 assume !(0 != activate_threads_~tmp___6~0#1); 21511#L1659-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 21558#L792 assume 1 == ~t8_pc~0; 21731#L793 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 22063#L803 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 21552#L804 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 21505#L1667 assume !(0 != activate_threads_~tmp___7~0#1); 21429#L1667-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 21430#L811 assume 1 == ~t9_pc~0; 21634#L812 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 22100#L822 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 21976#L823 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 21630#L1675 assume !(0 != activate_threads_~tmp___8~0#1); 21442#L1675-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 21443#L830 assume !(1 == ~t10_pc~0); 21164#L830-2 is_transmit10_triggered_~__retres1~10#1 := 0; 20688#L841 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 20381#L842 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 20382#L1683 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 20669#L1683-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 21967#L849 assume 1 == ~t11_pc~0; 21968#L850 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 20484#L860 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 20485#L861 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 21074#L1691 assume !(0 != activate_threads_~tmp___10~0#1); 21873#L1691-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 21874#L868 assume !(1 == ~t12_pc~0); 21289#L868-2 is_transmit12_triggered_~__retres1~12#1 := 0; 21288#L879 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 21083#L880 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 21084#L1699 assume !(0 != activate_threads_~tmp___11~0#1); 20720#L1699-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 20721#L887 assume 1 == ~t13_pc~0; 21888#L888 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 21330#L898 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 21331#L899 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 21767#L1707 assume !(0 != activate_threads_~tmp___12~0#1); 20424#L1707-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 20425#L1439 assume !(1 == ~M_E~0); 21498#L1439-2 assume !(1 == ~T1_E~0); 20596#L1444-1 assume !(1 == ~T2_E~0); 20597#L1449-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 21070#L1454-1 assume !(1 == ~T4_E~0); 21071#L1459-1 assume !(1 == ~T5_E~0); 21627#L1464-1 assume !(1 == ~T6_E~0); 21628#L1469-1 assume !(1 == ~T7_E~0); 21700#L1474-1 assume !(1 == ~T8_E~0); 21394#L1479-1 assume !(1 == ~T9_E~0); 21395#L1484-1 assume !(1 == ~T10_E~0); 21631#L1489-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 21277#L1494-1 assume !(1 == ~T12_E~0); 21278#L1499-1 assume !(1 == ~T13_E~0); 21470#L1504-1 assume !(1 == ~E_M~0); 21471#L1509-1 assume !(1 == ~E_1~0); 22046#L1514-1 assume !(1 == ~E_2~0); 21733#L1519-1 assume !(1 == ~E_3~0); 21734#L1524-1 assume !(1 == ~E_4~0); 22246#L1529-1 assume 1 == ~E_5~0;~E_5~0 := 2; 22247#L1534-1 assume !(1 == ~E_6~0); 20417#L1539-1 assume !(1 == ~E_7~0); 20418#L1544-1 assume !(1 == ~E_8~0); 20832#L1549-1 assume !(1 == ~E_9~0); 22221#L1554-1 assume !(1 == ~E_10~0); 22217#L1559-1 assume !(1 == ~E_11~0); 22084#L1564-1 assume !(1 == ~E_12~0); 22085#L1569-1 assume 1 == ~E_13~0;~E_13~0 := 2; 22242#L1574-1 assume { :end_inline_reset_delta_events } true; 20594#L1940-2 [2021-12-16 10:05:33,664 INFO L793 eck$LassoCheckResult]: Loop: 20594#L1940-2 assume !false; 20595#L1941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 20877#L1266 assume !false; 21896#L1075 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 21125#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 20858#L1064 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 21249#L1065 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 21250#L1079 assume !(0 != eval_~tmp~0#1); 21211#L1281 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 21212#L907-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 21816#L1291-3 assume 0 == ~M_E~0;~M_E~0 := 1; 21701#L1291-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 21702#L1296-3 assume !(0 == ~T2_E~0); 22274#L1301-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 22228#L1306-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 21359#L1311-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 20635#L1316-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 20636#L1321-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 20736#L1326-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 21493#L1331-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 21742#L1336-3 assume !(0 == ~T10_E~0); 21743#L1341-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 21063#L1346-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 21043#L1351-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 20988#L1356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 20989#L1361-3 assume 0 == ~E_1~0;~E_1~0 := 1; 21550#L1366-3 assume 0 == ~E_2~0;~E_2~0 := 1; 20339#L1371-3 assume 0 == ~E_3~0;~E_3~0 := 1; 20340#L1376-3 assume !(0 == ~E_4~0); 22069#L1381-3 assume 0 == ~E_5~0;~E_5~0 := 1; 21929#L1386-3 assume 0 == ~E_6~0;~E_6~0 := 1; 21930#L1391-3 assume 0 == ~E_7~0;~E_7~0 := 1; 22092#L1396-3 assume 0 == ~E_8~0;~E_8~0 := 1; 22093#L1401-3 assume 0 == ~E_9~0;~E_9~0 := 1; 20702#L1406-3 assume 0 == ~E_10~0;~E_10~0 := 1; 20556#L1411-3 assume 0 == ~E_11~0;~E_11~0 := 1; 20557#L1416-3 assume !(0 == ~E_12~0); 21218#L1421-3 assume 0 == ~E_13~0;~E_13~0 := 1; 21219#L1426-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 21326#L640-45 assume 1 == ~m_pc~0; 21328#L641-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 20793#L651-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 20794#L652-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 20333#L1603-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 20334#L1603-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 20432#L659-45 assume 1 == ~t1_pc~0; 20433#L660-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 20872#L670-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 21831#L671-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 21832#L1611-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 21853#L1611-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 21854#L678-45 assume 1 == ~t2_pc~0; 21797#L679-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 21332#L689-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 21333#L690-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 21485#L1619-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 22110#L1619-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22227#L697-45 assume 1 == ~t3_pc~0; 21590#L698-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 21591#L708-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22179#L709-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 21749#L1627-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 21750#L1627-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 21780#L716-45 assume 1 == ~t4_pc~0; 21411#L717-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 21412#L727-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 21962#L728-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 21417#L1635-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 21418#L1635-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 21080#L735-45 assume 1 == ~t5_pc~0; 21081#L736-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 21624#L746-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 22186#L747-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 22187#L1643-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 22245#L1643-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 22240#L754-45 assume 1 == ~t6_pc~0; 21572#L755-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 21573#L765-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 21002#L766-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 21003#L1651-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 21576#L1651-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 21308#L773-45 assume !(1 == ~t7_pc~0); 20865#L773-47 is_transmit7_triggered_~__retres1~7#1 := 0; 20866#L784-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 21786#L785-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 22068#L1659-45 assume !(0 != activate_threads_~tmp___6~0#1); 21314#L1659-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 20984#L792-45 assume 1 == ~t8_pc~0; 20985#L793-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 22014#L803-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 20587#L804-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 20446#L1667-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 20447#L1667-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 20942#L811-45 assume 1 == ~t9_pc~0; 20731#L812-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 20733#L822-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 21941#L823-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 21776#L1675-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 21385#L1675-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 21177#L830-45 assume !(1 == ~t10_pc~0); 20374#L830-47 is_transmit10_triggered_~__retres1~10#1 := 0; 20375#L841-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 21497#L842-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 20607#L1683-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 20608#L1683-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 20353#L849-45 assume !(1 == ~t11_pc~0); 20354#L849-47 is_transmit11_triggered_~__retres1~11#1 := 0; 20813#L860-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 20444#L861-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 20341#L1691-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 20342#L1691-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 20600#L868-45 assume 1 == ~t12_pc~0; 20601#L869-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 20540#L879-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 20541#L880-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 21879#L1699-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 22130#L1699-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 22131#L887-45 assume !(1 == ~t13_pc~0); 20609#L887-47 is_transmit13_triggered_~__retres1~13#1 := 0; 20610#L898-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 21892#L899-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 22237#L1707-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 20572#L1707-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 20573#L1439-3 assume 1 == ~M_E~0;~M_E~0 := 2; 21880#L1439-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 20592#L1444-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 20593#L1449-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 20750#L1454-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 21681#L1459-3 assume !(1 == ~T5_E~0); 21682#L1464-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 22133#L1469-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 22072#L1474-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 22073#L1479-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 22134#L1484-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 21366#L1489-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 21367#L1494-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 22003#L1499-3 assume !(1 == ~T13_E~0); 21642#L1504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 21643#L1509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 22081#L1514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 22111#L1519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 21285#L1524-3 assume 1 == ~E_4~0;~E_4~0 := 2; 21286#L1529-3 assume 1 == ~E_5~0;~E_5~0 := 2; 22153#L1534-3 assume 1 == ~E_6~0;~E_6~0 := 2; 21553#L1539-3 assume !(1 == ~E_7~0); 21029#L1544-3 assume 1 == ~E_8~0;~E_8~0 := 2; 21030#L1549-3 assume 1 == ~E_9~0;~E_9~0 := 2; 21525#L1554-3 assume 1 == ~E_10~0;~E_10~0 := 2; 20646#L1559-3 assume 1 == ~E_11~0;~E_11~0 := 2; 20647#L1564-3 assume 1 == ~E_12~0;~E_12~0 := 2; 21781#L1569-3 assume 1 == ~E_13~0;~E_13~0 := 2; 21782#L1574-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 20523#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 20294#L1064-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 20569#L1065-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 20530#L1959 assume !(0 == start_simulation_~tmp~3#1); 20532#L1959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 20564#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 20514#L1064-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 21823#L1065-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 21944#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 22151#L1921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 22165#L1922 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 22166#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 20594#L1940-2 [2021-12-16 10:05:33,672 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:33,672 INFO L85 PathProgramCache]: Analyzing trace with hash 1024455497, now seen corresponding path program 1 times [2021-12-16 10:05:33,673 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:33,673 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1973892473] [2021-12-16 10:05:33,673 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:33,673 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:33,684 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:33,700 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:05:33,701 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:33,701 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1973892473] [2021-12-16 10:05:33,701 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1973892473] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:33,701 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:33,701 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:05:33,702 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [175630046] [2021-12-16 10:05:33,702 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:33,703 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:05:33,706 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:33,707 INFO L85 PathProgramCache]: Analyzing trace with hash 2009983070, now seen corresponding path program 1 times [2021-12-16 10:05:33,707 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:33,711 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1851287038] [2021-12-16 10:05:33,711 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:33,711 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:33,728 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:33,769 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:05:33,770 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:33,770 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1851287038] [2021-12-16 10:05:33,770 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1851287038] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:33,771 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:33,771 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:05:33,771 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1256966286] [2021-12-16 10:05:33,771 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:33,772 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:05:33,772 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:05:33,772 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-16 10:05:33,772 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-16 10:05:33,773 INFO L87 Difference]: Start difference. First operand 2023 states and 2992 transitions. cyclomatic complexity: 970 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:33,806 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:05:33,807 INFO L93 Difference]: Finished difference Result 2023 states and 2991 transitions. [2021-12-16 10:05:33,807 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-16 10:05:33,808 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2023 states and 2991 transitions. [2021-12-16 10:05:33,817 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1848 [2021-12-16 10:05:33,826 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2023 states to 2023 states and 2991 transitions. [2021-12-16 10:05:33,827 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2023 [2021-12-16 10:05:33,828 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2023 [2021-12-16 10:05:33,828 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2023 states and 2991 transitions. [2021-12-16 10:05:33,831 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:05:33,831 INFO L681 BuchiCegarLoop]: Abstraction has 2023 states and 2991 transitions. [2021-12-16 10:05:33,834 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2023 states and 2991 transitions. [2021-12-16 10:05:33,858 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2023 to 2023. [2021-12-16 10:05:33,861 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2023 states, 2023 states have (on average 1.4784972812654473) internal successors, (2991), 2022 states have internal predecessors, (2991), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:33,866 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2023 states to 2023 states and 2991 transitions. [2021-12-16 10:05:33,867 INFO L704 BuchiCegarLoop]: Abstraction has 2023 states and 2991 transitions. [2021-12-16 10:05:33,867 INFO L587 BuchiCegarLoop]: Abstraction has 2023 states and 2991 transitions. [2021-12-16 10:05:33,867 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2021-12-16 10:05:33,867 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2023 states and 2991 transitions. [2021-12-16 10:05:33,874 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1848 [2021-12-16 10:05:33,874 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:05:33,874 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:05:33,876 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:33,877 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:33,877 INFO L791 eck$LassoCheckResult]: Stem: 25261#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 25262#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 26260#L1903 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 26261#L907 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 26346#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 25725#L914-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 25194#L919-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 25195#L924-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 26011#L929-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 26012#L934-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 26112#L939-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 26113#L944-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 24966#L949-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 24967#L954-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 26142#L959-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 25502#L964-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 25503#L969-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 26063#L974-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 25404#L979-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 25405#L1291 assume 0 == ~M_E~0;~M_E~0 := 1; 26347#L1291-2 assume !(0 == ~T1_E~0); 26345#L1296-1 assume !(0 == ~T2_E~0); 25561#L1301-1 assume !(0 == ~T3_E~0); 25562#L1306-1 assume !(0 == ~T4_E~0); 26071#L1311-1 assume !(0 == ~T5_E~0); 24809#L1316-1 assume !(0 == ~T6_E~0); 24810#L1321-1 assume !(0 == ~T7_E~0); 25574#L1326-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 24637#L1331-1 assume !(0 == ~T9_E~0); 24336#L1336-1 assume !(0 == ~T10_E~0); 24337#L1341-1 assume !(0 == ~T11_E~0); 24417#L1346-1 assume !(0 == ~T12_E~0); 24418#L1351-1 assume !(0 == ~T13_E~0); 24758#L1356-1 assume !(0 == ~E_M~0); 24759#L1361-1 assume !(0 == ~E_1~0); 26286#L1366-1 assume 0 == ~E_2~0;~E_2~0 := 1; 24799#L1371-1 assume !(0 == ~E_3~0); 24800#L1376-1 assume !(0 == ~E_4~0); 25621#L1381-1 assume !(0 == ~E_5~0); 25622#L1386-1 assume !(0 == ~E_6~0); 26316#L1391-1 assume !(0 == ~E_7~0); 26334#L1396-1 assume !(0 == ~E_8~0); 25534#L1401-1 assume !(0 == ~E_9~0); 25535#L1406-1 assume 0 == ~E_10~0;~E_10~0 := 1; 25813#L1411-1 assume !(0 == ~E_11~0); 25814#L1416-1 assume !(0 == ~E_12~0); 25446#L1421-1 assume !(0 == ~E_13~0); 24989#L1426-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 24990#L640 assume !(1 == ~m_pc~0); 25499#L640-2 is_master_triggered_~__retres1~0#1 := 0; 25498#L651 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 25590#L652 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 25484#L1603 assume !(0 != activate_threads_~tmp~1#1); 25485#L1603-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 25119#L659 assume 1 == ~t1_pc~0; 25120#L660 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 25225#L670 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 26171#L671 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 25245#L1611 assume !(0 != activate_threads_~tmp___0~0#1); 25246#L1611-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 25259#L678 assume 1 == ~t2_pc~0; 26213#L679 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 26214#L689 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 26313#L690 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 25357#L1619 assume !(0 != activate_threads_~tmp___1~0#1); 25358#L1619-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 25479#L697 assume !(1 == ~t3_pc~0); 25480#L697-2 is_transmit3_triggered_~__retres1~3#1 := 0; 25602#L708 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 25410#L709 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 25389#L1627 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 25390#L1627-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 26250#L716 assume 1 == ~t4_pc~0; 26236#L717 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 25100#L727 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 25101#L728 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 24600#L1635 assume !(0 != activate_threads_~tmp___3~0#1); 24601#L1635-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 25892#L735 assume !(1 == ~t5_pc~0); 24561#L735-2 is_transmit5_triggered_~__retres1~5#1 := 0; 24562#L746 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 25012#L747 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 25919#L1643 assume !(0 != activate_threads_~tmp___4~0#1); 25555#L1643-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 25556#L754 assume 1 == ~t6_pc~0; 25309#L755 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 25207#L765 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 25208#L766 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 25181#L1651 assume !(0 != activate_threads_~tmp___5~0#1); 25182#L1651-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 26002#L773 assume !(1 == ~t7_pc~0); 24762#L773-2 is_transmit7_triggered_~__retres1~7#1 := 0; 24761#L784 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 25591#L785 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 25563#L1659 assume !(0 != activate_threads_~tmp___6~0#1); 25564#L1659-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 25611#L792 assume 1 == ~t8_pc~0; 25784#L793 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 26116#L803 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 25605#L804 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 25558#L1667 assume !(0 != activate_threads_~tmp___7~0#1); 25482#L1667-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 25483#L811 assume 1 == ~t9_pc~0; 25687#L812 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 26153#L822 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 26029#L823 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 25683#L1675 assume !(0 != activate_threads_~tmp___8~0#1); 25495#L1675-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 25496#L830 assume !(1 == ~t10_pc~0); 25217#L830-2 is_transmit10_triggered_~__retres1~10#1 := 0; 24741#L841 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 24434#L842 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 24435#L1683 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 24722#L1683-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 26020#L849 assume 1 == ~t11_pc~0; 26021#L850 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 24537#L860 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 24538#L861 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 25127#L1691 assume !(0 != activate_threads_~tmp___10~0#1); 25926#L1691-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 25927#L868 assume !(1 == ~t12_pc~0); 25342#L868-2 is_transmit12_triggered_~__retres1~12#1 := 0; 25341#L879 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 25136#L880 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 25137#L1699 assume !(0 != activate_threads_~tmp___11~0#1); 24773#L1699-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 24774#L887 assume 1 == ~t13_pc~0; 25941#L888 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 25383#L898 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 25384#L899 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 25820#L1707 assume !(0 != activate_threads_~tmp___12~0#1); 24477#L1707-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 24478#L1439 assume !(1 == ~M_E~0); 25551#L1439-2 assume !(1 == ~T1_E~0); 24649#L1444-1 assume !(1 == ~T2_E~0); 24650#L1449-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 25123#L1454-1 assume !(1 == ~T4_E~0); 25124#L1459-1 assume !(1 == ~T5_E~0); 25680#L1464-1 assume !(1 == ~T6_E~0); 25681#L1469-1 assume !(1 == ~T7_E~0); 25753#L1474-1 assume !(1 == ~T8_E~0); 25447#L1479-1 assume !(1 == ~T9_E~0); 25448#L1484-1 assume !(1 == ~T10_E~0); 25684#L1489-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 25330#L1494-1 assume !(1 == ~T12_E~0); 25331#L1499-1 assume !(1 == ~T13_E~0); 25523#L1504-1 assume !(1 == ~E_M~0); 25524#L1509-1 assume !(1 == ~E_1~0); 26099#L1514-1 assume !(1 == ~E_2~0); 25786#L1519-1 assume !(1 == ~E_3~0); 25787#L1524-1 assume !(1 == ~E_4~0); 26299#L1529-1 assume 1 == ~E_5~0;~E_5~0 := 2; 26300#L1534-1 assume !(1 == ~E_6~0); 24470#L1539-1 assume !(1 == ~E_7~0); 24471#L1544-1 assume !(1 == ~E_8~0); 24885#L1549-1 assume !(1 == ~E_9~0); 26274#L1554-1 assume !(1 == ~E_10~0); 26270#L1559-1 assume !(1 == ~E_11~0); 26137#L1564-1 assume !(1 == ~E_12~0); 26138#L1569-1 assume 1 == ~E_13~0;~E_13~0 := 2; 26295#L1574-1 assume { :end_inline_reset_delta_events } true; 24647#L1940-2 [2021-12-16 10:05:33,878 INFO L793 eck$LassoCheckResult]: Loop: 24647#L1940-2 assume !false; 24648#L1941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 24930#L1266 assume !false; 25949#L1075 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 25178#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 24911#L1064 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 25302#L1065 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 25303#L1079 assume !(0 != eval_~tmp~0#1); 25264#L1281 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 25265#L907-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 25869#L1291-3 assume 0 == ~M_E~0;~M_E~0 := 1; 25754#L1291-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 25755#L1296-3 assume !(0 == ~T2_E~0); 26327#L1301-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 26281#L1306-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 25412#L1311-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 24688#L1316-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 24689#L1321-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 24789#L1326-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 25546#L1331-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 25795#L1336-3 assume !(0 == ~T10_E~0); 25796#L1341-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 25116#L1346-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 25096#L1351-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 25041#L1356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 25042#L1361-3 assume 0 == ~E_1~0;~E_1~0 := 1; 25603#L1366-3 assume 0 == ~E_2~0;~E_2~0 := 1; 24392#L1371-3 assume 0 == ~E_3~0;~E_3~0 := 1; 24393#L1376-3 assume !(0 == ~E_4~0); 26122#L1381-3 assume 0 == ~E_5~0;~E_5~0 := 1; 25982#L1386-3 assume 0 == ~E_6~0;~E_6~0 := 1; 25983#L1391-3 assume 0 == ~E_7~0;~E_7~0 := 1; 26145#L1396-3 assume 0 == ~E_8~0;~E_8~0 := 1; 26146#L1401-3 assume 0 == ~E_9~0;~E_9~0 := 1; 24755#L1406-3 assume 0 == ~E_10~0;~E_10~0 := 1; 24609#L1411-3 assume 0 == ~E_11~0;~E_11~0 := 1; 24610#L1416-3 assume !(0 == ~E_12~0); 25271#L1421-3 assume 0 == ~E_13~0;~E_13~0 := 1; 25272#L1426-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 25379#L640-45 assume !(1 == ~m_pc~0); 25380#L640-47 is_master_triggered_~__retres1~0#1 := 0; 24846#L651-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 24847#L652-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 24386#L1603-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 24387#L1603-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 24485#L659-45 assume 1 == ~t1_pc~0; 24486#L660-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 24925#L670-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 25884#L671-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 25885#L1611-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 25906#L1611-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 25907#L678-45 assume 1 == ~t2_pc~0; 25850#L679-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 25385#L689-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 25386#L690-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 25538#L1619-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 26163#L1619-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 26280#L697-45 assume 1 == ~t3_pc~0; 25643#L698-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 25644#L708-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 26232#L709-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 25802#L1627-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 25803#L1627-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 25833#L716-45 assume 1 == ~t4_pc~0; 25464#L717-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 25465#L727-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 26015#L728-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 25470#L1635-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 25471#L1635-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 25133#L735-45 assume 1 == ~t5_pc~0; 25134#L736-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 25677#L746-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 26239#L747-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 26240#L1643-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 26298#L1643-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 26293#L754-45 assume 1 == ~t6_pc~0; 25625#L755-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 25626#L765-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 25055#L766-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 25056#L1651-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 25629#L1651-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 25361#L773-45 assume 1 == ~t7_pc~0; 25362#L774-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 24919#L784-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 25839#L785-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 26121#L1659-45 assume !(0 != activate_threads_~tmp___6~0#1); 25367#L1659-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 25037#L792-45 assume 1 == ~t8_pc~0; 25038#L793-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 26067#L803-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 24640#L804-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 24499#L1667-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 24500#L1667-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 24995#L811-45 assume 1 == ~t9_pc~0; 24784#L812-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 24786#L822-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 25994#L823-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 25829#L1675-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 25438#L1675-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 25230#L830-45 assume !(1 == ~t10_pc~0); 24427#L830-47 is_transmit10_triggered_~__retres1~10#1 := 0; 24428#L841-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 25550#L842-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 24660#L1683-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 24661#L1683-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 24406#L849-45 assume !(1 == ~t11_pc~0); 24407#L849-47 is_transmit11_triggered_~__retres1~11#1 := 0; 24866#L860-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 24497#L861-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 24394#L1691-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 24395#L1691-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 24653#L868-45 assume 1 == ~t12_pc~0; 24654#L869-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 24593#L879-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 24594#L880-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 25932#L1699-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 26183#L1699-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 26184#L887-45 assume !(1 == ~t13_pc~0); 24662#L887-47 is_transmit13_triggered_~__retres1~13#1 := 0; 24663#L898-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 25945#L899-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 26290#L1707-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 24625#L1707-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 24626#L1439-3 assume 1 == ~M_E~0;~M_E~0 := 2; 25933#L1439-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 24645#L1444-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 24646#L1449-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 24803#L1454-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 25734#L1459-3 assume !(1 == ~T5_E~0); 25735#L1464-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 26186#L1469-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 26125#L1474-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 26126#L1479-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 26187#L1484-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 25419#L1489-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 25420#L1494-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 26056#L1499-3 assume !(1 == ~T13_E~0); 25695#L1504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 25696#L1509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 26134#L1514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 26164#L1519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 25338#L1524-3 assume 1 == ~E_4~0;~E_4~0 := 2; 25339#L1529-3 assume 1 == ~E_5~0;~E_5~0 := 2; 26206#L1534-3 assume 1 == ~E_6~0;~E_6~0 := 2; 25606#L1539-3 assume !(1 == ~E_7~0); 25082#L1544-3 assume 1 == ~E_8~0;~E_8~0 := 2; 25083#L1549-3 assume 1 == ~E_9~0;~E_9~0 := 2; 25578#L1554-3 assume 1 == ~E_10~0;~E_10~0 := 2; 24699#L1559-3 assume 1 == ~E_11~0;~E_11~0 := 2; 24700#L1564-3 assume 1 == ~E_12~0;~E_12~0 := 2; 25834#L1569-3 assume 1 == ~E_13~0;~E_13~0 := 2; 25835#L1574-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 24576#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 24347#L1064-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 24622#L1065-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 24583#L1959 assume !(0 == start_simulation_~tmp~3#1); 24585#L1959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 24617#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 24567#L1064-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 25876#L1065-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 25997#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 26204#L1921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 26218#L1922 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 26219#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 24647#L1940-2 [2021-12-16 10:05:33,878 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:33,878 INFO L85 PathProgramCache]: Analyzing trace with hash -869878389, now seen corresponding path program 1 times [2021-12-16 10:05:33,879 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:33,879 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1506437723] [2021-12-16 10:05:33,879 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:33,879 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:33,890 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:33,906 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:05:33,907 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:33,907 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1506437723] [2021-12-16 10:05:33,907 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1506437723] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:33,907 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:33,907 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:05:33,907 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [424502794] [2021-12-16 10:05:33,908 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:33,908 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:05:33,908 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:33,909 INFO L85 PathProgramCache]: Analyzing trace with hash 1630672670, now seen corresponding path program 1 times [2021-12-16 10:05:33,909 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:33,909 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [309008303] [2021-12-16 10:05:33,909 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:33,909 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:33,922 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:33,946 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:05:33,947 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:33,947 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [309008303] [2021-12-16 10:05:33,947 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [309008303] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:33,947 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:33,947 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:05:33,947 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1997402967] [2021-12-16 10:05:33,948 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:33,948 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:05:33,948 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:05:33,948 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-16 10:05:33,949 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-16 10:05:33,949 INFO L87 Difference]: Start difference. First operand 2023 states and 2991 transitions. cyclomatic complexity: 969 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:34,007 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:05:34,008 INFO L93 Difference]: Finished difference Result 2023 states and 2990 transitions. [2021-12-16 10:05:34,009 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-16 10:05:34,010 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2023 states and 2990 transitions. [2021-12-16 10:05:34,018 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1848 [2021-12-16 10:05:34,026 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2023 states to 2023 states and 2990 transitions. [2021-12-16 10:05:34,026 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2023 [2021-12-16 10:05:34,028 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2023 [2021-12-16 10:05:34,028 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2023 states and 2990 transitions. [2021-12-16 10:05:34,030 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:05:34,030 INFO L681 BuchiCegarLoop]: Abstraction has 2023 states and 2990 transitions. [2021-12-16 10:05:34,033 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2023 states and 2990 transitions. [2021-12-16 10:05:34,054 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2023 to 2023. [2021-12-16 10:05:34,058 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2023 states, 2023 states have (on average 1.4780029658922393) internal successors, (2990), 2022 states have internal predecessors, (2990), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:34,063 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2023 states to 2023 states and 2990 transitions. [2021-12-16 10:05:34,063 INFO L704 BuchiCegarLoop]: Abstraction has 2023 states and 2990 transitions. [2021-12-16 10:05:34,063 INFO L587 BuchiCegarLoop]: Abstraction has 2023 states and 2990 transitions. [2021-12-16 10:05:34,063 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2021-12-16 10:05:34,063 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2023 states and 2990 transitions. [2021-12-16 10:05:34,069 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1848 [2021-12-16 10:05:34,070 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:05:34,070 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:05:34,072 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:34,072 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:34,072 INFO L791 eck$LassoCheckResult]: Stem: 29314#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 29315#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 30313#L1903 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 30314#L907 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 30399#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 29778#L914-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 29247#L919-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 29248#L924-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 30064#L929-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 30065#L934-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 30165#L939-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 30166#L944-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 29019#L949-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 29020#L954-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 30195#L959-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 29555#L964-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 29556#L969-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 30116#L974-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 29457#L979-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 29458#L1291 assume 0 == ~M_E~0;~M_E~0 := 1; 30400#L1291-2 assume !(0 == ~T1_E~0); 30398#L1296-1 assume !(0 == ~T2_E~0); 29614#L1301-1 assume !(0 == ~T3_E~0); 29615#L1306-1 assume !(0 == ~T4_E~0); 30124#L1311-1 assume !(0 == ~T5_E~0); 28862#L1316-1 assume !(0 == ~T6_E~0); 28863#L1321-1 assume !(0 == ~T7_E~0); 29627#L1326-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 28690#L1331-1 assume !(0 == ~T9_E~0); 28389#L1336-1 assume !(0 == ~T10_E~0); 28390#L1341-1 assume !(0 == ~T11_E~0); 28470#L1346-1 assume !(0 == ~T12_E~0); 28471#L1351-1 assume !(0 == ~T13_E~0); 28811#L1356-1 assume !(0 == ~E_M~0); 28812#L1361-1 assume !(0 == ~E_1~0); 30339#L1366-1 assume 0 == ~E_2~0;~E_2~0 := 1; 28852#L1371-1 assume !(0 == ~E_3~0); 28853#L1376-1 assume !(0 == ~E_4~0); 29674#L1381-1 assume !(0 == ~E_5~0); 29675#L1386-1 assume !(0 == ~E_6~0); 30369#L1391-1 assume !(0 == ~E_7~0); 30387#L1396-1 assume !(0 == ~E_8~0); 29587#L1401-1 assume !(0 == ~E_9~0); 29588#L1406-1 assume 0 == ~E_10~0;~E_10~0 := 1; 29866#L1411-1 assume !(0 == ~E_11~0); 29867#L1416-1 assume !(0 == ~E_12~0); 29499#L1421-1 assume !(0 == ~E_13~0); 29042#L1426-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 29043#L640 assume !(1 == ~m_pc~0); 29552#L640-2 is_master_triggered_~__retres1~0#1 := 0; 29551#L651 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 29643#L652 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 29537#L1603 assume !(0 != activate_threads_~tmp~1#1); 29538#L1603-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 29172#L659 assume 1 == ~t1_pc~0; 29173#L660 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 29278#L670 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 30224#L671 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 29298#L1611 assume !(0 != activate_threads_~tmp___0~0#1); 29299#L1611-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 29312#L678 assume 1 == ~t2_pc~0; 30266#L679 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 30267#L689 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 30366#L690 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 29410#L1619 assume !(0 != activate_threads_~tmp___1~0#1); 29411#L1619-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 29532#L697 assume !(1 == ~t3_pc~0); 29533#L697-2 is_transmit3_triggered_~__retres1~3#1 := 0; 29655#L708 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 29463#L709 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 29442#L1627 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 29443#L1627-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 30303#L716 assume 1 == ~t4_pc~0; 30289#L717 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 29153#L727 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 29154#L728 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 28653#L1635 assume !(0 != activate_threads_~tmp___3~0#1); 28654#L1635-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 29945#L735 assume !(1 == ~t5_pc~0); 28614#L735-2 is_transmit5_triggered_~__retres1~5#1 := 0; 28615#L746 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 29065#L747 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 29972#L1643 assume !(0 != activate_threads_~tmp___4~0#1); 29608#L1643-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 29609#L754 assume 1 == ~t6_pc~0; 29362#L755 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 29260#L765 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 29261#L766 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 29234#L1651 assume !(0 != activate_threads_~tmp___5~0#1); 29235#L1651-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 30055#L773 assume !(1 == ~t7_pc~0); 28815#L773-2 is_transmit7_triggered_~__retres1~7#1 := 0; 28814#L784 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 29644#L785 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 29616#L1659 assume !(0 != activate_threads_~tmp___6~0#1); 29617#L1659-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 29664#L792 assume 1 == ~t8_pc~0; 29837#L793 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 30169#L803 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 29658#L804 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 29611#L1667 assume !(0 != activate_threads_~tmp___7~0#1); 29535#L1667-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 29536#L811 assume 1 == ~t9_pc~0; 29740#L812 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 30206#L822 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 30082#L823 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 29736#L1675 assume !(0 != activate_threads_~tmp___8~0#1); 29548#L1675-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 29549#L830 assume !(1 == ~t10_pc~0); 29270#L830-2 is_transmit10_triggered_~__retres1~10#1 := 0; 28794#L841 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 28487#L842 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 28488#L1683 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 28775#L1683-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 30073#L849 assume 1 == ~t11_pc~0; 30074#L850 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 28590#L860 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 28591#L861 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 29180#L1691 assume !(0 != activate_threads_~tmp___10~0#1); 29979#L1691-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 29980#L868 assume !(1 == ~t12_pc~0); 29395#L868-2 is_transmit12_triggered_~__retres1~12#1 := 0; 29394#L879 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 29189#L880 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 29190#L1699 assume !(0 != activate_threads_~tmp___11~0#1); 28826#L1699-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 28827#L887 assume 1 == ~t13_pc~0; 29994#L888 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 29436#L898 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 29437#L899 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 29873#L1707 assume !(0 != activate_threads_~tmp___12~0#1); 28530#L1707-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 28531#L1439 assume !(1 == ~M_E~0); 29604#L1439-2 assume !(1 == ~T1_E~0); 28702#L1444-1 assume !(1 == ~T2_E~0); 28703#L1449-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 29176#L1454-1 assume !(1 == ~T4_E~0); 29177#L1459-1 assume !(1 == ~T5_E~0); 29733#L1464-1 assume !(1 == ~T6_E~0); 29734#L1469-1 assume !(1 == ~T7_E~0); 29806#L1474-1 assume !(1 == ~T8_E~0); 29500#L1479-1 assume !(1 == ~T9_E~0); 29501#L1484-1 assume !(1 == ~T10_E~0); 29737#L1489-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 29383#L1494-1 assume !(1 == ~T12_E~0); 29384#L1499-1 assume !(1 == ~T13_E~0); 29576#L1504-1 assume !(1 == ~E_M~0); 29577#L1509-1 assume !(1 == ~E_1~0); 30152#L1514-1 assume !(1 == ~E_2~0); 29839#L1519-1 assume !(1 == ~E_3~0); 29840#L1524-1 assume !(1 == ~E_4~0); 30352#L1529-1 assume 1 == ~E_5~0;~E_5~0 := 2; 30353#L1534-1 assume !(1 == ~E_6~0); 28523#L1539-1 assume !(1 == ~E_7~0); 28524#L1544-1 assume !(1 == ~E_8~0); 28938#L1549-1 assume !(1 == ~E_9~0); 30327#L1554-1 assume !(1 == ~E_10~0); 30323#L1559-1 assume !(1 == ~E_11~0); 30190#L1564-1 assume !(1 == ~E_12~0); 30191#L1569-1 assume 1 == ~E_13~0;~E_13~0 := 2; 30348#L1574-1 assume { :end_inline_reset_delta_events } true; 28700#L1940-2 [2021-12-16 10:05:34,073 INFO L793 eck$LassoCheckResult]: Loop: 28700#L1940-2 assume !false; 28701#L1941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 28983#L1266 assume !false; 30002#L1075 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 29231#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 28964#L1064 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 29355#L1065 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 29356#L1079 assume !(0 != eval_~tmp~0#1); 29317#L1281 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 29318#L907-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 29922#L1291-3 assume 0 == ~M_E~0;~M_E~0 := 1; 29807#L1291-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 29808#L1296-3 assume !(0 == ~T2_E~0); 30380#L1301-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 30334#L1306-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 29465#L1311-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 28741#L1316-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 28742#L1321-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 28842#L1326-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 29599#L1331-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 29848#L1336-3 assume !(0 == ~T10_E~0); 29849#L1341-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 29169#L1346-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 29149#L1351-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 29094#L1356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 29095#L1361-3 assume 0 == ~E_1~0;~E_1~0 := 1; 29656#L1366-3 assume 0 == ~E_2~0;~E_2~0 := 1; 28445#L1371-3 assume 0 == ~E_3~0;~E_3~0 := 1; 28446#L1376-3 assume !(0 == ~E_4~0); 30175#L1381-3 assume 0 == ~E_5~0;~E_5~0 := 1; 30035#L1386-3 assume 0 == ~E_6~0;~E_6~0 := 1; 30036#L1391-3 assume 0 == ~E_7~0;~E_7~0 := 1; 30198#L1396-3 assume 0 == ~E_8~0;~E_8~0 := 1; 30199#L1401-3 assume 0 == ~E_9~0;~E_9~0 := 1; 28808#L1406-3 assume 0 == ~E_10~0;~E_10~0 := 1; 28662#L1411-3 assume 0 == ~E_11~0;~E_11~0 := 1; 28663#L1416-3 assume !(0 == ~E_12~0); 29324#L1421-3 assume 0 == ~E_13~0;~E_13~0 := 1; 29325#L1426-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 29432#L640-45 assume !(1 == ~m_pc~0); 29433#L640-47 is_master_triggered_~__retres1~0#1 := 0; 28899#L651-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 28900#L652-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 28439#L1603-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 28440#L1603-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 28538#L659-45 assume 1 == ~t1_pc~0; 28539#L660-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 28978#L670-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 29937#L671-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 29938#L1611-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 29959#L1611-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 29960#L678-45 assume !(1 == ~t2_pc~0); 29904#L678-47 is_transmit2_triggered_~__retres1~2#1 := 0; 29438#L689-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29439#L690-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 29591#L1619-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 30216#L1619-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 30333#L697-45 assume 1 == ~t3_pc~0; 29696#L698-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 29697#L708-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 30285#L709-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 29855#L1627-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 29856#L1627-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 29886#L716-45 assume 1 == ~t4_pc~0; 29517#L717-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 29518#L727-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 30068#L728-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 29523#L1635-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 29524#L1635-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 29186#L735-45 assume 1 == ~t5_pc~0; 29187#L736-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 29730#L746-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 30292#L747-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 30293#L1643-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 30351#L1643-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 30346#L754-45 assume !(1 == ~t6_pc~0); 29680#L754-47 is_transmit6_triggered_~__retres1~6#1 := 0; 29679#L765-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 29108#L766-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 29109#L1651-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 29682#L1651-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 29414#L773-45 assume 1 == ~t7_pc~0; 29415#L774-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 28972#L784-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 29892#L785-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 30174#L1659-45 assume !(0 != activate_threads_~tmp___6~0#1); 29420#L1659-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 29090#L792-45 assume 1 == ~t8_pc~0; 29091#L793-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 30120#L803-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 28693#L804-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 28552#L1667-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 28553#L1667-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 29048#L811-45 assume 1 == ~t9_pc~0; 28837#L812-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 28839#L822-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 30047#L823-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 29882#L1675-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 29491#L1675-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 29283#L830-45 assume !(1 == ~t10_pc~0); 28480#L830-47 is_transmit10_triggered_~__retres1~10#1 := 0; 28481#L841-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 29603#L842-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 28713#L1683-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 28714#L1683-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 28459#L849-45 assume !(1 == ~t11_pc~0); 28460#L849-47 is_transmit11_triggered_~__retres1~11#1 := 0; 28919#L860-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 28550#L861-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 28447#L1691-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 28448#L1691-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 28706#L868-45 assume 1 == ~t12_pc~0; 28707#L869-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 28646#L879-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 28647#L880-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 29985#L1699-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 30236#L1699-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 30237#L887-45 assume 1 == ~t13_pc~0; 30067#L888-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 28716#L898-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 29998#L899-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 30343#L1707-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 28678#L1707-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 28679#L1439-3 assume 1 == ~M_E~0;~M_E~0 := 2; 29986#L1439-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 28698#L1444-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 28699#L1449-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 28856#L1454-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 29787#L1459-3 assume !(1 == ~T5_E~0); 29788#L1464-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 30239#L1469-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 30178#L1474-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 30179#L1479-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 30240#L1484-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 29472#L1489-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 29473#L1494-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 30109#L1499-3 assume !(1 == ~T13_E~0); 29748#L1504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 29749#L1509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 30187#L1514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 30217#L1519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 29391#L1524-3 assume 1 == ~E_4~0;~E_4~0 := 2; 29392#L1529-3 assume 1 == ~E_5~0;~E_5~0 := 2; 30259#L1534-3 assume 1 == ~E_6~0;~E_6~0 := 2; 29659#L1539-3 assume !(1 == ~E_7~0); 29135#L1544-3 assume 1 == ~E_8~0;~E_8~0 := 2; 29136#L1549-3 assume 1 == ~E_9~0;~E_9~0 := 2; 29631#L1554-3 assume 1 == ~E_10~0;~E_10~0 := 2; 28752#L1559-3 assume 1 == ~E_11~0;~E_11~0 := 2; 28753#L1564-3 assume 1 == ~E_12~0;~E_12~0 := 2; 29887#L1569-3 assume 1 == ~E_13~0;~E_13~0 := 2; 29888#L1574-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 28629#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 28400#L1064-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 28675#L1065-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 28636#L1959 assume !(0 == start_simulation_~tmp~3#1); 28638#L1959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 28670#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 28620#L1064-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 29929#L1065-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 30050#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 30257#L1921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 30271#L1922 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 30272#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 28700#L1940-2 [2021-12-16 10:05:34,074 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:34,074 INFO L85 PathProgramCache]: Analyzing trace with hash 1978508041, now seen corresponding path program 1 times [2021-12-16 10:05:34,074 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:34,074 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [46885589] [2021-12-16 10:05:34,074 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:34,074 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:34,084 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:34,100 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:05:34,101 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:34,101 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [46885589] [2021-12-16 10:05:34,101 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [46885589] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:34,101 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:34,101 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:05:34,102 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1133891383] [2021-12-16 10:05:34,102 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:34,102 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:05:34,102 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:34,103 INFO L85 PathProgramCache]: Analyzing trace with hash -1140908257, now seen corresponding path program 1 times [2021-12-16 10:05:34,103 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:34,103 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [69976943] [2021-12-16 10:05:34,103 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:34,103 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:34,115 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:34,139 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:05:34,140 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:34,140 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [69976943] [2021-12-16 10:05:34,140 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [69976943] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:34,140 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:34,140 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:05:34,141 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2094463314] [2021-12-16 10:05:34,141 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:34,141 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:05:34,141 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:05:34,142 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-16 10:05:34,142 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-16 10:05:34,142 INFO L87 Difference]: Start difference. First operand 2023 states and 2990 transitions. cyclomatic complexity: 968 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:34,174 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:05:34,174 INFO L93 Difference]: Finished difference Result 2023 states and 2989 transitions. [2021-12-16 10:05:34,174 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-16 10:05:34,175 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2023 states and 2989 transitions. [2021-12-16 10:05:34,183 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1848 [2021-12-16 10:05:34,191 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2023 states to 2023 states and 2989 transitions. [2021-12-16 10:05:34,191 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2023 [2021-12-16 10:05:34,193 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2023 [2021-12-16 10:05:34,193 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2023 states and 2989 transitions. [2021-12-16 10:05:34,195 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:05:34,195 INFO L681 BuchiCegarLoop]: Abstraction has 2023 states and 2989 transitions. [2021-12-16 10:05:34,198 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2023 states and 2989 transitions. [2021-12-16 10:05:34,219 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2023 to 2023. [2021-12-16 10:05:34,222 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2023 states, 2023 states have (on average 1.4775086505190311) internal successors, (2989), 2022 states have internal predecessors, (2989), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:34,227 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2023 states to 2023 states and 2989 transitions. [2021-12-16 10:05:34,227 INFO L704 BuchiCegarLoop]: Abstraction has 2023 states and 2989 transitions. [2021-12-16 10:05:34,228 INFO L587 BuchiCegarLoop]: Abstraction has 2023 states and 2989 transitions. [2021-12-16 10:05:34,228 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2021-12-16 10:05:34,228 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2023 states and 2989 transitions. [2021-12-16 10:05:34,234 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1848 [2021-12-16 10:05:34,235 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:05:34,235 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:05:34,237 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:34,237 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:34,237 INFO L791 eck$LassoCheckResult]: Stem: 33367#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 33368#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 34366#L1903 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 34367#L907 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 34452#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 33831#L914-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 33300#L919-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 33301#L924-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 34117#L929-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 34118#L934-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 34218#L939-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 34219#L944-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 33072#L949-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 33073#L954-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 34248#L959-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 33608#L964-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 33609#L969-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 34169#L974-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 33510#L979-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 33511#L1291 assume 0 == ~M_E~0;~M_E~0 := 1; 34453#L1291-2 assume !(0 == ~T1_E~0); 34451#L1296-1 assume !(0 == ~T2_E~0); 33667#L1301-1 assume !(0 == ~T3_E~0); 33668#L1306-1 assume !(0 == ~T4_E~0); 34177#L1311-1 assume !(0 == ~T5_E~0); 32915#L1316-1 assume !(0 == ~T6_E~0); 32916#L1321-1 assume !(0 == ~T7_E~0); 33680#L1326-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 32743#L1331-1 assume !(0 == ~T9_E~0); 32442#L1336-1 assume !(0 == ~T10_E~0); 32443#L1341-1 assume !(0 == ~T11_E~0); 32523#L1346-1 assume !(0 == ~T12_E~0); 32524#L1351-1 assume !(0 == ~T13_E~0); 32864#L1356-1 assume !(0 == ~E_M~0); 32865#L1361-1 assume !(0 == ~E_1~0); 34392#L1366-1 assume 0 == ~E_2~0;~E_2~0 := 1; 32905#L1371-1 assume !(0 == ~E_3~0); 32906#L1376-1 assume !(0 == ~E_4~0); 33727#L1381-1 assume !(0 == ~E_5~0); 33728#L1386-1 assume !(0 == ~E_6~0); 34422#L1391-1 assume !(0 == ~E_7~0); 34440#L1396-1 assume !(0 == ~E_8~0); 33640#L1401-1 assume !(0 == ~E_9~0); 33641#L1406-1 assume 0 == ~E_10~0;~E_10~0 := 1; 33919#L1411-1 assume !(0 == ~E_11~0); 33920#L1416-1 assume !(0 == ~E_12~0); 33552#L1421-1 assume !(0 == ~E_13~0); 33095#L1426-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 33096#L640 assume !(1 == ~m_pc~0); 33605#L640-2 is_master_triggered_~__retres1~0#1 := 0; 33604#L651 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 33696#L652 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 33590#L1603 assume !(0 != activate_threads_~tmp~1#1); 33591#L1603-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 33225#L659 assume 1 == ~t1_pc~0; 33226#L660 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 33331#L670 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 34277#L671 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 33351#L1611 assume !(0 != activate_threads_~tmp___0~0#1); 33352#L1611-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 33365#L678 assume 1 == ~t2_pc~0; 34319#L679 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 34320#L689 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 34419#L690 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 33463#L1619 assume !(0 != activate_threads_~tmp___1~0#1); 33464#L1619-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 33585#L697 assume !(1 == ~t3_pc~0); 33586#L697-2 is_transmit3_triggered_~__retres1~3#1 := 0; 33708#L708 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 33516#L709 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 33495#L1627 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 33496#L1627-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 34356#L716 assume 1 == ~t4_pc~0; 34342#L717 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 33206#L727 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 33207#L728 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 32706#L1635 assume !(0 != activate_threads_~tmp___3~0#1); 32707#L1635-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 33998#L735 assume !(1 == ~t5_pc~0); 32667#L735-2 is_transmit5_triggered_~__retres1~5#1 := 0; 32668#L746 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 33118#L747 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 34025#L1643 assume !(0 != activate_threads_~tmp___4~0#1); 33661#L1643-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 33662#L754 assume 1 == ~t6_pc~0; 33415#L755 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 33313#L765 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 33314#L766 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 33287#L1651 assume !(0 != activate_threads_~tmp___5~0#1); 33288#L1651-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 34108#L773 assume !(1 == ~t7_pc~0); 32868#L773-2 is_transmit7_triggered_~__retres1~7#1 := 0; 32867#L784 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 33697#L785 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 33669#L1659 assume !(0 != activate_threads_~tmp___6~0#1); 33670#L1659-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 33717#L792 assume 1 == ~t8_pc~0; 33890#L793 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 34222#L803 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 33711#L804 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 33664#L1667 assume !(0 != activate_threads_~tmp___7~0#1); 33588#L1667-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 33589#L811 assume 1 == ~t9_pc~0; 33793#L812 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 34259#L822 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 34135#L823 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 33789#L1675 assume !(0 != activate_threads_~tmp___8~0#1); 33601#L1675-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 33602#L830 assume !(1 == ~t10_pc~0); 33323#L830-2 is_transmit10_triggered_~__retres1~10#1 := 0; 32847#L841 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 32540#L842 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 32541#L1683 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 32828#L1683-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 34126#L849 assume 1 == ~t11_pc~0; 34127#L850 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 32643#L860 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 32644#L861 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 33233#L1691 assume !(0 != activate_threads_~tmp___10~0#1); 34032#L1691-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 34033#L868 assume !(1 == ~t12_pc~0); 33448#L868-2 is_transmit12_triggered_~__retres1~12#1 := 0; 33447#L879 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 33242#L880 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 33243#L1699 assume !(0 != activate_threads_~tmp___11~0#1); 32879#L1699-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 32880#L887 assume 1 == ~t13_pc~0; 34047#L888 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 33489#L898 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 33490#L899 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 33926#L1707 assume !(0 != activate_threads_~tmp___12~0#1); 32583#L1707-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 32584#L1439 assume !(1 == ~M_E~0); 33657#L1439-2 assume !(1 == ~T1_E~0); 32755#L1444-1 assume !(1 == ~T2_E~0); 32756#L1449-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 33229#L1454-1 assume !(1 == ~T4_E~0); 33230#L1459-1 assume !(1 == ~T5_E~0); 33786#L1464-1 assume !(1 == ~T6_E~0); 33787#L1469-1 assume !(1 == ~T7_E~0); 33859#L1474-1 assume !(1 == ~T8_E~0); 33553#L1479-1 assume !(1 == ~T9_E~0); 33554#L1484-1 assume !(1 == ~T10_E~0); 33790#L1489-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 33436#L1494-1 assume !(1 == ~T12_E~0); 33437#L1499-1 assume !(1 == ~T13_E~0); 33629#L1504-1 assume !(1 == ~E_M~0); 33630#L1509-1 assume !(1 == ~E_1~0); 34205#L1514-1 assume !(1 == ~E_2~0); 33892#L1519-1 assume !(1 == ~E_3~0); 33893#L1524-1 assume !(1 == ~E_4~0); 34405#L1529-1 assume 1 == ~E_5~0;~E_5~0 := 2; 34406#L1534-1 assume !(1 == ~E_6~0); 32576#L1539-1 assume !(1 == ~E_7~0); 32577#L1544-1 assume !(1 == ~E_8~0); 32991#L1549-1 assume !(1 == ~E_9~0); 34380#L1554-1 assume !(1 == ~E_10~0); 34376#L1559-1 assume !(1 == ~E_11~0); 34243#L1564-1 assume !(1 == ~E_12~0); 34244#L1569-1 assume 1 == ~E_13~0;~E_13~0 := 2; 34401#L1574-1 assume { :end_inline_reset_delta_events } true; 32753#L1940-2 [2021-12-16 10:05:34,238 INFO L793 eck$LassoCheckResult]: Loop: 32753#L1940-2 assume !false; 32754#L1941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 33036#L1266 assume !false; 34055#L1075 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 33284#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 33017#L1064 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 33408#L1065 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 33409#L1079 assume !(0 != eval_~tmp~0#1); 33370#L1281 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 33371#L907-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 33975#L1291-3 assume 0 == ~M_E~0;~M_E~0 := 1; 33860#L1291-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 33861#L1296-3 assume !(0 == ~T2_E~0); 34433#L1301-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 34387#L1306-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 33518#L1311-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 32794#L1316-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 32795#L1321-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 32895#L1326-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 33652#L1331-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 33901#L1336-3 assume !(0 == ~T10_E~0); 33902#L1341-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 33222#L1346-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 33202#L1351-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 33147#L1356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 33148#L1361-3 assume 0 == ~E_1~0;~E_1~0 := 1; 33709#L1366-3 assume 0 == ~E_2~0;~E_2~0 := 1; 32498#L1371-3 assume 0 == ~E_3~0;~E_3~0 := 1; 32499#L1376-3 assume !(0 == ~E_4~0); 34228#L1381-3 assume 0 == ~E_5~0;~E_5~0 := 1; 34088#L1386-3 assume 0 == ~E_6~0;~E_6~0 := 1; 34089#L1391-3 assume 0 == ~E_7~0;~E_7~0 := 1; 34251#L1396-3 assume 0 == ~E_8~0;~E_8~0 := 1; 34252#L1401-3 assume 0 == ~E_9~0;~E_9~0 := 1; 32861#L1406-3 assume 0 == ~E_10~0;~E_10~0 := 1; 32715#L1411-3 assume 0 == ~E_11~0;~E_11~0 := 1; 32716#L1416-3 assume !(0 == ~E_12~0); 33377#L1421-3 assume 0 == ~E_13~0;~E_13~0 := 1; 33378#L1426-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 33485#L640-45 assume !(1 == ~m_pc~0); 33486#L640-47 is_master_triggered_~__retres1~0#1 := 0; 32952#L651-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 32953#L652-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 32492#L1603-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 32493#L1603-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 32591#L659-45 assume 1 == ~t1_pc~0; 32592#L660-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 33031#L670-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 33990#L671-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 33991#L1611-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 34012#L1611-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 34013#L678-45 assume 1 == ~t2_pc~0; 33956#L679-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 33491#L689-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 33492#L690-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 33644#L1619-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 34269#L1619-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 34386#L697-45 assume 1 == ~t3_pc~0; 33749#L698-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 33750#L708-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 34338#L709-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 33908#L1627-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 33909#L1627-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 33939#L716-45 assume 1 == ~t4_pc~0; 33570#L717-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 33571#L727-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 34121#L728-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 33576#L1635-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 33577#L1635-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 33239#L735-45 assume 1 == ~t5_pc~0; 33240#L736-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 33783#L746-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 34345#L747-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 34346#L1643-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 34404#L1643-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 34399#L754-45 assume 1 == ~t6_pc~0; 33731#L755-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 33732#L765-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 33161#L766-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 33162#L1651-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 33735#L1651-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 33467#L773-45 assume !(1 == ~t7_pc~0); 33024#L773-47 is_transmit7_triggered_~__retres1~7#1 := 0; 33025#L784-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 33945#L785-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 34227#L1659-45 assume !(0 != activate_threads_~tmp___6~0#1); 33473#L1659-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 33143#L792-45 assume 1 == ~t8_pc~0; 33144#L793-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 34173#L803-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 32746#L804-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 32605#L1667-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 32606#L1667-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 33101#L811-45 assume 1 == ~t9_pc~0; 32890#L812-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 32892#L822-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 34100#L823-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 33935#L1675-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 33544#L1675-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 33336#L830-45 assume !(1 == ~t10_pc~0); 32533#L830-47 is_transmit10_triggered_~__retres1~10#1 := 0; 32534#L841-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 33656#L842-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 32766#L1683-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 32767#L1683-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 32512#L849-45 assume !(1 == ~t11_pc~0); 32513#L849-47 is_transmit11_triggered_~__retres1~11#1 := 0; 32972#L860-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 32603#L861-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 32500#L1691-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 32501#L1691-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 32759#L868-45 assume 1 == ~t12_pc~0; 32760#L869-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 32699#L879-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 32700#L880-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 34038#L1699-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 34289#L1699-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 34290#L887-45 assume !(1 == ~t13_pc~0); 32768#L887-47 is_transmit13_triggered_~__retres1~13#1 := 0; 32769#L898-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 34051#L899-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 34396#L1707-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 32731#L1707-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 32732#L1439-3 assume 1 == ~M_E~0;~M_E~0 := 2; 34039#L1439-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 32751#L1444-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 32752#L1449-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 32909#L1454-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 33840#L1459-3 assume !(1 == ~T5_E~0); 33841#L1464-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 34292#L1469-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 34231#L1474-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 34232#L1479-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 34293#L1484-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 33525#L1489-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 33526#L1494-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 34162#L1499-3 assume !(1 == ~T13_E~0); 33801#L1504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 33802#L1509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 34240#L1514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 34270#L1519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 33444#L1524-3 assume 1 == ~E_4~0;~E_4~0 := 2; 33445#L1529-3 assume 1 == ~E_5~0;~E_5~0 := 2; 34312#L1534-3 assume 1 == ~E_6~0;~E_6~0 := 2; 33712#L1539-3 assume !(1 == ~E_7~0); 33188#L1544-3 assume 1 == ~E_8~0;~E_8~0 := 2; 33189#L1549-3 assume 1 == ~E_9~0;~E_9~0 := 2; 33684#L1554-3 assume 1 == ~E_10~0;~E_10~0 := 2; 32805#L1559-3 assume 1 == ~E_11~0;~E_11~0 := 2; 32806#L1564-3 assume 1 == ~E_12~0;~E_12~0 := 2; 33940#L1569-3 assume 1 == ~E_13~0;~E_13~0 := 2; 33941#L1574-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 32682#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 32453#L1064-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 32728#L1065-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 32689#L1959 assume !(0 == start_simulation_~tmp~3#1); 32691#L1959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 32723#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 32673#L1064-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 33982#L1065-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 34103#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 34310#L1921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 34324#L1922 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 34325#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 32753#L1940-2 [2021-12-16 10:05:34,238 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:34,239 INFO L85 PathProgramCache]: Analyzing trace with hash -1393291829, now seen corresponding path program 1 times [2021-12-16 10:05:34,239 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:34,239 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [973312645] [2021-12-16 10:05:34,239 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:34,239 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:34,249 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:34,264 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:05:34,265 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:34,265 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [973312645] [2021-12-16 10:05:34,265 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [973312645] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:34,265 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:34,265 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:05:34,265 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [414206731] [2021-12-16 10:05:34,266 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:34,266 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:05:34,266 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:34,267 INFO L85 PathProgramCache]: Analyzing trace with hash 230524959, now seen corresponding path program 2 times [2021-12-16 10:05:34,267 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:34,267 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1962239325] [2021-12-16 10:05:34,267 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:34,267 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:34,280 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:34,303 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:05:34,303 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:34,303 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1962239325] [2021-12-16 10:05:34,304 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1962239325] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:34,304 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:34,304 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:05:34,304 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [918279463] [2021-12-16 10:05:34,304 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:34,305 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:05:34,305 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:05:34,305 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-16 10:05:34,305 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-16 10:05:34,306 INFO L87 Difference]: Start difference. First operand 2023 states and 2989 transitions. cyclomatic complexity: 967 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:34,353 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:05:34,353 INFO L93 Difference]: Finished difference Result 2023 states and 2988 transitions. [2021-12-16 10:05:34,354 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-16 10:05:34,354 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2023 states and 2988 transitions. [2021-12-16 10:05:34,363 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1848 [2021-12-16 10:05:34,372 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2023 states to 2023 states and 2988 transitions. [2021-12-16 10:05:34,373 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2023 [2021-12-16 10:05:34,374 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2023 [2021-12-16 10:05:34,374 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2023 states and 2988 transitions. [2021-12-16 10:05:34,377 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:05:34,377 INFO L681 BuchiCegarLoop]: Abstraction has 2023 states and 2988 transitions. [2021-12-16 10:05:34,380 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2023 states and 2988 transitions. [2021-12-16 10:05:34,403 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2023 to 2023. [2021-12-16 10:05:34,406 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2023 states, 2023 states have (on average 1.4770143351458231) internal successors, (2988), 2022 states have internal predecessors, (2988), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:34,410 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2023 states to 2023 states and 2988 transitions. [2021-12-16 10:05:34,410 INFO L704 BuchiCegarLoop]: Abstraction has 2023 states and 2988 transitions. [2021-12-16 10:05:34,411 INFO L587 BuchiCegarLoop]: Abstraction has 2023 states and 2988 transitions. [2021-12-16 10:05:34,411 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2021-12-16 10:05:34,411 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2023 states and 2988 transitions. [2021-12-16 10:05:34,416 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1848 [2021-12-16 10:05:34,416 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:05:34,416 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:05:34,418 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:34,418 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:34,419 INFO L791 eck$LassoCheckResult]: Stem: 37420#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 37421#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 38419#L1903 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 38420#L907 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 38505#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 37884#L914-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 37353#L919-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 37354#L924-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 38170#L929-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 38171#L934-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 38271#L939-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 38272#L944-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 37125#L949-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 37126#L954-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 38301#L959-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 37661#L964-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 37662#L969-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 38222#L974-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 37563#L979-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 37564#L1291 assume 0 == ~M_E~0;~M_E~0 := 1; 38506#L1291-2 assume !(0 == ~T1_E~0); 38504#L1296-1 assume !(0 == ~T2_E~0); 37720#L1301-1 assume !(0 == ~T3_E~0); 37721#L1306-1 assume !(0 == ~T4_E~0); 38230#L1311-1 assume !(0 == ~T5_E~0); 36968#L1316-1 assume !(0 == ~T6_E~0); 36969#L1321-1 assume !(0 == ~T7_E~0); 37733#L1326-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 36796#L1331-1 assume !(0 == ~T9_E~0); 36495#L1336-1 assume !(0 == ~T10_E~0); 36496#L1341-1 assume !(0 == ~T11_E~0); 36576#L1346-1 assume !(0 == ~T12_E~0); 36577#L1351-1 assume !(0 == ~T13_E~0); 36917#L1356-1 assume !(0 == ~E_M~0); 36918#L1361-1 assume !(0 == ~E_1~0); 38445#L1366-1 assume 0 == ~E_2~0;~E_2~0 := 1; 36958#L1371-1 assume !(0 == ~E_3~0); 36959#L1376-1 assume !(0 == ~E_4~0); 37780#L1381-1 assume !(0 == ~E_5~0); 37781#L1386-1 assume !(0 == ~E_6~0); 38475#L1391-1 assume !(0 == ~E_7~0); 38493#L1396-1 assume !(0 == ~E_8~0); 37693#L1401-1 assume !(0 == ~E_9~0); 37694#L1406-1 assume 0 == ~E_10~0;~E_10~0 := 1; 37972#L1411-1 assume !(0 == ~E_11~0); 37973#L1416-1 assume !(0 == ~E_12~0); 37605#L1421-1 assume !(0 == ~E_13~0); 37148#L1426-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 37149#L640 assume !(1 == ~m_pc~0); 37658#L640-2 is_master_triggered_~__retres1~0#1 := 0; 37657#L651 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 37749#L652 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 37643#L1603 assume !(0 != activate_threads_~tmp~1#1); 37644#L1603-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 37278#L659 assume 1 == ~t1_pc~0; 37279#L660 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 37384#L670 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 38330#L671 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 37404#L1611 assume !(0 != activate_threads_~tmp___0~0#1); 37405#L1611-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 37418#L678 assume 1 == ~t2_pc~0; 38372#L679 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 38373#L689 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 38472#L690 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 37516#L1619 assume !(0 != activate_threads_~tmp___1~0#1); 37517#L1619-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 37638#L697 assume !(1 == ~t3_pc~0); 37639#L697-2 is_transmit3_triggered_~__retres1~3#1 := 0; 37761#L708 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 37569#L709 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 37548#L1627 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 37549#L1627-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 38409#L716 assume 1 == ~t4_pc~0; 38395#L717 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 37259#L727 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 37260#L728 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 36759#L1635 assume !(0 != activate_threads_~tmp___3~0#1); 36760#L1635-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 38051#L735 assume !(1 == ~t5_pc~0); 36720#L735-2 is_transmit5_triggered_~__retres1~5#1 := 0; 36721#L746 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 37171#L747 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 38078#L1643 assume !(0 != activate_threads_~tmp___4~0#1); 37714#L1643-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 37715#L754 assume 1 == ~t6_pc~0; 37468#L755 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 37366#L765 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 37367#L766 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 37340#L1651 assume !(0 != activate_threads_~tmp___5~0#1); 37341#L1651-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 38161#L773 assume !(1 == ~t7_pc~0); 36921#L773-2 is_transmit7_triggered_~__retres1~7#1 := 0; 36920#L784 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 37750#L785 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 37722#L1659 assume !(0 != activate_threads_~tmp___6~0#1); 37723#L1659-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 37770#L792 assume 1 == ~t8_pc~0; 37943#L793 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 38275#L803 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 37764#L804 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 37717#L1667 assume !(0 != activate_threads_~tmp___7~0#1); 37641#L1667-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 37642#L811 assume 1 == ~t9_pc~0; 37846#L812 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 38312#L822 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 38188#L823 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 37842#L1675 assume !(0 != activate_threads_~tmp___8~0#1); 37654#L1675-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 37655#L830 assume !(1 == ~t10_pc~0); 37376#L830-2 is_transmit10_triggered_~__retres1~10#1 := 0; 36900#L841 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 36593#L842 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 36594#L1683 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 36881#L1683-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 38179#L849 assume 1 == ~t11_pc~0; 38180#L850 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 36696#L860 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 36697#L861 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 37286#L1691 assume !(0 != activate_threads_~tmp___10~0#1); 38085#L1691-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 38086#L868 assume !(1 == ~t12_pc~0); 37501#L868-2 is_transmit12_triggered_~__retres1~12#1 := 0; 37500#L879 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 37295#L880 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 37296#L1699 assume !(0 != activate_threads_~tmp___11~0#1); 36932#L1699-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 36933#L887 assume 1 == ~t13_pc~0; 38100#L888 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 37542#L898 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 37543#L899 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 37979#L1707 assume !(0 != activate_threads_~tmp___12~0#1); 36636#L1707-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 36637#L1439 assume !(1 == ~M_E~0); 37710#L1439-2 assume !(1 == ~T1_E~0); 36808#L1444-1 assume !(1 == ~T2_E~0); 36809#L1449-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 37282#L1454-1 assume !(1 == ~T4_E~0); 37283#L1459-1 assume !(1 == ~T5_E~0); 37839#L1464-1 assume !(1 == ~T6_E~0); 37840#L1469-1 assume !(1 == ~T7_E~0); 37912#L1474-1 assume !(1 == ~T8_E~0); 37606#L1479-1 assume !(1 == ~T9_E~0); 37607#L1484-1 assume !(1 == ~T10_E~0); 37843#L1489-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 37489#L1494-1 assume !(1 == ~T12_E~0); 37490#L1499-1 assume !(1 == ~T13_E~0); 37682#L1504-1 assume !(1 == ~E_M~0); 37683#L1509-1 assume !(1 == ~E_1~0); 38258#L1514-1 assume !(1 == ~E_2~0); 37945#L1519-1 assume !(1 == ~E_3~0); 37946#L1524-1 assume !(1 == ~E_4~0); 38458#L1529-1 assume 1 == ~E_5~0;~E_5~0 := 2; 38459#L1534-1 assume !(1 == ~E_6~0); 36629#L1539-1 assume !(1 == ~E_7~0); 36630#L1544-1 assume !(1 == ~E_8~0); 37044#L1549-1 assume !(1 == ~E_9~0); 38433#L1554-1 assume !(1 == ~E_10~0); 38429#L1559-1 assume !(1 == ~E_11~0); 38296#L1564-1 assume !(1 == ~E_12~0); 38297#L1569-1 assume 1 == ~E_13~0;~E_13~0 := 2; 38454#L1574-1 assume { :end_inline_reset_delta_events } true; 36806#L1940-2 [2021-12-16 10:05:34,419 INFO L793 eck$LassoCheckResult]: Loop: 36806#L1940-2 assume !false; 36807#L1941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 37089#L1266 assume !false; 38108#L1075 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 37337#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 37070#L1064 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 37461#L1065 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 37462#L1079 assume !(0 != eval_~tmp~0#1); 37423#L1281 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 37424#L907-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 38028#L1291-3 assume 0 == ~M_E~0;~M_E~0 := 1; 37913#L1291-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 37914#L1296-3 assume !(0 == ~T2_E~0); 38486#L1301-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 38440#L1306-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 37571#L1311-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 36847#L1316-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 36848#L1321-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 36948#L1326-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 37705#L1331-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 37954#L1336-3 assume !(0 == ~T10_E~0); 37955#L1341-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 37275#L1346-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 37255#L1351-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 37200#L1356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 37201#L1361-3 assume 0 == ~E_1~0;~E_1~0 := 1; 37762#L1366-3 assume 0 == ~E_2~0;~E_2~0 := 1; 36551#L1371-3 assume 0 == ~E_3~0;~E_3~0 := 1; 36552#L1376-3 assume !(0 == ~E_4~0); 38281#L1381-3 assume 0 == ~E_5~0;~E_5~0 := 1; 38141#L1386-3 assume 0 == ~E_6~0;~E_6~0 := 1; 38142#L1391-3 assume 0 == ~E_7~0;~E_7~0 := 1; 38304#L1396-3 assume 0 == ~E_8~0;~E_8~0 := 1; 38305#L1401-3 assume 0 == ~E_9~0;~E_9~0 := 1; 36914#L1406-3 assume 0 == ~E_10~0;~E_10~0 := 1; 36768#L1411-3 assume 0 == ~E_11~0;~E_11~0 := 1; 36769#L1416-3 assume !(0 == ~E_12~0); 37430#L1421-3 assume 0 == ~E_13~0;~E_13~0 := 1; 37431#L1426-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 37538#L640-45 assume !(1 == ~m_pc~0); 37539#L640-47 is_master_triggered_~__retres1~0#1 := 0; 37005#L651-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 37006#L652-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 36545#L1603-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 36546#L1603-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 36644#L659-45 assume 1 == ~t1_pc~0; 36645#L660-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 37084#L670-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 38043#L671-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 38044#L1611-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 38065#L1611-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 38066#L678-45 assume 1 == ~t2_pc~0; 38009#L679-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 37544#L689-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 37545#L690-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 37697#L1619-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 38322#L1619-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 38439#L697-45 assume 1 == ~t3_pc~0; 37802#L698-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 37803#L708-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 38391#L709-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 37961#L1627-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 37962#L1627-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 37992#L716-45 assume 1 == ~t4_pc~0; 37623#L717-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 37624#L727-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 38174#L728-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 37629#L1635-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 37630#L1635-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 37292#L735-45 assume 1 == ~t5_pc~0; 37293#L736-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 37836#L746-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 38398#L747-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 38399#L1643-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 38457#L1643-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 38452#L754-45 assume 1 == ~t6_pc~0; 37784#L755-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 37785#L765-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 37214#L766-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 37215#L1651-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 37788#L1651-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 37520#L773-45 assume 1 == ~t7_pc~0; 37521#L774-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 37078#L784-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 37998#L785-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 38280#L1659-45 assume !(0 != activate_threads_~tmp___6~0#1); 37526#L1659-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 37196#L792-45 assume 1 == ~t8_pc~0; 37197#L793-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 38226#L803-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 36799#L804-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 36658#L1667-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 36659#L1667-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 37154#L811-45 assume !(1 == ~t9_pc~0); 36944#L811-47 is_transmit9_triggered_~__retres1~9#1 := 0; 36945#L822-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 38153#L823-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 37988#L1675-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 37597#L1675-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 37389#L830-45 assume !(1 == ~t10_pc~0); 36586#L830-47 is_transmit10_triggered_~__retres1~10#1 := 0; 36587#L841-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 37709#L842-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 36819#L1683-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 36820#L1683-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 36565#L849-45 assume !(1 == ~t11_pc~0); 36566#L849-47 is_transmit11_triggered_~__retres1~11#1 := 0; 37025#L860-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 36656#L861-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 36553#L1691-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 36554#L1691-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 36812#L868-45 assume 1 == ~t12_pc~0; 36813#L869-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 36752#L879-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 36753#L880-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 38091#L1699-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 38342#L1699-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 38343#L887-45 assume !(1 == ~t13_pc~0); 36821#L887-47 is_transmit13_triggered_~__retres1~13#1 := 0; 36822#L898-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 38104#L899-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 38449#L1707-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 36784#L1707-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 36785#L1439-3 assume 1 == ~M_E~0;~M_E~0 := 2; 38092#L1439-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 36804#L1444-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 36805#L1449-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 36962#L1454-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 37893#L1459-3 assume !(1 == ~T5_E~0); 37894#L1464-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 38345#L1469-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 38284#L1474-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 38285#L1479-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 38346#L1484-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 37578#L1489-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 37579#L1494-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 38215#L1499-3 assume !(1 == ~T13_E~0); 37854#L1504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 37855#L1509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 38293#L1514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 38323#L1519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 37497#L1524-3 assume 1 == ~E_4~0;~E_4~0 := 2; 37498#L1529-3 assume 1 == ~E_5~0;~E_5~0 := 2; 38365#L1534-3 assume 1 == ~E_6~0;~E_6~0 := 2; 37765#L1539-3 assume !(1 == ~E_7~0); 37241#L1544-3 assume 1 == ~E_8~0;~E_8~0 := 2; 37242#L1549-3 assume 1 == ~E_9~0;~E_9~0 := 2; 37737#L1554-3 assume 1 == ~E_10~0;~E_10~0 := 2; 36858#L1559-3 assume 1 == ~E_11~0;~E_11~0 := 2; 36859#L1564-3 assume 1 == ~E_12~0;~E_12~0 := 2; 37993#L1569-3 assume 1 == ~E_13~0;~E_13~0 := 2; 37994#L1574-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 36735#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 36506#L1064-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 36781#L1065-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 36742#L1959 assume !(0 == start_simulation_~tmp~3#1); 36744#L1959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 36776#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 36726#L1064-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 38035#L1065-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 38156#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 38363#L1921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 38377#L1922 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 38378#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 36806#L1940-2 [2021-12-16 10:05:34,420 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:34,420 INFO L85 PathProgramCache]: Analyzing trace with hash -1779154231, now seen corresponding path program 1 times [2021-12-16 10:05:34,420 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:34,420 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [854728460] [2021-12-16 10:05:34,421 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:34,421 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:34,430 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:34,445 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:05:34,446 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:34,446 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [854728460] [2021-12-16 10:05:34,446 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [854728460] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:34,446 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:34,446 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:05:34,447 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2141229729] [2021-12-16 10:05:34,447 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:34,447 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:05:34,448 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:34,448 INFO L85 PathProgramCache]: Analyzing trace with hash -324648545, now seen corresponding path program 1 times [2021-12-16 10:05:34,448 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:34,448 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1233997572] [2021-12-16 10:05:34,448 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:34,448 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:34,461 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:34,484 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:05:34,484 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:34,484 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1233997572] [2021-12-16 10:05:34,484 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1233997572] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:34,484 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:34,485 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:05:34,485 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [136141106] [2021-12-16 10:05:34,485 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:34,485 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:05:34,486 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:05:34,486 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-16 10:05:34,486 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-16 10:05:34,486 INFO L87 Difference]: Start difference. First operand 2023 states and 2988 transitions. cyclomatic complexity: 966 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:34,524 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:05:34,524 INFO L93 Difference]: Finished difference Result 2023 states and 2987 transitions. [2021-12-16 10:05:34,524 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-16 10:05:34,525 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2023 states and 2987 transitions. [2021-12-16 10:05:34,532 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1848 [2021-12-16 10:05:34,538 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2023 states to 2023 states and 2987 transitions. [2021-12-16 10:05:34,539 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2023 [2021-12-16 10:05:34,540 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2023 [2021-12-16 10:05:34,540 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2023 states and 2987 transitions. [2021-12-16 10:05:34,542 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:05:34,542 INFO L681 BuchiCegarLoop]: Abstraction has 2023 states and 2987 transitions. [2021-12-16 10:05:34,545 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2023 states and 2987 transitions. [2021-12-16 10:05:34,566 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2023 to 2023. [2021-12-16 10:05:34,569 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2023 states, 2023 states have (on average 1.476520019772615) internal successors, (2987), 2022 states have internal predecessors, (2987), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:34,572 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2023 states to 2023 states and 2987 transitions. [2021-12-16 10:05:34,572 INFO L704 BuchiCegarLoop]: Abstraction has 2023 states and 2987 transitions. [2021-12-16 10:05:34,572 INFO L587 BuchiCegarLoop]: Abstraction has 2023 states and 2987 transitions. [2021-12-16 10:05:34,572 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2021-12-16 10:05:34,573 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2023 states and 2987 transitions. [2021-12-16 10:05:34,577 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1848 [2021-12-16 10:05:34,577 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:05:34,578 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:05:34,579 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:34,579 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:34,580 INFO L791 eck$LassoCheckResult]: Stem: 41473#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 41474#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 42472#L1903 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 42473#L907 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 42558#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 41937#L914-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 41406#L919-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 41407#L924-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 42223#L929-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 42224#L934-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 42324#L939-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 42325#L944-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 41178#L949-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 41179#L954-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 42354#L959-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 41714#L964-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 41715#L969-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 42275#L974-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 41616#L979-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 41617#L1291 assume 0 == ~M_E~0;~M_E~0 := 1; 42559#L1291-2 assume !(0 == ~T1_E~0); 42557#L1296-1 assume !(0 == ~T2_E~0); 41773#L1301-1 assume !(0 == ~T3_E~0); 41774#L1306-1 assume !(0 == ~T4_E~0); 42283#L1311-1 assume !(0 == ~T5_E~0); 41021#L1316-1 assume !(0 == ~T6_E~0); 41022#L1321-1 assume !(0 == ~T7_E~0); 41786#L1326-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 40849#L1331-1 assume !(0 == ~T9_E~0); 40548#L1336-1 assume !(0 == ~T10_E~0); 40549#L1341-1 assume !(0 == ~T11_E~0); 40629#L1346-1 assume !(0 == ~T12_E~0); 40630#L1351-1 assume !(0 == ~T13_E~0); 40970#L1356-1 assume !(0 == ~E_M~0); 40971#L1361-1 assume !(0 == ~E_1~0); 42498#L1366-1 assume 0 == ~E_2~0;~E_2~0 := 1; 41011#L1371-1 assume !(0 == ~E_3~0); 41012#L1376-1 assume !(0 == ~E_4~0); 41833#L1381-1 assume !(0 == ~E_5~0); 41834#L1386-1 assume !(0 == ~E_6~0); 42528#L1391-1 assume !(0 == ~E_7~0); 42546#L1396-1 assume !(0 == ~E_8~0); 41746#L1401-1 assume !(0 == ~E_9~0); 41747#L1406-1 assume 0 == ~E_10~0;~E_10~0 := 1; 42025#L1411-1 assume !(0 == ~E_11~0); 42026#L1416-1 assume !(0 == ~E_12~0); 41658#L1421-1 assume !(0 == ~E_13~0); 41201#L1426-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 41202#L640 assume !(1 == ~m_pc~0); 41711#L640-2 is_master_triggered_~__retres1~0#1 := 0; 41710#L651 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 41802#L652 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 41696#L1603 assume !(0 != activate_threads_~tmp~1#1); 41697#L1603-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 41331#L659 assume 1 == ~t1_pc~0; 41332#L660 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 41437#L670 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 42383#L671 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 41457#L1611 assume !(0 != activate_threads_~tmp___0~0#1); 41458#L1611-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 41471#L678 assume 1 == ~t2_pc~0; 42425#L679 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 42426#L689 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 42525#L690 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 41569#L1619 assume !(0 != activate_threads_~tmp___1~0#1); 41570#L1619-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 41691#L697 assume !(1 == ~t3_pc~0); 41692#L697-2 is_transmit3_triggered_~__retres1~3#1 := 0; 41814#L708 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 41622#L709 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 41601#L1627 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 41602#L1627-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 42462#L716 assume 1 == ~t4_pc~0; 42448#L717 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 41312#L727 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 41313#L728 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 40812#L1635 assume !(0 != activate_threads_~tmp___3~0#1); 40813#L1635-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 42104#L735 assume !(1 == ~t5_pc~0); 40773#L735-2 is_transmit5_triggered_~__retres1~5#1 := 0; 40774#L746 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 41224#L747 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 42131#L1643 assume !(0 != activate_threads_~tmp___4~0#1); 41767#L1643-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 41768#L754 assume 1 == ~t6_pc~0; 41521#L755 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 41419#L765 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 41420#L766 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 41393#L1651 assume !(0 != activate_threads_~tmp___5~0#1); 41394#L1651-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 42214#L773 assume !(1 == ~t7_pc~0); 40974#L773-2 is_transmit7_triggered_~__retres1~7#1 := 0; 40973#L784 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 41803#L785 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 41775#L1659 assume !(0 != activate_threads_~tmp___6~0#1); 41776#L1659-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 41823#L792 assume 1 == ~t8_pc~0; 41996#L793 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 42328#L803 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 41817#L804 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 41770#L1667 assume !(0 != activate_threads_~tmp___7~0#1); 41694#L1667-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 41695#L811 assume 1 == ~t9_pc~0; 41899#L812 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 42365#L822 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 42241#L823 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 41895#L1675 assume !(0 != activate_threads_~tmp___8~0#1); 41707#L1675-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 41708#L830 assume !(1 == ~t10_pc~0); 41429#L830-2 is_transmit10_triggered_~__retres1~10#1 := 0; 40953#L841 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 40646#L842 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 40647#L1683 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 40934#L1683-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 42232#L849 assume 1 == ~t11_pc~0; 42233#L850 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 40749#L860 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 40750#L861 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 41339#L1691 assume !(0 != activate_threads_~tmp___10~0#1); 42138#L1691-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 42139#L868 assume !(1 == ~t12_pc~0); 41554#L868-2 is_transmit12_triggered_~__retres1~12#1 := 0; 41553#L879 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 41348#L880 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 41349#L1699 assume !(0 != activate_threads_~tmp___11~0#1); 40985#L1699-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 40986#L887 assume 1 == ~t13_pc~0; 42153#L888 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 41595#L898 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 41596#L899 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 42032#L1707 assume !(0 != activate_threads_~tmp___12~0#1); 40689#L1707-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 40690#L1439 assume !(1 == ~M_E~0); 41763#L1439-2 assume !(1 == ~T1_E~0); 40861#L1444-1 assume !(1 == ~T2_E~0); 40862#L1449-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 41335#L1454-1 assume !(1 == ~T4_E~0); 41336#L1459-1 assume !(1 == ~T5_E~0); 41892#L1464-1 assume !(1 == ~T6_E~0); 41893#L1469-1 assume !(1 == ~T7_E~0); 41965#L1474-1 assume !(1 == ~T8_E~0); 41659#L1479-1 assume !(1 == ~T9_E~0); 41660#L1484-1 assume !(1 == ~T10_E~0); 41896#L1489-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 41542#L1494-1 assume !(1 == ~T12_E~0); 41543#L1499-1 assume !(1 == ~T13_E~0); 41735#L1504-1 assume !(1 == ~E_M~0); 41736#L1509-1 assume !(1 == ~E_1~0); 42311#L1514-1 assume !(1 == ~E_2~0); 41998#L1519-1 assume !(1 == ~E_3~0); 41999#L1524-1 assume !(1 == ~E_4~0); 42511#L1529-1 assume 1 == ~E_5~0;~E_5~0 := 2; 42512#L1534-1 assume !(1 == ~E_6~0); 40682#L1539-1 assume !(1 == ~E_7~0); 40683#L1544-1 assume !(1 == ~E_8~0); 41097#L1549-1 assume !(1 == ~E_9~0); 42486#L1554-1 assume !(1 == ~E_10~0); 42482#L1559-1 assume !(1 == ~E_11~0); 42349#L1564-1 assume !(1 == ~E_12~0); 42350#L1569-1 assume 1 == ~E_13~0;~E_13~0 := 2; 42507#L1574-1 assume { :end_inline_reset_delta_events } true; 40859#L1940-2 [2021-12-16 10:05:34,580 INFO L793 eck$LassoCheckResult]: Loop: 40859#L1940-2 assume !false; 40860#L1941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 41142#L1266 assume !false; 42161#L1075 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 41390#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 41123#L1064 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 41514#L1065 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 41515#L1079 assume !(0 != eval_~tmp~0#1); 41476#L1281 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 41477#L907-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 42081#L1291-3 assume 0 == ~M_E~0;~M_E~0 := 1; 41966#L1291-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 41967#L1296-3 assume !(0 == ~T2_E~0); 42539#L1301-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 42493#L1306-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 41624#L1311-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 40900#L1316-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 40901#L1321-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 41001#L1326-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 41758#L1331-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 42007#L1336-3 assume !(0 == ~T10_E~0); 42008#L1341-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 41328#L1346-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 41308#L1351-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 41253#L1356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 41254#L1361-3 assume 0 == ~E_1~0;~E_1~0 := 1; 41815#L1366-3 assume 0 == ~E_2~0;~E_2~0 := 1; 40604#L1371-3 assume 0 == ~E_3~0;~E_3~0 := 1; 40605#L1376-3 assume !(0 == ~E_4~0); 42334#L1381-3 assume 0 == ~E_5~0;~E_5~0 := 1; 42194#L1386-3 assume 0 == ~E_6~0;~E_6~0 := 1; 42195#L1391-3 assume 0 == ~E_7~0;~E_7~0 := 1; 42357#L1396-3 assume 0 == ~E_8~0;~E_8~0 := 1; 42358#L1401-3 assume 0 == ~E_9~0;~E_9~0 := 1; 40967#L1406-3 assume 0 == ~E_10~0;~E_10~0 := 1; 40821#L1411-3 assume 0 == ~E_11~0;~E_11~0 := 1; 40822#L1416-3 assume !(0 == ~E_12~0); 41483#L1421-3 assume 0 == ~E_13~0;~E_13~0 := 1; 41484#L1426-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 41591#L640-45 assume !(1 == ~m_pc~0); 41592#L640-47 is_master_triggered_~__retres1~0#1 := 0; 41058#L651-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 41059#L652-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 40598#L1603-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 40599#L1603-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 40697#L659-45 assume 1 == ~t1_pc~0; 40698#L660-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 41137#L670-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 42096#L671-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 42097#L1611-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 42118#L1611-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 42119#L678-45 assume 1 == ~t2_pc~0; 42062#L679-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 41597#L689-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 41598#L690-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 41750#L1619-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 42375#L1619-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 42492#L697-45 assume !(1 == ~t3_pc~0); 41857#L697-47 is_transmit3_triggered_~__retres1~3#1 := 0; 41856#L708-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 42444#L709-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 42014#L1627-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 42015#L1627-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 42045#L716-45 assume 1 == ~t4_pc~0; 41676#L717-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 41677#L727-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 42227#L728-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 41682#L1635-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 41683#L1635-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 41345#L735-45 assume 1 == ~t5_pc~0; 41346#L736-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 41889#L746-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 42451#L747-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 42452#L1643-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 42510#L1643-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 42505#L754-45 assume 1 == ~t6_pc~0; 41837#L755-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 41838#L765-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 41267#L766-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 41268#L1651-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 41841#L1651-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 41573#L773-45 assume 1 == ~t7_pc~0; 41574#L774-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 41131#L784-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 42051#L785-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 42333#L1659-45 assume !(0 != activate_threads_~tmp___6~0#1); 41579#L1659-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 41249#L792-45 assume 1 == ~t8_pc~0; 41250#L793-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 42279#L803-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 40852#L804-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 40711#L1667-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 40712#L1667-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 41207#L811-45 assume 1 == ~t9_pc~0; 40996#L812-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 40998#L822-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 42206#L823-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 42041#L1675-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 41650#L1675-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 41442#L830-45 assume 1 == ~t10_pc~0; 41443#L831-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 40640#L841-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 41762#L842-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 40872#L1683-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 40873#L1683-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 40618#L849-45 assume !(1 == ~t11_pc~0); 40619#L849-47 is_transmit11_triggered_~__retres1~11#1 := 0; 41078#L860-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 40709#L861-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 40606#L1691-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 40607#L1691-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 40865#L868-45 assume 1 == ~t12_pc~0; 40866#L869-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 40805#L879-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 40806#L880-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 42144#L1699-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 42395#L1699-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 42396#L887-45 assume 1 == ~t13_pc~0; 42226#L888-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 40875#L898-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 42157#L899-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 42502#L1707-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 40837#L1707-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 40838#L1439-3 assume 1 == ~M_E~0;~M_E~0 := 2; 42145#L1439-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 40857#L1444-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 40858#L1449-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 41015#L1454-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 41946#L1459-3 assume !(1 == ~T5_E~0); 41947#L1464-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 42398#L1469-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 42337#L1474-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 42338#L1479-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 42399#L1484-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 41631#L1489-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 41632#L1494-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 42268#L1499-3 assume !(1 == ~T13_E~0); 41907#L1504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 41908#L1509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 42346#L1514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 42376#L1519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 41550#L1524-3 assume 1 == ~E_4~0;~E_4~0 := 2; 41551#L1529-3 assume 1 == ~E_5~0;~E_5~0 := 2; 42418#L1534-3 assume 1 == ~E_6~0;~E_6~0 := 2; 41818#L1539-3 assume !(1 == ~E_7~0); 41294#L1544-3 assume 1 == ~E_8~0;~E_8~0 := 2; 41295#L1549-3 assume 1 == ~E_9~0;~E_9~0 := 2; 41790#L1554-3 assume 1 == ~E_10~0;~E_10~0 := 2; 40911#L1559-3 assume 1 == ~E_11~0;~E_11~0 := 2; 40912#L1564-3 assume 1 == ~E_12~0;~E_12~0 := 2; 42046#L1569-3 assume 1 == ~E_13~0;~E_13~0 := 2; 42047#L1574-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 40788#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 40559#L1064-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 40834#L1065-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 40795#L1959 assume !(0 == start_simulation_~tmp~3#1); 40797#L1959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 40829#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 40779#L1064-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 42088#L1065-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 42209#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 42416#L1921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 42430#L1922 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 42431#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 40859#L1940-2 [2021-12-16 10:05:34,580 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:34,581 INFO L85 PathProgramCache]: Analyzing trace with hash 584687431, now seen corresponding path program 1 times [2021-12-16 10:05:34,581 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:34,581 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1540715293] [2021-12-16 10:05:34,581 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:34,581 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:34,590 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:34,610 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:05:34,610 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:34,610 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1540715293] [2021-12-16 10:05:34,611 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1540715293] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:34,611 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:34,611 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:05:34,611 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [196596127] [2021-12-16 10:05:34,611 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:34,611 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:05:34,612 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:34,612 INFO L85 PathProgramCache]: Analyzing trace with hash 222566493, now seen corresponding path program 1 times [2021-12-16 10:05:34,612 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:34,612 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [917556642] [2021-12-16 10:05:34,612 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:34,612 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:34,624 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:34,667 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:05:34,667 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:34,667 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [917556642] [2021-12-16 10:05:34,667 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [917556642] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:34,667 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:34,667 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:05:34,668 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1486852370] [2021-12-16 10:05:34,668 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:34,668 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:05:34,668 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:05:34,669 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-16 10:05:34,669 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-16 10:05:34,669 INFO L87 Difference]: Start difference. First operand 2023 states and 2987 transitions. cyclomatic complexity: 965 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:34,699 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:05:34,700 INFO L93 Difference]: Finished difference Result 2023 states and 2986 transitions. [2021-12-16 10:05:34,700 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-16 10:05:34,701 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2023 states and 2986 transitions. [2021-12-16 10:05:34,708 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1848 [2021-12-16 10:05:34,714 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2023 states to 2023 states and 2986 transitions. [2021-12-16 10:05:34,714 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2023 [2021-12-16 10:05:34,715 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2023 [2021-12-16 10:05:34,716 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2023 states and 2986 transitions. [2021-12-16 10:05:34,718 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:05:34,718 INFO L681 BuchiCegarLoop]: Abstraction has 2023 states and 2986 transitions. [2021-12-16 10:05:34,721 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2023 states and 2986 transitions. [2021-12-16 10:05:34,743 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2023 to 2023. [2021-12-16 10:05:34,746 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2023 states, 2023 states have (on average 1.4760257043994067) internal successors, (2986), 2022 states have internal predecessors, (2986), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:34,750 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2023 states to 2023 states and 2986 transitions. [2021-12-16 10:05:34,750 INFO L704 BuchiCegarLoop]: Abstraction has 2023 states and 2986 transitions. [2021-12-16 10:05:34,750 INFO L587 BuchiCegarLoop]: Abstraction has 2023 states and 2986 transitions. [2021-12-16 10:05:34,750 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2021-12-16 10:05:34,750 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2023 states and 2986 transitions. [2021-12-16 10:05:34,755 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1848 [2021-12-16 10:05:34,755 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:05:34,755 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:05:34,757 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:34,758 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:34,758 INFO L791 eck$LassoCheckResult]: Stem: 45526#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 45527#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 46525#L1903 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 46526#L907 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 46611#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 45990#L914-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 45459#L919-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 45460#L924-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 46276#L929-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 46277#L934-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 46377#L939-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 46378#L944-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 45231#L949-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 45232#L954-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 46407#L959-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 45767#L964-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 45768#L969-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 46328#L974-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 45669#L979-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 45670#L1291 assume 0 == ~M_E~0;~M_E~0 := 1; 46612#L1291-2 assume !(0 == ~T1_E~0); 46610#L1296-1 assume !(0 == ~T2_E~0); 45826#L1301-1 assume !(0 == ~T3_E~0); 45827#L1306-1 assume !(0 == ~T4_E~0); 46336#L1311-1 assume !(0 == ~T5_E~0); 45074#L1316-1 assume !(0 == ~T6_E~0); 45075#L1321-1 assume !(0 == ~T7_E~0); 45839#L1326-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 44902#L1331-1 assume !(0 == ~T9_E~0); 44601#L1336-1 assume !(0 == ~T10_E~0); 44602#L1341-1 assume !(0 == ~T11_E~0); 44682#L1346-1 assume !(0 == ~T12_E~0); 44683#L1351-1 assume !(0 == ~T13_E~0); 45023#L1356-1 assume !(0 == ~E_M~0); 45024#L1361-1 assume !(0 == ~E_1~0); 46551#L1366-1 assume 0 == ~E_2~0;~E_2~0 := 1; 45064#L1371-1 assume !(0 == ~E_3~0); 45065#L1376-1 assume !(0 == ~E_4~0); 45886#L1381-1 assume !(0 == ~E_5~0); 45887#L1386-1 assume !(0 == ~E_6~0); 46581#L1391-1 assume !(0 == ~E_7~0); 46599#L1396-1 assume !(0 == ~E_8~0); 45799#L1401-1 assume !(0 == ~E_9~0); 45800#L1406-1 assume 0 == ~E_10~0;~E_10~0 := 1; 46078#L1411-1 assume !(0 == ~E_11~0); 46079#L1416-1 assume !(0 == ~E_12~0); 45711#L1421-1 assume !(0 == ~E_13~0); 45254#L1426-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 45255#L640 assume !(1 == ~m_pc~0); 45764#L640-2 is_master_triggered_~__retres1~0#1 := 0; 45763#L651 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 45855#L652 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 45749#L1603 assume !(0 != activate_threads_~tmp~1#1); 45750#L1603-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 45384#L659 assume 1 == ~t1_pc~0; 45385#L660 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 45490#L670 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 46436#L671 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 45510#L1611 assume !(0 != activate_threads_~tmp___0~0#1); 45511#L1611-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 45524#L678 assume 1 == ~t2_pc~0; 46478#L679 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 46479#L689 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 46578#L690 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 45622#L1619 assume !(0 != activate_threads_~tmp___1~0#1); 45623#L1619-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 45744#L697 assume !(1 == ~t3_pc~0); 45745#L697-2 is_transmit3_triggered_~__retres1~3#1 := 0; 45867#L708 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 45675#L709 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 45654#L1627 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 45655#L1627-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 46515#L716 assume 1 == ~t4_pc~0; 46501#L717 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 45365#L727 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 45366#L728 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 44865#L1635 assume !(0 != activate_threads_~tmp___3~0#1); 44866#L1635-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 46157#L735 assume !(1 == ~t5_pc~0); 44826#L735-2 is_transmit5_triggered_~__retres1~5#1 := 0; 44827#L746 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 45277#L747 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 46184#L1643 assume !(0 != activate_threads_~tmp___4~0#1); 45820#L1643-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 45821#L754 assume 1 == ~t6_pc~0; 45574#L755 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 45472#L765 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 45473#L766 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 45446#L1651 assume !(0 != activate_threads_~tmp___5~0#1); 45447#L1651-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 46267#L773 assume !(1 == ~t7_pc~0); 45027#L773-2 is_transmit7_triggered_~__retres1~7#1 := 0; 45026#L784 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 45856#L785 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 45828#L1659 assume !(0 != activate_threads_~tmp___6~0#1); 45829#L1659-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 45876#L792 assume 1 == ~t8_pc~0; 46049#L793 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 46381#L803 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 45870#L804 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 45823#L1667 assume !(0 != activate_threads_~tmp___7~0#1); 45747#L1667-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 45748#L811 assume 1 == ~t9_pc~0; 45952#L812 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 46418#L822 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 46294#L823 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 45948#L1675 assume !(0 != activate_threads_~tmp___8~0#1); 45760#L1675-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 45761#L830 assume !(1 == ~t10_pc~0); 45482#L830-2 is_transmit10_triggered_~__retres1~10#1 := 0; 45006#L841 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 44699#L842 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 44700#L1683 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 44987#L1683-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 46285#L849 assume 1 == ~t11_pc~0; 46286#L850 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 44802#L860 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 44803#L861 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 45392#L1691 assume !(0 != activate_threads_~tmp___10~0#1); 46191#L1691-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 46192#L868 assume !(1 == ~t12_pc~0); 45607#L868-2 is_transmit12_triggered_~__retres1~12#1 := 0; 45606#L879 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 45401#L880 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 45402#L1699 assume !(0 != activate_threads_~tmp___11~0#1); 45038#L1699-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 45039#L887 assume 1 == ~t13_pc~0; 46206#L888 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 45648#L898 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 45649#L899 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 46085#L1707 assume !(0 != activate_threads_~tmp___12~0#1); 44742#L1707-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 44743#L1439 assume !(1 == ~M_E~0); 45816#L1439-2 assume !(1 == ~T1_E~0); 44914#L1444-1 assume !(1 == ~T2_E~0); 44915#L1449-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 45388#L1454-1 assume !(1 == ~T4_E~0); 45389#L1459-1 assume !(1 == ~T5_E~0); 45945#L1464-1 assume !(1 == ~T6_E~0); 45946#L1469-1 assume !(1 == ~T7_E~0); 46018#L1474-1 assume !(1 == ~T8_E~0); 45712#L1479-1 assume !(1 == ~T9_E~0); 45713#L1484-1 assume !(1 == ~T10_E~0); 45949#L1489-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 45595#L1494-1 assume !(1 == ~T12_E~0); 45596#L1499-1 assume !(1 == ~T13_E~0); 45788#L1504-1 assume !(1 == ~E_M~0); 45789#L1509-1 assume !(1 == ~E_1~0); 46364#L1514-1 assume !(1 == ~E_2~0); 46051#L1519-1 assume !(1 == ~E_3~0); 46052#L1524-1 assume !(1 == ~E_4~0); 46564#L1529-1 assume 1 == ~E_5~0;~E_5~0 := 2; 46565#L1534-1 assume !(1 == ~E_6~0); 44735#L1539-1 assume !(1 == ~E_7~0); 44736#L1544-1 assume !(1 == ~E_8~0); 45150#L1549-1 assume !(1 == ~E_9~0); 46539#L1554-1 assume !(1 == ~E_10~0); 46535#L1559-1 assume !(1 == ~E_11~0); 46402#L1564-1 assume !(1 == ~E_12~0); 46403#L1569-1 assume 1 == ~E_13~0;~E_13~0 := 2; 46560#L1574-1 assume { :end_inline_reset_delta_events } true; 44912#L1940-2 [2021-12-16 10:05:34,758 INFO L793 eck$LassoCheckResult]: Loop: 44912#L1940-2 assume !false; 44913#L1941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 45195#L1266 assume !false; 46214#L1075 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 45443#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 45176#L1064 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 45567#L1065 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 45568#L1079 assume !(0 != eval_~tmp~0#1); 45529#L1281 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 45530#L907-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 46134#L1291-3 assume 0 == ~M_E~0;~M_E~0 := 1; 46019#L1291-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 46020#L1296-3 assume !(0 == ~T2_E~0); 46592#L1301-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 46546#L1306-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 45677#L1311-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 44953#L1316-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 44954#L1321-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 45054#L1326-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 45811#L1331-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 46060#L1336-3 assume !(0 == ~T10_E~0); 46061#L1341-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 45381#L1346-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 45361#L1351-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 45306#L1356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 45307#L1361-3 assume 0 == ~E_1~0;~E_1~0 := 1; 45868#L1366-3 assume 0 == ~E_2~0;~E_2~0 := 1; 44657#L1371-3 assume 0 == ~E_3~0;~E_3~0 := 1; 44658#L1376-3 assume !(0 == ~E_4~0); 46387#L1381-3 assume 0 == ~E_5~0;~E_5~0 := 1; 46247#L1386-3 assume 0 == ~E_6~0;~E_6~0 := 1; 46248#L1391-3 assume 0 == ~E_7~0;~E_7~0 := 1; 46410#L1396-3 assume 0 == ~E_8~0;~E_8~0 := 1; 46411#L1401-3 assume 0 == ~E_9~0;~E_9~0 := 1; 45020#L1406-3 assume 0 == ~E_10~0;~E_10~0 := 1; 44874#L1411-3 assume 0 == ~E_11~0;~E_11~0 := 1; 44875#L1416-3 assume !(0 == ~E_12~0); 45536#L1421-3 assume 0 == ~E_13~0;~E_13~0 := 1; 45537#L1426-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 45644#L640-45 assume !(1 == ~m_pc~0); 45645#L640-47 is_master_triggered_~__retres1~0#1 := 0; 45111#L651-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 45112#L652-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 44651#L1603-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 44652#L1603-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 44750#L659-45 assume !(1 == ~t1_pc~0); 44752#L659-47 is_transmit1_triggered_~__retres1~1#1 := 0; 45190#L670-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 46149#L671-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 46150#L1611-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 46171#L1611-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 46172#L678-45 assume 1 == ~t2_pc~0; 46115#L679-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 45650#L689-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 45651#L690-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 45803#L1619-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 46428#L1619-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 46545#L697-45 assume 1 == ~t3_pc~0; 45908#L698-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 45909#L708-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 46497#L709-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 46067#L1627-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 46068#L1627-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 46098#L716-45 assume 1 == ~t4_pc~0; 45729#L717-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 45730#L727-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 46280#L728-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 45735#L1635-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 45736#L1635-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 45398#L735-45 assume 1 == ~t5_pc~0; 45399#L736-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 45942#L746-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 46504#L747-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 46505#L1643-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 46563#L1643-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 46558#L754-45 assume 1 == ~t6_pc~0; 45890#L755-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 45891#L765-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 45320#L766-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 45321#L1651-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 45894#L1651-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 45626#L773-45 assume 1 == ~t7_pc~0; 45627#L774-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 45184#L784-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 46104#L785-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 46386#L1659-45 assume !(0 != activate_threads_~tmp___6~0#1); 45632#L1659-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 45302#L792-45 assume 1 == ~t8_pc~0; 45303#L793-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 46332#L803-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 44905#L804-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 44764#L1667-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 44765#L1667-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 45260#L811-45 assume 1 == ~t9_pc~0; 45049#L812-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 45051#L822-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 46259#L823-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 46094#L1675-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 45703#L1675-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 45495#L830-45 assume !(1 == ~t10_pc~0); 44692#L830-47 is_transmit10_triggered_~__retres1~10#1 := 0; 44693#L841-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 45815#L842-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 44925#L1683-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 44926#L1683-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 44671#L849-45 assume !(1 == ~t11_pc~0); 44672#L849-47 is_transmit11_triggered_~__retres1~11#1 := 0; 45131#L860-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 44762#L861-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 44659#L1691-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 44660#L1691-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 44918#L868-45 assume 1 == ~t12_pc~0; 44919#L869-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 44858#L879-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 44859#L880-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 46197#L1699-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 46448#L1699-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 46449#L887-45 assume 1 == ~t13_pc~0; 46279#L888-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 44928#L898-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 46210#L899-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 46555#L1707-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 44890#L1707-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 44891#L1439-3 assume 1 == ~M_E~0;~M_E~0 := 2; 46198#L1439-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 44910#L1444-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 44911#L1449-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 45068#L1454-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 45999#L1459-3 assume !(1 == ~T5_E~0); 46000#L1464-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 46451#L1469-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 46390#L1474-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 46391#L1479-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 46452#L1484-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 45684#L1489-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 45685#L1494-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 46321#L1499-3 assume !(1 == ~T13_E~0); 45960#L1504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 45961#L1509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 46399#L1514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 46429#L1519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 45603#L1524-3 assume 1 == ~E_4~0;~E_4~0 := 2; 45604#L1529-3 assume 1 == ~E_5~0;~E_5~0 := 2; 46471#L1534-3 assume 1 == ~E_6~0;~E_6~0 := 2; 45871#L1539-3 assume !(1 == ~E_7~0); 45347#L1544-3 assume 1 == ~E_8~0;~E_8~0 := 2; 45348#L1549-3 assume 1 == ~E_9~0;~E_9~0 := 2; 45843#L1554-3 assume 1 == ~E_10~0;~E_10~0 := 2; 44964#L1559-3 assume 1 == ~E_11~0;~E_11~0 := 2; 44965#L1564-3 assume 1 == ~E_12~0;~E_12~0 := 2; 46099#L1569-3 assume 1 == ~E_13~0;~E_13~0 := 2; 46100#L1574-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 44841#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 44612#L1064-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 44887#L1065-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 44848#L1959 assume !(0 == start_simulation_~tmp~3#1); 44850#L1959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 44882#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 44832#L1064-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 46141#L1065-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 46262#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 46469#L1921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 46483#L1922 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 46484#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 44912#L1940-2 [2021-12-16 10:05:34,759 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:34,759 INFO L85 PathProgramCache]: Analyzing trace with hash 1907866377, now seen corresponding path program 1 times [2021-12-16 10:05:34,759 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:34,759 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [692625838] [2021-12-16 10:05:34,759 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:34,760 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:34,772 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:34,791 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:05:34,791 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:34,791 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [692625838] [2021-12-16 10:05:34,791 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [692625838] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:34,792 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:34,792 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:05:34,792 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [98042656] [2021-12-16 10:05:34,792 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:34,792 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:05:34,793 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:34,793 INFO L85 PathProgramCache]: Analyzing trace with hash 2099019294, now seen corresponding path program 1 times [2021-12-16 10:05:34,793 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:34,793 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [353039631] [2021-12-16 10:05:34,793 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:34,793 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:34,805 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:34,830 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:05:34,830 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:34,830 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [353039631] [2021-12-16 10:05:34,830 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [353039631] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:34,830 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:34,831 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:05:34,831 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1517333316] [2021-12-16 10:05:34,831 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:34,831 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:05:34,831 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:05:34,832 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-16 10:05:34,832 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-16 10:05:34,832 INFO L87 Difference]: Start difference. First operand 2023 states and 2986 transitions. cyclomatic complexity: 964 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:34,862 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:05:34,862 INFO L93 Difference]: Finished difference Result 2023 states and 2985 transitions. [2021-12-16 10:05:34,862 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-16 10:05:34,863 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2023 states and 2985 transitions. [2021-12-16 10:05:34,870 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1848 [2021-12-16 10:05:34,876 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2023 states to 2023 states and 2985 transitions. [2021-12-16 10:05:34,876 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2023 [2021-12-16 10:05:34,877 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2023 [2021-12-16 10:05:34,878 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2023 states and 2985 transitions. [2021-12-16 10:05:34,880 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:05:34,881 INFO L681 BuchiCegarLoop]: Abstraction has 2023 states and 2985 transitions. [2021-12-16 10:05:34,883 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2023 states and 2985 transitions. [2021-12-16 10:05:34,906 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2023 to 2023. [2021-12-16 10:05:34,908 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2023 states, 2023 states have (on average 1.4755313890261987) internal successors, (2985), 2022 states have internal predecessors, (2985), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:34,912 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2023 states to 2023 states and 2985 transitions. [2021-12-16 10:05:34,912 INFO L704 BuchiCegarLoop]: Abstraction has 2023 states and 2985 transitions. [2021-12-16 10:05:34,912 INFO L587 BuchiCegarLoop]: Abstraction has 2023 states and 2985 transitions. [2021-12-16 10:05:34,912 INFO L425 BuchiCegarLoop]: ======== Iteration 13============ [2021-12-16 10:05:34,912 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2023 states and 2985 transitions. [2021-12-16 10:05:34,917 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1848 [2021-12-16 10:05:34,917 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:05:34,917 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:05:34,919 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:34,919 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:34,920 INFO L791 eck$LassoCheckResult]: Stem: 49579#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 49580#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 50578#L1903 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 50579#L907 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 50664#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 50043#L914-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 49512#L919-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 49513#L924-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 50329#L929-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 50330#L934-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 50430#L939-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 50431#L944-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 49284#L949-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 49285#L954-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 50460#L959-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 49820#L964-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 49821#L969-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 50381#L974-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 49722#L979-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 49723#L1291 assume 0 == ~M_E~0;~M_E~0 := 1; 50665#L1291-2 assume !(0 == ~T1_E~0); 50663#L1296-1 assume !(0 == ~T2_E~0); 49879#L1301-1 assume !(0 == ~T3_E~0); 49880#L1306-1 assume !(0 == ~T4_E~0); 50389#L1311-1 assume !(0 == ~T5_E~0); 49127#L1316-1 assume !(0 == ~T6_E~0); 49128#L1321-1 assume !(0 == ~T7_E~0); 49892#L1326-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 48955#L1331-1 assume !(0 == ~T9_E~0); 48654#L1336-1 assume !(0 == ~T10_E~0); 48655#L1341-1 assume !(0 == ~T11_E~0); 48735#L1346-1 assume !(0 == ~T12_E~0); 48736#L1351-1 assume !(0 == ~T13_E~0); 49076#L1356-1 assume !(0 == ~E_M~0); 49077#L1361-1 assume !(0 == ~E_1~0); 50604#L1366-1 assume 0 == ~E_2~0;~E_2~0 := 1; 49117#L1371-1 assume !(0 == ~E_3~0); 49118#L1376-1 assume !(0 == ~E_4~0); 49939#L1381-1 assume !(0 == ~E_5~0); 49940#L1386-1 assume !(0 == ~E_6~0); 50634#L1391-1 assume !(0 == ~E_7~0); 50652#L1396-1 assume !(0 == ~E_8~0); 49852#L1401-1 assume !(0 == ~E_9~0); 49853#L1406-1 assume 0 == ~E_10~0;~E_10~0 := 1; 50131#L1411-1 assume !(0 == ~E_11~0); 50132#L1416-1 assume !(0 == ~E_12~0); 49764#L1421-1 assume !(0 == ~E_13~0); 49307#L1426-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 49308#L640 assume !(1 == ~m_pc~0); 49817#L640-2 is_master_triggered_~__retres1~0#1 := 0; 49816#L651 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 49908#L652 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 49802#L1603 assume !(0 != activate_threads_~tmp~1#1); 49803#L1603-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 49437#L659 assume 1 == ~t1_pc~0; 49438#L660 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 49543#L670 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 50489#L671 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 49563#L1611 assume !(0 != activate_threads_~tmp___0~0#1); 49564#L1611-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 49577#L678 assume 1 == ~t2_pc~0; 50531#L679 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 50532#L689 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 50631#L690 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 49675#L1619 assume !(0 != activate_threads_~tmp___1~0#1); 49676#L1619-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 49797#L697 assume !(1 == ~t3_pc~0); 49798#L697-2 is_transmit3_triggered_~__retres1~3#1 := 0; 49920#L708 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 49728#L709 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 49707#L1627 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 49708#L1627-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 50568#L716 assume 1 == ~t4_pc~0; 50554#L717 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 49418#L727 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 49419#L728 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 48918#L1635 assume !(0 != activate_threads_~tmp___3~0#1); 48919#L1635-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 50210#L735 assume !(1 == ~t5_pc~0); 48879#L735-2 is_transmit5_triggered_~__retres1~5#1 := 0; 48880#L746 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 49330#L747 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 50237#L1643 assume !(0 != activate_threads_~tmp___4~0#1); 49873#L1643-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 49874#L754 assume 1 == ~t6_pc~0; 49627#L755 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 49525#L765 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 49526#L766 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 49499#L1651 assume !(0 != activate_threads_~tmp___5~0#1); 49500#L1651-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 50320#L773 assume !(1 == ~t7_pc~0); 49080#L773-2 is_transmit7_triggered_~__retres1~7#1 := 0; 49079#L784 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 49909#L785 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 49881#L1659 assume !(0 != activate_threads_~tmp___6~0#1); 49882#L1659-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 49929#L792 assume 1 == ~t8_pc~0; 50102#L793 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 50434#L803 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 49923#L804 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 49876#L1667 assume !(0 != activate_threads_~tmp___7~0#1); 49800#L1667-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 49801#L811 assume 1 == ~t9_pc~0; 50005#L812 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 50471#L822 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 50347#L823 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 50001#L1675 assume !(0 != activate_threads_~tmp___8~0#1); 49813#L1675-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 49814#L830 assume !(1 == ~t10_pc~0); 49535#L830-2 is_transmit10_triggered_~__retres1~10#1 := 0; 49059#L841 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 48752#L842 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 48753#L1683 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 49040#L1683-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 50338#L849 assume 1 == ~t11_pc~0; 50339#L850 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 48855#L860 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 48856#L861 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 49445#L1691 assume !(0 != activate_threads_~tmp___10~0#1); 50244#L1691-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 50245#L868 assume !(1 == ~t12_pc~0); 49660#L868-2 is_transmit12_triggered_~__retres1~12#1 := 0; 49659#L879 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 49454#L880 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 49455#L1699 assume !(0 != activate_threads_~tmp___11~0#1); 49091#L1699-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 49092#L887 assume 1 == ~t13_pc~0; 50259#L888 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 49701#L898 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 49702#L899 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 50138#L1707 assume !(0 != activate_threads_~tmp___12~0#1); 48795#L1707-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 48796#L1439 assume !(1 == ~M_E~0); 49869#L1439-2 assume !(1 == ~T1_E~0); 48967#L1444-1 assume !(1 == ~T2_E~0); 48968#L1449-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 49441#L1454-1 assume !(1 == ~T4_E~0); 49442#L1459-1 assume !(1 == ~T5_E~0); 49998#L1464-1 assume !(1 == ~T6_E~0); 49999#L1469-1 assume !(1 == ~T7_E~0); 50071#L1474-1 assume !(1 == ~T8_E~0); 49765#L1479-1 assume !(1 == ~T9_E~0); 49766#L1484-1 assume !(1 == ~T10_E~0); 50002#L1489-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 49648#L1494-1 assume !(1 == ~T12_E~0); 49649#L1499-1 assume !(1 == ~T13_E~0); 49841#L1504-1 assume !(1 == ~E_M~0); 49842#L1509-1 assume !(1 == ~E_1~0); 50417#L1514-1 assume !(1 == ~E_2~0); 50104#L1519-1 assume !(1 == ~E_3~0); 50105#L1524-1 assume !(1 == ~E_4~0); 50617#L1529-1 assume 1 == ~E_5~0;~E_5~0 := 2; 50618#L1534-1 assume !(1 == ~E_6~0); 48788#L1539-1 assume !(1 == ~E_7~0); 48789#L1544-1 assume !(1 == ~E_8~0); 49203#L1549-1 assume !(1 == ~E_9~0); 50592#L1554-1 assume !(1 == ~E_10~0); 50588#L1559-1 assume !(1 == ~E_11~0); 50455#L1564-1 assume !(1 == ~E_12~0); 50456#L1569-1 assume 1 == ~E_13~0;~E_13~0 := 2; 50613#L1574-1 assume { :end_inline_reset_delta_events } true; 48965#L1940-2 [2021-12-16 10:05:34,920 INFO L793 eck$LassoCheckResult]: Loop: 48965#L1940-2 assume !false; 48966#L1941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 49248#L1266 assume !false; 50267#L1075 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 49496#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 49229#L1064 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 49620#L1065 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 49621#L1079 assume !(0 != eval_~tmp~0#1); 49582#L1281 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 49583#L907-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 50187#L1291-3 assume 0 == ~M_E~0;~M_E~0 := 1; 50072#L1291-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 50073#L1296-3 assume !(0 == ~T2_E~0); 50645#L1301-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 50599#L1306-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 49730#L1311-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 49006#L1316-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 49007#L1321-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 49107#L1326-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 49864#L1331-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 50113#L1336-3 assume !(0 == ~T10_E~0); 50114#L1341-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 49434#L1346-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 49414#L1351-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 49359#L1356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 49360#L1361-3 assume 0 == ~E_1~0;~E_1~0 := 1; 49921#L1366-3 assume 0 == ~E_2~0;~E_2~0 := 1; 48710#L1371-3 assume 0 == ~E_3~0;~E_3~0 := 1; 48711#L1376-3 assume !(0 == ~E_4~0); 50440#L1381-3 assume 0 == ~E_5~0;~E_5~0 := 1; 50300#L1386-3 assume 0 == ~E_6~0;~E_6~0 := 1; 50301#L1391-3 assume 0 == ~E_7~0;~E_7~0 := 1; 50463#L1396-3 assume 0 == ~E_8~0;~E_8~0 := 1; 50464#L1401-3 assume 0 == ~E_9~0;~E_9~0 := 1; 49073#L1406-3 assume 0 == ~E_10~0;~E_10~0 := 1; 48927#L1411-3 assume 0 == ~E_11~0;~E_11~0 := 1; 48928#L1416-3 assume !(0 == ~E_12~0); 49589#L1421-3 assume 0 == ~E_13~0;~E_13~0 := 1; 49590#L1426-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 49697#L640-45 assume !(1 == ~m_pc~0); 49698#L640-47 is_master_triggered_~__retres1~0#1 := 0; 49164#L651-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 49165#L652-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 48704#L1603-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 48705#L1603-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 48803#L659-45 assume 1 == ~t1_pc~0; 48804#L660-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 49243#L670-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 50202#L671-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 50203#L1611-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 50224#L1611-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 50225#L678-45 assume 1 == ~t2_pc~0; 50168#L679-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 49703#L689-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 49704#L690-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 49856#L1619-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 50481#L1619-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 50598#L697-45 assume 1 == ~t3_pc~0; 49961#L698-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 49962#L708-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 50550#L709-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 50120#L1627-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 50121#L1627-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 50151#L716-45 assume 1 == ~t4_pc~0; 49782#L717-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 49783#L727-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 50333#L728-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 49788#L1635-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 49789#L1635-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 49451#L735-45 assume 1 == ~t5_pc~0; 49452#L736-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 49995#L746-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 50557#L747-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 50558#L1643-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 50616#L1643-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 50611#L754-45 assume 1 == ~t6_pc~0; 49943#L755-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 49944#L765-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 49373#L766-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 49374#L1651-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 49947#L1651-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 49679#L773-45 assume 1 == ~t7_pc~0; 49680#L774-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 49237#L784-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 50157#L785-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 50439#L1659-45 assume !(0 != activate_threads_~tmp___6~0#1); 49685#L1659-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 49355#L792-45 assume 1 == ~t8_pc~0; 49356#L793-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 50385#L803-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 48958#L804-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 48817#L1667-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 48818#L1667-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 49313#L811-45 assume 1 == ~t9_pc~0; 49102#L812-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 49104#L822-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 50312#L823-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 50147#L1675-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 49756#L1675-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 49548#L830-45 assume !(1 == ~t10_pc~0); 48745#L830-47 is_transmit10_triggered_~__retres1~10#1 := 0; 48746#L841-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 49868#L842-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 48978#L1683-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 48979#L1683-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 48724#L849-45 assume !(1 == ~t11_pc~0); 48725#L849-47 is_transmit11_triggered_~__retres1~11#1 := 0; 49184#L860-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 48815#L861-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 48712#L1691-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 48713#L1691-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 48971#L868-45 assume 1 == ~t12_pc~0; 48972#L869-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 48911#L879-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 48912#L880-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 50250#L1699-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 50501#L1699-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 50502#L887-45 assume !(1 == ~t13_pc~0); 48980#L887-47 is_transmit13_triggered_~__retres1~13#1 := 0; 48981#L898-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 50263#L899-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 50608#L1707-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 48943#L1707-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 48944#L1439-3 assume 1 == ~M_E~0;~M_E~0 := 2; 50251#L1439-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 48963#L1444-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 48964#L1449-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 49121#L1454-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 50052#L1459-3 assume !(1 == ~T5_E~0); 50053#L1464-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 50504#L1469-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 50443#L1474-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 50444#L1479-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 50505#L1484-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 49737#L1489-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 49738#L1494-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 50374#L1499-3 assume !(1 == ~T13_E~0); 50013#L1504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 50014#L1509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 50452#L1514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 50482#L1519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 49656#L1524-3 assume 1 == ~E_4~0;~E_4~0 := 2; 49657#L1529-3 assume 1 == ~E_5~0;~E_5~0 := 2; 50524#L1534-3 assume 1 == ~E_6~0;~E_6~0 := 2; 49924#L1539-3 assume !(1 == ~E_7~0); 49400#L1544-3 assume 1 == ~E_8~0;~E_8~0 := 2; 49401#L1549-3 assume 1 == ~E_9~0;~E_9~0 := 2; 49896#L1554-3 assume 1 == ~E_10~0;~E_10~0 := 2; 49017#L1559-3 assume 1 == ~E_11~0;~E_11~0 := 2; 49018#L1564-3 assume 1 == ~E_12~0;~E_12~0 := 2; 50152#L1569-3 assume 1 == ~E_13~0;~E_13~0 := 2; 50153#L1574-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 48894#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 48665#L1064-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 48940#L1065-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 48901#L1959 assume !(0 == start_simulation_~tmp~3#1); 48903#L1959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 48935#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 48885#L1064-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 50194#L1065-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 50315#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 50522#L1921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 50536#L1922 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 50537#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 48965#L1940-2 [2021-12-16 10:05:34,921 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:34,921 INFO L85 PathProgramCache]: Analyzing trace with hash 10886919, now seen corresponding path program 1 times [2021-12-16 10:05:34,921 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:34,921 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [795548995] [2021-12-16 10:05:34,921 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:34,921 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:34,931 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:34,947 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:05:34,947 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:34,947 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [795548995] [2021-12-16 10:05:34,947 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [795548995] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:34,947 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:34,948 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:05:34,948 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1780832321] [2021-12-16 10:05:34,948 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:34,948 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:05:34,948 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:34,949 INFO L85 PathProgramCache]: Analyzing trace with hash 1630672670, now seen corresponding path program 2 times [2021-12-16 10:05:34,949 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:34,949 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [143163623] [2021-12-16 10:05:34,949 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:34,949 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:34,961 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:34,983 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:05:34,983 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:34,983 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [143163623] [2021-12-16 10:05:34,983 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [143163623] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:34,983 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:34,983 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:05:34,983 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [338674650] [2021-12-16 10:05:34,983 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:34,984 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:05:34,984 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:05:34,984 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-16 10:05:34,984 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-16 10:05:34,985 INFO L87 Difference]: Start difference. First operand 2023 states and 2985 transitions. cyclomatic complexity: 963 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:35,012 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:05:35,013 INFO L93 Difference]: Finished difference Result 2023 states and 2984 transitions. [2021-12-16 10:05:35,013 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-16 10:05:35,014 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2023 states and 2984 transitions. [2021-12-16 10:05:35,021 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1848 [2021-12-16 10:05:35,026 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2023 states to 2023 states and 2984 transitions. [2021-12-16 10:05:35,026 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2023 [2021-12-16 10:05:35,028 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2023 [2021-12-16 10:05:35,028 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2023 states and 2984 transitions. [2021-12-16 10:05:35,030 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:05:35,030 INFO L681 BuchiCegarLoop]: Abstraction has 2023 states and 2984 transitions. [2021-12-16 10:05:35,032 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2023 states and 2984 transitions. [2021-12-16 10:05:35,050 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2023 to 2023. [2021-12-16 10:05:35,052 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2023 states, 2023 states have (on average 1.4750370736529905) internal successors, (2984), 2022 states have internal predecessors, (2984), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:35,056 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2023 states to 2023 states and 2984 transitions. [2021-12-16 10:05:35,056 INFO L704 BuchiCegarLoop]: Abstraction has 2023 states and 2984 transitions. [2021-12-16 10:05:35,056 INFO L587 BuchiCegarLoop]: Abstraction has 2023 states and 2984 transitions. [2021-12-16 10:05:35,056 INFO L425 BuchiCegarLoop]: ======== Iteration 14============ [2021-12-16 10:05:35,056 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2023 states and 2984 transitions. [2021-12-16 10:05:35,061 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1848 [2021-12-16 10:05:35,061 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:05:35,061 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:05:35,088 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:35,088 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:35,088 INFO L791 eck$LassoCheckResult]: Stem: 53632#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 53633#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 54631#L1903 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 54632#L907 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 54717#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 54096#L914-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 53565#L919-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 53566#L924-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 54382#L929-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 54383#L934-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 54483#L939-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 54484#L944-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 53337#L949-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 53338#L954-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 54513#L959-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 53873#L964-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 53874#L969-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 54434#L974-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 53775#L979-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 53776#L1291 assume 0 == ~M_E~0;~M_E~0 := 1; 54718#L1291-2 assume !(0 == ~T1_E~0); 54716#L1296-1 assume !(0 == ~T2_E~0); 53932#L1301-1 assume !(0 == ~T3_E~0); 53933#L1306-1 assume !(0 == ~T4_E~0); 54442#L1311-1 assume !(0 == ~T5_E~0); 53180#L1316-1 assume !(0 == ~T6_E~0); 53181#L1321-1 assume !(0 == ~T7_E~0); 53945#L1326-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 53008#L1331-1 assume !(0 == ~T9_E~0); 52707#L1336-1 assume !(0 == ~T10_E~0); 52708#L1341-1 assume !(0 == ~T11_E~0); 52788#L1346-1 assume !(0 == ~T12_E~0); 52789#L1351-1 assume !(0 == ~T13_E~0); 53129#L1356-1 assume !(0 == ~E_M~0); 53130#L1361-1 assume !(0 == ~E_1~0); 54657#L1366-1 assume 0 == ~E_2~0;~E_2~0 := 1; 53170#L1371-1 assume !(0 == ~E_3~0); 53171#L1376-1 assume !(0 == ~E_4~0); 53992#L1381-1 assume !(0 == ~E_5~0); 53993#L1386-1 assume !(0 == ~E_6~0); 54687#L1391-1 assume !(0 == ~E_7~0); 54705#L1396-1 assume !(0 == ~E_8~0); 53905#L1401-1 assume !(0 == ~E_9~0); 53906#L1406-1 assume 0 == ~E_10~0;~E_10~0 := 1; 54184#L1411-1 assume !(0 == ~E_11~0); 54185#L1416-1 assume !(0 == ~E_12~0); 53817#L1421-1 assume !(0 == ~E_13~0); 53360#L1426-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 53361#L640 assume !(1 == ~m_pc~0); 53870#L640-2 is_master_triggered_~__retres1~0#1 := 0; 53869#L651 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 53961#L652 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 53855#L1603 assume !(0 != activate_threads_~tmp~1#1); 53856#L1603-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 53490#L659 assume 1 == ~t1_pc~0; 53491#L660 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 53596#L670 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 54542#L671 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 53616#L1611 assume !(0 != activate_threads_~tmp___0~0#1); 53617#L1611-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 53630#L678 assume 1 == ~t2_pc~0; 54584#L679 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 54585#L689 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 54684#L690 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 53728#L1619 assume !(0 != activate_threads_~tmp___1~0#1); 53729#L1619-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 53850#L697 assume !(1 == ~t3_pc~0); 53851#L697-2 is_transmit3_triggered_~__retres1~3#1 := 0; 53973#L708 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 53781#L709 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 53760#L1627 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 53761#L1627-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 54621#L716 assume 1 == ~t4_pc~0; 54607#L717 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 53471#L727 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 53472#L728 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 52971#L1635 assume !(0 != activate_threads_~tmp___3~0#1); 52972#L1635-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 54263#L735 assume !(1 == ~t5_pc~0); 52932#L735-2 is_transmit5_triggered_~__retres1~5#1 := 0; 52933#L746 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 53383#L747 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 54290#L1643 assume !(0 != activate_threads_~tmp___4~0#1); 53926#L1643-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 53927#L754 assume 1 == ~t6_pc~0; 53680#L755 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 53578#L765 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 53579#L766 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 53552#L1651 assume !(0 != activate_threads_~tmp___5~0#1); 53553#L1651-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 54373#L773 assume !(1 == ~t7_pc~0); 53133#L773-2 is_transmit7_triggered_~__retres1~7#1 := 0; 53132#L784 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 53962#L785 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 53934#L1659 assume !(0 != activate_threads_~tmp___6~0#1); 53935#L1659-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 53982#L792 assume 1 == ~t8_pc~0; 54155#L793 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 54487#L803 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 53976#L804 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 53929#L1667 assume !(0 != activate_threads_~tmp___7~0#1); 53853#L1667-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 53854#L811 assume 1 == ~t9_pc~0; 54058#L812 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 54524#L822 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 54400#L823 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 54054#L1675 assume !(0 != activate_threads_~tmp___8~0#1); 53866#L1675-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 53867#L830 assume !(1 == ~t10_pc~0); 53588#L830-2 is_transmit10_triggered_~__retres1~10#1 := 0; 53112#L841 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 52805#L842 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 52806#L1683 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 53093#L1683-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 54391#L849 assume 1 == ~t11_pc~0; 54392#L850 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 52908#L860 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 52909#L861 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 53498#L1691 assume !(0 != activate_threads_~tmp___10~0#1); 54297#L1691-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 54298#L868 assume !(1 == ~t12_pc~0); 53713#L868-2 is_transmit12_triggered_~__retres1~12#1 := 0; 53712#L879 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 53507#L880 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 53508#L1699 assume !(0 != activate_threads_~tmp___11~0#1); 53144#L1699-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 53145#L887 assume 1 == ~t13_pc~0; 54312#L888 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 53754#L898 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 53755#L899 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 54191#L1707 assume !(0 != activate_threads_~tmp___12~0#1); 52848#L1707-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 52849#L1439 assume !(1 == ~M_E~0); 53922#L1439-2 assume !(1 == ~T1_E~0); 53020#L1444-1 assume !(1 == ~T2_E~0); 53021#L1449-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 53494#L1454-1 assume !(1 == ~T4_E~0); 53495#L1459-1 assume !(1 == ~T5_E~0); 54051#L1464-1 assume !(1 == ~T6_E~0); 54052#L1469-1 assume !(1 == ~T7_E~0); 54124#L1474-1 assume !(1 == ~T8_E~0); 53818#L1479-1 assume !(1 == ~T9_E~0); 53819#L1484-1 assume !(1 == ~T10_E~0); 54055#L1489-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 53701#L1494-1 assume !(1 == ~T12_E~0); 53702#L1499-1 assume !(1 == ~T13_E~0); 53894#L1504-1 assume !(1 == ~E_M~0); 53895#L1509-1 assume !(1 == ~E_1~0); 54470#L1514-1 assume !(1 == ~E_2~0); 54157#L1519-1 assume !(1 == ~E_3~0); 54158#L1524-1 assume !(1 == ~E_4~0); 54670#L1529-1 assume 1 == ~E_5~0;~E_5~0 := 2; 54671#L1534-1 assume !(1 == ~E_6~0); 52841#L1539-1 assume !(1 == ~E_7~0); 52842#L1544-1 assume !(1 == ~E_8~0); 53256#L1549-1 assume !(1 == ~E_9~0); 54645#L1554-1 assume !(1 == ~E_10~0); 54641#L1559-1 assume !(1 == ~E_11~0); 54508#L1564-1 assume !(1 == ~E_12~0); 54509#L1569-1 assume 1 == ~E_13~0;~E_13~0 := 2; 54666#L1574-1 assume { :end_inline_reset_delta_events } true; 53018#L1940-2 [2021-12-16 10:05:35,089 INFO L793 eck$LassoCheckResult]: Loop: 53018#L1940-2 assume !false; 53019#L1941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 53301#L1266 assume !false; 54320#L1075 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 53549#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 53282#L1064 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 53673#L1065 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 53674#L1079 assume !(0 != eval_~tmp~0#1); 53635#L1281 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 53636#L907-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 54240#L1291-3 assume 0 == ~M_E~0;~M_E~0 := 1; 54125#L1291-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 54126#L1296-3 assume !(0 == ~T2_E~0); 54698#L1301-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 54652#L1306-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 53783#L1311-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 53059#L1316-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 53060#L1321-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 53160#L1326-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 53917#L1331-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 54166#L1336-3 assume !(0 == ~T10_E~0); 54167#L1341-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 53487#L1346-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 53467#L1351-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 53412#L1356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 53413#L1361-3 assume 0 == ~E_1~0;~E_1~0 := 1; 53974#L1366-3 assume 0 == ~E_2~0;~E_2~0 := 1; 52763#L1371-3 assume 0 == ~E_3~0;~E_3~0 := 1; 52764#L1376-3 assume !(0 == ~E_4~0); 54493#L1381-3 assume 0 == ~E_5~0;~E_5~0 := 1; 54353#L1386-3 assume 0 == ~E_6~0;~E_6~0 := 1; 54354#L1391-3 assume 0 == ~E_7~0;~E_7~0 := 1; 54516#L1396-3 assume 0 == ~E_8~0;~E_8~0 := 1; 54517#L1401-3 assume 0 == ~E_9~0;~E_9~0 := 1; 53126#L1406-3 assume 0 == ~E_10~0;~E_10~0 := 1; 52980#L1411-3 assume 0 == ~E_11~0;~E_11~0 := 1; 52981#L1416-3 assume !(0 == ~E_12~0); 53642#L1421-3 assume 0 == ~E_13~0;~E_13~0 := 1; 53643#L1426-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 53750#L640-45 assume !(1 == ~m_pc~0); 53751#L640-47 is_master_triggered_~__retres1~0#1 := 0; 53217#L651-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 53218#L652-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 52757#L1603-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 52758#L1603-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 52856#L659-45 assume 1 == ~t1_pc~0; 52857#L660-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 53296#L670-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 54255#L671-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 54256#L1611-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 54277#L1611-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 54278#L678-45 assume 1 == ~t2_pc~0; 54221#L679-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 53756#L689-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 53757#L690-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 53909#L1619-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 54534#L1619-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 54651#L697-45 assume !(1 == ~t3_pc~0); 54016#L697-47 is_transmit3_triggered_~__retres1~3#1 := 0; 54015#L708-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 54603#L709-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 54173#L1627-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 54174#L1627-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 54204#L716-45 assume 1 == ~t4_pc~0; 53835#L717-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 53836#L727-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 54386#L728-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 53841#L1635-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 53842#L1635-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 53504#L735-45 assume 1 == ~t5_pc~0; 53505#L736-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 54048#L746-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 54610#L747-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 54611#L1643-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 54669#L1643-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 54664#L754-45 assume 1 == ~t6_pc~0; 53996#L755-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 53997#L765-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 53426#L766-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 53427#L1651-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 54000#L1651-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 53732#L773-45 assume 1 == ~t7_pc~0; 53733#L774-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 53290#L784-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 54210#L785-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 54492#L1659-45 assume !(0 != activate_threads_~tmp___6~0#1); 53738#L1659-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 53408#L792-45 assume 1 == ~t8_pc~0; 53409#L793-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 54438#L803-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 53011#L804-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 52870#L1667-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 52871#L1667-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 53366#L811-45 assume 1 == ~t9_pc~0; 53155#L812-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 53157#L822-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 54365#L823-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 54200#L1675-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 53809#L1675-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 53601#L830-45 assume 1 == ~t10_pc~0; 53602#L831-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 52799#L841-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 53921#L842-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 53031#L1683-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 53032#L1683-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 52777#L849-45 assume !(1 == ~t11_pc~0); 52778#L849-47 is_transmit11_triggered_~__retres1~11#1 := 0; 53237#L860-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 52868#L861-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 52765#L1691-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 52766#L1691-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 53024#L868-45 assume 1 == ~t12_pc~0; 53025#L869-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 52964#L879-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 52965#L880-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 54303#L1699-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 54554#L1699-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 54555#L887-45 assume 1 == ~t13_pc~0; 54385#L888-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 53034#L898-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 54316#L899-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 54661#L1707-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 52996#L1707-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 52997#L1439-3 assume 1 == ~M_E~0;~M_E~0 := 2; 54304#L1439-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 53016#L1444-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 53017#L1449-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 53174#L1454-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 54105#L1459-3 assume !(1 == ~T5_E~0); 54106#L1464-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 54557#L1469-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 54496#L1474-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 54497#L1479-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 54558#L1484-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 53790#L1489-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 53791#L1494-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 54427#L1499-3 assume !(1 == ~T13_E~0); 54066#L1504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 54067#L1509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 54505#L1514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 54535#L1519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 53709#L1524-3 assume 1 == ~E_4~0;~E_4~0 := 2; 53710#L1529-3 assume 1 == ~E_5~0;~E_5~0 := 2; 54577#L1534-3 assume 1 == ~E_6~0;~E_6~0 := 2; 53977#L1539-3 assume !(1 == ~E_7~0); 53453#L1544-3 assume 1 == ~E_8~0;~E_8~0 := 2; 53454#L1549-3 assume 1 == ~E_9~0;~E_9~0 := 2; 53949#L1554-3 assume 1 == ~E_10~0;~E_10~0 := 2; 53070#L1559-3 assume 1 == ~E_11~0;~E_11~0 := 2; 53071#L1564-3 assume 1 == ~E_12~0;~E_12~0 := 2; 54205#L1569-3 assume 1 == ~E_13~0;~E_13~0 := 2; 54206#L1574-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 52947#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 52718#L1064-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 52993#L1065-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 52954#L1959 assume !(0 == start_simulation_~tmp~3#1); 52956#L1959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 52988#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 52938#L1064-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 54247#L1065-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 54368#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 54575#L1921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 54589#L1922 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 54590#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 53018#L1940-2 [2021-12-16 10:05:35,089 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:35,089 INFO L85 PathProgramCache]: Analyzing trace with hash -327400631, now seen corresponding path program 1 times [2021-12-16 10:05:35,089 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:35,089 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [588735464] [2021-12-16 10:05:35,090 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:35,090 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:35,103 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:35,124 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:05:35,125 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:35,125 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [588735464] [2021-12-16 10:05:35,125 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [588735464] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:35,125 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:35,125 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-16 10:05:35,125 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1035464878] [2021-12-16 10:05:35,125 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:35,126 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:05:35,126 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:35,126 INFO L85 PathProgramCache]: Analyzing trace with hash 222566493, now seen corresponding path program 2 times [2021-12-16 10:05:35,126 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:35,126 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1856791029] [2021-12-16 10:05:35,126 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:35,126 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:35,141 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:35,166 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:05:35,167 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:35,167 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1856791029] [2021-12-16 10:05:35,167 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1856791029] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:35,167 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:35,167 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:05:35,167 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1837957192] [2021-12-16 10:05:35,167 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:35,168 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:05:35,168 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:05:35,168 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-16 10:05:35,168 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-16 10:05:35,168 INFO L87 Difference]: Start difference. First operand 2023 states and 2984 transitions. cyclomatic complexity: 962 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 2 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:35,234 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:05:35,234 INFO L93 Difference]: Finished difference Result 3771 states and 5546 transitions. [2021-12-16 10:05:35,235 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-16 10:05:35,235 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3771 states and 5546 transitions. [2021-12-16 10:05:35,250 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3596 [2021-12-16 10:05:35,261 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3771 states to 3771 states and 5546 transitions. [2021-12-16 10:05:35,261 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3771 [2021-12-16 10:05:35,264 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3771 [2021-12-16 10:05:35,264 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3771 states and 5546 transitions. [2021-12-16 10:05:35,268 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:05:35,269 INFO L681 BuchiCegarLoop]: Abstraction has 3771 states and 5546 transitions. [2021-12-16 10:05:35,272 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3771 states and 5546 transitions. [2021-12-16 10:05:35,316 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3771 to 3771. [2021-12-16 10:05:35,321 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3771 states, 3771 states have (on average 1.4706974277380005) internal successors, (5546), 3770 states have internal predecessors, (5546), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:35,328 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3771 states to 3771 states and 5546 transitions. [2021-12-16 10:05:35,329 INFO L704 BuchiCegarLoop]: Abstraction has 3771 states and 5546 transitions. [2021-12-16 10:05:35,329 INFO L587 BuchiCegarLoop]: Abstraction has 3771 states and 5546 transitions. [2021-12-16 10:05:35,329 INFO L425 BuchiCegarLoop]: ======== Iteration 15============ [2021-12-16 10:05:35,329 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3771 states and 5546 transitions. [2021-12-16 10:05:35,338 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3596 [2021-12-16 10:05:35,339 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:05:35,339 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:05:35,341 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:35,341 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:35,341 INFO L791 eck$LassoCheckResult]: Stem: 59438#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 59439#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 60454#L1903 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 60455#L907 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 60552#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 59908#L914-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 59369#L919-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 59370#L924-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 60200#L929-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 60201#L934-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 60302#L939-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 60303#L944-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 59139#L949-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 59140#L954-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 60332#L959-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 59680#L964-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 59681#L969-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 60252#L974-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 59581#L979-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 59582#L1291 assume !(0 == ~M_E~0); 60553#L1291-2 assume !(0 == ~T1_E~0); 60551#L1296-1 assume !(0 == ~T2_E~0); 59741#L1301-1 assume !(0 == ~T3_E~0); 59742#L1306-1 assume !(0 == ~T4_E~0); 60260#L1311-1 assume !(0 == ~T5_E~0); 58982#L1316-1 assume !(0 == ~T6_E~0); 58983#L1321-1 assume !(0 == ~T7_E~0); 59754#L1326-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 58810#L1331-1 assume !(0 == ~T9_E~0); 58508#L1336-1 assume !(0 == ~T10_E~0); 58509#L1341-1 assume !(0 == ~T11_E~0); 58589#L1346-1 assume !(0 == ~T12_E~0); 58590#L1351-1 assume !(0 == ~T13_E~0); 58931#L1356-1 assume !(0 == ~E_M~0); 58932#L1361-1 assume !(0 == ~E_1~0); 60482#L1366-1 assume 0 == ~E_2~0;~E_2~0 := 1; 58972#L1371-1 assume !(0 == ~E_3~0); 58973#L1376-1 assume !(0 == ~E_4~0); 59804#L1381-1 assume !(0 == ~E_5~0); 59805#L1386-1 assume !(0 == ~E_6~0); 60517#L1391-1 assume !(0 == ~E_7~0); 60539#L1396-1 assume !(0 == ~E_8~0); 59713#L1401-1 assume !(0 == ~E_9~0); 59714#L1406-1 assume 0 == ~E_10~0;~E_10~0 := 1; 59997#L1411-1 assume !(0 == ~E_11~0); 59998#L1416-1 assume !(0 == ~E_12~0); 59624#L1421-1 assume !(0 == ~E_13~0); 59164#L1426-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 59165#L640 assume !(1 == ~m_pc~0); 59677#L640-2 is_master_triggered_~__retres1~0#1 := 0; 59676#L651 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 59770#L652 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 59662#L1603 assume !(0 != activate_threads_~tmp~1#1); 59663#L1603-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 59294#L659 assume 1 == ~t1_pc~0; 59295#L660 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 59401#L670 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 60363#L671 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 59422#L1611 assume !(0 != activate_threads_~tmp___0~0#1); 59423#L1611-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 59436#L678 assume 1 == ~t2_pc~0; 60406#L679 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 60407#L689 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 60512#L690 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 59534#L1619 assume !(0 != activate_threads_~tmp___1~0#1); 59535#L1619-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 59657#L697 assume !(1 == ~t3_pc~0); 59658#L697-2 is_transmit3_triggered_~__retres1~3#1 := 0; 59785#L708 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 59587#L709 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 59566#L1627 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 59567#L1627-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 60444#L716 assume 1 == ~t4_pc~0; 60430#L717 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 59276#L727 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 59277#L728 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 58773#L1635 assume !(0 != activate_threads_~tmp___3~0#1); 58774#L1635-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 60078#L735 assume !(1 == ~t5_pc~0); 58734#L735-2 is_transmit5_triggered_~__retres1~5#1 := 0; 58735#L746 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 59185#L747 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 60104#L1643 assume !(0 != activate_threads_~tmp___4~0#1); 59735#L1643-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 59736#L754 assume 1 == ~t6_pc~0; 59486#L755 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 59383#L765 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 59384#L766 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 59356#L1651 assume !(0 != activate_threads_~tmp___5~0#1); 59357#L1651-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 60190#L773 assume !(1 == ~t7_pc~0); 58935#L773-2 is_transmit7_triggered_~__retres1~7#1 := 0; 58934#L784 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 59771#L785 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 59743#L1659 assume !(0 != activate_threads_~tmp___6~0#1); 59744#L1659-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 59794#L792 assume 1 == ~t8_pc~0; 59970#L793 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 60306#L803 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 59788#L804 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 59738#L1667 assume !(0 != activate_threads_~tmp___7~0#1); 59660#L1667-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 59661#L811 assume 1 == ~t9_pc~0; 59871#L812 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 60343#L822 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 60217#L823 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 59866#L1675 assume !(0 != activate_threads_~tmp___8~0#1); 59673#L1675-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 59674#L830 assume !(1 == ~t10_pc~0); 59393#L830-2 is_transmit10_triggered_~__retres1~10#1 := 0; 58914#L841 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 58606#L842 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 58607#L1683 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 58895#L1683-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 60208#L849 assume 1 == ~t11_pc~0; 60209#L850 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 58710#L860 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 58711#L861 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 59302#L1691 assume !(0 != activate_threads_~tmp___10~0#1); 60113#L1691-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 60114#L868 assume !(1 == ~t12_pc~0); 59519#L868-2 is_transmit12_triggered_~__retres1~12#1 := 0; 59518#L879 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 59311#L880 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 59312#L1699 assume !(0 != activate_threads_~tmp___11~0#1); 58946#L1699-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 58947#L887 assume 1 == ~t13_pc~0; 60126#L888 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 59560#L898 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 59561#L899 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 60004#L1707 assume !(0 != activate_threads_~tmp___12~0#1); 58649#L1707-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 58650#L1439 assume !(1 == ~M_E~0); 59733#L1439-2 assume !(1 == ~T1_E~0); 58822#L1444-1 assume !(1 == ~T2_E~0); 58823#L1449-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 59300#L1454-1 assume !(1 == ~T4_E~0); 59301#L1459-1 assume !(1 == ~T5_E~0); 59863#L1464-1 assume !(1 == ~T6_E~0); 59864#L1469-1 assume !(1 == ~T7_E~0); 59937#L1474-1 assume !(1 == ~T8_E~0); 59625#L1479-1 assume !(1 == ~T9_E~0); 59626#L1484-1 assume !(1 == ~T10_E~0); 59867#L1489-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 59507#L1494-1 assume !(1 == ~T12_E~0); 59508#L1499-1 assume !(1 == ~T13_E~0); 59702#L1504-1 assume !(1 == ~E_M~0); 59703#L1509-1 assume !(1 == ~E_1~0); 60289#L1514-1 assume !(1 == ~E_2~0); 59972#L1519-1 assume !(1 == ~E_3~0); 59973#L1524-1 assume !(1 == ~E_4~0); 60497#L1529-1 assume 1 == ~E_5~0;~E_5~0 := 2; 60498#L1534-1 assume !(1 == ~E_6~0); 58642#L1539-1 assume !(1 == ~E_7~0); 58643#L1544-1 assume !(1 == ~E_8~0); 59058#L1549-1 assume !(1 == ~E_9~0); 60473#L1554-1 assume !(1 == ~E_10~0); 60465#L1559-1 assume !(1 == ~E_11~0); 60327#L1564-1 assume !(1 == ~E_12~0); 60328#L1569-1 assume 1 == ~E_13~0;~E_13~0 := 2; 60492#L1574-1 assume { :end_inline_reset_delta_events } true; 58820#L1940-2 [2021-12-16 10:05:35,342 INFO L793 eck$LassoCheckResult]: Loop: 58820#L1940-2 assume !false; 58821#L1941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 59103#L1266 assume !false; 60135#L1075 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 59353#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 59084#L1064 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 59480#L1065 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 59481#L1079 assume !(0 != eval_~tmp~0#1); 59441#L1281 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 59442#L907-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 60053#L1291-3 assume !(0 == ~M_E~0); 60054#L1291-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 62088#L1296-3 assume !(0 == ~T2_E~0); 62087#L1301-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 62086#L1306-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 62085#L1311-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 62084#L1316-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 62083#L1321-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 62082#L1326-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 62081#L1331-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 62080#L1336-3 assume !(0 == ~T10_E~0); 62079#L1341-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 62078#L1346-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 62077#L1351-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 62076#L1356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 62075#L1361-3 assume 0 == ~E_1~0;~E_1~0 := 1; 62074#L1366-3 assume 0 == ~E_2~0;~E_2~0 := 1; 62073#L1371-3 assume 0 == ~E_3~0;~E_3~0 := 1; 62072#L1376-3 assume !(0 == ~E_4~0); 62071#L1381-3 assume 0 == ~E_5~0;~E_5~0 := 1; 62070#L1386-3 assume 0 == ~E_6~0;~E_6~0 := 1; 62069#L1391-3 assume 0 == ~E_7~0;~E_7~0 := 1; 62068#L1396-3 assume 0 == ~E_8~0;~E_8~0 := 1; 62067#L1401-3 assume 0 == ~E_9~0;~E_9~0 := 1; 62066#L1406-3 assume 0 == ~E_10~0;~E_10~0 := 1; 62065#L1411-3 assume 0 == ~E_11~0;~E_11~0 := 1; 62064#L1416-3 assume !(0 == ~E_12~0); 62063#L1421-3 assume 0 == ~E_13~0;~E_13~0 := 1; 62062#L1426-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 62061#L640-45 assume 1 == ~m_pc~0; 62059#L641-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 62058#L651-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 62057#L652-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 62056#L1603-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 62055#L1603-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 62054#L659-45 assume 1 == ~t1_pc~0; 62052#L660-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 62051#L670-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 62050#L671-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 62049#L1611-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 62048#L1611-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 62047#L678-45 assume !(1 == ~t2_pc~0); 62045#L678-47 is_transmit2_triggered_~__retres1~2#1 := 0; 62044#L689-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 62043#L690-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 62042#L1619-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 62041#L1619-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 62040#L697-45 assume 1 == ~t3_pc~0; 62038#L698-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 62037#L708-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 62036#L709-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 62035#L1627-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 62034#L1627-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 62033#L716-45 assume 1 == ~t4_pc~0; 62032#L717-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 62030#L727-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 62029#L728-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 62028#L1635-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 62027#L1635-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 62026#L735-45 assume 1 == ~t5_pc~0; 62024#L736-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 62023#L746-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 62022#L747-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 62021#L1643-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 62020#L1643-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 62019#L754-45 assume !(1 == ~t6_pc~0); 62017#L754-47 is_transmit6_triggered_~__retres1~6#1 := 0; 62016#L765-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 62015#L766-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 62014#L1651-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 62013#L1651-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 62012#L773-45 assume 1 == ~t7_pc~0; 62010#L774-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 62009#L784-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 62008#L785-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 62007#L1659-45 assume !(0 != activate_threads_~tmp___6~0#1); 62006#L1659-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 62005#L792-45 assume 1 == ~t8_pc~0; 62003#L793-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 62002#L803-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 62001#L804-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 62000#L1667-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 61999#L1667-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 61935#L811-45 assume !(1 == ~t9_pc~0); 61933#L811-47 is_transmit9_triggered_~__retres1~9#1 := 0; 60180#L822-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 60181#L823-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 60509#L1675-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 61931#L1675-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 59406#L830-45 assume !(1 == ~t10_pc~0); 59408#L830-47 is_transmit10_triggered_~__retres1~10#1 := 0; 61930#L841-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 61929#L842-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 61928#L1683-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 61927#L1683-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 61926#L849-45 assume 1 == ~t11_pc~0; 59778#L850-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 59779#L860-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 61925#L861-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 58566#L1691-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 58567#L1691-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 58826#L868-45 assume 1 == ~t12_pc~0; 58827#L869-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 59286#L879-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 61920#L880-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 61919#L1699-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 61918#L1699-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 61917#L887-45 assume !(1 == ~t13_pc~0); 61915#L887-47 is_transmit13_triggered_~__retres1~13#1 := 0; 60129#L898-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 60130#L899-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 60487#L1707-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 58798#L1707-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 58799#L1439-3 assume !(1 == ~M_E~0); 60118#L1439-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 58818#L1444-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 58819#L1449-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 58976#L1454-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 59918#L1459-3 assume !(1 == ~T5_E~0); 59919#L1464-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 60378#L1469-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 60315#L1474-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 60316#L1479-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 60379#L1484-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 59594#L1489-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 59595#L1494-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 60245#L1499-3 assume !(1 == ~T13_E~0); 59878#L1504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 59879#L1509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 60324#L1514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 60356#L1519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 59515#L1524-3 assume 1 == ~E_4~0;~E_4~0 := 2; 59516#L1529-3 assume 1 == ~E_5~0;~E_5~0 := 2; 60399#L1534-3 assume 1 == ~E_6~0;~E_6~0 := 2; 59789#L1539-3 assume !(1 == ~E_7~0); 59256#L1544-3 assume 1 == ~E_8~0;~E_8~0 := 2; 59257#L1549-3 assume 1 == ~E_9~0;~E_9~0 := 2; 59757#L1554-3 assume 1 == ~E_10~0;~E_10~0 := 2; 58872#L1559-3 assume 1 == ~E_11~0;~E_11~0 := 2; 58873#L1564-3 assume 1 == ~E_12~0;~E_12~0 := 2; 60018#L1569-3 assume 1 == ~E_13~0;~E_13~0 := 2; 60019#L1574-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 58749#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 58519#L1064-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 58795#L1065-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 58756#L1959 assume !(0 == start_simulation_~tmp~3#1); 58758#L1959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 58790#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 58740#L1064-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 60061#L1065-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 60184#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 60397#L1921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 60412#L1922 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 60413#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 58820#L1940-2 [2021-12-16 10:05:35,342 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:35,342 INFO L85 PathProgramCache]: Analyzing trace with hash -867830137, now seen corresponding path program 1 times [2021-12-16 10:05:35,342 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:35,342 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1036029031] [2021-12-16 10:05:35,342 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:35,343 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:35,352 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:35,374 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:05:35,374 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:35,374 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1036029031] [2021-12-16 10:05:35,375 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1036029031] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:35,375 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:35,375 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:05:35,375 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1792746398] [2021-12-16 10:05:35,375 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:35,375 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:05:35,376 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:35,376 INFO L85 PathProgramCache]: Analyzing trace with hash 1928462239, now seen corresponding path program 1 times [2021-12-16 10:05:35,376 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:35,376 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1524180423] [2021-12-16 10:05:35,376 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:35,376 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:35,388 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:35,411 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:05:35,411 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:35,412 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1524180423] [2021-12-16 10:05:35,412 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1524180423] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:35,412 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:35,412 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:05:35,412 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [529530097] [2021-12-16 10:05:35,412 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:35,412 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:05:35,412 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:05:35,413 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-16 10:05:35,413 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-16 10:05:35,413 INFO L87 Difference]: Start difference. First operand 3771 states and 5546 transitions. cyclomatic complexity: 1776 Second operand has 4 states, 4 states have (on average 40.25) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:35,533 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:05:35,533 INFO L93 Difference]: Finished difference Result 5511 states and 8090 transitions. [2021-12-16 10:05:35,533 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-16 10:05:35,534 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5511 states and 8090 transitions. [2021-12-16 10:05:35,555 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 5316 [2021-12-16 10:05:35,571 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5511 states to 5511 states and 8090 transitions. [2021-12-16 10:05:35,571 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5511 [2021-12-16 10:05:35,576 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5511 [2021-12-16 10:05:35,576 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5511 states and 8090 transitions. [2021-12-16 10:05:35,582 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:05:35,583 INFO L681 BuchiCegarLoop]: Abstraction has 5511 states and 8090 transitions. [2021-12-16 10:05:35,588 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5511 states and 8090 transitions. [2021-12-16 10:05:35,642 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5511 to 3771. [2021-12-16 10:05:35,647 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3771 states, 3771 states have (on average 1.469901882789711) internal successors, (5543), 3770 states have internal predecessors, (5543), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:35,654 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3771 states to 3771 states and 5543 transitions. [2021-12-16 10:05:35,655 INFO L704 BuchiCegarLoop]: Abstraction has 3771 states and 5543 transitions. [2021-12-16 10:05:35,655 INFO L587 BuchiCegarLoop]: Abstraction has 3771 states and 5543 transitions. [2021-12-16 10:05:35,655 INFO L425 BuchiCegarLoop]: ======== Iteration 16============ [2021-12-16 10:05:35,655 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3771 states and 5543 transitions. [2021-12-16 10:05:35,664 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3596 [2021-12-16 10:05:35,664 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:05:35,664 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:05:35,666 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:35,666 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:35,685 INFO L791 eck$LassoCheckResult]: Stem: 68726#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 68727#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 69726#L1903 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 69727#L907 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 69812#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 69190#L914-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 68658#L919-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 68659#L924-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 69477#L929-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 69478#L934-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 69577#L939-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 69578#L944-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 68433#L949-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 68434#L954-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 69607#L959-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 68967#L964-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 68968#L969-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 69528#L974-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 68870#L979-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 68871#L1291 assume !(0 == ~M_E~0); 69813#L1291-2 assume !(0 == ~T1_E~0); 69811#L1296-1 assume !(0 == ~T2_E~0); 69026#L1301-1 assume !(0 == ~T3_E~0); 69027#L1306-1 assume !(0 == ~T4_E~0); 69537#L1311-1 assume !(0 == ~T5_E~0); 68273#L1316-1 assume !(0 == ~T6_E~0); 68274#L1321-1 assume !(0 == ~T7_E~0); 69039#L1326-1 assume !(0 == ~T8_E~0); 68101#L1331-1 assume !(0 == ~T9_E~0); 67800#L1336-1 assume !(0 == ~T10_E~0); 67801#L1341-1 assume !(0 == ~T11_E~0); 67881#L1346-1 assume !(0 == ~T12_E~0); 67882#L1351-1 assume !(0 == ~T13_E~0); 68222#L1356-1 assume !(0 == ~E_M~0); 68223#L1361-1 assume !(0 == ~E_1~0); 69752#L1366-1 assume 0 == ~E_2~0;~E_2~0 := 1; 68263#L1371-1 assume !(0 == ~E_3~0); 68264#L1376-1 assume !(0 == ~E_4~0); 69086#L1381-1 assume !(0 == ~E_5~0); 69087#L1386-1 assume !(0 == ~E_6~0); 69782#L1391-1 assume !(0 == ~E_7~0); 69800#L1396-1 assume !(0 == ~E_8~0); 68999#L1401-1 assume !(0 == ~E_9~0); 69000#L1406-1 assume 0 == ~E_10~0;~E_10~0 := 1; 69278#L1411-1 assume !(0 == ~E_11~0); 69279#L1416-1 assume !(0 == ~E_12~0); 68911#L1421-1 assume !(0 == ~E_13~0); 68457#L1426-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 68458#L640 assume !(1 == ~m_pc~0); 68964#L640-2 is_master_triggered_~__retres1~0#1 := 0; 68963#L651 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 69055#L652 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 68949#L1603 assume !(0 != activate_threads_~tmp~1#1); 68950#L1603-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 68583#L659 assume 1 == ~t1_pc~0; 68584#L660 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 68690#L670 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 69636#L671 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 68710#L1611 assume !(0 != activate_threads_~tmp___0~0#1); 68711#L1611-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 68724#L678 assume 1 == ~t2_pc~0; 69678#L679 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 69679#L689 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 69779#L690 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 68822#L1619 assume !(0 != activate_threads_~tmp___1~0#1); 68823#L1619-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 68944#L697 assume !(1 == ~t3_pc~0); 68945#L697-2 is_transmit3_triggered_~__retres1~3#1 := 0; 69067#L708 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 68875#L709 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 68854#L1627 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 68855#L1627-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 69716#L716 assume 1 == ~t4_pc~0; 69702#L717 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 68566#L727 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 68567#L728 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 68064#L1635 assume !(0 != activate_threads_~tmp___3~0#1); 68065#L1635-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 69358#L735 assume !(1 == ~t5_pc~0); 68025#L735-2 is_transmit5_triggered_~__retres1~5#1 := 0; 68026#L746 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 68476#L747 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 69386#L1643 assume !(0 != activate_threads_~tmp___4~0#1); 69020#L1643-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 69021#L754 assume 1 == ~t6_pc~0; 68776#L755 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 68672#L765 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 68673#L766 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 68645#L1651 assume !(0 != activate_threads_~tmp___5~0#1); 68646#L1651-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 69467#L773 assume !(1 == ~t7_pc~0); 68226#L773-2 is_transmit7_triggered_~__retres1~7#1 := 0; 68225#L784 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 69056#L785 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 69028#L1659 assume !(0 != activate_threads_~tmp___6~0#1); 69029#L1659-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 69076#L792 assume 1 == ~t8_pc~0; 69251#L793 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 69581#L803 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 69070#L804 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 69024#L1667 assume !(0 != activate_threads_~tmp___7~0#1); 68947#L1667-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 68948#L811 assume 1 == ~t9_pc~0; 69153#L812 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 69618#L822 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 69494#L823 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 69148#L1675 assume !(0 != activate_threads_~tmp___8~0#1); 68960#L1675-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 68961#L830 assume !(1 == ~t10_pc~0); 68684#L830-2 is_transmit10_triggered_~__retres1~10#1 := 0; 68205#L841 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 67898#L842 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 67899#L1683 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 68186#L1683-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 69485#L849 assume 1 == ~t11_pc~0; 69486#L850 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 68001#L860 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 68002#L861 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 68593#L1691 assume !(0 != activate_threads_~tmp___10~0#1); 69393#L1691-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 69394#L868 assume !(1 == ~t12_pc~0); 68807#L868-2 is_transmit12_triggered_~__retres1~12#1 := 0; 68806#L879 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 68600#L880 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 68601#L1699 assume !(0 != activate_threads_~tmp___11~0#1); 68237#L1699-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 68238#L887 assume 1 == ~t13_pc~0; 69406#L888 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 68848#L898 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 68849#L899 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 69285#L1707 assume !(0 != activate_threads_~tmp___12~0#1); 67941#L1707-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 67942#L1439 assume !(1 == ~M_E~0); 69018#L1439-2 assume !(1 == ~T1_E~0); 68113#L1444-1 assume !(1 == ~T2_E~0); 68114#L1449-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 68589#L1454-1 assume !(1 == ~T4_E~0); 68590#L1459-1 assume !(1 == ~T5_E~0); 69145#L1464-1 assume !(1 == ~T6_E~0); 69146#L1469-1 assume !(1 == ~T7_E~0); 69221#L1474-1 assume !(1 == ~T8_E~0); 68912#L1479-1 assume !(1 == ~T9_E~0); 68913#L1484-1 assume !(1 == ~T10_E~0); 69149#L1489-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 68798#L1494-1 assume !(1 == ~T12_E~0); 68799#L1499-1 assume !(1 == ~T13_E~0); 68988#L1504-1 assume !(1 == ~E_M~0); 68989#L1509-1 assume !(1 == ~E_1~0); 69564#L1514-1 assume !(1 == ~E_2~0); 69253#L1519-1 assume !(1 == ~E_3~0); 69254#L1524-1 assume !(1 == ~E_4~0); 69765#L1529-1 assume 1 == ~E_5~0;~E_5~0 := 2; 69766#L1534-1 assume !(1 == ~E_6~0); 67934#L1539-1 assume !(1 == ~E_7~0); 67935#L1544-1 assume !(1 == ~E_8~0); 68349#L1549-1 assume !(1 == ~E_9~0); 69744#L1554-1 assume !(1 == ~E_10~0); 69737#L1559-1 assume !(1 == ~E_11~0); 69602#L1564-1 assume !(1 == ~E_12~0); 69603#L1569-1 assume 1 == ~E_13~0;~E_13~0 := 2; 69761#L1574-1 assume { :end_inline_reset_delta_events } true; 68111#L1940-2 [2021-12-16 10:05:35,686 INFO L793 eck$LassoCheckResult]: Loop: 68111#L1940-2 assume !false; 68112#L1941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 68394#L1266 assume !false; 69414#L1075 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 68642#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 68375#L1064 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 68767#L1065 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 68768#L1079 assume !(0 != eval_~tmp~0#1); 68729#L1281 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 68730#L907-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 69334#L1291-3 assume !(0 == ~M_E~0); 69218#L1291-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 69219#L1296-3 assume !(0 == ~T2_E~0); 69793#L1301-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 69747#L1306-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 68877#L1311-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 68152#L1316-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 68153#L1321-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 68253#L1326-3 assume !(0 == ~T8_E~0); 69011#L1331-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 69260#L1336-3 assume !(0 == ~T10_E~0); 69261#L1341-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 68580#L1346-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 68560#L1351-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 68505#L1356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 68506#L1361-3 assume 0 == ~E_1~0;~E_1~0 := 1; 69068#L1366-3 assume 0 == ~E_2~0;~E_2~0 := 1; 67856#L1371-3 assume 0 == ~E_3~0;~E_3~0 := 1; 67857#L1376-3 assume !(0 == ~E_4~0); 69587#L1381-3 assume 0 == ~E_5~0;~E_5~0 := 1; 69447#L1386-3 assume 0 == ~E_6~0;~E_6~0 := 1; 69448#L1391-3 assume 0 == ~E_7~0;~E_7~0 := 1; 69610#L1396-3 assume 0 == ~E_8~0;~E_8~0 := 1; 69611#L1401-3 assume 0 == ~E_9~0;~E_9~0 := 1; 68219#L1406-3 assume 0 == ~E_10~0;~E_10~0 := 1; 68073#L1411-3 assume 0 == ~E_11~0;~E_11~0 := 1; 68074#L1416-3 assume !(0 == ~E_12~0); 68736#L1421-3 assume 0 == ~E_13~0;~E_13~0 := 1; 68737#L1426-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 68844#L640-45 assume !(1 == ~m_pc~0); 68845#L640-47 is_master_triggered_~__retres1~0#1 := 0; 68310#L651-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 68311#L652-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 67850#L1603-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 67851#L1603-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 67949#L659-45 assume !(1 == ~t1_pc~0); 67951#L659-47 is_transmit1_triggered_~__retres1~1#1 := 0; 68392#L670-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 69349#L671-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 69350#L1611-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 69371#L1611-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 69372#L678-45 assume 1 == ~t2_pc~0; 69315#L679-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 68850#L689-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 68851#L690-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 69003#L1619-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 69628#L1619-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 69746#L697-45 assume 1 == ~t3_pc~0; 69108#L698-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 69109#L708-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 69697#L709-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 69267#L1627-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 69268#L1627-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 69298#L716-45 assume 1 == ~t4_pc~0; 68929#L717-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 68930#L727-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 69480#L728-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 68935#L1635-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 68936#L1635-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 68597#L735-45 assume !(1 == ~t5_pc~0); 68599#L735-47 is_transmit5_triggered_~__retres1~5#1 := 0; 69142#L746-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 69705#L747-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 69706#L1643-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 69764#L1643-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 69759#L754-45 assume 1 == ~t6_pc~0; 69090#L755-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 69091#L765-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 68519#L766-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 68520#L1651-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 69094#L1651-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 68826#L773-45 assume 1 == ~t7_pc~0; 68827#L774-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 68384#L784-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 69304#L785-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 69586#L1659-45 assume !(0 != activate_threads_~tmp___6~0#1); 68832#L1659-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 68501#L792-45 assume !(1 == ~t8_pc~0); 68503#L792-47 is_transmit8_triggered_~__retres1~8#1 := 0; 69532#L803-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 68104#L804-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 67963#L1667-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 67964#L1667-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 68459#L811-45 assume !(1 == ~t9_pc~0); 68251#L811-47 is_transmit9_triggered_~__retres1~9#1 := 0; 68252#L822-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 69459#L823-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 69294#L1675-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 68903#L1675-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 68694#L830-45 assume !(1 == ~t10_pc~0); 67891#L830-47 is_transmit10_triggered_~__retres1~10#1 := 0; 67892#L841-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 69015#L842-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 68124#L1683-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 68125#L1683-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 67867#L849-45 assume 1 == ~t11_pc~0; 67869#L850-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 68330#L860-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 67961#L861-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 67858#L1691-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 67859#L1691-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 68117#L868-45 assume !(1 == ~t12_pc~0); 68119#L868-47 is_transmit12_triggered_~__retres1~12#1 := 0; 68055#L879-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 68056#L880-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 69397#L1699-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 69648#L1699-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 69649#L887-45 assume 1 == ~t13_pc~0; 69479#L888-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 68127#L898-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 69408#L899-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 69756#L1707-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 68089#L1707-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 68090#L1439-3 assume !(1 == ~M_E~0); 69398#L1439-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 68109#L1444-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 68110#L1449-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 68267#L1454-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 69199#L1459-3 assume !(1 == ~T5_E~0); 69200#L1464-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 69651#L1469-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 69590#L1474-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 69591#L1479-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 69652#L1484-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 68882#L1489-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 68883#L1494-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 69521#L1499-3 assume !(1 == ~T13_E~0); 69160#L1504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 69161#L1509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 69599#L1514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 69629#L1519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 68803#L1524-3 assume 1 == ~E_4~0;~E_4~0 := 2; 68804#L1529-3 assume 1 == ~E_5~0;~E_5~0 := 2; 69671#L1534-3 assume 1 == ~E_6~0;~E_6~0 := 2; 69071#L1539-3 assume !(1 == ~E_7~0); 68546#L1544-3 assume 1 == ~E_8~0;~E_8~0 := 2; 68547#L1549-3 assume 1 == ~E_9~0;~E_9~0 := 2; 69042#L1554-3 assume 1 == ~E_10~0;~E_10~0 := 2; 68163#L1559-3 assume 1 == ~E_11~0;~E_11~0 := 2; 68164#L1564-3 assume 1 == ~E_12~0;~E_12~0 := 2; 69299#L1569-3 assume 1 == ~E_13~0;~E_13~0 := 2; 69300#L1574-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 68040#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 67811#L1064-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 68086#L1065-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 68047#L1959 assume !(0 == start_simulation_~tmp~3#1); 68049#L1959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 68081#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 68031#L1064-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 69341#L1065-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 69462#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 69668#L1921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 69683#L1922 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 69684#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 68111#L1940-2 [2021-12-16 10:05:35,686 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:35,686 INFO L85 PathProgramCache]: Analyzing trace with hash 1809696709, now seen corresponding path program 1 times [2021-12-16 10:05:35,687 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:35,687 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1978183606] [2021-12-16 10:05:35,687 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:35,687 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:35,700 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:35,728 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:05:35,728 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:35,728 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1978183606] [2021-12-16 10:05:35,728 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1978183606] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:35,728 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:35,728 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:05:35,728 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1685001180] [2021-12-16 10:05:35,729 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:35,729 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:05:35,729 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:35,729 INFO L85 PathProgramCache]: Analyzing trace with hash 1716026143, now seen corresponding path program 1 times [2021-12-16 10:05:35,730 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:35,730 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [523256510] [2021-12-16 10:05:35,730 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:35,730 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:35,742 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:35,766 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:05:35,767 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:35,767 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [523256510] [2021-12-16 10:05:35,767 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [523256510] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:35,767 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:35,767 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:05:35,767 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1814481023] [2021-12-16 10:05:35,767 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:35,768 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:05:35,768 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:05:35,768 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-16 10:05:35,768 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-16 10:05:35,768 INFO L87 Difference]: Start difference. First operand 3771 states and 5543 transitions. cyclomatic complexity: 1773 Second operand has 4 states, 4 states have (on average 40.25) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:35,937 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:05:35,937 INFO L93 Difference]: Finished difference Result 5404 states and 7929 transitions. [2021-12-16 10:05:35,938 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-16 10:05:35,938 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5404 states and 7929 transitions. [2021-12-16 10:05:35,960 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 5216 [2021-12-16 10:05:35,976 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5404 states to 5404 states and 7929 transitions. [2021-12-16 10:05:35,977 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5404 [2021-12-16 10:05:35,981 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5404 [2021-12-16 10:05:35,981 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5404 states and 7929 transitions. [2021-12-16 10:05:35,988 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:05:35,988 INFO L681 BuchiCegarLoop]: Abstraction has 5404 states and 7929 transitions. [2021-12-16 10:05:35,992 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5404 states and 7929 transitions. [2021-12-16 10:05:36,047 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5404 to 3771. [2021-12-16 10:05:36,051 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3771 states, 3771 states have (on average 1.4691063378414213) internal successors, (5540), 3770 states have internal predecessors, (5540), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:36,059 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3771 states to 3771 states and 5540 transitions. [2021-12-16 10:05:36,059 INFO L704 BuchiCegarLoop]: Abstraction has 3771 states and 5540 transitions. [2021-12-16 10:05:36,059 INFO L587 BuchiCegarLoop]: Abstraction has 3771 states and 5540 transitions. [2021-12-16 10:05:36,060 INFO L425 BuchiCegarLoop]: ======== Iteration 17============ [2021-12-16 10:05:36,060 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3771 states and 5540 transitions. [2021-12-16 10:05:36,069 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3596 [2021-12-16 10:05:36,069 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:05:36,069 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:05:36,071 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:36,071 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:36,072 INFO L791 eck$LassoCheckResult]: Stem: 77912#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 77913#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 78930#L1903 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 78931#L907 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 79025#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 78377#L914-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 77844#L919-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 77845#L924-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 78671#L929-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 78672#L934-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 78774#L939-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 78775#L944-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 77619#L949-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 77620#L954-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 78804#L959-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 78154#L964-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 78155#L969-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 78723#L974-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 78056#L979-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 78057#L1291 assume !(0 == ~M_E~0); 79026#L1291-2 assume !(0 == ~T1_E~0); 79024#L1296-1 assume !(0 == ~T2_E~0); 78213#L1301-1 assume !(0 == ~T3_E~0); 78214#L1306-1 assume !(0 == ~T4_E~0); 78733#L1311-1 assume !(0 == ~T5_E~0); 77458#L1316-1 assume !(0 == ~T6_E~0); 77459#L1321-1 assume !(0 == ~T7_E~0); 78226#L1326-1 assume !(0 == ~T8_E~0); 77286#L1331-1 assume !(0 == ~T9_E~0); 76985#L1336-1 assume !(0 == ~T10_E~0); 76986#L1341-1 assume !(0 == ~T11_E~0); 77066#L1346-1 assume !(0 == ~T12_E~0); 77067#L1351-1 assume !(0 == ~T13_E~0); 77407#L1356-1 assume !(0 == ~E_M~0); 77408#L1361-1 assume !(0 == ~E_1~0); 78958#L1366-1 assume !(0 == ~E_2~0); 77448#L1371-1 assume !(0 == ~E_3~0); 77449#L1376-1 assume !(0 == ~E_4~0); 78273#L1381-1 assume !(0 == ~E_5~0); 78274#L1386-1 assume !(0 == ~E_6~0); 78993#L1391-1 assume !(0 == ~E_7~0); 79011#L1396-1 assume !(0 == ~E_8~0); 78186#L1401-1 assume !(0 == ~E_9~0); 78187#L1406-1 assume 0 == ~E_10~0;~E_10~0 := 1; 78466#L1411-1 assume !(0 == ~E_11~0); 78467#L1416-1 assume !(0 == ~E_12~0); 78098#L1421-1 assume !(0 == ~E_13~0); 77643#L1426-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 77644#L640 assume !(1 == ~m_pc~0); 78151#L640-2 is_master_triggered_~__retres1~0#1 := 0; 78150#L651 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 78242#L652 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 78136#L1603 assume !(0 != activate_threads_~tmp~1#1); 78137#L1603-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 77769#L659 assume 1 == ~t1_pc~0; 77770#L660 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 77876#L670 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 78833#L671 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 77896#L1611 assume !(0 != activate_threads_~tmp___0~0#1); 77897#L1611-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 77910#L678 assume 1 == ~t2_pc~0; 78879#L679 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 78880#L689 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 78990#L690 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 78008#L1619 assume !(0 != activate_threads_~tmp___1~0#1); 78009#L1619-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 78131#L697 assume !(1 == ~t3_pc~0); 78132#L697-2 is_transmit3_triggered_~__retres1~3#1 := 0; 78254#L708 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 78061#L709 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 78040#L1627 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 78041#L1627-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 78918#L716 assume 1 == ~t4_pc~0; 78904#L717 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 77752#L727 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 77753#L728 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 77249#L1635 assume !(0 != activate_threads_~tmp___3~0#1); 77250#L1635-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 78548#L735 assume !(1 == ~t5_pc~0); 77210#L735-2 is_transmit5_triggered_~__retres1~5#1 := 0; 77211#L746 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 77662#L747 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 78577#L1643 assume !(0 != activate_threads_~tmp___4~0#1); 78207#L1643-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 78208#L754 assume 1 == ~t6_pc~0; 77962#L755 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 77858#L765 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 77859#L766 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 77831#L1651 assume !(0 != activate_threads_~tmp___5~0#1); 77832#L1651-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 78661#L773 assume !(1 == ~t7_pc~0); 77411#L773-2 is_transmit7_triggered_~__retres1~7#1 := 0; 77410#L784 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 78243#L785 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 78215#L1659 assume !(0 != activate_threads_~tmp___6~0#1); 78216#L1659-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 78263#L792 assume 1 == ~t8_pc~0; 78438#L793 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 78778#L803 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 78257#L804 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 78211#L1667 assume !(0 != activate_threads_~tmp___7~0#1); 78134#L1667-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 78135#L811 assume 1 == ~t9_pc~0; 78340#L812 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 78815#L822 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 78688#L823 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 78335#L1675 assume !(0 != activate_threads_~tmp___8~0#1); 78147#L1675-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 78148#L830 assume !(1 == ~t10_pc~0); 77870#L830-2 is_transmit10_triggered_~__retres1~10#1 := 0; 77390#L841 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 77083#L842 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 77084#L1683 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 77371#L1683-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 78679#L849 assume 1 == ~t11_pc~0; 78680#L850 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 77186#L860 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 77187#L861 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 77779#L1691 assume !(0 != activate_threads_~tmp___10~0#1); 78585#L1691-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 78586#L868 assume !(1 == ~t12_pc~0); 77993#L868-2 is_transmit12_triggered_~__retres1~12#1 := 0; 77992#L879 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 77786#L880 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 77787#L1699 assume !(0 != activate_threads_~tmp___11~0#1); 77422#L1699-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 77423#L887 assume 1 == ~t13_pc~0; 78598#L888 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 78034#L898 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 78035#L899 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 78473#L1707 assume !(0 != activate_threads_~tmp___12~0#1); 77126#L1707-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 77127#L1439 assume !(1 == ~M_E~0); 78205#L1439-2 assume !(1 == ~T1_E~0); 77298#L1444-1 assume !(1 == ~T2_E~0); 77299#L1449-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 77775#L1454-1 assume !(1 == ~T4_E~0); 77776#L1459-1 assume !(1 == ~T5_E~0); 78332#L1464-1 assume !(1 == ~T6_E~0); 78333#L1469-1 assume !(1 == ~T7_E~0); 78408#L1474-1 assume !(1 == ~T8_E~0); 78099#L1479-1 assume !(1 == ~T9_E~0); 78100#L1484-1 assume !(1 == ~T10_E~0); 78336#L1489-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 77984#L1494-1 assume !(1 == ~T12_E~0); 77985#L1499-1 assume !(1 == ~T13_E~0); 78175#L1504-1 assume !(1 == ~E_M~0); 78176#L1509-1 assume !(1 == ~E_1~0); 78760#L1514-1 assume !(1 == ~E_2~0); 78440#L1519-1 assume !(1 == ~E_3~0); 78441#L1524-1 assume !(1 == ~E_4~0); 78975#L1529-1 assume 1 == ~E_5~0;~E_5~0 := 2; 78976#L1534-1 assume !(1 == ~E_6~0); 77119#L1539-1 assume !(1 == ~E_7~0); 77120#L1544-1 assume !(1 == ~E_8~0); 77534#L1549-1 assume !(1 == ~E_9~0); 78950#L1554-1 assume !(1 == ~E_10~0); 78943#L1559-1 assume !(1 == ~E_11~0); 78799#L1564-1 assume !(1 == ~E_12~0); 78800#L1569-1 assume 1 == ~E_13~0;~E_13~0 := 2; 78971#L1574-1 assume { :end_inline_reset_delta_events } true; 77296#L1940-2 [2021-12-16 10:05:36,072 INFO L793 eck$LassoCheckResult]: Loop: 77296#L1940-2 assume !false; 77297#L1941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 77579#L1266 assume !false; 78606#L1075 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 77828#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 77560#L1064 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 77953#L1065 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 77954#L1079 assume !(0 != eval_~tmp~0#1); 77915#L1281 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 77916#L907-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 78524#L1291-3 assume !(0 == ~M_E~0); 78405#L1291-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 78406#L1296-3 assume !(0 == ~T2_E~0); 79004#L1301-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 78953#L1306-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 78063#L1311-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 77337#L1316-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 77338#L1321-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 77438#L1326-3 assume !(0 == ~T8_E~0); 78198#L1331-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 78447#L1336-3 assume !(0 == ~T10_E~0); 78448#L1341-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 77766#L1346-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 77746#L1351-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 77691#L1356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 77692#L1361-3 assume 0 == ~E_1~0;~E_1~0 := 1; 78255#L1366-3 assume !(0 == ~E_2~0); 77041#L1371-3 assume 0 == ~E_3~0;~E_3~0 := 1; 77042#L1376-3 assume !(0 == ~E_4~0); 78784#L1381-3 assume 0 == ~E_5~0;~E_5~0 := 1; 78641#L1386-3 assume 0 == ~E_6~0;~E_6~0 := 1; 78642#L1391-3 assume 0 == ~E_7~0;~E_7~0 := 1; 78807#L1396-3 assume 0 == ~E_8~0;~E_8~0 := 1; 78808#L1401-3 assume 0 == ~E_9~0;~E_9~0 := 1; 77406#L1406-3 assume 0 == ~E_10~0;~E_10~0 := 1; 77258#L1411-3 assume 0 == ~E_11~0;~E_11~0 := 1; 77259#L1416-3 assume !(0 == ~E_12~0); 77922#L1421-3 assume 0 == ~E_13~0;~E_13~0 := 1; 77923#L1426-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 78030#L640-45 assume 1 == ~m_pc~0; 78032#L641-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 77495#L651-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 77496#L652-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 77035#L1603-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 77036#L1603-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 77134#L659-45 assume !(1 == ~t1_pc~0); 77136#L659-47 is_transmit1_triggered_~__retres1~1#1 := 0; 77577#L670-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 78539#L671-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 78540#L1611-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 78561#L1611-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 78562#L678-45 assume 1 == ~t2_pc~0; 78505#L679-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 78036#L689-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 78037#L690-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 78190#L1619-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 78825#L1619-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 78952#L697-45 assume 1 == ~t3_pc~0; 78296#L698-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 78297#L708-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 78899#L709-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 78454#L1627-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 78455#L1627-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 78488#L716-45 assume 1 == ~t4_pc~0; 78116#L717-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 78117#L727-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 78674#L728-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 78122#L1635-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 78123#L1635-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 77780#L735-45 assume 1 == ~t5_pc~0; 77781#L736-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 78329#L746-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 78907#L747-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 78908#L1643-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 78974#L1643-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 78967#L754-45 assume 1 == ~t6_pc~0; 78277#L755-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 78278#L765-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 77705#L766-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 77706#L1651-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 78281#L1651-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 78012#L773-45 assume 1 == ~t7_pc~0; 78013#L774-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 77568#L784-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 78494#L785-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 78783#L1659-45 assume !(0 != activate_threads_~tmp___6~0#1); 78018#L1659-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 77687#L792-45 assume !(1 == ~t8_pc~0); 77689#L792-47 is_transmit8_triggered_~__retres1~8#1 := 0; 78726#L803-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 77289#L804-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 77148#L1667-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 77149#L1667-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 77645#L811-45 assume 1 == ~t9_pc~0; 77433#L812-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 77435#L822-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 78653#L823-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 78484#L1675-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 78090#L1675-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 77881#L830-45 assume !(1 == ~t10_pc~0); 77076#L830-47 is_transmit10_triggered_~__retres1~10#1 := 0; 77077#L841-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 78202#L842-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 77309#L1683-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 77310#L1683-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 77055#L849-45 assume 1 == ~t11_pc~0; 77057#L850-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 77515#L860-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 77146#L861-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 77043#L1691-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 77044#L1691-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 77302#L868-45 assume 1 == ~t12_pc~0; 77303#L869-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 77240#L879-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 77241#L880-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 78589#L1699-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 78847#L1699-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 78848#L887-45 assume 1 == ~t13_pc~0; 78673#L888-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 77312#L898-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 78601#L899-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 78964#L1707-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 77274#L1707-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 77275#L1439-3 assume !(1 == ~M_E~0); 78590#L1439-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 77294#L1444-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 77295#L1449-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 77452#L1454-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 78386#L1459-3 assume !(1 == ~T5_E~0); 78387#L1464-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 78850#L1469-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 78787#L1474-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 78788#L1479-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 78851#L1484-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 78069#L1489-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 78070#L1494-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 78716#L1499-3 assume !(1 == ~T13_E~0); 78347#L1504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 78348#L1509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 78796#L1514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 78826#L1519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 77989#L1524-3 assume 1 == ~E_4~0;~E_4~0 := 2; 77990#L1529-3 assume 1 == ~E_5~0;~E_5~0 := 2; 78872#L1534-3 assume 1 == ~E_6~0;~E_6~0 := 2; 78258#L1539-3 assume !(1 == ~E_7~0); 77732#L1544-3 assume 1 == ~E_8~0;~E_8~0 := 2; 77733#L1549-3 assume 1 == ~E_9~0;~E_9~0 := 2; 78229#L1554-3 assume 1 == ~E_10~0;~E_10~0 := 2; 77348#L1559-3 assume 1 == ~E_11~0;~E_11~0 := 2; 77349#L1564-3 assume 1 == ~E_12~0;~E_12~0 := 2; 78489#L1569-3 assume 1 == ~E_13~0;~E_13~0 := 2; 78490#L1574-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 77225#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 76996#L1064-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 77271#L1065-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 77232#L1959 assume !(0 == start_simulation_~tmp~3#1); 77234#L1959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 77266#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 77216#L1064-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 78531#L1065-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 78656#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 78870#L1921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 78885#L1922 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 78886#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 77296#L1940-2 [2021-12-16 10:05:36,073 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:36,073 INFO L85 PathProgramCache]: Analyzing trace with hash 1380038403, now seen corresponding path program 1 times [2021-12-16 10:05:36,073 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:36,073 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [513352788] [2021-12-16 10:05:36,073 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:36,073 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:36,084 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:36,110 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:05:36,110 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:36,110 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [513352788] [2021-12-16 10:05:36,110 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [513352788] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:36,110 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:36,110 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:05:36,111 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [996646902] [2021-12-16 10:05:36,111 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:36,111 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:05:36,111 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:36,111 INFO L85 PathProgramCache]: Analyzing trace with hash -579190055, now seen corresponding path program 1 times [2021-12-16 10:05:36,112 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:36,112 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [35008445] [2021-12-16 10:05:36,112 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:36,112 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:36,124 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:36,146 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:05:36,147 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:36,147 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [35008445] [2021-12-16 10:05:36,147 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [35008445] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:36,147 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:36,147 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:05:36,147 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1291983798] [2021-12-16 10:05:36,147 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:36,148 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:05:36,148 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:05:36,148 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-16 10:05:36,148 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-16 10:05:36,148 INFO L87 Difference]: Start difference. First operand 3771 states and 5540 transitions. cyclomatic complexity: 1770 Second operand has 4 states, 4 states have (on average 40.25) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:36,310 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:05:36,310 INFO L93 Difference]: Finished difference Result 5396 states and 7909 transitions. [2021-12-16 10:05:36,310 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-16 10:05:36,311 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5396 states and 7909 transitions. [2021-12-16 10:05:36,336 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 5216 [2021-12-16 10:05:36,354 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5396 states to 5396 states and 7909 transitions. [2021-12-16 10:05:36,354 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5396 [2021-12-16 10:05:36,359 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5396 [2021-12-16 10:05:36,360 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5396 states and 7909 transitions. [2021-12-16 10:05:36,367 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:05:36,367 INFO L681 BuchiCegarLoop]: Abstraction has 5396 states and 7909 transitions. [2021-12-16 10:05:36,372 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5396 states and 7909 transitions. [2021-12-16 10:05:36,471 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5396 to 3771. [2021-12-16 10:05:36,477 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3771 states, 3771 states have (on average 1.4683107928931318) internal successors, (5537), 3770 states have internal predecessors, (5537), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:36,485 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3771 states to 3771 states and 5537 transitions. [2021-12-16 10:05:36,486 INFO L704 BuchiCegarLoop]: Abstraction has 3771 states and 5537 transitions. [2021-12-16 10:05:36,486 INFO L587 BuchiCegarLoop]: Abstraction has 3771 states and 5537 transitions. [2021-12-16 10:05:36,486 INFO L425 BuchiCegarLoop]: ======== Iteration 18============ [2021-12-16 10:05:36,486 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3771 states and 5537 transitions. [2021-12-16 10:05:36,498 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3596 [2021-12-16 10:05:36,498 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:05:36,498 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:05:36,501 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:36,501 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:36,501 INFO L791 eck$LassoCheckResult]: Stem: 87088#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 87089#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 88095#L1903 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 88096#L907 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 88182#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 87554#L914-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 87020#L919-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 87021#L924-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 87844#L929-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 87845#L934-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 87945#L939-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 87946#L944-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 86795#L949-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 86796#L954-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 87975#L959-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 87331#L964-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 87332#L969-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 87895#L974-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 87234#L979-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 87235#L1291 assume !(0 == ~M_E~0); 88183#L1291-2 assume !(0 == ~T1_E~0); 88181#L1296-1 assume !(0 == ~T2_E~0); 87390#L1301-1 assume !(0 == ~T3_E~0); 87391#L1306-1 assume !(0 == ~T4_E~0); 87904#L1311-1 assume !(0 == ~T5_E~0); 86635#L1316-1 assume !(0 == ~T6_E~0); 86636#L1321-1 assume !(0 == ~T7_E~0); 87403#L1326-1 assume !(0 == ~T8_E~0); 86463#L1331-1 assume !(0 == ~T9_E~0); 86162#L1336-1 assume !(0 == ~T10_E~0); 86163#L1341-1 assume !(0 == ~T11_E~0); 86243#L1346-1 assume !(0 == ~T12_E~0); 86244#L1351-1 assume !(0 == ~T13_E~0); 86584#L1356-1 assume !(0 == ~E_M~0); 86585#L1361-1 assume !(0 == ~E_1~0); 88121#L1366-1 assume !(0 == ~E_2~0); 86625#L1371-1 assume !(0 == ~E_3~0); 86626#L1376-1 assume !(0 == ~E_4~0); 87450#L1381-1 assume !(0 == ~E_5~0); 87451#L1386-1 assume !(0 == ~E_6~0); 88151#L1391-1 assume !(0 == ~E_7~0); 88170#L1396-1 assume !(0 == ~E_8~0); 87363#L1401-1 assume !(0 == ~E_9~0); 87364#L1406-1 assume !(0 == ~E_10~0); 87642#L1411-1 assume !(0 == ~E_11~0); 87643#L1416-1 assume !(0 == ~E_12~0); 87275#L1421-1 assume !(0 == ~E_13~0); 86819#L1426-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 86820#L640 assume !(1 == ~m_pc~0); 87328#L640-2 is_master_triggered_~__retres1~0#1 := 0; 87327#L651 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 87419#L652 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 87313#L1603 assume !(0 != activate_threads_~tmp~1#1); 87314#L1603-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 86945#L659 assume 1 == ~t1_pc~0; 86946#L660 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 87052#L670 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 88004#L671 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 87072#L1611 assume !(0 != activate_threads_~tmp___0~0#1); 87073#L1611-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 87086#L678 assume 1 == ~t2_pc~0; 88047#L679 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 88048#L689 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 88148#L690 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 87185#L1619 assume !(0 != activate_threads_~tmp___1~0#1); 87186#L1619-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 87308#L697 assume !(1 == ~t3_pc~0); 87309#L697-2 is_transmit3_triggered_~__retres1~3#1 := 0; 87431#L708 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 87239#L709 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 87217#L1627 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 87218#L1627-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 88085#L716 assume 1 == ~t4_pc~0; 88071#L717 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 86928#L727 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 86929#L728 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 86426#L1635 assume !(0 != activate_threads_~tmp___3~0#1); 86427#L1635-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 87725#L735 assume !(1 == ~t5_pc~0); 86387#L735-2 is_transmit5_triggered_~__retres1~5#1 := 0; 86388#L746 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 86838#L747 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 87753#L1643 assume !(0 != activate_threads_~tmp___4~0#1); 87384#L1643-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 87385#L754 assume 1 == ~t6_pc~0; 87139#L755 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 87034#L765 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 87035#L766 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 87007#L1651 assume !(0 != activate_threads_~tmp___5~0#1); 87008#L1651-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 87834#L773 assume !(1 == ~t7_pc~0); 86588#L773-2 is_transmit7_triggered_~__retres1~7#1 := 0; 86587#L784 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 87420#L785 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 87392#L1659 assume !(0 != activate_threads_~tmp___6~0#1); 87393#L1659-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 87440#L792 assume 1 == ~t8_pc~0; 87615#L793 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 87949#L803 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 87434#L804 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 87388#L1667 assume !(0 != activate_threads_~tmp___7~0#1); 87311#L1667-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 87312#L811 assume 1 == ~t9_pc~0; 87517#L812 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 87986#L822 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 87861#L823 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 87512#L1675 assume !(0 != activate_threads_~tmp___8~0#1); 87324#L1675-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 87325#L830 assume !(1 == ~t10_pc~0); 87046#L830-2 is_transmit10_triggered_~__retres1~10#1 := 0; 86567#L841 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 86260#L842 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 86261#L1683 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 86548#L1683-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 87852#L849 assume 1 == ~t11_pc~0; 87853#L850 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 86363#L860 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 86364#L861 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 86955#L1691 assume !(0 != activate_threads_~tmp___10~0#1); 87760#L1691-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 87761#L868 assume !(1 == ~t12_pc~0); 87170#L868-2 is_transmit12_triggered_~__retres1~12#1 := 0; 87169#L879 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 86962#L880 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 86963#L1699 assume !(0 != activate_threads_~tmp___11~0#1); 86599#L1699-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 86600#L887 assume 1 == ~t13_pc~0; 87773#L888 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 87211#L898 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 87212#L899 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 87649#L1707 assume !(0 != activate_threads_~tmp___12~0#1); 86303#L1707-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 86304#L1439 assume !(1 == ~M_E~0); 87382#L1439-2 assume !(1 == ~T1_E~0); 86475#L1444-1 assume !(1 == ~T2_E~0); 86476#L1449-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 86951#L1454-1 assume !(1 == ~T4_E~0); 86952#L1459-1 assume !(1 == ~T5_E~0); 87509#L1464-1 assume !(1 == ~T6_E~0); 87510#L1469-1 assume !(1 == ~T7_E~0); 87585#L1474-1 assume !(1 == ~T8_E~0); 87276#L1479-1 assume !(1 == ~T9_E~0); 87277#L1484-1 assume !(1 == ~T10_E~0); 87513#L1489-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 87161#L1494-1 assume !(1 == ~T12_E~0); 87162#L1499-1 assume !(1 == ~T13_E~0); 87352#L1504-1 assume !(1 == ~E_M~0); 87353#L1509-1 assume !(1 == ~E_1~0); 87931#L1514-1 assume !(1 == ~E_2~0); 87617#L1519-1 assume !(1 == ~E_3~0); 87618#L1524-1 assume !(1 == ~E_4~0); 88134#L1529-1 assume 1 == ~E_5~0;~E_5~0 := 2; 88135#L1534-1 assume !(1 == ~E_6~0); 86296#L1539-1 assume !(1 == ~E_7~0); 86297#L1544-1 assume !(1 == ~E_8~0); 86711#L1549-1 assume !(1 == ~E_9~0); 88113#L1554-1 assume !(1 == ~E_10~0); 88106#L1559-1 assume !(1 == ~E_11~0); 87970#L1564-1 assume !(1 == ~E_12~0); 87971#L1569-1 assume 1 == ~E_13~0;~E_13~0 := 2; 88130#L1574-1 assume { :end_inline_reset_delta_events } true; 86473#L1940-2 [2021-12-16 10:05:36,502 INFO L793 eck$LassoCheckResult]: Loop: 86473#L1940-2 assume !false; 86474#L1941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 86756#L1266 assume !false; 87781#L1075 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 87004#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 86737#L1064 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 87132#L1065 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 87133#L1079 assume !(0 != eval_~tmp~0#1); 87091#L1281 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 87092#L907-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 87701#L1291-3 assume !(0 == ~M_E~0); 87582#L1291-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 87583#L1296-3 assume !(0 == ~T2_E~0); 88163#L1301-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 88116#L1306-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 87241#L1311-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 86514#L1316-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 86515#L1321-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 86615#L1326-3 assume !(0 == ~T8_E~0); 87375#L1331-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 87624#L1336-3 assume !(0 == ~T10_E~0); 87625#L1341-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 86942#L1346-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 86923#L1351-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 86867#L1356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 86868#L1361-3 assume 0 == ~E_1~0;~E_1~0 := 1; 87432#L1366-3 assume !(0 == ~E_2~0); 86218#L1371-3 assume 0 == ~E_3~0;~E_3~0 := 1; 86219#L1376-3 assume !(0 == ~E_4~0); 87955#L1381-3 assume 0 == ~E_5~0;~E_5~0 := 1; 87814#L1386-3 assume 0 == ~E_6~0;~E_6~0 := 1; 87815#L1391-3 assume 0 == ~E_7~0;~E_7~0 := 1; 87978#L1396-3 assume 0 == ~E_8~0;~E_8~0 := 1; 87979#L1401-3 assume 0 == ~E_9~0;~E_9~0 := 1; 86583#L1406-3 assume !(0 == ~E_10~0); 86435#L1411-3 assume 0 == ~E_11~0;~E_11~0 := 1; 86436#L1416-3 assume !(0 == ~E_12~0); 87098#L1421-3 assume 0 == ~E_13~0;~E_13~0 := 1; 87099#L1426-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 87205#L640-45 assume 1 == ~m_pc~0; 87207#L641-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 86672#L651-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 86673#L652-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 86212#L1603-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 86213#L1603-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 86308#L659-45 assume 1 == ~t1_pc~0; 86309#L660-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 86749#L670-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 87716#L671-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 87717#L1611-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 87738#L1611-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 87739#L678-45 assume !(1 == ~t2_pc~0); 87683#L678-47 is_transmit2_triggered_~__retres1~2#1 := 0; 87213#L689-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 87214#L690-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 87367#L1619-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 87996#L1619-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 88115#L697-45 assume 1 == ~t3_pc~0; 87472#L698-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 87473#L708-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 88066#L709-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 87631#L1627-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 87632#L1627-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 87662#L716-45 assume 1 == ~t4_pc~0; 87293#L717-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 87294#L727-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 87847#L728-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 87296#L1635-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 87297#L1635-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 86959#L735-45 assume !(1 == ~t5_pc~0); 86961#L735-47 is_transmit5_triggered_~__retres1~5#1 := 0; 87506#L746-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 88074#L747-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 88075#L1643-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 88133#L1643-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 88128#L754-45 assume !(1 == ~t6_pc~0); 87456#L754-47 is_transmit6_triggered_~__retres1~6#1 := 0; 87455#L765-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 86881#L766-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 86882#L1651-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 87458#L1651-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 87189#L773-45 assume 1 == ~t7_pc~0; 87190#L774-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 86745#L784-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 87670#L785-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 87954#L1659-45 assume !(0 != activate_threads_~tmp___6~0#1); 87195#L1659-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 86863#L792-45 assume !(1 == ~t8_pc~0); 86865#L792-47 is_transmit8_triggered_~__retres1~8#1 := 0; 87898#L803-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 86466#L804-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 86325#L1667-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 86326#L1667-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 86821#L811-45 assume !(1 == ~t9_pc~0); 86611#L811-47 is_transmit9_triggered_~__retres1~9#1 := 0; 86612#L822-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 87826#L823-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 87658#L1675-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 87267#L1675-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 87057#L830-45 assume 1 == ~t10_pc~0; 87058#L831-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 86254#L841-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 87379#L842-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 86486#L1683-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 86487#L1683-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 86232#L849-45 assume !(1 == ~t11_pc~0); 86233#L849-47 is_transmit11_triggered_~__retres1~11#1 := 0; 86692#L860-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 86323#L861-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 86220#L1691-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 86221#L1691-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 86479#L868-45 assume !(1 == ~t12_pc~0); 86481#L868-47 is_transmit12_triggered_~__retres1~12#1 := 0; 86419#L879-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 86420#L880-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 87764#L1699-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 88016#L1699-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 88017#L887-45 assume 1 == ~t13_pc~0; 87846#L888-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 86489#L898-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 87776#L899-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 88125#L1707-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 86451#L1707-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 86452#L1439-3 assume !(1 == ~M_E~0); 87765#L1439-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 86471#L1444-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 86472#L1449-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 86629#L1454-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 87563#L1459-3 assume !(1 == ~T5_E~0); 87564#L1464-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 88019#L1469-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 87958#L1474-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 87959#L1479-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 88020#L1484-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 87246#L1489-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 87247#L1494-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 87888#L1499-3 assume !(1 == ~T13_E~0); 87524#L1504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 87525#L1509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 87967#L1514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 87997#L1519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 87166#L1524-3 assume 1 == ~E_4~0;~E_4~0 := 2; 87167#L1529-3 assume 1 == ~E_5~0;~E_5~0 := 2; 88040#L1534-3 assume 1 == ~E_6~0;~E_6~0 := 2; 87435#L1539-3 assume !(1 == ~E_7~0); 86908#L1544-3 assume 1 == ~E_8~0;~E_8~0 := 2; 86909#L1549-3 assume 1 == ~E_9~0;~E_9~0 := 2; 87406#L1554-3 assume 1 == ~E_10~0;~E_10~0 := 2; 86525#L1559-3 assume 1 == ~E_11~0;~E_11~0 := 2; 86526#L1564-3 assume 1 == ~E_12~0;~E_12~0 := 2; 87663#L1569-3 assume 1 == ~E_13~0;~E_13~0 := 2; 87664#L1574-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 86402#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 86173#L1064-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 86448#L1065-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 86409#L1959 assume !(0 == start_simulation_~tmp~3#1); 86411#L1959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 86443#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 86393#L1064-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 87708#L1065-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 87829#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 88038#L1921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 88052#L1922 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 88053#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 86473#L1940-2 [2021-12-16 10:05:36,502 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:36,503 INFO L85 PathProgramCache]: Analyzing trace with hash -462437311, now seen corresponding path program 1 times [2021-12-16 10:05:36,503 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:36,503 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [540589873] [2021-12-16 10:05:36,503 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:36,503 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:36,516 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:36,535 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:05:36,535 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:36,535 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [540589873] [2021-12-16 10:05:36,535 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [540589873] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:36,536 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:36,536 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-16 10:05:36,536 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1955042093] [2021-12-16 10:05:36,536 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:36,537 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:05:36,537 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:36,537 INFO L85 PathProgramCache]: Analyzing trace with hash 1680827291, now seen corresponding path program 1 times [2021-12-16 10:05:36,537 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:36,537 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1881717278] [2021-12-16 10:05:36,538 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:36,538 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:36,550 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:36,573 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:05:36,573 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:36,573 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1881717278] [2021-12-16 10:05:36,573 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1881717278] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:36,573 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:36,574 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:05:36,574 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1327646550] [2021-12-16 10:05:36,574 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:36,575 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:05:36,575 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:05:36,575 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-16 10:05:36,576 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-16 10:05:36,576 INFO L87 Difference]: Start difference. First operand 3771 states and 5537 transitions. cyclomatic complexity: 1767 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 2 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:36,686 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:05:36,687 INFO L93 Difference]: Finished difference Result 7133 states and 10422 transitions. [2021-12-16 10:05:36,687 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-16 10:05:36,688 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7133 states and 10422 transitions. [2021-12-16 10:05:36,720 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 6957 [2021-12-16 10:05:36,746 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7133 states to 7133 states and 10422 transitions. [2021-12-16 10:05:36,746 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7133 [2021-12-16 10:05:36,754 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7133 [2021-12-16 10:05:36,754 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7133 states and 10422 transitions. [2021-12-16 10:05:36,763 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:05:36,763 INFO L681 BuchiCegarLoop]: Abstraction has 7133 states and 10422 transitions. [2021-12-16 10:05:36,769 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7133 states and 10422 transitions. [2021-12-16 10:05:36,859 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7133 to 7129. [2021-12-16 10:05:36,868 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7129 states, 7129 states have (on average 1.4613550287557862) internal successors, (10418), 7128 states have internal predecessors, (10418), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:36,885 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7129 states to 7129 states and 10418 transitions. [2021-12-16 10:05:36,886 INFO L704 BuchiCegarLoop]: Abstraction has 7129 states and 10418 transitions. [2021-12-16 10:05:36,886 INFO L587 BuchiCegarLoop]: Abstraction has 7129 states and 10418 transitions. [2021-12-16 10:05:36,886 INFO L425 BuchiCegarLoop]: ======== Iteration 19============ [2021-12-16 10:05:36,886 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7129 states and 10418 transitions. [2021-12-16 10:05:36,910 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 6953 [2021-12-16 10:05:36,910 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:05:36,910 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:05:36,913 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:36,913 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:36,913 INFO L791 eck$LassoCheckResult]: Stem: 98008#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 98009#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 99084#L1903 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 99085#L907 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 99213#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 98488#L914-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 97939#L919-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 97940#L924-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 98798#L929-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 98799#L934-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 98916#L939-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 98917#L944-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 97707#L949-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 97708#L954-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 98947#L959-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 98252#L964-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 98253#L969-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 98862#L974-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 98155#L979-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 98156#L1291 assume !(0 == ~M_E~0); 99214#L1291-2 assume !(0 == ~T1_E~0); 99212#L1296-1 assume !(0 == ~T2_E~0); 98313#L1301-1 assume !(0 == ~T3_E~0); 98314#L1306-1 assume !(0 == ~T4_E~0); 98870#L1311-1 assume !(0 == ~T5_E~0); 97550#L1316-1 assume !(0 == ~T6_E~0); 97551#L1321-1 assume !(0 == ~T7_E~0); 98326#L1326-1 assume !(0 == ~T8_E~0); 97376#L1331-1 assume !(0 == ~T9_E~0); 97073#L1336-1 assume !(0 == ~T10_E~0); 97074#L1341-1 assume !(0 == ~T11_E~0); 97154#L1346-1 assume !(0 == ~T12_E~0); 97155#L1351-1 assume !(0 == ~T13_E~0); 97496#L1356-1 assume !(0 == ~E_M~0); 97497#L1361-1 assume !(0 == ~E_1~0); 99123#L1366-1 assume !(0 == ~E_2~0); 97540#L1371-1 assume !(0 == ~E_3~0); 97541#L1376-1 assume !(0 == ~E_4~0); 98378#L1381-1 assume !(0 == ~E_5~0); 98379#L1386-1 assume !(0 == ~E_6~0); 99168#L1391-1 assume !(0 == ~E_7~0); 99192#L1396-1 assume !(0 == ~E_8~0); 98284#L1401-1 assume !(0 == ~E_9~0); 98285#L1406-1 assume !(0 == ~E_10~0); 98579#L1411-1 assume !(0 == ~E_11~0); 98580#L1416-1 assume !(0 == ~E_12~0); 98197#L1421-1 assume !(0 == ~E_13~0); 97730#L1426-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 97731#L640 assume !(1 == ~m_pc~0); 98249#L640-2 is_master_triggered_~__retres1~0#1 := 0; 98248#L651 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 98343#L652 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 98234#L1603 assume !(0 != activate_threads_~tmp~1#1); 98235#L1603-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 97866#L659 assume !(1 == ~t1_pc~0); 97867#L659-2 is_transmit1_triggered_~__retres1~1#1 := 0; 99011#L670 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 98980#L671 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 97992#L1611 assume !(0 != activate_threads_~tmp___0~0#1); 97993#L1611-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 98006#L678 assume 1 == ~t2_pc~0; 99030#L679 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 99031#L689 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 99164#L690 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 98106#L1619 assume !(0 != activate_threads_~tmp___1~0#1); 98107#L1619-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 98229#L697 assume !(1 == ~t3_pc~0); 98230#L697-2 is_transmit3_triggered_~__retres1~3#1 := 0; 98359#L708 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 98161#L709 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 98140#L1627 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 98141#L1627-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 99074#L716 assume 1 == ~t4_pc~0; 99059#L717 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 97846#L727 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 97847#L728 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 97338#L1635 assume !(0 != activate_threads_~tmp___3~0#1); 97339#L1635-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 98664#L735 assume !(1 == ~t5_pc~0); 97299#L735-2 is_transmit5_triggered_~__retres1~5#1 := 0; 97300#L746 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 97755#L747 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 98693#L1643 assume !(0 != activate_threads_~tmp___4~0#1); 98307#L1643-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 98308#L754 assume 1 == ~t6_pc~0; 98058#L755 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 97954#L765 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 97955#L766 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 97926#L1651 assume !(0 != activate_threads_~tmp___5~0#1); 97927#L1651-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 98787#L773 assume !(1 == ~t7_pc~0); 97500#L773-2 is_transmit7_triggered_~__retres1~7#1 := 0; 97499#L784 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 98344#L785 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 98315#L1659 assume !(0 != activate_threads_~tmp___6~0#1); 98316#L1659-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 98368#L792 assume 1 == ~t8_pc~0; 98549#L793 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 98920#L803 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 98362#L804 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 98310#L1667 assume !(0 != activate_threads_~tmp___7~0#1); 98232#L1667-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 98233#L811 assume 1 == ~t9_pc~0; 98446#L812 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 98959#L822 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 98816#L823 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 98442#L1675 assume !(0 != activate_threads_~tmp___8~0#1); 98245#L1675-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 98246#L830 assume !(1 == ~t10_pc~0); 97964#L830-2 is_transmit10_triggered_~__retres1~10#1 := 0; 97479#L841 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 97172#L842 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 97173#L1683 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 97461#L1683-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 98807#L849 assume 1 == ~t11_pc~0; 98808#L850 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 97275#L860 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 97276#L861 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 97873#L1691 assume !(0 != activate_threads_~tmp___10~0#1); 98700#L1691-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 98701#L868 assume !(1 == ~t12_pc~0); 98091#L868-2 is_transmit12_triggered_~__retres1~12#1 := 0; 98090#L879 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 97882#L880 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 97883#L1699 assume !(0 != activate_threads_~tmp___11~0#1); 97513#L1699-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 97514#L887 assume 1 == ~t13_pc~0; 98717#L888 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 98134#L898 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 98135#L899 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 98588#L1707 assume !(0 != activate_threads_~tmp___12~0#1); 97215#L1707-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 97216#L1439 assume !(1 == ~M_E~0); 98303#L1439-2 assume !(1 == ~T1_E~0); 97388#L1444-1 assume !(1 == ~T2_E~0); 97389#L1449-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 97869#L1454-1 assume !(1 == ~T4_E~0); 97870#L1459-1 assume !(1 == ~T5_E~0); 98439#L1464-1 assume !(1 == ~T6_E~0); 98440#L1469-1 assume !(1 == ~T7_E~0); 98516#L1474-1 assume !(1 == ~T8_E~0); 98198#L1479-1 assume !(1 == ~T9_E~0); 98199#L1484-1 assume !(1 == ~T10_E~0); 98443#L1489-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 98079#L1494-1 assume !(1 == ~T12_E~0); 98080#L1499-1 assume !(1 == ~T13_E~0); 98273#L1504-1 assume !(1 == ~E_M~0); 98274#L1509-1 assume !(1 == ~E_1~0); 98902#L1514-1 assume !(1 == ~E_2~0); 98551#L1519-1 assume !(1 == ~E_3~0); 98552#L1524-1 assume !(1 == ~E_4~0); 99144#L1529-1 assume 1 == ~E_5~0;~E_5~0 := 2; 99145#L1534-1 assume !(1 == ~E_6~0); 97208#L1539-1 assume !(1 == ~E_7~0); 97209#L1544-1 assume !(1 == ~E_8~0); 97627#L1549-1 assume !(1 == ~E_9~0); 99102#L1554-1 assume !(1 == ~E_10~0); 99098#L1559-1 assume !(1 == ~E_11~0); 98942#L1564-1 assume !(1 == ~E_12~0); 98943#L1569-1 assume 1 == ~E_13~0;~E_13~0 := 2; 99138#L1574-1 assume { :end_inline_reset_delta_events } true; 99175#L1940-2 [2021-12-16 10:05:36,914 INFO L793 eck$LassoCheckResult]: Loop: 99175#L1940-2 assume !false; 99944#L1941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 99940#L1266 assume !false; 99935#L1075 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 99936#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 99442#L1064 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 99443#L1065 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 99356#L1079 assume !(0 != eval_~tmp~0#1); 99358#L1281 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 100347#L907-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 100345#L1291-3 assume !(0 == ~M_E~0); 100343#L1291-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 100341#L1296-3 assume !(0 == ~T2_E~0); 100339#L1301-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 100337#L1306-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 100335#L1311-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 100333#L1316-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 100331#L1321-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 100329#L1326-3 assume !(0 == ~T8_E~0); 100327#L1331-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 100325#L1336-3 assume !(0 == ~T10_E~0); 100323#L1341-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 100321#L1346-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 100319#L1351-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 100317#L1356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 100315#L1361-3 assume 0 == ~E_1~0;~E_1~0 := 1; 100313#L1366-3 assume !(0 == ~E_2~0); 100311#L1371-3 assume 0 == ~E_3~0;~E_3~0 := 1; 100309#L1376-3 assume !(0 == ~E_4~0); 100307#L1381-3 assume 0 == ~E_5~0;~E_5~0 := 1; 100305#L1386-3 assume 0 == ~E_6~0;~E_6~0 := 1; 100303#L1391-3 assume 0 == ~E_7~0;~E_7~0 := 1; 100301#L1396-3 assume 0 == ~E_8~0;~E_8~0 := 1; 100299#L1401-3 assume 0 == ~E_9~0;~E_9~0 := 1; 100297#L1406-3 assume !(0 == ~E_10~0); 100295#L1411-3 assume 0 == ~E_11~0;~E_11~0 := 1; 100293#L1416-3 assume !(0 == ~E_12~0); 100291#L1421-3 assume 0 == ~E_13~0;~E_13~0 := 1; 100289#L1426-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 100287#L640-45 assume !(1 == ~m_pc~0); 100285#L640-47 is_master_triggered_~__retres1~0#1 := 0; 100281#L651-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 100279#L652-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 100277#L1603-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 100275#L1603-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 100273#L659-45 assume !(1 == ~t1_pc~0); 100271#L659-47 is_transmit1_triggered_~__retres1~1#1 := 0; 100269#L670-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 100267#L671-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 100265#L1611-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 100263#L1611-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 100261#L678-45 assume 1 == ~t2_pc~0; 100259#L679-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 100255#L689-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 100253#L690-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 100251#L1619-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 100249#L1619-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 100247#L697-45 assume !(1 == ~t3_pc~0); 100245#L697-47 is_transmit3_triggered_~__retres1~3#1 := 0; 100241#L708-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 100239#L709-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 100237#L1627-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 100235#L1627-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 100233#L716-45 assume 1 == ~t4_pc~0; 100231#L717-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 100227#L727-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 100225#L728-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 100223#L1635-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 100221#L1635-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 100219#L735-45 assume !(1 == ~t5_pc~0); 100217#L735-47 is_transmit5_triggered_~__retres1~5#1 := 0; 100213#L746-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 100211#L747-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 100209#L1643-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 100207#L1643-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 100205#L754-45 assume 1 == ~t6_pc~0; 100203#L755-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 100199#L765-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 100197#L766-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 100195#L1651-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 100193#L1651-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 100191#L773-45 assume !(1 == ~t7_pc~0); 100189#L773-47 is_transmit7_triggered_~__retres1~7#1 := 0; 100185#L784-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 100183#L785-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 100181#L1659-45 assume !(0 != activate_threads_~tmp___6~0#1); 100179#L1659-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 100177#L792-45 assume !(1 == ~t8_pc~0); 100175#L792-47 is_transmit8_triggered_~__retres1~8#1 := 0; 100171#L803-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 100169#L804-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 100167#L1667-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 100165#L1667-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 100163#L811-45 assume 1 == ~t9_pc~0; 100161#L812-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 100157#L822-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 100155#L823-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 100153#L1675-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 100151#L1675-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 100149#L830-45 assume !(1 == ~t10_pc~0); 100147#L830-47 is_transmit10_triggered_~__retres1~10#1 := 0; 100143#L841-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 100141#L842-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 100139#L1683-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 100137#L1683-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 100135#L849-45 assume 1 == ~t11_pc~0; 100133#L850-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 100129#L860-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 100127#L861-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 100125#L1691-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 100123#L1691-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 100121#L868-45 assume !(1 == ~t12_pc~0); 100119#L868-47 is_transmit12_triggered_~__retres1~12#1 := 0; 100115#L879-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 100113#L880-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 100111#L1699-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 100109#L1699-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 100107#L887-45 assume 1 == ~t13_pc~0; 100105#L888-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 100101#L898-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 100099#L899-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 100097#L1707-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 100095#L1707-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 100093#L1439-3 assume !(1 == ~M_E~0); 100089#L1439-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 100087#L1444-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 100083#L1449-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 100080#L1454-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 100078#L1459-3 assume !(1 == ~T5_E~0); 100076#L1464-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 100074#L1469-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 100071#L1474-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 100067#L1479-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 100064#L1484-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 100062#L1489-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 100060#L1494-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 100058#L1499-3 assume !(1 == ~T13_E~0); 100056#L1504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 100052#L1509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 100049#L1514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 100047#L1519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 100045#L1524-3 assume 1 == ~E_4~0;~E_4~0 := 2; 100042#L1529-3 assume 1 == ~E_5~0;~E_5~0 := 2; 100043#L1534-3 assume 1 == ~E_6~0;~E_6~0 := 2; 101937#L1539-3 assume !(1 == ~E_7~0); 101935#L1544-3 assume 1 == ~E_8~0;~E_8~0 := 2; 101932#L1549-3 assume 1 == ~E_9~0;~E_9~0 := 2; 101930#L1554-3 assume 1 == ~E_10~0;~E_10~0 := 2; 101928#L1559-3 assume 1 == ~E_11~0;~E_11~0 := 2; 101926#L1564-3 assume 1 == ~E_12~0;~E_12~0 := 2; 101924#L1569-3 assume 1 == ~E_13~0;~E_13~0 := 2; 101922#L1574-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 101911#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 101897#L1064-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 101895#L1065-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 99994#L1959 assume !(0 == start_simulation_~tmp~3#1); 99993#L1959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 99980#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 99965#L1064-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 99966#L1065-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 100555#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 99955#L1921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 99956#L1922 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 99948#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 99175#L1940-2 [2021-12-16 10:05:36,914 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:36,914 INFO L85 PathProgramCache]: Analyzing trace with hash 908624450, now seen corresponding path program 1 times [2021-12-16 10:05:36,915 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:36,915 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1785130333] [2021-12-16 10:05:36,915 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:36,915 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:36,926 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:37,012 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:05:37,013 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:37,013 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1785130333] [2021-12-16 10:05:37,013 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1785130333] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:37,013 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:37,013 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:05:37,014 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1105120222] [2021-12-16 10:05:37,014 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:37,015 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:05:37,017 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:37,017 INFO L85 PathProgramCache]: Analyzing trace with hash -2113428964, now seen corresponding path program 1 times [2021-12-16 10:05:37,017 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:37,017 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [248554667] [2021-12-16 10:05:37,017 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:37,018 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:37,031 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:37,061 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:05:37,062 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:37,062 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [248554667] [2021-12-16 10:05:37,062 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [248554667] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:37,062 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:37,062 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:05:37,062 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [435889739] [2021-12-16 10:05:37,063 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:37,064 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:05:37,064 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:05:37,064 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-16 10:05:37,065 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-16 10:05:37,065 INFO L87 Difference]: Start difference. First operand 7129 states and 10418 transitions. cyclomatic complexity: 3291 Second operand has 4 states, 4 states have (on average 40.25) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:37,328 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:05:37,329 INFO L93 Difference]: Finished difference Result 17093 states and 24821 transitions. [2021-12-16 10:05:37,329 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-16 10:05:37,330 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 17093 states and 24821 transitions. [2021-12-16 10:05:37,423 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 16902 [2021-12-16 10:05:37,495 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 17093 states to 17093 states and 24821 transitions. [2021-12-16 10:05:37,495 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 17093 [2021-12-16 10:05:37,518 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 17093 [2021-12-16 10:05:37,519 INFO L73 IsDeterministic]: Start isDeterministic. Operand 17093 states and 24821 transitions. [2021-12-16 10:05:37,539 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:05:37,540 INFO L681 BuchiCegarLoop]: Abstraction has 17093 states and 24821 transitions. [2021-12-16 10:05:37,553 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17093 states and 24821 transitions. [2021-12-16 10:05:37,744 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17093 to 13617. [2021-12-16 10:05:37,764 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 13617 states, 13617 states have (on average 1.4555335242711316) internal successors, (19820), 13616 states have internal predecessors, (19820), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:37,800 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13617 states to 13617 states and 19820 transitions. [2021-12-16 10:05:37,801 INFO L704 BuchiCegarLoop]: Abstraction has 13617 states and 19820 transitions. [2021-12-16 10:05:37,801 INFO L587 BuchiCegarLoop]: Abstraction has 13617 states and 19820 transitions. [2021-12-16 10:05:37,801 INFO L425 BuchiCegarLoop]: ======== Iteration 20============ [2021-12-16 10:05:37,801 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 13617 states and 19820 transitions. [2021-12-16 10:05:37,853 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 13440 [2021-12-16 10:05:37,853 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:05:37,853 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:05:37,856 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:37,856 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:37,857 INFO L791 eck$LassoCheckResult]: Stem: 122246#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 122247#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 123405#L1903 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 123406#L907 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 123560#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 122741#L914-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 122175#L919-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 122176#L924-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 123066#L929-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 123067#L934-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 123194#L939-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 123195#L944-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 121940#L949-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 121941#L954-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 123228#L959-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 122501#L964-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 122502#L969-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 123129#L974-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 122398#L979-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 122399#L1291 assume !(0 == ~M_E~0); 123561#L1291-2 assume !(0 == ~T1_E~0); 123558#L1296-1 assume !(0 == ~T2_E~0); 122568#L1301-1 assume !(0 == ~T3_E~0); 122569#L1306-1 assume !(0 == ~T4_E~0); 123143#L1311-1 assume !(0 == ~T5_E~0); 121784#L1316-1 assume !(0 == ~T6_E~0); 121785#L1321-1 assume !(0 == ~T7_E~0); 122581#L1326-1 assume !(0 == ~T8_E~0); 121604#L1331-1 assume !(0 == ~T9_E~0); 121305#L1336-1 assume !(0 == ~T10_E~0); 121306#L1341-1 assume !(0 == ~T11_E~0); 121386#L1346-1 assume !(0 == ~T12_E~0); 121387#L1351-1 assume !(0 == ~T13_E~0); 121729#L1356-1 assume !(0 == ~E_M~0); 121730#L1361-1 assume !(0 == ~E_1~0); 123456#L1366-1 assume !(0 == ~E_2~0); 121774#L1371-1 assume !(0 == ~E_3~0); 121775#L1376-1 assume !(0 == ~E_4~0); 122631#L1381-1 assume !(0 == ~E_5~0); 122632#L1386-1 assume !(0 == ~E_6~0); 123509#L1391-1 assume !(0 == ~E_7~0); 123536#L1396-1 assume !(0 == ~E_8~0); 122533#L1401-1 assume !(0 == ~E_9~0); 122534#L1406-1 assume !(0 == ~E_10~0); 122833#L1411-1 assume !(0 == ~E_11~0); 122834#L1416-1 assume !(0 == ~E_12~0); 122441#L1421-1 assume !(0 == ~E_13~0); 121963#L1426-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 121964#L640 assume !(1 == ~m_pc~0); 122498#L640-2 is_master_triggered_~__retres1~0#1 := 0; 122497#L651 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 122596#L652 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 122483#L1603 assume !(0 != activate_threads_~tmp~1#1); 122484#L1603-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 122100#L659 assume !(1 == ~t1_pc~0); 122101#L659-2 is_transmit1_triggered_~__retres1~1#1 := 0; 123295#L670 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 123262#L671 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 122229#L1611 assume !(0 != activate_threads_~tmp___0~0#1); 122230#L1611-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 122244#L678 assume !(1 == ~t2_pc~0); 123432#L678-2 is_transmit2_triggered_~__retres1~2#1 := 0; 123504#L689 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 123505#L690 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 122345#L1619 assume !(0 != activate_threads_~tmp___1~0#1); 122346#L1619-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 122478#L697 assume !(1 == ~t3_pc~0); 122479#L697-2 is_transmit3_triggered_~__retres1~3#1 := 0; 122612#L708 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 122404#L709 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 122382#L1627 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 122383#L1627-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 123386#L716 assume 1 == ~t4_pc~0; 123365#L717 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 122079#L727 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 122080#L728 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 121567#L1635 assume !(0 != activate_threads_~tmp___3~0#1); 121568#L1635-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 122926#L735 assume !(1 == ~t5_pc~0); 121528#L735-2 is_transmit5_triggered_~__retres1~5#1 := 0; 121529#L746 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 121989#L747 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 122955#L1643 assume !(0 != activate_threads_~tmp___4~0#1); 122557#L1643-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 122558#L754 assume 1 == ~t6_pc~0; 122295#L755 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 122191#L765 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 122192#L766 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 122162#L1651 assume !(0 != activate_threads_~tmp___5~0#1); 122163#L1651-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 123056#L773 assume !(1 == ~t7_pc~0); 121733#L773-2 is_transmit7_triggered_~__retres1~7#1 := 0; 121732#L784 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 122597#L785 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 122570#L1659 assume !(0 != activate_threads_~tmp___6~0#1); 122571#L1659-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 122621#L792 assume 1 == ~t8_pc~0; 122801#L793 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 123198#L803 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 122615#L804 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 122560#L1667 assume !(0 != activate_threads_~tmp___7~0#1); 122481#L1667-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 122482#L811 assume 1 == ~t9_pc~0; 122701#L812 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 123239#L822 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 123085#L823 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 122697#L1675 assume !(0 != activate_threads_~tmp___8~0#1); 122494#L1675-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 122495#L830 assume !(1 == ~t10_pc~0); 122201#L830-2 is_transmit10_triggered_~__retres1~10#1 := 0; 121712#L841 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 121403#L842 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 121404#L1683 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 121694#L1683-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 123076#L849 assume 1 == ~t11_pc~0; 123077#L850 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 121504#L860 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 121505#L861 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 122108#L1691 assume !(0 != activate_threads_~tmp___10~0#1); 122964#L1691-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 122965#L868 assume !(1 == ~t12_pc~0); 122329#L868-2 is_transmit12_triggered_~__retres1~12#1 := 0; 122328#L879 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 122117#L880 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 122118#L1699 assume !(0 != activate_threads_~tmp___11~0#1); 121748#L1699-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 121749#L887 assume 1 == ~t13_pc~0; 122980#L888 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 122376#L898 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 122377#L899 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 122842#L1707 assume !(0 != activate_threads_~tmp___12~0#1); 121446#L1707-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 121447#L1439 assume !(1 == ~M_E~0); 122553#L1439-2 assume !(1 == ~T1_E~0); 121617#L1444-1 assume !(1 == ~T2_E~0); 121618#L1449-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 122104#L1454-1 assume !(1 == ~T4_E~0); 122105#L1459-1 assume !(1 == ~T5_E~0); 122694#L1464-1 assume !(1 == ~T6_E~0); 122695#L1469-1 assume !(1 == ~T7_E~0); 122770#L1474-1 assume !(1 == ~T8_E~0); 122442#L1479-1 assume !(1 == ~T9_E~0); 122443#L1484-1 assume !(1 == ~T10_E~0); 122698#L1489-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 122317#L1494-1 assume !(1 == ~T12_E~0); 122318#L1499-1 assume !(1 == ~T13_E~0); 122522#L1504-1 assume !(1 == ~E_M~0); 122523#L1509-1 assume !(1 == ~E_1~0); 123178#L1514-1 assume !(1 == ~E_2~0); 122803#L1519-1 assume !(1 == ~E_3~0); 122804#L1524-1 assume !(1 == ~E_4~0); 123485#L1529-1 assume 1 == ~E_5~0;~E_5~0 := 2; 123486#L1534-1 assume !(1 == ~E_6~0); 121439#L1539-1 assume !(1 == ~E_7~0); 121440#L1544-1 assume !(1 == ~E_8~0); 121860#L1549-1 assume !(1 == ~E_9~0); 123423#L1554-1 assume !(1 == ~E_10~0); 123420#L1559-1 assume !(1 == ~E_11~0); 123223#L1564-1 assume !(1 == ~E_12~0); 123224#L1569-1 assume 1 == ~E_13~0;~E_13~0 := 2; 123475#L1574-1 assume { :end_inline_reset_delta_events } true; 123518#L1940-2 [2021-12-16 10:05:37,857 INFO L793 eck$LassoCheckResult]: Loop: 123518#L1940-2 assume !false; 133328#L1941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 122989#L1266 assume !false; 122990#L1075 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 122158#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 121886#L1064 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 133308#L1065 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 123183#L1079 assume !(0 != eval_~tmp~0#1); 122249#L1281 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 122250#L907-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 133305#L1291-3 assume !(0 == ~M_E~0); 133304#L1291-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 133303#L1296-3 assume !(0 == ~T2_E~0); 133302#L1301-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 123439#L1306-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 122406#L1311-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 121657#L1316-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 121658#L1321-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 121764#L1326-3 assume !(0 == ~T8_E~0); 122547#L1331-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 133297#L1336-3 assume !(0 == ~T10_E~0); 123353#L1341-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 123354#L1346-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 133296#L1351-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 133295#L1356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 133294#L1361-3 assume 0 == ~E_1~0;~E_1~0 := 1; 133293#L1366-3 assume !(0 == ~E_2~0); 133292#L1371-3 assume 0 == ~E_3~0;~E_3~0 := 1; 123205#L1376-3 assume !(0 == ~E_4~0); 123206#L1381-3 assume 0 == ~E_5~0;~E_5~0 := 1; 123031#L1386-3 assume 0 == ~E_6~0;~E_6~0 := 1; 123032#L1391-3 assume 0 == ~E_7~0;~E_7~0 := 1; 123492#L1396-3 assume 0 == ~E_8~0;~E_8~0 := 1; 133290#L1401-3 assume 0 == ~E_9~0;~E_9~0 := 1; 133289#L1406-3 assume !(0 == ~E_10~0); 133288#L1411-3 assume 0 == ~E_11~0;~E_11~0 := 1; 133287#L1416-3 assume !(0 == ~E_12~0); 133286#L1421-3 assume 0 == ~E_13~0;~E_13~0 := 1; 123065#L1426-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 122372#L640-45 assume !(1 == ~m_pc~0); 122373#L640-47 is_master_triggered_~__retres1~0#1 := 0; 133284#L651-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 133283#L652-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 133282#L1603-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 133281#L1603-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 133280#L659-45 assume !(1 == ~t1_pc~0); 133279#L659-47 is_transmit1_triggered_~__retres1~1#1 := 0; 123531#L670-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 122919#L671-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 122920#L1611-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 133277#L1611-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 123378#L678-45 assume !(1 == ~t2_pc~0); 122904#L678-47 is_transmit2_triggered_~__retres1~2#1 := 0; 122905#L689-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 133276#L690-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 123253#L1619-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 123254#L1619-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 123436#L697-45 assume 1 == ~t3_pc~0; 123437#L698-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 133275#L708-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 123359#L709-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 122821#L1627-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 122822#L1627-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 122859#L716-45 assume !(1 == ~t4_pc~0); 123587#L716-47 is_transmit4_triggered_~__retres1~4#1 := 0; 133271#L727-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 123070#L728-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 122467#L1635-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 122468#L1635-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 133269#L735-45 assume 1 == ~t5_pc~0; 122689#L736-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 122690#L746-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 123369#L747-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 123370#L1643-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 123552#L1643-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 123469#L754-45 assume !(1 == ~t6_pc~0); 123471#L754-47 is_transmit6_triggered_~__retres1~6#1 := 0; 133267#L765-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 133266#L766-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 133265#L1651-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 122640#L1651-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 122350#L773-45 assume 1 == ~t7_pc~0; 122352#L774-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 133263#L784-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 123203#L785-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 123204#L1659-45 assume !(0 != activate_threads_~tmp___6~0#1); 122357#L1659-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 122014#L792-45 assume !(1 == ~t8_pc~0); 122016#L792-47 is_transmit8_triggered_~__retres1~8#1 := 0; 123133#L803-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 123134#L804-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 121467#L1667-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 121468#L1667-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 121969#L811-45 assume 1 == ~t9_pc~0; 121971#L812-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 123045#L822-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 123046#L823-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 122853#L1675-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 122854#L1675-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 133257#L830-45 assume !(1 == ~t10_pc~0); 121396#L830-47 is_transmit10_triggered_~__retres1~10#1 := 0; 121397#L841-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 123429#L842-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 121628#L1683-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 121629#L1683-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 133255#L849-45 assume 1 == ~t11_pc~0; 133254#L850-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 121840#L860-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 121841#L861-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 133252#L1691-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 133251#L1691-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 133250#L868-45 assume 1 == ~t12_pc~0; 133248#L869-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 133247#L879-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 133246#L880-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 133245#L1699-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 123276#L1699-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 123277#L887-45 assume 1 == ~t13_pc~0; 123069#L888-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 121631#L898-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 123463#L899-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 123464#L1707-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 123578#L1707-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 122996#L1439-3 assume !(1 == ~M_E~0); 122971#L1439-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 121613#L1444-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 121614#L1449-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 121778#L1454-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 122750#L1459-3 assume !(1 == ~T5_E~0); 122751#L1464-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 123280#L1469-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 123209#L1474-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 123210#L1479-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 123283#L1484-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 122413#L1489-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 122414#L1494-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 123122#L1499-3 assume !(1 == ~T13_E~0); 122710#L1504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 122711#L1509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 123220#L1514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 123255#L1519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 122325#L1524-3 assume 1 == ~E_4~0;~E_4~0 := 2; 122326#L1529-3 assume 1 == ~E_5~0;~E_5~0 := 2; 133602#L1534-3 assume 1 == ~E_6~0;~E_6~0 := 2; 133600#L1539-3 assume !(1 == ~E_7~0); 133598#L1544-3 assume 1 == ~E_8~0;~E_8~0 := 2; 123288#L1549-3 assume 1 == ~E_9~0;~E_9~0 := 2; 122585#L1554-3 assume 1 == ~E_10~0;~E_10~0 := 2; 121668#L1559-3 assume 1 == ~E_11~0;~E_11~0 := 2; 121669#L1564-3 assume 1 == ~E_12~0;~E_12~0 := 2; 122860#L1569-3 assume 1 == ~E_13~0;~E_13~0 := 2; 122861#L1574-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 121543#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 121316#L1064-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 121589#L1065-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 121550#L1959 assume !(0 == start_simulation_~tmp~3#1); 121552#L1959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 121584#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 121534#L1064-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 122911#L1065-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 123050#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 123307#L1921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 123330#L1922 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 123331#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 123518#L1940-2 [2021-12-16 10:05:37,858 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:37,858 INFO L85 PathProgramCache]: Analyzing trace with hash -121367293, now seen corresponding path program 1 times [2021-12-16 10:05:37,859 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:37,859 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [885951360] [2021-12-16 10:05:37,860 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:37,860 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:37,875 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:37,964 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:05:37,964 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:37,964 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [885951360] [2021-12-16 10:05:37,964 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [885951360] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:37,964 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:37,964 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-16 10:05:37,965 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [920964827] [2021-12-16 10:05:37,965 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:37,965 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:05:37,965 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:37,965 INFO L85 PathProgramCache]: Analyzing trace with hash 1211431707, now seen corresponding path program 1 times [2021-12-16 10:05:37,965 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:37,965 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1011151263] [2021-12-16 10:05:37,966 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:37,966 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:37,977 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:38,000 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:05:38,000 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:38,000 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1011151263] [2021-12-16 10:05:38,001 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1011151263] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:38,001 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:38,001 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:05:38,001 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1754828130] [2021-12-16 10:05:38,001 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:38,002 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:05:38,002 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:05:38,002 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-16 10:05:38,002 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-16 10:05:38,003 INFO L87 Difference]: Start difference. First operand 13617 states and 19820 transitions. cyclomatic complexity: 6205 Second operand has 5 states, 5 states have (on average 32.2) internal successors, (161), 5 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:38,406 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:05:38,406 INFO L93 Difference]: Finished difference Result 37340 states and 54365 transitions. [2021-12-16 10:05:38,407 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-16 10:05:38,407 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 37340 states and 54365 transitions. [2021-12-16 10:05:38,599 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 36952 [2021-12-16 10:05:38,746 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 37340 states to 37340 states and 54365 transitions. [2021-12-16 10:05:38,747 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 37340 [2021-12-16 10:05:38,784 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 37340 [2021-12-16 10:05:38,784 INFO L73 IsDeterministic]: Start isDeterministic. Operand 37340 states and 54365 transitions. [2021-12-16 10:05:38,822 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:05:38,822 INFO L681 BuchiCegarLoop]: Abstraction has 37340 states and 54365 transitions. [2021-12-16 10:05:38,853 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 37340 states and 54365 transitions. [2021-12-16 10:05:39,217 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 37340 to 13968. [2021-12-16 10:05:39,234 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 13968 states, 13968 states have (on average 1.444086483390607) internal successors, (20171), 13967 states have internal predecessors, (20171), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:39,269 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13968 states to 13968 states and 20171 transitions. [2021-12-16 10:05:39,270 INFO L704 BuchiCegarLoop]: Abstraction has 13968 states and 20171 transitions. [2021-12-16 10:05:39,270 INFO L587 BuchiCegarLoop]: Abstraction has 13968 states and 20171 transitions. [2021-12-16 10:05:39,270 INFO L425 BuchiCegarLoop]: ======== Iteration 21============ [2021-12-16 10:05:39,270 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 13968 states and 20171 transitions. [2021-12-16 10:05:39,321 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 13788 [2021-12-16 10:05:39,321 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:05:39,321 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:05:39,324 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:39,324 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:39,325 INFO L791 eck$LassoCheckResult]: Stem: 173220#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 173221#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 174388#L1903 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 174389#L907 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 174554#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 173730#L914-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 173151#L919-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 173152#L924-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 174056#L929-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 174057#L934-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 174191#L939-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 174192#L944-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 172916#L949-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 172917#L954-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 174227#L959-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 173484#L964-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 173485#L969-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 174119#L974-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 173376#L979-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 173377#L1291 assume !(0 == ~M_E~0); 174555#L1291-2 assume !(0 == ~T1_E~0); 174552#L1296-1 assume !(0 == ~T2_E~0); 173549#L1301-1 assume !(0 == ~T3_E~0); 173550#L1306-1 assume !(0 == ~T4_E~0); 174132#L1311-1 assume !(0 == ~T5_E~0); 172756#L1316-1 assume !(0 == ~T6_E~0); 172757#L1321-1 assume !(0 == ~T7_E~0); 173562#L1326-1 assume !(0 == ~T8_E~0); 172578#L1331-1 assume !(0 == ~T9_E~0); 172275#L1336-1 assume !(0 == ~T10_E~0); 172276#L1341-1 assume !(0 == ~T11_E~0); 172356#L1346-1 assume !(0 == ~T12_E~0); 172357#L1351-1 assume !(0 == ~T13_E~0); 172700#L1356-1 assume !(0 == ~E_M~0); 172701#L1361-1 assume !(0 == ~E_1~0); 174438#L1366-1 assume !(0 == ~E_2~0); 172745#L1371-1 assume !(0 == ~E_3~0); 172746#L1376-1 assume !(0 == ~E_4~0); 173615#L1381-1 assume !(0 == ~E_5~0); 173616#L1386-1 assume !(0 == ~E_6~0); 174488#L1391-1 assume !(0 == ~E_7~0); 174522#L1396-1 assume !(0 == ~E_8~0); 173517#L1401-1 assume !(0 == ~E_9~0); 173518#L1406-1 assume !(0 == ~E_10~0); 173821#L1411-1 assume !(0 == ~E_11~0); 173822#L1416-1 assume !(0 == ~E_12~0); 173421#L1421-1 assume !(0 == ~E_13~0); 172939#L1426-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 172940#L640 assume !(1 == ~m_pc~0); 173481#L640-2 is_master_triggered_~__retres1~0#1 := 0; 173480#L651 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 173580#L652 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 173466#L1603 assume !(0 != activate_threads_~tmp~1#1); 173467#L1603-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 173075#L659 assume !(1 == ~t1_pc~0); 173076#L659-2 is_transmit1_triggered_~__retres1~1#1 := 0; 174299#L670 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 174265#L671 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 173204#L1611 assume !(0 != activate_threads_~tmp___0~0#1); 173205#L1611-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 173218#L678 assume !(1 == ~t2_pc~0); 174415#L678-2 is_transmit2_triggered_~__retres1~2#1 := 0; 174481#L689 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 174482#L690 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 173327#L1619 assume !(0 != activate_threads_~tmp___1~0#1); 173328#L1619-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 173461#L697 assume !(1 == ~t3_pc~0); 173462#L697-2 is_transmit3_triggered_~__retres1~3#1 := 0; 173594#L708 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 174346#L709 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 173359#L1627 assume !(0 != activate_threads_~tmp___2~0#1); 173360#L1627-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 174370#L716 assume 1 == ~t4_pc~0; 174352#L717 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 173054#L727 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 173055#L728 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 172540#L1635 assume !(0 != activate_threads_~tmp___3~0#1); 172541#L1635-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 173912#L735 assume !(1 == ~t5_pc~0); 172499#L735-2 is_transmit5_triggered_~__retres1~5#1 := 0; 172500#L746 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 172964#L747 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 173941#L1643 assume !(0 != activate_threads_~tmp___4~0#1); 173540#L1643-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 173541#L754 assume 1 == ~t6_pc~0; 173278#L755 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 173166#L765 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 173167#L766 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 173136#L1651 assume !(0 != activate_threads_~tmp___5~0#1); 173137#L1651-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 174047#L773 assume !(1 == ~t7_pc~0); 172704#L773-2 is_transmit7_triggered_~__retres1~7#1 := 0; 172703#L784 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 173581#L785 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 173551#L1659 assume !(0 != activate_threads_~tmp___6~0#1); 173552#L1659-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 173605#L792 assume 1 == ~t8_pc~0; 173791#L793 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 174195#L803 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 173599#L804 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 173544#L1667 assume !(0 != activate_threads_~tmp___7~0#1); 173464#L1667-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 173465#L811 assume 1 == ~t9_pc~0; 173687#L812 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 174238#L822 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 174079#L823 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 173682#L1675 assume !(0 != activate_threads_~tmp___8~0#1); 173477#L1675-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 173478#L830 assume !(1 == ~t10_pc~0); 173176#L830-2 is_transmit10_triggered_~__retres1~10#1 := 0; 172683#L841 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 172373#L842 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 172374#L1683 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 172664#L1683-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 174068#L849 assume 1 == ~t11_pc~0; 174069#L850 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 172475#L860 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 172476#L861 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 173082#L1691 assume !(0 != activate_threads_~tmp___10~0#1); 173949#L1691-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 173950#L868 assume !(1 == ~t12_pc~0); 173312#L868-2 is_transmit12_triggered_~__retres1~12#1 := 0; 173311#L879 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 173091#L880 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 173092#L1699 assume !(0 != activate_threads_~tmp___11~0#1); 172717#L1699-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 172718#L887 assume 1 == ~t13_pc~0; 173965#L888 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 173353#L898 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 173354#L899 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 173829#L1707 assume !(0 != activate_threads_~tmp___12~0#1); 172416#L1707-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 172417#L1439 assume !(1 == ~M_E~0); 173536#L1439-2 assume !(1 == ~T1_E~0); 172590#L1444-1 assume !(1 == ~T2_E~0); 172591#L1449-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 173078#L1454-1 assume !(1 == ~T4_E~0); 173079#L1459-1 assume !(1 == ~T5_E~0); 173679#L1464-1 assume !(1 == ~T6_E~0); 173680#L1469-1 assume !(1 == ~T7_E~0); 173760#L1474-1 assume !(1 == ~T8_E~0); 173422#L1479-1 assume !(1 == ~T9_E~0); 173423#L1484-1 assume !(1 == ~T10_E~0); 173683#L1489-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 173300#L1494-1 assume !(1 == ~T12_E~0); 173301#L1499-1 assume !(1 == ~T13_E~0); 173505#L1504-1 assume !(1 == ~E_M~0); 173506#L1509-1 assume !(1 == ~E_1~0); 174173#L1514-1 assume !(1 == ~E_2~0); 173793#L1519-1 assume !(1 == ~E_3~0); 173794#L1524-1 assume !(1 == ~E_4~0); 174464#L1529-1 assume 1 == ~E_5~0;~E_5~0 := 2; 174465#L1534-1 assume !(1 == ~E_6~0); 172409#L1539-1 assume !(1 == ~E_7~0); 172410#L1544-1 assume !(1 == ~E_8~0); 172833#L1549-1 assume !(1 == ~E_9~0); 174410#L1554-1 assume !(1 == ~E_10~0); 174403#L1559-1 assume !(1 == ~E_11~0); 174222#L1564-1 assume !(1 == ~E_12~0); 174223#L1569-1 assume 1 == ~E_13~0;~E_13~0 := 2; 174455#L1574-1 assume { :end_inline_reset_delta_events } true; 174496#L1940-2 [2021-12-16 10:05:39,325 INFO L793 eck$LassoCheckResult]: Loop: 174496#L1940-2 assume !false; 178109#L1941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 178100#L1266 assume !false; 178098#L1075 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 178083#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 178042#L1064 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 178037#L1065 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 178031#L1079 assume !(0 != eval_~tmp~0#1); 178032#L1281 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 179023#L907-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 179021#L1291-3 assume !(0 == ~M_E~0); 179019#L1291-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 179017#L1296-3 assume !(0 == ~T2_E~0); 179015#L1301-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 179012#L1306-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 179010#L1311-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 179008#L1316-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 179006#L1321-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 179004#L1326-3 assume !(0 == ~T8_E~0); 179002#L1331-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 178999#L1336-3 assume !(0 == ~T10_E~0); 178997#L1341-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 178995#L1346-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 178993#L1351-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 178991#L1356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 178989#L1361-3 assume 0 == ~E_1~0;~E_1~0 := 1; 178986#L1366-3 assume !(0 == ~E_2~0); 178984#L1371-3 assume 0 == ~E_3~0;~E_3~0 := 1; 178982#L1376-3 assume !(0 == ~E_4~0); 178980#L1381-3 assume 0 == ~E_5~0;~E_5~0 := 1; 178978#L1386-3 assume 0 == ~E_6~0;~E_6~0 := 1; 178976#L1391-3 assume 0 == ~E_7~0;~E_7~0 := 1; 178973#L1396-3 assume 0 == ~E_8~0;~E_8~0 := 1; 178971#L1401-3 assume 0 == ~E_9~0;~E_9~0 := 1; 178969#L1406-3 assume !(0 == ~E_10~0); 178967#L1411-3 assume 0 == ~E_11~0;~E_11~0 := 1; 178965#L1416-3 assume !(0 == ~E_12~0); 178963#L1421-3 assume 0 == ~E_13~0;~E_13~0 := 1; 178962#L1426-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 178961#L640-45 assume !(1 == ~m_pc~0); 178960#L640-47 is_master_triggered_~__retres1~0#1 := 0; 178958#L651-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 178957#L652-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 178956#L1603-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 178955#L1603-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 178954#L659-45 assume !(1 == ~t1_pc~0); 178953#L659-47 is_transmit1_triggered_~__retres1~1#1 := 0; 178952#L670-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 178951#L671-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 178950#L1611-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 178949#L1611-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 178948#L678-45 assume !(1 == ~t2_pc~0); 175082#L678-47 is_transmit2_triggered_~__retres1~2#1 := 0; 178947#L689-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 178946#L690-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 178945#L1619-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 178944#L1619-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 178943#L697-45 assume !(1 == ~t3_pc~0); 178942#L697-47 is_transmit3_triggered_~__retres1~3#1 := 0; 178940#L708-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 178938#L709-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 178936#L1627-45 assume !(0 != activate_threads_~tmp___2~0#1); 178934#L1627-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 178933#L716-45 assume !(1 == ~t4_pc~0); 178931#L716-47 is_transmit4_triggered_~__retres1~4#1 := 0; 178930#L727-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 178929#L728-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 178928#L1635-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 178927#L1635-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 178926#L735-45 assume 1 == ~t5_pc~0; 178924#L736-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 178923#L746-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 178922#L747-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 178921#L1643-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 178920#L1643-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 178919#L754-45 assume 1 == ~t6_pc~0; 178918#L755-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 178916#L765-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 178913#L766-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 178912#L1651-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 178911#L1651-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 178905#L773-45 assume 1 == ~t7_pc~0; 178874#L774-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 178872#L784-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 178870#L785-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 178867#L1659-45 assume !(0 != activate_threads_~tmp___6~0#1); 178865#L1659-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 178863#L792-45 assume 1 == ~t8_pc~0; 178860#L793-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 178858#L803-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 178856#L804-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 178855#L1667-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 178852#L1667-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 178850#L811-45 assume 1 == ~t9_pc~0; 178848#L812-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 178845#L822-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 178843#L823-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 178841#L1675-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 178838#L1675-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 178836#L830-45 assume !(1 == ~t10_pc~0); 178834#L830-47 is_transmit10_triggered_~__retres1~10#1 := 0; 178831#L841-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 178829#L842-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 178827#L1683-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 178824#L1683-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 178822#L849-45 assume !(1 == ~t11_pc~0); 178819#L849-47 is_transmit11_triggered_~__retres1~11#1 := 0; 178817#L860-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 178815#L861-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 178813#L1691-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 178810#L1691-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 178808#L868-45 assume 1 == ~t12_pc~0; 178771#L869-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 178769#L879-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 178767#L880-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 178765#L1699-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 178762#L1699-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 178759#L887-45 assume !(1 == ~t13_pc~0); 178756#L887-47 is_transmit13_triggered_~__retres1~13#1 := 0; 178754#L898-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 178752#L899-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 178750#L1707-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 178747#L1707-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 178745#L1439-3 assume !(1 == ~M_E~0); 178741#L1439-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 178739#L1444-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 178737#L1449-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 178735#L1454-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 178733#L1459-3 assume !(1 == ~T5_E~0); 178731#L1464-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 178729#L1469-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 178727#L1474-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 178725#L1479-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 178723#L1484-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 178721#L1489-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 178719#L1494-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 178717#L1499-3 assume !(1 == ~T13_E~0); 178715#L1504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 178713#L1509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 178711#L1514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 178709#L1519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 178707#L1524-3 assume 1 == ~E_4~0;~E_4~0 := 2; 178705#L1529-3 assume 1 == ~E_5~0;~E_5~0 := 2; 178703#L1534-3 assume 1 == ~E_6~0;~E_6~0 := 2; 178701#L1539-3 assume !(1 == ~E_7~0); 178699#L1544-3 assume 1 == ~E_8~0;~E_8~0 := 2; 174809#L1549-3 assume 1 == ~E_9~0;~E_9~0 := 2; 174800#L1554-3 assume 1 == ~E_10~0;~E_10~0 := 2; 174792#L1559-3 assume 1 == ~E_11~0;~E_11~0 := 2; 174783#L1564-3 assume 1 == ~E_12~0;~E_12~0 := 2; 174777#L1569-3 assume 1 == ~E_13~0;~E_13~0 := 2; 174773#L1574-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 174756#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 174744#L1064-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 174703#L1065-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 174704#L1959 assume !(0 == start_simulation_~tmp~3#1); 178628#L1959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 178163#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 178149#L1064-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 178147#L1065-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 178145#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 178143#L1921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 178141#L1922 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 178128#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 174496#L1940-2 [2021-12-16 10:05:39,326 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:39,326 INFO L85 PathProgramCache]: Analyzing trace with hash -2061949307, now seen corresponding path program 1 times [2021-12-16 10:05:39,326 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:39,326 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [351506192] [2021-12-16 10:05:39,327 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:39,327 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:39,343 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:39,382 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:05:39,383 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:39,383 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [351506192] [2021-12-16 10:05:39,383 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [351506192] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:39,383 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:39,383 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:05:39,384 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1270984271] [2021-12-16 10:05:39,384 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:39,384 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:05:39,384 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:39,385 INFO L85 PathProgramCache]: Analyzing trace with hash 853321502, now seen corresponding path program 1 times [2021-12-16 10:05:39,385 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:39,385 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [636459157] [2021-12-16 10:05:39,385 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:39,385 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:39,401 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:39,430 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:05:39,430 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:39,430 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [636459157] [2021-12-16 10:05:39,431 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [636459157] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:39,431 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:39,431 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:05:39,431 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2049117643] [2021-12-16 10:05:39,431 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:39,432 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:05:39,432 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:05:39,432 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-16 10:05:39,432 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-16 10:05:39,433 INFO L87 Difference]: Start difference. First operand 13968 states and 20171 transitions. cyclomatic complexity: 6205 Second operand has 4 states, 4 states have (on average 40.25) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:39,819 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:05:39,819 INFO L93 Difference]: Finished difference Result 33580 states and 48223 transitions. [2021-12-16 10:05:39,819 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-16 10:05:39,820 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 33580 states and 48223 transitions. [2021-12-16 10:05:39,993 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 33369 [2021-12-16 10:05:40,252 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 33580 states to 33580 states and 48223 transitions. [2021-12-16 10:05:40,257 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 33580 [2021-12-16 10:05:40,300 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 33580 [2021-12-16 10:05:40,300 INFO L73 IsDeterministic]: Start isDeterministic. Operand 33580 states and 48223 transitions. [2021-12-16 10:05:40,326 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:05:40,327 INFO L681 BuchiCegarLoop]: Abstraction has 33580 states and 48223 transitions. [2021-12-16 10:05:40,343 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 33580 states and 48223 transitions. [2021-12-16 10:05:40,626 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 33580 to 26811. [2021-12-16 10:05:40,661 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 26811 states, 26811 states have (on average 1.4389616202305024) internal successors, (38580), 26810 states have internal predecessors, (38580), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:40,895 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 26811 states to 26811 states and 38580 transitions. [2021-12-16 10:05:40,901 INFO L704 BuchiCegarLoop]: Abstraction has 26811 states and 38580 transitions. [2021-12-16 10:05:40,901 INFO L587 BuchiCegarLoop]: Abstraction has 26811 states and 38580 transitions. [2021-12-16 10:05:40,901 INFO L425 BuchiCegarLoop]: ======== Iteration 22============ [2021-12-16 10:05:40,901 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 26811 states and 38580 transitions. [2021-12-16 10:05:40,974 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 26628 [2021-12-16 10:05:40,974 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:05:40,974 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:05:40,977 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:40,977 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:40,978 INFO L791 eck$LassoCheckResult]: Stem: 220763#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 220764#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 221908#L1903 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 221909#L907 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 222043#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 221256#L914-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 220696#L919-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 220697#L924-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 221594#L929-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 221595#L934-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 221717#L939-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 221718#L944-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 220467#L949-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 220468#L954-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 221748#L959-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 221014#L964-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 221015#L969-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 221657#L974-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 220913#L979-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 220914#L1291 assume !(0 == ~M_E~0); 222044#L1291-2 assume !(0 == ~T1_E~0); 222041#L1296-1 assume !(0 == ~T2_E~0); 221079#L1301-1 assume !(0 == ~T3_E~0); 221080#L1306-1 assume !(0 == ~T4_E~0); 221671#L1311-1 assume !(0 == ~T5_E~0); 220306#L1316-1 assume !(0 == ~T6_E~0); 220307#L1321-1 assume !(0 == ~T7_E~0); 221092#L1326-1 assume !(0 == ~T8_E~0); 220131#L1331-1 assume !(0 == ~T9_E~0); 219833#L1336-1 assume !(0 == ~T10_E~0); 219834#L1341-1 assume !(0 == ~T11_E~0); 219913#L1346-1 assume !(0 == ~T12_E~0); 219914#L1351-1 assume !(0 == ~T13_E~0); 220254#L1356-1 assume !(0 == ~E_M~0); 220255#L1361-1 assume !(0 == ~E_1~0); 221947#L1366-1 assume !(0 == ~E_2~0); 220296#L1371-1 assume !(0 == ~E_3~0); 220297#L1376-1 assume !(0 == ~E_4~0); 221144#L1381-1 assume !(0 == ~E_5~0); 221145#L1386-1 assume !(0 == ~E_6~0); 221988#L1391-1 assume !(0 == ~E_7~0); 222021#L1396-1 assume !(0 == ~E_8~0); 221046#L1401-1 assume !(0 == ~E_9~0); 221047#L1406-1 assume !(0 == ~E_10~0); 221351#L1411-1 assume !(0 == ~E_11~0); 221352#L1416-1 assume !(0 == ~E_12~0); 220956#L1421-1 assume !(0 == ~E_13~0); 220491#L1426-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 220492#L640 assume !(1 == ~m_pc~0); 221011#L640-2 is_master_triggered_~__retres1~0#1 := 0; 221010#L651 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 221108#L652 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 220996#L1603 assume !(0 != activate_threads_~tmp~1#1); 220997#L1603-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 220622#L659 assume !(1 == ~t1_pc~0); 220623#L659-2 is_transmit1_triggered_~__retres1~1#1 := 0; 221812#L670 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 221780#L671 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 220747#L1611 assume !(0 != activate_threads_~tmp___0~0#1); 220748#L1611-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 220761#L678 assume !(1 == ~t2_pc~0); 221934#L678-2 is_transmit2_triggered_~__retres1~2#1 := 0; 221983#L689 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 221984#L690 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 220861#L1619 assume !(0 != activate_threads_~tmp___1~0#1); 220862#L1619-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 220991#L697 assume !(1 == ~t3_pc~0); 220992#L697-2 is_transmit3_triggered_~__retres1~3#1 := 0; 221124#L708 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 221861#L709 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 220897#L1627 assume !(0 != activate_threads_~tmp___2~0#1); 220898#L1627-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 221884#L716 assume !(1 == ~t4_pc~0); 221432#L716-2 is_transmit4_triggered_~__retres1~4#1 := 0; 220604#L727 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 220605#L728 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 220094#L1635 assume !(0 != activate_threads_~tmp___3~0#1); 220095#L1635-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 221445#L735 assume !(1 == ~t5_pc~0); 220055#L735-2 is_transmit5_triggered_~__retres1~5#1 := 0; 220056#L746 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 220511#L747 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 221478#L1643 assume !(0 != activate_threads_~tmp___4~0#1); 221069#L1643-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 221070#L754 assume 1 == ~t6_pc~0; 220814#L755 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 220710#L765 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 220711#L766 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 220683#L1651 assume !(0 != activate_threads_~tmp___5~0#1); 220684#L1651-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 221584#L773 assume !(1 == ~t7_pc~0); 220258#L773-2 is_transmit7_triggered_~__retres1~7#1 := 0; 220257#L784 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 221109#L785 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 221081#L1659 assume !(0 != activate_threads_~tmp___6~0#1); 221082#L1659-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 221133#L792 assume 1 == ~t8_pc~0; 221323#L793 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 221721#L803 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 221127#L804 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 221073#L1667 assume !(0 != activate_threads_~tmp___7~0#1); 220994#L1667-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 220995#L811 assume 1 == ~t9_pc~0; 221214#L812 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 221759#L822 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 221614#L823 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 221209#L1675 assume !(0 != activate_threads_~tmp___8~0#1); 221007#L1675-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 221008#L830 assume !(1 == ~t10_pc~0); 220722#L830-2 is_transmit10_triggered_~__retres1~10#1 := 0; 220237#L841 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 219930#L842 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 219931#L1683 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 220219#L1683-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 221603#L849 assume 1 == ~t11_pc~0; 221604#L850 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 220031#L860 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 220032#L861 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 220631#L1691 assume !(0 != activate_threads_~tmp___10~0#1); 221487#L1691-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 221488#L868 assume !(1 == ~t12_pc~0); 220846#L868-2 is_transmit12_triggered_~__retres1~12#1 := 0; 220845#L879 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 220638#L880 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 220639#L1699 assume !(0 != activate_threads_~tmp___11~0#1); 220270#L1699-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 220271#L887 assume 1 == ~t13_pc~0; 221500#L888 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 220891#L898 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 220892#L899 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 221360#L1707 assume !(0 != activate_threads_~tmp___12~0#1); 219973#L1707-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 219974#L1439 assume !(1 == ~M_E~0); 221067#L1439-2 assume !(1 == ~T1_E~0); 220143#L1444-1 assume !(1 == ~T2_E~0); 220144#L1449-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 220627#L1454-1 assume !(1 == ~T4_E~0); 220628#L1459-1 assume !(1 == ~T5_E~0); 221206#L1464-1 assume !(1 == ~T6_E~0); 221207#L1469-1 assume !(1 == ~T7_E~0); 221291#L1474-1 assume !(1 == ~T8_E~0); 220957#L1479-1 assume !(1 == ~T9_E~0); 220958#L1484-1 assume !(1 == ~T10_E~0); 221210#L1489-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 220837#L1494-1 assume !(1 == ~T12_E~0); 220838#L1499-1 assume !(1 == ~T13_E~0); 221035#L1504-1 assume !(1 == ~E_M~0); 221036#L1509-1 assume !(1 == ~E_1~0); 221703#L1514-1 assume !(1 == ~E_2~0); 221325#L1519-1 assume !(1 == ~E_3~0); 221326#L1524-1 assume !(1 == ~E_4~0); 221964#L1529-1 assume 1 == ~E_5~0;~E_5~0 := 2; 221965#L1534-1 assume !(1 == ~E_6~0); 219966#L1539-1 assume !(1 == ~E_7~0); 219967#L1544-1 assume !(1 == ~E_8~0); 220382#L1549-1 assume !(1 == ~E_9~0); 221931#L1554-1 assume !(1 == ~E_10~0); 221924#L1559-1 assume !(1 == ~E_11~0); 221743#L1564-1 assume !(1 == ~E_12~0); 221744#L1569-1 assume 1 == ~E_13~0;~E_13~0 := 2; 221958#L1574-1 assume { :end_inline_reset_delta_events } true; 221997#L1940-2 [2021-12-16 10:05:40,978 INFO L793 eck$LassoCheckResult]: Loop: 221997#L1940-2 assume !false; 243568#L1941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 221510#L1266 assume !false; 221511#L1075 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 220680#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 220408#L1064 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 220804#L1065 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 220805#L1079 assume !(0 != eval_~tmp~0#1); 220766#L1281 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 220767#L907-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 221418#L1291-3 assume !(0 == ~M_E~0); 221289#L1291-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 221290#L1296-3 assume !(0 == ~T2_E~0); 222012#L1301-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 221938#L1306-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 220921#L1311-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 220184#L1316-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 220185#L1321-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 220286#L1326-3 assume !(0 == ~T8_E~0); 221060#L1331-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 221332#L1336-3 assume !(0 == ~T10_E~0); 221333#L1341-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 220619#L1346-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 220598#L1351-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 220541#L1356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 220542#L1361-3 assume 0 == ~E_1~0;~E_1~0 := 1; 221125#L1366-3 assume !(0 == ~E_2~0); 219888#L1371-3 assume 0 == ~E_3~0;~E_3~0 := 1; 219889#L1376-3 assume !(0 == ~E_4~0); 221728#L1381-3 assume 0 == ~E_5~0;~E_5~0 := 1; 221894#L1386-3 assume 0 == ~E_6~0;~E_6~0 := 1; 246589#L1391-3 assume 0 == ~E_7~0;~E_7~0 := 1; 221750#L1396-3 assume 0 == ~E_8~0;~E_8~0 := 1; 221751#L1401-3 assume 0 == ~E_9~0;~E_9~0 := 1; 220253#L1406-3 assume !(0 == ~E_10~0); 220103#L1411-3 assume 0 == ~E_11~0;~E_11~0 := 1; 220104#L1416-3 assume !(0 == ~E_12~0); 220773#L1421-3 assume 0 == ~E_13~0;~E_13~0 := 1; 220774#L1426-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 220887#L640-45 assume 1 == ~m_pc~0; 220889#L641-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 220343#L651-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 220344#L652-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 219882#L1603-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 219883#L1603-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 219978#L659-45 assume !(1 == ~t1_pc~0); 219979#L659-47 is_transmit1_triggered_~__retres1~1#1 := 0; 220422#L670-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 221437#L671-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 221438#L1611-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 221458#L1611-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 221459#L678-45 assume !(1 == ~t2_pc~0); 221424#L678-47 is_transmit2_triggered_~__retres1~2#1 := 0; 220893#L689-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 220894#L690-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 221051#L1619-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 221770#L1619-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 221937#L697-45 assume !(1 == ~t3_pc~0); 221171#L697-47 is_transmit3_triggered_~__retres1~3#1 := 0; 221699#L708-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 246550#L709-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 221339#L1627-45 assume !(0 != activate_threads_~tmp___2~0#1); 221340#L1627-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 221376#L716-45 assume !(1 == ~t4_pc~0); 221541#L716-47 is_transmit4_triggered_~__retres1~4#1 := 0; 221542#L727-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 221598#L728-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 220979#L1635-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 220980#L1635-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 220632#L735-45 assume !(1 == ~t5_pc~0); 220634#L735-47 is_transmit5_triggered_~__retres1~5#1 := 0; 221202#L746-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 221869#L747-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 221870#L1643-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 221961#L1643-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 221956#L754-45 assume !(1 == ~t6_pc~0); 221151#L754-47 is_transmit6_triggered_~__retres1~6#1 := 0; 221150#L765-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 220556#L766-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 220557#L1651-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 221154#L1651-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 220866#L773-45 assume 1 == ~t7_pc~0; 220867#L774-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 220416#L784-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 221382#L785-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 221727#L1659-45 assume !(0 != activate_threads_~tmp___6~0#1); 220873#L1659-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 220535#L792-45 assume !(1 == ~t8_pc~0); 220537#L792-47 is_transmit8_triggered_~__retres1~8#1 := 0; 221660#L803-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 220134#L804-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 219994#L1667-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 219995#L1667-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 220493#L811-45 assume !(1 == ~t9_pc~0); 220282#L811-47 is_transmit9_triggered_~__retres1~9#1 := 0; 220283#L822-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 221570#L823-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 221372#L1675-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 220948#L1675-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 220732#L830-45 assume !(1 == ~t10_pc~0); 219923#L830-47 is_transmit10_triggered_~__retres1~10#1 := 0; 219924#L841-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 221064#L842-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 220154#L1683-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 220155#L1683-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 219902#L849-45 assume 1 == ~t11_pc~0; 219904#L850-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 221117#L860-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 246225#L861-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 246224#L1691-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 246223#L1691-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 246222#L868-45 assume !(1 == ~t12_pc~0); 246221#L868-47 is_transmit12_triggered_~__retres1~12#1 := 0; 246218#L879-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 246215#L880-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 246213#L1699-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 221793#L1699-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 221794#L887-45 assume 1 == ~t13_pc~0; 221597#L888-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 220157#L898-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 221504#L899-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 221953#L1707-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 222069#L1707-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 245555#L1439-3 assume !(1 == ~M_E~0); 245554#L1439-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 246071#L1444-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 246070#L1449-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 246069#L1454-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 246068#L1459-3 assume !(1 == ~T5_E~0); 246067#L1464-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 246066#L1469-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 246065#L1474-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 246064#L1479-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 246063#L1484-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 246062#L1489-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 246061#L1494-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 246060#L1499-3 assume !(1 == ~T13_E~0); 246059#L1504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 246058#L1509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 246057#L1514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 246056#L1519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 246055#L1524-3 assume 1 == ~E_4~0;~E_4~0 := 2; 246054#L1529-3 assume 1 == ~E_5~0;~E_5~0 := 2; 246053#L1534-3 assume 1 == ~E_6~0;~E_6~0 := 2; 246052#L1539-3 assume !(1 == ~E_7~0); 246051#L1544-3 assume 1 == ~E_8~0;~E_8~0 := 2; 246050#L1549-3 assume 1 == ~E_9~0;~E_9~0 := 2; 246049#L1554-3 assume 1 == ~E_10~0;~E_10~0 := 2; 246048#L1559-3 assume 1 == ~E_11~0;~E_11~0 := 2; 246047#L1564-3 assume 1 == ~E_12~0;~E_12~0 := 2; 246046#L1569-3 assume 1 == ~E_13~0;~E_13~0 := 2; 246045#L1574-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 220070#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 219843#L1064-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 220183#L1065-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 243750#L1959 assume !(0 == start_simulation_~tmp~3#1); 243747#L1959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 243604#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 243588#L1064-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 243586#L1065-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 243584#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 243583#L1921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 243578#L1922 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 243573#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 221997#L1940-2 [2021-12-16 10:05:40,979 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:40,979 INFO L85 PathProgramCache]: Analyzing trace with hash 846336710, now seen corresponding path program 1 times [2021-12-16 10:05:40,979 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:40,979 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1673226186] [2021-12-16 10:05:40,979 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:40,980 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:40,991 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:41,017 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:05:41,017 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:41,018 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1673226186] [2021-12-16 10:05:41,018 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1673226186] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:41,018 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:41,019 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:05:41,019 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [152964153] [2021-12-16 10:05:41,019 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:41,019 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:05:41,020 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:41,020 INFO L85 PathProgramCache]: Analyzing trace with hash -27618656, now seen corresponding path program 1 times [2021-12-16 10:05:41,020 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:41,020 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [387082800] [2021-12-16 10:05:41,020 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:41,021 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:41,035 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:41,067 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:05:41,067 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:41,067 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [387082800] [2021-12-16 10:05:41,068 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [387082800] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:41,068 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:41,068 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:05:41,068 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [381514167] [2021-12-16 10:05:41,068 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:41,069 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:05:41,069 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:05:41,069 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-16 10:05:41,069 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-16 10:05:41,070 INFO L87 Difference]: Start difference. First operand 26811 states and 38580 transitions. cyclomatic complexity: 11771 Second operand has 4 states, 4 states have (on average 40.25) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:41,566 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:05:41,566 INFO L93 Difference]: Finished difference Result 64418 states and 92213 transitions. [2021-12-16 10:05:41,566 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-16 10:05:41,567 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 64418 states and 92213 transitions. [2021-12-16 10:05:41,915 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 64172 [2021-12-16 10:05:42,291 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 64418 states to 64418 states and 92213 transitions. [2021-12-16 10:05:42,292 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 64418 [2021-12-16 10:05:42,329 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 64418 [2021-12-16 10:05:42,329 INFO L73 IsDeterministic]: Start isDeterministic. Operand 64418 states and 92213 transitions. [2021-12-16 10:05:42,400 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:05:42,400 INFO L681 BuchiCegarLoop]: Abstraction has 64418 states and 92213 transitions. [2021-12-16 10:05:42,442 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 64418 states and 92213 transitions. [2021-12-16 10:05:42,987 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 64418 to 51566. [2021-12-16 10:05:43,043 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 51566 states, 51566 states have (on average 1.4342202226273126) internal successors, (73957), 51565 states have internal predecessors, (73957), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:43,163 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 51566 states to 51566 states and 73957 transitions. [2021-12-16 10:05:43,163 INFO L704 BuchiCegarLoop]: Abstraction has 51566 states and 73957 transitions. [2021-12-16 10:05:43,163 INFO L587 BuchiCegarLoop]: Abstraction has 51566 states and 73957 transitions. [2021-12-16 10:05:43,164 INFO L425 BuchiCegarLoop]: ======== Iteration 23============ [2021-12-16 10:05:43,164 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 51566 states and 73957 transitions. [2021-12-16 10:05:43,358 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 51376 [2021-12-16 10:05:43,359 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:05:43,359 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:05:43,363 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:43,364 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:43,364 INFO L791 eck$LassoCheckResult]: Stem: 311997#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 311998#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 313165#L1903 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 313166#L907 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 313303#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 312496#L914-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 311930#L919-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 311931#L924-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 312832#L929-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 312833#L934-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 312963#L939-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 312964#L944-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 311703#L949-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 311704#L954-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 312997#L959-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 312251#L964-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 312252#L969-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 312896#L974-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 312145#L979-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 312146#L1291 assume !(0 == ~M_E~0); 313304#L1291-2 assume !(0 == ~T1_E~0); 313302#L1296-1 assume !(0 == ~T2_E~0); 312314#L1301-1 assume !(0 == ~T3_E~0); 312315#L1306-1 assume !(0 == ~T4_E~0); 312909#L1311-1 assume !(0 == ~T5_E~0); 311543#L1316-1 assume !(0 == ~T6_E~0); 311544#L1321-1 assume !(0 == ~T7_E~0); 312327#L1326-1 assume !(0 == ~T8_E~0); 311370#L1331-1 assume !(0 == ~T9_E~0); 311072#L1336-1 assume !(0 == ~T10_E~0); 311073#L1341-1 assume !(0 == ~T11_E~0); 311151#L1346-1 assume !(0 == ~T12_E~0); 311152#L1351-1 assume !(0 == ~T13_E~0); 311491#L1356-1 assume !(0 == ~E_M~0); 311492#L1361-1 assume !(0 == ~E_1~0); 313200#L1366-1 assume !(0 == ~E_2~0); 311533#L1371-1 assume !(0 == ~E_3~0); 311534#L1376-1 assume !(0 == ~E_4~0); 312381#L1381-1 assume !(0 == ~E_5~0); 312382#L1386-1 assume !(0 == ~E_6~0); 313248#L1391-1 assume !(0 == ~E_7~0); 313276#L1396-1 assume !(0 == ~E_8~0); 312283#L1401-1 assume !(0 == ~E_9~0); 312284#L1406-1 assume !(0 == ~E_10~0); 312593#L1411-1 assume !(0 == ~E_11~0); 312594#L1416-1 assume !(0 == ~E_12~0); 312192#L1421-1 assume !(0 == ~E_13~0); 311729#L1426-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 311730#L640 assume !(1 == ~m_pc~0); 312247#L640-2 is_master_triggered_~__retres1~0#1 := 0; 312246#L651 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 312347#L652 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 312232#L1603 assume !(0 != activate_threads_~tmp~1#1); 312233#L1603-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 311859#L659 assume !(1 == ~t1_pc~0); 311860#L659-2 is_transmit1_triggered_~__retres1~1#1 := 0; 313060#L670 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 313031#L671 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 311981#L1611 assume !(0 != activate_threads_~tmp___0~0#1); 311982#L1611-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 311995#L678 assume !(1 == ~t2_pc~0); 313189#L678-2 is_transmit2_triggered_~__retres1~2#1 := 0; 313239#L689 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 313240#L690 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 312096#L1619 assume !(0 != activate_threads_~tmp___1~0#1); 312097#L1619-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 312227#L697 assume !(1 == ~t3_pc~0); 312228#L697-2 is_transmit3_triggered_~__retres1~3#1 := 0; 312362#L708 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 313118#L709 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 312129#L1627 assume !(0 != activate_threads_~tmp___2~0#1); 312130#L1627-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 313146#L716 assume !(1 == ~t4_pc~0); 312671#L716-2 is_transmit4_triggered_~__retres1~4#1 := 0; 311841#L727 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 311842#L728 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 311333#L1635 assume !(0 != activate_threads_~tmp___3~0#1); 311334#L1635-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 312685#L735 assume !(1 == ~t5_pc~0); 311294#L735-2 is_transmit5_triggered_~__retres1~5#1 := 0; 311295#L746 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 311748#L747 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 312719#L1643 assume !(0 != activate_threads_~tmp___4~0#1); 312306#L1643-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 312307#L754 assume !(1 == ~t6_pc~0); 312549#L754-2 is_transmit6_triggered_~__retres1~6#1 := 0; 311943#L765 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 311944#L766 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 311917#L1651 assume !(0 != activate_threads_~tmp___5~0#1); 311918#L1651-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 312820#L773 assume !(1 == ~t7_pc~0); 311495#L773-2 is_transmit7_triggered_~__retres1~7#1 := 0; 311494#L784 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 312348#L785 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 312316#L1659 assume !(0 != activate_threads_~tmp___6~0#1); 312317#L1659-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 312371#L792 assume 1 == ~t8_pc~0; 312565#L793 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 312967#L803 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 312365#L804 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 312310#L1667 assume !(0 != activate_threads_~tmp___7~0#1); 312230#L1667-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 312231#L811 assume 1 == ~t9_pc~0; 312455#L812 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 313008#L822 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 312854#L823 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 312449#L1675 assume !(0 != activate_threads_~tmp___8~0#1); 312243#L1675-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 312244#L830 assume !(1 == ~t10_pc~0); 311955#L830-2 is_transmit10_triggered_~__retres1~10#1 := 0; 311475#L841 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 311168#L842 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 311169#L1683 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 311457#L1683-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 312843#L849 assume 1 == ~t11_pc~0; 312844#L850 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 311269#L860 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 311270#L861 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 311868#L1691 assume !(0 != activate_threads_~tmp___10~0#1); 312726#L1691-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 312727#L868 assume !(1 == ~t12_pc~0); 312081#L868-2 is_transmit12_triggered_~__retres1~12#1 := 0; 312080#L879 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 311875#L880 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 311876#L1699 assume !(0 != activate_threads_~tmp___11~0#1); 311507#L1699-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 311508#L887 assume 1 == ~t13_pc~0; 312740#L888 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 312123#L898 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 312124#L899 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 312602#L1707 assume !(0 != activate_threads_~tmp___12~0#1); 311211#L1707-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 311212#L1439 assume !(1 == ~M_E~0); 312304#L1439-2 assume !(1 == ~T1_E~0); 311382#L1444-1 assume !(1 == ~T2_E~0); 311383#L1449-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 311864#L1454-1 assume !(1 == ~T4_E~0); 311865#L1459-1 assume !(1 == ~T5_E~0); 312446#L1464-1 assume !(1 == ~T6_E~0); 312447#L1469-1 assume !(1 == ~T7_E~0); 312531#L1474-1 assume !(1 == ~T8_E~0); 312193#L1479-1 assume !(1 == ~T9_E~0); 312194#L1484-1 assume !(1 == ~T10_E~0); 312450#L1489-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 312072#L1494-1 assume !(1 == ~T12_E~0); 312073#L1499-1 assume !(1 == ~T13_E~0); 312272#L1504-1 assume !(1 == ~E_M~0); 312273#L1509-1 assume !(1 == ~E_1~0); 312946#L1514-1 assume !(1 == ~E_2~0); 312567#L1519-1 assume !(1 == ~E_3~0); 312568#L1524-1 assume !(1 == ~E_4~0); 313220#L1529-1 assume 1 == ~E_5~0;~E_5~0 := 2; 313221#L1534-1 assume !(1 == ~E_6~0); 311204#L1539-1 assume !(1 == ~E_7~0); 311205#L1544-1 assume !(1 == ~E_8~0); 311619#L1549-1 assume !(1 == ~E_9~0); 313188#L1554-1 assume !(1 == ~E_10~0); 313180#L1559-1 assume !(1 == ~E_11~0); 312990#L1564-1 assume !(1 == ~E_12~0); 312991#L1569-1 assume 1 == ~E_13~0;~E_13~0 := 2; 313214#L1574-1 assume { :end_inline_reset_delta_events } true; 313256#L1940-2 [2021-12-16 10:05:43,543 INFO L793 eck$LassoCheckResult]: Loop: 313256#L1940-2 assume !false; 349964#L1941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 349959#L1266 assume !false; 349958#L1075 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 348313#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 348304#L1064 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 348302#L1065 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 348299#L1079 assume !(0 != eval_~tmp~0#1); 348300#L1281 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 360907#L907-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 360905#L1291-3 assume !(0 == ~M_E~0); 360906#L1291-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 361995#L1296-3 assume !(0 == ~T2_E~0); 361994#L1301-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 361993#L1306-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 361992#L1311-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 361991#L1316-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 361990#L1321-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 361989#L1326-3 assume !(0 == ~T8_E~0); 361988#L1331-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 361987#L1336-3 assume !(0 == ~T10_E~0); 361986#L1341-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 361985#L1346-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 361984#L1351-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 361983#L1356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 361982#L1361-3 assume 0 == ~E_1~0;~E_1~0 := 1; 312403#L1366-3 assume !(0 == ~E_2~0); 311126#L1371-3 assume 0 == ~E_3~0;~E_3~0 := 1; 311127#L1376-3 assume !(0 == ~E_4~0); 312973#L1381-3 assume 0 == ~E_5~0;~E_5~0 := 1; 312792#L1386-3 assume 0 == ~E_6~0;~E_6~0 := 1; 312793#L1391-3 assume 0 == ~E_7~0;~E_7~0 := 1; 313000#L1396-3 assume 0 == ~E_8~0;~E_8~0 := 1; 313001#L1401-3 assume 0 == ~E_9~0;~E_9~0 := 1; 313329#L1406-3 assume !(0 == ~E_10~0); 361222#L1411-3 assume 0 == ~E_11~0;~E_11~0 := 1; 361221#L1416-3 assume !(0 == ~E_12~0); 361220#L1421-3 assume 0 == ~E_13~0;~E_13~0 := 1; 312829#L1426-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 312830#L640-45 assume 1 == ~m_pc~0; 360737#L641-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 360736#L651-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 360735#L652-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 360734#L1603-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 360733#L1603-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 360732#L659-45 assume !(1 == ~t1_pc~0); 360731#L659-47 is_transmit1_triggered_~__retres1~1#1 := 0; 360730#L670-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 360729#L671-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 360728#L1611-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 360727#L1611-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 313136#L678-45 assume !(1 == ~t2_pc~0); 313137#L678-47 is_transmit2_triggered_~__retres1~2#1 := 0; 361324#L689-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 361323#L690-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 361322#L1619-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 361321#L1619-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 361320#L697-45 assume 1 == ~t3_pc~0; 361319#L698-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 361317#L708-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 361315#L709-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 361312#L1627-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 361311#L1627-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 361310#L716-45 assume !(1 == ~t4_pc~0); 359963#L716-47 is_transmit4_triggered_~__retres1~4#1 := 0; 361309#L727-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 361308#L728-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 361305#L1635-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 361304#L1635-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 361303#L735-45 assume !(1 == ~t5_pc~0); 361296#L735-47 is_transmit5_triggered_~__retres1~5#1 := 0; 313216#L746-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 313217#L747-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 313297#L1643-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 313219#L1643-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 313209#L754-45 assume !(1 == ~t6_pc~0); 313108#L754-47 is_transmit6_triggered_~__retres1~6#1 := 0; 313109#L765-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 311793#L766-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 311794#L1651-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 312390#L1651-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 312100#L773-45 assume !(1 == ~t7_pc~0); 311652#L773-47 is_transmit7_triggered_~__retres1~7#1 := 0; 311653#L784-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 312623#L785-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 312972#L1659-45 assume !(0 != activate_threads_~tmp___6~0#1); 312107#L1659-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 311773#L792-45 assume 1 == ~t8_pc~0; 311774#L793-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 312899#L803-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 311373#L804-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 311232#L1667-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 311233#L1667-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 311731#L811-45 assume 1 == ~t9_pc~0; 311518#L812-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 311520#L822-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 312807#L823-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 312613#L1675-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 312184#L1675-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 311966#L830-45 assume 1 == ~t10_pc~0; 311967#L831-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 311162#L841-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 312301#L842-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 311393#L1683-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 311394#L1683-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 311140#L849-45 assume !(1 == ~t11_pc~0); 311141#L849-47 is_transmit11_triggered_~__retres1~11#1 := 0; 311600#L860-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 311230#L861-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 311128#L1691-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 311129#L1691-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 311386#L868-45 assume !(1 == ~t12_pc~0); 311388#L868-47 is_transmit12_triggered_~__retres1~12#1 := 0; 311324#L879-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 311325#L880-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 312730#L1699-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 313044#L1699-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 313045#L887-45 assume 1 == ~t13_pc~0; 312836#L888-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 311396#L898-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 312743#L899-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 313206#L1707-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 311358#L1707-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 311359#L1439-3 assume !(1 == ~M_E~0); 312755#L1439-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 358401#L1444-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 358399#L1449-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 358397#L1454-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 358395#L1459-3 assume !(1 == ~T5_E~0); 358393#L1464-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 357858#L1469-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 357851#L1474-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 357845#L1479-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 357394#L1484-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 357391#L1489-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 357389#L1494-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 357387#L1499-3 assume !(1 == ~T13_E~0); 357385#L1504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 357383#L1509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 357381#L1514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 357378#L1519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 357376#L1524-3 assume 1 == ~E_4~0;~E_4~0 := 2; 357374#L1529-3 assume 1 == ~E_5~0;~E_5~0 := 2; 357372#L1534-3 assume 1 == ~E_6~0;~E_6~0 := 2; 357370#L1539-3 assume !(1 == ~E_7~0); 357368#L1544-3 assume 1 == ~E_8~0;~E_8~0 := 2; 357365#L1549-3 assume 1 == ~E_9~0;~E_9~0 := 2; 357363#L1554-3 assume 1 == ~E_10~0;~E_10~0 := 2; 357361#L1559-3 assume 1 == ~E_11~0;~E_11~0 := 2; 357359#L1564-3 assume 1 == ~E_12~0;~E_12~0 := 2; 357357#L1569-3 assume 1 == ~E_13~0;~E_13~0 := 2; 357353#L1574-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 357347#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 357333#L1064-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 357331#L1065-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 357329#L1959 assume !(0 == start_simulation_~tmp~3#1); 357325#L1959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 357319#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 357305#L1064-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 357302#L1065-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 357300#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 357298#L1921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 357296#L1922 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 357294#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 313256#L1940-2 [2021-12-16 10:05:43,544 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:43,544 INFO L85 PathProgramCache]: Analyzing trace with hash -995977081, now seen corresponding path program 1 times [2021-12-16 10:05:43,544 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:43,544 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [76400406] [2021-12-16 10:05:43,544 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:43,544 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:43,579 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:43,613 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:05:43,613 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:43,613 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [76400406] [2021-12-16 10:05:43,613 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [76400406] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:43,613 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:43,614 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:05:43,614 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1017621956] [2021-12-16 10:05:43,614 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:43,614 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:05:43,615 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:43,615 INFO L85 PathProgramCache]: Analyzing trace with hash 1623227292, now seen corresponding path program 1 times [2021-12-16 10:05:43,615 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:43,615 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [342747103] [2021-12-16 10:05:43,615 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:43,615 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:43,625 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:43,645 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:05:43,645 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:43,645 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [342747103] [2021-12-16 10:05:43,646 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [342747103] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:43,646 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:43,646 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:05:43,646 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [242118988] [2021-12-16 10:05:43,646 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:43,647 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:05:43,647 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:05:43,647 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-16 10:05:43,647 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-16 10:05:43,648 INFO L87 Difference]: Start difference. First operand 51566 states and 73957 transitions. cyclomatic complexity: 22393 Second operand has 4 states, 4 states have (on average 40.25) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:44,403 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:05:44,403 INFO L93 Difference]: Finished difference Result 123569 states and 176350 transitions. [2021-12-16 10:05:44,404 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-16 10:05:44,404 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 123569 states and 176350 transitions. [2021-12-16 10:05:45,170 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 123252 [2021-12-16 10:05:45,823 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 123569 states to 123569 states and 176350 transitions. [2021-12-16 10:05:45,823 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 123569 [2021-12-16 10:05:45,911 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 123569 [2021-12-16 10:05:45,911 INFO L73 IsDeterministic]: Start isDeterministic. Operand 123569 states and 176350 transitions. [2021-12-16 10:05:46,005 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:05:46,005 INFO L681 BuchiCegarLoop]: Abstraction has 123569 states and 176350 transitions. [2021-12-16 10:05:46,098 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 123569 states and 176350 transitions. [2021-12-16 10:05:47,093 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 123569 to 99229. [2021-12-16 10:05:47,173 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 99229 states, 99229 states have (on average 1.4297634764030676) internal successors, (141874), 99228 states have internal predecessors, (141874), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:47,673 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 99229 states to 99229 states and 141874 transitions. [2021-12-16 10:05:47,673 INFO L704 BuchiCegarLoop]: Abstraction has 99229 states and 141874 transitions. [2021-12-16 10:05:47,674 INFO L587 BuchiCegarLoop]: Abstraction has 99229 states and 141874 transitions. [2021-12-16 10:05:47,674 INFO L425 BuchiCegarLoop]: ======== Iteration 24============ [2021-12-16 10:05:47,674 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 99229 states and 141874 transitions. [2021-12-16 10:05:47,948 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 99024 [2021-12-16 10:05:47,948 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:05:47,948 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:05:47,956 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:47,956 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:47,956 INFO L791 eck$LassoCheckResult]: Stem: 487148#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 487149#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 488340#L1903 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 488341#L907 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 488490#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 487645#L914-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 487077#L919-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 487078#L924-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 487986#L929-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 487987#L934-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 488124#L939-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 488125#L944-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 486845#L949-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 486846#L954-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 488160#L959-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 487400#L964-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 487401#L969-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 488059#L974-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 487296#L979-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 487297#L1291 assume !(0 == ~M_E~0); 488491#L1291-2 assume !(0 == ~T1_E~0); 488487#L1296-1 assume !(0 == ~T2_E~0); 487465#L1301-1 assume !(0 == ~T3_E~0); 487466#L1306-1 assume !(0 == ~T4_E~0); 488075#L1311-1 assume !(0 == ~T5_E~0); 486688#L1316-1 assume !(0 == ~T6_E~0); 486689#L1321-1 assume !(0 == ~T7_E~0); 487479#L1326-1 assume !(0 == ~T8_E~0); 486514#L1331-1 assume !(0 == ~T9_E~0); 486217#L1336-1 assume !(0 == ~T10_E~0); 486218#L1341-1 assume !(0 == ~T11_E~0); 486296#L1346-1 assume !(0 == ~T12_E~0); 486297#L1351-1 assume !(0 == ~T13_E~0); 486634#L1356-1 assume !(0 == ~E_M~0); 486635#L1361-1 assume !(0 == ~E_1~0); 488381#L1366-1 assume !(0 == ~E_2~0); 486677#L1371-1 assume !(0 == ~E_3~0); 486678#L1376-1 assume !(0 == ~E_4~0); 487532#L1381-1 assume !(0 == ~E_5~0); 487533#L1386-1 assume !(0 == ~E_6~0); 488428#L1391-1 assume !(0 == ~E_7~0); 488462#L1396-1 assume !(0 == ~E_8~0); 487432#L1401-1 assume !(0 == ~E_9~0); 487433#L1406-1 assume !(0 == ~E_10~0); 487738#L1411-1 assume !(0 == ~E_11~0); 487739#L1416-1 assume !(0 == ~E_12~0); 487344#L1421-1 assume !(0 == ~E_13~0); 486869#L1426-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 486870#L640 assume !(1 == ~m_pc~0); 487396#L640-2 is_master_triggered_~__retres1~0#1 := 0; 487395#L651 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 487495#L652 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 487381#L1603 assume !(0 != activate_threads_~tmp~1#1); 487382#L1603-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 487005#L659 assume !(1 == ~t1_pc~0); 487006#L659-2 is_transmit1_triggered_~__retres1~1#1 := 0; 488226#L670 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 488193#L671 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 487130#L1611 assume !(0 != activate_threads_~tmp___0~0#1); 487131#L1611-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 487146#L678 assume !(1 == ~t2_pc~0); 488367#L678-2 is_transmit2_triggered_~__retres1~2#1 := 0; 488421#L689 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 488422#L690 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 487245#L1619 assume !(0 != activate_threads_~tmp___1~0#1); 487246#L1619-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 487376#L697 assume !(1 == ~t3_pc~0); 487377#L697-2 is_transmit3_triggered_~__retres1~3#1 := 0; 487511#L708 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 488291#L709 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 487281#L1627 assume !(0 != activate_threads_~tmp___2~0#1); 487282#L1627-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 488321#L716 assume !(1 == ~t4_pc~0); 487823#L716-2 is_transmit4_triggered_~__retres1~4#1 := 0; 486984#L727 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 486985#L728 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 486477#L1635 assume !(0 != activate_threads_~tmp___3~0#1); 486478#L1635-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 487835#L735 assume !(1 == ~t5_pc~0); 486438#L735-2 is_transmit5_triggered_~__retres1~5#1 := 0; 486439#L746 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 486894#L747 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 487871#L1643 assume !(0 != activate_threads_~tmp___4~0#1); 487457#L1643-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 487458#L754 assume !(1 == ~t6_pc~0); 487697#L754-2 is_transmit6_triggered_~__retres1~6#1 := 0; 487091#L765 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 487092#L766 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 487064#L1651 assume !(0 != activate_threads_~tmp___5~0#1); 487065#L1651-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 487976#L773 assume !(1 == ~t7_pc~0); 486638#L773-2 is_transmit7_triggered_~__retres1~7#1 := 0; 486637#L784 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 487496#L785 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 487467#L1659 assume !(0 != activate_threads_~tmp___6~0#1); 487468#L1659-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 487522#L792 assume !(1 == ~t8_pc~0); 487709#L792-2 is_transmit8_triggered_~__retres1~8#1 := 0; 488128#L803 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 487516#L804 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 487460#L1667 assume !(0 != activate_threads_~tmp___7~0#1); 487379#L1667-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 487380#L811 assume 1 == ~t9_pc~0; 487603#L812 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 488172#L822 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 488009#L823 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 487598#L1675 assume !(0 != activate_threads_~tmp___8~0#1); 487392#L1675-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 487393#L830 assume !(1 == ~t10_pc~0); 487101#L830-2 is_transmit10_triggered_~__retres1~10#1 := 0; 486618#L841 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 486313#L842 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 486314#L1683 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 486600#L1683-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 487997#L849 assume 1 == ~t11_pc~0; 487998#L850 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 486414#L860 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 486415#L861 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 487012#L1691 assume !(0 != activate_threads_~tmp___10~0#1); 487879#L1691-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 487880#L868 assume !(1 == ~t12_pc~0); 487230#L868-2 is_transmit12_triggered_~__retres1~12#1 := 0; 487229#L879 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 487021#L880 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 487022#L1699 assume !(0 != activate_threads_~tmp___11~0#1); 486650#L1699-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 486651#L887 assume 1 == ~t13_pc~0; 487896#L888 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 487275#L898 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 487276#L899 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 487747#L1707 assume !(0 != activate_threads_~tmp___12~0#1); 486356#L1707-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 486357#L1439 assume !(1 == ~M_E~0); 487453#L1439-2 assume !(1 == ~T1_E~0); 486526#L1444-1 assume !(1 == ~T2_E~0); 486527#L1449-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 487008#L1454-1 assume !(1 == ~T4_E~0); 487009#L1459-1 assume !(1 == ~T5_E~0); 487595#L1464-1 assume !(1 == ~T6_E~0); 487596#L1469-1 assume !(1 == ~T7_E~0); 487676#L1474-1 assume !(1 == ~T8_E~0); 487345#L1479-1 assume !(1 == ~T9_E~0); 487346#L1484-1 assume !(1 == ~T10_E~0); 487599#L1489-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 487218#L1494-1 assume !(1 == ~T12_E~0); 487219#L1499-1 assume !(1 == ~T13_E~0); 487421#L1504-1 assume !(1 == ~E_M~0); 487422#L1509-1 assume !(1 == ~E_1~0); 488110#L1514-1 assume !(1 == ~E_2~0); 487710#L1519-1 assume !(1 == ~E_3~0); 487711#L1524-1 assume !(1 == ~E_4~0); 488402#L1529-1 assume 1 == ~E_5~0;~E_5~0 := 2; 488403#L1534-1 assume !(1 == ~E_6~0); 486349#L1539-1 assume !(1 == ~E_7~0); 486350#L1544-1 assume !(1 == ~E_8~0); 486765#L1549-1 assume !(1 == ~E_9~0); 488360#L1554-1 assume !(1 == ~E_10~0); 488354#L1559-1 assume !(1 == ~E_11~0); 488152#L1564-1 assume !(1 == ~E_12~0); 488153#L1569-1 assume 1 == ~E_13~0;~E_13~0 := 2; 488397#L1574-1 assume { :end_inline_reset_delta_events } true; 488437#L1940-2 [2021-12-16 10:05:47,957 INFO L793 eck$LassoCheckResult]: Loop: 488437#L1940-2 assume !false; 566111#L1941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 566104#L1266 assume !false; 566102#L1075 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 564747#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 564738#L1064 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 564736#L1065 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 564735#L1079 assume !(0 != eval_~tmp~0#1); 487151#L1281 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 487152#L907-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 487809#L1291-3 assume !(0 == ~M_E~0); 487677#L1291-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 487678#L1296-3 assume !(0 == ~T2_E~0); 488495#L1301-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 585439#L1306-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 585438#L1311-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 585437#L1316-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 585436#L1321-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 585435#L1326-3 assume !(0 == ~T8_E~0); 585434#L1331-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 585433#L1336-3 assume !(0 == ~T10_E~0); 585432#L1341-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 585431#L1346-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 585430#L1351-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 585429#L1356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 585428#L1361-3 assume 0 == ~E_1~0;~E_1~0 := 1; 585427#L1366-3 assume !(0 == ~E_2~0); 585426#L1371-3 assume 0 == ~E_3~0;~E_3~0 := 1; 585425#L1376-3 assume !(0 == ~E_4~0); 488331#L1381-3 assume 0 == ~E_5~0;~E_5~0 := 1; 488332#L1386-3 assume 0 == ~E_6~0;~E_6~0 := 1; 585424#L1391-3 assume 0 == ~E_7~0;~E_7~0 := 1; 585423#L1396-3 assume 0 == ~E_8~0;~E_8~0 := 1; 585422#L1401-3 assume 0 == ~E_9~0;~E_9~0 := 1; 585421#L1406-3 assume !(0 == ~E_10~0); 585420#L1411-3 assume 0 == ~E_11~0;~E_11~0 := 1; 488450#L1416-3 assume !(0 == ~E_12~0); 488451#L1421-3 assume 0 == ~E_13~0;~E_13~0 := 1; 487985#L1426-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 487271#L640-45 assume 1 == ~m_pc~0; 487273#L641-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 486726#L651-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 486727#L652-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 486265#L1603-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 486266#L1603-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 486364#L659-45 assume !(1 == ~t1_pc~0); 486365#L659-47 is_transmit1_triggered_~__retres1~1#1 := 0; 486805#L670-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 487828#L671-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 487829#L1611-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 487853#L1611-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 487854#L678-45 assume !(1 == ~t2_pc~0); 487815#L678-47 is_transmit2_triggered_~__retres1~2#1 := 0; 487277#L689-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 487278#L690-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 487438#L1619-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 488184#L1619-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 488370#L697-45 assume !(1 == ~t3_pc~0); 487557#L697-47 is_transmit3_triggered_~__retres1~3#1 := 0; 488106#L708-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 488292#L709-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 487727#L1627-45 assume !(0 != activate_threads_~tmp___2~0#1); 487728#L1627-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 487765#L716-45 assume !(1 == ~t4_pc~0); 488537#L716-47 is_transmit4_triggered_~__retres1~4#1 := 0; 581756#L727-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 581753#L728-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 581751#L1635-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 581749#L1635-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 581747#L735-45 assume 1 == ~t5_pc~0; 581744#L736-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 581742#L746-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 581740#L747-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 581699#L1643-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 581692#L1643-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 488394#L754-45 assume !(1 == ~t6_pc~0); 488395#L754-47 is_transmit6_triggered_~__retres1~6#1 := 0; 578698#L765-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 578697#L766-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 578696#L1651-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 578695#L1651-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 578694#L773-45 assume 1 == ~t7_pc~0; 578692#L774-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 578691#L784-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 578689#L785-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 578688#L1659-45 assume !(0 != activate_threads_~tmp___6~0#1); 578687#L1659-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 578686#L792-45 assume !(1 == ~t8_pc~0); 520585#L792-47 is_transmit8_triggered_~__retres1~8#1 := 0; 578684#L803-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 578682#L804-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 578680#L1667-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 578678#L1667-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 578674#L811-45 assume !(1 == ~t9_pc~0); 578671#L811-47 is_transmit9_triggered_~__retres1~9#1 := 0; 578669#L822-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 578667#L823-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 578664#L1675-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 578662#L1675-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 578660#L830-45 assume 1 == ~t10_pc~0; 578656#L831-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 578654#L841-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 578652#L842-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 578650#L1683-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 578648#L1683-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 578646#L849-45 assume !(1 == ~t11_pc~0); 578643#L849-47 is_transmit11_triggered_~__retres1~11#1 := 0; 578641#L860-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 578639#L861-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 578620#L1691-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 578614#L1691-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 578608#L868-45 assume 1 == ~t12_pc~0; 578600#L869-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 578595#L879-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 578540#L880-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 578513#L1699-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 578510#L1699-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 578506#L887-45 assume !(1 == ~t13_pc~0); 578456#L887-47 is_transmit13_triggered_~__retres1~13#1 := 0; 578334#L898-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 578209#L899-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 578163#L1707-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 578162#L1707-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 487912#L1439-3 assume !(1 == ~M_E~0); 487913#L1439-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 572460#L1444-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 572458#L1449-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 572456#L1454-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 572454#L1459-3 assume !(1 == ~T5_E~0); 572452#L1464-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 572449#L1469-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 572447#L1474-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 572445#L1479-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 572443#L1484-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 572441#L1489-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 572439#L1494-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 572438#L1499-3 assume !(1 == ~T13_E~0); 572436#L1504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 572434#L1509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 572432#L1514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 572430#L1519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 572428#L1524-3 assume 1 == ~E_4~0;~E_4~0 := 2; 572425#L1529-3 assume 1 == ~E_5~0;~E_5~0 := 2; 572423#L1534-3 assume 1 == ~E_6~0;~E_6~0 := 2; 572421#L1539-3 assume !(1 == ~E_7~0); 572419#L1544-3 assume 1 == ~E_8~0;~E_8~0 := 2; 572417#L1549-3 assume 1 == ~E_9~0;~E_9~0 := 2; 572415#L1554-3 assume 1 == ~E_10~0;~E_10~0 := 2; 572412#L1559-3 assume 1 == ~E_11~0;~E_11~0 := 2; 572410#L1564-3 assume 1 == ~E_12~0;~E_12~0 := 2; 572408#L1569-3 assume 1 == ~E_13~0;~E_13~0 := 2; 572406#L1574-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 572398#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 572384#L1064-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 572382#L1065-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 572380#L1959 assume !(0 == start_simulation_~tmp~3#1); 572376#L1959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 572370#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 572356#L1064-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 572353#L1065-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 572351#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 572350#L1921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 572349#L1922 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 572348#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 488437#L1940-2 [2021-12-16 10:05:47,957 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:47,957 INFO L85 PathProgramCache]: Analyzing trace with hash -618334264, now seen corresponding path program 1 times [2021-12-16 10:05:47,958 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:47,958 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [633358924] [2021-12-16 10:05:47,958 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:47,958 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:47,967 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:47,991 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:05:47,991 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:47,991 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [633358924] [2021-12-16 10:05:47,991 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [633358924] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:47,991 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:47,992 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:05:47,992 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1137280798] [2021-12-16 10:05:47,992 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:47,992 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:05:47,993 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:47,993 INFO L85 PathProgramCache]: Analyzing trace with hash 1365787807, now seen corresponding path program 1 times [2021-12-16 10:05:47,993 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:47,993 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [176754783] [2021-12-16 10:05:47,993 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:47,993 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:48,003 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:48,025 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:05:48,025 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:48,026 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [176754783] [2021-12-16 10:05:48,026 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [176754783] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:48,026 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:48,026 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:05:48,026 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1611304633] [2021-12-16 10:05:48,026 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:48,027 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:05:48,027 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:05:48,028 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-16 10:05:48,028 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-16 10:05:48,028 INFO L87 Difference]: Start difference. First operand 99229 states and 141874 transitions. cyclomatic complexity: 42647 Second operand has 4 states, 4 states have (on average 40.25) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:49,125 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:05:49,126 INFO L93 Difference]: Finished difference Result 237308 states and 337695 transitions. [2021-12-16 10:05:49,126 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-16 10:05:49,126 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 237308 states and 337695 transitions. [2021-12-16 10:05:50,601 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 236848 [2021-12-16 10:05:51,615 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 237308 states to 237308 states and 337695 transitions. [2021-12-16 10:05:51,616 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 237308 [2021-12-16 10:05:51,702 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 237308 [2021-12-16 10:05:51,703 INFO L73 IsDeterministic]: Start isDeterministic. Operand 237308 states and 337695 transitions. [2021-12-16 10:05:51,793 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:05:51,793 INFO L681 BuchiCegarLoop]: Abstraction has 237308 states and 337695 transitions. [2021-12-16 10:05:51,914 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 237308 states and 337695 transitions. [2021-12-16 10:05:53,781 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 237308 to 190892. [2021-12-16 10:05:53,942 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 190892 states, 190892 states have (on average 1.4255547639502966) internal successors, (272127), 190891 states have internal predecessors, (272127), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:54,309 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 190892 states to 190892 states and 272127 transitions. [2021-12-16 10:05:54,310 INFO L704 BuchiCegarLoop]: Abstraction has 190892 states and 272127 transitions. [2021-12-16 10:05:54,310 INFO L587 BuchiCegarLoop]: Abstraction has 190892 states and 272127 transitions. [2021-12-16 10:05:54,310 INFO L425 BuchiCegarLoop]: ======== Iteration 25============ [2021-12-16 10:05:54,310 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 190892 states and 272127 transitions. [2021-12-16 10:05:54,898 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 190656 [2021-12-16 10:05:54,898 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:05:54,898 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:05:54,911 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:54,912 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:54,912 INFO L791 eck$LassoCheckResult]: Stem: 823699#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 823700#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 824889#L1903 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 824890#L907 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 825050#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 824193#L914-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 823626#L919-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 823627#L924-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 824532#L929-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 824533#L934-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 824664#L939-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 824665#L944-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 823393#L949-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 823394#L954-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 824700#L959-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 823950#L964-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 823951#L969-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 824599#L974-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 823845#L979-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 823846#L1291 assume !(0 == ~M_E~0); 825051#L1291-2 assume !(0 == ~T1_E~0); 825048#L1296-1 assume !(0 == ~T2_E~0); 824011#L1301-1 assume !(0 == ~T3_E~0); 824012#L1306-1 assume !(0 == ~T4_E~0); 824612#L1311-1 assume !(0 == ~T5_E~0); 823233#L1316-1 assume !(0 == ~T6_E~0); 823234#L1321-1 assume !(0 == ~T7_E~0); 824026#L1326-1 assume !(0 == ~T8_E~0); 823063#L1331-1 assume !(0 == ~T9_E~0); 822764#L1336-1 assume !(0 == ~T10_E~0); 822765#L1341-1 assume !(0 == ~T11_E~0); 822843#L1346-1 assume !(0 == ~T12_E~0); 822844#L1351-1 assume !(0 == ~T13_E~0); 823184#L1356-1 assume !(0 == ~E_M~0); 823185#L1361-1 assume !(0 == ~E_1~0); 824934#L1366-1 assume !(0 == ~E_2~0); 823223#L1371-1 assume !(0 == ~E_3~0); 823224#L1376-1 assume !(0 == ~E_4~0); 824081#L1381-1 assume !(0 == ~E_5~0); 824082#L1386-1 assume !(0 == ~E_6~0); 824982#L1391-1 assume !(0 == ~E_7~0); 825023#L1396-1 assume !(0 == ~E_8~0); 823981#L1401-1 assume !(0 == ~E_9~0); 823982#L1406-1 assume !(0 == ~E_10~0); 824290#L1411-1 assume !(0 == ~E_11~0); 824291#L1416-1 assume !(0 == ~E_12~0); 823891#L1421-1 assume !(0 == ~E_13~0); 823417#L1426-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 823418#L640 assume !(1 == ~m_pc~0); 823947#L640-2 is_master_triggered_~__retres1~0#1 := 0; 823946#L651 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 824044#L652 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 823931#L1603 assume !(0 != activate_threads_~tmp~1#1); 823932#L1603-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 823556#L659 assume !(1 == ~t1_pc~0); 823557#L659-2 is_transmit1_triggered_~__retres1~1#1 := 0; 824771#L670 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 824735#L671 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 823681#L1611 assume !(0 != activate_threads_~tmp___0~0#1); 823682#L1611-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 823696#L678 assume !(1 == ~t2_pc~0); 824915#L678-2 is_transmit2_triggered_~__retres1~2#1 := 0; 824975#L689 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 824976#L690 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 823796#L1619 assume !(0 != activate_threads_~tmp___1~0#1); 823797#L1619-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 823926#L697 assume !(1 == ~t3_pc~0); 823927#L697-2 is_transmit3_triggered_~__retres1~3#1 := 0; 824058#L708 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 824838#L709 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 823831#L1627 assume !(0 != activate_threads_~tmp___2~0#1); 823832#L1627-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 824866#L716 assume !(1 == ~t4_pc~0); 824373#L716-2 is_transmit4_triggered_~__retres1~4#1 := 0; 823535#L727 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 823536#L728 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 823025#L1635 assume !(0 != activate_threads_~tmp___3~0#1); 823026#L1635-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 824386#L735 assume !(1 == ~t5_pc~0); 822985#L735-2 is_transmit5_triggered_~__retres1~5#1 := 0; 822986#L746 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 823444#L747 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 824418#L1643 assume !(0 != activate_threads_~tmp___4~0#1); 824005#L1643-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 824006#L754 assume !(1 == ~t6_pc~0); 824247#L754-2 is_transmit6_triggered_~__retres1~6#1 := 0; 823641#L765 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 823642#L766 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 823613#L1651 assume !(0 != activate_threads_~tmp___5~0#1); 823614#L1651-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 824523#L773 assume !(1 == ~t7_pc~0); 823188#L773-2 is_transmit7_triggered_~__retres1~7#1 := 0; 823187#L784 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 824045#L785 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 824013#L1659 assume !(0 != activate_threads_~tmp___6~0#1); 824014#L1659-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 824071#L792 assume !(1 == ~t8_pc~0); 824260#L792-2 is_transmit8_triggered_~__retres1~8#1 := 0; 824668#L803 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 824065#L804 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 824008#L1667 assume !(0 != activate_threads_~tmp___7~0#1); 823929#L1667-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 823930#L811 assume !(1 == ~t9_pc~0); 824151#L811-2 is_transmit9_triggered_~__retres1~9#1 := 0; 824750#L822 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 824553#L823 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 824147#L1675 assume !(0 != activate_threads_~tmp___8~0#1); 823943#L1675-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 823944#L830 assume !(1 == ~t10_pc~0); 823652#L830-2 is_transmit10_triggered_~__retres1~10#1 := 0; 823168#L841 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 822861#L842 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 822862#L1683 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 823150#L1683-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 824543#L849 assume 1 == ~t11_pc~0; 824544#L850 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 822961#L860 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 822962#L861 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 823563#L1691 assume !(0 != activate_threads_~tmp___10~0#1); 824425#L1691-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 824426#L868 assume !(1 == ~t12_pc~0); 823781#L868-2 is_transmit12_triggered_~__retres1~12#1 := 0; 823780#L879 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 823572#L880 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 823573#L1699 assume !(0 != activate_threads_~tmp___11~0#1); 823200#L1699-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 823201#L887 assume 1 == ~t13_pc~0; 824442#L888 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 823825#L898 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 823826#L899 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 824300#L1707 assume !(0 != activate_threads_~tmp___12~0#1); 822903#L1707-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 822904#L1439 assume !(1 == ~M_E~0); 824001#L1439-2 assume !(1 == ~T1_E~0); 823075#L1444-1 assume !(1 == ~T2_E~0); 823076#L1449-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 823559#L1454-1 assume !(1 == ~T4_E~0); 823560#L1459-1 assume !(1 == ~T5_E~0); 824143#L1464-1 assume !(1 == ~T6_E~0); 824144#L1469-1 assume !(1 == ~T7_E~0); 824226#L1474-1 assume !(1 == ~T8_E~0); 823892#L1479-1 assume !(1 == ~T9_E~0); 823893#L1484-1 assume !(1 == ~T10_E~0); 824148#L1489-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 823769#L1494-1 assume !(1 == ~T12_E~0); 823770#L1499-1 assume !(1 == ~T13_E~0); 823970#L1504-1 assume !(1 == ~E_M~0); 823971#L1509-1 assume !(1 == ~E_1~0); 824647#L1514-1 assume !(1 == ~E_2~0); 824261#L1519-1 assume !(1 == ~E_3~0); 824262#L1524-1 assume !(1 == ~E_4~0); 824956#L1529-1 assume 1 == ~E_5~0;~E_5~0 := 2; 824957#L1534-1 assume !(1 == ~E_6~0); 822897#L1539-1 assume !(1 == ~E_7~0); 822898#L1544-1 assume !(1 == ~E_8~0); 823310#L1549-1 assume !(1 == ~E_9~0); 824909#L1554-1 assume !(1 == ~E_10~0); 824905#L1559-1 assume !(1 == ~E_11~0); 824693#L1564-1 assume !(1 == ~E_12~0); 824694#L1569-1 assume 1 == ~E_13~0;~E_13~0 := 2; 824949#L1574-1 assume { :end_inline_reset_delta_events } true; 824994#L1940-2 [2021-12-16 10:05:54,913 INFO L793 eck$LassoCheckResult]: Loop: 824994#L1940-2 assume !false; 965961#L1941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 965956#L1266 assume !false; 965955#L1075 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 965923#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 965913#L1064 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 965910#L1065 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 965907#L1079 assume !(0 != eval_~tmp~0#1); 965908#L1281 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1013337#L907-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1013335#L1291-3 assume !(0 == ~M_E~0); 1013333#L1291-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1013331#L1296-3 assume !(0 == ~T2_E~0); 1013329#L1301-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1013327#L1306-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1013324#L1311-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1013322#L1316-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1013320#L1321-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1013318#L1326-3 assume !(0 == ~T8_E~0); 1013316#L1331-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1013314#L1336-3 assume !(0 == ~T10_E~0); 1013312#L1341-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 1013311#L1346-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 1013310#L1351-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 1013308#L1356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1013306#L1361-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1013304#L1366-3 assume !(0 == ~E_2~0); 1013303#L1371-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1013302#L1376-3 assume !(0 == ~E_4~0); 1013301#L1381-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1013300#L1386-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1013299#L1391-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1013298#L1396-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1013297#L1401-3 assume 0 == ~E_9~0;~E_9~0 := 1; 1013296#L1406-3 assume !(0 == ~E_10~0); 1013295#L1411-3 assume 0 == ~E_11~0;~E_11~0 := 1; 1013294#L1416-3 assume !(0 == ~E_12~0); 1013292#L1421-3 assume 0 == ~E_13~0;~E_13~0 := 1; 1013291#L1426-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1013288#L640-45 assume !(1 == ~m_pc~0); 1013286#L640-47 is_master_triggered_~__retres1~0#1 := 0; 1013283#L651-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1013281#L652-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1013279#L1603-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1013277#L1603-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1013275#L659-45 assume !(1 == ~t1_pc~0); 1013272#L659-47 is_transmit1_triggered_~__retres1~1#1 := 0; 1013273#L670-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1013309#L671-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1013307#L1611-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1013305#L1611-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 824857#L678-45 assume !(1 == ~t2_pc~0); 824858#L678-47 is_transmit2_triggered_~__retres1~2#1 := 0; 1008390#L689-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1008388#L690-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1008386#L1619-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1008384#L1619-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1008382#L697-45 assume 1 == ~t3_pc~0; 1008380#L698-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1008381#L708-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1008460#L709-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1008369#L1627-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1008367#L1627-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1008365#L716-45 assume !(1 == ~t4_pc~0); 991488#L716-47 is_transmit4_triggered_~__retres1~4#1 := 0; 1008362#L727-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1008360#L728-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1008358#L1635-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1008356#L1635-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1008354#L735-45 assume 1 == ~t5_pc~0; 1008351#L736-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1008349#L746-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1008347#L747-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1008346#L1643-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1008344#L1643-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1008342#L754-45 assume !(1 == ~t6_pc~0); 994467#L754-47 is_transmit6_triggered_~__retres1~6#1 := 0; 1008339#L765-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1008337#L766-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1008335#L1651-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1008333#L1651-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1008331#L773-45 assume !(1 == ~t7_pc~0); 1008329#L773-47 is_transmit7_triggered_~__retres1~7#1 := 0; 1008326#L784-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1008324#L785-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1008321#L1659-45 assume !(0 != activate_threads_~tmp___6~0#1); 1008319#L1659-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 966222#L792-45 assume !(1 == ~t8_pc~0); 966221#L792-47 is_transmit8_triggered_~__retres1~8#1 := 0; 966220#L803-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 966219#L804-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 966218#L1667-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 966217#L1667-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 966149#L811-45 assume !(1 == ~t9_pc~0); 871339#L811-47 is_transmit9_triggered_~__retres1~9#1 := 0; 966147#L822-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 966145#L823-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 966143#L1675-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 966141#L1675-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 966139#L830-45 assume 1 == ~t10_pc~0; 966136#L831-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 966135#L841-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 966133#L842-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 966131#L1683-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 966129#L1683-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 966127#L849-45 assume !(1 == ~t11_pc~0); 966124#L849-47 is_transmit11_triggered_~__retres1~11#1 := 0; 966121#L860-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 966119#L861-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 966117#L1691-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 966115#L1691-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 966113#L868-45 assume 1 == ~t12_pc~0; 966110#L869-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 966107#L879-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 966105#L880-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 966103#L1699-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 966101#L1699-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 966099#L887-45 assume !(1 == ~t13_pc~0); 966096#L887-47 is_transmit13_triggered_~__retres1~13#1 := 0; 966093#L898-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 966091#L899-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 966089#L1707-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 966087#L1707-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 966085#L1439-3 assume !(1 == ~M_E~0); 966081#L1439-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 966078#L1444-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 966076#L1449-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 966074#L1454-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 966072#L1459-3 assume !(1 == ~T5_E~0); 966070#L1464-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 966067#L1469-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 966065#L1474-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 966063#L1479-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 966061#L1484-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 966059#L1489-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 966057#L1494-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 966055#L1499-3 assume !(1 == ~T13_E~0); 966053#L1504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 966051#L1509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 966049#L1514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 966047#L1519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 966045#L1524-3 assume 1 == ~E_4~0;~E_4~0 := 2; 966043#L1529-3 assume 1 == ~E_5~0;~E_5~0 := 2; 966041#L1534-3 assume 1 == ~E_6~0;~E_6~0 := 2; 966039#L1539-3 assume !(1 == ~E_7~0); 966037#L1544-3 assume 1 == ~E_8~0;~E_8~0 := 2; 966035#L1549-3 assume 1 == ~E_9~0;~E_9~0 := 2; 966033#L1554-3 assume 1 == ~E_10~0;~E_10~0 := 2; 966031#L1559-3 assume 1 == ~E_11~0;~E_11~0 := 2; 966029#L1564-3 assume 1 == ~E_12~0;~E_12~0 := 2; 966027#L1569-3 assume 1 == ~E_13~0;~E_13~0 := 2; 966025#L1574-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 966019#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 966005#L1064-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 966003#L1065-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 966001#L1959 assume !(0 == start_simulation_~tmp~3#1); 965999#L1959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 965997#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 965981#L1064-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 965979#L1065-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 965977#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 965976#L1921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 965971#L1922 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 965966#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 824994#L1940-2 [2021-12-16 10:05:54,913 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:54,914 INFO L85 PathProgramCache]: Analyzing trace with hash -1649665079, now seen corresponding path program 1 times [2021-12-16 10:05:54,914 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:54,914 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1316051508] [2021-12-16 10:05:54,914 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:54,914 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:54,926 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:55,526 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:05:55,527 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:55,527 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1316051508] [2021-12-16 10:05:55,527 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1316051508] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:55,527 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:55,527 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-16 10:05:55,529 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [223199612] [2021-12-16 10:05:55,529 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:55,530 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:05:55,530 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:55,530 INFO L85 PathProgramCache]: Analyzing trace with hash -1151485730, now seen corresponding path program 1 times [2021-12-16 10:05:55,532 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:55,532 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [437863589] [2021-12-16 10:05:55,532 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:55,532 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:55,564 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:55,615 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:05:55,616 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:55,616 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [437863589] [2021-12-16 10:05:55,616 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [437863589] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:55,616 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:55,616 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:05:55,617 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [52815473] [2021-12-16 10:05:55,617 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:55,617 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:05:55,617 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:05:55,618 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-16 10:05:55,618 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-16 10:05:55,618 INFO L87 Difference]: Start difference. First operand 190892 states and 272127 transitions. cyclomatic complexity: 81237 Second operand has 5 states, 5 states have (on average 32.2) internal successors, (161), 5 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:57,779 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:05:57,779 INFO L93 Difference]: Finished difference Result 445845 states and 641072 transitions. [2021-12-16 10:05:57,779 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-16 10:05:57,780 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 445845 states and 641072 transitions. [2021-12-16 10:06:00,534 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 445376 [2021-12-16 10:06:01,676 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 445845 states to 445845 states and 641072 transitions. [2021-12-16 10:06:01,677 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 445845 [2021-12-16 10:06:02,428 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 445845 [2021-12-16 10:06:02,429 INFO L73 IsDeterministic]: Start isDeterministic. Operand 445845 states and 641072 transitions. [2021-12-16 10:06:02,572 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:06:02,573 INFO L681 BuchiCegarLoop]: Abstraction has 445845 states and 641072 transitions. [2021-12-16 10:06:02,835 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 445845 states and 641072 transitions. [2021-12-16 10:06:05,266 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 445845 to 195695. [2021-12-16 10:06:05,428 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 195695 states, 195695 states have (on average 1.4151102480901403) internal successors, (276930), 195694 states have internal predecessors, (276930), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:06,463 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 195695 states to 195695 states and 276930 transitions. [2021-12-16 10:06:06,463 INFO L704 BuchiCegarLoop]: Abstraction has 195695 states and 276930 transitions. [2021-12-16 10:06:06,463 INFO L587 BuchiCegarLoop]: Abstraction has 195695 states and 276930 transitions. [2021-12-16 10:06:06,463 INFO L425 BuchiCegarLoop]: ======== Iteration 26============ [2021-12-16 10:06:06,463 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 195695 states and 276930 transitions. [2021-12-16 10:06:07,006 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 195456 [2021-12-16 10:06:07,006 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:06:07,006 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:06:07,016 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:07,017 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:07,017 INFO L791 eck$LassoCheckResult]: Stem: 1460460#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 1460461#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 1461676#L1903 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1461677#L907 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1461832#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 1460976#L914-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1460383#L919-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1460384#L924-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1461332#L929-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1461333#L934-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1461461#L939-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1461462#L944-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1460148#L949-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1460149#L954-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1461496#L959-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 1460729#L964-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 1460730#L969-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 1461393#L974-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 1460619#L979-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1460620#L1291 assume !(0 == ~M_E~0); 1461833#L1291-2 assume !(0 == ~T1_E~0); 1461830#L1296-1 assume !(0 == ~T2_E~0); 1460792#L1301-1 assume !(0 == ~T3_E~0); 1460793#L1306-1 assume !(0 == ~T4_E~0); 1461408#L1311-1 assume !(0 == ~T5_E~0); 1459985#L1316-1 assume !(0 == ~T6_E~0); 1459986#L1321-1 assume !(0 == ~T7_E~0); 1460807#L1326-1 assume !(0 == ~T8_E~0); 1459813#L1331-1 assume !(0 == ~T9_E~0); 1459514#L1336-1 assume !(0 == ~T10_E~0); 1459515#L1341-1 assume !(0 == ~T11_E~0); 1459593#L1346-1 assume !(0 == ~T12_E~0); 1459594#L1351-1 assume !(0 == ~T13_E~0); 1459935#L1356-1 assume !(0 == ~E_M~0); 1459936#L1361-1 assume !(0 == ~E_1~0); 1461725#L1366-1 assume !(0 == ~E_2~0); 1459975#L1371-1 assume !(0 == ~E_3~0); 1459976#L1376-1 assume !(0 == ~E_4~0); 1460860#L1381-1 assume !(0 == ~E_5~0); 1460861#L1386-1 assume !(0 == ~E_6~0); 1461776#L1391-1 assume !(0 == ~E_7~0); 1461804#L1396-1 assume !(0 == ~E_8~0); 1460760#L1401-1 assume !(0 == ~E_9~0); 1460761#L1406-1 assume !(0 == ~E_10~0); 1461075#L1411-1 assume !(0 == ~E_11~0); 1461076#L1416-1 assume !(0 == ~E_12~0); 1460670#L1421-1 assume !(0 == ~E_13~0); 1460173#L1426-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1460174#L640 assume !(1 == ~m_pc~0); 1460725#L640-2 is_master_triggered_~__retres1~0#1 := 0; 1460724#L651 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1460825#L652 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1460710#L1603 assume !(0 != activate_threads_~tmp~1#1); 1460711#L1603-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1460310#L659 assume !(1 == ~t1_pc~0); 1460311#L659-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1461569#L670 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1461533#L671 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1460443#L1611 assume !(0 != activate_threads_~tmp___0~0#1); 1460444#L1611-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1460458#L678 assume !(1 == ~t2_pc~0); 1461707#L678-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1461768#L689 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1461769#L690 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1460563#L1619 assume !(0 != activate_threads_~tmp___1~0#1); 1460564#L1619-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1460705#L697 assume !(1 == ~t3_pc~0); 1460706#L697-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1460839#L708 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1461624#L709 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1460602#L1627 assume !(0 != activate_threads_~tmp___2~0#1); 1460603#L1627-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1461656#L716 assume !(1 == ~t4_pc~0); 1461158#L716-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1460291#L727 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1460292#L728 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1459775#L1635 assume !(0 != activate_threads_~tmp___3~0#1); 1459776#L1635-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1461173#L735 assume !(1 == ~t5_pc~0); 1459735#L735-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1459736#L746 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1460195#L747 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1461209#L1643 assume !(0 != activate_threads_~tmp___4~0#1); 1460782#L1643-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1460783#L754 assume !(1 == ~t6_pc~0); 1461031#L754-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1460397#L765 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1460398#L766 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1460368#L1651 assume !(0 != activate_threads_~tmp___5~0#1); 1460369#L1651-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1461320#L773 assume !(1 == ~t7_pc~0); 1459939#L773-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1459938#L784 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1460826#L785 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1460794#L1659 assume !(0 != activate_threads_~tmp___6~0#1); 1460795#L1659-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1460850#L792 assume !(1 == ~t8_pc~0); 1461047#L792-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1461465#L803 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1460844#L804 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1460788#L1667 assume !(0 != activate_threads_~tmp___7~0#1); 1460708#L1667-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1460709#L811 assume !(1 == ~t9_pc~0); 1460934#L811-2 is_transmit9_triggered_~__retres1~9#1 := 0; 1461548#L822 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1461351#L823 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1460928#L1675 assume !(0 != activate_threads_~tmp___8~0#1); 1460721#L1675-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1460722#L830 assume !(1 == ~t10_pc~0); 1460411#L830-2 is_transmit10_triggered_~__retres1~10#1 := 0; 1459917#L841 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1459918#L842 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1459897#L1683 assume !(0 != activate_threads_~tmp___9~0#1); 1459898#L1683-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1461340#L849 assume 1 == ~t11_pc~0; 1461341#L850 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 1459711#L860 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1459712#L861 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1460319#L1691 assume !(0 != activate_threads_~tmp___10~0#1); 1461219#L1691-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1461220#L868 assume !(1 == ~t12_pc~0); 1460548#L868-2 is_transmit12_triggered_~__retres1~12#1 := 0; 1460547#L879 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1460326#L880 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 1460327#L1699 assume !(0 != activate_threads_~tmp___11~0#1); 1459951#L1699-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 1459952#L887 assume 1 == ~t13_pc~0; 1461236#L888 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 1460596#L898 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 1460597#L899 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 1461085#L1707 assume !(0 != activate_threads_~tmp___12~0#1); 1459652#L1707-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1459653#L1439 assume !(1 == ~M_E~0); 1460780#L1439-2 assume !(1 == ~T1_E~0); 1459825#L1444-1 assume !(1 == ~T2_E~0); 1459826#L1449-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1460315#L1454-1 assume !(1 == ~T4_E~0); 1460316#L1459-1 assume !(1 == ~T5_E~0); 1460925#L1464-1 assume !(1 == ~T6_E~0); 1460926#L1469-1 assume !(1 == ~T7_E~0); 1461013#L1474-1 assume !(1 == ~T8_E~0); 1460671#L1479-1 assume !(1 == ~T9_E~0); 1460672#L1484-1 assume !(1 == ~T10_E~0); 1460929#L1489-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 1460538#L1494-1 assume !(1 == ~T12_E~0); 1460539#L1499-1 assume !(1 == ~T13_E~0); 1460749#L1504-1 assume !(1 == ~E_M~0); 1460750#L1509-1 assume !(1 == ~E_1~0); 1461443#L1514-1 assume !(1 == ~E_2~0); 1461048#L1519-1 assume !(1 == ~E_3~0); 1461049#L1524-1 assume !(1 == ~E_4~0); 1461746#L1529-1 assume 1 == ~E_5~0;~E_5~0 := 2; 1461747#L1534-1 assume !(1 == ~E_6~0); 1459646#L1539-1 assume !(1 == ~E_7~0); 1459647#L1544-1 assume !(1 == ~E_8~0); 1460062#L1549-1 assume !(1 == ~E_9~0); 1461704#L1554-1 assume !(1 == ~E_10~0); 1461695#L1559-1 assume !(1 == ~E_11~0); 1461490#L1564-1 assume !(1 == ~E_12~0); 1461491#L1569-1 assume 1 == ~E_13~0;~E_13~0 := 2; 1461739#L1574-1 assume { :end_inline_reset_delta_events } true; 1461784#L1940-2 [2021-12-16 10:06:07,018 INFO L793 eck$LassoCheckResult]: Loop: 1461784#L1940-2 assume !false; 1549023#L1941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1549014#L1266 assume !false; 1549013#L1075 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 1548650#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 1548634#L1064 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 1548626#L1065 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1548542#L1079 assume !(0 != eval_~tmp~0#1); 1548543#L1281 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1558490#L907-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1558262#L1291-3 assume !(0 == ~M_E~0); 1558256#L1291-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1558253#L1296-3 assume !(0 == ~T2_E~0); 1558249#L1301-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1558245#L1306-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1558240#L1311-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1558235#L1316-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1558230#L1321-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1558225#L1326-3 assume !(0 == ~T8_E~0); 1558220#L1331-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1558215#L1336-3 assume !(0 == ~T10_E~0); 1558210#L1341-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 1558205#L1346-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 1558200#L1351-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 1558195#L1356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1558190#L1361-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1558185#L1366-3 assume !(0 == ~E_2~0); 1558180#L1371-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1558175#L1376-3 assume !(0 == ~E_4~0); 1558170#L1381-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1558165#L1386-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1558160#L1391-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1558155#L1396-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1558148#L1401-3 assume 0 == ~E_9~0;~E_9~0 := 1; 1558138#L1406-3 assume !(0 == ~E_10~0); 1558133#L1411-3 assume 0 == ~E_11~0;~E_11~0 := 1; 1558130#L1416-3 assume !(0 == ~E_12~0); 1558127#L1421-3 assume 0 == ~E_13~0;~E_13~0 := 1; 1557977#L1426-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1555223#L640-45 assume 1 == ~m_pc~0; 1555225#L641-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1555115#L651-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1555116#L652-15 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1555107#L1603-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1555108#L1603-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1555099#L659-45 assume !(1 == ~t1_pc~0); 1555100#L659-47 is_transmit1_triggered_~__retres1~1#1 := 0; 1555091#L670-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1555092#L671-15 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1555083#L1611-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1555084#L1611-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1555038#L678-45 assume !(1 == ~t2_pc~0); 1555036#L678-47 is_transmit2_triggered_~__retres1~2#1 := 0; 1555035#L689-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1555033#L690-15 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1555031#L1619-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1555029#L1619-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1555027#L697-45 assume !(1 == ~t3_pc~0); 1555025#L697-47 is_transmit3_triggered_~__retres1~3#1 := 0; 1555021#L708-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1555017#L709-15 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1555013#L1627-45 assume !(0 != activate_threads_~tmp___2~0#1); 1555009#L1627-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1550398#L716-45 assume !(1 == ~t4_pc~0); 1550395#L716-47 is_transmit4_triggered_~__retres1~4#1 := 0; 1550392#L727-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1550389#L728-15 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1550386#L1635-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1550384#L1635-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1550382#L735-45 assume !(1 == ~t5_pc~0); 1550379#L735-47 is_transmit5_triggered_~__retres1~5#1 := 0; 1550376#L746-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1550374#L747-15 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1550372#L1643-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1550370#L1643-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1550368#L754-45 assume !(1 == ~t6_pc~0); 1508815#L754-47 is_transmit6_triggered_~__retres1~6#1 := 0; 1550364#L765-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1550362#L766-15 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1550360#L1651-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1550358#L1651-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1550356#L773-45 assume !(1 == ~t7_pc~0); 1550355#L773-47 is_transmit7_triggered_~__retres1~7#1 := 0; 1550351#L784-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1550347#L785-15 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1550344#L1659-45 assume !(0 != activate_threads_~tmp___6~0#1); 1550341#L1659-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1550338#L792-45 assume !(1 == ~t8_pc~0); 1541305#L792-47 is_transmit8_triggered_~__retres1~8#1 := 0; 1550332#L803-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1550329#L804-15 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1550326#L1667-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1550323#L1667-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1550320#L811-45 assume !(1 == ~t9_pc~0); 1525349#L811-47 is_transmit9_triggered_~__retres1~9#1 := 0; 1550316#L822-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1550314#L823-15 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1550309#L1675-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1550307#L1675-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1550306#L830-45 assume !(1 == ~t10_pc~0); 1550305#L830-47 is_transmit10_triggered_~__retres1~10#1 := 0; 1550303#L841-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1550301#L842-15 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1550299#L1683-45 assume !(0 != activate_threads_~tmp___9~0#1); 1550295#L1683-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1550293#L849-45 assume 1 == ~t11_pc~0; 1550290#L850-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 1550287#L860-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1550284#L861-15 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1550282#L1691-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 1550280#L1691-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1550279#L868-45 assume !(1 == ~t12_pc~0); 1550218#L868-47 is_transmit12_triggered_~__retres1~12#1 := 0; 1550208#L879-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1550199#L880-15 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 1550188#L1699-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 1550178#L1699-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 1550169#L887-45 assume 1 == ~t13_pc~0; 1550161#L888-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 1550158#L898-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 1550154#L899-15 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 1550152#L1707-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 1550103#L1707-47 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1550066#L1439-3 assume !(1 == ~M_E~0); 1541459#L1439-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1550063#L1444-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1550061#L1449-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1550059#L1454-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1550056#L1459-3 assume !(1 == ~T5_E~0); 1550053#L1464-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1549876#L1469-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1549837#L1474-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1549830#L1479-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1549822#L1484-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 1549814#L1489-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 1549806#L1494-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 1549564#L1499-3 assume !(1 == ~T13_E~0); 1549562#L1504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1549560#L1509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1549557#L1514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1549555#L1519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1549553#L1524-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1549551#L1529-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1549549#L1534-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1549547#L1539-3 assume !(1 == ~E_7~0); 1549544#L1544-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1549542#L1549-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1549540#L1554-3 assume 1 == ~E_10~0;~E_10~0 := 2; 1549538#L1559-3 assume 1 == ~E_11~0;~E_11~0 := 2; 1549536#L1564-3 assume 1 == ~E_12~0;~E_12~0 := 2; 1549534#L1569-3 assume 1 == ~E_13~0;~E_13~0 := 2; 1549531#L1574-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 1549101#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 1549088#L1064-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 1549087#L1065-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 1549083#L1959 assume !(0 == start_simulation_~tmp~3#1); 1549080#L1959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 1549076#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 1549059#L1064-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 1549056#L1065-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 1549053#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1549052#L1921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1549051#L1922 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 1549046#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 1461784#L1940-2 [2021-12-16 10:06:07,018 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:07,018 INFO L85 PathProgramCache]: Analyzing trace with hash -1665183797, now seen corresponding path program 1 times [2021-12-16 10:06:07,019 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:07,019 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [346293885] [2021-12-16 10:06:07,019 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:07,019 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:07,030 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:06:07,054 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:06:07,054 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:06:07,054 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [346293885] [2021-12-16 10:06:07,055 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [346293885] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:06:07,055 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:06:07,055 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:06:07,055 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1325391537] [2021-12-16 10:06:07,055 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:06:07,056 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:06:07,056 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:07,056 INFO L85 PathProgramCache]: Analyzing trace with hash 533808291, now seen corresponding path program 1 times [2021-12-16 10:06:07,056 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:07,056 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2126508170] [2021-12-16 10:06:07,057 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:07,057 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:07,067 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:06:07,090 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:06:07,090 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:06:07,090 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2126508170] [2021-12-16 10:06:07,091 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2126508170] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:06:07,091 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:06:07,091 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:06:07,091 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [631439829] [2021-12-16 10:06:07,091 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:06:07,092 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:06:07,092 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:06:07,092 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-16 10:06:07,092 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-16 10:06:07,092 INFO L87 Difference]: Start difference. First operand 195695 states and 276930 transitions. cyclomatic complexity: 81237 Second operand has 4 states, 4 states have (on average 40.25) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:09,247 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:06:09,247 INFO L93 Difference]: Finished difference Result 465726 states and 656175 transitions. [2021-12-16 10:06:09,247 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-16 10:06:09,248 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 465726 states and 656175 transitions. [2021-12-16 10:06:12,305 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 464976 [2021-12-16 10:06:13,958 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 465726 states to 465726 states and 656175 transitions. [2021-12-16 10:06:13,959 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 465726 [2021-12-16 10:06:14,148 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 465726 [2021-12-16 10:06:14,148 INFO L73 IsDeterministic]: Start isDeterministic. Operand 465726 states and 656175 transitions. [2021-12-16 10:06:14,366 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:06:14,366 INFO L681 BuchiCegarLoop]: Abstraction has 465726 states and 656175 transitions. [2021-12-16 10:06:14,613 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 465726 states and 656175 transitions. [2021-12-16 10:06:18,080 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 465726 to 376174. [2021-12-16 10:06:18,396 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 376174 states, 376174 states have (on average 1.411259151350173) internal successors, (530879), 376173 states have internal predecessors, (530879), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)