./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/transmitter.02.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version c3fed411 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/transmitter.02.cil.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 2cbfaf31aa56f767af01fea9a12ccb47d60ab19076d72b85e8ca46d6ff778e4c --- Real Ultimate output --- This is Ultimate 0.2.2-tmp.no-commuhash-c3fed41 [2021-12-16 10:05:34,848 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-12-16 10:05:34,851 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-12-16 10:05:34,886 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-12-16 10:05:34,903 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-12-16 10:05:34,916 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-12-16 10:05:34,919 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-12-16 10:05:34,924 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-12-16 10:05:34,926 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-12-16 10:05:34,931 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-12-16 10:05:34,931 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-12-16 10:05:34,932 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-12-16 10:05:34,933 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-12-16 10:05:34,935 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-12-16 10:05:34,936 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-12-16 10:05:34,954 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-12-16 10:05:34,955 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-12-16 10:05:34,955 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-12-16 10:05:34,959 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-12-16 10:05:34,961 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-12-16 10:05:34,964 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-12-16 10:05:34,965 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-12-16 10:05:34,966 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-12-16 10:05:34,967 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-12-16 10:05:34,970 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-12-16 10:05:34,970 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-12-16 10:05:34,971 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-12-16 10:05:34,972 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-12-16 10:05:34,973 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-12-16 10:05:34,973 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-12-16 10:05:34,974 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-12-16 10:05:34,975 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-12-16 10:05:34,976 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-12-16 10:05:34,977 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-12-16 10:05:34,978 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-12-16 10:05:34,978 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-12-16 10:05:34,978 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-12-16 10:05:34,979 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-12-16 10:05:34,979 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-12-16 10:05:34,979 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-12-16 10:05:34,980 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-12-16 10:05:34,980 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2021-12-16 10:05:35,011 INFO L113 SettingsManager]: Loading preferences was successful [2021-12-16 10:05:35,014 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-12-16 10:05:35,015 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2021-12-16 10:05:35,015 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2021-12-16 10:05:35,016 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-12-16 10:05:35,017 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-12-16 10:05:35,017 INFO L138 SettingsManager]: * Use SBE=true [2021-12-16 10:05:35,017 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2021-12-16 10:05:35,017 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2021-12-16 10:05:35,017 INFO L138 SettingsManager]: * Use old map elimination=false [2021-12-16 10:05:35,018 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2021-12-16 10:05:35,018 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2021-12-16 10:05:35,018 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2021-12-16 10:05:35,018 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-12-16 10:05:35,019 INFO L138 SettingsManager]: * sizeof long=4 [2021-12-16 10:05:35,019 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2021-12-16 10:05:35,019 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-12-16 10:05:35,019 INFO L138 SettingsManager]: * sizeof POINTER=4 [2021-12-16 10:05:35,019 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-12-16 10:05:35,019 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2021-12-16 10:05:35,019 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2021-12-16 10:05:35,020 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2021-12-16 10:05:35,020 INFO L138 SettingsManager]: * sizeof long double=12 [2021-12-16 10:05:35,020 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-12-16 10:05:35,020 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2021-12-16 10:05:35,020 INFO L138 SettingsManager]: * Use constant arrays=true [2021-12-16 10:05:35,020 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2021-12-16 10:05:35,020 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-12-16 10:05:35,021 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-12-16 10:05:35,021 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-12-16 10:05:35,021 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-12-16 10:05:35,021 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2021-12-16 10:05:35,022 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2021-12-16 10:05:35,022 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 2cbfaf31aa56f767af01fea9a12ccb47d60ab19076d72b85e8ca46d6ff778e4c [2021-12-16 10:05:35,276 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-12-16 10:05:35,306 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-12-16 10:05:35,308 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-12-16 10:05:35,309 INFO L271 PluginConnector]: Initializing CDTParser... [2021-12-16 10:05:35,309 INFO L275 PluginConnector]: CDTParser initialized [2021-12-16 10:05:35,310 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/transmitter.02.cil.c [2021-12-16 10:05:35,359 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/d9470bc0d/f797ef9a3b7c48eb889c31fa603f5ca5/FLAGddc3ea8c3 [2021-12-16 10:05:35,777 INFO L306 CDTParser]: Found 1 translation units. [2021-12-16 10:05:35,787 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.02.cil.c [2021-12-16 10:05:35,798 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/d9470bc0d/f797ef9a3b7c48eb889c31fa603f5ca5/FLAGddc3ea8c3 [2021-12-16 10:05:35,833 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/d9470bc0d/f797ef9a3b7c48eb889c31fa603f5ca5 [2021-12-16 10:05:35,840 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-12-16 10:05:35,841 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-12-16 10:05:35,856 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-12-16 10:05:35,856 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-12-16 10:05:35,859 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-12-16 10:05:35,860 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 16.12 10:05:35" (1/1) ... [2021-12-16 10:05:35,860 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@488643c7 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:05:35, skipping insertion in model container [2021-12-16 10:05:35,861 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 16.12 10:05:35" (1/1) ... [2021-12-16 10:05:35,866 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-12-16 10:05:35,885 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-12-16 10:05:35,981 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.02.cil.c[706,719] [2021-12-16 10:05:36,031 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-16 10:05:36,038 INFO L203 MainTranslator]: Completed pre-run [2021-12-16 10:05:36,048 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.02.cil.c[706,719] [2021-12-16 10:05:36,088 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-16 10:05:36,103 INFO L208 MainTranslator]: Completed translation [2021-12-16 10:05:36,103 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:05:36 WrapperNode [2021-12-16 10:05:36,103 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-12-16 10:05:36,105 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-12-16 10:05:36,105 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-12-16 10:05:36,105 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-12-16 10:05:36,110 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:05:36" (1/1) ... [2021-12-16 10:05:36,128 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:05:36" (1/1) ... [2021-12-16 10:05:36,164 INFO L137 Inliner]: procedures = 32, calls = 36, calls flagged for inlining = 31, calls inlined = 44, statements flattened = 530 [2021-12-16 10:05:36,168 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-12-16 10:05:36,169 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-12-16 10:05:36,169 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-12-16 10:05:36,169 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-12-16 10:05:36,174 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:05:36" (1/1) ... [2021-12-16 10:05:36,175 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:05:36" (1/1) ... [2021-12-16 10:05:36,182 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:05:36" (1/1) ... [2021-12-16 10:05:36,182 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:05:36" (1/1) ... [2021-12-16 10:05:36,196 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:05:36" (1/1) ... [2021-12-16 10:05:36,201 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:05:36" (1/1) ... [2021-12-16 10:05:36,203 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:05:36" (1/1) ... [2021-12-16 10:05:36,205 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-12-16 10:05:36,206 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-12-16 10:05:36,206 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-12-16 10:05:36,207 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-12-16 10:05:36,219 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:05:36" (1/1) ... [2021-12-16 10:05:36,225 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-16 10:05:36,234 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-16 10:05:36,251 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-16 10:05:36,267 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2021-12-16 10:05:36,280 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2021-12-16 10:05:36,280 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2021-12-16 10:05:36,281 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-12-16 10:05:36,281 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-12-16 10:05:36,333 INFO L236 CfgBuilder]: Building ICFG [2021-12-16 10:05:36,335 INFO L262 CfgBuilder]: Building CFG for each procedure with an implementation [2021-12-16 10:05:36,657 INFO L277 CfgBuilder]: Performing block encoding [2021-12-16 10:05:36,663 INFO L296 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-12-16 10:05:36,664 INFO L301 CfgBuilder]: Removed 6 assume(true) statements. [2021-12-16 10:05:36,665 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 16.12 10:05:36 BoogieIcfgContainer [2021-12-16 10:05:36,665 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-12-16 10:05:36,666 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2021-12-16 10:05:36,666 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2021-12-16 10:05:36,669 INFO L275 PluginConnector]: BuchiAutomizer initialized [2021-12-16 10:05:36,669 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-16 10:05:36,669 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 16.12 10:05:35" (1/3) ... [2021-12-16 10:05:36,670 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@291311d4 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 16.12 10:05:36, skipping insertion in model container [2021-12-16 10:05:36,670 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-16 10:05:36,670 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:05:36" (2/3) ... [2021-12-16 10:05:36,670 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@291311d4 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 16.12 10:05:36, skipping insertion in model container [2021-12-16 10:05:36,671 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-16 10:05:36,671 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 16.12 10:05:36" (3/3) ... [2021-12-16 10:05:36,672 INFO L388 chiAutomizerObserver]: Analyzing ICFG transmitter.02.cil.c [2021-12-16 10:05:36,699 INFO L359 BuchiCegarLoop]: Interprodecural is true [2021-12-16 10:05:36,705 INFO L360 BuchiCegarLoop]: Hoare is false [2021-12-16 10:05:36,706 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2021-12-16 10:05:36,706 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2021-12-16 10:05:36,706 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2021-12-16 10:05:36,706 INFO L364 BuchiCegarLoop]: Difference is false [2021-12-16 10:05:36,706 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2021-12-16 10:05:36,706 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2021-12-16 10:05:36,719 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 205 states, 204 states have (on average 1.5392156862745099) internal successors, (314), 204 states have internal predecessors, (314), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:36,751 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 160 [2021-12-16 10:05:36,751 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:05:36,751 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:05:36,758 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:36,759 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:36,763 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2021-12-16 10:05:36,764 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 205 states, 204 states have (on average 1.5392156862745099) internal successors, (314), 204 states have internal predecessors, (314), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:36,797 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 160 [2021-12-16 10:05:36,801 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:05:36,801 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:05:36,803 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:36,823 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:36,828 INFO L791 eck$LassoCheckResult]: Stem: 197#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 144#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 4#L491true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 200#L214true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 176#L221true assume !(1 == ~m_i~0);~m_st~0 := 2; 55#L221-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 38#L226-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 149#L231-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 31#L334true assume !(0 == ~M_E~0); 156#L334-2true assume !(0 == ~T1_E~0); 99#L339-1true assume !(0 == ~T2_E~0); 94#L344-1true assume 0 == ~E_1~0;~E_1~0 := 1; 131#L349-1true assume !(0 == ~E_2~0); 37#L354-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 105#L156true assume !(1 == ~m_pc~0); 142#L156-2true is_master_triggered_~__retres1~0#1 := 0; 125#L167true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 115#L168true activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 71#L405true assume !(0 != activate_threads_~tmp~1#1); 58#L405-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 113#L175true assume 1 == ~t1_pc~0; 148#L176true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 59#L186true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 101#L187true activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 102#L413true assume !(0 != activate_threads_~tmp___0~0#1); 179#L413-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 182#L194true assume !(1 == ~t2_pc~0); 201#L194-2true is_transmit2_triggered_~__retres1~2#1 := 0; 65#L205true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 32#L206true activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 25#L421true assume !(0 != activate_threads_~tmp___1~0#1); 76#L421-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12#L367true assume !(1 == ~M_E~0); 181#L367-2true assume !(1 == ~T1_E~0); 119#L372-1true assume 1 == ~T2_E~0;~T2_E~0 := 2; 122#L377-1true assume !(1 == ~E_1~0); 22#L382-1true assume !(1 == ~E_2~0); 73#L387-1true assume { :end_inline_reset_delta_events } true; 93#L528-2true [2021-12-16 10:05:36,836 INFO L793 eck$LassoCheckResult]: Loop: 93#L528-2true assume !false; 77#L529true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 175#L309true assume false; 13#L324true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 72#L214-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 204#L334-3true assume 0 == ~M_E~0;~M_E~0 := 1; 145#L334-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 103#L339-3true assume !(0 == ~T2_E~0); 177#L344-3true assume 0 == ~E_1~0;~E_1~0 := 1; 69#L349-3true assume 0 == ~E_2~0;~E_2~0 := 1; 30#L354-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 88#L156-9true assume !(1 == ~m_pc~0); 6#L156-11true is_master_triggered_~__retres1~0#1 := 0; 53#L167-3true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 167#L168-3true activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 106#L405-9true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 19#L405-11true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 189#L175-9true assume !(1 == ~t1_pc~0); 129#L175-11true is_transmit1_triggered_~__retres1~1#1 := 0; 14#L186-3true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 100#L187-3true activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 141#L413-9true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 135#L413-11true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 186#L194-9true assume !(1 == ~t2_pc~0); 26#L194-11true is_transmit2_triggered_~__retres1~2#1 := 0; 193#L205-3true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 75#L206-3true activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 97#L421-9true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 132#L421-11true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 51#L367-3true assume 1 == ~M_E~0;~M_E~0 := 2; 8#L367-5true assume !(1 == ~T1_E~0); 33#L372-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 17#L377-3true assume 1 == ~E_1~0;~E_1~0 := 2; 28#L382-3true assume 1 == ~E_2~0;~E_2~0 := 2; 98#L387-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 133#L244-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 169#L261-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 23#L262-1true start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 140#L547true assume !(0 == start_simulation_~tmp~3#1); 152#L547-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 137#L244-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 49#L261-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 166#L262-2true stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1; 36#L502true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 46#L509true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 174#L510true start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 18#L560true assume !(0 != start_simulation_~tmp___0~1#1); 93#L528-2true [2021-12-16 10:05:36,841 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:36,841 INFO L85 PathProgramCache]: Analyzing trace with hash -886407522, now seen corresponding path program 1 times [2021-12-16 10:05:36,847 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:36,848 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [403328364] [2021-12-16 10:05:36,848 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:36,849 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:36,910 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:36,962 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:05:36,962 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:36,963 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [403328364] [2021-12-16 10:05:36,965 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [403328364] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:36,965 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:36,965 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:05:36,967 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [321989186] [2021-12-16 10:05:36,967 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:36,970 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:05:36,972 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:36,972 INFO L85 PathProgramCache]: Analyzing trace with hash 707442261, now seen corresponding path program 1 times [2021-12-16 10:05:36,972 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:36,973 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [536291609] [2021-12-16 10:05:36,973 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:36,973 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:36,981 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:36,990 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:05:36,990 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:36,991 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [536291609] [2021-12-16 10:05:36,991 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [536291609] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:36,991 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:36,991 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-16 10:05:36,992 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [224130063] [2021-12-16 10:05:36,992 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:36,993 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:05:36,995 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:05:37,022 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-16 10:05:37,023 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-16 10:05:37,025 INFO L87 Difference]: Start difference. First operand has 205 states, 204 states have (on average 1.5392156862745099) internal successors, (314), 204 states have internal predecessors, (314), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 12.666666666666666) internal successors, (38), 3 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:37,058 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:05:37,058 INFO L93 Difference]: Finished difference Result 204 states and 299 transitions. [2021-12-16 10:05:37,062 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-16 10:05:37,066 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 204 states and 299 transitions. [2021-12-16 10:05:37,071 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 157 [2021-12-16 10:05:37,077 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 204 states to 198 states and 293 transitions. [2021-12-16 10:05:37,079 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 198 [2021-12-16 10:05:37,080 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 198 [2021-12-16 10:05:37,080 INFO L73 IsDeterministic]: Start isDeterministic. Operand 198 states and 293 transitions. [2021-12-16 10:05:37,082 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:05:37,083 INFO L681 BuchiCegarLoop]: Abstraction has 198 states and 293 transitions. [2021-12-16 10:05:37,095 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 198 states and 293 transitions. [2021-12-16 10:05:37,118 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 198 to 198. [2021-12-16 10:05:37,120 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 198 states, 198 states have (on average 1.47979797979798) internal successors, (293), 197 states have internal predecessors, (293), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:37,125 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 198 states to 198 states and 293 transitions. [2021-12-16 10:05:37,126 INFO L704 BuchiCegarLoop]: Abstraction has 198 states and 293 transitions. [2021-12-16 10:05:37,126 INFO L587 BuchiCegarLoop]: Abstraction has 198 states and 293 transitions. [2021-12-16 10:05:37,126 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2021-12-16 10:05:37,126 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 198 states and 293 transitions. [2021-12-16 10:05:37,132 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 157 [2021-12-16 10:05:37,132 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:05:37,132 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:05:37,134 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:37,136 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:37,136 INFO L791 eck$LassoCheckResult]: Stem: 615#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 601#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 421#L491 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 422#L214 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 609#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 514#L221-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 488#L226-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 489#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 476#L334 assume !(0 == ~M_E~0); 477#L334-2 assume !(0 == ~T1_E~0); 565#L339-1 assume !(0 == ~T2_E~0); 559#L344-1 assume 0 == ~E_1~0;~E_1~0 := 1; 560#L349-1 assume !(0 == ~E_2~0); 486#L354-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 487#L156 assume !(1 == ~m_pc~0); 429#L156-2 is_master_triggered_~__retres1~0#1 := 0; 428#L167 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 581#L168 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 534#L405 assume !(0 != activate_threads_~tmp~1#1); 518#L405-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 519#L175 assume 1 == ~t1_pc~0; 578#L176 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 520#L186 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 521#L187 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 567#L413 assume !(0 != activate_threads_~tmp___0~0#1); 568#L413-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 611#L194 assume !(1 == ~t2_pc~0); 558#L194-2 is_transmit2_triggered_~__retres1~2#1 := 0; 530#L205 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 478#L206 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 465#L421 assume !(0 != activate_threads_~tmp___1~0#1); 466#L421-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 440#L367 assume !(1 == ~M_E~0); 441#L367-2 assume !(1 == ~T1_E~0); 585#L372-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 586#L377-1 assume !(1 == ~E_1~0); 460#L382-1 assume !(1 == ~E_2~0); 461#L387-1 assume { :end_inline_reset_delta_events } true; 452#L528-2 [2021-12-16 10:05:37,137 INFO L793 eck$LassoCheckResult]: Loop: 452#L528-2 assume !false; 539#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 513#L309 assume !false; 492#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 432#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 433#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 577#L262 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 418#L276 assume !(0 != eval_~tmp~0#1); 420#L324 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 442#L214-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 535#L334-3 assume 0 == ~M_E~0;~M_E~0 := 1; 602#L334-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 569#L339-3 assume !(0 == ~T2_E~0); 570#L344-3 assume 0 == ~E_1~0;~E_1~0 := 1; 533#L349-3 assume 0 == ~E_2~0;~E_2~0 := 1; 474#L354-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 475#L156-9 assume !(1 == ~m_pc~0); 425#L156-11 is_master_triggered_~__retres1~0#1 := 0; 426#L167-3 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 511#L168-3 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 572#L405-9 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 453#L405-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 454#L175-9 assume 1 == ~t1_pc~0; 496#L176-3 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 443#L186-3 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 444#L187-3 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 566#L413-9 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 596#L413-11 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 597#L194-9 assume !(1 == ~t2_pc~0); 467#L194-11 is_transmit2_triggered_~__retres1~2#1 := 0; 468#L205-3 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 537#L206-3 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 538#L421-9 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 563#L421-11 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 508#L367-3 assume 1 == ~M_E~0;~M_E~0 := 2; 430#L367-5 assume !(1 == ~T1_E~0); 431#L372-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 449#L377-3 assume 1 == ~E_1~0;~E_1~0 := 2; 450#L382-3 assume 1 == ~E_2~0;~E_2~0 := 2; 471#L387-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 564#L244-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 480#L261-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 462#L262-1 start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 463#L547 assume !(0 == start_simulation_~tmp~3#1); 587#L547-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 598#L244-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 505#L261-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 506#L262-2 stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1; 484#L502 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 485#L509 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 501#L510 start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 451#L560 assume !(0 != start_simulation_~tmp___0~1#1); 452#L528-2 [2021-12-16 10:05:37,138 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:37,138 INFO L85 PathProgramCache]: Analyzing trace with hash 1357575776, now seen corresponding path program 1 times [2021-12-16 10:05:37,138 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:37,139 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [442861005] [2021-12-16 10:05:37,139 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:37,139 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:37,148 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:37,174 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:05:37,174 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:37,175 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [442861005] [2021-12-16 10:05:37,175 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [442861005] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:37,176 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:37,176 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:05:37,176 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1275637595] [2021-12-16 10:05:37,176 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:37,176 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:05:37,177 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:37,178 INFO L85 PathProgramCache]: Analyzing trace with hash -1486806721, now seen corresponding path program 1 times [2021-12-16 10:05:37,178 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:37,179 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2018687917] [2021-12-16 10:05:37,179 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:37,179 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:37,193 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:37,219 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:05:37,219 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:37,219 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2018687917] [2021-12-16 10:05:37,219 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2018687917] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:37,220 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:37,220 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:05:37,220 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [324829714] [2021-12-16 10:05:37,220 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:37,220 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:05:37,220 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:05:37,221 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-16 10:05:37,221 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-16 10:05:37,221 INFO L87 Difference]: Start difference. First operand 198 states and 293 transitions. cyclomatic complexity: 96 Second operand has 3 states, 3 states have (on average 12.666666666666666) internal successors, (38), 3 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:37,232 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:05:37,232 INFO L93 Difference]: Finished difference Result 198 states and 292 transitions. [2021-12-16 10:05:37,232 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-16 10:05:37,233 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 198 states and 292 transitions. [2021-12-16 10:05:37,234 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 157 [2021-12-16 10:05:37,235 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 198 states to 198 states and 292 transitions. [2021-12-16 10:05:37,236 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 198 [2021-12-16 10:05:37,236 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 198 [2021-12-16 10:05:37,236 INFO L73 IsDeterministic]: Start isDeterministic. Operand 198 states and 292 transitions. [2021-12-16 10:05:37,237 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:05:37,237 INFO L681 BuchiCegarLoop]: Abstraction has 198 states and 292 transitions. [2021-12-16 10:05:37,237 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 198 states and 292 transitions. [2021-12-16 10:05:37,240 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 198 to 198. [2021-12-16 10:05:37,241 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 198 states, 198 states have (on average 1.4747474747474747) internal successors, (292), 197 states have internal predecessors, (292), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:37,241 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 198 states to 198 states and 292 transitions. [2021-12-16 10:05:37,242 INFO L704 BuchiCegarLoop]: Abstraction has 198 states and 292 transitions. [2021-12-16 10:05:37,242 INFO L587 BuchiCegarLoop]: Abstraction has 198 states and 292 transitions. [2021-12-16 10:05:37,242 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2021-12-16 10:05:37,242 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 198 states and 292 transitions. [2021-12-16 10:05:37,243 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 157 [2021-12-16 10:05:37,243 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:05:37,243 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:05:37,244 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:37,244 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:37,244 INFO L791 eck$LassoCheckResult]: Stem: 1018#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 1004#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 824#L491 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 825#L214 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1012#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 917#L221-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 891#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 892#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 879#L334 assume !(0 == ~M_E~0); 880#L334-2 assume !(0 == ~T1_E~0); 968#L339-1 assume !(0 == ~T2_E~0); 962#L344-1 assume 0 == ~E_1~0;~E_1~0 := 1; 963#L349-1 assume !(0 == ~E_2~0); 889#L354-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 890#L156 assume !(1 == ~m_pc~0); 832#L156-2 is_master_triggered_~__retres1~0#1 := 0; 831#L167 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 984#L168 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 937#L405 assume !(0 != activate_threads_~tmp~1#1); 921#L405-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 922#L175 assume 1 == ~t1_pc~0; 981#L176 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 923#L186 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 924#L187 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 970#L413 assume !(0 != activate_threads_~tmp___0~0#1); 971#L413-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1014#L194 assume !(1 == ~t2_pc~0); 961#L194-2 is_transmit2_triggered_~__retres1~2#1 := 0; 933#L205 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 881#L206 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 868#L421 assume !(0 != activate_threads_~tmp___1~0#1); 869#L421-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 843#L367 assume !(1 == ~M_E~0); 844#L367-2 assume !(1 == ~T1_E~0); 988#L372-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 989#L377-1 assume !(1 == ~E_1~0); 863#L382-1 assume !(1 == ~E_2~0); 864#L387-1 assume { :end_inline_reset_delta_events } true; 855#L528-2 [2021-12-16 10:05:37,244 INFO L793 eck$LassoCheckResult]: Loop: 855#L528-2 assume !false; 942#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 916#L309 assume !false; 895#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 835#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 836#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 980#L262 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 821#L276 assume !(0 != eval_~tmp~0#1); 823#L324 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 845#L214-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 938#L334-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1005#L334-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 972#L339-3 assume !(0 == ~T2_E~0); 973#L344-3 assume 0 == ~E_1~0;~E_1~0 := 1; 936#L349-3 assume 0 == ~E_2~0;~E_2~0 := 1; 877#L354-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 878#L156-9 assume !(1 == ~m_pc~0); 828#L156-11 is_master_triggered_~__retres1~0#1 := 0; 829#L167-3 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 914#L168-3 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 975#L405-9 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 856#L405-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 857#L175-9 assume 1 == ~t1_pc~0; 899#L176-3 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 846#L186-3 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 847#L187-3 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 969#L413-9 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 999#L413-11 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1000#L194-9 assume !(1 == ~t2_pc~0); 870#L194-11 is_transmit2_triggered_~__retres1~2#1 := 0; 871#L205-3 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 940#L206-3 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 941#L421-9 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 966#L421-11 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 911#L367-3 assume 1 == ~M_E~0;~M_E~0 := 2; 833#L367-5 assume !(1 == ~T1_E~0); 834#L372-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 852#L377-3 assume 1 == ~E_1~0;~E_1~0 := 2; 853#L382-3 assume 1 == ~E_2~0;~E_2~0 := 2; 874#L387-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 967#L244-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 883#L261-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 865#L262-1 start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 866#L547 assume !(0 == start_simulation_~tmp~3#1); 990#L547-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 1001#L244-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 908#L261-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 909#L262-2 stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1; 887#L502 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 888#L509 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 904#L510 start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 854#L560 assume !(0 != start_simulation_~tmp___0~1#1); 855#L528-2 [2021-12-16 10:05:37,245 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:37,245 INFO L85 PathProgramCache]: Analyzing trace with hash 1082816162, now seen corresponding path program 1 times [2021-12-16 10:05:37,245 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:37,245 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1291125439] [2021-12-16 10:05:37,245 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:37,246 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:37,256 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:37,271 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:05:37,271 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:37,271 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1291125439] [2021-12-16 10:05:37,272 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1291125439] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:37,272 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:37,272 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-16 10:05:37,272 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1203088569] [2021-12-16 10:05:37,272 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:37,272 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:05:37,273 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:37,273 INFO L85 PathProgramCache]: Analyzing trace with hash -1486806721, now seen corresponding path program 2 times [2021-12-16 10:05:37,273 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:37,273 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [189980993] [2021-12-16 10:05:37,273 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:37,274 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:37,283 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:37,300 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:05:37,300 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:37,300 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [189980993] [2021-12-16 10:05:37,301 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [189980993] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:37,301 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:37,301 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:05:37,301 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1286302945] [2021-12-16 10:05:37,301 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:37,301 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:05:37,302 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:05:37,302 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-16 10:05:37,302 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-16 10:05:37,302 INFO L87 Difference]: Start difference. First operand 198 states and 292 transitions. cyclomatic complexity: 95 Second operand has 3 states, 3 states have (on average 12.666666666666666) internal successors, (38), 2 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:37,326 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:05:37,326 INFO L93 Difference]: Finished difference Result 198 states and 283 transitions. [2021-12-16 10:05:37,326 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-16 10:05:37,327 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 198 states and 283 transitions. [2021-12-16 10:05:37,328 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 157 [2021-12-16 10:05:37,329 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 198 states to 198 states and 283 transitions. [2021-12-16 10:05:37,329 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 198 [2021-12-16 10:05:37,347 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 198 [2021-12-16 10:05:37,347 INFO L73 IsDeterministic]: Start isDeterministic. Operand 198 states and 283 transitions. [2021-12-16 10:05:37,348 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:05:37,348 INFO L681 BuchiCegarLoop]: Abstraction has 198 states and 283 transitions. [2021-12-16 10:05:37,348 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 198 states and 283 transitions. [2021-12-16 10:05:37,351 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 198 to 198. [2021-12-16 10:05:37,352 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 198 states, 198 states have (on average 1.4292929292929293) internal successors, (283), 197 states have internal predecessors, (283), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:37,352 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 198 states to 198 states and 283 transitions. [2021-12-16 10:05:37,352 INFO L704 BuchiCegarLoop]: Abstraction has 198 states and 283 transitions. [2021-12-16 10:05:37,353 INFO L587 BuchiCegarLoop]: Abstraction has 198 states and 283 transitions. [2021-12-16 10:05:37,353 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2021-12-16 10:05:37,353 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 198 states and 283 transitions. [2021-12-16 10:05:37,354 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 157 [2021-12-16 10:05:37,354 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:05:37,354 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:05:37,355 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:37,355 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:37,355 INFO L791 eck$LassoCheckResult]: Stem: 1421#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 1407#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 1227#L491 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1228#L214 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1415#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 1320#L221-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1294#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1295#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1282#L334 assume !(0 == ~M_E~0); 1283#L334-2 assume !(0 == ~T1_E~0); 1371#L339-1 assume !(0 == ~T2_E~0); 1365#L344-1 assume !(0 == ~E_1~0); 1366#L349-1 assume !(0 == ~E_2~0); 1292#L354-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1293#L156 assume !(1 == ~m_pc~0); 1235#L156-2 is_master_triggered_~__retres1~0#1 := 0; 1234#L167 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1387#L168 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 1340#L405 assume !(0 != activate_threads_~tmp~1#1); 1324#L405-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1325#L175 assume !(1 == ~t1_pc~0); 1332#L175-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1326#L186 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1327#L187 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 1373#L413 assume !(0 != activate_threads_~tmp___0~0#1); 1374#L413-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1417#L194 assume !(1 == ~t2_pc~0); 1364#L194-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1336#L205 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1284#L206 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1271#L421 assume !(0 != activate_threads_~tmp___1~0#1); 1272#L421-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1246#L367 assume !(1 == ~M_E~0); 1247#L367-2 assume !(1 == ~T1_E~0); 1391#L372-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1392#L377-1 assume !(1 == ~E_1~0); 1266#L382-1 assume !(1 == ~E_2~0); 1267#L387-1 assume { :end_inline_reset_delta_events } true; 1258#L528-2 [2021-12-16 10:05:37,355 INFO L793 eck$LassoCheckResult]: Loop: 1258#L528-2 assume !false; 1345#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1319#L309 assume !false; 1298#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 1238#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 1239#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 1383#L262 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1224#L276 assume !(0 != eval_~tmp~0#1); 1226#L324 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1248#L214-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1341#L334-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1408#L334-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1375#L339-3 assume !(0 == ~T2_E~0); 1376#L344-3 assume !(0 == ~E_1~0); 1339#L349-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1280#L354-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1281#L156-9 assume 1 == ~m_pc~0; 1360#L157-3 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1232#L167-3 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1317#L168-3 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 1378#L405-9 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1259#L405-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1260#L175-9 assume !(1 == ~t1_pc~0); 1303#L175-11 is_transmit1_triggered_~__retres1~1#1 := 0; 1249#L186-3 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1250#L187-3 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 1372#L413-9 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1402#L413-11 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1403#L194-9 assume !(1 == ~t2_pc~0); 1273#L194-11 is_transmit2_triggered_~__retres1~2#1 := 0; 1274#L205-3 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1343#L206-3 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1344#L421-9 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1369#L421-11 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1314#L367-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1236#L367-5 assume !(1 == ~T1_E~0); 1237#L372-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1255#L377-3 assume !(1 == ~E_1~0); 1256#L382-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1277#L387-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 1370#L244-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 1286#L261-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 1268#L262-1 start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 1269#L547 assume !(0 == start_simulation_~tmp~3#1); 1393#L547-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 1404#L244-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 1311#L261-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 1312#L262-2 stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1; 1290#L502 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1291#L509 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1307#L510 start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 1257#L560 assume !(0 != start_simulation_~tmp___0~1#1); 1258#L528-2 [2021-12-16 10:05:37,356 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:37,356 INFO L85 PathProgramCache]: Analyzing trace with hash -148571389, now seen corresponding path program 1 times [2021-12-16 10:05:37,356 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:37,356 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1802320506] [2021-12-16 10:05:37,356 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:37,357 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:37,364 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:37,394 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:05:37,395 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:37,395 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1802320506] [2021-12-16 10:05:37,395 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1802320506] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:37,395 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:37,395 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:05:37,395 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1122855792] [2021-12-16 10:05:37,396 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:37,396 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:05:37,396 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:37,396 INFO L85 PathProgramCache]: Analyzing trace with hash 1390602115, now seen corresponding path program 1 times [2021-12-16 10:05:37,397 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:37,397 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [781126841] [2021-12-16 10:05:37,397 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:37,397 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:37,405 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:37,421 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:05:37,421 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:37,422 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [781126841] [2021-12-16 10:05:37,422 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [781126841] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:37,422 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:37,422 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:05:37,422 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [743471541] [2021-12-16 10:05:37,422 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:37,423 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:05:37,423 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:05:37,423 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-16 10:05:37,423 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-16 10:05:37,424 INFO L87 Difference]: Start difference. First operand 198 states and 283 transitions. cyclomatic complexity: 86 Second operand has 4 states, 4 states have (on average 9.5) internal successors, (38), 3 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:37,493 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:05:37,493 INFO L93 Difference]: Finished difference Result 413 states and 582 transitions. [2021-12-16 10:05:37,494 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-16 10:05:37,494 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 413 states and 582 transitions. [2021-12-16 10:05:37,497 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 313 [2021-12-16 10:05:37,498 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 413 states to 413 states and 582 transitions. [2021-12-16 10:05:37,499 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 413 [2021-12-16 10:05:37,499 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 413 [2021-12-16 10:05:37,499 INFO L73 IsDeterministic]: Start isDeterministic. Operand 413 states and 582 transitions. [2021-12-16 10:05:37,500 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:05:37,500 INFO L681 BuchiCegarLoop]: Abstraction has 413 states and 582 transitions. [2021-12-16 10:05:37,500 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 413 states and 582 transitions. [2021-12-16 10:05:37,508 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 413 to 413. [2021-12-16 10:05:37,508 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 413 states, 413 states have (on average 1.4092009685230025) internal successors, (582), 412 states have internal predecessors, (582), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:37,509 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 413 states to 413 states and 582 transitions. [2021-12-16 10:05:37,509 INFO L704 BuchiCegarLoop]: Abstraction has 413 states and 582 transitions. [2021-12-16 10:05:37,510 INFO L587 BuchiCegarLoop]: Abstraction has 413 states and 582 transitions. [2021-12-16 10:05:37,510 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2021-12-16 10:05:37,510 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 413 states and 582 transitions. [2021-12-16 10:05:37,511 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 313 [2021-12-16 10:05:37,512 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:05:37,512 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:05:37,512 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:37,512 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:37,513 INFO L791 eck$LassoCheckResult]: Stem: 2093#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 2055#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 1848#L491 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1849#L214 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2079#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 1944#L221-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1916#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1917#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1903#L334 assume 0 == ~M_E~0;~M_E~0 := 1; 1904#L334-2 assume !(0 == ~T1_E~0); 2004#L339-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2005#L344-1 assume !(0 == ~E_1~0); 2120#L349-1 assume !(0 == ~E_2~0); 2119#L354-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2118#L156 assume !(1 == ~m_pc~0); 2117#L156-2 is_master_triggered_~__retres1~0#1 := 0; 2115#L167 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2114#L168 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 2113#L405 assume !(0 != activate_threads_~tmp~1#1); 2112#L405-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2111#L175 assume !(1 == ~t1_pc~0); 2109#L175-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2108#L186 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2107#L187 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 2106#L413 assume !(0 != activate_threads_~tmp___0~0#1); 2105#L413-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2104#L194 assume !(1 == ~t2_pc~0); 2102#L194-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2101#L205 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2100#L206 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 2099#L421 assume !(0 != activate_threads_~tmp___1~0#1); 2098#L421-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2097#L367 assume !(1 == ~M_E~0); 2096#L367-2 assume !(1 == ~T1_E~0); 2095#L372-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2035#L377-1 assume !(1 == ~E_1~0); 1887#L382-1 assume !(1 == ~E_2~0); 1888#L387-1 assume { :end_inline_reset_delta_events } true; 2152#L528-2 [2021-12-16 10:05:37,513 INFO L793 eck$LassoCheckResult]: Loop: 2152#L528-2 assume !false; 1976#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1943#L309 assume !false; 1920#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 1859#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 1860#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 2066#L262 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 2067#L276 assume !(0 != eval_~tmp~0#1); 1869#L324 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1870#L214-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1971#L334-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2056#L334-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2010#L339-3 assume !(0 == ~T2_E~0); 2011#L344-3 assume !(0 == ~E_1~0); 2257#L349-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2256#L354-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2255#L156-9 assume 1 == ~m_pc~0; 2253#L157-3 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 2252#L167-3 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2251#L168-3 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 2250#L405-9 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2249#L405-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2247#L175-9 assume !(1 == ~t1_pc~0); 2246#L175-11 is_transmit1_triggered_~__retres1~1#1 := 0; 1871#L186-3 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1872#L187-3 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 2007#L413-9 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2053#L413-11 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2196#L194-9 assume 1 == ~t2_pc~0; 2192#L195-3 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2190#L205-3 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2188#L206-3 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 2186#L421-9 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2184#L421-11 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2182#L367-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2180#L367-5 assume !(1 == ~T1_E~0); 2179#L372-3 assume !(1 == ~T2_E~0); 2177#L377-3 assume !(1 == ~E_1~0); 2176#L382-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2175#L387-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 2173#L244-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 2171#L261-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 2170#L262-1 start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 2169#L547 assume !(0 == start_simulation_~tmp~3#1); 2033#L547-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 2166#L244-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 1933#L261-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 1934#L262-2 stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1; 1912#L502 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1913#L509 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1929#L510 start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 2154#L560 assume !(0 != start_simulation_~tmp___0~1#1); 2152#L528-2 [2021-12-16 10:05:37,513 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:37,514 INFO L85 PathProgramCache]: Analyzing trace with hash 338269447, now seen corresponding path program 1 times [2021-12-16 10:05:37,514 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:37,514 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1204413326] [2021-12-16 10:05:37,514 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:37,514 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:37,519 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:37,537 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:05:37,538 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:37,538 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1204413326] [2021-12-16 10:05:37,538 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1204413326] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:37,538 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:37,538 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-16 10:05:37,539 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [541307403] [2021-12-16 10:05:37,539 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:37,539 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:05:37,539 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:37,539 INFO L85 PathProgramCache]: Analyzing trace with hash 1959928738, now seen corresponding path program 1 times [2021-12-16 10:05:37,540 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:37,540 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [539183305] [2021-12-16 10:05:37,540 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:37,540 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:37,546 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:37,561 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:05:37,561 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:37,561 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [539183305] [2021-12-16 10:05:37,561 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [539183305] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:37,561 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:37,561 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:05:37,562 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [568045983] [2021-12-16 10:05:37,562 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:37,562 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:05:37,562 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:05:37,563 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-16 10:05:37,563 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-16 10:05:37,563 INFO L87 Difference]: Start difference. First operand 413 states and 582 transitions. cyclomatic complexity: 171 Second operand has 3 states, 3 states have (on average 12.666666666666666) internal successors, (38), 2 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:37,595 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:05:37,595 INFO L93 Difference]: Finished difference Result 545 states and 759 transitions. [2021-12-16 10:05:37,595 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-16 10:05:37,597 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 545 states and 759 transitions. [2021-12-16 10:05:37,600 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 474 [2021-12-16 10:05:37,602 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 545 states to 545 states and 759 transitions. [2021-12-16 10:05:37,602 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 545 [2021-12-16 10:05:37,603 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 545 [2021-12-16 10:05:37,603 INFO L73 IsDeterministic]: Start isDeterministic. Operand 545 states and 759 transitions. [2021-12-16 10:05:37,604 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:05:37,604 INFO L681 BuchiCegarLoop]: Abstraction has 545 states and 759 transitions. [2021-12-16 10:05:37,604 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 545 states and 759 transitions. [2021-12-16 10:05:37,610 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 545 to 413. [2021-12-16 10:05:37,610 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 413 states, 413 states have (on average 1.3946731234866827) internal successors, (576), 412 states have internal predecessors, (576), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:37,611 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 413 states to 413 states and 576 transitions. [2021-12-16 10:05:37,612 INFO L704 BuchiCegarLoop]: Abstraction has 413 states and 576 transitions. [2021-12-16 10:05:37,612 INFO L587 BuchiCegarLoop]: Abstraction has 413 states and 576 transitions. [2021-12-16 10:05:37,612 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2021-12-16 10:05:37,612 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 413 states and 576 transitions. [2021-12-16 10:05:37,613 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 345 [2021-12-16 10:05:37,613 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:05:37,613 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:05:37,614 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:37,614 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:37,614 INFO L791 eck$LassoCheckResult]: Stem: 3032#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 3011#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 2813#L491 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2814#L214 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3019#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 2907#L221-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2880#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2881#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2867#L334 assume !(0 == ~M_E~0); 2868#L334-2 assume !(0 == ~T1_E~0); 2963#L339-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2964#L344-1 assume !(0 == ~E_1~0); 3039#L349-1 assume !(0 == ~E_2~0); 2878#L354-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2879#L156 assume !(1 == ~m_pc~0); 3010#L156-2 is_master_triggered_~__retres1~0#1 := 0; 2997#L167 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2998#L168 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 2929#L405 assume !(0 != activate_threads_~tmp~1#1); 2930#L405-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2981#L175 assume !(1 == ~t1_pc~0); 2919#L175-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2920#L186 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2966#L187 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 2967#L413 assume !(0 != activate_threads_~tmp___0~0#1); 3021#L413-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3022#L194 assume !(1 == ~t2_pc~0); 2956#L194-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2924#L205 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2869#L206 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 2870#L421 assume !(0 != activate_threads_~tmp___1~0#1); 2935#L421-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2936#L367 assume !(1 == ~M_E~0); 3024#L367-2 assume !(1 == ~T1_E~0); 3025#L372-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2991#L377-1 assume !(1 == ~E_1~0); 2851#L382-1 assume !(1 == ~E_2~0); 2852#L387-1 assume { :end_inline_reset_delta_events } true; 2843#L528-2 [2021-12-16 10:05:37,615 INFO L793 eck$LassoCheckResult]: Loop: 2843#L528-2 assume !false; 2937#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2906#L309 assume !false; 2884#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 2824#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 2825#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 2980#L262 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 2810#L276 assume !(0 != eval_~tmp~0#1); 2812#L324 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2834#L214-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2931#L334-3 assume !(0 == ~M_E~0); 3012#L334-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2970#L339-3 assume !(0 == ~T2_E~0); 2971#L344-3 assume !(0 == ~E_1~0); 2928#L349-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2865#L354-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2866#L156-9 assume !(1 == ~m_pc~0); 2818#L156-11 is_master_triggered_~__retres1~0#1 := 0; 2819#L167-3 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2904#L168-3 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 2975#L405-9 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2844#L405-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2845#L175-9 assume !(1 == ~t1_pc~0); 2889#L175-11 is_transmit1_triggered_~__retres1~1#1 := 0; 2835#L186-3 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2836#L187-3 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 2965#L413-9 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3005#L413-11 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3006#L194-9 assume 1 == ~t2_pc~0; 2932#L195-3 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2859#L205-3 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2933#L206-3 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 2934#L421-9 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2961#L421-11 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2901#L367-3 assume !(1 == ~M_E~0); 2822#L367-5 assume !(1 == ~T1_E~0); 2823#L372-3 assume !(1 == ~T2_E~0); 2840#L377-3 assume !(1 == ~E_1~0); 2841#L382-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2862#L387-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 2962#L244-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 2872#L261-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 2853#L262-1 start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 2854#L547 assume !(0 == start_simulation_~tmp~3#1); 2993#L547-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 3007#L244-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 2898#L261-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 2899#L262-2 stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1; 2876#L502 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2877#L509 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2894#L510 start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 2842#L560 assume !(0 != start_simulation_~tmp___0~1#1); 2843#L528-2 [2021-12-16 10:05:37,615 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:37,615 INFO L85 PathProgramCache]: Analyzing trace with hash 360901701, now seen corresponding path program 1 times [2021-12-16 10:05:37,616 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:37,616 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [915325913] [2021-12-16 10:05:37,616 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:37,616 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:37,626 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:37,641 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:05:37,642 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:37,642 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [915325913] [2021-12-16 10:05:37,642 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [915325913] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:37,642 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:37,642 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:05:37,642 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1412601628] [2021-12-16 10:05:37,643 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:37,643 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:05:37,643 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:37,643 INFO L85 PathProgramCache]: Analyzing trace with hash -1550886083, now seen corresponding path program 1 times [2021-12-16 10:05:37,643 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:37,643 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [843490834] [2021-12-16 10:05:37,644 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:37,644 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:37,649 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:37,662 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:05:37,662 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:37,663 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [843490834] [2021-12-16 10:05:37,663 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [843490834] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:37,663 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:37,663 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:05:37,663 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [17029708] [2021-12-16 10:05:37,663 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:37,664 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:05:37,664 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:05:37,664 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-16 10:05:37,664 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-16 10:05:37,664 INFO L87 Difference]: Start difference. First operand 413 states and 576 transitions. cyclomatic complexity: 164 Second operand has 4 states, 4 states have (on average 9.5) internal successors, (38), 3 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:37,713 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:05:37,713 INFO L93 Difference]: Finished difference Result 461 states and 638 transitions. [2021-12-16 10:05:37,713 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-16 10:05:37,715 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 461 states and 638 transitions. [2021-12-16 10:05:37,717 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 420 [2021-12-16 10:05:37,719 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 461 states to 461 states and 638 transitions. [2021-12-16 10:05:37,719 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 461 [2021-12-16 10:05:37,719 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 461 [2021-12-16 10:05:37,719 INFO L73 IsDeterministic]: Start isDeterministic. Operand 461 states and 638 transitions. [2021-12-16 10:05:37,720 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:05:37,720 INFO L681 BuchiCegarLoop]: Abstraction has 461 states and 638 transitions. [2021-12-16 10:05:37,720 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 461 states and 638 transitions. [2021-12-16 10:05:37,723 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 461 to 332. [2021-12-16 10:05:37,724 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 332 states, 332 states have (on average 1.3855421686746987) internal successors, (460), 331 states have internal predecessors, (460), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:37,725 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 332 states to 332 states and 460 transitions. [2021-12-16 10:05:37,725 INFO L704 BuchiCegarLoop]: Abstraction has 332 states and 460 transitions. [2021-12-16 10:05:37,725 INFO L587 BuchiCegarLoop]: Abstraction has 332 states and 460 transitions. [2021-12-16 10:05:37,725 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2021-12-16 10:05:37,726 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 332 states and 460 transitions. [2021-12-16 10:05:37,727 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 291 [2021-12-16 10:05:37,727 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:05:37,727 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:05:37,727 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:37,728 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:37,728 INFO L791 eck$LassoCheckResult]: Stem: 3896#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 3880#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 3697#L491 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3698#L214 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3888#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 3790#L221-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3763#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3764#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3751#L334 assume !(0 == ~M_E~0); 3752#L334-2 assume !(0 == ~T1_E~0); 3842#L339-1 assume !(0 == ~T2_E~0); 3836#L344-1 assume !(0 == ~E_1~0); 3837#L349-1 assume !(0 == ~E_2~0); 3761#L354-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3762#L156 assume !(1 == ~m_pc~0); 3705#L156-2 is_master_triggered_~__retres1~0#1 := 0; 3869#L167 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3858#L168 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 3811#L405 assume !(0 != activate_threads_~tmp~1#1); 3794#L405-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3795#L175 assume !(1 == ~t1_pc~0); 3802#L175-2 is_transmit1_triggered_~__retres1~1#1 := 0; 3796#L186 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3797#L187 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 3844#L413 assume !(0 != activate_threads_~tmp___0~0#1); 3845#L413-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3890#L194 assume !(1 == ~t2_pc~0); 3835#L194-2 is_transmit2_triggered_~__retres1~2#1 := 0; 3806#L205 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3753#L206 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 3740#L421 assume !(0 != activate_threads_~tmp___1~0#1); 3741#L421-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3716#L367 assume !(1 == ~M_E~0); 3717#L367-2 assume !(1 == ~T1_E~0); 3862#L372-1 assume !(1 == ~T2_E~0); 3863#L377-1 assume !(1 == ~E_1~0); 3735#L382-1 assume !(1 == ~E_2~0); 3736#L387-1 assume { :end_inline_reset_delta_events } true; 3727#L528-2 [2021-12-16 10:05:37,728 INFO L793 eck$LassoCheckResult]: Loop: 3727#L528-2 assume !false; 3816#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3789#L309 assume !false; 3767#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 3708#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 3709#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 3854#L262 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 3694#L276 assume !(0 != eval_~tmp~0#1); 3696#L324 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3718#L214-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3812#L334-3 assume !(0 == ~M_E~0); 3881#L334-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3846#L339-3 assume !(0 == ~T2_E~0); 3847#L344-3 assume !(0 == ~E_1~0); 3810#L349-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3749#L354-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3750#L156-9 assume !(1 == ~m_pc~0); 3702#L156-11 is_master_triggered_~__retres1~0#1 := 0; 3703#L167-3 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3787#L168-3 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 3849#L405-9 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3728#L405-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3729#L175-9 assume !(1 == ~t1_pc~0); 3772#L175-11 is_transmit1_triggered_~__retres1~1#1 := 0; 3719#L186-3 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3720#L187-3 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 3843#L413-9 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3875#L413-11 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3876#L194-9 assume 1 == ~t2_pc~0; 3813#L195-3 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3743#L205-3 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3814#L206-3 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 3815#L421-9 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3840#L421-11 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3784#L367-3 assume !(1 == ~M_E~0); 3706#L367-5 assume !(1 == ~T1_E~0); 3707#L372-3 assume !(1 == ~T2_E~0); 3724#L377-3 assume !(1 == ~E_1~0); 3725#L382-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3746#L387-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 3841#L244-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 3755#L261-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 3737#L262-1 start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 3738#L547 assume !(0 == start_simulation_~tmp~3#1); 3865#L547-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 3877#L244-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 3781#L261-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 3782#L262-2 stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1; 3759#L502 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3760#L509 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3777#L510 start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 3726#L560 assume !(0 != start_simulation_~tmp___0~1#1); 3727#L528-2 [2021-12-16 10:05:37,729 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:37,729 INFO L85 PathProgramCache]: Analyzing trace with hash -148511807, now seen corresponding path program 1 times [2021-12-16 10:05:37,729 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:37,729 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [167194495] [2021-12-16 10:05:37,729 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:37,730 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:37,741 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:05:37,741 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-16 10:05:37,749 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:05:37,773 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-16 10:05:37,774 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:37,774 INFO L85 PathProgramCache]: Analyzing trace with hash -1550886083, now seen corresponding path program 2 times [2021-12-16 10:05:37,774 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:37,775 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1209119847] [2021-12-16 10:05:37,775 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:37,775 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:37,788 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:37,820 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:05:37,823 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:37,823 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1209119847] [2021-12-16 10:05:37,823 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1209119847] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:37,823 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:37,823 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:05:37,823 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [351466653] [2021-12-16 10:05:37,824 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:37,824 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:05:37,824 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:05:37,824 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-16 10:05:37,824 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-16 10:05:37,825 INFO L87 Difference]: Start difference. First operand 332 states and 460 transitions. cyclomatic complexity: 129 Second operand has 3 states, 3 states have (on average 17.333333333333332) internal successors, (52), 3 states have internal predecessors, (52), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:37,838 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:05:37,838 INFO L93 Difference]: Finished difference Result 413 states and 567 transitions. [2021-12-16 10:05:37,838 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-16 10:05:37,840 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 413 states and 567 transitions. [2021-12-16 10:05:37,842 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 345 [2021-12-16 10:05:37,844 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 413 states to 413 states and 567 transitions. [2021-12-16 10:05:37,844 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 413 [2021-12-16 10:05:37,844 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 413 [2021-12-16 10:05:37,845 INFO L73 IsDeterministic]: Start isDeterministic. Operand 413 states and 567 transitions. [2021-12-16 10:05:37,845 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:05:37,845 INFO L681 BuchiCegarLoop]: Abstraction has 413 states and 567 transitions. [2021-12-16 10:05:37,845 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 413 states and 567 transitions. [2021-12-16 10:05:37,850 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 413 to 413. [2021-12-16 10:05:37,851 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 413 states, 413 states have (on average 1.3728813559322033) internal successors, (567), 412 states have internal predecessors, (567), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:37,852 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 413 states to 413 states and 567 transitions. [2021-12-16 10:05:37,852 INFO L704 BuchiCegarLoop]: Abstraction has 413 states and 567 transitions. [2021-12-16 10:05:37,852 INFO L587 BuchiCegarLoop]: Abstraction has 413 states and 567 transitions. [2021-12-16 10:05:37,852 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2021-12-16 10:05:37,852 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 413 states and 567 transitions. [2021-12-16 10:05:37,854 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 345 [2021-12-16 10:05:37,854 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:05:37,854 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:05:37,855 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:37,855 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:37,855 INFO L791 eck$LassoCheckResult]: Stem: 4658#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 4635#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 4448#L491 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4449#L214 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4651#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 4541#L221-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4514#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4515#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4502#L334 assume !(0 == ~M_E~0); 4503#L334-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4645#L339-1 assume !(0 == ~T2_E~0); 4845#L344-1 assume !(0 == ~E_1~0); 4843#L349-1 assume !(0 == ~E_2~0); 4841#L354-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4839#L156 assume !(1 == ~m_pc~0); 4836#L156-2 is_master_triggered_~__retres1~0#1 := 0; 4834#L167 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4832#L168 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 4829#L405 assume !(0 != activate_threads_~tmp~1#1); 4827#L405-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4825#L175 assume !(1 == ~t1_pc~0); 4822#L175-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4820#L186 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4819#L187 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 4818#L413 assume !(0 != activate_threads_~tmp___0~0#1); 4817#L413-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4816#L194 assume !(1 == ~t2_pc~0); 4814#L194-2 is_transmit2_triggered_~__retres1~2#1 := 0; 4813#L205 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4812#L206 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 4811#L421 assume !(0 != activate_threads_~tmp___1~0#1); 4810#L421-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4659#L367 assume !(1 == ~M_E~0); 4655#L367-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4614#L372-1 assume !(1 == ~T2_E~0); 4615#L377-1 assume !(1 == ~E_1~0); 4486#L382-1 assume !(1 == ~E_2~0); 4487#L387-1 assume { :end_inline_reset_delta_events } true; 4478#L528-2 [2021-12-16 10:05:37,859 INFO L793 eck$LassoCheckResult]: Loop: 4478#L528-2 assume !false; 4568#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4540#L309 assume !false; 4518#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 4459#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 4460#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 4606#L262 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 4663#L276 assume !(0 != eval_~tmp~0#1); 4662#L324 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4562#L214-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4563#L334-3 assume !(0 == ~M_E~0); 4636#L334-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4637#L339-3 assume !(0 == ~T2_E~0); 4807#L344-3 assume !(0 == ~E_1~0); 4805#L349-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4803#L354-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4801#L156-9 assume !(1 == ~m_pc~0); 4798#L156-11 is_master_triggered_~__retres1~0#1 := 0; 4795#L167-3 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4793#L168-3 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 4791#L405-9 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4789#L405-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4784#L175-9 assume !(1 == ~t1_pc~0); 4782#L175-11 is_transmit1_triggered_~__retres1~1#1 := 0; 4780#L186-3 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4778#L187-3 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 4776#L413-9 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4774#L413-11 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4772#L194-9 assume 1 == ~t2_pc~0; 4768#L195-3 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4766#L205-3 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4764#L206-3 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 4762#L421-9 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4760#L421-11 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4759#L367-3 assume !(1 == ~M_E~0); 4757#L367-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4756#L372-3 assume !(1 == ~T2_E~0); 4755#L377-3 assume !(1 == ~E_1~0); 4754#L382-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4753#L387-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 4751#L244-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 4749#L261-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 4745#L262-1 start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 4744#L547 assume !(0 == start_simulation_~tmp~3#1); 4742#L547-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 4631#L244-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 4531#L261-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 4532#L262-2 stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1; 4510#L502 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4511#L509 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4527#L510 start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 4477#L560 assume !(0 != start_simulation_~tmp___0~1#1); 4478#L528-2 [2021-12-16 10:05:37,859 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:37,859 INFO L85 PathProgramCache]: Analyzing trace with hash -1536562243, now seen corresponding path program 1 times [2021-12-16 10:05:37,859 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:37,860 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1395738370] [2021-12-16 10:05:37,860 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:37,862 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:37,871 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:37,893 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:05:37,893 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:37,894 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1395738370] [2021-12-16 10:05:37,894 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1395738370] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:37,894 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:37,894 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:05:37,895 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [528721190] [2021-12-16 10:05:37,895 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:37,895 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:05:37,895 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:37,896 INFO L85 PathProgramCache]: Analyzing trace with hash 37461819, now seen corresponding path program 1 times [2021-12-16 10:05:37,896 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:37,896 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2047871222] [2021-12-16 10:05:37,896 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:37,896 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:37,906 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:37,937 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:05:37,938 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:37,938 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2047871222] [2021-12-16 10:05:37,938 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2047871222] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:37,945 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:37,945 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-16 10:05:37,945 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [164212329] [2021-12-16 10:05:37,946 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:37,946 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:05:37,946 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:05:37,946 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-16 10:05:37,947 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-16 10:05:37,947 INFO L87 Difference]: Start difference. First operand 413 states and 567 transitions. cyclomatic complexity: 155 Second operand has 4 states, 4 states have (on average 9.5) internal successors, (38), 3 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:37,986 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:05:37,987 INFO L93 Difference]: Finished difference Result 465 states and 639 transitions. [2021-12-16 10:05:37,987 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-16 10:05:37,989 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 465 states and 639 transitions. [2021-12-16 10:05:37,991 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 420 [2021-12-16 10:05:37,993 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 465 states to 465 states and 639 transitions. [2021-12-16 10:05:37,993 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 465 [2021-12-16 10:05:37,993 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 465 [2021-12-16 10:05:37,993 INFO L73 IsDeterministic]: Start isDeterministic. Operand 465 states and 639 transitions. [2021-12-16 10:05:37,994 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:05:37,994 INFO L681 BuchiCegarLoop]: Abstraction has 465 states and 639 transitions. [2021-12-16 10:05:37,994 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 465 states and 639 transitions. [2021-12-16 10:05:37,998 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 465 to 332. [2021-12-16 10:05:37,998 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 332 states, 332 states have (on average 1.3765060240963856) internal successors, (457), 331 states have internal predecessors, (457), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:37,999 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 332 states to 332 states and 457 transitions. [2021-12-16 10:05:38,000 INFO L704 BuchiCegarLoop]: Abstraction has 332 states and 457 transitions. [2021-12-16 10:05:38,000 INFO L587 BuchiCegarLoop]: Abstraction has 332 states and 457 transitions. [2021-12-16 10:05:38,000 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2021-12-16 10:05:38,000 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 332 states and 457 transitions. [2021-12-16 10:05:38,001 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 291 [2021-12-16 10:05:38,001 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:05:38,002 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:05:38,002 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:38,003 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:38,003 INFO L791 eck$LassoCheckResult]: Stem: 5537#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 5521#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 5338#L491 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5339#L214 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5529#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 5431#L221-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5404#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5405#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5392#L334 assume !(0 == ~M_E~0); 5393#L334-2 assume !(0 == ~T1_E~0); 5483#L339-1 assume !(0 == ~T2_E~0); 5477#L344-1 assume !(0 == ~E_1~0); 5478#L349-1 assume !(0 == ~E_2~0); 5402#L354-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5403#L156 assume !(1 == ~m_pc~0); 5348#L156-2 is_master_triggered_~__retres1~0#1 := 0; 5511#L167 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5499#L168 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 5453#L405 assume !(0 != activate_threads_~tmp~1#1); 5438#L405-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5439#L175 assume !(1 == ~t1_pc~0); 5443#L175-2 is_transmit1_triggered_~__retres1~1#1 := 0; 5440#L186 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5441#L187 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 5485#L413 assume !(0 != activate_threads_~tmp___0~0#1); 5488#L413-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5531#L194 assume !(1 == ~t2_pc~0); 5476#L194-2 is_transmit2_triggered_~__retres1~2#1 := 0; 5449#L205 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5396#L206 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 5381#L421 assume !(0 != activate_threads_~tmp___1~0#1); 5382#L421-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5357#L367 assume !(1 == ~M_E~0); 5358#L367-2 assume !(1 == ~T1_E~0); 5503#L372-1 assume !(1 == ~T2_E~0); 5504#L377-1 assume !(1 == ~E_1~0); 5376#L382-1 assume !(1 == ~E_2~0); 5377#L387-1 assume { :end_inline_reset_delta_events } true; 5368#L528-2 [2021-12-16 10:05:38,003 INFO L793 eck$LassoCheckResult]: Loop: 5368#L528-2 assume !false; 5458#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5430#L309 assume !false; 5408#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 5349#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 5350#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 5495#L262 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 5335#L276 assume !(0 != eval_~tmp~0#1); 5337#L324 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5359#L214-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5452#L334-3 assume !(0 == ~M_E~0); 5522#L334-5 assume !(0 == ~T1_E~0); 5486#L339-3 assume !(0 == ~T2_E~0); 5487#L344-3 assume !(0 == ~E_1~0); 5451#L349-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5390#L354-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5391#L156-9 assume !(1 == ~m_pc~0); 5343#L156-11 is_master_triggered_~__retres1~0#1 := 0; 5344#L167-3 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5428#L168-3 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 5490#L405-9 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 5369#L405-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5370#L175-9 assume !(1 == ~t1_pc~0); 5413#L175-11 is_transmit1_triggered_~__retres1~1#1 := 0; 5360#L186-3 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5361#L187-3 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 5484#L413-9 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5516#L413-11 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5517#L194-9 assume !(1 == ~t2_pc~0); 5385#L194-11 is_transmit2_triggered_~__retres1~2#1 := 0; 5386#L205-3 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5455#L206-3 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 5456#L421-9 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5481#L421-11 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5425#L367-3 assume !(1 == ~M_E~0); 5345#L367-5 assume !(1 == ~T1_E~0); 5346#L372-3 assume !(1 == ~T2_E~0); 5365#L377-3 assume !(1 == ~E_1~0); 5366#L382-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5387#L387-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 5482#L244-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 5395#L261-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 5378#L262-1 start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 5379#L547 assume !(0 == start_simulation_~tmp~3#1); 5506#L547-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 5518#L244-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 5420#L261-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 5421#L262-2 stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1; 5400#L502 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5401#L509 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5418#L510 start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 5367#L560 assume !(0 != start_simulation_~tmp___0~1#1); 5368#L528-2 [2021-12-16 10:05:38,003 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:38,004 INFO L85 PathProgramCache]: Analyzing trace with hash -148511807, now seen corresponding path program 2 times [2021-12-16 10:05:38,004 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:38,005 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1800397098] [2021-12-16 10:05:38,005 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:38,006 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:38,012 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:05:38,013 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-16 10:05:38,017 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:05:38,023 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-16 10:05:38,024 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:38,024 INFO L85 PathProgramCache]: Analyzing trace with hash 1577332958, now seen corresponding path program 1 times [2021-12-16 10:05:38,024 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:38,024 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1938740701] [2021-12-16 10:05:38,024 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:38,025 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:38,035 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:38,056 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:05:38,057 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:38,057 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1938740701] [2021-12-16 10:05:38,057 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1938740701] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:38,057 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:38,057 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-16 10:05:38,057 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1337410326] [2021-12-16 10:05:38,057 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:38,058 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:05:38,058 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:05:38,058 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-16 10:05:38,058 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-16 10:05:38,059 INFO L87 Difference]: Start difference. First operand 332 states and 457 transitions. cyclomatic complexity: 126 Second operand has 5 states, 5 states have (on average 10.4) internal successors, (52), 5 states have internal predecessors, (52), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:38,108 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:05:38,108 INFO L93 Difference]: Finished difference Result 553 states and 755 transitions. [2021-12-16 10:05:38,109 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2021-12-16 10:05:38,109 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 553 states and 755 transitions. [2021-12-16 10:05:38,111 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 512 [2021-12-16 10:05:38,113 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 553 states to 553 states and 755 transitions. [2021-12-16 10:05:38,113 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 553 [2021-12-16 10:05:38,114 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 553 [2021-12-16 10:05:38,114 INFO L73 IsDeterministic]: Start isDeterministic. Operand 553 states and 755 transitions. [2021-12-16 10:05:38,114 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:05:38,114 INFO L681 BuchiCegarLoop]: Abstraction has 553 states and 755 transitions. [2021-12-16 10:05:38,115 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 553 states and 755 transitions. [2021-12-16 10:05:38,118 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 553 to 338. [2021-12-16 10:05:38,118 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 338 states, 338 states have (on average 1.3698224852071006) internal successors, (463), 337 states have internal predecessors, (463), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:38,119 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 338 states to 338 states and 463 transitions. [2021-12-16 10:05:38,119 INFO L704 BuchiCegarLoop]: Abstraction has 338 states and 463 transitions. [2021-12-16 10:05:38,119 INFO L587 BuchiCegarLoop]: Abstraction has 338 states and 463 transitions. [2021-12-16 10:05:38,119 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2021-12-16 10:05:38,119 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 338 states and 463 transitions. [2021-12-16 10:05:38,120 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 297 [2021-12-16 10:05:38,121 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:05:38,121 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:05:38,121 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:38,121 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:38,121 INFO L791 eck$LassoCheckResult]: Stem: 6456#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 6434#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 6238#L491 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6239#L214 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6446#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 6335#L221-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6308#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6309#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6294#L334 assume !(0 == ~M_E~0); 6295#L334-2 assume !(0 == ~T1_E~0); 6390#L339-1 assume !(0 == ~T2_E~0); 6383#L344-1 assume !(0 == ~E_1~0); 6384#L349-1 assume !(0 == ~E_2~0); 6306#L354-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6307#L156 assume !(1 == ~m_pc~0); 6248#L156-2 is_master_triggered_~__retres1~0#1 := 0; 6420#L167 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6409#L168 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 6357#L405 assume !(0 != activate_threads_~tmp~1#1); 6342#L405-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6343#L175 assume !(1 == ~t1_pc~0); 6348#L175-2 is_transmit1_triggered_~__retres1~1#1 := 0; 6344#L186 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6345#L187 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 6393#L413 assume !(0 != activate_threads_~tmp___0~0#1); 6394#L413-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6449#L194 assume !(1 == ~t2_pc~0); 6382#L194-2 is_transmit2_triggered_~__retres1~2#1 := 0; 6352#L205 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6300#L206 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 6282#L421 assume !(0 != activate_threads_~tmp___1~0#1); 6283#L421-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6257#L367 assume !(1 == ~M_E~0); 6258#L367-2 assume !(1 == ~T1_E~0); 6413#L372-1 assume !(1 == ~T2_E~0); 6414#L377-1 assume !(1 == ~E_1~0); 6277#L382-1 assume !(1 == ~E_2~0); 6278#L387-1 assume { :end_inline_reset_delta_events } true; 6269#L528-2 [2021-12-16 10:05:38,122 INFO L793 eck$LassoCheckResult]: Loop: 6269#L528-2 assume !false; 6363#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 6334#L309 assume !false; 6315#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 6249#L244 assume !(0 == ~m_st~0); 6251#L248 assume !(0 == ~t1_st~0); 6403#L252 assume !(0 == ~t2_st~0);exists_runnable_thread_~__retres1~3#1 := 0; 6437#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 6465#L262 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 6458#L276 assume !(0 != eval_~tmp~0#1); 6459#L324 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 6358#L214-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 6359#L334-3 assume !(0 == ~M_E~0); 6457#L334-5 assume !(0 == ~T1_E~0); 6487#L339-3 assume !(0 == ~T2_E~0); 6486#L344-3 assume !(0 == ~E_1~0); 6356#L349-3 assume 0 == ~E_2~0;~E_2~0 := 1; 6292#L354-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6293#L156-9 assume !(1 == ~m_pc~0); 6243#L156-11 is_master_triggered_~__retres1~0#1 := 0; 6244#L167-3 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6332#L168-3 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 6399#L405-9 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 6400#L405-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6476#L175-9 assume !(1 == ~t1_pc~0); 6475#L175-11 is_transmit1_triggered_~__retres1~1#1 := 0; 6474#L186-3 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6391#L187-3 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 6392#L413-9 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 6427#L413-11 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6428#L194-9 assume 1 == ~t2_pc~0; 6451#L195-3 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 6472#L205-3 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6361#L206-3 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 6362#L421-9 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 6387#L421-11 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6328#L367-3 assume !(1 == ~M_E~0); 6329#L367-5 assume !(1 == ~T1_E~0); 6296#L372-3 assume !(1 == ~T2_E~0); 6297#L377-3 assume !(1 == ~E_1~0); 6288#L382-3 assume 1 == ~E_2~0;~E_2~0 := 2; 6289#L387-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 6424#L244-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 6299#L261-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 6542#L262-1 start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 6529#L547 assume !(0 == start_simulation_~tmp~3#1); 6525#L547-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 6429#L244-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 6325#L261-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 6326#L262-2 stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1; 6304#L502 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 6305#L509 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6321#L510 start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 6268#L560 assume !(0 != start_simulation_~tmp___0~1#1); 6269#L528-2 [2021-12-16 10:05:38,122 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:38,122 INFO L85 PathProgramCache]: Analyzing trace with hash -148511807, now seen corresponding path program 3 times [2021-12-16 10:05:38,122 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:38,122 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [490387953] [2021-12-16 10:05:38,122 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:38,123 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:38,126 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:05:38,126 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-16 10:05:38,128 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:05:38,132 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-16 10:05:38,132 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:38,132 INFO L85 PathProgramCache]: Analyzing trace with hash 386960344, now seen corresponding path program 1 times [2021-12-16 10:05:38,132 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:38,132 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [927639244] [2021-12-16 10:05:38,133 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:38,133 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:38,138 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:38,167 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:05:38,167 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:38,167 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [927639244] [2021-12-16 10:05:38,168 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [927639244] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:38,168 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:38,168 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-16 10:05:38,168 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [355498779] [2021-12-16 10:05:38,168 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:38,168 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:05:38,168 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:05:38,169 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-16 10:05:38,169 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-16 10:05:38,169 INFO L87 Difference]: Start difference. First operand 338 states and 463 transitions. cyclomatic complexity: 126 Second operand has 5 states, 5 states have (on average 10.8) internal successors, (54), 5 states have internal predecessors, (54), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:38,249 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:05:38,249 INFO L93 Difference]: Finished difference Result 764 states and 1045 transitions. [2021-12-16 10:05:38,250 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-16 10:05:38,250 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 764 states and 1045 transitions. [2021-12-16 10:05:38,253 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 723 [2021-12-16 10:05:38,255 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 764 states to 764 states and 1045 transitions. [2021-12-16 10:05:38,256 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 764 [2021-12-16 10:05:38,256 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 764 [2021-12-16 10:05:38,256 INFO L73 IsDeterministic]: Start isDeterministic. Operand 764 states and 1045 transitions. [2021-12-16 10:05:38,257 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:05:38,257 INFO L681 BuchiCegarLoop]: Abstraction has 764 states and 1045 transitions. [2021-12-16 10:05:38,257 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 764 states and 1045 transitions. [2021-12-16 10:05:38,261 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 764 to 350. [2021-12-16 10:05:38,261 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 350 states, 350 states have (on average 1.3457142857142856) internal successors, (471), 349 states have internal predecessors, (471), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:38,262 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 350 states to 350 states and 471 transitions. [2021-12-16 10:05:38,262 INFO L704 BuchiCegarLoop]: Abstraction has 350 states and 471 transitions. [2021-12-16 10:05:38,262 INFO L587 BuchiCegarLoop]: Abstraction has 350 states and 471 transitions. [2021-12-16 10:05:38,262 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2021-12-16 10:05:38,262 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 350 states and 471 transitions. [2021-12-16 10:05:38,263 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 309 [2021-12-16 10:05:38,263 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:05:38,264 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:05:38,264 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:38,264 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:38,264 INFO L791 eck$LassoCheckResult]: Stem: 7561#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 7541#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 7353#L491 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7354#L214 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7553#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 7446#L221-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7420#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7421#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7408#L334 assume !(0 == ~M_E~0); 7409#L334-2 assume !(0 == ~T1_E~0); 7501#L339-1 assume !(0 == ~T2_E~0); 7494#L344-1 assume !(0 == ~E_1~0); 7495#L349-1 assume !(0 == ~E_2~0); 7418#L354-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7419#L156 assume !(1 == ~m_pc~0); 7363#L156-2 is_master_triggered_~__retres1~0#1 := 0; 7530#L167 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7520#L168 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 7468#L405 assume !(0 != activate_threads_~tmp~1#1); 7453#L405-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7454#L175 assume !(1 == ~t1_pc~0); 7458#L175-2 is_transmit1_triggered_~__retres1~1#1 := 0; 7455#L186 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7456#L187 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 7503#L413 assume !(0 != activate_threads_~tmp___0~0#1); 7504#L413-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7555#L194 assume !(1 == ~t2_pc~0); 7493#L194-2 is_transmit2_triggered_~__retres1~2#1 := 0; 7462#L205 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7412#L206 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 7397#L421 assume !(0 != activate_threads_~tmp___1~0#1); 7398#L421-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7372#L367 assume !(1 == ~M_E~0); 7373#L367-2 assume !(1 == ~T1_E~0); 7524#L372-1 assume !(1 == ~T2_E~0); 7525#L377-1 assume !(1 == ~E_1~0); 7392#L382-1 assume !(1 == ~E_2~0); 7393#L387-1 assume { :end_inline_reset_delta_events } true; 7384#L528-2 [2021-12-16 10:05:38,265 INFO L793 eck$LassoCheckResult]: Loop: 7384#L528-2 assume !false; 7473#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7445#L309 assume !false; 7427#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 7364#L244 assume !(0 == ~m_st~0); 7366#L248 assume !(0 == ~t1_st~0); 7515#L252 assume !(0 == ~t2_st~0);exists_runnable_thread_~__retres1~3#1 := 0; 7544#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 7655#L262 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 7654#L276 assume !(0 != eval_~tmp~0#1); 7376#L324 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 7377#L214-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 7469#L334-3 assume !(0 == ~M_E~0); 7542#L334-5 assume !(0 == ~T1_E~0); 7505#L339-3 assume !(0 == ~T2_E~0); 7506#L344-3 assume !(0 == ~E_1~0); 7467#L349-3 assume 0 == ~E_2~0;~E_2~0 := 1; 7406#L354-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7407#L156-9 assume !(1 == ~m_pc~0); 7514#L156-11 is_master_triggered_~__retres1~0#1 := 0; 7698#L167-3 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7697#L168-3 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 7696#L405-9 assume !(0 != activate_threads_~tmp~1#1); 7695#L405-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7693#L175-9 assume !(1 == ~t1_pc~0); 7692#L175-11 is_transmit1_triggered_~__retres1~1#1 := 0; 7691#L186-3 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7690#L187-3 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 7689#L413-9 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7688#L413-11 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7687#L194-9 assume 1 == ~t2_pc~0; 7685#L195-3 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 7684#L205-3 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7683#L206-3 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 7498#L421-9 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 7499#L421-11 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7440#L367-3 assume !(1 == ~M_E~0); 7360#L367-5 assume !(1 == ~T1_E~0); 7361#L372-3 assume !(1 == ~T2_E~0); 7381#L377-3 assume !(1 == ~E_1~0); 7382#L382-3 assume 1 == ~E_2~0;~E_2~0 := 2; 7403#L387-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 7500#L244-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 7411#L261-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 7394#L262-1 start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 7395#L547 assume !(0 == start_simulation_~tmp~3#1); 7526#L547-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 7538#L244-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 7437#L261-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 7438#L262-2 stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1; 7416#L502 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 7417#L509 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 7433#L510 start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 7383#L560 assume !(0 != start_simulation_~tmp___0~1#1); 7384#L528-2 [2021-12-16 10:05:38,265 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:38,265 INFO L85 PathProgramCache]: Analyzing trace with hash -148511807, now seen corresponding path program 4 times [2021-12-16 10:05:38,265 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:38,265 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [222479143] [2021-12-16 10:05:38,265 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:38,266 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:38,269 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:05:38,269 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-16 10:05:38,271 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:05:38,275 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-16 10:05:38,275 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:38,275 INFO L85 PathProgramCache]: Analyzing trace with hash 661719958, now seen corresponding path program 1 times [2021-12-16 10:05:38,275 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:38,275 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [490947032] [2021-12-16 10:05:38,275 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:38,276 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:38,279 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:38,287 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:05:38,287 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:38,287 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [490947032] [2021-12-16 10:05:38,287 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [490947032] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:38,287 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:38,287 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:05:38,288 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1358706084] [2021-12-16 10:05:38,288 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:38,288 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:05:38,288 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:05:38,288 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-16 10:05:38,288 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-16 10:05:38,289 INFO L87 Difference]: Start difference. First operand 350 states and 471 transitions. cyclomatic complexity: 122 Second operand has 3 states, 3 states have (on average 18.0) internal successors, (54), 3 states have internal predecessors, (54), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:38,307 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:05:38,307 INFO L93 Difference]: Finished difference Result 549 states and 731 transitions. [2021-12-16 10:05:38,308 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-16 10:05:38,308 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 549 states and 731 transitions. [2021-12-16 10:05:38,310 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 508 [2021-12-16 10:05:38,312 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 549 states to 549 states and 731 transitions. [2021-12-16 10:05:38,312 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 549 [2021-12-16 10:05:38,312 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 549 [2021-12-16 10:05:38,312 INFO L73 IsDeterministic]: Start isDeterministic. Operand 549 states and 731 transitions. [2021-12-16 10:05:38,313 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:05:38,313 INFO L681 BuchiCegarLoop]: Abstraction has 549 states and 731 transitions. [2021-12-16 10:05:38,313 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 549 states and 731 transitions. [2021-12-16 10:05:38,317 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 549 to 531. [2021-12-16 10:05:38,318 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 531 states, 531 states have (on average 1.3314500941619585) internal successors, (707), 530 states have internal predecessors, (707), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:38,319 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 531 states to 531 states and 707 transitions. [2021-12-16 10:05:38,319 INFO L704 BuchiCegarLoop]: Abstraction has 531 states and 707 transitions. [2021-12-16 10:05:38,319 INFO L587 BuchiCegarLoop]: Abstraction has 531 states and 707 transitions. [2021-12-16 10:05:38,319 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2021-12-16 10:05:38,319 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 531 states and 707 transitions. [2021-12-16 10:05:38,321 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 490 [2021-12-16 10:05:38,321 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:05:38,321 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:05:38,321 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:38,321 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:38,322 INFO L791 eck$LassoCheckResult]: Stem: 8493#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 8463#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 8258#L491 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8259#L214 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 8482#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 8356#L221-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8327#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8328#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8314#L334 assume !(0 == ~M_E~0); 8315#L334-2 assume !(0 == ~T1_E~0); 8415#L339-1 assume !(0 == ~T2_E~0); 8409#L344-1 assume !(0 == ~E_1~0); 8410#L349-1 assume !(0 == ~E_2~0); 8325#L354-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8326#L156 assume !(1 == ~m_pc~0); 8268#L156-2 is_master_triggered_~__retres1~0#1 := 0; 8446#L167 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8436#L168 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 8378#L405 assume !(0 != activate_threads_~tmp~1#1); 8362#L405-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8363#L175 assume !(1 == ~t1_pc~0); 8369#L175-2 is_transmit1_triggered_~__retres1~1#1 := 0; 8364#L186 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8365#L187 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 8417#L413 assume !(0 != activate_threads_~tmp___0~0#1); 8418#L413-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8485#L194 assume !(1 == ~t2_pc~0); 8408#L194-2 is_transmit2_triggered_~__retres1~2#1 := 0; 8375#L205 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8319#L206 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 8302#L421 assume !(0 != activate_threads_~tmp___1~0#1); 8303#L421-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8276#L367 assume !(1 == ~M_E~0); 8277#L367-2 assume !(1 == ~T1_E~0); 8440#L372-1 assume !(1 == ~T2_E~0); 8441#L377-1 assume !(1 == ~E_1~0); 8297#L382-1 assume !(1 == ~E_2~0); 8298#L387-1 assume { :end_inline_reset_delta_events } true; 8381#L528-2 [2021-12-16 10:05:38,322 INFO L793 eck$LassoCheckResult]: Loop: 8381#L528-2 assume !false; 8386#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 8355#L309 assume !false; 8331#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 8332#L244 assume !(0 == ~m_st~0); 8270#L248 assume !(0 == ~t1_st~0); 8429#L252 assume !(0 == ~t2_st~0);exists_runnable_thread_~__retres1~3#1 := 0; 8499#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 8498#L262 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 8497#L276 assume !(0 != eval_~tmp~0#1); 8496#L324 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8379#L214-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8380#L334-3 assume !(0 == ~M_E~0); 8464#L334-5 assume !(0 == ~T1_E~0); 8419#L339-3 assume !(0 == ~T2_E~0); 8420#L344-3 assume !(0 == ~E_1~0); 8377#L349-3 assume 0 == ~E_2~0;~E_2~0 := 1; 8312#L354-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8313#L156-9 assume !(1 == ~m_pc~0); 8403#L156-11 is_master_triggered_~__retres1~0#1 := 0; 8772#L167-3 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8771#L168-3 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 8425#L405-9 assume !(0 != activate_threads_~tmp~1#1); 8426#L405-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8754#L175-9 assume !(1 == ~t1_pc~0); 8752#L175-11 is_transmit1_triggered_~__retres1~1#1 := 0; 8750#L186-3 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8747#L187-3 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 8744#L413-9 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8453#L413-11 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8454#L194-9 assume !(1 == ~t2_pc~0); 8306#L194-11 is_transmit2_triggered_~__retres1~2#1 := 0; 8307#L205-3 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8383#L206-3 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 8384#L421-9 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 8413#L421-11 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8349#L367-3 assume !(1 == ~M_E~0); 8265#L367-5 assume !(1 == ~T1_E~0); 8266#L372-3 assume !(1 == ~T2_E~0); 8316#L377-3 assume !(1 == ~E_1~0); 8737#L382-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8736#L387-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 8450#L244-1 assume !(0 == ~m_st~0); 8451#L248-1 assume 0 == ~t1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 8318#L261-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 8720#L262-1 start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 8460#L547 assume 0 == start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 4;assume { :begin_inline_fire_time_events } true;~M_E~0 := 1; 8452#L447 assume { :end_inline_fire_time_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8373#L156-12 assume 1 == ~m_pc~0; 8374#L157-4 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 8489#L167-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8711#L168-4 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 8707#L405-12 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8706#L405-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8273#L175-12 assume !(1 == ~t1_pc~0); 8275#L175-14 is_transmit1_triggered_~__retres1~1#1 := 0; 8700#L186-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8699#L187-4 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 8483#L413-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8484#L413-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8389#L194-12 assume !(1 == ~t2_pc~0); 8390#L194-14 is_transmit2_triggered_~__retres1~2#1 := 0; 8465#L205-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8387#L206-4 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 8388#L421-12 assume !(0 != activate_threads_~tmp___1~0#1); 8639#L421-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_time_events } true; 8633#L454 assume 1 == ~M_E~0;~M_E~0 := 2; 8634#L454-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8784#L459-1 assume !(1 == ~T2_E~0); 8783#L464-1 assume !(1 == ~E_1~0); 8782#L469-1 assume !(1 == ~E_2~0); 8781#L474-1 assume { :end_inline_reset_time_events } true; 8718#L547-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 8779#L244-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 8780#L261-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 8726#L262-2 stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1; 8724#L502 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 8341#L509 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8342#L510 start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 8481#L560 assume !(0 != start_simulation_~tmp___0~1#1); 8381#L528-2 [2021-12-16 10:05:38,322 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:38,322 INFO L85 PathProgramCache]: Analyzing trace with hash -148511807, now seen corresponding path program 5 times [2021-12-16 10:05:38,323 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:38,323 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [937078906] [2021-12-16 10:05:38,323 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:38,323 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:38,326 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:05:38,326 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-16 10:05:38,328 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:05:38,331 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-16 10:05:38,332 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:38,332 INFO L85 PathProgramCache]: Analyzing trace with hash 1445514504, now seen corresponding path program 1 times [2021-12-16 10:05:38,332 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:38,332 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [721700585] [2021-12-16 10:05:38,332 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:38,332 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:38,336 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:38,344 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:05:38,344 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:38,345 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [721700585] [2021-12-16 10:05:38,345 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [721700585] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:38,345 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:38,345 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:05:38,345 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1201331636] [2021-12-16 10:05:38,345 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:38,345 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:05:38,345 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:05:38,346 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-16 10:05:38,346 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-16 10:05:38,346 INFO L87 Difference]: Start difference. First operand 531 states and 707 transitions. cyclomatic complexity: 177 Second operand has 3 states, 3 states have (on average 26.666666666666668) internal successors, (80), 3 states have internal predecessors, (80), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:38,365 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:05:38,366 INFO L93 Difference]: Finished difference Result 903 states and 1190 transitions. [2021-12-16 10:05:38,366 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-16 10:05:38,366 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 903 states and 1190 transitions. [2021-12-16 10:05:38,369 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 863 [2021-12-16 10:05:38,372 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 903 states to 903 states and 1190 transitions. [2021-12-16 10:05:38,372 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 903 [2021-12-16 10:05:38,373 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 903 [2021-12-16 10:05:38,373 INFO L73 IsDeterministic]: Start isDeterministic. Operand 903 states and 1190 transitions. [2021-12-16 10:05:38,374 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:05:38,374 INFO L681 BuchiCegarLoop]: Abstraction has 903 states and 1190 transitions. [2021-12-16 10:05:38,374 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 903 states and 1190 transitions. [2021-12-16 10:05:38,380 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 903 to 899. [2021-12-16 10:05:38,381 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 899 states, 899 states have (on average 1.3192436040044493) internal successors, (1186), 898 states have internal predecessors, (1186), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:38,383 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 899 states to 899 states and 1186 transitions. [2021-12-16 10:05:38,383 INFO L704 BuchiCegarLoop]: Abstraction has 899 states and 1186 transitions. [2021-12-16 10:05:38,383 INFO L587 BuchiCegarLoop]: Abstraction has 899 states and 1186 transitions. [2021-12-16 10:05:38,383 INFO L425 BuchiCegarLoop]: ======== Iteration 13============ [2021-12-16 10:05:38,383 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 899 states and 1186 transitions. [2021-12-16 10:05:38,386 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 859 [2021-12-16 10:05:38,386 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:05:38,386 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:05:38,387 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:38,387 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:38,387 INFO L791 eck$LassoCheckResult]: Stem: 9926#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 9891#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 9698#L491 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 9699#L214 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9913#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 9788#L221-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9760#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 9761#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 9748#L334 assume !(0 == ~M_E~0); 9749#L334-2 assume !(0 == ~T1_E~0); 9846#L339-1 assume !(0 == ~T2_E~0); 9840#L344-1 assume !(0 == ~E_1~0); 9841#L349-1 assume !(0 == ~E_2~0); 9758#L354-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9759#L156 assume !(1 == ~m_pc~0); 9853#L156-2 is_master_triggered_~__retres1~0#1 := 0; 9877#L167 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9865#L168 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 9812#L405 assume !(0 != activate_threads_~tmp~1#1); 9793#L405-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9794#L175 assume !(1 == ~t1_pc~0); 9802#L175-2 is_transmit1_triggered_~__retres1~1#1 := 0; 9795#L186 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9796#L187 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 9848#L413 assume !(0 != activate_threads_~tmp___0~0#1); 9849#L413-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9917#L194 assume !(1 == ~t2_pc~0); 9839#L194-2 is_transmit2_triggered_~__retres1~2#1 := 0; 9806#L205 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9750#L206 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 9737#L421 assume !(0 != activate_threads_~tmp___1~0#1); 9738#L421-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9714#L367 assume !(1 == ~M_E~0); 9715#L367-2 assume !(1 == ~T1_E~0); 9869#L372-1 assume !(1 == ~T2_E~0); 9870#L377-1 assume !(1 == ~E_1~0); 9732#L382-1 assume !(1 == ~E_2~0); 9733#L387-1 assume { :end_inline_reset_delta_events } true; 9815#L528-2 [2021-12-16 10:05:38,388 INFO L793 eck$LassoCheckResult]: Loop: 9815#L528-2 assume !false; 9987#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 9976#L309 assume !false; 9972#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 9973#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 10036#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 10067#L262 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 10032#L276 assume 0 != eval_~tmp~0#1; 10033#L276-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 10028#L284 assume 0 != eval_~tmp_ndt_1~0#1;~m_st~0 := 1;assume { :begin_inline_master } true; 9753#L47 assume 0 == ~m_pc~0; 9754#L74 assume !false; 9836#L59 ~E_1~0 := 1;assume { :begin_inline_immediate_notify } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9837#L156-3 assume !(1 == ~m_pc~0); 9809#L156-5 is_master_triggered_~__retres1~0#1 := 0; 9810#L167-1 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9852#L168-1 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 9826#L405-3 assume !(0 != activate_threads_~tmp~1#1); 9827#L405-5 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9878#L175-3 assume !(1 == ~t1_pc~0); 9729#L175-5 is_transmit1_triggered_~__retres1~1#1 := 0; 9728#L186-1 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9880#L187-1 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 9834#L413-3 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 9792#L413-5 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9766#L194-3 assume !(1 == ~t2_pc~0); 9767#L194-5 is_transmit2_triggered_~__retres1~2#1 := 0; 9781#L205-1 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9910#L206-1 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 9911#L421-3 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 10575#L421-5 assume { :end_inline_activate_threads } true; 9918#L438 assume { :end_inline_immediate_notify } true;~E_1~0 := 2; 9919#L51 assume !false; 9920#L67 ~m_pc~0 := 1;~m_st~0 := 2; 9925#L77 assume { :end_inline_master } true; 10332#L281 assume !(0 == ~t1_st~0); 10341#L295 assume !(0 == ~t2_st~0); 10337#L309 assume !false; 10336#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 10281#L244 assume !(0 == ~m_st~0); 10278#L248 assume !(0 == ~t1_st~0); 10275#L252 assume !(0 == ~t2_st~0);exists_runnable_thread_~__retres1~3#1 := 0; 10273#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 10271#L262 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 9946#L276 assume !(0 != eval_~tmp~0#1); 9948#L324 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 9813#L214-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 9814#L334-3 assume !(0 == ~M_E~0); 9892#L334-5 assume !(0 == ~T1_E~0); 9893#L339-3 assume !(0 == ~T2_E~0); 10228#L344-3 assume !(0 == ~E_1~0); 10226#L349-3 assume 0 == ~E_2~0;~E_2~0 := 1; 10224#L354-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10222#L156-9 assume 1 == ~m_pc~0; 9858#L157-3 assume !(1 == ~M_E~0); 9703#L156-11 is_master_triggered_~__retres1~0#1 := 0; 9704#L167-3 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9785#L168-3 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 9855#L405-9 assume !(0 != activate_threads_~tmp~1#1); 9725#L405-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9726#L175-9 assume !(1 == ~t1_pc~0); 9770#L175-11 is_transmit1_triggered_~__retres1~1#1 := 0; 9718#L186-3 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9719#L187-3 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 9847#L413-9 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 9883#L413-11 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9884#L194-9 assume 1 == ~t2_pc~0; 9816#L195-3 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 9742#L205-3 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9817#L206-3 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 9818#L421-9 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 9844#L421-11 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9782#L367-3 assume !(1 == ~M_E~0); 9705#L367-5 assume !(1 == ~T1_E~0); 9706#L372-3 assume !(1 == ~T2_E~0); 9721#L377-3 assume !(1 == ~E_1~0); 9722#L382-3 assume 1 == ~E_2~0;~E_2~0 := 2; 9743#L387-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 9845#L244-1 assume !(0 == ~m_st~0); 9881#L248-1 assume 0 == ~t1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 10291#L261-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 10292#L262-1 start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 10111#L547 assume 0 == start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 4;assume { :begin_inline_fire_time_events } true;~M_E~0 := 1; 9929#L447 assume { :end_inline_fire_time_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9928#L156-12 assume 1 == ~m_pc~0; 9921#L157-4 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 9922#L167-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10524#L168-4 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 10520#L405-12 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 9923#L405-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9924#L175-12 assume !(1 == ~t1_pc~0); 10510#L175-14 is_transmit1_triggered_~__retres1~1#1 := 0; 10508#L186-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10507#L187-4 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 10506#L413-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 9832#L413-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9823#L194-12 assume !(1 == ~t2_pc~0); 9824#L194-14 is_transmit2_triggered_~__retres1~2#1 := 0; 9894#L205-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9821#L206-4 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 9822#L421-12 assume !(0 != activate_threads_~tmp___1~0#1); 10496#L421-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_time_events } true; 10492#L454 assume !(1 == ~M_E~0); 10493#L454-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 10447#L459-1 assume !(1 == ~T2_E~0); 10448#L464-1 assume !(1 == ~E_1~0); 10389#L469-1 assume !(1 == ~E_2~0); 10390#L474-1 assume { :end_inline_reset_time_events } true; 10385#L547-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 10386#L244-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 10545#L261-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 10544#L262-2 stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1; 9756#L502 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 9757#L509 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 9774#L510 start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 9723#L560 assume !(0 != start_simulation_~tmp___0~1#1); 9724#L528-2 assume !false; 9819#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 9787#L309 assume !false; 9764#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 9765#L244 assume !(0 == ~m_st~0); 9708#L248 assume !(0 == ~t1_st~0); 9859#L252 assume !(0 == ~t2_st~0);exists_runnable_thread_~__retres1~3#1 := 0; 9895#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 10504#L262 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 10501#L276 assume !(0 != eval_~tmp~0#1); 9716#L324 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 9717#L214-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 9936#L334-3 assume 0 == ~M_E~0;~M_E~0 := 1; 9937#L334-5 assume !(0 == ~T1_E~0); 9850#L339-3 assume !(0 == ~T2_E~0); 9851#L344-3 assume !(0 == ~E_1~0); 9914#L349-3 assume 0 == ~E_2~0;~E_2~0 := 1; 9935#L354-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9933#L156-9 assume 1 == ~m_pc~0; 9934#L157-3 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 10442#L167-3 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10440#L168-3 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 10438#L405-9 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 10436#L405-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10432#L175-9 assume !(1 == ~t1_pc~0); 10430#L175-11 is_transmit1_triggered_~__retres1~1#1 := 0; 10428#L186-3 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10426#L187-3 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 10424#L413-9 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 10422#L413-11 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10420#L194-9 assume 1 == ~t2_pc~0; 10416#L195-3 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 10414#L205-3 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10412#L206-3 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 10410#L421-9 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 10408#L421-11 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10405#L367-3 assume !(1 == ~M_E~0); 10403#L367-5 assume !(1 == ~T1_E~0); 10401#L372-3 assume !(1 == ~T2_E~0); 10399#L377-3 assume !(1 == ~E_1~0); 10397#L382-3 assume 1 == ~E_2~0;~E_2~0 := 2; 10395#L387-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 10393#L244-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 10391#L261-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 9734#L262-1 start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 9735#L547 assume 0 == start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 4;assume { :begin_inline_fire_time_events } true;~M_E~0 := 1; 9932#L447 assume { :end_inline_fire_time_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10106#L156-12 assume !(1 == ~m_pc~0); 10104#L156-14 is_master_triggered_~__retres1~0#1 := 0; 10102#L167-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10100#L168-4 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 10098#L405-12 assume !(0 != activate_threads_~tmp~1#1); 10095#L405-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10093#L175-12 assume !(1 == ~t1_pc~0); 10090#L175-14 is_transmit1_triggered_~__retres1~1#1 := 0; 10088#L186-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10086#L187-4 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 10083#L413-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 10081#L413-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10079#L194-12 assume 1 == ~t2_pc~0; 10076#L195-4 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 10074#L205-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10073#L206-4 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 10072#L421-12 assume !(0 != activate_threads_~tmp___1~0#1); 10071#L421-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_time_events } true; 10069#L454 assume 1 == ~M_E~0;~M_E~0 := 2; 10070#L454-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 10263#L459-1 assume !(1 == ~T2_E~0); 10261#L464-1 assume !(1 == ~E_1~0); 10259#L469-1 assume !(1 == ~E_2~0); 10257#L474-1 assume { :end_inline_reset_time_events } true; 10255#L547-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 10252#L244-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 10250#L261-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 10248#L262-2 stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1; 10245#L502 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 10242#L509 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 10237#L510 start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 10235#L560 assume !(0 != start_simulation_~tmp___0~1#1); 9815#L528-2 [2021-12-16 10:05:38,388 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:38,388 INFO L85 PathProgramCache]: Analyzing trace with hash -148511807, now seen corresponding path program 6 times [2021-12-16 10:05:38,388 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:38,389 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1990589105] [2021-12-16 10:05:38,389 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:38,389 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:38,392 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:05:38,392 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-16 10:05:38,394 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:05:38,397 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-16 10:05:38,397 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:38,398 INFO L85 PathProgramCache]: Analyzing trace with hash 1921614430, now seen corresponding path program 1 times [2021-12-16 10:05:38,398 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:38,398 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1079491791] [2021-12-16 10:05:38,398 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:38,398 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:38,404 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:38,424 INFO L134 CoverageAnalysis]: Checked inductivity of 89 backedges. 14 proven. 0 refuted. 0 times theorem prover too weak. 75 trivial. 0 not checked. [2021-12-16 10:05:38,424 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:38,424 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1079491791] [2021-12-16 10:05:38,424 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1079491791] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:38,424 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:38,425 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-16 10:05:38,425 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [187432873] [2021-12-16 10:05:38,425 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:38,425 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:05:38,425 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:05:38,425 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-16 10:05:38,426 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-16 10:05:38,426 INFO L87 Difference]: Start difference. First operand 899 states and 1186 transitions. cyclomatic complexity: 289 Second operand has 5 states, 5 states have (on average 25.6) internal successors, (128), 5 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:38,472 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:05:38,473 INFO L93 Difference]: Finished difference Result 1149 states and 1484 transitions. [2021-12-16 10:05:38,473 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-16 10:05:38,473 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1149 states and 1484 transitions. [2021-12-16 10:05:38,477 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1089 [2021-12-16 10:05:38,480 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1149 states to 1149 states and 1484 transitions. [2021-12-16 10:05:38,481 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1149 [2021-12-16 10:05:38,481 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1149 [2021-12-16 10:05:38,481 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1149 states and 1484 transitions. [2021-12-16 10:05:38,482 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:05:38,482 INFO L681 BuchiCegarLoop]: Abstraction has 1149 states and 1484 transitions. [2021-12-16 10:05:38,483 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1149 states and 1484 transitions. [2021-12-16 10:05:38,490 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1149 to 905. [2021-12-16 10:05:38,491 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 905 states, 905 states have (on average 1.2972375690607736) internal successors, (1174), 904 states have internal predecessors, (1174), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:38,492 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 905 states to 905 states and 1174 transitions. [2021-12-16 10:05:38,492 INFO L704 BuchiCegarLoop]: Abstraction has 905 states and 1174 transitions. [2021-12-16 10:05:38,492 INFO L587 BuchiCegarLoop]: Abstraction has 905 states and 1174 transitions. [2021-12-16 10:05:38,492 INFO L425 BuchiCegarLoop]: ======== Iteration 14============ [2021-12-16 10:05:38,493 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 905 states and 1174 transitions. [2021-12-16 10:05:38,495 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 865 [2021-12-16 10:05:38,495 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:05:38,495 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:05:38,496 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:38,496 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:38,496 INFO L791 eck$LassoCheckResult]: Stem: 12026#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 11980#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 11760#L491 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 11761#L214 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12006#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 11854#L221-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 11824#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 11825#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 11811#L334 assume !(0 == ~M_E~0); 11812#L334-2 assume !(0 == ~T1_E~0); 11920#L339-1 assume !(0 == ~T2_E~0); 11912#L344-1 assume !(0 == ~E_1~0); 11913#L349-1 assume !(0 == ~E_2~0); 11822#L354-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11823#L156 assume !(1 == ~m_pc~0); 11929#L156-2 is_master_triggered_~__retres1~0#1 := 0; 11956#L167 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11942#L168 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 11881#L405 assume !(0 != activate_threads_~tmp~1#1); 11860#L405-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11861#L175 assume !(1 == ~t1_pc~0); 11870#L175-2 is_transmit1_triggered_~__retres1~1#1 := 0; 11862#L186 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11863#L187 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 11923#L413 assume !(0 != activate_threads_~tmp___0~0#1); 11924#L413-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12008#L194 assume !(1 == ~t2_pc~0); 11909#L194-2 is_transmit2_triggered_~__retres1~2#1 := 0; 11874#L205 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11813#L206 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 11799#L421 assume !(0 != activate_threads_~tmp___1~0#1); 11800#L421-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11776#L367 assume !(1 == ~M_E~0); 11777#L367-2 assume !(1 == ~T1_E~0); 11946#L372-1 assume !(1 == ~T2_E~0); 11947#L377-1 assume !(1 == ~E_1~0); 11794#L382-1 assume !(1 == ~E_2~0); 11795#L387-1 assume { :end_inline_reset_delta_events } true; 11883#L528-2 [2021-12-16 10:05:38,497 INFO L793 eck$LassoCheckResult]: Loop: 11883#L528-2 assume !false; 12345#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 12334#L309 assume !false; 12331#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 12326#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 12327#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 12366#L262 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 12363#L276 assume 0 != eval_~tmp~0#1; 12357#L276-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 12353#L284 assume 0 != eval_~tmp_ndt_1~0#1;~m_st~0 := 1;assume { :begin_inline_master } true; 12354#L47 assume 0 == ~m_pc~0; 11996#L74 assume !false; 11997#L59 ~E_1~0 := 1;assume { :begin_inline_immediate_notify } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12027#L156-3 assume !(1 == ~m_pc~0); 12028#L156-5 is_master_triggered_~__retres1~0#1 := 0; 12021#L167-1 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12022#L168-1 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 11894#L405-3 assume !(0 != activate_threads_~tmp~1#1); 11895#L405-5 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11988#L175-3 assume 1 == ~t1_pc~0; 11989#L176-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 12648#L186-1 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12646#L187-1 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 12644#L413-3 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 12643#L413-5 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11829#L194-3 assume !(1 == ~t2_pc~0); 11830#L194-5 is_transmit2_triggered_~__retres1~2#1 := 0; 11846#L205-1 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11991#L206-1 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 11995#L421-3 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 11826#L421-5 assume { :end_inline_activate_threads } true; 11827#L438 assume { :end_inline_immediate_notify } true;~E_1~0 := 2; 12009#L51 assume !false; 12015#L67 ~m_pc~0 := 1;~m_st~0 := 2; 12000#L77 assume { :end_inline_master } true; 11950#L281 assume !(0 == ~t1_st~0); 11951#L295 assume !(0 == ~t2_st~0); 12623#L309 assume !false; 12620#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 12618#L244 assume !(0 == ~m_st~0); 12464#L248 assume !(0 == ~t1_st~0); 12613#L252 assume !(0 == ~t2_st~0);exists_runnable_thread_~__retres1~3#1 := 0; 12610#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 12608#L262 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 12606#L276 assume !(0 != eval_~tmp~0#1); 12605#L324 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 12599#L214-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 12030#L334-3 assume !(0 == ~M_E~0); 11981#L334-5 assume !(0 == ~T1_E~0); 11925#L339-3 assume !(0 == ~T2_E~0); 11926#L344-3 assume !(0 == ~E_1~0); 11879#L349-3 assume 0 == ~E_2~0;~E_2~0 := 1; 11880#L354-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12140#L156-9 assume 1 == ~m_pc~0; 11934#L157-3 assume !(1 == ~M_E~0); 11935#L156-11 is_master_triggered_~__retres1~0#1 := 0; 12449#L167-3 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12143#L168-3 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 12136#L405-9 assume !(0 != activate_threads_~tmp~1#1); 12135#L405-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12016#L175-9 assume !(1 == ~t1_pc~0); 11833#L175-11 is_transmit1_triggered_~__retres1~1#1 := 0; 11780#L186-3 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11781#L187-3 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 11978#L413-9 assume !(0 != activate_threads_~tmp___0~0#1); 11979#L413-11 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12012#L194-9 assume 1 == ~t2_pc~0; 12013#L195-3 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 12023#L205-3 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12024#L206-3 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 11916#L421-9 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 11917#L421-11 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11847#L367-3 assume !(1 == ~M_E~0); 11848#L367-5 assume !(1 == ~T1_E~0); 12633#L372-3 assume !(1 == ~T2_E~0); 12632#L377-3 assume !(1 == ~E_1~0); 12631#L382-3 assume 1 == ~E_2~0;~E_2~0 := 2; 12630#L387-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 12629#L244-1 assume !(0 == ~m_st~0); 12058#L248-1 assume 0 == ~t1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 12039#L261-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 12040#L262-1 start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 12035#L547 assume 0 == start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 4;assume { :begin_inline_fire_time_events } true;~M_E~0 := 1; 12036#L447 assume { :end_inline_fire_time_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12031#L156-12 assume 1 == ~m_pc~0; 12032#L157-4 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 12523#L167-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12522#L168-4 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 12521#L405-12 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12025#L405-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11773#L175-12 assume !(1 == ~t1_pc~0); 11775#L175-14 is_transmit1_triggered_~__retres1~1#1 := 0; 11899#L186-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11953#L187-4 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 12007#L413-12 assume !(0 != activate_threads_~tmp___0~0#1); 11900#L413-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11891#L194-12 assume !(1 == ~t2_pc~0); 11892#L194-14 is_transmit2_triggered_~__retres1~2#1 := 0; 11982#L205-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11889#L206-4 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 11890#L421-12 assume !(0 != activate_threads_~tmp___1~0#1); 11954#L421-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_time_events } true; 11955#L454 assume !(1 == ~M_E~0); 12503#L454-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12581#L459-1 assume !(1 == ~T2_E~0); 12579#L464-1 assume !(1 == ~E_1~0); 12577#L469-1 assume !(1 == ~E_2~0); 12575#L474-1 assume { :end_inline_reset_time_events } true; 12323#L547-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 12571#L244-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 12569#L261-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 12567#L262-2 stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1; 12565#L502 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 12563#L509 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 12561#L510 start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 12559#L560 assume !(0 != start_simulation_~tmp___0~1#1); 12556#L528-2 assume !false; 12553#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 12549#L309 assume !false; 12548#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 12132#L244 assume !(0 == ~m_st~0); 11770#L248 assume !(0 == ~t1_st~0); 11936#L252 assume !(0 == ~t2_st~0);exists_runnable_thread_~__retres1~3#1 := 0; 11984#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 12639#L262 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 12638#L276 assume !(0 != eval_~tmp~0#1); 11778#L324 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 11779#L214-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 11882#L334-3 assume 0 == ~M_E~0;~M_E~0 := 1; 12547#L334-5 assume !(0 == ~T1_E~0); 12544#L339-3 assume !(0 == ~T2_E~0); 12536#L344-3 assume !(0 == ~E_1~0); 12535#L349-3 assume 0 == ~E_2~0;~E_2~0 := 1; 12047#L354-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12045#L156-9 assume 1 == ~m_pc~0; 12046#L157-3 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 12137#L167-3 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12131#L168-3 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 12092#L405-9 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12089#L405-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12087#L175-9 assume !(1 == ~t1_pc~0); 12086#L175-11 is_transmit1_triggered_~__retres1~1#1 := 0; 12085#L186-3 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12084#L187-3 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 12083#L413-9 assume !(0 != activate_threads_~tmp___0~0#1); 12082#L413-11 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12081#L194-9 assume !(1 == ~t2_pc~0); 12080#L194-11 is_transmit2_triggered_~__retres1~2#1 := 0; 12078#L205-3 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12077#L206-3 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 12076#L421-9 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 12075#L421-11 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12073#L367-3 assume 1 == ~M_E~0;~M_E~0 := 2; 12072#L367-5 assume !(1 == ~T1_E~0); 12069#L372-3 assume !(1 == ~T2_E~0); 12070#L377-3 assume !(1 == ~E_1~0); 12063#L382-3 assume 1 == ~E_2~0;~E_2~0 := 2; 12064#L387-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 12056#L244-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 12057#L261-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 12442#L262-1 start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 12443#L547 assume 0 == start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 4;assume { :begin_inline_fire_time_events } true;~M_E~0 := 1; 12033#L447 assume { :end_inline_fire_time_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12034#L156-12 assume !(1 == ~m_pc~0); 12313#L156-14 is_master_triggered_~__retres1~0#1 := 0; 12309#L167-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12304#L168-4 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 12299#L405-12 assume !(0 != activate_threads_~tmp~1#1); 12295#L405-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12291#L175-12 assume !(1 == ~t1_pc~0); 12284#L175-14 is_transmit1_triggered_~__retres1~1#1 := 0; 12278#L186-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12273#L187-4 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 12269#L413-12 assume !(0 != activate_threads_~tmp___0~0#1); 12264#L413-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12254#L194-12 assume 1 == ~t2_pc~0; 12251#L195-4 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 12249#L205-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12246#L206-4 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 12244#L421-12 assume !(0 != activate_threads_~tmp___1~0#1); 12241#L421-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_time_events } true; 12238#L454 assume 1 == ~M_E~0;~M_E~0 := 2; 12239#L454-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12385#L459-1 assume !(1 == ~T2_E~0); 12383#L464-1 assume !(1 == ~E_1~0); 12381#L469-1 assume !(1 == ~E_2~0); 12379#L474-1 assume { :end_inline_reset_time_events } true; 12377#L547-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 12373#L244-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 12371#L261-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 12369#L262-2 stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1; 12367#L502 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 12364#L509 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 12359#L510 start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 12355#L560 assume !(0 != start_simulation_~tmp___0~1#1); 11883#L528-2 [2021-12-16 10:05:38,497 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:38,497 INFO L85 PathProgramCache]: Analyzing trace with hash -148511807, now seen corresponding path program 7 times [2021-12-16 10:05:38,498 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:38,498 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [712119566] [2021-12-16 10:05:38,498 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:38,498 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:38,501 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:05:38,501 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-16 10:05:38,503 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:05:38,518 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-16 10:05:38,518 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:38,518 INFO L85 PathProgramCache]: Analyzing trace with hash -1553370430, now seen corresponding path program 1 times [2021-12-16 10:05:38,519 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:38,519 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1220812602] [2021-12-16 10:05:38,519 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:38,519 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:38,525 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:38,544 INFO L134 CoverageAnalysis]: Checked inductivity of 88 backedges. 14 proven. 0 refuted. 0 times theorem prover too weak. 74 trivial. 0 not checked. [2021-12-16 10:05:38,545 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:38,545 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1220812602] [2021-12-16 10:05:38,545 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1220812602] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:38,545 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:38,545 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-16 10:05:38,545 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [345642812] [2021-12-16 10:05:38,545 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:38,546 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:05:38,546 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:05:38,546 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-16 10:05:38,546 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-16 10:05:38,546 INFO L87 Difference]: Start difference. First operand 905 states and 1174 transitions. cyclomatic complexity: 271 Second operand has 5 states, 5 states have (on average 26.2) internal successors, (131), 5 states have internal predecessors, (131), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:38,606 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:05:38,606 INFO L93 Difference]: Finished difference Result 2211 states and 2851 transitions. [2021-12-16 10:05:38,606 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-16 10:05:38,606 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2211 states and 2851 transitions. [2021-12-16 10:05:38,614 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2154 [2021-12-16 10:05:38,620 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2211 states to 2211 states and 2851 transitions. [2021-12-16 10:05:38,620 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2211 [2021-12-16 10:05:38,621 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2211 [2021-12-16 10:05:38,621 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2211 states and 2851 transitions. [2021-12-16 10:05:38,623 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:05:38,623 INFO L681 BuchiCegarLoop]: Abstraction has 2211 states and 2851 transitions. [2021-12-16 10:05:38,624 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2211 states and 2851 transitions. [2021-12-16 10:05:38,634 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2211 to 965. [2021-12-16 10:05:38,635 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 965 states, 965 states have (on average 1.2787564766839379) internal successors, (1234), 964 states have internal predecessors, (1234), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:38,637 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 965 states to 965 states and 1234 transitions. [2021-12-16 10:05:38,637 INFO L704 BuchiCegarLoop]: Abstraction has 965 states and 1234 transitions. [2021-12-16 10:05:38,637 INFO L587 BuchiCegarLoop]: Abstraction has 965 states and 1234 transitions. [2021-12-16 10:05:38,637 INFO L425 BuchiCegarLoop]: ======== Iteration 15============ [2021-12-16 10:05:38,637 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 965 states and 1234 transitions. [2021-12-16 10:05:38,640 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 922 [2021-12-16 10:05:38,640 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:05:38,640 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:05:38,641 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:38,641 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:38,641 INFO L791 eck$LassoCheckResult]: Stem: 15151#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 15103#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 14890#L491 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 14891#L214 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 15132#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 14986#L221-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 14955#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 14956#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 14941#L334 assume !(0 == ~M_E~0); 14942#L334-2 assume !(0 == ~T1_E~0); 15049#L339-1 assume !(0 == ~T2_E~0); 15042#L344-1 assume !(0 == ~E_1~0); 15043#L349-1 assume !(0 == ~E_2~0); 14953#L354-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14954#L156 assume !(1 == ~m_pc~0); 15058#L156-2 is_master_triggered_~__retres1~0#1 := 0; 15082#L167 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 15072#L168 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 15012#L405 assume !(0 != activate_threads_~tmp~1#1); 14991#L405-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14992#L175 assume !(1 == ~t1_pc~0); 14999#L175-2 is_transmit1_triggered_~__retres1~1#1 := 0; 14993#L186 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14994#L187 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 15052#L413 assume !(0 != activate_threads_~tmp___0~0#1); 15053#L413-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15134#L194 assume !(1 == ~t2_pc~0); 15040#L194-2 is_transmit2_triggered_~__retres1~2#1 := 0; 15003#L205 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 15004#L206 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 14930#L421 assume !(0 != activate_threads_~tmp___1~0#1); 14931#L421-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14906#L367 assume !(1 == ~M_E~0); 14907#L367-2 assume !(1 == ~T1_E~0); 15076#L372-1 assume !(1 == ~T2_E~0); 15077#L377-1 assume !(1 == ~E_1~0); 14924#L382-1 assume !(1 == ~E_2~0); 14925#L387-1 assume { :end_inline_reset_delta_events } true; 15014#L528-2 [2021-12-16 10:05:38,641 INFO L793 eck$LassoCheckResult]: Loop: 15014#L528-2 assume !false; 15356#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 15351#L309 assume !false; 15350#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 15349#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 15348#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 15347#L262 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 15346#L276 assume 0 != eval_~tmp~0#1; 15345#L276-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 15343#L284 assume 0 != eval_~tmp_ndt_1~0#1;~m_st~0 := 1;assume { :begin_inline_master } true; 15341#L47 assume 0 == ~m_pc~0; 15183#L74 assume !false; 15340#L59 ~E_1~0 := 1;assume { :begin_inline_immediate_notify } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15152#L156-3 assume !(1 == ~m_pc~0); 15153#L156-5 is_master_triggered_~__retres1~0#1 := 0; 15146#L167-1 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 15147#L168-1 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 15027#L405-3 assume !(0 != activate_threads_~tmp~1#1); 15028#L405-5 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15114#L175-3 assume 1 == ~t1_pc~0; 15115#L176-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 15169#L186-1 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15170#L187-1 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 15164#L413-3 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 15035#L413-5 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14960#L194-3 assume !(1 == ~t2_pc~0); 14961#L194-5 is_transmit2_triggered_~__retres1~2#1 := 0; 15117#L205-1 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 15118#L206-1 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 15120#L421-3 assume !(0 != activate_threads_~tmp___1~0#1); 15121#L421-5 assume { :end_inline_activate_threads } true; 15135#L438 assume { :end_inline_immediate_notify } true;~E_1~0 := 2; 15136#L51 assume !false; 15141#L67 ~m_pc~0 := 1;~m_st~0 := 2; 15150#L77 assume { :end_inline_master } true; 15242#L281 assume !(0 == ~t1_st~0); 15284#L295 assume !(0 == ~t2_st~0); 15282#L309 assume !false; 15281#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 15218#L244 assume !(0 == ~m_st~0); 15217#L248 assume !(0 == ~t1_st~0); 15215#L252 assume !(0 == ~t2_st~0);exists_runnable_thread_~__retres1~3#1 := 0; 15214#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 15213#L262 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 15211#L276 assume !(0 != eval_~tmp~0#1); 15210#L324 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 15209#L214-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 15208#L334-3 assume !(0 == ~M_E~0); 15207#L334-5 assume !(0 == ~T1_E~0); 15206#L339-3 assume !(0 == ~T2_E~0); 15180#L344-3 assume !(0 == ~E_1~0); 15181#L349-3 assume 0 == ~E_2~0;~E_2~0 := 1; 15165#L354-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15166#L156-9 assume 1 == ~m_pc~0; 15063#L157-3 assume !(1 == ~M_E~0); 15064#L156-11 is_master_triggered_~__retres1~0#1 := 0; 15626#L167-3 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 15625#L168-3 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 15624#L405-9 assume !(0 != activate_threads_~tmp~1#1); 15623#L405-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15621#L175-9 assume !(1 == ~t1_pc~0); 15620#L175-11 is_transmit1_triggered_~__retres1~1#1 := 0; 15619#L186-3 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15618#L187-3 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 15617#L413-9 assume !(0 != activate_threads_~tmp___0~0#1); 15616#L413-11 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15615#L194-9 assume 1 == ~t2_pc~0; 15613#L195-3 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 15611#L205-3 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 15609#L206-3 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 15607#L421-9 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 15585#L421-11 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15582#L367-3 assume !(1 == ~M_E~0); 15578#L367-5 assume !(1 == ~T1_E~0); 15576#L372-3 assume !(1 == ~T2_E~0); 15574#L377-3 assume !(1 == ~E_1~0); 15554#L382-3 assume 1 == ~E_2~0;~E_2~0 := 2; 15552#L387-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 15549#L244-1 assume !(0 == ~m_st~0); 15464#L248-1 assume 0 == ~t1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 15545#L261-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 15543#L262-1 start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 15541#L547 assume 0 == start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 4;assume { :begin_inline_fire_time_events } true;~M_E~0 := 1; 15505#L447 assume { :end_inline_fire_time_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15158#L156-12 assume 1 == ~m_pc~0; 15159#L157-4 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 15197#L167-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 15198#L168-4 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 15192#L405-12 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 15193#L405-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15500#L175-12 assume !(1 == ~t1_pc~0); 15498#L175-14 is_transmit1_triggered_~__retres1~1#1 := 0; 15497#L186-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15496#L187-4 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 15495#L413-12 assume !(0 != activate_threads_~tmp___0~0#1); 15494#L413-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15493#L194-12 assume !(1 == ~t2_pc~0); 15491#L194-14 is_transmit2_triggered_~__retres1~2#1 := 0; 15489#L205-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 15487#L206-4 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 15485#L421-12 assume !(0 != activate_threads_~tmp___1~0#1); 15480#L421-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_time_events } true; 15474#L454 assume !(1 == ~M_E~0); 15475#L454-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 15648#L459-1 assume !(1 == ~T2_E~0); 15515#L464-1 assume !(1 == ~E_1~0); 15513#L469-1 assume !(1 == ~E_2~0); 15510#L474-1 assume { :end_inline_reset_time_events } true; 15177#L547-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 15482#L244-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 15477#L261-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 15473#L262-2 stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1; 15470#L502 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 15461#L509 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 15435#L510 start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 15431#L560 assume !(0 != start_simulation_~tmp___0~1#1); 15421#L528-2 assume !false; 15415#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 15408#L309 assume !false; 15405#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 15401#L244 assume !(0 == ~m_st~0); 15402#L248 assume !(0 == ~t1_st~0); 15650#L252 assume !(0 == ~t2_st~0);exists_runnable_thread_~__retres1~3#1 := 0; 15649#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 15300#L262 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 15295#L276 assume !(0 != eval_~tmp~0#1); 15293#L324 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 15291#L214-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 15290#L334-3 assume 0 == ~M_E~0;~M_E~0 := 1; 15289#L334-5 assume !(0 == ~T1_E~0); 15201#L339-3 assume !(0 == ~T2_E~0); 15202#L344-3 assume !(0 == ~E_1~0); 15178#L349-3 assume 0 == ~E_2~0;~E_2~0 := 1; 15179#L354-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15162#L156-9 assume 1 == ~m_pc~0; 15163#L157-3 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 15203#L167-3 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 15535#L168-3 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 15533#L405-9 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 15532#L405-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15530#L175-9 assume !(1 == ~t1_pc~0); 15529#L175-11 is_transmit1_triggered_~__retres1~1#1 := 0; 15528#L186-3 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15527#L187-3 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 15526#L413-9 assume !(0 != activate_threads_~tmp___0~0#1); 15525#L413-11 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15524#L194-9 assume 1 == ~t2_pc~0; 15522#L195-3 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 15520#L205-3 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 15518#L206-3 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 15516#L421-9 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 15514#L421-11 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15511#L367-3 assume 1 == ~M_E~0;~M_E~0 := 2; 15509#L367-5 assume !(1 == ~T1_E~0); 15508#L372-3 assume !(1 == ~T2_E~0); 15481#L377-3 assume !(1 == ~E_1~0); 15476#L382-3 assume 1 == ~E_2~0;~E_2~0 := 2; 15472#L387-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 15463#L244-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 15437#L261-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 15433#L262-1 start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 15423#L547 assume 0 == start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 4;assume { :begin_inline_fire_time_events } true;~M_E~0 := 1; 15160#L447 assume { :end_inline_fire_time_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15161#L156-12 assume !(1 == ~m_pc~0); 14901#L156-14 is_master_triggered_~__retres1~0#1 := 0; 14902#L167-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 15021#L168-4 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 15128#L405-12 assume !(0 != activate_threads_~tmp~1#1); 15149#L405-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14903#L175-12 assume !(1 == ~t1_pc~0); 14905#L175-14 is_transmit1_triggered_~__retres1~1#1 := 0; 15031#L186-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15080#L187-4 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 15133#L413-12 assume !(0 != activate_threads_~tmp___0~0#1); 15032#L413-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15024#L194-12 assume !(1 == ~t2_pc~0); 15025#L194-14 is_transmit2_triggered_~__retres1~2#1 := 0; 15636#L205-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 15635#L206-4 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 15628#L421-12 assume !(0 != activate_threads_~tmp___1~0#1); 15627#L421-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_time_events } true; 15586#L454 assume 1 == ~M_E~0;~M_E~0 := 2; 15583#L454-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 15579#L459-1 assume !(1 == ~T2_E~0); 15577#L464-1 assume !(1 == ~E_1~0); 15575#L469-1 assume !(1 == ~E_2~0); 15375#L474-1 assume { :end_inline_reset_time_events } true; 15373#L547-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 15371#L244-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 15370#L261-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 15366#L262-2 stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1; 15364#L502 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 15362#L509 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 15361#L510 start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 15360#L560 assume !(0 != start_simulation_~tmp___0~1#1); 15014#L528-2 [2021-12-16 10:05:38,642 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:38,642 INFO L85 PathProgramCache]: Analyzing trace with hash -148511807, now seen corresponding path program 8 times [2021-12-16 10:05:38,642 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:38,642 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [634350665] [2021-12-16 10:05:38,642 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:38,642 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:38,646 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:05:38,646 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-16 10:05:38,648 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:05:38,651 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-16 10:05:38,651 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:38,651 INFO L85 PathProgramCache]: Analyzing trace with hash -1851461154, now seen corresponding path program 1 times [2021-12-16 10:05:38,651 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:38,651 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [770771700] [2021-12-16 10:05:38,651 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:38,651 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:38,657 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:38,669 INFO L134 CoverageAnalysis]: Checked inductivity of 90 backedges. 14 proven. 0 refuted. 0 times theorem prover too weak. 76 trivial. 0 not checked. [2021-12-16 10:05:38,670 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:38,670 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [770771700] [2021-12-16 10:05:38,670 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [770771700] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:38,670 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:38,670 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:05:38,670 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [692436654] [2021-12-16 10:05:38,670 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:38,671 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:05:38,671 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:05:38,671 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-16 10:05:38,671 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-16 10:05:38,671 INFO L87 Difference]: Start difference. First operand 965 states and 1234 transitions. cyclomatic complexity: 271 Second operand has 3 states, 3 states have (on average 42.333333333333336) internal successors, (127), 3 states have internal predecessors, (127), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:38,688 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:05:38,688 INFO L93 Difference]: Finished difference Result 1383 states and 1755 transitions. [2021-12-16 10:05:38,688 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-16 10:05:38,689 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1383 states and 1755 transitions. [2021-12-16 10:05:38,694 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1301 [2021-12-16 10:05:38,698 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1383 states to 1383 states and 1755 transitions. [2021-12-16 10:05:38,698 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1383 [2021-12-16 10:05:38,699 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1383 [2021-12-16 10:05:38,699 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1383 states and 1755 transitions. [2021-12-16 10:05:38,700 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:05:38,700 INFO L681 BuchiCegarLoop]: Abstraction has 1383 states and 1755 transitions. [2021-12-16 10:05:38,701 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1383 states and 1755 transitions. [2021-12-16 10:05:38,710 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1383 to 1383. [2021-12-16 10:05:38,711 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1383 states, 1383 states have (on average 1.2689804772234274) internal successors, (1755), 1382 states have internal predecessors, (1755), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:38,713 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1383 states to 1383 states and 1755 transitions. [2021-12-16 10:05:38,713 INFO L704 BuchiCegarLoop]: Abstraction has 1383 states and 1755 transitions. [2021-12-16 10:05:38,713 INFO L587 BuchiCegarLoop]: Abstraction has 1383 states and 1755 transitions. [2021-12-16 10:05:38,713 INFO L425 BuchiCegarLoop]: ======== Iteration 16============ [2021-12-16 10:05:38,713 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1383 states and 1755 transitions. [2021-12-16 10:05:38,717 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1301 [2021-12-16 10:05:38,717 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:05:38,717 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:05:38,718 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:38,718 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:38,719 INFO L791 eck$LassoCheckResult]: Stem: 17495#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 17458#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 17244#L491 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 17245#L214 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 17481#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 17336#L221-2 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 17337#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 18108#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 18107#L334 assume !(0 == ~M_E~0); 18106#L334-2 assume !(0 == ~T1_E~0); 18105#L339-1 assume !(0 == ~T2_E~0); 18104#L344-1 assume !(0 == ~E_1~0); 18103#L349-1 assume !(0 == ~E_2~0); 18102#L354-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 18101#L156 assume !(1 == ~m_pc~0); 18100#L156-2 is_master_triggered_~__retres1~0#1 := 0; 18099#L167 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 18098#L168 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 18097#L405 assume !(0 != activate_threads_~tmp~1#1); 18096#L405-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 18095#L175 assume !(1 == ~t1_pc~0); 18093#L175-2 is_transmit1_triggered_~__retres1~1#1 := 0; 18092#L186 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18091#L187 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 18090#L413 assume !(0 != activate_threads_~tmp___0~0#1); 18089#L413-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18088#L194 assume !(1 == ~t2_pc~0); 18087#L194-2 is_transmit2_triggered_~__retres1~2#1 := 0; 17505#L205 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17504#L206 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 17285#L421 assume !(0 != activate_threads_~tmp___1~0#1); 17286#L421-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17260#L367 assume !(1 == ~M_E~0); 17261#L367-2 assume !(1 == ~T1_E~0); 17430#L372-1 assume !(1 == ~T2_E~0); 17431#L377-1 assume !(1 == ~E_1~0); 17279#L382-1 assume !(1 == ~E_2~0); 17280#L387-1 assume { :end_inline_reset_delta_events } true; 18003#L528-2 [2021-12-16 10:05:38,719 INFO L793 eck$LassoCheckResult]: Loop: 18003#L528-2 assume !false; 17588#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 17548#L309 assume !false; 17549#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 17578#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 17912#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 17903#L262 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 17896#L276 assume 0 != eval_~tmp~0#1; 17890#L276-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 17883#L284 assume 0 != eval_~tmp_ndt_1~0#1;~m_st~0 := 1;assume { :begin_inline_master } true; 17884#L47 assume 0 == ~m_pc~0; 18323#L74 assume !false; 18394#L59 ~E_1~0 := 1;assume { :begin_inline_immediate_notify } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 18392#L156-3 assume !(1 == ~m_pc~0); 18387#L156-5 is_master_triggered_~__retres1~0#1 := 0; 18385#L167-1 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 18384#L168-1 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 18383#L405-3 assume !(0 != activate_threads_~tmp~1#1); 18380#L405-5 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 18378#L175-3 assume !(1 == ~t1_pc~0); 17490#L175-5 is_transmit1_triggered_~__retres1~1#1 := 0; 17443#L186-1 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17444#L187-1 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 17391#L413-3 assume !(0 != activate_threads_~tmp___0~0#1); 17341#L413-5 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 17342#L194-3 assume !(1 == ~t2_pc~0); 18338#L194-5 is_transmit2_triggered_~__retres1~2#1 := 0; 18337#L205-1 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 18332#L206-1 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 18330#L421-3 assume !(0 != activate_threads_~tmp___1~0#1); 18327#L421-5 assume { :end_inline_activate_threads } true; 18321#L438 assume { :end_inline_immediate_notify } true;~E_1~0 := 2; 18319#L51 assume !false; 18317#L67 ~m_pc~0 := 1;~m_st~0 := 2; 17477#L77 assume { :end_inline_master } true; 17457#L281 assume !(0 == ~t1_st~0); 17468#L295 assume !(0 == ~t2_st~0); 17557#L309 assume !false; 17543#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 17544#L244 assume !(0 == ~m_st~0); 17534#L248 assume !(0 == ~t1_st~0); 17535#L252 assume !(0 == ~t2_st~0);exists_runnable_thread_~__retres1~3#1 := 0; 17567#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 17568#L262 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 17562#L276 assume !(0 != eval_~tmp~0#1); 17563#L324 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 17516#L214-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 17517#L334-3 assume !(0 == ~M_E~0); 17570#L334-5 assume !(0 == ~T1_E~0); 17775#L339-3 assume !(0 == ~T2_E~0); 17770#L344-3 assume !(0 == ~E_1~0); 17768#L349-3 assume 0 == ~E_2~0;~E_2~0 := 1; 17766#L354-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17506#L156-9 assume 1 == ~m_pc~0; 17418#L157-3 assume !(1 == ~M_E~0); 17419#L156-11 is_master_triggered_~__retres1~0#1 := 0; 18173#L167-3 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 18172#L168-3 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 18171#L405-9 assume !(0 != activate_threads_~tmp~1#1); 18169#L405-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 18165#L175-9 assume !(1 == ~t1_pc~0); 18164#L175-11 is_transmit1_triggered_~__retres1~1#1 := 0; 18163#L186-3 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18162#L187-3 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 18159#L413-9 assume !(0 != activate_threads_~tmp___0~0#1); 18156#L413-11 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 17488#L194-9 assume !(1 == ~t2_pc~0); 17289#L194-11 is_transmit2_triggered_~__retres1~2#1 := 0; 17290#L205-3 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17373#L206-3 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 17374#L421-9 assume !(0 != activate_threads_~tmp___1~0#1); 17404#L421-11 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17330#L367-3 assume !(1 == ~M_E~0); 17251#L367-5 assume !(1 == ~T1_E~0); 17252#L372-3 assume !(1 == ~T2_E~0); 17268#L377-3 assume !(1 == ~E_1~0); 17269#L382-3 assume 1 == ~E_2~0;~E_2~0 := 2; 17291#L387-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 17405#L244-1 assume !(0 == ~m_st~0); 17445#L248-1 assume !(0 == ~t1_st~0); 17298#L252-1 assume 0 == ~t2_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 17299#L261-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 17479#L262-1 start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 17512#L547 assume 0 == start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 4;assume { :begin_inline_fire_time_events } true;~M_E~0 := 1; 17511#L447 assume { :end_inline_fire_time_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17508#L156-12 assume 1 == ~m_pc~0; 17509#L157-4 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 17739#L167-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 17887#L168-4 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 17713#L405-12 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 17708#L405-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17703#L175-12 assume !(1 == ~t1_pc~0); 17697#L175-14 is_transmit1_triggered_~__retres1~1#1 := 0; 17692#L186-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17686#L187-4 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 17681#L413-12 assume !(0 != activate_threads_~tmp___0~0#1); 17676#L413-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 17670#L194-12 assume 1 == ~t2_pc~0; 17665#L195-4 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 17660#L205-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17655#L206-4 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 17651#L421-12 assume !(0 != activate_threads_~tmp___1~0#1); 17645#L421-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_time_events } true; 17640#L454 assume !(1 == ~M_E~0); 17636#L454-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 17631#L459-1 assume !(1 == ~T2_E~0); 17627#L464-1 assume !(1 == ~E_1~0); 17623#L469-1 assume !(1 == ~E_2~0); 17619#L474-1 assume { :end_inline_reset_time_events } true; 17617#L547-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 17614#L244-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 17610#L261-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 17608#L262-2 stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1; 17607#L502 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 17605#L509 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 17606#L510 start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 18231#L560 assume !(0 != start_simulation_~tmp___0~1#1); 18229#L528-2 assume !false; 18227#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 18221#L309 assume !false; 18219#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 18217#L244 assume !(0 == ~m_st~0); 17530#L248 assume !(0 == ~t1_st~0); 17531#L252 assume !(0 == ~t2_st~0);exists_runnable_thread_~__retres1~3#1 := 0; 17525#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 17526#L262 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 17520#L276 assume !(0 != eval_~tmp~0#1); 17522#L324 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 17366#L214-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 17367#L334-3 assume 0 == ~M_E~0;~M_E~0 := 1; 17459#L334-5 assume !(0 == ~T1_E~0); 17460#L339-3 assume !(0 == ~T2_E~0); 17566#L344-3 assume !(0 == ~E_1~0); 17363#L349-3 assume 0 == ~E_2~0;~E_2~0 := 1; 17294#L354-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17295#L156-9 assume 1 == ~m_pc~0; 17759#L157-3 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 17756#L167-3 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 17753#L168-3 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 17744#L405-9 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 17732#L405-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17726#L175-9 assume !(1 == ~t1_pc~0); 17721#L175-11 is_transmit1_triggered_~__retres1~1#1 := 0; 17717#L186-3 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17709#L187-3 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 17704#L413-9 assume !(0 != activate_threads_~tmp___0~0#1); 17698#L413-11 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 17693#L194-9 assume 1 == ~t2_pc~0; 17687#L195-3 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 17682#L205-3 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17677#L206-3 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 17671#L421-9 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 17667#L421-11 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17661#L367-3 assume !(1 == ~M_E~0); 17656#L367-5 assume !(1 == ~T1_E~0); 17652#L372-3 assume !(1 == ~T2_E~0); 17646#L377-3 assume !(1 == ~E_1~0); 17642#L382-3 assume 1 == ~E_2~0;~E_2~0 := 2; 17637#L387-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 17632#L244-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 17628#L261-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 17624#L262-1 start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 17620#L547 assume 0 == start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 4;assume { :begin_inline_fire_time_events } true;~M_E~0 := 1; 17621#L447 assume { :end_inline_fire_time_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17737#L156-12 assume !(1 == ~m_pc~0); 17738#L156-14 is_master_triggered_~__retres1~0#1 := 0; 17956#L167-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 17954#L168-4 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 17952#L405-12 assume !(0 != activate_threads_~tmp~1#1); 17950#L405-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17948#L175-12 assume !(1 == ~t1_pc~0); 17944#L175-14 is_transmit1_triggered_~__retres1~1#1 := 0; 17942#L186-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17940#L187-4 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 17936#L413-12 assume !(0 != activate_threads_~tmp___0~0#1); 17934#L413-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 17932#L194-12 assume !(1 == ~t2_pc~0); 17929#L194-14 is_transmit2_triggered_~__retres1~2#1 := 0; 17927#L205-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17925#L206-4 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 17914#L421-12 assume !(0 != activate_threads_~tmp___1~0#1); 17905#L421-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_time_events } true; 17898#L454 assume 1 == ~M_E~0;~M_E~0 := 2; 17899#L454-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 18161#L459-1 assume !(1 == ~T2_E~0); 18158#L464-1 assume !(1 == ~E_1~0); 18154#L469-1 assume !(1 == ~E_2~0); 18056#L474-1 assume { :end_inline_reset_time_events } true; 18055#L547-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 18048#L244-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 18044#L261-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 18040#L262-2 stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1; 18036#L502 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 18031#L509 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 18028#L510 start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 18008#L560 assume !(0 != start_simulation_~tmp___0~1#1); 18003#L528-2 [2021-12-16 10:05:38,719 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:38,719 INFO L85 PathProgramCache]: Analyzing trace with hash -220898365, now seen corresponding path program 1 times [2021-12-16 10:05:38,720 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:38,720 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1360565829] [2021-12-16 10:05:38,720 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:38,720 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:38,723 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:38,729 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:05:38,729 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:38,729 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1360565829] [2021-12-16 10:05:38,729 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1360565829] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:38,730 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:38,730 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:05:38,730 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1212768548] [2021-12-16 10:05:38,730 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:38,730 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:05:38,730 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:38,730 INFO L85 PathProgramCache]: Analyzing trace with hash 469176911, now seen corresponding path program 1 times [2021-12-16 10:05:38,731 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:38,731 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [444132266] [2021-12-16 10:05:38,731 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:38,731 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:38,737 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:38,751 INFO L134 CoverageAnalysis]: Checked inductivity of 88 backedges. 54 proven. 0 refuted. 0 times theorem prover too weak. 34 trivial. 0 not checked. [2021-12-16 10:05:38,751 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:38,751 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [444132266] [2021-12-16 10:05:38,751 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [444132266] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:38,751 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:38,752 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:05:38,752 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1719570893] [2021-12-16 10:05:38,752 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:38,752 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:05:38,752 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:05:38,752 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-16 10:05:38,753 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-16 10:05:38,753 INFO L87 Difference]: Start difference. First operand 1383 states and 1755 transitions. cyclomatic complexity: 374 Second operand has 3 states, 3 states have (on average 12.666666666666666) internal successors, (38), 3 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:38,759 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:05:38,759 INFO L93 Difference]: Finished difference Result 1346 states and 1710 transitions. [2021-12-16 10:05:38,759 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-16 10:05:38,760 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1346 states and 1710 transitions. [2021-12-16 10:05:38,764 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1301 [2021-12-16 10:05:38,767 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1346 states to 1346 states and 1710 transitions. [2021-12-16 10:05:38,792 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1346 [2021-12-16 10:05:38,793 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1346 [2021-12-16 10:05:38,793 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1346 states and 1710 transitions. [2021-12-16 10:05:38,794 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:05:38,794 INFO L681 BuchiCegarLoop]: Abstraction has 1346 states and 1710 transitions. [2021-12-16 10:05:38,794 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1346 states and 1710 transitions. [2021-12-16 10:05:38,803 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1346 to 1346. [2021-12-16 10:05:38,805 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1346 states, 1346 states have (on average 1.2704309063893016) internal successors, (1710), 1345 states have internal predecessors, (1710), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:38,807 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1346 states to 1346 states and 1710 transitions. [2021-12-16 10:05:38,807 INFO L704 BuchiCegarLoop]: Abstraction has 1346 states and 1710 transitions. [2021-12-16 10:05:38,807 INFO L587 BuchiCegarLoop]: Abstraction has 1346 states and 1710 transitions. [2021-12-16 10:05:38,807 INFO L425 BuchiCegarLoop]: ======== Iteration 17============ [2021-12-16 10:05:38,807 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1346 states and 1710 transitions. [2021-12-16 10:05:38,810 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1301 [2021-12-16 10:05:38,810 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:05:38,810 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:05:38,810 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:38,810 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:38,810 INFO L791 eck$LassoCheckResult]: Stem: 20207#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 20180#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 19980#L491 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 19981#L214 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 20197#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 20071#L221-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 20043#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 20044#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 20030#L334 assume !(0 == ~M_E~0); 20031#L334-2 assume !(0 == ~T1_E~0); 20133#L339-1 assume !(0 == ~T2_E~0); 20125#L344-1 assume !(0 == ~E_1~0); 20126#L349-1 assume !(0 == ~E_2~0); 20041#L354-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20042#L156 assume !(1 == ~m_pc~0); 20140#L156-2 is_master_triggered_~__retres1~0#1 := 0; 20164#L167 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 20152#L168 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 20096#L405 assume !(0 != activate_threads_~tmp~1#1); 20076#L405-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 20077#L175 assume !(1 == ~t1_pc~0); 20084#L175-2 is_transmit1_triggered_~__retres1~1#1 := 0; 20078#L186 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 20079#L187 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 20135#L413 assume !(0 != activate_threads_~tmp___0~0#1); 20136#L413-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 20200#L194 assume !(1 == ~t2_pc~0); 20124#L194-2 is_transmit2_triggered_~__retres1~2#1 := 0; 20208#L205 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20214#L206 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 20019#L421 assume !(0 != activate_threads_~tmp___1~0#1); 20020#L421-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19996#L367 assume !(1 == ~M_E~0); 19997#L367-2 assume !(1 == ~T1_E~0); 20156#L372-1 assume !(1 == ~T2_E~0); 20157#L377-1 assume !(1 == ~E_1~0); 20014#L382-1 assume !(1 == ~E_2~0); 20015#L387-1 assume { :end_inline_reset_delta_events } true; 20099#L528-2 assume !false; 21262#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 21258#L309 [2021-12-16 10:05:38,811 INFO L793 eck$LassoCheckResult]: Loop: 21258#L309 assume !false; 21257#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 20933#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 20930#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 20928#L262 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 20926#L276 assume 0 != eval_~tmp~0#1; 20924#L276-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 20922#L284 assume !(0 != eval_~tmp_ndt_1~0#1); 20920#L281 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 20904#L298 assume !(0 != eval_~tmp_ndt_2~0#1); 20918#L295 assume !(0 == ~t2_st~0); 21258#L309 [2021-12-16 10:05:38,811 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:38,811 INFO L85 PathProgramCache]: Analyzing trace with hash -985920349, now seen corresponding path program 1 times [2021-12-16 10:05:38,811 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:38,811 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1847390958] [2021-12-16 10:05:38,811 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:38,811 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:38,815 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:05:38,815 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-16 10:05:38,817 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:05:38,819 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-16 10:05:38,819 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:38,819 INFO L85 PathProgramCache]: Analyzing trace with hash 993952052, now seen corresponding path program 1 times [2021-12-16 10:05:38,820 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:38,820 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1194137496] [2021-12-16 10:05:38,820 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:38,820 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:38,821 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:05:38,822 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-16 10:05:38,822 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:05:38,823 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-16 10:05:38,823 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:38,824 INFO L85 PathProgramCache]: Analyzing trace with hash 1252891474, now seen corresponding path program 1 times [2021-12-16 10:05:38,824 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:38,824 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2097425302] [2021-12-16 10:05:38,824 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:38,824 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:38,827 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:38,835 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:05:38,835 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:38,835 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2097425302] [2021-12-16 10:05:38,835 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2097425302] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:38,835 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:38,835 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-16 10:05:38,835 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [622943016] [2021-12-16 10:05:38,836 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:38,892 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:05:38,893 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-16 10:05:38,893 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-16 10:05:38,893 INFO L87 Difference]: Start difference. First operand 1346 states and 1710 transitions. cyclomatic complexity: 366 Second operand has 3 states, 2 states have (on average 25.5) internal successors, (51), 3 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:38,920 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:05:38,920 INFO L93 Difference]: Finished difference Result 2385 states and 3012 transitions. [2021-12-16 10:05:38,920 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-16 10:05:38,921 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2385 states and 3012 transitions. [2021-12-16 10:05:38,928 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2340 [2021-12-16 10:05:38,934 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2385 states to 2385 states and 3012 transitions. [2021-12-16 10:05:38,935 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2385 [2021-12-16 10:05:38,936 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2385 [2021-12-16 10:05:38,936 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2385 states and 3012 transitions. [2021-12-16 10:05:38,938 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:05:38,938 INFO L681 BuchiCegarLoop]: Abstraction has 2385 states and 3012 transitions. [2021-12-16 10:05:38,939 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2385 states and 3012 transitions. [2021-12-16 10:05:38,955 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2385 to 2385. [2021-12-16 10:05:38,958 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2385 states, 2385 states have (on average 1.2628930817610062) internal successors, (3012), 2384 states have internal predecessors, (3012), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:38,961 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2385 states to 2385 states and 3012 transitions. [2021-12-16 10:05:38,962 INFO L704 BuchiCegarLoop]: Abstraction has 2385 states and 3012 transitions. [2021-12-16 10:05:38,962 INFO L587 BuchiCegarLoop]: Abstraction has 2385 states and 3012 transitions. [2021-12-16 10:05:38,962 INFO L425 BuchiCegarLoop]: ======== Iteration 18============ [2021-12-16 10:05:38,962 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2385 states and 3012 transitions. [2021-12-16 10:05:38,966 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2340 [2021-12-16 10:05:38,967 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:05:38,967 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:05:38,967 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:38,967 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:38,967 INFO L791 eck$LassoCheckResult]: Stem: 23958#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 23927#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 23719#L491 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 23720#L214 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 23944#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 23812#L221-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 23783#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 23784#L231-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 23770#L334 assume !(0 == ~M_E~0); 23771#L334-2 assume !(0 == ~T1_E~0); 23878#L339-1 assume !(0 == ~T2_E~0); 23871#L344-1 assume !(0 == ~E_1~0); 23872#L349-1 assume !(0 == ~E_2~0); 23781#L354-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 23782#L156 assume !(1 == ~m_pc~0); 23885#L156-2 is_master_triggered_~__retres1~0#1 := 0; 23908#L167 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 23897#L168 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 23838#L405 assume !(0 != activate_threads_~tmp~1#1); 23817#L405-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 23818#L175 assume !(1 == ~t1_pc~0); 23825#L175-2 is_transmit1_triggered_~__retres1~1#1 := 0; 23819#L186 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 23820#L187 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 23880#L413 assume !(0 != activate_threads_~tmp___0~0#1); 23881#L413-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 23947#L194 assume !(1 == ~t2_pc~0); 23869#L194-2 is_transmit2_triggered_~__retres1~2#1 := 0; 23959#L205 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 23965#L206 activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 23759#L421 assume !(0 != activate_threads_~tmp___1~0#1); 23760#L421-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 23735#L367 assume !(1 == ~M_E~0); 23736#L367-2 assume !(1 == ~T1_E~0); 23902#L372-1 assume !(1 == ~T2_E~0); 23903#L377-1 assume !(1 == ~E_1~0); 23754#L382-1 assume !(1 == ~E_2~0); 23755#L387-1 assume { :end_inline_reset_delta_events } true; 23841#L528-2 assume !false; 25062#L529 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 24518#L309 [2021-12-16 10:05:38,967 INFO L793 eck$LassoCheckResult]: Loop: 24518#L309 assume !false; 25060#L272 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 25056#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 25054#L261 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 25053#L262 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 25052#L276 assume 0 != eval_~tmp~0#1; 25050#L276-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 24947#L284 assume !(0 != eval_~tmp_ndt_1~0#1); 24526#L281 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 24523#L298 assume !(0 != eval_~tmp_ndt_2~0#1); 24520#L295 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 24506#L312 assume !(0 != eval_~tmp_ndt_3~0#1); 24518#L309 [2021-12-16 10:05:38,968 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:38,968 INFO L85 PathProgramCache]: Analyzing trace with hash -985920349, now seen corresponding path program 2 times [2021-12-16 10:05:38,968 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:38,968 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2141219895] [2021-12-16 10:05:38,968 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:38,968 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:38,972 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:05:38,972 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-16 10:05:38,974 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:05:38,976 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-16 10:05:38,976 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:38,976 INFO L85 PathProgramCache]: Analyzing trace with hash 747741784, now seen corresponding path program 1 times [2021-12-16 10:05:38,977 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:38,977 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1203023652] [2021-12-16 10:05:38,977 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:38,977 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:38,979 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:05:38,979 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-16 10:05:38,980 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:05:38,981 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-16 10:05:38,982 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:38,982 INFO L85 PathProgramCache]: Analyzing trace with hash 184929274, now seen corresponding path program 1 times [2021-12-16 10:05:38,982 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:38,982 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [584198825] [2021-12-16 10:05:38,982 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:38,982 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:38,986 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:05:38,986 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-16 10:05:38,989 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:05:38,992 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-16 10:05:39,624 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 16.12 10:05:39 BoogieIcfgContainer [2021-12-16 10:05:39,624 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2021-12-16 10:05:39,625 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2021-12-16 10:05:39,625 INFO L271 PluginConnector]: Initializing Witness Printer... [2021-12-16 10:05:39,625 INFO L275 PluginConnector]: Witness Printer initialized [2021-12-16 10:05:39,625 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 16.12 10:05:36" (3/4) ... [2021-12-16 10:05:39,627 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2021-12-16 10:05:39,660 INFO L141 WitnessManager]: Wrote witness to /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/witness.graphml [2021-12-16 10:05:39,660 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2021-12-16 10:05:39,661 INFO L158 Benchmark]: Toolchain (without parser) took 3819.44ms. Allocated memory was 132.1MB in the beginning and 237.0MB in the end (delta: 104.9MB). Free memory was 103.5MB in the beginning and 171.1MB in the end (delta: -67.6MB). Peak memory consumption was 37.0MB. Max. memory is 16.1GB. [2021-12-16 10:05:39,661 INFO L158 Benchmark]: CDTParser took 0.16ms. Allocated memory is still 90.2MB. Free memory is still 48.7MB. There was no memory consumed. Max. memory is 16.1GB. [2021-12-16 10:05:39,661 INFO L158 Benchmark]: CACSL2BoogieTranslator took 247.70ms. Allocated memory is still 132.1MB. Free memory was 103.5MB in the beginning and 106.4MB in the end (delta: -2.9MB). Peak memory consumption was 10.5MB. Max. memory is 16.1GB. [2021-12-16 10:05:39,661 INFO L158 Benchmark]: Boogie Procedure Inliner took 63.42ms. Allocated memory is still 132.1MB. Free memory was 105.9MB in the beginning and 103.3MB in the end (delta: 2.5MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2021-12-16 10:05:39,662 INFO L158 Benchmark]: Boogie Preprocessor took 36.98ms. Allocated memory is still 132.1MB. Free memory was 103.3MB in the beginning and 101.3MB in the end (delta: 2.1MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2021-12-16 10:05:39,662 INFO L158 Benchmark]: RCFGBuilder took 459.22ms. Allocated memory is still 132.1MB. Free memory was 101.3MB in the beginning and 79.4MB in the end (delta: 21.9MB). Peak memory consumption was 21.0MB. Max. memory is 16.1GB. [2021-12-16 10:05:39,662 INFO L158 Benchmark]: BuchiAutomizer took 2957.98ms. Allocated memory was 132.1MB in the beginning and 237.0MB in the end (delta: 104.9MB). Free memory was 79.4MB in the beginning and 174.2MB in the end (delta: -94.9MB). Peak memory consumption was 77.9MB. Max. memory is 16.1GB. [2021-12-16 10:05:39,662 INFO L158 Benchmark]: Witness Printer took 35.77ms. Allocated memory is still 237.0MB. Free memory was 174.2MB in the beginning and 171.1MB in the end (delta: 3.1MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2021-12-16 10:05:39,663 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.16ms. Allocated memory is still 90.2MB. Free memory is still 48.7MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 247.70ms. Allocated memory is still 132.1MB. Free memory was 103.5MB in the beginning and 106.4MB in the end (delta: -2.9MB). Peak memory consumption was 10.5MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 63.42ms. Allocated memory is still 132.1MB. Free memory was 105.9MB in the beginning and 103.3MB in the end (delta: 2.5MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * Boogie Preprocessor took 36.98ms. Allocated memory is still 132.1MB. Free memory was 103.3MB in the beginning and 101.3MB in the end (delta: 2.1MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * RCFGBuilder took 459.22ms. Allocated memory is still 132.1MB. Free memory was 101.3MB in the beginning and 79.4MB in the end (delta: 21.9MB). Peak memory consumption was 21.0MB. Max. memory is 16.1GB. * BuchiAutomizer took 2957.98ms. Allocated memory was 132.1MB in the beginning and 237.0MB in the end (delta: 104.9MB). Free memory was 79.4MB in the beginning and 174.2MB in the end (delta: -94.9MB). Peak memory consumption was 77.9MB. Max. memory is 16.1GB. * Witness Printer took 35.77ms. Allocated memory is still 237.0MB. Free memory was 174.2MB in the beginning and 171.1MB in the end (delta: 3.1MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 17 terminating modules (17 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.17 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 2385 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 2.8s and 18 iterations. TraceHistogramMax:3. Analysis of lassos took 1.6s. Construction of modules took 0.2s. Büchi inclusion checks took 0.3s. Highest rank in rank-based complementation 0. Minimization of det autom 17. Minimization of nondet autom 0. Automata minimization 0.2s AutomataMinimizationTime, 17 MinimizatonAttempts, 2535 StatesRemovedByMinimization, 9 NontrivialMinimizations. Non-live state removal took 0.1s Buchi closure took 0.0s. Biggest automaton had 2385 states and ocurred in iteration 17. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 6122 SdHoareTripleChecker+Valid, 0.4s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 6122 mSDsluCounter, 10639 SdHoareTripleChecker+Invalid, 0.3s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 5367 mSDsCounter, 153 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 449 IncrementalHoareTripleChecker+Invalid, 602 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 153 mSolverCounterUnsat, 5272 mSDtfsCounter, 449 mSolverCounterSat, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI8 SFLT0 conc1 concLT0 SILN0 SILU0 SILI8 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - FixpointNonTerminationResult [Line: 271]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite execution State at position 0 is {NULL=1} State at position 1 is {tmp_ndt_3=0, NULL=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@79676552=0, NULL=1, \result=0, tmp=0, \result=0, __retres1=0, tmp___1=0, T2_E=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@6845beb5=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@34965ed6=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@69de851a=0, t2_st=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@e3919e7=0, tmp=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@2ad321ea=0, t1_pc=0, tmp_ndt_2=0, E_2=2, tmp___0=0, T1_E=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@79f6ae42=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@4639dee4=0, E_1=2, __retres1=0, M_E=2, __retres1=1, tmp_ndt_1=0, t2_i=1, tmp=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@235bf46b=0, \result=0, m_i=1, t1_st=0, __retres1=0, t2_pc=0, m_st=0, NULL=0, kernel_st=1, __retres1=0, tmp___0=0, t1_i=1, m_pc=0, \result=0, \result=1} - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 271]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L25] int m_pc = 0; [L26] int t1_pc = 0; [L27] int t2_pc = 0; [L28] int m_st ; [L29] int t1_st ; [L30] int t2_st ; [L31] int m_i ; [L32] int t1_i ; [L33] int t2_i ; [L34] int M_E = 2; [L35] int T1_E = 2; [L36] int T2_E = 2; [L37] int E_1 = 2; [L38] int E_2 = 2; [L573] int __retres1 ; [L577] CALL init_model() [L487] m_i = 1 [L488] t1_i = 1 [L489] t2_i = 1 [L577] RET init_model() [L578] CALL start_simulation() [L514] int kernel_st ; [L515] int tmp ; [L516] int tmp___0 ; [L520] kernel_st = 0 [L521] FCALL update_channels() [L522] CALL init_threads() [L221] COND TRUE m_i == 1 [L222] m_st = 0 [L226] COND TRUE t1_i == 1 [L227] t1_st = 0 [L231] COND TRUE t2_i == 1 [L232] t2_st = 0 [L522] RET init_threads() [L523] CALL fire_delta_events() [L334] COND FALSE !(M_E == 0) [L339] COND FALSE !(T1_E == 0) [L344] COND FALSE !(T2_E == 0) [L349] COND FALSE !(E_1 == 0) [L354] COND FALSE !(E_2 == 0) [L523] RET fire_delta_events() [L524] CALL activate_threads() [L397] int tmp ; [L398] int tmp___0 ; [L399] int tmp___1 ; [L403] CALL, EXPR is_master_triggered() [L153] int __retres1 ; [L156] COND FALSE !(m_pc == 1) [L166] __retres1 = 0 [L168] return (__retres1); [L403] RET, EXPR is_master_triggered() [L403] tmp = is_master_triggered() [L405] COND FALSE !(\read(tmp)) [L411] CALL, EXPR is_transmit1_triggered() [L172] int __retres1 ; [L175] COND FALSE !(t1_pc == 1) [L185] __retres1 = 0 [L187] return (__retres1); [L411] RET, EXPR is_transmit1_triggered() [L411] tmp___0 = is_transmit1_triggered() [L413] COND FALSE !(\read(tmp___0)) [L419] CALL, EXPR is_transmit2_triggered() [L191] int __retres1 ; [L194] COND FALSE !(t2_pc == 1) [L204] __retres1 = 0 [L206] return (__retres1); [L419] RET, EXPR is_transmit2_triggered() [L419] tmp___1 = is_transmit2_triggered() [L421] COND FALSE !(\read(tmp___1)) [L524] RET activate_threads() [L525] CALL reset_delta_events() [L367] COND FALSE !(M_E == 1) [L372] COND FALSE !(T1_E == 1) [L377] COND FALSE !(T2_E == 1) [L382] COND FALSE !(E_1 == 1) [L387] COND FALSE !(E_2 == 1) [L525] RET reset_delta_events() [L528] COND TRUE 1 [L531] kernel_st = 1 [L532] CALL eval() [L267] int tmp ; Loop: [L271] COND TRUE 1 [L274] CALL, EXPR exists_runnable_thread() [L241] int __retres1 ; [L244] COND TRUE m_st == 0 [L245] __retres1 = 1 [L262] return (__retres1); [L274] RET, EXPR exists_runnable_thread() [L274] tmp = exists_runnable_thread() [L276] COND TRUE \read(tmp) [L281] COND TRUE m_st == 0 [L282] int tmp_ndt_1; [L283] tmp_ndt_1 = __VERIFIER_nondet_int() [L284] COND FALSE !(\read(tmp_ndt_1)) [L295] COND TRUE t1_st == 0 [L296] int tmp_ndt_2; [L297] tmp_ndt_2 = __VERIFIER_nondet_int() [L298] COND FALSE !(\read(tmp_ndt_2)) [L309] COND TRUE t2_st == 0 [L310] int tmp_ndt_3; [L311] tmp_ndt_3 = __VERIFIER_nondet_int() [L312] COND FALSE !(\read(tmp_ndt_3)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2021-12-16 10:05:39,706 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)