./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/transmitter.05.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version c3fed411 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/transmitter.05.cil.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash d8722862ca37b1ee13dec8b9e420cd40ba7901837b8f3b6258499da6e8a2ca6f --- Real Ultimate output --- This is Ultimate 0.2.2-tmp.no-commuhash-c3fed41 [2021-12-16 10:05:42,769 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-12-16 10:05:42,770 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-12-16 10:05:42,805 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-12-16 10:05:42,805 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-12-16 10:05:42,806 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-12-16 10:05:42,807 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-12-16 10:05:42,808 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-12-16 10:05:42,809 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-12-16 10:05:42,809 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-12-16 10:05:42,810 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-12-16 10:05:42,811 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-12-16 10:05:42,811 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-12-16 10:05:42,812 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-12-16 10:05:42,812 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-12-16 10:05:42,813 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-12-16 10:05:42,814 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-12-16 10:05:42,814 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-12-16 10:05:42,816 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-12-16 10:05:42,817 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-12-16 10:05:42,818 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-12-16 10:05:42,819 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-12-16 10:05:42,820 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-12-16 10:05:42,820 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-12-16 10:05:42,822 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-12-16 10:05:42,823 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-12-16 10:05:42,823 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-12-16 10:05:42,823 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-12-16 10:05:42,824 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-12-16 10:05:42,824 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-12-16 10:05:42,825 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-12-16 10:05:42,825 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-12-16 10:05:42,826 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-12-16 10:05:42,826 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-12-16 10:05:42,827 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-12-16 10:05:42,827 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-12-16 10:05:42,828 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-12-16 10:05:42,828 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-12-16 10:05:42,828 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-12-16 10:05:42,829 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-12-16 10:05:42,829 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-12-16 10:05:42,831 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2021-12-16 10:05:42,846 INFO L113 SettingsManager]: Loading preferences was successful [2021-12-16 10:05:42,846 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-12-16 10:05:42,846 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2021-12-16 10:05:42,846 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2021-12-16 10:05:42,847 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-12-16 10:05:42,847 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-12-16 10:05:42,847 INFO L138 SettingsManager]: * Use SBE=true [2021-12-16 10:05:42,848 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2021-12-16 10:05:42,848 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2021-12-16 10:05:42,848 INFO L138 SettingsManager]: * Use old map elimination=false [2021-12-16 10:05:42,848 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2021-12-16 10:05:42,848 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2021-12-16 10:05:42,848 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2021-12-16 10:05:42,849 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-12-16 10:05:42,849 INFO L138 SettingsManager]: * sizeof long=4 [2021-12-16 10:05:42,849 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2021-12-16 10:05:42,849 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-12-16 10:05:42,849 INFO L138 SettingsManager]: * sizeof POINTER=4 [2021-12-16 10:05:42,849 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-12-16 10:05:42,849 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2021-12-16 10:05:42,850 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2021-12-16 10:05:42,850 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2021-12-16 10:05:42,850 INFO L138 SettingsManager]: * sizeof long double=12 [2021-12-16 10:05:42,850 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-12-16 10:05:42,850 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2021-12-16 10:05:42,850 INFO L138 SettingsManager]: * Use constant arrays=true [2021-12-16 10:05:42,851 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2021-12-16 10:05:42,851 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-12-16 10:05:42,851 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-12-16 10:05:42,851 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-12-16 10:05:42,851 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-12-16 10:05:42,851 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2021-12-16 10:05:42,852 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2021-12-16 10:05:42,852 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> d8722862ca37b1ee13dec8b9e420cd40ba7901837b8f3b6258499da6e8a2ca6f [2021-12-16 10:05:43,156 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-12-16 10:05:43,173 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-12-16 10:05:43,175 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-12-16 10:05:43,176 INFO L271 PluginConnector]: Initializing CDTParser... [2021-12-16 10:05:43,177 INFO L275 PluginConnector]: CDTParser initialized [2021-12-16 10:05:43,178 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/transmitter.05.cil.c [2021-12-16 10:05:43,239 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/476366207/af52628535764a10ab76ac5301aee0c4/FLAG3d6ad9419 [2021-12-16 10:05:43,636 INFO L306 CDTParser]: Found 1 translation units. [2021-12-16 10:05:43,637 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.05.cil.c [2021-12-16 10:05:43,654 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/476366207/af52628535764a10ab76ac5301aee0c4/FLAG3d6ad9419 [2021-12-16 10:05:43,666 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/476366207/af52628535764a10ab76ac5301aee0c4 [2021-12-16 10:05:43,669 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-12-16 10:05:43,670 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-12-16 10:05:43,674 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-12-16 10:05:43,674 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-12-16 10:05:43,676 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-12-16 10:05:43,677 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 16.12 10:05:43" (1/1) ... [2021-12-16 10:05:43,677 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@59371cda and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:05:43, skipping insertion in model container [2021-12-16 10:05:43,677 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 16.12 10:05:43" (1/1) ... [2021-12-16 10:05:43,682 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-12-16 10:05:43,720 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-12-16 10:05:43,872 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.05.cil.c[706,719] [2021-12-16 10:05:43,949 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-16 10:05:43,960 INFO L203 MainTranslator]: Completed pre-run [2021-12-16 10:05:43,970 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.05.cil.c[706,719] [2021-12-16 10:05:44,045 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-16 10:05:44,055 INFO L208 MainTranslator]: Completed translation [2021-12-16 10:05:44,060 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:05:44 WrapperNode [2021-12-16 10:05:44,063 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-12-16 10:05:44,065 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-12-16 10:05:44,065 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-12-16 10:05:44,065 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-12-16 10:05:44,074 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:05:44" (1/1) ... [2021-12-16 10:05:44,101 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:05:44" (1/1) ... [2021-12-16 10:05:44,166 INFO L137 Inliner]: procedures = 38, calls = 45, calls flagged for inlining = 40, calls inlined = 86, statements flattened = 1229 [2021-12-16 10:05:44,167 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-12-16 10:05:44,168 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-12-16 10:05:44,168 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-12-16 10:05:44,168 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-12-16 10:05:44,177 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:05:44" (1/1) ... [2021-12-16 10:05:44,186 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:05:44" (1/1) ... [2021-12-16 10:05:44,194 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:05:44" (1/1) ... [2021-12-16 10:05:44,195 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:05:44" (1/1) ... [2021-12-16 10:05:44,214 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:05:44" (1/1) ... [2021-12-16 10:05:44,271 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:05:44" (1/1) ... [2021-12-16 10:05:44,285 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:05:44" (1/1) ... [2021-12-16 10:05:44,289 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-12-16 10:05:44,294 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-12-16 10:05:44,294 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-12-16 10:05:44,294 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-12-16 10:05:44,295 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:05:44" (1/1) ... [2021-12-16 10:05:44,312 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-16 10:05:44,325 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-16 10:05:44,371 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-16 10:05:44,377 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2021-12-16 10:05:44,427 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2021-12-16 10:05:44,439 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2021-12-16 10:05:44,439 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-12-16 10:05:44,440 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-12-16 10:05:44,599 INFO L236 CfgBuilder]: Building ICFG [2021-12-16 10:05:44,601 INFO L262 CfgBuilder]: Building CFG for each procedure with an implementation [2021-12-16 10:05:45,242 INFO L277 CfgBuilder]: Performing block encoding [2021-12-16 10:05:45,255 INFO L296 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-12-16 10:05:45,256 INFO L301 CfgBuilder]: Removed 9 assume(true) statements. [2021-12-16 10:05:45,259 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 16.12 10:05:45 BoogieIcfgContainer [2021-12-16 10:05:45,259 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-12-16 10:05:45,260 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2021-12-16 10:05:45,260 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2021-12-16 10:05:45,263 INFO L275 PluginConnector]: BuchiAutomizer initialized [2021-12-16 10:05:45,263 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-16 10:05:45,263 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 16.12 10:05:43" (1/3) ... [2021-12-16 10:05:45,264 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@596c8fd9 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 16.12 10:05:45, skipping insertion in model container [2021-12-16 10:05:45,264 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-16 10:05:45,264 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:05:44" (2/3) ... [2021-12-16 10:05:45,265 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@596c8fd9 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 16.12 10:05:45, skipping insertion in model container [2021-12-16 10:05:45,265 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-16 10:05:45,265 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 16.12 10:05:45" (3/3) ... [2021-12-16 10:05:45,266 INFO L388 chiAutomizerObserver]: Analyzing ICFG transmitter.05.cil.c [2021-12-16 10:05:45,302 INFO L359 BuchiCegarLoop]: Interprodecural is true [2021-12-16 10:05:45,303 INFO L360 BuchiCegarLoop]: Hoare is false [2021-12-16 10:05:45,303 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2021-12-16 10:05:45,303 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2021-12-16 10:05:45,304 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2021-12-16 10:05:45,304 INFO L364 BuchiCegarLoop]: Difference is false [2021-12-16 10:05:45,304 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2021-12-16 10:05:45,304 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2021-12-16 10:05:45,330 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 505 states, 504 states have (on average 1.5337301587301588) internal successors, (773), 504 states have internal predecessors, (773), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:45,373 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 424 [2021-12-16 10:05:45,373 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:05:45,373 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:05:45,382 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:45,383 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:45,383 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2021-12-16 10:05:45,384 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 505 states, 504 states have (on average 1.5337301587301588) internal successors, (773), 504 states have internal predecessors, (773), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:45,388 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 424 [2021-12-16 10:05:45,388 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:05:45,388 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:05:45,390 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:45,391 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:45,396 INFO L791 eck$LassoCheckResult]: Stem: 490#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 410#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 389#L863true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 385#L394true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 255#L401true assume !(1 == ~m_i~0);~m_st~0 := 2; 343#L401-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 106#L406-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 401#L411-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 384#L416-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 460#L421-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 326#L426-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 87#L586true assume 0 == ~M_E~0;~M_E~0 := 1; 119#L586-2true assume !(0 == ~T1_E~0); 231#L591-1true assume !(0 == ~T2_E~0); 207#L596-1true assume !(0 == ~T3_E~0); 269#L601-1true assume !(0 == ~T4_E~0); 247#L606-1true assume !(0 == ~T5_E~0); 462#L611-1true assume !(0 == ~E_1~0); 341#L616-1true assume !(0 == ~E_2~0); 349#L621-1true assume 0 == ~E_3~0;~E_3~0 := 1; 50#L626-1true assume !(0 == ~E_4~0); 301#L631-1true assume !(0 == ~E_5~0); 140#L636-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 48#L279true assume 1 == ~m_pc~0; 215#L280true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 366#L290true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 189#L291true activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 268#L720true assume !(0 != activate_threads_~tmp~1#1); 484#L720-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 144#L298true assume !(1 == ~t1_pc~0); 26#L298-2true is_transmit1_triggered_~__retres1~1#1 := 0; 451#L309true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 181#L310true activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 55#L728true assume !(0 != activate_threads_~tmp___0~0#1); 260#L728-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 122#L317true assume 1 == ~t2_pc~0; 238#L318true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 466#L328true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 402#L329true activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 150#L736true assume !(0 != activate_threads_~tmp___1~0#1); 421#L736-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 323#L336true assume 1 == ~t3_pc~0; 185#L337true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 485#L347true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 230#L348true activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 277#L744true assume !(0 != activate_threads_~tmp___2~0#1); 333#L744-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 405#L355true assume !(1 == ~t4_pc~0); 331#L355-2true is_transmit4_triggered_~__retres1~4#1 := 0; 98#L366true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 258#L367true activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 316#L752true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 62#L752-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 369#L374true assume 1 == ~t5_pc~0; 382#L375true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 386#L385true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 188#L386true activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 425#L760true assume !(0 != activate_threads_~tmp___4~0#1); 233#L760-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 434#L649true assume 1 == ~M_E~0;~M_E~0 := 2; 493#L649-2true assume !(1 == ~T1_E~0); 41#L654-1true assume !(1 == ~T2_E~0); 265#L659-1true assume !(1 == ~T3_E~0); 149#L664-1true assume !(1 == ~T4_E~0); 37#L669-1true assume !(1 == ~T5_E~0); 318#L674-1true assume !(1 == ~E_1~0); 329#L679-1true assume !(1 == ~E_2~0); 90#L684-1true assume 1 == ~E_3~0;~E_3~0 := 2; 201#L689-1true assume !(1 == ~E_4~0); 480#L694-1true assume !(1 == ~E_5~0); 200#L699-1true assume { :end_inline_reset_delta_events } true; 469#L900-2true [2021-12-16 10:05:45,398 INFO L793 eck$LassoCheckResult]: Loop: 469#L900-2true assume !false; 502#L901true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 60#L561true assume !true; 454#L576true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 419#L394-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 422#L586-3true assume 0 == ~M_E~0;~M_E~0 := 1; 317#L586-5true assume !(0 == ~T1_E~0); 217#L591-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 101#L596-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 228#L601-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 372#L606-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 257#L611-3true assume 0 == ~E_1~0;~E_1~0 := 1; 261#L616-3true assume 0 == ~E_2~0;~E_2~0 := 1; 44#L621-3true assume 0 == ~E_3~0;~E_3~0 := 1; 24#L626-3true assume !(0 == ~E_4~0); 503#L631-3true assume 0 == ~E_5~0;~E_5~0 := 1; 28#L636-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 431#L279-18true assume !(1 == ~m_pc~0); 161#L279-20true is_master_triggered_~__retres1~0#1 := 0; 222#L290-6true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 151#L291-6true activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 391#L720-18true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 344#L720-20true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 232#L298-18true assume 1 == ~t1_pc~0; 14#L299-6true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 105#L309-6true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 133#L310-6true activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 117#L728-18true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 443#L728-20true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 209#L317-18true assume 1 == ~t2_pc~0; 135#L318-6true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 240#L328-6true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 102#L329-6true activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 107#L736-18true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 353#L736-20true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 348#L336-18true assume !(1 == ~t3_pc~0); 488#L336-20true is_transmit3_triggered_~__retres1~3#1 := 0; 394#L347-6true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 153#L348-6true activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 174#L744-18true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 74#L744-20true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 287#L355-18true assume 1 == ~t4_pc~0; 412#L356-6true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 418#L366-6true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 123#L367-6true activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 213#L752-18true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 126#L752-20true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 332#L374-18true assume 1 == ~t5_pc~0; 458#L375-6true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 171#L385-6true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 288#L386-6true activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 445#L760-18true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 271#L760-20true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 456#L649-3true assume 1 == ~M_E~0;~M_E~0 := 2; 184#L649-5true assume !(1 == ~T1_E~0); 168#L654-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 79#L659-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 450#L664-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 29#L669-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 474#L674-3true assume 1 == ~E_1~0;~E_1~0 := 2; 23#L679-3true assume 1 == ~E_2~0;~E_2~0 := 2; 179#L684-3true assume 1 == ~E_3~0;~E_3~0 := 2; 3#L689-3true assume !(1 == ~E_4~0); 131#L694-3true assume 1 == ~E_5~0;~E_5~0 := 2; 21#L699-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 416#L439-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 473#L471-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 347#L472-1true start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 199#L919true assume !(0 == start_simulation_~tmp~3#1); 483#L919-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 299#L439-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 375#L471-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 157#L472-2true stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 192#L874true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 352#L881true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 155#L882true start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 328#L932true assume !(0 != start_simulation_~tmp___0~1#1); 469#L900-2true [2021-12-16 10:05:45,402 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:45,402 INFO L85 PathProgramCache]: Analyzing trace with hash -777385748, now seen corresponding path program 1 times [2021-12-16 10:05:45,408 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:45,409 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1950320897] [2021-12-16 10:05:45,409 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:45,410 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:45,488 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:45,572 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:05:45,572 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:45,573 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1950320897] [2021-12-16 10:05:45,574 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1950320897] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:45,574 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:45,575 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:05:45,576 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2102405452] [2021-12-16 10:05:45,576 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:45,579 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:05:45,581 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:45,581 INFO L85 PathProgramCache]: Analyzing trace with hash -129051228, now seen corresponding path program 1 times [2021-12-16 10:05:45,581 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:45,581 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [909668248] [2021-12-16 10:05:45,582 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:45,582 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:45,598 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:45,626 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:05:45,627 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:45,627 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [909668248] [2021-12-16 10:05:45,627 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [909668248] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:45,628 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:45,628 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-16 10:05:45,628 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1861039816] [2021-12-16 10:05:45,628 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:45,629 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:05:45,630 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:05:45,652 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-16 10:05:45,653 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-16 10:05:45,655 INFO L87 Difference]: Start difference. First operand has 505 states, 504 states have (on average 1.5337301587301588) internal successors, (773), 504 states have internal predecessors, (773), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 23.666666666666668) internal successors, (71), 3 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:45,697 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:05:45,700 INFO L93 Difference]: Finished difference Result 504 states and 752 transitions. [2021-12-16 10:05:45,702 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-16 10:05:45,705 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 504 states and 752 transitions. [2021-12-16 10:05:45,709 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 421 [2021-12-16 10:05:45,717 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 504 states to 498 states and 746 transitions. [2021-12-16 10:05:45,718 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 498 [2021-12-16 10:05:45,719 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 498 [2021-12-16 10:05:45,720 INFO L73 IsDeterministic]: Start isDeterministic. Operand 498 states and 746 transitions. [2021-12-16 10:05:45,727 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:05:45,727 INFO L681 BuchiCegarLoop]: Abstraction has 498 states and 746 transitions. [2021-12-16 10:05:45,740 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 498 states and 746 transitions. [2021-12-16 10:05:45,766 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 498 to 498. [2021-12-16 10:05:45,768 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 498 states, 498 states have (on average 1.497991967871486) internal successors, (746), 497 states have internal predecessors, (746), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:45,769 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 498 states to 498 states and 746 transitions. [2021-12-16 10:05:45,770 INFO L704 BuchiCegarLoop]: Abstraction has 498 states and 746 transitions. [2021-12-16 10:05:45,770 INFO L587 BuchiCegarLoop]: Abstraction has 498 states and 746 transitions. [2021-12-16 10:05:45,770 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2021-12-16 10:05:45,770 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 498 states and 746 transitions. [2021-12-16 10:05:45,774 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 421 [2021-12-16 10:05:45,775 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:05:45,778 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:05:45,780 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:45,780 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:45,781 INFO L791 eck$LassoCheckResult]: Stem: 1515#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 1501#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 1493#L863 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1491#L394 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1405#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 1406#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1211#L406-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1212#L411-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1489#L416-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1490#L421-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 1462#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1183#L586 assume 0 == ~M_E~0;~M_E~0 := 1; 1184#L586-2 assume !(0 == ~T1_E~0); 1237#L591-1 assume !(0 == ~T2_E~0); 1357#L596-1 assume !(0 == ~T3_E~0); 1358#L601-1 assume !(0 == ~T4_E~0); 1396#L606-1 assume !(0 == ~T5_E~0); 1397#L611-1 assume !(0 == ~E_1~0); 1468#L616-1 assume !(0 == ~E_2~0); 1469#L621-1 assume 0 == ~E_3~0;~E_3~0 := 1; 1116#L626-1 assume !(0 == ~E_4~0); 1117#L631-1 assume !(0 == ~E_5~0); 1272#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1111#L279 assume 1 == ~m_pc~0; 1112#L280 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1363#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1339#L291 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1340#L720 assume !(0 != activate_threads_~tmp~1#1); 1413#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1276#L298 assume !(1 == ~t1_pc~0); 1068#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1069#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1328#L310 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1125#L728 assume !(0 != activate_threads_~tmp___0~0#1); 1126#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1243#L317 assume 1 == ~t2_pc~0; 1244#L318 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1390#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1497#L329 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1285#L736 assume !(0 != activate_threads_~tmp___1~0#1); 1286#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1460#L336 assume 1 == ~t3_pc~0; 1332#L337 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1333#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1380#L348 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1381#L744 assume !(0 != activate_threads_~tmp___2~0#1); 1421#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1465#L355 assume !(1 == ~t4_pc~0); 1354#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1197#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1198#L367 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1409#L752 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1135#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1136#L374 assume 1 == ~t5_pc~0; 1483#L375 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1264#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1337#L386 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1338#L760 assume !(0 != activate_threads_~tmp___4~0#1); 1383#L760-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1384#L649 assume 1 == ~M_E~0;~M_E~0 := 2; 1506#L649-2 assume !(1 == ~T1_E~0); 1100#L654-1 assume !(1 == ~T2_E~0); 1101#L659-1 assume !(1 == ~T3_E~0); 1284#L664-1 assume !(1 == ~T4_E~0); 1093#L669-1 assume !(1 == ~T5_E~0); 1094#L674-1 assume !(1 == ~E_1~0); 1456#L679-1 assume !(1 == ~E_2~0); 1188#L684-1 assume 1 == ~E_3~0;~E_3~0 := 2; 1189#L689-1 assume !(1 == ~E_4~0); 1351#L694-1 assume !(1 == ~E_5~0); 1349#L699-1 assume { :end_inline_reset_delta_events } true; 1350#L900-2 [2021-12-16 10:05:45,781 INFO L793 eck$LassoCheckResult]: Loop: 1350#L900-2 assume !false; 1513#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1047#L561 assume !false; 1132#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 1313#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 1070#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 1071#L472 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1176#L486 assume !(0 != eval_~tmp~0#1); 1178#L576 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1503#L394-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1504#L586-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1455#L586-5 assume !(0 == ~T1_E~0); 1364#L591-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1202#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1203#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1377#L606-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1407#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1408#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1104#L621-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1065#L626-3 assume !(0 == ~E_4~0); 1066#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1072#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1073#L279-18 assume 1 == ~m_pc~0; 1165#L280-6 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1166#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1287#L291-6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1288#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1471#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1382#L298-18 assume 1 == ~t1_pc~0; 1044#L299-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1038#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1210#L310-6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1233#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1234#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1359#L317-18 assume 1 == ~t2_pc~0; 1265#L318-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1267#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1204#L329-6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1205#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1213#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1474#L336-18 assume 1 == ~t3_pc~0; 1457#L337-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1458#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1290#L348-6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1291#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1157#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1158#L355-18 assume 1 == ~t4_pc~0; 1431#L356-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1420#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1246#L367-6 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1247#L752-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1253#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1254#L374-18 assume 1 == ~t5_pc~0; 1464#L375-6 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1318#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1319#L386-6 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1432#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1414#L760-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1415#L649-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1331#L649-5 assume !(1 == ~T1_E~0); 1312#L654-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1168#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1169#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1074#L669-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1075#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1063#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1064#L684-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1018#L689-3 assume !(1 == ~E_4~0); 1019#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1058#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 1059#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 1061#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 1473#L472-1 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 1348#L919 assume !(0 == start_simulation_~tmp~3#1); 1077#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 1444#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 1052#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 1297#L472-2 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 1298#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1343#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1293#L882 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 1294#L932 assume !(0 != start_simulation_~tmp___0~1#1); 1350#L900-2 [2021-12-16 10:05:45,782 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:45,782 INFO L85 PathProgramCache]: Analyzing trace with hash 438767978, now seen corresponding path program 1 times [2021-12-16 10:05:45,782 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:45,783 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [910707091] [2021-12-16 10:05:45,783 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:45,784 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:45,792 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:45,822 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:05:45,822 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:45,822 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [910707091] [2021-12-16 10:05:45,823 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [910707091] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:45,823 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:45,823 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:05:45,823 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [290569485] [2021-12-16 10:05:45,823 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:45,824 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:05:45,824 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:45,824 INFO L85 PathProgramCache]: Analyzing trace with hash -1476238801, now seen corresponding path program 1 times [2021-12-16 10:05:45,824 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:45,825 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1068070477] [2021-12-16 10:05:45,825 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:45,825 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:45,845 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:45,919 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:05:45,919 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:45,919 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1068070477] [2021-12-16 10:05:45,919 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1068070477] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:45,919 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:45,919 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:05:45,920 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1815579615] [2021-12-16 10:05:45,920 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:45,920 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:05:45,920 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:05:45,920 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-16 10:05:45,920 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-16 10:05:45,921 INFO L87 Difference]: Start difference. First operand 498 states and 746 transitions. cyclomatic complexity: 249 Second operand has 3 states, 3 states have (on average 23.666666666666668) internal successors, (71), 3 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:45,932 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:05:45,932 INFO L93 Difference]: Finished difference Result 498 states and 745 transitions. [2021-12-16 10:05:45,934 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-16 10:05:45,935 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 498 states and 745 transitions. [2021-12-16 10:05:45,938 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 421 [2021-12-16 10:05:45,940 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 498 states to 498 states and 745 transitions. [2021-12-16 10:05:45,940 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 498 [2021-12-16 10:05:45,940 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 498 [2021-12-16 10:05:45,940 INFO L73 IsDeterministic]: Start isDeterministic. Operand 498 states and 745 transitions. [2021-12-16 10:05:45,941 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:05:45,941 INFO L681 BuchiCegarLoop]: Abstraction has 498 states and 745 transitions. [2021-12-16 10:05:45,942 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 498 states and 745 transitions. [2021-12-16 10:05:45,948 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 498 to 498. [2021-12-16 10:05:45,949 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 498 states, 498 states have (on average 1.4959839357429718) internal successors, (745), 497 states have internal predecessors, (745), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:45,950 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 498 states to 498 states and 745 transitions. [2021-12-16 10:05:45,950 INFO L704 BuchiCegarLoop]: Abstraction has 498 states and 745 transitions. [2021-12-16 10:05:45,950 INFO L587 BuchiCegarLoop]: Abstraction has 498 states and 745 transitions. [2021-12-16 10:05:45,950 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2021-12-16 10:05:45,950 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 498 states and 745 transitions. [2021-12-16 10:05:45,952 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 421 [2021-12-16 10:05:45,953 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:05:45,953 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:05:45,954 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:45,954 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:45,954 INFO L791 eck$LassoCheckResult]: Stem: 2518#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 2504#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 2496#L863 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2494#L394 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2408#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 2409#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2214#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2215#L411-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2492#L416-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2493#L421-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 2465#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2186#L586 assume 0 == ~M_E~0;~M_E~0 := 1; 2187#L586-2 assume !(0 == ~T1_E~0); 2240#L591-1 assume !(0 == ~T2_E~0); 2360#L596-1 assume !(0 == ~T3_E~0); 2361#L601-1 assume !(0 == ~T4_E~0); 2399#L606-1 assume !(0 == ~T5_E~0); 2400#L611-1 assume !(0 == ~E_1~0); 2471#L616-1 assume !(0 == ~E_2~0); 2472#L621-1 assume 0 == ~E_3~0;~E_3~0 := 1; 2119#L626-1 assume !(0 == ~E_4~0); 2120#L631-1 assume !(0 == ~E_5~0); 2275#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2114#L279 assume 1 == ~m_pc~0; 2115#L280 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 2366#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2342#L291 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 2343#L720 assume !(0 != activate_threads_~tmp~1#1); 2416#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2279#L298 assume !(1 == ~t1_pc~0); 2071#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2072#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2331#L310 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2128#L728 assume !(0 != activate_threads_~tmp___0~0#1); 2129#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2246#L317 assume 1 == ~t2_pc~0; 2247#L318 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2393#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2500#L329 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2288#L736 assume !(0 != activate_threads_~tmp___1~0#1); 2289#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2463#L336 assume 1 == ~t3_pc~0; 2335#L337 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2336#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2383#L348 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2384#L744 assume !(0 != activate_threads_~tmp___2~0#1); 2424#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2468#L355 assume !(1 == ~t4_pc~0); 2357#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 2200#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2201#L367 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2412#L752 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2138#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2139#L374 assume 1 == ~t5_pc~0; 2486#L375 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2267#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2340#L386 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2341#L760 assume !(0 != activate_threads_~tmp___4~0#1); 2386#L760-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2387#L649 assume 1 == ~M_E~0;~M_E~0 := 2; 2509#L649-2 assume !(1 == ~T1_E~0); 2103#L654-1 assume !(1 == ~T2_E~0); 2104#L659-1 assume !(1 == ~T3_E~0); 2287#L664-1 assume !(1 == ~T4_E~0); 2096#L669-1 assume !(1 == ~T5_E~0); 2097#L674-1 assume !(1 == ~E_1~0); 2459#L679-1 assume !(1 == ~E_2~0); 2191#L684-1 assume 1 == ~E_3~0;~E_3~0 := 2; 2192#L689-1 assume !(1 == ~E_4~0); 2354#L694-1 assume !(1 == ~E_5~0); 2352#L699-1 assume { :end_inline_reset_delta_events } true; 2353#L900-2 [2021-12-16 10:05:45,955 INFO L793 eck$LassoCheckResult]: Loop: 2353#L900-2 assume !false; 2516#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2050#L561 assume !false; 2135#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 2316#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 2073#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 2074#L472 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 2179#L486 assume !(0 != eval_~tmp~0#1); 2181#L576 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2506#L394-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2507#L586-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2458#L586-5 assume !(0 == ~T1_E~0); 2367#L591-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2205#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2206#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2380#L606-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2410#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2411#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2107#L621-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2068#L626-3 assume !(0 == ~E_4~0); 2069#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2075#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2076#L279-18 assume 1 == ~m_pc~0; 2168#L280-6 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 2169#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2290#L291-6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 2291#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2474#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2385#L298-18 assume !(1 == ~t1_pc~0); 2040#L298-20 is_transmit1_triggered_~__retres1~1#1 := 0; 2041#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2213#L310-6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2236#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2237#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2362#L317-18 assume 1 == ~t2_pc~0; 2268#L318-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2270#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2207#L329-6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2208#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2216#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2477#L336-18 assume 1 == ~t3_pc~0; 2460#L337-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2461#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2293#L348-6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2294#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2160#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2161#L355-18 assume 1 == ~t4_pc~0; 2434#L356-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2423#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2249#L367-6 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2250#L752-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2256#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2257#L374-18 assume 1 == ~t5_pc~0; 2467#L375-6 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2321#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2322#L386-6 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2435#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2417#L760-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2418#L649-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2334#L649-5 assume !(1 == ~T1_E~0); 2315#L654-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2171#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2172#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2077#L669-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2078#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2066#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2067#L684-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2021#L689-3 assume !(1 == ~E_4~0); 2022#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2061#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 2062#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 2064#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 2476#L472-1 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 2351#L919 assume !(0 == start_simulation_~tmp~3#1); 2080#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 2447#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 2055#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 2300#L472-2 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 2301#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2346#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2296#L882 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 2297#L932 assume !(0 != start_simulation_~tmp___0~1#1); 2353#L900-2 [2021-12-16 10:05:45,956 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:45,956 INFO L85 PathProgramCache]: Analyzing trace with hash 2124947816, now seen corresponding path program 1 times [2021-12-16 10:05:45,956 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:45,956 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [632441612] [2021-12-16 10:05:45,956 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:45,957 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:45,964 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:45,980 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:05:45,980 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:45,980 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [632441612] [2021-12-16 10:05:45,980 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [632441612] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:45,980 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:45,981 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:05:45,981 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1686885301] [2021-12-16 10:05:45,981 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:45,981 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:05:45,982 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:45,982 INFO L85 PathProgramCache]: Analyzing trace with hash -1373437554, now seen corresponding path program 1 times [2021-12-16 10:05:45,982 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:45,982 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2109839935] [2021-12-16 10:05:45,982 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:45,982 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:45,992 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:46,010 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:05:46,011 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:46,011 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2109839935] [2021-12-16 10:05:46,011 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2109839935] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:46,011 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:46,011 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:05:46,011 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [627873920] [2021-12-16 10:05:46,012 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:46,012 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:05:46,012 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:05:46,012 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-16 10:05:46,012 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-16 10:05:46,013 INFO L87 Difference]: Start difference. First operand 498 states and 745 transitions. cyclomatic complexity: 248 Second operand has 3 states, 3 states have (on average 23.666666666666668) internal successors, (71), 3 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:46,020 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:05:46,020 INFO L93 Difference]: Finished difference Result 498 states and 744 transitions. [2021-12-16 10:05:46,020 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-16 10:05:46,021 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 498 states and 744 transitions. [2021-12-16 10:05:46,023 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 421 [2021-12-16 10:05:46,025 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 498 states to 498 states and 744 transitions. [2021-12-16 10:05:46,025 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 498 [2021-12-16 10:05:46,025 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 498 [2021-12-16 10:05:46,026 INFO L73 IsDeterministic]: Start isDeterministic. Operand 498 states and 744 transitions. [2021-12-16 10:05:46,026 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:05:46,026 INFO L681 BuchiCegarLoop]: Abstraction has 498 states and 744 transitions. [2021-12-16 10:05:46,027 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 498 states and 744 transitions. [2021-12-16 10:05:46,032 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 498 to 498. [2021-12-16 10:05:46,033 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 498 states, 498 states have (on average 1.4939759036144578) internal successors, (744), 497 states have internal predecessors, (744), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:46,034 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 498 states to 498 states and 744 transitions. [2021-12-16 10:05:46,034 INFO L704 BuchiCegarLoop]: Abstraction has 498 states and 744 transitions. [2021-12-16 10:05:46,034 INFO L587 BuchiCegarLoop]: Abstraction has 498 states and 744 transitions. [2021-12-16 10:05:46,034 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2021-12-16 10:05:46,034 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 498 states and 744 transitions. [2021-12-16 10:05:46,036 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 421 [2021-12-16 10:05:46,036 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:05:46,036 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:05:46,037 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:46,037 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:46,038 INFO L791 eck$LassoCheckResult]: Stem: 3521#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 3507#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 3499#L863 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3497#L394 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3411#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 3412#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3217#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3218#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3495#L416-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 3496#L421-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3468#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3189#L586 assume 0 == ~M_E~0;~M_E~0 := 1; 3190#L586-2 assume !(0 == ~T1_E~0); 3243#L591-1 assume !(0 == ~T2_E~0); 3363#L596-1 assume !(0 == ~T3_E~0); 3364#L601-1 assume !(0 == ~T4_E~0); 3402#L606-1 assume !(0 == ~T5_E~0); 3403#L611-1 assume !(0 == ~E_1~0); 3474#L616-1 assume !(0 == ~E_2~0); 3475#L621-1 assume 0 == ~E_3~0;~E_3~0 := 1; 3122#L626-1 assume !(0 == ~E_4~0); 3123#L631-1 assume !(0 == ~E_5~0); 3278#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3117#L279 assume 1 == ~m_pc~0; 3118#L280 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 3369#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3345#L291 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 3346#L720 assume !(0 != activate_threads_~tmp~1#1); 3419#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3282#L298 assume !(1 == ~t1_pc~0); 3074#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 3075#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3334#L310 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 3131#L728 assume !(0 != activate_threads_~tmp___0~0#1); 3132#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3249#L317 assume 1 == ~t2_pc~0; 3250#L318 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3396#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3503#L329 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3291#L736 assume !(0 != activate_threads_~tmp___1~0#1); 3292#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3466#L336 assume 1 == ~t3_pc~0; 3338#L337 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3339#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3386#L348 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3387#L744 assume !(0 != activate_threads_~tmp___2~0#1); 3427#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3471#L355 assume !(1 == ~t4_pc~0); 3360#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 3203#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3204#L367 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3415#L752 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3141#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3142#L374 assume 1 == ~t5_pc~0; 3489#L375 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 3270#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3343#L386 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3344#L760 assume !(0 != activate_threads_~tmp___4~0#1); 3389#L760-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3390#L649 assume 1 == ~M_E~0;~M_E~0 := 2; 3512#L649-2 assume !(1 == ~T1_E~0); 3106#L654-1 assume !(1 == ~T2_E~0); 3107#L659-1 assume !(1 == ~T3_E~0); 3290#L664-1 assume !(1 == ~T4_E~0); 3099#L669-1 assume !(1 == ~T5_E~0); 3100#L674-1 assume !(1 == ~E_1~0); 3462#L679-1 assume !(1 == ~E_2~0); 3194#L684-1 assume 1 == ~E_3~0;~E_3~0 := 2; 3195#L689-1 assume !(1 == ~E_4~0); 3357#L694-1 assume !(1 == ~E_5~0); 3355#L699-1 assume { :end_inline_reset_delta_events } true; 3356#L900-2 [2021-12-16 10:05:46,038 INFO L793 eck$LassoCheckResult]: Loop: 3356#L900-2 assume !false; 3519#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3053#L561 assume !false; 3138#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 3319#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 3076#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 3077#L472 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 3182#L486 assume !(0 != eval_~tmp~0#1); 3184#L576 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3509#L394-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3510#L586-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3461#L586-5 assume !(0 == ~T1_E~0); 3370#L591-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3208#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3209#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3383#L606-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3413#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3414#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3110#L621-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3071#L626-3 assume !(0 == ~E_4~0); 3072#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 3078#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3079#L279-18 assume 1 == ~m_pc~0; 3171#L280-6 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 3172#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3293#L291-6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 3294#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3477#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3388#L298-18 assume !(1 == ~t1_pc~0); 3043#L298-20 is_transmit1_triggered_~__retres1~1#1 := 0; 3044#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3216#L310-6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 3239#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3240#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3365#L317-18 assume 1 == ~t2_pc~0; 3271#L318-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3273#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3210#L329-6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3211#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3219#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3480#L336-18 assume 1 == ~t3_pc~0; 3463#L337-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3464#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3296#L348-6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3297#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3163#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3164#L355-18 assume !(1 == ~t4_pc~0); 3425#L355-20 is_transmit4_triggered_~__retres1~4#1 := 0; 3426#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3252#L367-6 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3253#L752-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3259#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3260#L374-18 assume !(1 == ~t5_pc~0); 3444#L374-20 is_transmit5_triggered_~__retres1~5#1 := 0; 3324#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3325#L386-6 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3438#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 3420#L760-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3421#L649-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3337#L649-5 assume !(1 == ~T1_E~0); 3318#L654-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3174#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3175#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3080#L669-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3081#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3069#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3070#L684-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3024#L689-3 assume !(1 == ~E_4~0); 3025#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3064#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 3065#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 3067#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 3479#L472-1 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 3354#L919 assume !(0 == start_simulation_~tmp~3#1); 3083#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 3450#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 3058#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 3303#L472-2 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 3304#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3349#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3299#L882 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 3300#L932 assume !(0 != start_simulation_~tmp___0~1#1); 3356#L900-2 [2021-12-16 10:05:46,038 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:46,039 INFO L85 PathProgramCache]: Analyzing trace with hash -2115626582, now seen corresponding path program 1 times [2021-12-16 10:05:46,039 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:46,039 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [174364084] [2021-12-16 10:05:46,039 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:46,039 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:46,046 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:46,057 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:05:46,058 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:46,058 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [174364084] [2021-12-16 10:05:46,058 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [174364084] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:46,058 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:46,059 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:05:46,059 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1304694435] [2021-12-16 10:05:46,059 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:46,059 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:05:46,060 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:46,060 INFO L85 PathProgramCache]: Analyzing trace with hash 1099568908, now seen corresponding path program 1 times [2021-12-16 10:05:46,060 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:46,060 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1335871963] [2021-12-16 10:05:46,060 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:46,060 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:46,071 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:46,091 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:05:46,091 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:46,092 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1335871963] [2021-12-16 10:05:46,092 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1335871963] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:46,092 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:46,092 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-16 10:05:46,092 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1821907483] [2021-12-16 10:05:46,093 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:46,093 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:05:46,093 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:05:46,093 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-16 10:05:46,094 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-16 10:05:46,094 INFO L87 Difference]: Start difference. First operand 498 states and 744 transitions. cyclomatic complexity: 247 Second operand has 3 states, 3 states have (on average 23.666666666666668) internal successors, (71), 3 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:46,102 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:05:46,102 INFO L93 Difference]: Finished difference Result 498 states and 743 transitions. [2021-12-16 10:05:46,103 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-16 10:05:46,104 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 498 states and 743 transitions. [2021-12-16 10:05:46,106 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 421 [2021-12-16 10:05:46,108 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 498 states to 498 states and 743 transitions. [2021-12-16 10:05:46,108 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 498 [2021-12-16 10:05:46,108 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 498 [2021-12-16 10:05:46,109 INFO L73 IsDeterministic]: Start isDeterministic. Operand 498 states and 743 transitions. [2021-12-16 10:05:46,109 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:05:46,109 INFO L681 BuchiCegarLoop]: Abstraction has 498 states and 743 transitions. [2021-12-16 10:05:46,110 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 498 states and 743 transitions. [2021-12-16 10:05:46,114 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 498 to 498. [2021-12-16 10:05:46,114 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 498 states, 498 states have (on average 1.4919678714859437) internal successors, (743), 497 states have internal predecessors, (743), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:46,115 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 498 states to 498 states and 743 transitions. [2021-12-16 10:05:46,116 INFO L704 BuchiCegarLoop]: Abstraction has 498 states and 743 transitions. [2021-12-16 10:05:46,116 INFO L587 BuchiCegarLoop]: Abstraction has 498 states and 743 transitions. [2021-12-16 10:05:46,116 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2021-12-16 10:05:46,116 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 498 states and 743 transitions. [2021-12-16 10:05:46,118 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 421 [2021-12-16 10:05:46,118 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:05:46,118 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:05:46,119 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:46,119 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:46,119 INFO L791 eck$LassoCheckResult]: Stem: 4526#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 4512#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 4504#L863 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4502#L394 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4416#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 4417#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4222#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4223#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4500#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 4501#L421-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 4473#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4194#L586 assume 0 == ~M_E~0;~M_E~0 := 1; 4195#L586-2 assume !(0 == ~T1_E~0); 4248#L591-1 assume !(0 == ~T2_E~0); 4368#L596-1 assume !(0 == ~T3_E~0); 4369#L601-1 assume !(0 == ~T4_E~0); 4407#L606-1 assume !(0 == ~T5_E~0); 4408#L611-1 assume !(0 == ~E_1~0); 4479#L616-1 assume !(0 == ~E_2~0); 4480#L621-1 assume 0 == ~E_3~0;~E_3~0 := 1; 4127#L626-1 assume !(0 == ~E_4~0); 4128#L631-1 assume !(0 == ~E_5~0); 4283#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4122#L279 assume 1 == ~m_pc~0; 4123#L280 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 4374#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4350#L291 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 4351#L720 assume !(0 != activate_threads_~tmp~1#1); 4424#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4287#L298 assume !(1 == ~t1_pc~0); 4079#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4080#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4339#L310 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 4136#L728 assume !(0 != activate_threads_~tmp___0~0#1); 4137#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4254#L317 assume 1 == ~t2_pc~0; 4255#L318 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4401#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4508#L329 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4296#L736 assume !(0 != activate_threads_~tmp___1~0#1); 4297#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4471#L336 assume 1 == ~t3_pc~0; 4343#L337 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4344#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4391#L348 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4392#L744 assume !(0 != activate_threads_~tmp___2~0#1); 4432#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4476#L355 assume !(1 == ~t4_pc~0); 4365#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 4208#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4209#L367 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4420#L752 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4146#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4147#L374 assume 1 == ~t5_pc~0; 4494#L375 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 4275#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4348#L386 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4349#L760 assume !(0 != activate_threads_~tmp___4~0#1); 4394#L760-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4395#L649 assume 1 == ~M_E~0;~M_E~0 := 2; 4517#L649-2 assume !(1 == ~T1_E~0); 4111#L654-1 assume !(1 == ~T2_E~0); 4112#L659-1 assume !(1 == ~T3_E~0); 4295#L664-1 assume !(1 == ~T4_E~0); 4104#L669-1 assume !(1 == ~T5_E~0); 4105#L674-1 assume !(1 == ~E_1~0); 4467#L679-1 assume !(1 == ~E_2~0); 4199#L684-1 assume 1 == ~E_3~0;~E_3~0 := 2; 4200#L689-1 assume !(1 == ~E_4~0); 4362#L694-1 assume !(1 == ~E_5~0); 4360#L699-1 assume { :end_inline_reset_delta_events } true; 4361#L900-2 [2021-12-16 10:05:46,120 INFO L793 eck$LassoCheckResult]: Loop: 4361#L900-2 assume !false; 4524#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4058#L561 assume !false; 4143#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 4324#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 4081#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 4082#L472 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 4187#L486 assume !(0 != eval_~tmp~0#1); 4189#L576 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4514#L394-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4515#L586-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4466#L586-5 assume !(0 == ~T1_E~0); 4375#L591-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4213#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4214#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4388#L606-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4418#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4419#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4115#L621-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4076#L626-3 assume !(0 == ~E_4~0); 4077#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4083#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4084#L279-18 assume 1 == ~m_pc~0; 4176#L280-6 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 4177#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4298#L291-6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 4299#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4482#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4393#L298-18 assume !(1 == ~t1_pc~0); 4048#L298-20 is_transmit1_triggered_~__retres1~1#1 := 0; 4049#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4221#L310-6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 4244#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4245#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4370#L317-18 assume 1 == ~t2_pc~0; 4276#L318-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4278#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4215#L329-6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4216#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4224#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4485#L336-18 assume 1 == ~t3_pc~0; 4468#L337-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4469#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4301#L348-6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4302#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4168#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4169#L355-18 assume 1 == ~t4_pc~0; 4442#L356-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4431#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4257#L367-6 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4258#L752-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4264#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4265#L374-18 assume !(1 == ~t5_pc~0); 4449#L374-20 is_transmit5_triggered_~__retres1~5#1 := 0; 4329#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4330#L386-6 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4443#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 4425#L760-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4426#L649-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4342#L649-5 assume !(1 == ~T1_E~0); 4323#L654-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4179#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4180#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4085#L669-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4086#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4074#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4075#L684-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4029#L689-3 assume !(1 == ~E_4~0); 4030#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4069#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 4070#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 4072#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 4484#L472-1 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 4359#L919 assume !(0 == start_simulation_~tmp~3#1); 4088#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 4455#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 4063#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 4308#L472-2 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 4309#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4354#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4304#L882 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 4305#L932 assume !(0 != start_simulation_~tmp___0~1#1); 4361#L900-2 [2021-12-16 10:05:46,120 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:46,120 INFO L85 PathProgramCache]: Analyzing trace with hash -1698229976, now seen corresponding path program 1 times [2021-12-16 10:05:46,120 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:46,121 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [776667378] [2021-12-16 10:05:46,121 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:46,121 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:46,127 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:46,155 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:05:46,155 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:46,155 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [776667378] [2021-12-16 10:05:46,156 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [776667378] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:46,156 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:46,156 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:05:46,156 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1630593949] [2021-12-16 10:05:46,156 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:46,157 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:05:46,157 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:46,157 INFO L85 PathProgramCache]: Analyzing trace with hash -1430581779, now seen corresponding path program 1 times [2021-12-16 10:05:46,157 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:46,157 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1289956849] [2021-12-16 10:05:46,158 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:46,158 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:46,165 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:46,185 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:05:46,185 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:46,185 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1289956849] [2021-12-16 10:05:46,185 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1289956849] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:46,186 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:46,186 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:05:46,186 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [979397696] [2021-12-16 10:05:46,186 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:46,186 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:05:46,187 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:05:46,187 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-16 10:05:46,187 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-16 10:05:46,187 INFO L87 Difference]: Start difference. First operand 498 states and 743 transitions. cyclomatic complexity: 246 Second operand has 3 states, 3 states have (on average 23.666666666666668) internal successors, (71), 3 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:46,194 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:05:46,194 INFO L93 Difference]: Finished difference Result 498 states and 742 transitions. [2021-12-16 10:05:46,194 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-16 10:05:46,195 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 498 states and 742 transitions. [2021-12-16 10:05:46,197 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 421 [2021-12-16 10:05:46,199 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 498 states to 498 states and 742 transitions. [2021-12-16 10:05:46,199 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 498 [2021-12-16 10:05:46,199 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 498 [2021-12-16 10:05:46,199 INFO L73 IsDeterministic]: Start isDeterministic. Operand 498 states and 742 transitions. [2021-12-16 10:05:46,203 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:05:46,203 INFO L681 BuchiCegarLoop]: Abstraction has 498 states and 742 transitions. [2021-12-16 10:05:46,204 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 498 states and 742 transitions. [2021-12-16 10:05:46,207 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 498 to 498. [2021-12-16 10:05:46,208 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 498 states, 498 states have (on average 1.4899598393574298) internal successors, (742), 497 states have internal predecessors, (742), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:46,210 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 498 states to 498 states and 742 transitions. [2021-12-16 10:05:46,211 INFO L704 BuchiCegarLoop]: Abstraction has 498 states and 742 transitions. [2021-12-16 10:05:46,211 INFO L587 BuchiCegarLoop]: Abstraction has 498 states and 742 transitions. [2021-12-16 10:05:46,211 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2021-12-16 10:05:46,211 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 498 states and 742 transitions. [2021-12-16 10:05:46,213 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 421 [2021-12-16 10:05:46,213 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:05:46,213 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:05:46,215 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:46,216 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:46,216 INFO L791 eck$LassoCheckResult]: Stem: 5529#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 5515#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 5507#L863 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5505#L394 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5419#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 5420#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5225#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5226#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5503#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 5504#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 5476#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5197#L586 assume 0 == ~M_E~0;~M_E~0 := 1; 5198#L586-2 assume !(0 == ~T1_E~0); 5251#L591-1 assume !(0 == ~T2_E~0); 5371#L596-1 assume !(0 == ~T3_E~0); 5372#L601-1 assume !(0 == ~T4_E~0); 5410#L606-1 assume !(0 == ~T5_E~0); 5411#L611-1 assume !(0 == ~E_1~0); 5482#L616-1 assume !(0 == ~E_2~0); 5483#L621-1 assume 0 == ~E_3~0;~E_3~0 := 1; 5130#L626-1 assume !(0 == ~E_4~0); 5131#L631-1 assume !(0 == ~E_5~0); 5286#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5125#L279 assume 1 == ~m_pc~0; 5126#L280 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 5377#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5353#L291 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 5354#L720 assume !(0 != activate_threads_~tmp~1#1); 5427#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5290#L298 assume !(1 == ~t1_pc~0); 5082#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 5083#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5342#L310 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 5139#L728 assume !(0 != activate_threads_~tmp___0~0#1); 5140#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5257#L317 assume 1 == ~t2_pc~0; 5258#L318 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5404#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5511#L329 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 5299#L736 assume !(0 != activate_threads_~tmp___1~0#1); 5300#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5474#L336 assume 1 == ~t3_pc~0; 5346#L337 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5347#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5394#L348 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5395#L744 assume !(0 != activate_threads_~tmp___2~0#1); 5435#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5479#L355 assume !(1 == ~t4_pc~0); 5368#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 5211#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5212#L367 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5423#L752 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5149#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5150#L374 assume 1 == ~t5_pc~0; 5497#L375 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5278#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5351#L386 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5352#L760 assume !(0 != activate_threads_~tmp___4~0#1); 5397#L760-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5398#L649 assume 1 == ~M_E~0;~M_E~0 := 2; 5520#L649-2 assume !(1 == ~T1_E~0); 5114#L654-1 assume !(1 == ~T2_E~0); 5115#L659-1 assume !(1 == ~T3_E~0); 5298#L664-1 assume !(1 == ~T4_E~0); 5107#L669-1 assume !(1 == ~T5_E~0); 5108#L674-1 assume !(1 == ~E_1~0); 5470#L679-1 assume !(1 == ~E_2~0); 5202#L684-1 assume 1 == ~E_3~0;~E_3~0 := 2; 5203#L689-1 assume !(1 == ~E_4~0); 5365#L694-1 assume !(1 == ~E_5~0); 5363#L699-1 assume { :end_inline_reset_delta_events } true; 5364#L900-2 [2021-12-16 10:05:46,216 INFO L793 eck$LassoCheckResult]: Loop: 5364#L900-2 assume !false; 5527#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5061#L561 assume !false; 5146#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 5327#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 5084#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 5085#L472 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 5190#L486 assume !(0 != eval_~tmp~0#1); 5192#L576 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5517#L394-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5518#L586-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5469#L586-5 assume !(0 == ~T1_E~0); 5378#L591-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5216#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5217#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5391#L606-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5421#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5422#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5118#L621-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5079#L626-3 assume !(0 == ~E_4~0); 5080#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 5086#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5087#L279-18 assume 1 == ~m_pc~0; 5179#L280-6 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 5180#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5301#L291-6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 5302#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 5485#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5396#L298-18 assume 1 == ~t1_pc~0; 5058#L299-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5052#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5224#L310-6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 5247#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5248#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5373#L317-18 assume !(1 == ~t2_pc~0); 5280#L317-20 is_transmit2_triggered_~__retres1~2#1 := 0; 5281#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5218#L329-6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 5219#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5227#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5488#L336-18 assume !(1 == ~t3_pc~0); 5473#L336-20 is_transmit3_triggered_~__retres1~3#1 := 0; 5472#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5304#L348-6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5305#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5171#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5172#L355-18 assume 1 == ~t4_pc~0; 5445#L356-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5434#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5260#L367-6 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5261#L752-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5267#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5268#L374-18 assume 1 == ~t5_pc~0; 5478#L375-6 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5332#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5333#L386-6 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5446#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 5428#L760-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5429#L649-3 assume 1 == ~M_E~0;~M_E~0 := 2; 5345#L649-5 assume !(1 == ~T1_E~0); 5326#L654-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5182#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5183#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5088#L669-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5089#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5077#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5078#L684-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5032#L689-3 assume !(1 == ~E_4~0); 5033#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 5072#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 5073#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 5075#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 5487#L472-1 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 5362#L919 assume !(0 == start_simulation_~tmp~3#1); 5091#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 5458#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 5066#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 5311#L472-2 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 5312#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5357#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5307#L882 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 5308#L932 assume !(0 != start_simulation_~tmp___0~1#1); 5364#L900-2 [2021-12-16 10:05:46,220 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:46,220 INFO L85 PathProgramCache]: Analyzing trace with hash 1917465066, now seen corresponding path program 1 times [2021-12-16 10:05:46,220 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:46,220 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1927545953] [2021-12-16 10:05:46,220 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:46,221 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:46,236 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:46,256 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:05:46,256 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:46,257 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1927545953] [2021-12-16 10:05:46,257 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1927545953] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:46,257 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:46,257 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-16 10:05:46,258 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1393183786] [2021-12-16 10:05:46,258 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:46,258 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:05:46,259 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:46,260 INFO L85 PathProgramCache]: Analyzing trace with hash 2096048813, now seen corresponding path program 1 times [2021-12-16 10:05:46,260 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:46,263 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2104628320] [2021-12-16 10:05:46,263 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:46,263 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:46,273 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:46,331 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:05:46,332 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:46,332 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2104628320] [2021-12-16 10:05:46,332 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2104628320] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:46,332 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:46,332 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:05:46,332 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1585509787] [2021-12-16 10:05:46,333 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:46,333 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:05:46,333 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:05:46,333 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-16 10:05:46,333 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-16 10:05:46,334 INFO L87 Difference]: Start difference. First operand 498 states and 742 transitions. cyclomatic complexity: 245 Second operand has 3 states, 3 states have (on average 23.666666666666668) internal successors, (71), 2 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:46,375 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:05:46,375 INFO L93 Difference]: Finished difference Result 875 states and 1292 transitions. [2021-12-16 10:05:46,375 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-16 10:05:46,376 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 875 states and 1292 transitions. [2021-12-16 10:05:46,380 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 798 [2021-12-16 10:05:46,383 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 875 states to 875 states and 1292 transitions. [2021-12-16 10:05:46,383 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 875 [2021-12-16 10:05:46,384 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 875 [2021-12-16 10:05:46,384 INFO L73 IsDeterministic]: Start isDeterministic. Operand 875 states and 1292 transitions. [2021-12-16 10:05:46,385 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:05:46,385 INFO L681 BuchiCegarLoop]: Abstraction has 875 states and 1292 transitions. [2021-12-16 10:05:46,385 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 875 states and 1292 transitions. [2021-12-16 10:05:46,394 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 875 to 875. [2021-12-16 10:05:46,395 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 875 states, 875 states have (on average 1.4765714285714286) internal successors, (1292), 874 states have internal predecessors, (1292), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:46,397 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 875 states to 875 states and 1292 transitions. [2021-12-16 10:05:46,397 INFO L704 BuchiCegarLoop]: Abstraction has 875 states and 1292 transitions. [2021-12-16 10:05:46,397 INFO L587 BuchiCegarLoop]: Abstraction has 875 states and 1292 transitions. [2021-12-16 10:05:46,397 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2021-12-16 10:05:46,397 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 875 states and 1292 transitions. [2021-12-16 10:05:46,400 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 798 [2021-12-16 10:05:46,400 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:05:46,400 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:05:46,401 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:46,401 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:46,401 INFO L791 eck$LassoCheckResult]: Stem: 6939#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 6919#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 6910#L863 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6908#L394 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6808#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 6809#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6608#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6609#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 6906#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 6907#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 6871#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6581#L586 assume !(0 == ~M_E~0); 6582#L586-2 assume !(0 == ~T1_E~0); 6635#L591-1 assume !(0 == ~T2_E~0); 6760#L596-1 assume !(0 == ~T3_E~0); 6761#L601-1 assume !(0 == ~T4_E~0); 6799#L606-1 assume !(0 == ~T5_E~0); 6800#L611-1 assume !(0 == ~E_1~0); 6878#L616-1 assume !(0 == ~E_2~0); 6879#L621-1 assume 0 == ~E_3~0;~E_3~0 := 1; 6509#L626-1 assume !(0 == ~E_4~0); 6510#L631-1 assume !(0 == ~E_5~0); 6670#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6504#L279 assume !(1 == ~m_pc~0); 6506#L279-2 is_master_triggered_~__retres1~0#1 := 0; 6817#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6741#L291 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 6742#L720 assume !(0 != activate_threads_~tmp~1#1); 6816#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6676#L298 assume !(1 == ~t1_pc~0); 6462#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 6463#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6729#L310 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 6518#L728 assume !(0 != activate_threads_~tmp___0~0#1); 6519#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6641#L317 assume 1 == ~t2_pc~0; 6642#L318 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 6793#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6914#L329 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 6690#L736 assume !(0 != activate_threads_~tmp___1~0#1); 6691#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6869#L336 assume 1 == ~t3_pc~0; 6733#L337 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6734#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6782#L348 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 6783#L744 assume !(0 != activate_threads_~tmp___2~0#1); 6825#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6875#L355 assume !(1 == ~t4_pc~0); 6759#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 6596#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6597#L367 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 6812#L752 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 6531#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6532#L374 assume 1 == ~t5_pc~0; 6897#L375 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 6665#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6739#L386 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6740#L760 assume !(0 != activate_threads_~tmp___4~0#1); 6785#L760-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6786#L649 assume !(1 == ~M_E~0); 6927#L649-2 assume !(1 == ~T1_E~0); 6493#L654-1 assume !(1 == ~T2_E~0); 6494#L659-1 assume !(1 == ~T3_E~0); 6684#L664-1 assume !(1 == ~T4_E~0); 6486#L669-1 assume !(1 == ~T5_E~0); 6487#L674-1 assume !(1 == ~E_1~0); 6863#L679-1 assume !(1 == ~E_2~0); 6583#L684-1 assume 1 == ~E_3~0;~E_3~0 := 2; 6584#L689-1 assume !(1 == ~E_4~0); 6754#L694-1 assume !(1 == ~E_5~0); 6752#L699-1 assume { :end_inline_reset_delta_events } true; 6753#L900-2 [2021-12-16 10:05:46,402 INFO L793 eck$LassoCheckResult]: Loop: 6753#L900-2 assume !false; 6936#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 6441#L561 assume !false; 6525#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 6714#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 6464#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 6465#L472 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 6570#L486 assume !(0 != eval_~tmp~0#1); 6572#L576 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 6922#L394-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 6923#L586-3 assume !(0 == ~M_E~0); 6925#L586-5 assume !(0 == ~T1_E~0); 7098#L591-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7097#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 7096#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 7095#L606-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 7094#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7093#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 7092#L621-3 assume 0 == ~E_3~0;~E_3~0 := 1; 7091#L626-3 assume !(0 == ~E_4~0); 7090#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 6466#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6467#L279-18 assume !(1 == ~m_pc~0); 6559#L279-20 is_master_triggered_~__retres1~0#1 := 0; 6701#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6685#L291-6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 6686#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 6881#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6784#L298-18 assume 1 == ~t1_pc~0; 6438#L299-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 6432#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6607#L310-6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 6631#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 6632#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6762#L317-18 assume 1 == ~t2_pc~0; 6661#L318-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 6663#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6599#L329-6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 6600#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 6610#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6884#L336-18 assume 1 == ~t3_pc~0; 6864#L337-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6865#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6688#L348-6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 6689#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 6550#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6551#L355-18 assume 1 == ~t4_pc~0; 6837#L356-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 6824#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6644#L367-6 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 6645#L752-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 6651#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6652#L374-18 assume 1 == ~t5_pc~0; 6873#L375-6 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 6719#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6720#L386-6 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6838#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 6818#L760-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6819#L649-3 assume !(1 == ~M_E~0); 6732#L649-5 assume !(1 == ~T1_E~0); 6713#L654-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 6560#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 6561#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 6468#L669-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 6469#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 6457#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 6458#L684-3 assume 1 == ~E_3~0;~E_3~0 := 2; 6412#L689-3 assume !(1 == ~E_4~0); 6413#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 6452#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 6453#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 6455#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 6883#L472-1 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 6750#L919 assume !(0 == start_simulation_~tmp~3#1); 6471#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 6938#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 7074#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 7073#L472-2 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 7072#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 6885#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6693#L882 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 6694#L932 assume !(0 != start_simulation_~tmp___0~1#1); 6753#L900-2 [2021-12-16 10:05:46,402 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:46,402 INFO L85 PathProgramCache]: Analyzing trace with hash -484678139, now seen corresponding path program 1 times [2021-12-16 10:05:46,402 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:46,403 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1631184091] [2021-12-16 10:05:46,403 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:46,403 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:46,410 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:46,429 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:05:46,429 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:46,429 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1631184091] [2021-12-16 10:05:46,430 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1631184091] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:46,430 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:46,430 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:05:46,430 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1897536436] [2021-12-16 10:05:46,430 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:46,430 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:05:46,431 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:46,431 INFO L85 PathProgramCache]: Analyzing trace with hash 855131594, now seen corresponding path program 1 times [2021-12-16 10:05:46,431 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:46,431 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1995608581] [2021-12-16 10:05:46,432 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:46,432 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:46,440 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:46,455 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:05:46,456 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:46,456 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1995608581] [2021-12-16 10:05:46,456 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1995608581] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:46,456 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:46,457 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:05:46,457 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [831467464] [2021-12-16 10:05:46,457 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:46,458 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:05:46,458 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:05:46,458 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-16 10:05:46,458 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-16 10:05:46,458 INFO L87 Difference]: Start difference. First operand 875 states and 1292 transitions. cyclomatic complexity: 418 Second operand has 4 states, 4 states have (on average 17.75) internal successors, (71), 3 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:46,536 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:05:46,536 INFO L93 Difference]: Finished difference Result 1201 states and 1765 transitions. [2021-12-16 10:05:46,536 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-16 10:05:46,538 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1201 states and 1765 transitions. [2021-12-16 10:05:46,543 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1120 [2021-12-16 10:05:46,548 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1201 states to 1201 states and 1765 transitions. [2021-12-16 10:05:46,548 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1201 [2021-12-16 10:05:46,549 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1201 [2021-12-16 10:05:46,549 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1201 states and 1765 transitions. [2021-12-16 10:05:46,550 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:05:46,550 INFO L681 BuchiCegarLoop]: Abstraction has 1201 states and 1765 transitions. [2021-12-16 10:05:46,551 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1201 states and 1765 transitions. [2021-12-16 10:05:46,559 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1201 to 875. [2021-12-16 10:05:46,560 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 875 states, 875 states have (on average 1.473142857142857) internal successors, (1289), 874 states have internal predecessors, (1289), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:46,562 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 875 states to 875 states and 1289 transitions. [2021-12-16 10:05:46,562 INFO L704 BuchiCegarLoop]: Abstraction has 875 states and 1289 transitions. [2021-12-16 10:05:46,562 INFO L587 BuchiCegarLoop]: Abstraction has 875 states and 1289 transitions. [2021-12-16 10:05:46,562 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2021-12-16 10:05:46,562 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 875 states and 1289 transitions. [2021-12-16 10:05:46,565 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 798 [2021-12-16 10:05:46,565 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:05:46,566 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:05:46,567 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:46,567 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:46,567 INFO L791 eck$LassoCheckResult]: Stem: 9025#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 9001#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 8990#L863 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8988#L394 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 8892#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 8893#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8691#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8692#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 8986#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 8987#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 8956#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8666#L586 assume !(0 == ~M_E~0); 8667#L586-2 assume !(0 == ~T1_E~0); 8718#L591-1 assume !(0 == ~T2_E~0); 8840#L596-1 assume !(0 == ~T3_E~0); 8841#L601-1 assume !(0 == ~T4_E~0); 8881#L606-1 assume !(0 == ~T5_E~0); 8882#L611-1 assume !(0 == ~E_1~0); 8962#L616-1 assume !(0 == ~E_2~0); 8963#L621-1 assume !(0 == ~E_3~0); 8595#L626-1 assume !(0 == ~E_4~0); 8596#L631-1 assume !(0 == ~E_5~0); 8753#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8590#L279 assume !(1 == ~m_pc~0); 8592#L279-2 is_master_triggered_~__retres1~0#1 := 0; 8902#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8819#L291 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 8820#L720 assume !(0 != activate_threads_~tmp~1#1); 8901#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8757#L298 assume !(1 == ~t1_pc~0); 8548#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 8549#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8808#L310 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 8604#L728 assume !(0 != activate_threads_~tmp___0~0#1); 8605#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8724#L317 assume 1 == ~t2_pc~0; 8725#L318 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 8876#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8997#L329 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 8771#L736 assume !(0 != activate_threads_~tmp___1~0#1); 8772#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8954#L336 assume 1 == ~t3_pc~0; 8812#L337 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 8813#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8862#L348 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 8863#L744 assume !(0 != activate_threads_~tmp___2~0#1); 8910#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8960#L355 assume !(1 == ~t4_pc~0); 8839#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 8679#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8680#L367 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 8896#L752 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 8617#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8618#L374 assume 1 == ~t5_pc~0; 8979#L375 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 8748#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8817#L386 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8818#L760 assume !(0 != activate_threads_~tmp___4~0#1); 8865#L760-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8866#L649 assume !(1 == ~M_E~0); 9010#L649-2 assume !(1 == ~T1_E~0); 8579#L654-1 assume !(1 == ~T2_E~0); 8580#L659-1 assume !(1 == ~T3_E~0); 8765#L664-1 assume !(1 == ~T4_E~0); 8572#L669-1 assume !(1 == ~T5_E~0); 8573#L674-1 assume !(1 == ~E_1~0); 8947#L679-1 assume !(1 == ~E_2~0); 8668#L684-1 assume 1 == ~E_3~0;~E_3~0 := 2; 8669#L689-1 assume !(1 == ~E_4~0); 8834#L694-1 assume !(1 == ~E_5~0); 8832#L699-1 assume { :end_inline_reset_delta_events } true; 8833#L900-2 [2021-12-16 10:05:46,567 INFO L793 eck$LassoCheckResult]: Loop: 8833#L900-2 assume !false; 9080#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 9076#L561 assume !false; 9074#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 9061#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 9054#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 9049#L472 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 9046#L486 assume !(0 != eval_~tmp~0#1); 9016#L576 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 9005#L394-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 9006#L586-3 assume !(0 == ~M_E~0); 9007#L586-5 assume !(0 == ~T1_E~0); 9370#L591-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 9369#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 9368#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 9367#L606-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 9366#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 9365#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 9364#L621-3 assume !(0 == ~E_3~0); 9363#L626-3 assume !(0 == ~E_4~0); 9362#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 9361#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9360#L279-18 assume !(1 == ~m_pc~0); 9358#L279-20 is_master_triggered_~__retres1~0#1 := 0; 9357#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9356#L291-6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 8992#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8965#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8864#L298-18 assume !(1 == ~t1_pc~0); 8517#L298-20 is_transmit1_triggered_~__retres1~1#1 := 0; 8518#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8690#L310-6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 8714#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8715#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8842#L317-18 assume 1 == ~t2_pc~0; 8744#L318-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 8746#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8682#L329-6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 8683#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 9342#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9341#L336-18 assume 1 == ~t3_pc~0; 9339#L337-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 9338#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9337#L348-6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 9336#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9335#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9334#L355-18 assume !(1 == ~t4_pc~0); 9332#L355-20 is_transmit4_triggered_~__retres1~4#1 := 0; 9331#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8727#L367-6 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 8728#L752-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 8734#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8735#L374-18 assume 1 == ~t5_pc~0; 8958#L375-6 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 8799#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8800#L386-6 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8921#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 8903#L760-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8904#L649-3 assume !(1 == ~M_E~0); 8811#L649-5 assume !(1 == ~T1_E~0); 8793#L654-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 8647#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8648#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8554#L669-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 8555#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 8543#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8544#L684-3 assume 1 == ~E_3~0;~E_3~0 := 2; 8498#L689-3 assume !(1 == ~E_4~0); 8499#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 8538#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 8539#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 8541#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 8967#L472-1 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 8831#L919 assume !(0 == start_simulation_~tmp~3#1); 8557#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 8933#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 8532#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 9179#L472-2 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 9171#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 9148#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 9142#L882 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 9094#L932 assume !(0 != start_simulation_~tmp___0~1#1); 8833#L900-2 [2021-12-16 10:05:46,568 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:46,568 INFO L85 PathProgramCache]: Analyzing trace with hash 1053661891, now seen corresponding path program 1 times [2021-12-16 10:05:46,568 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:46,568 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [310270110] [2021-12-16 10:05:46,569 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:46,569 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:46,576 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:46,591 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:05:46,591 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:46,591 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [310270110] [2021-12-16 10:05:46,591 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [310270110] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:46,591 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:46,592 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:05:46,592 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1046473616] [2021-12-16 10:05:46,592 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:46,592 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:05:46,592 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:46,593 INFO L85 PathProgramCache]: Analyzing trace with hash -861276666, now seen corresponding path program 1 times [2021-12-16 10:05:46,593 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:46,593 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1392736920] [2021-12-16 10:05:46,593 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:46,593 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:46,599 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:46,615 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:05:46,616 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:46,616 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1392736920] [2021-12-16 10:05:46,616 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1392736920] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:46,616 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:46,616 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-16 10:05:46,616 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [984689062] [2021-12-16 10:05:46,617 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:46,617 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:05:46,617 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:05:46,617 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-16 10:05:46,618 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-16 10:05:46,618 INFO L87 Difference]: Start difference. First operand 875 states and 1289 transitions. cyclomatic complexity: 415 Second operand has 4 states, 4 states have (on average 17.75) internal successors, (71), 3 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:46,701 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:05:46,702 INFO L93 Difference]: Finished difference Result 2224 states and 3239 transitions. [2021-12-16 10:05:46,702 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-16 10:05:46,703 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2224 states and 3239 transitions. [2021-12-16 10:05:46,712 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2133 [2021-12-16 10:05:46,738 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2224 states to 2224 states and 3239 transitions. [2021-12-16 10:05:46,738 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2224 [2021-12-16 10:05:46,739 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2224 [2021-12-16 10:05:46,739 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2224 states and 3239 transitions. [2021-12-16 10:05:46,741 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:05:46,741 INFO L681 BuchiCegarLoop]: Abstraction has 2224 states and 3239 transitions. [2021-12-16 10:05:46,742 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2224 states and 3239 transitions. [2021-12-16 10:05:46,756 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2224 to 2154. [2021-12-16 10:05:46,759 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2154 states, 2154 states have (on average 1.4610027855153203) internal successors, (3147), 2153 states have internal predecessors, (3147), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:46,763 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2154 states to 2154 states and 3147 transitions. [2021-12-16 10:05:46,763 INFO L704 BuchiCegarLoop]: Abstraction has 2154 states and 3147 transitions. [2021-12-16 10:05:46,763 INFO L587 BuchiCegarLoop]: Abstraction has 2154 states and 3147 transitions. [2021-12-16 10:05:46,763 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2021-12-16 10:05:46,763 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2154 states and 3147 transitions. [2021-12-16 10:05:46,770 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2075 [2021-12-16 10:05:46,770 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:05:46,770 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:05:46,771 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:46,771 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:46,771 INFO L791 eck$LassoCheckResult]: Stem: 12214#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 12171#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 12155#L863 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 12153#L394 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12036#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 12037#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 11807#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 11808#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 12151#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 12152#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 12111#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 11777#L586 assume !(0 == ~M_E~0); 11778#L586-2 assume !(0 == ~T1_E~0); 11836#L591-1 assume !(0 == ~T2_E~0); 11977#L596-1 assume !(0 == ~T3_E~0); 11978#L601-1 assume !(0 == ~T4_E~0); 12025#L606-1 assume !(0 == ~T5_E~0); 12026#L611-1 assume !(0 == ~E_1~0); 12124#L616-1 assume !(0 == ~E_2~0); 12125#L621-1 assume !(0 == ~E_3~0); 11706#L626-1 assume !(0 == ~E_4~0); 11707#L631-1 assume !(0 == ~E_5~0); 11870#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11701#L279 assume !(1 == ~m_pc~0); 11703#L279-2 is_master_triggered_~__retres1~0#1 := 0; 12047#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11953#L291 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 11954#L720 assume !(0 != activate_threads_~tmp~1#1); 12046#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11877#L298 assume !(1 == ~t1_pc~0); 11659#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 11660#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11941#L310 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 11716#L728 assume !(0 != activate_threads_~tmp___0~0#1); 11717#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11843#L317 assume !(1 == ~t2_pc~0); 11844#L317-2 is_transmit2_triggered_~__retres1~2#1 := 0; 12066#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12165#L329 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 11886#L736 assume !(0 != activate_threads_~tmp___1~0#1); 11887#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12109#L336 assume 1 == ~t3_pc~0; 11946#L337 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 11947#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12007#L348 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 12008#L744 assume !(0 != activate_threads_~tmp___2~0#1); 12058#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12117#L355 assume !(1 == ~t4_pc~0); 11974#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 11793#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11794#L367 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 12040#L752 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 11728#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11729#L374 assume 1 == ~t5_pc~0; 12142#L375 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 11862#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11951#L386 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 11952#L760 assume !(0 != activate_threads_~tmp___4~0#1); 12010#L760-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12011#L649 assume !(1 == ~M_E~0); 12190#L649-2 assume !(1 == ~T1_E~0); 11690#L654-1 assume !(1 == ~T2_E~0); 11691#L659-1 assume !(1 == ~T3_E~0); 11885#L664-1 assume !(1 == ~T4_E~0); 11683#L669-1 assume !(1 == ~T5_E~0); 11684#L674-1 assume !(1 == ~E_1~0); 12103#L679-1 assume !(1 == ~E_2~0); 11782#L684-1 assume 1 == ~E_3~0;~E_3~0 := 2; 11783#L689-1 assume !(1 == ~E_4~0); 11969#L694-1 assume !(1 == ~E_5~0); 11967#L699-1 assume { :end_inline_reset_delta_events } true; 11968#L900-2 [2021-12-16 10:05:46,771 INFO L793 eck$LassoCheckResult]: Loop: 11968#L900-2 assume !false; 12641#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 12633#L561 assume !false; 12627#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 12580#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 12574#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 12572#L472 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 12569#L486 assume !(0 != eval_~tmp~0#1); 12567#L576 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 12565#L394-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 12563#L586-3 assume !(0 == ~M_E~0); 12561#L586-5 assume !(0 == ~T1_E~0); 12559#L591-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 12558#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 12555#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 12553#L606-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 12551#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 12549#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 12547#L621-3 assume !(0 == ~E_3~0); 12545#L626-3 assume !(0 == ~E_4~0); 12542#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 12505#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12500#L279-18 assume !(1 == ~m_pc~0); 12494#L279-20 is_master_triggered_~__retres1~0#1 := 0; 12434#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12431#L291-6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 12429#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12427#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12425#L298-18 assume !(1 == ~t1_pc~0); 12423#L298-20 is_transmit1_triggered_~__retres1~1#1 := 0; 12421#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12418#L310-6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 12416#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 12412#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12387#L317-18 assume !(1 == ~t2_pc~0); 12379#L317-20 is_transmit2_triggered_~__retres1~2#1 := 0; 12371#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12364#L329-6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 12361#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 12359#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12357#L336-18 assume 1 == ~t3_pc~0; 12354#L337-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 12351#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12349#L348-6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 12347#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 12338#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12333#L355-18 assume !(1 == ~t4_pc~0); 12326#L355-20 is_transmit4_triggered_~__retres1~4#1 := 0; 12321#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12315#L367-6 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 12310#L752-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 12305#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12303#L374-18 assume 1 == ~t5_pc~0; 12299#L375-6 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12297#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12294#L386-6 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 12292#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 12290#L760-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12287#L649-3 assume !(1 == ~M_E~0); 12284#L649-5 assume !(1 == ~T1_E~0); 12279#L654-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12277#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 12275#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12273#L669-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 12271#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 12269#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 12268#L684-3 assume 1 == ~E_3~0;~E_3~0 := 2; 12265#L689-3 assume !(1 == ~E_4~0); 12262#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 12263#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 12755#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 12748#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 12746#L472-1 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 12738#L919 assume !(0 == start_simulation_~tmp~3#1); 12736#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 12731#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 12725#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 12723#L472-2 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 12721#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 12719#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 12708#L882 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 12702#L932 assume !(0 != start_simulation_~tmp___0~1#1); 11968#L900-2 [2021-12-16 10:05:46,772 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:46,772 INFO L85 PathProgramCache]: Analyzing trace with hash -711154718, now seen corresponding path program 1 times [2021-12-16 10:05:46,772 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:46,772 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [548646594] [2021-12-16 10:05:46,772 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:46,773 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:46,777 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:46,788 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:05:46,788 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:46,788 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [548646594] [2021-12-16 10:05:46,789 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [548646594] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:46,789 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:46,789 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-16 10:05:46,789 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [183748037] [2021-12-16 10:05:46,789 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:46,789 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:05:46,790 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:46,790 INFO L85 PathProgramCache]: Analyzing trace with hash 571558053, now seen corresponding path program 1 times [2021-12-16 10:05:46,790 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:46,790 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [257472356] [2021-12-16 10:05:46,790 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:46,790 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:46,795 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:46,810 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:05:46,810 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:46,810 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [257472356] [2021-12-16 10:05:46,810 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [257472356] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:46,810 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:46,811 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-16 10:05:46,811 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1337169264] [2021-12-16 10:05:46,811 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:46,811 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:05:46,811 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:05:46,812 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-16 10:05:46,812 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-16 10:05:46,812 INFO L87 Difference]: Start difference. First operand 2154 states and 3147 transitions. cyclomatic complexity: 995 Second operand has 3 states, 3 states have (on average 23.666666666666668) internal successors, (71), 2 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:46,853 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:05:46,853 INFO L93 Difference]: Finished difference Result 3941 states and 5739 transitions. [2021-12-16 10:05:46,854 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-16 10:05:46,854 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3941 states and 5739 transitions. [2021-12-16 10:05:46,872 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3847 [2021-12-16 10:05:46,885 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3941 states to 3941 states and 5739 transitions. [2021-12-16 10:05:46,885 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3941 [2021-12-16 10:05:46,887 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3941 [2021-12-16 10:05:46,887 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3941 states and 5739 transitions. [2021-12-16 10:05:46,890 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:05:46,890 INFO L681 BuchiCegarLoop]: Abstraction has 3941 states and 5739 transitions. [2021-12-16 10:05:46,892 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3941 states and 5739 transitions. [2021-12-16 10:05:46,924 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3941 to 3929. [2021-12-16 10:05:46,929 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3929 states, 3929 states have (on average 1.4576228047849324) internal successors, (5727), 3928 states have internal predecessors, (5727), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:46,936 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3929 states to 3929 states and 5727 transitions. [2021-12-16 10:05:46,936 INFO L704 BuchiCegarLoop]: Abstraction has 3929 states and 5727 transitions. [2021-12-16 10:05:46,936 INFO L587 BuchiCegarLoop]: Abstraction has 3929 states and 5727 transitions. [2021-12-16 10:05:46,936 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2021-12-16 10:05:46,936 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3929 states and 5727 transitions. [2021-12-16 10:05:46,946 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3835 [2021-12-16 10:05:46,946 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:05:46,947 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:05:46,947 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:46,947 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:46,964 INFO L791 eck$LassoCheckResult]: Stem: 18273#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 18237#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 18226#L863 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 18224#L394 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 18117#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 18118#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 17908#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 17909#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 18222#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 18223#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 18187#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 17883#L586 assume !(0 == ~M_E~0); 17884#L586-2 assume !(0 == ~T1_E~0); 17936#L591-1 assume !(0 == ~T2_E~0); 18065#L596-1 assume !(0 == ~T3_E~0); 18066#L601-1 assume !(0 == ~T4_E~0); 18108#L606-1 assume !(0 == ~T5_E~0); 18109#L611-1 assume !(0 == ~E_1~0); 18194#L616-1 assume !(0 == ~E_2~0); 18195#L621-1 assume !(0 == ~E_3~0); 17810#L626-1 assume !(0 == ~E_4~0); 17811#L631-1 assume !(0 == ~E_5~0); 17971#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17805#L279 assume !(1 == ~m_pc~0); 17807#L279-2 is_master_triggered_~__retres1~0#1 := 0; 18128#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 18043#L291 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 18044#L720 assume !(0 != activate_threads_~tmp~1#1); 18127#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17977#L298 assume !(1 == ~t1_pc~0); 17763#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 17764#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18034#L310 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 17819#L728 assume !(0 != activate_threads_~tmp___0~0#1); 17820#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 17943#L317 assume !(1 == ~t2_pc~0); 17944#L317-2 is_transmit2_triggered_~__retres1~2#1 := 0; 18146#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 18233#L329 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 17991#L736 assume !(0 != activate_threads_~tmp___1~0#1); 17992#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18184#L336 assume !(1 == ~t3_pc~0); 18185#L336-2 is_transmit3_triggered_~__retres1~3#1 := 0; 18257#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18089#L348 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 18090#L744 assume !(0 != activate_threads_~tmp___2~0#1); 18136#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 18192#L355 assume !(1 == ~t4_pc~0); 18064#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 17896#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 17897#L367 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 18122#L752 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 17834#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 17835#L374 assume 1 == ~t5_pc~0; 18214#L375 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 17966#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 18041#L386 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 18042#L760 assume !(0 != activate_threads_~tmp___4~0#1); 18092#L760-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 18093#L649 assume !(1 == ~M_E~0); 18248#L649-2 assume !(1 == ~T1_E~0); 17794#L654-1 assume !(1 == ~T2_E~0); 17795#L659-1 assume !(1 == ~T3_E~0); 17985#L664-1 assume !(1 == ~T4_E~0); 17787#L669-1 assume !(1 == ~T5_E~0); 17788#L674-1 assume !(1 == ~E_1~0); 18179#L679-1 assume !(1 == ~E_2~0); 17885#L684-1 assume 1 == ~E_3~0;~E_3~0 := 2; 17886#L689-1 assume !(1 == ~E_4~0); 18058#L694-1 assume !(1 == ~E_5~0); 18056#L699-1 assume { :end_inline_reset_delta_events } true; 18057#L900-2 [2021-12-16 10:05:46,965 INFO L793 eck$LassoCheckResult]: Loop: 18057#L900-2 assume !false; 20157#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 20155#L561 assume !false; 20154#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 20152#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 20147#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 20143#L472 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 20140#L486 assume !(0 != eval_~tmp~0#1); 20138#L576 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 20136#L394-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 20133#L586-3 assume !(0 == ~M_E~0); 20131#L586-5 assume !(0 == ~T1_E~0); 20129#L591-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 20128#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 20127#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 20126#L606-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 20125#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 20124#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 20122#L621-3 assume !(0 == ~E_3~0); 20119#L626-3 assume !(0 == ~E_4~0); 20117#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 20115#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20113#L279-18 assume !(1 == ~m_pc~0); 20110#L279-20 is_master_triggered_~__retres1~0#1 := 0; 20108#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 20106#L291-6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 20104#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 20102#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 20100#L298-18 assume !(1 == ~t1_pc~0); 20098#L298-20 is_transmit1_triggered_~__retres1~1#1 := 0; 20096#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 20094#L310-6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 20092#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 20090#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 20088#L317-18 assume !(1 == ~t2_pc~0); 20086#L317-20 is_transmit2_triggered_~__retres1~2#1 := 0; 20084#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20083#L329-6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 20082#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 20081#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 20080#L336-18 assume !(1 == ~t3_pc~0); 20079#L336-20 is_transmit3_triggered_~__retres1~3#1 := 0; 20078#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 20077#L348-6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 20076#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 20075#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 20074#L355-18 assume !(1 == ~t4_pc~0); 20072#L355-20 is_transmit4_triggered_~__retres1~4#1 := 0; 20071#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 20070#L367-6 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 20069#L752-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 20068#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 20067#L374-18 assume 1 == ~t5_pc~0; 20065#L375-6 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 20064#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19602#L386-6 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 19597#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 19594#L760-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19592#L649-3 assume !(1 == ~M_E~0); 19591#L649-5 assume !(1 == ~T1_E~0); 20387#L654-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 20386#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 20385#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 20384#L669-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 20383#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 20382#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 20381#L684-3 assume 1 == ~E_3~0;~E_3~0 := 2; 20380#L689-3 assume !(1 == ~E_4~0); 20379#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 20378#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 20377#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 20371#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 20370#L472-1 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 20289#L919 assume !(0 == start_simulation_~tmp~3#1); 20287#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 20279#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 20273#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 20271#L472-2 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 20270#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 20269#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 20267#L882 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 20265#L932 assume !(0 != start_simulation_~tmp___0~1#1); 18057#L900-2 [2021-12-16 10:05:46,965 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:46,965 INFO L85 PathProgramCache]: Analyzing trace with hash -768298943, now seen corresponding path program 1 times [2021-12-16 10:05:46,966 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:46,966 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2100589862] [2021-12-16 10:05:46,966 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:46,966 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:46,971 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:46,989 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:05:46,990 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:46,990 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2100589862] [2021-12-16 10:05:46,990 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2100589862] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:46,990 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:46,990 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-16 10:05:46,990 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1423816714] [2021-12-16 10:05:46,990 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:46,991 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:05:46,991 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:46,991 INFO L85 PathProgramCache]: Analyzing trace with hash -1583956348, now seen corresponding path program 1 times [2021-12-16 10:05:46,991 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:46,991 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [687218581] [2021-12-16 10:05:46,992 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:46,992 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:46,997 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:47,013 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:05:47,013 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:47,014 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [687218581] [2021-12-16 10:05:47,014 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [687218581] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:47,014 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:47,014 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-16 10:05:47,014 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1364351878] [2021-12-16 10:05:47,014 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:47,015 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:05:47,015 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:05:47,015 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-16 10:05:47,015 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-16 10:05:47,015 INFO L87 Difference]: Start difference. First operand 3929 states and 5727 transitions. cyclomatic complexity: 1802 Second operand has 5 states, 5 states have (on average 14.2) internal successors, (71), 5 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:47,134 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:05:47,134 INFO L93 Difference]: Finished difference Result 9541 states and 14004 transitions. [2021-12-16 10:05:47,135 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-16 10:05:47,135 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9541 states and 14004 transitions. [2021-12-16 10:05:47,171 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 9364 [2021-12-16 10:05:47,204 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9541 states to 9541 states and 14004 transitions. [2021-12-16 10:05:47,205 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9541 [2021-12-16 10:05:47,212 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9541 [2021-12-16 10:05:47,212 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9541 states and 14004 transitions. [2021-12-16 10:05:47,220 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:05:47,221 INFO L681 BuchiCegarLoop]: Abstraction has 9541 states and 14004 transitions. [2021-12-16 10:05:47,225 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9541 states and 14004 transitions. [2021-12-16 10:05:47,298 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9541 to 4112. [2021-12-16 10:05:47,304 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4112 states, 4112 states have (on average 1.4372568093385214) internal successors, (5910), 4111 states have internal predecessors, (5910), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:47,311 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4112 states to 4112 states and 5910 transitions. [2021-12-16 10:05:47,311 INFO L704 BuchiCegarLoop]: Abstraction has 4112 states and 5910 transitions. [2021-12-16 10:05:47,312 INFO L587 BuchiCegarLoop]: Abstraction has 4112 states and 5910 transitions. [2021-12-16 10:05:47,312 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2021-12-16 10:05:47,312 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4112 states and 5910 transitions. [2021-12-16 10:05:47,323 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4015 [2021-12-16 10:05:47,323 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:05:47,323 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:05:47,324 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:47,324 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:47,324 INFO L791 eck$LassoCheckResult]: Stem: 31802#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 31756#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 31745#L863 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 31742#L394 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 31610#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 31611#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 31395#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 31396#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 31740#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 31741#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 31696#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 31367#L586 assume !(0 == ~M_E~0); 31368#L586-2 assume !(0 == ~T1_E~0); 31421#L591-1 assume !(0 == ~T2_E~0); 31555#L596-1 assume !(0 == ~T3_E~0); 31556#L601-1 assume !(0 == ~T4_E~0); 31600#L606-1 assume !(0 == ~T5_E~0); 31601#L611-1 assume !(0 == ~E_1~0); 31706#L616-1 assume !(0 == ~E_2~0); 31707#L621-1 assume !(0 == ~E_3~0); 31296#L626-1 assume !(0 == ~E_4~0); 31297#L631-1 assume !(0 == ~E_5~0); 31457#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 31291#L279 assume !(1 == ~m_pc~0); 31293#L279-2 is_master_triggered_~__retres1~0#1 := 0; 31622#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 31529#L291 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 31530#L720 assume !(0 != activate_threads_~tmp~1#1); 31621#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 31461#L298 assume !(1 == ~t1_pc~0); 31248#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 31249#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 31520#L310 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 31305#L728 assume !(0 != activate_threads_~tmp___0~0#1); 31306#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 31427#L317 assume !(1 == ~t2_pc~0); 31428#L317-2 is_transmit2_triggered_~__retres1~2#1 := 0; 31641#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 31749#L329 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 31469#L736 assume !(0 != activate_threads_~tmp___1~0#1); 31470#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 31693#L336 assume !(1 == ~t3_pc~0); 31694#L336-2 is_transmit3_triggered_~__retres1~3#1 := 0; 31782#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 31582#L348 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 31583#L744 assume !(0 != activate_threads_~tmp___2~0#1); 31631#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 31700#L355 assume !(1 == ~t4_pc~0); 31552#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 31381#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 31382#L367 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 31683#L752 assume !(0 != activate_threads_~tmp___3~0#1); 31315#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 31316#L374 assume 1 == ~t5_pc~0; 31734#L375 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 31447#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 31527#L386 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 31528#L760 assume !(0 != activate_threads_~tmp___4~0#1); 31585#L760-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 31586#L649 assume !(1 == ~M_E~0); 31768#L649-2 assume !(1 == ~T1_E~0); 31280#L654-1 assume !(1 == ~T2_E~0); 31281#L659-1 assume !(1 == ~T3_E~0); 31468#L664-1 assume !(1 == ~T4_E~0); 31273#L669-1 assume !(1 == ~T5_E~0); 31274#L674-1 assume !(1 == ~E_1~0); 31686#L679-1 assume !(1 == ~E_2~0); 31372#L684-1 assume 1 == ~E_3~0;~E_3~0 := 2; 31373#L689-1 assume !(1 == ~E_4~0); 31547#L694-1 assume !(1 == ~E_5~0); 31545#L699-1 assume { :end_inline_reset_delta_events } true; 31546#L900-2 [2021-12-16 10:05:47,324 INFO L793 eck$LassoCheckResult]: Loop: 31546#L900-2 assume !false; 33591#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 33583#L561 assume !false; 33577#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 33574#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 33568#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 33561#L472 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 33558#L486 assume !(0 != eval_~tmp~0#1); 33556#L576 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 33553#L394-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 33551#L586-3 assume !(0 == ~M_E~0); 33549#L586-5 assume !(0 == ~T1_E~0); 33547#L591-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 33545#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 33543#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 33541#L606-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 33539#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 33537#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 33535#L621-3 assume !(0 == ~E_3~0); 33533#L626-3 assume !(0 == ~E_4~0); 33531#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 33529#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 33528#L279-18 assume !(1 == ~m_pc~0); 33526#L279-20 is_master_triggered_~__retres1~0#1 := 0; 33525#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 33524#L291-6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 33523#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 33522#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 33521#L298-18 assume !(1 == ~t1_pc~0); 33520#L298-20 is_transmit1_triggered_~__retres1~1#1 := 0; 33519#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 33518#L310-6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 33517#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 33516#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 33515#L317-18 assume !(1 == ~t2_pc~0); 33514#L317-20 is_transmit2_triggered_~__retres1~2#1 := 0; 33513#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 33512#L329-6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 33511#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 33510#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 33509#L336-18 assume !(1 == ~t3_pc~0); 33508#L336-20 is_transmit3_triggered_~__retres1~3#1 := 0; 33507#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 33506#L348-6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 33505#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 33504#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 33503#L355-18 assume 1 == ~t4_pc~0; 33501#L356-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 33499#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 33497#L367-6 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 33495#L752-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 33493#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 33456#L374-18 assume 1 == ~t5_pc~0; 33453#L375-6 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 33450#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 33448#L386-6 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 33446#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 33444#L760-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 33442#L649-3 assume !(1 == ~M_E~0); 33441#L649-5 assume !(1 == ~T1_E~0); 33686#L654-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 33685#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 33684#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 33429#L669-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 33427#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 33424#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 33425#L684-3 assume 1 == ~E_3~0;~E_3~0 := 2; 33675#L689-3 assume !(1 == ~E_4~0); 33673#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 33408#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 33409#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 33390#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 33391#L472-1 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 33657#L919 assume !(0 == start_simulation_~tmp~3#1); 33653#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 33648#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 33643#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 33642#L472-2 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 33641#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 33624#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 33623#L882 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 33613#L932 assume !(0 != start_simulation_~tmp___0~1#1); 31546#L900-2 [2021-12-16 10:05:47,325 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:47,325 INFO L85 PathProgramCache]: Analyzing trace with hash -1585947393, now seen corresponding path program 1 times [2021-12-16 10:05:47,325 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:47,325 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2128676116] [2021-12-16 10:05:47,325 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:47,326 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:47,339 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:47,355 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:05:47,355 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:47,355 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2128676116] [2021-12-16 10:05:47,355 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2128676116] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:47,356 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:47,356 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:05:47,356 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [717515043] [2021-12-16 10:05:47,356 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:47,356 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:05:47,356 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:47,357 INFO L85 PathProgramCache]: Analyzing trace with hash 180860261, now seen corresponding path program 1 times [2021-12-16 10:05:47,357 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:47,357 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [768997208] [2021-12-16 10:05:47,357 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:47,357 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:47,362 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:47,373 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:05:47,373 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:47,373 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [768997208] [2021-12-16 10:05:47,373 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [768997208] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:47,374 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:47,374 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:05:47,374 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [360298703] [2021-12-16 10:05:47,374 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:47,374 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:05:47,374 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:05:47,375 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-16 10:05:47,375 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-16 10:05:47,375 INFO L87 Difference]: Start difference. First operand 4112 states and 5910 transitions. cyclomatic complexity: 1802 Second operand has 4 states, 4 states have (on average 17.75) internal successors, (71), 3 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:47,491 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:05:47,492 INFO L93 Difference]: Finished difference Result 11609 states and 16511 transitions. [2021-12-16 10:05:47,492 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-16 10:05:47,492 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 11609 states and 16511 transitions. [2021-12-16 10:05:47,532 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 11393 [2021-12-16 10:05:47,562 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 11609 states to 11609 states and 16511 transitions. [2021-12-16 10:05:47,562 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11609 [2021-12-16 10:05:47,569 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11609 [2021-12-16 10:05:47,570 INFO L73 IsDeterministic]: Start isDeterministic. Operand 11609 states and 16511 transitions. [2021-12-16 10:05:47,580 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:05:47,580 INFO L681 BuchiCegarLoop]: Abstraction has 11609 states and 16511 transitions. [2021-12-16 10:05:47,586 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11609 states and 16511 transitions. [2021-12-16 10:05:47,680 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11609 to 11505. [2021-12-16 10:05:47,696 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 11505 states, 11505 states have (on average 1.4232942199043894) internal successors, (16375), 11504 states have internal predecessors, (16375), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:47,714 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11505 states to 11505 states and 16375 transitions. [2021-12-16 10:05:47,714 INFO L704 BuchiCegarLoop]: Abstraction has 11505 states and 16375 transitions. [2021-12-16 10:05:47,714 INFO L587 BuchiCegarLoop]: Abstraction has 11505 states and 16375 transitions. [2021-12-16 10:05:47,714 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2021-12-16 10:05:47,714 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 11505 states and 16375 transitions. [2021-12-16 10:05:47,746 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 11369 [2021-12-16 10:05:47,747 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:05:47,747 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:05:47,747 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:47,747 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:47,748 INFO L791 eck$LassoCheckResult]: Stem: 47500#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 47467#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 47456#L863 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 47454#L394 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 47339#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 47340#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 47124#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 47125#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 47452#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 47453#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 47417#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 47096#L586 assume !(0 == ~M_E~0); 47097#L586-2 assume !(0 == ~T1_E~0); 47151#L591-1 assume !(0 == ~T2_E~0); 47285#L596-1 assume !(0 == ~T3_E~0); 47286#L601-1 assume !(0 == ~T4_E~0); 47330#L606-1 assume !(0 == ~T5_E~0); 47331#L611-1 assume !(0 == ~E_1~0); 47426#L616-1 assume !(0 == ~E_2~0); 47427#L621-1 assume !(0 == ~E_3~0); 47027#L626-1 assume !(0 == ~E_4~0); 47028#L631-1 assume !(0 == ~E_5~0); 47186#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 47022#L279 assume !(1 == ~m_pc~0); 47024#L279-2 is_master_triggered_~__retres1~0#1 := 0; 47350#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 47261#L291 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 47262#L720 assume !(0 != activate_threads_~tmp~1#1); 47349#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 47192#L298 assume !(1 == ~t1_pc~0); 46980#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 46981#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 47252#L310 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 47037#L728 assume !(0 != activate_threads_~tmp___0~0#1); 47038#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 47157#L317 assume !(1 == ~t2_pc~0); 47158#L317-2 is_transmit2_triggered_~__retres1~2#1 := 0; 47371#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 47461#L329 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 47201#L736 assume !(0 != activate_threads_~tmp___1~0#1); 47202#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 47414#L336 assume !(1 == ~t3_pc~0); 47415#L336-2 is_transmit3_triggered_~__retres1~3#1 := 0; 47485#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 47311#L348 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 47312#L744 assume !(0 != activate_threads_~tmp___2~0#1); 47360#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 47422#L355 assume !(1 == ~t4_pc~0); 47282#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 47421#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 47506#L367 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 47407#L752 assume !(0 != activate_threads_~tmp___3~0#1); 47048#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 47049#L374 assume !(1 == ~t5_pc~0); 47175#L374-2 is_transmit5_triggered_~__retres1~5#1 := 0; 47176#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 47259#L386 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 47260#L760 assume !(0 != activate_threads_~tmp___4~0#1); 47314#L760-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 47315#L649 assume !(1 == ~M_E~0); 47480#L649-2 assume !(1 == ~T1_E~0); 47011#L654-1 assume !(1 == ~T2_E~0); 47012#L659-1 assume !(1 == ~T3_E~0); 47200#L664-1 assume !(1 == ~T4_E~0); 47004#L669-1 assume !(1 == ~T5_E~0); 47005#L674-1 assume !(1 == ~E_1~0); 47409#L679-1 assume !(1 == ~E_2~0); 47101#L684-1 assume 1 == ~E_3~0;~E_3~0 := 2; 47102#L689-1 assume !(1 == ~E_4~0); 47278#L694-1 assume !(1 == ~E_5~0); 47276#L699-1 assume { :end_inline_reset_delta_events } true; 47277#L900-2 [2021-12-16 10:05:47,748 INFO L793 eck$LassoCheckResult]: Loop: 47277#L900-2 assume !false; 57921#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 57919#L561 assume !false; 57917#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 57508#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 57503#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 57502#L472 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 57498#L486 assume !(0 != eval_~tmp~0#1); 57499#L576 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 57942#L394-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 57940#L586-3 assume !(0 == ~M_E~0); 57938#L586-5 assume !(0 == ~T1_E~0); 57936#L591-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 57934#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 57932#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 57930#L606-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 57928#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 57927#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 57925#L621-3 assume !(0 == ~E_3~0); 57923#L626-3 assume !(0 == ~E_4~0); 57920#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 57918#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 57916#L279-18 assume !(1 == ~m_pc~0); 57914#L279-20 is_master_triggered_~__retres1~0#1 := 0; 57913#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 57912#L291-6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 57911#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 57910#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 57909#L298-18 assume !(1 == ~t1_pc~0); 57906#L298-20 is_transmit1_triggered_~__retres1~1#1 := 0; 57904#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 57902#L310-6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 57900#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 57898#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 57896#L317-18 assume !(1 == ~t2_pc~0); 57894#L317-20 is_transmit2_triggered_~__retres1~2#1 := 0; 57892#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 57890#L329-6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 57888#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 57886#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 57884#L336-18 assume !(1 == ~t3_pc~0); 57883#L336-20 is_transmit3_triggered_~__retres1~3#1 := 0; 57882#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 57881#L348-6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 57879#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 57878#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 57874#L355-18 assume !(1 == ~t4_pc~0); 57872#L355-20 is_transmit4_triggered_~__retres1~4#1 := 0; 57870#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 57868#L367-6 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 57866#L752-18 assume !(0 != activate_threads_~tmp___3~0#1); 57863#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 57861#L374-18 assume !(1 == ~t5_pc~0); 57859#L374-20 is_transmit5_triggered_~__retres1~5#1 := 0; 57857#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 57855#L386-6 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 57854#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 57853#L760-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 57852#L649-3 assume !(1 == ~M_E~0); 57195#L649-5 assume !(1 == ~T1_E~0); 57302#L654-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 57301#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 57300#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 57293#L669-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 57291#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 57289#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 57287#L684-3 assume 1 == ~E_3~0;~E_3~0 := 2; 57285#L689-3 assume !(1 == ~E_4~0); 57283#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 57281#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 57279#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 57271#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 57269#L472-1 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 57266#L919 assume !(0 == start_simulation_~tmp~3#1); 57267#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 57968#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 57962#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 57961#L472-2 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 57960#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 57959#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 57958#L882 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 57956#L932 assume !(0 != start_simulation_~tmp___0~1#1); 47277#L900-2 [2021-12-16 10:05:47,748 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:47,749 INFO L85 PathProgramCache]: Analyzing trace with hash -445595682, now seen corresponding path program 1 times [2021-12-16 10:05:47,749 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:47,749 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [430082799] [2021-12-16 10:05:47,749 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:47,749 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:47,754 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:47,815 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:05:47,815 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:47,815 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [430082799] [2021-12-16 10:05:47,816 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [430082799] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:47,816 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:47,816 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:05:47,816 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1780212913] [2021-12-16 10:05:47,816 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:47,816 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:05:47,816 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:47,816 INFO L85 PathProgramCache]: Analyzing trace with hash -1366340959, now seen corresponding path program 1 times [2021-12-16 10:05:47,816 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:47,816 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1993944579] [2021-12-16 10:05:47,816 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:47,817 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:47,822 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:47,846 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:05:47,846 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:47,846 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1993944579] [2021-12-16 10:05:47,846 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1993944579] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:47,846 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:47,846 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-16 10:05:47,846 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1250120488] [2021-12-16 10:05:47,846 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:47,847 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:05:47,847 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:05:47,847 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-16 10:05:47,847 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-16 10:05:47,847 INFO L87 Difference]: Start difference. First operand 11505 states and 16375 transitions. cyclomatic complexity: 4878 Second operand has 4 states, 4 states have (on average 17.75) internal successors, (71), 3 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:48,000 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:05:48,000 INFO L93 Difference]: Finished difference Result 16487 states and 23143 transitions. [2021-12-16 10:05:48,001 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-16 10:05:48,002 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 16487 states and 23143 transitions. [2021-12-16 10:05:48,134 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 16315 [2021-12-16 10:05:48,192 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 16487 states to 16487 states and 23143 transitions. [2021-12-16 10:05:48,193 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 16487 [2021-12-16 10:05:48,211 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 16487 [2021-12-16 10:05:48,211 INFO L73 IsDeterministic]: Start isDeterministic. Operand 16487 states and 23143 transitions. [2021-12-16 10:05:48,228 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:05:48,228 INFO L681 BuchiCegarLoop]: Abstraction has 16487 states and 23143 transitions. [2021-12-16 10:05:48,239 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16487 states and 23143 transitions. [2021-12-16 10:05:48,417 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16487 to 11505. [2021-12-16 10:05:48,445 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 11505 states, 11505 states have (on average 1.4092133854845719) internal successors, (16213), 11504 states have internal predecessors, (16213), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:48,464 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11505 states to 11505 states and 16213 transitions. [2021-12-16 10:05:48,464 INFO L704 BuchiCegarLoop]: Abstraction has 11505 states and 16213 transitions. [2021-12-16 10:05:48,464 INFO L587 BuchiCegarLoop]: Abstraction has 11505 states and 16213 transitions. [2021-12-16 10:05:48,464 INFO L425 BuchiCegarLoop]: ======== Iteration 13============ [2021-12-16 10:05:48,465 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 11505 states and 16213 transitions. [2021-12-16 10:05:48,498 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 11369 [2021-12-16 10:05:48,498 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:05:48,498 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:05:48,499 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:48,499 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:48,500 INFO L791 eck$LassoCheckResult]: Stem: 75518#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 75471#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 75460#L863 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 75458#L394 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 75341#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 75342#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 75125#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 75126#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 75456#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 75457#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 75420#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 75100#L586 assume !(0 == ~M_E~0); 75101#L586-2 assume !(0 == ~T1_E~0); 75152#L591-1 assume !(0 == ~T2_E~0); 75283#L596-1 assume !(0 == ~T3_E~0); 75284#L601-1 assume !(0 == ~T4_E~0); 75330#L606-1 assume !(0 == ~T5_E~0); 75331#L611-1 assume !(0 == ~E_1~0); 75428#L616-1 assume !(0 == ~E_2~0); 75429#L621-1 assume !(0 == ~E_3~0); 75029#L626-1 assume !(0 == ~E_4~0); 75030#L631-1 assume !(0 == ~E_5~0); 75184#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 75026#L279 assume !(1 == ~m_pc~0); 75028#L279-2 is_master_triggered_~__retres1~0#1 := 0; 75353#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 75259#L291 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 75260#L720 assume !(0 != activate_threads_~tmp~1#1); 75352#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 75190#L298 assume !(1 == ~t1_pc~0); 74984#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 74985#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 75250#L310 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 75039#L728 assume !(0 != activate_threads_~tmp___0~0#1); 75040#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 75157#L317 assume !(1 == ~t2_pc~0); 75158#L317-2 is_transmit2_triggered_~__retres1~2#1 := 0; 75372#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 75467#L329 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 75205#L736 assume !(0 != activate_threads_~tmp___1~0#1); 75206#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 75416#L336 assume !(1 == ~t3_pc~0); 75417#L336-2 is_transmit3_triggered_~__retres1~3#1 := 0; 75495#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 75311#L348 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 75312#L744 assume !(0 != activate_threads_~tmp___2~0#1); 75363#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 75425#L355 assume !(1 == ~t4_pc~0); 75282#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 75422#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 75521#L367 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 75410#L752 assume !(0 != activate_threads_~tmp___3~0#1); 75051#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 75052#L374 assume !(1 == ~t5_pc~0); 75177#L374-2 is_transmit5_triggered_~__retres1~5#1 := 0; 75178#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 75257#L386 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 75258#L760 assume !(0 != activate_threads_~tmp___4~0#1); 75314#L760-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 75315#L649 assume !(1 == ~M_E~0); 75487#L649-2 assume !(1 == ~T1_E~0); 75013#L654-1 assume !(1 == ~T2_E~0); 75014#L659-1 assume !(1 == ~T3_E~0); 75198#L664-1 assume !(1 == ~T4_E~0); 75006#L669-1 assume !(1 == ~T5_E~0); 75007#L674-1 assume !(1 == ~E_1~0); 75411#L679-1 assume !(1 == ~E_2~0); 75102#L684-1 assume !(1 == ~E_3~0); 75103#L689-1 assume !(1 == ~E_4~0); 75277#L694-1 assume !(1 == ~E_5~0); 75275#L699-1 assume { :end_inline_reset_delta_events } true; 75276#L900-2 [2021-12-16 10:05:48,500 INFO L793 eck$LassoCheckResult]: Loop: 75276#L900-2 assume !false; 80589#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 80585#L561 assume !false; 80582#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 80464#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 80456#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 80454#L472 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 80443#L486 assume !(0 != eval_~tmp~0#1); 80437#L576 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 80434#L394-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 80414#L586-3 assume !(0 == ~M_E~0); 79867#L586-5 assume !(0 == ~T1_E~0); 79829#L591-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 79827#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 79824#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 79820#L606-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 79817#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 79811#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 79805#L621-3 assume !(0 == ~E_3~0); 79800#L626-3 assume !(0 == ~E_4~0); 79795#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 79789#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 79782#L279-18 assume !(1 == ~m_pc~0); 79776#L279-20 is_master_triggered_~__retres1~0#1 := 0; 79769#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 79763#L291-6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 79756#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 79748#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 79742#L298-18 assume !(1 == ~t1_pc~0); 79735#L298-20 is_transmit1_triggered_~__retres1~1#1 := 0; 79729#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 79723#L310-6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 79716#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 79710#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 79702#L317-18 assume !(1 == ~t2_pc~0); 79694#L317-20 is_transmit2_triggered_~__retres1~2#1 := 0; 79686#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 79678#L329-6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 79671#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 79665#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 79630#L336-18 assume !(1 == ~t3_pc~0); 79621#L336-20 is_transmit3_triggered_~__retres1~3#1 := 0; 79613#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 79603#L348-6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 79597#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 79592#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 79591#L355-18 assume 1 == ~t4_pc~0; 79589#L356-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 79587#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 79585#L367-6 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 79553#L752-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 79549#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 79534#L374-18 assume !(1 == ~t5_pc~0); 79516#L374-20 is_transmit5_triggered_~__retres1~5#1 := 0; 79506#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 79484#L386-6 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 79344#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 79337#L760-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 79332#L649-3 assume !(1 == ~M_E~0); 78410#L649-5 assume !(1 == ~T1_E~0); 79284#L654-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 79269#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 79247#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 79232#L669-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 79198#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 79107#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 79086#L684-3 assume !(1 == ~E_3~0); 79082#L689-3 assume !(1 == ~E_4~0); 79078#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 79074#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 78910#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 78889#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 78837#L472-1 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 78642#L919 assume !(0 == start_simulation_~tmp~3#1); 78643#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 80651#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 80645#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 80643#L472-2 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 80642#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 80638#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 80636#L882 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 80634#L932 assume !(0 != start_simulation_~tmp___0~1#1); 75276#L900-2 [2021-12-16 10:05:48,500 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:48,500 INFO L85 PathProgramCache]: Analyzing trace with hash -445536100, now seen corresponding path program 1 times [2021-12-16 10:05:48,501 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:48,501 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [627907911] [2021-12-16 10:05:48,501 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:48,501 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:48,510 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:05:48,511 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-16 10:05:48,573 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:05:48,595 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-16 10:05:48,596 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:48,596 INFO L85 PathProgramCache]: Analyzing trace with hash -897352318, now seen corresponding path program 1 times [2021-12-16 10:05:48,596 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:48,596 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1936691725] [2021-12-16 10:05:48,596 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:48,597 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:48,602 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:48,613 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:05:48,613 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:48,613 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1936691725] [2021-12-16 10:05:48,613 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1936691725] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:48,614 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:48,614 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:05:48,614 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1505071735] [2021-12-16 10:05:48,614 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:48,614 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:05:48,615 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:05:48,615 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-16 10:05:48,615 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-16 10:05:48,616 INFO L87 Difference]: Start difference. First operand 11505 states and 16213 transitions. cyclomatic complexity: 4716 Second operand has 3 states, 3 states have (on average 27.333333333333332) internal successors, (82), 3 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:48,716 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:05:48,716 INFO L93 Difference]: Finished difference Result 20121 states and 28122 transitions. [2021-12-16 10:05:48,716 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-16 10:05:48,717 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 20121 states and 28122 transitions. [2021-12-16 10:05:48,799 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 19875 [2021-12-16 10:05:48,875 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 20121 states to 20121 states and 28122 transitions. [2021-12-16 10:05:48,876 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 20121 [2021-12-16 10:05:48,900 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 20121 [2021-12-16 10:05:48,900 INFO L73 IsDeterministic]: Start isDeterministic. Operand 20121 states and 28122 transitions. [2021-12-16 10:05:48,926 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:05:48,927 INFO L681 BuchiCegarLoop]: Abstraction has 20121 states and 28122 transitions. [2021-12-16 10:05:48,944 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 20121 states and 28122 transitions. [2021-12-16 10:05:49,272 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 20121 to 20103. [2021-12-16 10:05:49,297 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 20103 states, 20103 states have (on average 1.398000298462916) internal successors, (28104), 20102 states have internal predecessors, (28104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:49,330 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20103 states to 20103 states and 28104 transitions. [2021-12-16 10:05:49,330 INFO L704 BuchiCegarLoop]: Abstraction has 20103 states and 28104 transitions. [2021-12-16 10:05:49,330 INFO L587 BuchiCegarLoop]: Abstraction has 20103 states and 28104 transitions. [2021-12-16 10:05:49,330 INFO L425 BuchiCegarLoop]: ======== Iteration 14============ [2021-12-16 10:05:49,331 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 20103 states and 28104 transitions. [2021-12-16 10:05:49,385 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 19857 [2021-12-16 10:05:49,386 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:05:49,386 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:05:49,387 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:49,387 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:49,387 INFO L791 eck$LassoCheckResult]: Stem: 107198#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 107141#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 107129#L863 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 107124#L394 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 106989#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 106990#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 106762#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 106763#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 107122#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 107123#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 107079#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 106736#L586 assume !(0 == ~M_E~0); 106737#L586-2 assume !(0 == ~T1_E~0); 106791#L591-1 assume !(0 == ~T2_E~0); 106929#L596-1 assume !(0 == ~T3_E~0); 106930#L601-1 assume !(0 == ~T4_E~0); 106979#L606-1 assume !(0 == ~T5_E~0); 106980#L611-1 assume !(0 == ~E_1~0); 107093#L616-1 assume !(0 == ~E_2~0); 107094#L621-1 assume !(0 == ~E_3~0); 106662#L626-1 assume 0 == ~E_4~0;~E_4~0 := 1; 106663#L631-1 assume !(0 == ~E_5~0); 107053#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 106657#L279 assume !(1 == ~m_pc~0); 106659#L279-2 is_master_triggered_~__retres1~0#1 := 0; 107110#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 107111#L291 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 107003#L720 assume !(0 != activate_threads_~tmp~1#1); 107004#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 107195#L298 assume !(1 == ~t1_pc~0); 106618#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 106619#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 106892#L310 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 106893#L728 assume !(0 != activate_threads_~tmp___0~0#1); 107222#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 107221#L317 assume !(1 == ~t2_pc~0); 107028#L317-2 is_transmit2_triggered_~__retres1~2#1 := 0; 107029#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 107217#L329 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 106849#L736 assume !(0 != activate_threads_~tmp___1~0#1); 106850#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 107076#L336 assume !(1 == ~t3_pc~0); 107077#L336-2 is_transmit3_triggered_~__retres1~3#1 := 0; 107214#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 107213#L348 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 107016#L744 assume !(0 != activate_threads_~tmp___2~0#1); 107017#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 107138#L355 assume !(1 == ~t4_pc~0); 107083#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 107084#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 107223#L367 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 107068#L752 assume !(0 != activate_threads_~tmp___3~0#1); 106687#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 106688#L374 assume !(1 == ~t5_pc~0); 107215#L374-2 is_transmit5_triggered_~__retres1~5#1 := 0; 107125#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 107126#L386 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 107157#L760 assume !(0 != activate_threads_~tmp___4~0#1); 107158#L760-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 107160#L649 assume !(1 == ~M_E~0); 107161#L649-2 assume !(1 == ~T1_E~0); 106646#L654-1 assume !(1 == ~T2_E~0); 106647#L659-1 assume !(1 == ~T3_E~0); 107208#L664-1 assume !(1 == ~T4_E~0); 107207#L669-1 assume !(1 == ~T5_E~0); 107206#L674-1 assume !(1 == ~E_1~0); 107205#L679-1 assume !(1 == ~E_2~0); 107204#L684-1 assume !(1 == ~E_3~0); 106923#L689-1 assume 1 == ~E_4~0;~E_4~0 := 2; 106924#L694-1 assume !(1 == ~E_5~0); 106921#L699-1 assume { :end_inline_reset_delta_events } true; 106922#L900-2 [2021-12-16 10:05:49,387 INFO L793 eck$LassoCheckResult]: Loop: 106922#L900-2 assume !false; 117366#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 117364#L561 assume !false; 117361#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 117356#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 117350#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 117348#L472 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 117344#L486 assume !(0 != eval_~tmp~0#1); 117346#L576 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 121755#L394-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 121753#L586-3 assume !(0 == ~M_E~0); 121751#L586-5 assume !(0 == ~T1_E~0); 121749#L591-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 121747#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 121745#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 121743#L606-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 121741#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 121739#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 121738#L621-3 assume !(0 == ~E_3~0); 121736#L626-3 assume 0 == ~E_4~0;~E_4~0 := 1; 121733#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 121730#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 121728#L279-18 assume !(1 == ~m_pc~0); 121725#L279-20 is_master_triggered_~__retres1~0#1 := 0; 121723#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 121721#L291-6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 121719#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 121717#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 121715#L298-18 assume !(1 == ~t1_pc~0); 121713#L298-20 is_transmit1_triggered_~__retres1~1#1 := 0; 121711#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 121709#L310-6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 121707#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 121705#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 121703#L317-18 assume !(1 == ~t2_pc~0); 121701#L317-20 is_transmit2_triggered_~__retres1~2#1 := 0; 121699#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 121697#L329-6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 121695#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 121693#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 121691#L336-18 assume !(1 == ~t3_pc~0); 121689#L336-20 is_transmit3_triggered_~__retres1~3#1 := 0; 121687#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 121685#L348-6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 121683#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 121682#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 121677#L355-18 assume !(1 == ~t4_pc~0); 121675#L355-20 is_transmit4_triggered_~__retres1~4#1 := 0; 121673#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 121671#L367-6 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 121669#L752-18 assume !(0 != activate_threads_~tmp___3~0#1); 121666#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 121664#L374-18 assume !(1 == ~t5_pc~0); 121662#L374-20 is_transmit5_triggered_~__retres1~5#1 := 0; 121660#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 121658#L386-6 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 121656#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 121654#L760-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 121652#L649-3 assume !(1 == ~M_E~0); 110715#L649-5 assume !(1 == ~T1_E~0); 121650#L654-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 121648#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 121646#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 121644#L669-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 121642#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 121640#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 121638#L684-3 assume !(1 == ~E_3~0); 121637#L689-3 assume 1 == ~E_4~0;~E_4~0 := 2; 121635#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 121634#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 121633#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 121627#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 121626#L472-1 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 121585#L919 assume !(0 == start_simulation_~tmp~3#1); 121583#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 121578#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 121570#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 121568#L472-2 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 121566#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 121564#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 121562#L882 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 121560#L932 assume !(0 != start_simulation_~tmp___0~1#1); 106922#L900-2 [2021-12-16 10:05:49,388 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:49,388 INFO L85 PathProgramCache]: Analyzing trace with hash 1583048088, now seen corresponding path program 1 times [2021-12-16 10:05:49,388 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:49,388 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1563080187] [2021-12-16 10:05:49,388 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:49,389 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:49,399 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:49,411 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:05:49,411 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:49,411 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1563080187] [2021-12-16 10:05:49,411 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1563080187] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:49,412 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:49,412 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-16 10:05:49,412 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1413908923] [2021-12-16 10:05:49,412 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:49,414 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:05:49,414 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:49,414 INFO L85 PathProgramCache]: Analyzing trace with hash -690149029, now seen corresponding path program 1 times [2021-12-16 10:05:49,414 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:49,414 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [887957219] [2021-12-16 10:05:49,414 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:49,415 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:49,420 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:49,435 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:05:49,435 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:49,435 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [887957219] [2021-12-16 10:05:49,435 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [887957219] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:49,435 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:49,436 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-16 10:05:49,436 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2082056777] [2021-12-16 10:05:49,436 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:49,436 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:05:49,436 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:05:49,437 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-16 10:05:49,437 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-16 10:05:49,437 INFO L87 Difference]: Start difference. First operand 20103 states and 28104 transitions. cyclomatic complexity: 8009 Second operand has 3 states, 3 states have (on average 23.666666666666668) internal successors, (71), 2 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:49,622 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:05:49,624 INFO L93 Difference]: Finished difference Result 11040 states and 15310 transitions. [2021-12-16 10:05:49,625 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-16 10:05:49,625 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 11040 states and 15310 transitions. [2021-12-16 10:05:49,654 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 10907 [2021-12-16 10:05:49,675 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 11040 states to 11040 states and 15310 transitions. [2021-12-16 10:05:49,676 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11040 [2021-12-16 10:05:49,682 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11040 [2021-12-16 10:05:49,682 INFO L73 IsDeterministic]: Start isDeterministic. Operand 11040 states and 15310 transitions. [2021-12-16 10:05:49,690 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:05:49,691 INFO L681 BuchiCegarLoop]: Abstraction has 11040 states and 15310 transitions. [2021-12-16 10:05:49,695 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11040 states and 15310 transitions. [2021-12-16 10:05:49,766 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11040 to 11040. [2021-12-16 10:05:49,777 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 11040 states, 11040 states have (on average 1.3867753623188406) internal successors, (15310), 11039 states have internal predecessors, (15310), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:49,792 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11040 states to 11040 states and 15310 transitions. [2021-12-16 10:05:49,793 INFO L704 BuchiCegarLoop]: Abstraction has 11040 states and 15310 transitions. [2021-12-16 10:05:49,793 INFO L587 BuchiCegarLoop]: Abstraction has 11040 states and 15310 transitions. [2021-12-16 10:05:49,793 INFO L425 BuchiCegarLoop]: ======== Iteration 15============ [2021-12-16 10:05:49,793 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 11040 states and 15310 transitions. [2021-12-16 10:05:49,894 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 10907 [2021-12-16 10:05:49,895 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:05:49,895 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:05:49,895 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:49,896 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:49,896 INFO L791 eck$LassoCheckResult]: Stem: 138279#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 138244#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 138231#L863 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 138229#L394 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 138118#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 138119#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 137907#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 137908#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 138227#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 138228#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 138192#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 137882#L586 assume !(0 == ~M_E~0); 137883#L586-2 assume !(0 == ~T1_E~0); 137934#L591-1 assume !(0 == ~T2_E~0); 138065#L596-1 assume !(0 == ~T3_E~0); 138066#L601-1 assume !(0 == ~T4_E~0); 138109#L606-1 assume !(0 == ~T5_E~0); 138110#L611-1 assume !(0 == ~E_1~0); 138200#L616-1 assume !(0 == ~E_2~0); 138201#L621-1 assume !(0 == ~E_3~0); 137813#L626-1 assume !(0 == ~E_4~0); 137814#L631-1 assume !(0 == ~E_5~0); 137969#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 137810#L279 assume !(1 == ~m_pc~0); 137812#L279-2 is_master_triggered_~__retres1~0#1 := 0; 138129#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 138041#L291 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 138042#L720 assume !(0 != activate_threads_~tmp~1#1); 138128#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 137975#L298 assume !(1 == ~t1_pc~0); 137768#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 137769#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 138033#L310 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 137822#L728 assume !(0 != activate_threads_~tmp___0~0#1); 137823#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 137939#L317 assume !(1 == ~t2_pc~0); 137940#L317-2 is_transmit2_triggered_~__retres1~2#1 := 0; 138148#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 138241#L329 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 137991#L736 assume !(0 != activate_threads_~tmp___1~0#1); 137992#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 138187#L336 assume !(1 == ~t3_pc~0); 138188#L336-2 is_transmit3_triggered_~__retres1~3#1 := 0; 138262#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 138089#L348 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 138090#L744 assume !(0 != activate_threads_~tmp___2~0#1); 138138#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 138195#L355 assume !(1 == ~t4_pc~0); 138064#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 137895#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 137896#L367 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 138123#L752 assume !(0 != activate_threads_~tmp___3~0#1); 137835#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 137836#L374 assume !(1 == ~t5_pc~0); 137961#L374-2 is_transmit5_triggered_~__retres1~5#1 := 0; 137962#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 138039#L386 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 138040#L760 assume !(0 != activate_threads_~tmp___4~0#1); 138092#L760-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 138093#L649 assume !(1 == ~M_E~0); 138254#L649-2 assume !(1 == ~T1_E~0); 137797#L654-1 assume !(1 == ~T2_E~0); 137798#L659-1 assume !(1 == ~T3_E~0); 137984#L664-1 assume !(1 == ~T4_E~0); 137790#L669-1 assume !(1 == ~T5_E~0); 137791#L674-1 assume !(1 == ~E_1~0); 138181#L679-1 assume !(1 == ~E_2~0); 137884#L684-1 assume !(1 == ~E_3~0); 137885#L689-1 assume !(1 == ~E_4~0); 138059#L694-1 assume !(1 == ~E_5~0); 138057#L699-1 assume { :end_inline_reset_delta_events } true; 138058#L900-2 [2021-12-16 10:05:49,896 INFO L793 eck$LassoCheckResult]: Loop: 138058#L900-2 assume !false; 143446#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 143445#L561 assume !false; 143444#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 143441#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 143435#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 143432#L472 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 143429#L486 assume !(0 != eval_~tmp~0#1); 143427#L576 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 143425#L394-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 143423#L586-3 assume !(0 == ~M_E~0); 143421#L586-5 assume !(0 == ~T1_E~0); 143419#L591-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 143417#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 143415#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 143413#L606-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 143411#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 143409#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 143407#L621-3 assume !(0 == ~E_3~0); 143405#L626-3 assume !(0 == ~E_4~0); 143403#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 143401#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 143399#L279-18 assume !(1 == ~m_pc~0); 143396#L279-20 is_master_triggered_~__retres1~0#1 := 0; 143394#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 143392#L291-6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 143390#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 143388#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 143386#L298-18 assume !(1 == ~t1_pc~0); 143383#L298-20 is_transmit1_triggered_~__retres1~1#1 := 0; 143381#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 143379#L310-6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 143377#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 143375#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 143373#L317-18 assume !(1 == ~t2_pc~0); 143371#L317-20 is_transmit2_triggered_~__retres1~2#1 := 0; 143369#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 143367#L329-6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 143365#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 143363#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 143361#L336-18 assume !(1 == ~t3_pc~0); 143360#L336-20 is_transmit3_triggered_~__retres1~3#1 := 0; 143359#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 143358#L348-6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 143357#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 143356#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 143354#L355-18 assume !(1 == ~t4_pc~0); 143353#L355-20 is_transmit4_triggered_~__retres1~4#1 := 0; 143352#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 143351#L367-6 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 143350#L752-18 assume !(0 != activate_threads_~tmp___3~0#1); 143349#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 143348#L374-18 assume !(1 == ~t5_pc~0); 143347#L374-20 is_transmit5_triggered_~__retres1~5#1 := 0; 143346#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 143345#L386-6 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 143344#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 143342#L760-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 143340#L649-3 assume !(1 == ~M_E~0); 143236#L649-5 assume !(1 == ~T1_E~0); 143337#L654-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 143335#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 143333#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 143331#L669-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 143329#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 143327#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 143325#L684-3 assume !(1 == ~E_3~0); 143323#L689-3 assume !(1 == ~E_4~0); 143321#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 143319#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 143317#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 143309#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 143307#L472-1 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 143304#L919 assume !(0 == start_simulation_~tmp~3#1); 143305#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 148189#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 148183#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 143556#L472-2 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 143555#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 143554#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 143553#L882 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 143552#L932 assume !(0 != start_simulation_~tmp___0~1#1); 138058#L900-2 [2021-12-16 10:05:49,896 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:49,897 INFO L85 PathProgramCache]: Analyzing trace with hash -445536100, now seen corresponding path program 2 times [2021-12-16 10:05:49,897 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:49,897 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1649271275] [2021-12-16 10:05:49,897 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:49,897 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:49,902 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:05:49,902 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-16 10:05:49,905 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:05:49,914 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-16 10:05:49,915 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:49,915 INFO L85 PathProgramCache]: Analyzing trace with hash 1907557983, now seen corresponding path program 1 times [2021-12-16 10:05:49,915 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:49,915 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [797919769] [2021-12-16 10:05:49,915 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:49,915 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:49,920 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:49,935 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:05:49,935 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:49,935 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [797919769] [2021-12-16 10:05:49,935 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [797919769] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:49,936 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:49,936 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-16 10:05:49,936 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [475159518] [2021-12-16 10:05:49,936 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:49,936 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:05:49,936 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:05:49,937 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-16 10:05:49,937 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-16 10:05:49,937 INFO L87 Difference]: Start difference. First operand 11040 states and 15310 transitions. cyclomatic complexity: 4278 Second operand has 5 states, 5 states have (on average 16.4) internal successors, (82), 5 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:50,033 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:05:50,034 INFO L93 Difference]: Finished difference Result 19429 states and 26497 transitions. [2021-12-16 10:05:50,034 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2021-12-16 10:05:50,035 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 19429 states and 26497 transitions. [2021-12-16 10:05:50,111 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 19236 [2021-12-16 10:05:50,247 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 19429 states to 19429 states and 26497 transitions. [2021-12-16 10:05:50,247 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 19429 [2021-12-16 10:05:50,267 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 19429 [2021-12-16 10:05:50,267 INFO L73 IsDeterministic]: Start isDeterministic. Operand 19429 states and 26497 transitions. [2021-12-16 10:05:50,283 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:05:50,283 INFO L681 BuchiCegarLoop]: Abstraction has 19429 states and 26497 transitions. [2021-12-16 10:05:50,290 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19429 states and 26497 transitions. [2021-12-16 10:05:50,434 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19429 to 11148. [2021-12-16 10:05:50,448 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 11148 states, 11148 states have (on average 1.3830283458916397) internal successors, (15418), 11147 states have internal predecessors, (15418), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:50,466 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11148 states to 11148 states and 15418 transitions. [2021-12-16 10:05:50,466 INFO L704 BuchiCegarLoop]: Abstraction has 11148 states and 15418 transitions. [2021-12-16 10:05:50,466 INFO L587 BuchiCegarLoop]: Abstraction has 11148 states and 15418 transitions. [2021-12-16 10:05:50,466 INFO L425 BuchiCegarLoop]: ======== Iteration 16============ [2021-12-16 10:05:50,467 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 11148 states and 15418 transitions. [2021-12-16 10:05:50,497 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 11015 [2021-12-16 10:05:50,498 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:05:50,498 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:05:50,501 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:50,501 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:50,501 INFO L791 eck$LassoCheckResult]: Stem: 168783#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 168744#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 168731#L863 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 168729#L394 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 168616#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 168617#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 168397#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 168398#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 168727#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 168728#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 168694#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 168372#L586 assume !(0 == ~M_E~0); 168373#L586-2 assume !(0 == ~T1_E~0); 168424#L591-1 assume !(0 == ~T2_E~0); 168563#L596-1 assume !(0 == ~T3_E~0); 168564#L601-1 assume !(0 == ~T4_E~0); 168606#L606-1 assume !(0 == ~T5_E~0); 168607#L611-1 assume !(0 == ~E_1~0); 168700#L616-1 assume !(0 == ~E_2~0); 168701#L621-1 assume !(0 == ~E_3~0); 168301#L626-1 assume !(0 == ~E_4~0); 168302#L631-1 assume !(0 == ~E_5~0); 168459#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 168296#L279 assume !(1 == ~m_pc~0); 168298#L279-2 is_master_triggered_~__retres1~0#1 := 0; 168629#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 168539#L291 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 168540#L720 assume !(0 != activate_threads_~tmp~1#1); 168628#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 168465#L298 assume !(1 == ~t1_pc~0); 168254#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 168255#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 168530#L310 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 168311#L728 assume !(0 != activate_threads_~tmp___0~0#1); 168312#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 168430#L317 assume !(1 == ~t2_pc~0); 168431#L317-2 is_transmit2_triggered_~__retres1~2#1 := 0; 168648#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 168738#L329 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 168480#L736 assume !(0 != activate_threads_~tmp___1~0#1); 168481#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 168691#L336 assume !(1 == ~t3_pc~0); 168692#L336-2 is_transmit3_triggered_~__retres1~3#1 := 0; 168762#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 168588#L348 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 168589#L744 assume !(0 != activate_threads_~tmp___2~0#1); 168637#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 168698#L355 assume !(1 == ~t4_pc~0); 168562#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 168385#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 168386#L367 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 168621#L752 assume !(0 != activate_threads_~tmp___3~0#1); 168325#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 168326#L374 assume !(1 == ~t5_pc~0); 168451#L374-2 is_transmit5_triggered_~__retres1~5#1 := 0; 168452#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 168537#L386 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 168538#L760 assume !(0 != activate_threads_~tmp___4~0#1); 168591#L760-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 168592#L649 assume !(1 == ~M_E~0); 168758#L649-2 assume !(1 == ~T1_E~0); 168284#L654-1 assume !(1 == ~T2_E~0); 168285#L659-1 assume !(1 == ~T3_E~0); 168473#L664-1 assume !(1 == ~T4_E~0); 168277#L669-1 assume !(1 == ~T5_E~0); 168278#L674-1 assume !(1 == ~E_1~0); 168685#L679-1 assume !(1 == ~E_2~0); 168374#L684-1 assume !(1 == ~E_3~0); 168375#L689-1 assume !(1 == ~E_4~0); 168556#L694-1 assume !(1 == ~E_5~0); 168554#L699-1 assume { :end_inline_reset_delta_events } true; 168555#L900-2 [2021-12-16 10:05:50,502 INFO L793 eck$LassoCheckResult]: Loop: 168555#L900-2 assume !false; 175442#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 174914#L561 assume !false; 174905#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 174904#L439 assume !(0 == ~m_st~0); 174903#L443 assume !(0 == ~t1_st~0); 174902#L447 assume !(0 == ~t2_st~0); 174901#L451 assume !(0 == ~t3_st~0); 174900#L455 assume !(0 == ~t4_st~0); 174898#L459 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6#1 := 0; 174897#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 174896#L472 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 174895#L486 assume !(0 != eval_~tmp~0#1); 174894#L576 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 174893#L394-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 174892#L586-3 assume !(0 == ~M_E~0); 174891#L586-5 assume !(0 == ~T1_E~0); 174890#L591-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 174889#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 174888#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 174887#L606-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 174886#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 174885#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 174884#L621-3 assume !(0 == ~E_3~0); 174883#L626-3 assume !(0 == ~E_4~0); 174882#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 174881#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 174880#L279-18 assume !(1 == ~m_pc~0); 174878#L279-20 is_master_triggered_~__retres1~0#1 := 0; 174877#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 174876#L291-6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 174875#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 174874#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 174873#L298-18 assume !(1 == ~t1_pc~0); 174872#L298-20 is_transmit1_triggered_~__retres1~1#1 := 0; 174871#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 174870#L310-6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 174869#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 174868#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 174867#L317-18 assume !(1 == ~t2_pc~0); 174866#L317-20 is_transmit2_triggered_~__retres1~2#1 := 0; 174865#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 174864#L329-6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 174863#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 174862#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 174861#L336-18 assume !(1 == ~t3_pc~0); 174860#L336-20 is_transmit3_triggered_~__retres1~3#1 := 0; 174859#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 174858#L348-6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 174857#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 174856#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 174854#L355-18 assume !(1 == ~t4_pc~0); 174853#L355-20 is_transmit4_triggered_~__retres1~4#1 := 0; 174852#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 174851#L367-6 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 174850#L752-18 assume !(0 != activate_threads_~tmp___3~0#1); 174849#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 174848#L374-18 assume !(1 == ~t5_pc~0); 174847#L374-20 is_transmit5_triggered_~__retres1~5#1 := 0; 174846#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 174845#L386-6 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 174844#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 174843#L760-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 174842#L649-3 assume !(1 == ~M_E~0); 174701#L649-5 assume !(1 == ~T1_E~0); 174841#L654-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 174840#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 174839#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 174838#L669-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 174837#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 174836#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 174835#L684-3 assume !(1 == ~E_3~0); 174834#L689-3 assume !(1 == ~E_4~0); 174833#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 174832#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 174831#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 174825#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 174824#L472-1 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 174822#L919 assume !(0 == start_simulation_~tmp~3#1); 174823#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 175487#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 175481#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 175479#L472-2 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 175477#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 175475#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 175474#L882 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 175473#L932 assume !(0 != start_simulation_~tmp___0~1#1); 168555#L900-2 [2021-12-16 10:05:50,502 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:50,502 INFO L85 PathProgramCache]: Analyzing trace with hash -445536100, now seen corresponding path program 3 times [2021-12-16 10:05:50,502 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:50,502 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1600705174] [2021-12-16 10:05:50,502 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:50,502 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:50,514 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:05:50,515 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-16 10:05:50,520 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:05:50,537 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-16 10:05:50,537 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:50,537 INFO L85 PathProgramCache]: Analyzing trace with hash -982384866, now seen corresponding path program 1 times [2021-12-16 10:05:50,538 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:50,538 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2003066224] [2021-12-16 10:05:50,538 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:50,538 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:50,545 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:50,581 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:05:50,581 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:50,581 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2003066224] [2021-12-16 10:05:50,581 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2003066224] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:50,581 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:50,581 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-16 10:05:50,581 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1435902830] [2021-12-16 10:05:50,581 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:50,582 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:05:50,582 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:05:50,582 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-16 10:05:50,582 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-16 10:05:50,582 INFO L87 Difference]: Start difference. First operand 11148 states and 15418 transitions. cyclomatic complexity: 4278 Second operand has 5 states, 5 states have (on average 17.4) internal successors, (87), 5 states have internal predecessors, (87), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:50,773 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:05:50,773 INFO L93 Difference]: Finished difference Result 26101 states and 36635 transitions. [2021-12-16 10:05:50,773 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-16 10:05:50,774 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 26101 states and 36635 transitions. [2021-12-16 10:05:51,057 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 25848 [2021-12-16 10:05:51,221 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 26101 states to 26101 states and 36635 transitions. [2021-12-16 10:05:51,222 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 26101 [2021-12-16 10:05:51,258 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 26101 [2021-12-16 10:05:51,259 INFO L73 IsDeterministic]: Start isDeterministic. Operand 26101 states and 36635 transitions. [2021-12-16 10:05:51,281 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:05:51,282 INFO L681 BuchiCegarLoop]: Abstraction has 26101 states and 36635 transitions. [2021-12-16 10:05:51,299 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 26101 states and 36635 transitions. [2021-12-16 10:05:51,431 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 26101 to 11433. [2021-12-16 10:05:51,443 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 11433 states, 11433 states have (on average 1.3666579200559783) internal successors, (15625), 11432 states have internal predecessors, (15625), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:51,465 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11433 states to 11433 states and 15625 transitions. [2021-12-16 10:05:51,465 INFO L704 BuchiCegarLoop]: Abstraction has 11433 states and 15625 transitions. [2021-12-16 10:05:51,466 INFO L587 BuchiCegarLoop]: Abstraction has 11433 states and 15625 transitions. [2021-12-16 10:05:51,466 INFO L425 BuchiCegarLoop]: ======== Iteration 17============ [2021-12-16 10:05:51,466 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 11433 states and 15625 transitions. [2021-12-16 10:05:51,503 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 11300 [2021-12-16 10:05:51,503 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:05:51,503 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:05:51,504 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:51,504 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:51,505 INFO L791 eck$LassoCheckResult]: Stem: 206075#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 206024#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 206010#L863 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 206007#L394 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 205881#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 205882#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 205659#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 205660#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 206005#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 206006#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 205963#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 205632#L586 assume !(0 == ~M_E~0); 205633#L586-2 assume !(0 == ~T1_E~0); 205685#L591-1 assume !(0 == ~T2_E~0); 205822#L596-1 assume !(0 == ~T3_E~0); 205823#L601-1 assume !(0 == ~T4_E~0); 205870#L606-1 assume !(0 == ~T5_E~0); 205871#L611-1 assume !(0 == ~E_1~0); 205970#L616-1 assume !(0 == ~E_2~0); 205971#L621-1 assume !(0 == ~E_3~0); 205561#L626-1 assume !(0 == ~E_4~0); 205562#L631-1 assume !(0 == ~E_5~0); 205719#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 205556#L279 assume !(1 == ~m_pc~0); 205558#L279-2 is_master_triggered_~__retres1~0#1 := 0; 205892#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 205797#L291 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 205798#L720 assume !(0 != activate_threads_~tmp~1#1); 205891#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 205725#L298 assume !(1 == ~t1_pc~0); 205514#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 205515#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 205787#L310 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 205571#L728 assume !(0 != activate_threads_~tmp___0~0#1); 205572#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 205690#L317 assume !(1 == ~t2_pc~0); 205691#L317-2 is_transmit2_triggered_~__retres1~2#1 := 0; 205912#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 206020#L329 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 205741#L736 assume !(0 != activate_threads_~tmp___1~0#1); 205742#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 205960#L336 assume !(1 == ~t3_pc~0); 205961#L336-2 is_transmit3_triggered_~__retres1~3#1 := 0; 206047#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 205849#L348 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 205850#L744 assume !(0 != activate_threads_~tmp___2~0#1); 205902#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 205967#L355 assume !(1 == ~t4_pc~0); 205821#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 205647#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 205648#L367 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 205885#L752 assume !(0 != activate_threads_~tmp___3~0#1); 205585#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 205586#L374 assume !(1 == ~t5_pc~0); 205712#L374-2 is_transmit5_triggered_~__retres1~5#1 := 0; 205713#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 205795#L386 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 205796#L760 assume !(0 != activate_threads_~tmp___4~0#1); 205852#L760-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 205853#L649 assume !(1 == ~M_E~0); 206040#L649-2 assume !(1 == ~T1_E~0); 205545#L654-1 assume !(1 == ~T2_E~0); 205546#L659-1 assume !(1 == ~T3_E~0); 205734#L664-1 assume !(1 == ~T4_E~0); 205538#L669-1 assume !(1 == ~T5_E~0); 205539#L674-1 assume !(1 == ~E_1~0); 205954#L679-1 assume !(1 == ~E_2~0); 205634#L684-1 assume !(1 == ~E_3~0); 205635#L689-1 assume !(1 == ~E_4~0); 205815#L694-1 assume !(1 == ~E_5~0); 205813#L699-1 assume { :end_inline_reset_delta_events } true; 205814#L900-2 [2021-12-16 10:05:51,505 INFO L793 eck$LassoCheckResult]: Loop: 205814#L900-2 assume !false; 216148#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 210322#L561 assume !false; 216145#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 216139#L439 assume !(0 == ~m_st~0); 216140#L443 assume !(0 == ~t1_st~0); 216136#L447 assume !(0 == ~t2_st~0); 216137#L451 assume !(0 == ~t3_st~0); 216138#L455 assume !(0 == ~t4_st~0); 216134#L459 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6#1 := 0; 216135#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 216282#L472 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 216280#L486 assume !(0 != eval_~tmp~0#1); 216278#L576 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 216276#L394-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 216274#L586-3 assume !(0 == ~M_E~0); 216272#L586-5 assume !(0 == ~T1_E~0); 216270#L591-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 216268#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 216266#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 216264#L606-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 216262#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 216260#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 216259#L621-3 assume !(0 == ~E_3~0); 216258#L626-3 assume !(0 == ~E_4~0); 216256#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 216254#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 216253#L279-18 assume !(1 == ~m_pc~0); 216251#L279-20 is_master_triggered_~__retres1~0#1 := 0; 216250#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 216249#L291-6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 216248#L720-18 assume !(0 != activate_threads_~tmp~1#1); 216247#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 216246#L298-18 assume !(1 == ~t1_pc~0); 216245#L298-20 is_transmit1_triggered_~__retres1~1#1 := 0; 216244#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 216243#L310-6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 216242#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 216241#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 216240#L317-18 assume !(1 == ~t2_pc~0); 216239#L317-20 is_transmit2_triggered_~__retres1~2#1 := 0; 216238#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 216237#L329-6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 216236#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 216235#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 216234#L336-18 assume !(1 == ~t3_pc~0); 216233#L336-20 is_transmit3_triggered_~__retres1~3#1 := 0; 216232#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 216231#L348-6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 216230#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 216229#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 216227#L355-18 assume !(1 == ~t4_pc~0); 216226#L355-20 is_transmit4_triggered_~__retres1~4#1 := 0; 216225#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 216224#L367-6 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 216223#L752-18 assume !(0 != activate_threads_~tmp___3~0#1); 216222#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 216221#L374-18 assume !(1 == ~t5_pc~0); 216220#L374-20 is_transmit5_triggered_~__retres1~5#1 := 0; 216219#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 216218#L386-6 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 216217#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 216216#L760-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 216215#L649-3 assume !(1 == ~M_E~0); 216212#L649-5 assume !(1 == ~T1_E~0); 216211#L654-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 216210#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 216209#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 216208#L669-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 216207#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 216206#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 216205#L684-3 assume !(1 == ~E_3~0); 216204#L689-3 assume !(1 == ~E_4~0); 216203#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 216202#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 216201#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 216195#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 216193#L472-1 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 216176#L919 assume !(0 == start_simulation_~tmp~3#1); 216174#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 216167#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 216161#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 216159#L472-2 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 216157#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 216155#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 216153#L882 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 216151#L932 assume !(0 != start_simulation_~tmp___0~1#1); 205814#L900-2 [2021-12-16 10:05:51,505 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:51,505 INFO L85 PathProgramCache]: Analyzing trace with hash -445536100, now seen corresponding path program 4 times [2021-12-16 10:05:51,505 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:51,505 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2132266988] [2021-12-16 10:05:51,505 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:51,506 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:51,524 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:05:51,524 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-16 10:05:51,528 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:05:51,541 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-16 10:05:51,542 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:51,542 INFO L85 PathProgramCache]: Analyzing trace with hash -941710116, now seen corresponding path program 1 times [2021-12-16 10:05:51,542 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:51,542 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [329763104] [2021-12-16 10:05:51,543 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:51,543 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:51,551 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:51,588 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:05:51,589 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:51,589 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [329763104] [2021-12-16 10:05:51,589 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [329763104] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:51,589 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:51,589 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:05:51,589 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [451748365] [2021-12-16 10:05:51,590 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:51,590 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:05:51,590 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:05:51,590 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-16 10:05:51,590 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-16 10:05:51,591 INFO L87 Difference]: Start difference. First operand 11433 states and 15625 transitions. cyclomatic complexity: 4200 Second operand has 3 states, 3 states have (on average 29.0) internal successors, (87), 3 states have internal predecessors, (87), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:51,728 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:05:51,728 INFO L93 Difference]: Finished difference Result 19603 states and 26408 transitions. [2021-12-16 10:05:51,729 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-16 10:05:51,729 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 19603 states and 26408 transitions. [2021-12-16 10:05:51,795 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 19410 [2021-12-16 10:05:51,841 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 19603 states to 19603 states and 26408 transitions. [2021-12-16 10:05:51,841 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 19603 [2021-12-16 10:05:51,851 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 19603 [2021-12-16 10:05:51,851 INFO L73 IsDeterministic]: Start isDeterministic. Operand 19603 states and 26408 transitions. [2021-12-16 10:05:51,866 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:05:51,866 INFO L681 BuchiCegarLoop]: Abstraction has 19603 states and 26408 transitions. [2021-12-16 10:05:51,875 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19603 states and 26408 transitions. [2021-12-16 10:05:51,996 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19603 to 18944. [2021-12-16 10:05:52,014 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 18944 states, 18944 states have (on average 1.351879222972973) internal successors, (25610), 18943 states have internal predecessors, (25610), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:52,047 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18944 states to 18944 states and 25610 transitions. [2021-12-16 10:05:52,047 INFO L704 BuchiCegarLoop]: Abstraction has 18944 states and 25610 transitions. [2021-12-16 10:05:52,047 INFO L587 BuchiCegarLoop]: Abstraction has 18944 states and 25610 transitions. [2021-12-16 10:05:52,047 INFO L425 BuchiCegarLoop]: ======== Iteration 18============ [2021-12-16 10:05:52,047 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 18944 states and 25610 transitions. [2021-12-16 10:05:52,096 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 18751 [2021-12-16 10:05:52,096 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:05:52,096 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:05:52,097 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:52,097 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:52,097 INFO L791 eck$LassoCheckResult]: Stem: 237097#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 237056#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 237044#L863 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 237041#L394 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 236924#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 236925#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 236701#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 236702#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 237039#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 237040#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 237002#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 236676#L586 assume !(0 == ~M_E~0); 236677#L586-2 assume !(0 == ~T1_E~0); 236728#L591-1 assume !(0 == ~T2_E~0); 236866#L596-1 assume !(0 == ~T3_E~0); 236867#L601-1 assume !(0 == ~T4_E~0); 236912#L606-1 assume !(0 == ~T5_E~0); 236913#L611-1 assume !(0 == ~E_1~0); 237013#L616-1 assume !(0 == ~E_2~0); 237014#L621-1 assume !(0 == ~E_3~0); 236606#L626-1 assume !(0 == ~E_4~0); 236607#L631-1 assume !(0 == ~E_5~0); 236761#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 236601#L279 assume !(1 == ~m_pc~0); 236603#L279-2 is_master_triggered_~__retres1~0#1 := 0; 236936#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 236840#L291 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 236841#L720 assume !(0 != activate_threads_~tmp~1#1); 236935#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 236768#L298 assume !(1 == ~t1_pc~0); 236558#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 236559#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 236829#L310 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 236615#L728 assume !(0 != activate_threads_~tmp___0~0#1); 236616#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 236734#L317 assume !(1 == ~t2_pc~0); 236735#L317-2 is_transmit2_triggered_~__retres1~2#1 := 0; 236955#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 237050#L329 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 236782#L736 assume !(0 != activate_threads_~tmp___1~0#1); 236783#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 236999#L336 assume !(1 == ~t3_pc~0); 237000#L336-2 is_transmit3_triggered_~__retres1~3#1 := 0; 237077#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 236891#L348 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 236892#L744 assume !(0 != activate_threads_~tmp___2~0#1); 236945#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 237007#L355 assume !(1 == ~t4_pc~0); 236865#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 236689#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 236690#L367 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 236929#L752 assume !(0 != activate_threads_~tmp___3~0#1); 236628#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 236629#L374 assume !(1 == ~t5_pc~0); 236755#L374-2 is_transmit5_triggered_~__retres1~5#1 := 0; 236756#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 236838#L386 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 236839#L760 assume !(0 != activate_threads_~tmp___4~0#1); 236894#L760-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 236895#L649 assume !(1 == ~M_E~0); 237069#L649-2 assume !(1 == ~T1_E~0); 236590#L654-1 assume !(1 == ~T2_E~0); 236591#L659-1 assume !(1 == ~T3_E~0); 236775#L664-1 assume !(1 == ~T4_E~0); 236582#L669-1 assume !(1 == ~T5_E~0); 236583#L674-1 assume !(1 == ~E_1~0); 236993#L679-1 assume !(1 == ~E_2~0); 236678#L684-1 assume !(1 == ~E_3~0); 236679#L689-1 assume !(1 == ~E_4~0); 236860#L694-1 assume !(1 == ~E_5~0); 236858#L699-1 assume { :end_inline_reset_delta_events } true; 236859#L900-2 [2021-12-16 10:05:52,102 INFO L793 eck$LassoCheckResult]: Loop: 236859#L900-2 assume !false; 246661#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 246659#L561 assume !false; 246657#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 246655#L439 assume !(0 == ~m_st~0); 245097#L443 assume !(0 == ~t1_st~0); 245095#L447 assume !(0 == ~t2_st~0); 245093#L451 assume !(0 == ~t3_st~0); 245091#L455 assume !(0 == ~t4_st~0); 245088#L459 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6#1 := 0; 245086#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 245083#L472 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 245079#L486 assume !(0 != eval_~tmp~0#1); 245077#L576 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 245075#L394-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 245073#L586-3 assume !(0 == ~M_E~0); 245071#L586-5 assume !(0 == ~T1_E~0); 245069#L591-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 245067#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 245065#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 245063#L606-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 244356#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 244353#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 244351#L621-3 assume !(0 == ~E_3~0); 244349#L626-3 assume !(0 == ~E_4~0); 244347#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 244346#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 244344#L279-18 assume !(1 == ~m_pc~0); 244341#L279-20 is_master_triggered_~__retres1~0#1 := 0; 244339#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 244336#L291-6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 244334#L720-18 assume !(0 != activate_threads_~tmp~1#1); 244332#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 244330#L298-18 assume !(1 == ~t1_pc~0); 244328#L298-20 is_transmit1_triggered_~__retres1~1#1 := 0; 244326#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 244324#L310-6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 244322#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 244320#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 244318#L317-18 assume !(1 == ~t2_pc~0); 244316#L317-20 is_transmit2_triggered_~__retres1~2#1 := 0; 244314#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 244312#L329-6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 244310#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 244308#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 244306#L336-18 assume !(1 == ~t3_pc~0); 244304#L336-20 is_transmit3_triggered_~__retres1~3#1 := 0; 244302#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 244300#L348-6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 244297#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 244295#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 244290#L355-18 assume !(1 == ~t4_pc~0); 244288#L355-20 is_transmit4_triggered_~__retres1~4#1 := 0; 244286#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 244284#L367-6 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 244282#L752-18 assume !(0 != activate_threads_~tmp___3~0#1); 244280#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 244278#L374-18 assume !(1 == ~t5_pc~0); 244276#L374-20 is_transmit5_triggered_~__retres1~5#1 := 0; 244274#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 244272#L386-6 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 244270#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 244268#L760-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 244266#L649-3 assume !(1 == ~M_E~0); 244262#L649-5 assume !(1 == ~T1_E~0); 244260#L654-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 244258#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 244256#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 244254#L669-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 244252#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 244250#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 244249#L684-3 assume !(1 == ~E_3~0); 244248#L689-3 assume !(1 == ~E_4~0); 244247#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 244245#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 244243#L439-1 assume !(0 == ~m_st~0); 244222#L443-1 assume 0 == ~t1_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 244231#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 244232#L472-1 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 244225#L919 assume 0 == start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 4;assume { :begin_inline_fire_time_events } true;~M_E~0 := 1; 244223#L786 assume { :end_inline_fire_time_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 244220#L279-21 assume 1 == ~m_pc~0; 244217#L280-7 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 244215#L290-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 244212#L291-7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 244201#L720-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 244198#L720-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 244196#L298-21 assume !(1 == ~t1_pc~0); 244194#L298-23 is_transmit1_triggered_~__retres1~1#1 := 0; 244192#L309-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 244190#L310-7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 244188#L728-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 244186#L728-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 244184#L317-21 assume !(1 == ~t2_pc~0); 244182#L317-23 is_transmit2_triggered_~__retres1~2#1 := 0; 244180#L328-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 244178#L329-7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 244176#L736-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 244173#L736-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 244171#L336-21 assume !(1 == ~t3_pc~0); 244169#L336-23 is_transmit3_triggered_~__retres1~3#1 := 0; 244167#L347-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 244165#L348-7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 244163#L744-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 244161#L744-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 244159#L355-21 assume !(1 == ~t4_pc~0); 244156#L355-23 is_transmit4_triggered_~__retres1~4#1 := 0; 244154#L366-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 244152#L367-7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 244150#L752-21 assume !(0 != activate_threads_~tmp___3~0#1); 244147#L752-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 244145#L374-21 assume !(1 == ~t5_pc~0); 244143#L374-23 is_transmit5_triggered_~__retres1~5#1 := 0; 244142#L385-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 244141#L386-7 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 244139#L760-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 244138#L760-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_time_events } true; 244136#L793 assume 1 == ~M_E~0;~M_E~0 := 2; 244137#L793-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 248905#L798-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 248902#L803-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 248896#L808-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 248892#L813-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 248888#L818-1 assume 1 == ~E_1~0;~E_1~0 := 2; 248883#L823-1 assume 1 == ~E_2~0;~E_2~0 := 2; 248877#L828-1 assume !(1 == ~E_3~0); 248867#L833-1 assume !(1 == ~E_4~0); 248863#L838-1 assume 1 == ~E_5~0;~E_5~0 := 2; 246712#L843-1 assume { :end_inline_reset_time_events } true; 244214#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 246710#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 246709#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 246708#L472-2 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 246704#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 246701#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 246697#L882 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 246695#L932 assume !(0 != start_simulation_~tmp___0~1#1); 236859#L900-2 [2021-12-16 10:05:52,103 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:52,103 INFO L85 PathProgramCache]: Analyzing trace with hash -445536100, now seen corresponding path program 5 times [2021-12-16 10:05:52,103 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:52,103 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [592052743] [2021-12-16 10:05:52,103 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:52,103 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:52,113 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:05:52,113 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-16 10:05:52,119 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:05:52,127 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-16 10:05:52,127 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:52,127 INFO L85 PathProgramCache]: Analyzing trace with hash 968028547, now seen corresponding path program 1 times [2021-12-16 10:05:52,127 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:52,127 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1826919533] [2021-12-16 10:05:52,127 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:52,127 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:52,137 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:52,150 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:05:52,150 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:52,150 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1826919533] [2021-12-16 10:05:52,150 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1826919533] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:52,150 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:52,150 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:05:52,150 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1953842872] [2021-12-16 10:05:52,150 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:52,151 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:05:52,151 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:05:52,151 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-16 10:05:52,151 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-16 10:05:52,151 INFO L87 Difference]: Start difference. First operand 18944 states and 25610 transitions. cyclomatic complexity: 6674 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:52,338 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:05:52,338 INFO L93 Difference]: Finished difference Result 34257 states and 46082 transitions. [2021-12-16 10:05:52,339 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-16 10:05:52,339 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 34257 states and 46082 transitions. [2021-12-16 10:05:52,466 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 33945 [2021-12-16 10:05:52,540 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 34257 states to 34257 states and 46082 transitions. [2021-12-16 10:05:52,540 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 34257 [2021-12-16 10:05:52,560 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 34257 [2021-12-16 10:05:52,560 INFO L73 IsDeterministic]: Start isDeterministic. Operand 34257 states and 46082 transitions. [2021-12-16 10:05:52,584 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:05:52,584 INFO L681 BuchiCegarLoop]: Abstraction has 34257 states and 46082 transitions. [2021-12-16 10:05:52,601 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 34257 states and 46082 transitions. [2021-12-16 10:05:52,822 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 34257 to 34185. [2021-12-16 10:05:52,854 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 34185 states, 34185 states have (on average 1.3459119496855345) internal successors, (46010), 34184 states have internal predecessors, (46010), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:52,910 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 34185 states to 34185 states and 46010 transitions. [2021-12-16 10:05:52,910 INFO L704 BuchiCegarLoop]: Abstraction has 34185 states and 46010 transitions. [2021-12-16 10:05:52,910 INFO L587 BuchiCegarLoop]: Abstraction has 34185 states and 46010 transitions. [2021-12-16 10:05:52,910 INFO L425 BuchiCegarLoop]: ======== Iteration 19============ [2021-12-16 10:05:52,910 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 34185 states and 46010 transitions. [2021-12-16 10:05:53,002 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 33873 [2021-12-16 10:05:53,005 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:05:53,005 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:05:53,027 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:53,027 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:53,027 INFO L791 eck$LassoCheckResult]: Stem: 290299#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 290257#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 290245#L863 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 290241#L394 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 290122#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 290123#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 289906#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 289907#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 290239#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 290240#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 290202#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 289879#L586 assume !(0 == ~M_E~0); 289880#L586-2 assume !(0 == ~T1_E~0); 289930#L591-1 assume !(0 == ~T2_E~0); 290069#L596-1 assume !(0 == ~T3_E~0); 290070#L601-1 assume !(0 == ~T4_E~0); 290111#L606-1 assume !(0 == ~T5_E~0); 290112#L611-1 assume !(0 == ~E_1~0); 290210#L616-1 assume !(0 == ~E_2~0); 290211#L621-1 assume !(0 == ~E_3~0); 289807#L626-1 assume !(0 == ~E_4~0); 289808#L631-1 assume !(0 == ~E_5~0); 289965#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 289805#L279 assume !(1 == ~m_pc~0); 289806#L279-2 is_master_triggered_~__retres1~0#1 := 0; 290134#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 290045#L291 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 290046#L720 assume !(0 != activate_threads_~tmp~1#1); 290133#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 289971#L298 assume !(1 == ~t1_pc~0); 289765#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 289766#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 290035#L310 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 289817#L728 assume !(0 != activate_threads_~tmp___0~0#1); 289818#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 289936#L317 assume !(1 == ~t2_pc~0); 289937#L317-2 is_transmit2_triggered_~__retres1~2#1 := 0; 290155#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 290254#L329 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 289985#L736 assume !(0 != activate_threads_~tmp___1~0#1); 289986#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 290198#L336 assume !(1 == ~t3_pc~0); 290199#L336-2 is_transmit3_triggered_~__retres1~3#1 := 0; 290278#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 290093#L348 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 290094#L744 assume !(0 != activate_threads_~tmp___2~0#1); 290144#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 290205#L355 assume !(1 == ~t4_pc~0); 290068#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 289894#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 289895#L367 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 290127#L752 assume !(0 != activate_threads_~tmp___3~0#1); 289829#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 289830#L374 assume !(1 == ~t5_pc~0); 289956#L374-2 is_transmit5_triggered_~__retres1~5#1 := 0; 289957#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 290043#L386 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 290044#L760 assume !(0 != activate_threads_~tmp___4~0#1); 290096#L760-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 290097#L649 assume !(1 == ~M_E~0); 290272#L649-2 assume !(1 == ~T1_E~0); 289792#L654-1 assume !(1 == ~T2_E~0); 289793#L659-1 assume !(1 == ~T3_E~0); 289978#L664-1 assume !(1 == ~T4_E~0); 289784#L669-1 assume !(1 == ~T5_E~0); 289785#L674-1 assume !(1 == ~E_1~0); 290191#L679-1 assume !(1 == ~E_2~0); 289881#L684-1 assume !(1 == ~E_3~0); 289882#L689-1 assume !(1 == ~E_4~0); 290062#L694-1 assume !(1 == ~E_5~0); 290060#L699-1 assume { :end_inline_reset_delta_events } true; 290061#L900-2 [2021-12-16 10:05:53,028 INFO L793 eck$LassoCheckResult]: Loop: 290061#L900-2 assume !false; 310513#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 310428#L561 assume !false; 310512#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 310510#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 310509#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 310508#L472 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 310507#L486 assume 0 != eval_~tmp~0#1; 310505#L486-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 310503#L494 assume 0 != eval_~tmp_ndt_1~0#1;~m_st~0 := 1;assume { :begin_inline_master } true; 310504#L65 assume 0 == ~m_pc~0; 295208#L92 assume !false; 313644#L77 ~E_1~0 := 1;assume { :begin_inline_immediate_notify } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 313643#L279-3 assume !(1 == ~m_pc~0); 313642#L279-5 is_master_triggered_~__retres1~0#1 := 0; 313641#L290-1 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 313640#L291-1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 313639#L720-3 assume !(0 != activate_threads_~tmp~1#1); 313638#L720-5 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 313637#L298-3 assume !(1 == ~t1_pc~0); 313636#L298-5 is_transmit1_triggered_~__retres1~1#1 := 0; 313635#L309-1 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 313634#L310-1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 313633#L728-3 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 313632#L728-5 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 313631#L317-3 assume !(1 == ~t2_pc~0); 313630#L317-5 is_transmit2_triggered_~__retres1~2#1 := 0; 313629#L328-1 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 313628#L329-1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 313627#L736-3 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 313626#L736-5 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 313625#L336-3 assume !(1 == ~t3_pc~0); 313624#L336-5 is_transmit3_triggered_~__retres1~3#1 := 0; 313623#L347-1 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 313622#L348-1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 313619#L744-3 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 294822#L744-5 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 294823#L355-3 assume !(1 == ~t4_pc~0); 309646#L355-5 is_transmit4_triggered_~__retres1~4#1 := 0; 309644#L366-1 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 309641#L367-1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 309639#L752-3 assume !(0 != activate_threads_~tmp___3~0#1); 309637#L752-5 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 309635#L374-3 assume !(1 == ~t5_pc~0); 309633#L374-5 is_transmit5_triggered_~__retres1~5#1 := 0; 309631#L385-1 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 309629#L386-1 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 309627#L760-3 assume !(0 != activate_threads_~tmp___4~0#1); 309625#L760-5 assume { :end_inline_activate_threads } true; 309433#L777 assume { :end_inline_immediate_notify } true;~E_1~0 := 2; 309425#L69 assume !false; 294535#L85 ~m_pc~0 := 1;~m_st~0 := 2; 294529#L95 assume { :end_inline_master } true; 293483#L491 assume !(0 == ~t1_st~0); 294516#L505 assume !(0 == ~t2_st~0); 294511#L519 assume !(0 == ~t3_st~0); 295428#L533 assume !(0 == ~t4_st~0); 295087#L547 assume !(0 == ~t5_st~0); 295082#L561 assume !false; 295080#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 295078#L439 assume !(0 == ~m_st~0); 293491#L443 assume !(0 == ~t1_st~0); 294589#L447 assume !(0 == ~t2_st~0); 294590#L451 assume !(0 == ~t3_st~0); 294591#L455 assume !(0 == ~t4_st~0); 294587#L459 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6#1 := 0; 294588#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 294777#L472 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 294775#L486 assume !(0 != eval_~tmp~0#1); 294773#L576 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 294772#L394-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 294770#L586-3 assume !(0 == ~M_E~0); 294768#L586-5 assume !(0 == ~T1_E~0); 294766#L591-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 294764#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 294761#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 294759#L606-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 294757#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 294755#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 294753#L621-3 assume !(0 == ~E_3~0); 294751#L626-3 assume !(0 == ~E_4~0); 294750#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 294747#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 294744#L279-18 assume 1 == ~m_pc~0; 294742#L280-6 assume !(1 == ~M_E~0); 294740#L279-20 is_master_triggered_~__retres1~0#1 := 0; 294738#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 294736#L291-6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 294734#L720-18 assume !(0 != activate_threads_~tmp~1#1); 294732#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 294730#L298-18 assume !(1 == ~t1_pc~0); 294728#L298-20 is_transmit1_triggered_~__retres1~1#1 := 0; 294726#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 294724#L310-6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 294720#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 294718#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 294716#L317-18 assume !(1 == ~t2_pc~0); 294714#L317-20 is_transmit2_triggered_~__retres1~2#1 := 0; 294712#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 294710#L329-6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 294708#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 294706#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 294704#L336-18 assume !(1 == ~t3_pc~0); 294702#L336-20 is_transmit3_triggered_~__retres1~3#1 := 0; 294700#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 294698#L348-6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 294696#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 294695#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 294693#L355-18 assume !(1 == ~t4_pc~0); 294692#L355-20 is_transmit4_triggered_~__retres1~4#1 := 0; 294690#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 294686#L367-6 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 294684#L752-18 assume !(0 != activate_threads_~tmp___3~0#1); 294682#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 294680#L374-18 assume !(1 == ~t5_pc~0); 294678#L374-20 is_transmit5_triggered_~__retres1~5#1 := 0; 294676#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 294674#L386-6 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 294672#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 294670#L760-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 294668#L649-3 assume !(1 == ~M_E~0); 293912#L649-5 assume !(1 == ~T1_E~0); 294665#L654-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 294663#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 294661#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 294659#L669-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 294657#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 294565#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 294562#L684-3 assume !(1 == ~E_3~0); 294559#L689-3 assume !(1 == ~E_4~0); 294554#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 294552#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 294174#L439-1 assume !(0 == ~m_st~0); 294167#L443-1 assume 0 == ~t1_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 294163#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 293881#L472-1 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 293620#L919 assume 0 == start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 4;assume { :begin_inline_fire_time_events } true;~M_E~0 := 1; 293618#L786 assume { :end_inline_fire_time_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 293614#L279-21 assume 1 == ~m_pc~0; 293611#L280-7 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 293609#L290-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 293608#L291-7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 293599#L720-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 293598#L720-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 293597#L298-21 assume !(1 == ~t1_pc~0); 293594#L298-23 is_transmit1_triggered_~__retres1~1#1 := 0; 293592#L309-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 293590#L310-7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 293588#L728-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 293586#L728-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 293584#L317-21 assume !(1 == ~t2_pc~0); 293582#L317-23 is_transmit2_triggered_~__retres1~2#1 := 0; 293580#L328-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 293578#L329-7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 293576#L736-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 293574#L736-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 293572#L336-21 assume !(1 == ~t3_pc~0); 293570#L336-23 is_transmit3_triggered_~__retres1~3#1 := 0; 293568#L347-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 293567#L348-7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 293565#L744-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 293563#L744-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 293561#L355-21 assume !(1 == ~t4_pc~0); 293558#L355-23 is_transmit4_triggered_~__retres1~4#1 := 0; 293556#L366-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 293554#L367-7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 293552#L752-21 assume !(0 != activate_threads_~tmp___3~0#1); 293550#L752-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 293548#L374-21 assume !(1 == ~t5_pc~0); 293546#L374-23 is_transmit5_triggered_~__retres1~5#1 := 0; 293545#L385-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 293542#L386-7 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 293540#L760-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 293538#L760-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_time_events } true; 293535#L793 assume !(1 == ~M_E~0); 293533#L793-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 293531#L798-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 293529#L803-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 293527#L808-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 293525#L813-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 293523#L818-1 assume 1 == ~E_1~0;~E_1~0 := 2; 293521#L823-1 assume 1 == ~E_2~0;~E_2~0 := 2; 293519#L828-1 assume !(1 == ~E_3~0); 293518#L833-1 assume !(1 == ~E_4~0); 293514#L838-1 assume 1 == ~E_5~0;~E_5~0 := 2; 293512#L843-1 assume { :end_inline_reset_time_events } true; 293509#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 293507#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 293501#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 293496#L472-2 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 293494#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 293492#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 293489#L882 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 293487#L932 assume !(0 != start_simulation_~tmp___0~1#1); 293485#L900-2 assume !false; 292359#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 292354#L561 assume !false; 292349#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 292346#L439 assume !(0 == ~m_st~0); 292347#L443 assume !(0 == ~t1_st~0); 293778#L447 assume !(0 == ~t2_st~0); 293777#L451 assume !(0 == ~t3_st~0); 293776#L455 assume !(0 == ~t4_st~0); 293774#L459 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6#1 := 0; 293771#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 293770#L472 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 293768#L486 assume !(0 != eval_~tmp~0#1); 293767#L576 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 293766#L394-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 293764#L586-3 assume 0 == ~M_E~0;~M_E~0 := 1; 293762#L586-5 assume !(0 == ~T1_E~0); 293760#L591-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 293758#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 293756#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 293754#L606-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 293752#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 293750#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 293748#L621-3 assume !(0 == ~E_3~0); 293746#L626-3 assume !(0 == ~E_4~0); 293744#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 293741#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 293738#L279-18 assume 1 == ~m_pc~0; 293735#L280-6 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 293733#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 293731#L291-6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 293728#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 293726#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 293724#L298-18 assume !(1 == ~t1_pc~0); 293723#L298-20 is_transmit1_triggered_~__retres1~1#1 := 0; 293722#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 293720#L310-6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 293713#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 293710#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 293705#L317-18 assume !(1 == ~t2_pc~0); 293700#L317-20 is_transmit2_triggered_~__retres1~2#1 := 0; 293698#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 293696#L329-6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 293693#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 293691#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 293689#L336-18 assume !(1 == ~t3_pc~0); 293687#L336-20 is_transmit3_triggered_~__retres1~3#1 := 0; 293684#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 293681#L348-6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 293677#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 293675#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 293669#L355-18 assume !(1 == ~t4_pc~0); 293668#L355-20 is_transmit4_triggered_~__retres1~4#1 := 0; 293666#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 293663#L367-6 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 293660#L752-18 assume !(0 != activate_threads_~tmp___3~0#1); 293658#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 293655#L374-18 assume !(1 == ~t5_pc~0); 293653#L374-20 is_transmit5_triggered_~__retres1~5#1 := 0; 293650#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 293648#L386-6 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 293646#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 293644#L760-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 293641#L649-3 assume !(1 == ~M_E~0); 293639#L649-5 assume !(1 == ~T1_E~0); 293637#L654-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 293635#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 293633#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 293631#L669-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 293629#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 293627#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 293625#L684-3 assume !(1 == ~E_3~0); 293624#L689-3 assume !(1 == ~E_4~0); 293622#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 293619#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 293616#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 293613#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 293610#L472-1 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 293511#L919 assume 0 == start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 4;assume { :begin_inline_fire_time_events } true;~M_E~0 := 1; 293347#L786 assume { :end_inline_fire_time_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 293340#L279-21 assume !(1 == ~m_pc~0); 293342#L279-23 is_master_triggered_~__retres1~0#1 := 0; 304765#L290-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 304764#L291-7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 304763#L720-21 assume !(0 != activate_threads_~tmp~1#1); 304762#L720-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 304761#L298-21 assume !(1 == ~t1_pc~0); 304760#L298-23 is_transmit1_triggered_~__retres1~1#1 := 0; 304759#L309-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 304758#L310-7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 304757#L728-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 304756#L728-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 304755#L317-21 assume !(1 == ~t2_pc~0); 304754#L317-23 is_transmit2_triggered_~__retres1~2#1 := 0; 304753#L328-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 304752#L329-7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 304751#L736-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 304750#L736-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 304749#L336-21 assume !(1 == ~t3_pc~0); 304748#L336-23 is_transmit3_triggered_~__retres1~3#1 := 0; 304747#L347-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 304746#L348-7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 304745#L744-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 304744#L744-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 304743#L355-21 assume !(1 == ~t4_pc~0); 304741#L355-23 is_transmit4_triggered_~__retres1~4#1 := 0; 304740#L366-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 304739#L367-7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 304738#L752-21 assume !(0 != activate_threads_~tmp___3~0#1); 304737#L752-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 304736#L374-21 assume !(1 == ~t5_pc~0); 304735#L374-23 is_transmit5_triggered_~__retres1~5#1 := 0; 304734#L385-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 304733#L386-7 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 304732#L760-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 304731#L760-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_time_events } true; 304729#L793 assume 1 == ~M_E~0;~M_E~0 := 2; 304730#L793-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 310532#L798-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 310531#L803-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 310530#L808-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 310529#L813-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 310528#L818-1 assume 1 == ~E_1~0;~E_1~0 := 2; 310527#L823-1 assume 1 == ~E_2~0;~E_2~0 := 2; 310526#L828-1 assume !(1 == ~E_3~0); 310525#L833-1 assume !(1 == ~E_4~0); 310524#L838-1 assume 1 == ~E_5~0;~E_5~0 := 2; 310523#L843-1 assume { :end_inline_reset_time_events } true; 310522#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 310520#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 310519#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 310518#L472-2 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 310517#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 310516#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 310515#L882 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 310514#L932 assume !(0 != start_simulation_~tmp___0~1#1); 290061#L900-2 [2021-12-16 10:05:53,028 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:53,028 INFO L85 PathProgramCache]: Analyzing trace with hash -445536100, now seen corresponding path program 6 times [2021-12-16 10:05:53,028 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:53,028 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1816033090] [2021-12-16 10:05:53,028 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:53,028 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:53,034 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:05:53,034 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-16 10:05:53,037 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:05:53,044 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-16 10:05:53,044 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:53,045 INFO L85 PathProgramCache]: Analyzing trace with hash -1117504309, now seen corresponding path program 1 times [2021-12-16 10:05:53,045 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:53,045 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [481886011] [2021-12-16 10:05:53,045 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:53,045 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:53,053 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:53,080 INFO L134 CoverageAnalysis]: Checked inductivity of 147 backedges. 14 proven. 0 refuted. 0 times theorem prover too weak. 133 trivial. 0 not checked. [2021-12-16 10:05:53,081 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:53,081 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [481886011] [2021-12-16 10:05:53,081 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [481886011] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:53,081 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:53,081 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-16 10:05:53,081 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1043803358] [2021-12-16 10:05:53,081 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:53,081 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:05:53,082 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:05:53,082 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-16 10:05:53,082 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-16 10:05:53,082 INFO L87 Difference]: Start difference. First operand 34185 states and 46010 transitions. cyclomatic complexity: 11841 Second operand has 5 states, 5 states have (on average 40.8) internal successors, (204), 5 states have internal predecessors, (204), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:53,331 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:05:53,331 INFO L93 Difference]: Finished difference Result 64849 states and 86851 transitions. [2021-12-16 10:05:53,332 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-16 10:05:53,332 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 64849 states and 86851 transitions. [2021-12-16 10:05:53,904 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 64409 [2021-12-16 10:05:54,263 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 64849 states to 64849 states and 86851 transitions. [2021-12-16 10:05:54,263 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 64849 [2021-12-16 10:05:54,306 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 64849 [2021-12-16 10:05:54,306 INFO L73 IsDeterministic]: Start isDeterministic. Operand 64849 states and 86851 transitions. [2021-12-16 10:05:54,353 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:05:54,353 INFO L681 BuchiCegarLoop]: Abstraction has 64849 states and 86851 transitions. [2021-12-16 10:05:54,389 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 64849 states and 86851 transitions. [2021-12-16 10:05:54,742 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 64849 to 35025. [2021-12-16 10:05:54,777 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 35025 states, 35025 states have (on average 1.3305638829407567) internal successors, (46603), 35024 states have internal predecessors, (46603), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:54,835 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 35025 states to 35025 states and 46603 transitions. [2021-12-16 10:05:54,835 INFO L704 BuchiCegarLoop]: Abstraction has 35025 states and 46603 transitions. [2021-12-16 10:05:54,835 INFO L587 BuchiCegarLoop]: Abstraction has 35025 states and 46603 transitions. [2021-12-16 10:05:54,835 INFO L425 BuchiCegarLoop]: ======== Iteration 20============ [2021-12-16 10:05:54,835 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 35025 states and 46603 transitions. [2021-12-16 10:05:54,925 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 34713 [2021-12-16 10:05:54,925 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:05:54,926 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:05:54,927 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:54,927 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:54,928 INFO L791 eck$LassoCheckResult]: Stem: 389366#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 389322#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 389307#L863 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 389304#L394 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 389172#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 389173#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 388952#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 388953#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 389302#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 389303#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 389252#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 388923#L586 assume !(0 == ~M_E~0); 388924#L586-2 assume !(0 == ~T1_E~0); 388976#L591-1 assume !(0 == ~T2_E~0); 389111#L596-1 assume !(0 == ~T3_E~0); 389112#L601-1 assume !(0 == ~T4_E~0); 389161#L606-1 assume !(0 == ~T5_E~0); 389162#L611-1 assume !(0 == ~E_1~0); 389264#L616-1 assume !(0 == ~E_2~0); 389265#L621-1 assume !(0 == ~E_3~0); 388855#L626-1 assume !(0 == ~E_4~0); 388856#L631-1 assume !(0 == ~E_5~0); 389014#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 388851#L279 assume !(1 == ~m_pc~0); 388852#L279-2 is_master_triggered_~__retres1~0#1 := 0; 389185#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 389087#L291 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 389088#L720 assume !(0 != activate_threads_~tmp~1#1); 389184#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 389021#L298 assume !(1 == ~t1_pc~0); 388811#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 388812#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 389075#L310 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 388865#L728 assume !(0 != activate_threads_~tmp___0~0#1); 388866#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 388982#L317 assume !(1 == ~t2_pc~0); 388983#L317-2 is_transmit2_triggered_~__retres1~2#1 := 0; 389205#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 389316#L329 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 389029#L736 assume !(0 != activate_threads_~tmp___1~0#1); 389030#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 389247#L336 assume !(1 == ~t3_pc~0); 389248#L336-2 is_transmit3_triggered_~__retres1~3#1 := 0; 389343#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 389138#L348 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 389139#L744 assume !(0 != activate_threads_~tmp___2~0#1); 389194#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 389258#L355 assume !(1 == ~t4_pc~0); 389108#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 388937#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 388938#L367 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 389177#L752 assume !(0 != activate_threads_~tmp___3~0#1); 388875#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 388876#L374 assume !(1 == ~t5_pc~0); 389003#L374-2 is_transmit5_triggered_~__retres1~5#1 := 0; 389004#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 389085#L386 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 389086#L760 assume !(0 != activate_threads_~tmp___4~0#1); 389143#L760-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 389144#L649 assume !(1 == ~M_E~0); 389336#L649-2 assume !(1 == ~T1_E~0); 388840#L654-1 assume !(1 == ~T2_E~0); 388841#L659-1 assume !(1 == ~T3_E~0); 389028#L664-1 assume !(1 == ~T4_E~0); 388833#L669-1 assume !(1 == ~T5_E~0); 388834#L674-1 assume !(1 == ~E_1~0); 389242#L679-1 assume !(1 == ~E_2~0); 388927#L684-1 assume !(1 == ~E_3~0); 388928#L689-1 assume !(1 == ~E_4~0); 389104#L694-1 assume !(1 == ~E_5~0); 389102#L699-1 assume { :end_inline_reset_delta_events } true; 389103#L900-2 [2021-12-16 10:05:54,928 INFO L793 eck$LassoCheckResult]: Loop: 389103#L900-2 assume !false; 396609#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 396608#L561 assume !false; 396607#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 396605#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 396604#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 396603#L472 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 396602#L486 assume 0 != eval_~tmp~0#1; 396600#L486-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 396598#L494 assume 0 != eval_~tmp_ndt_1~0#1;~m_st~0 := 1;assume { :begin_inline_master } true; 396596#L65 assume 0 == ~m_pc~0; 396555#L92 assume !false; 396595#L77 ~E_1~0 := 1;assume { :begin_inline_immediate_notify } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 396594#L279-3 assume !(1 == ~m_pc~0); 396593#L279-5 is_master_triggered_~__retres1~0#1 := 0; 396592#L290-1 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 396591#L291-1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 396590#L720-3 assume !(0 != activate_threads_~tmp~1#1); 396589#L720-5 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 396588#L298-3 assume !(1 == ~t1_pc~0); 396587#L298-5 is_transmit1_triggered_~__retres1~1#1 := 0; 396586#L309-1 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 396585#L310-1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 396584#L728-3 assume !(0 != activate_threads_~tmp___0~0#1); 396583#L728-5 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 396582#L317-3 assume !(1 == ~t2_pc~0); 396581#L317-5 is_transmit2_triggered_~__retres1~2#1 := 0; 396580#L328-1 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 396579#L329-1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 396578#L736-3 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 396577#L736-5 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 396576#L336-3 assume !(1 == ~t3_pc~0); 396575#L336-5 is_transmit3_triggered_~__retres1~3#1 := 0; 396574#L347-1 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 396573#L348-1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 396572#L744-3 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 396571#L744-5 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 396570#L355-3 assume !(1 == ~t4_pc~0); 396568#L355-5 is_transmit4_triggered_~__retres1~4#1 := 0; 396567#L366-1 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 396566#L367-1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 396565#L752-3 assume !(0 != activate_threads_~tmp___3~0#1); 396564#L752-5 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 396563#L374-3 assume !(1 == ~t5_pc~0); 396562#L374-5 is_transmit5_triggered_~__retres1~5#1 := 0; 396561#L385-1 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 396560#L386-1 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 396559#L760-3 assume !(0 != activate_threads_~tmp___4~0#1); 396558#L760-5 assume { :end_inline_activate_threads } true; 396553#L777 assume { :end_inline_immediate_notify } true;~E_1~0 := 2; 396552#L69 assume !false; 396551#L85 ~m_pc~0 := 1;~m_st~0 := 2; 396544#L95 assume { :end_inline_master } true; 396543#L491 assume !(0 == ~t1_st~0); 396541#L505 assume !(0 == ~t2_st~0); 396539#L519 assume !(0 == ~t3_st~0); 396481#L533 assume !(0 == ~t4_st~0); 396480#L547 assume !(0 == ~t5_st~0); 396476#L561 assume !false; 396475#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 396474#L439 assume !(0 == ~m_st~0); 396471#L443 assume !(0 == ~t1_st~0); 396470#L447 assume !(0 == ~t2_st~0); 396469#L451 assume !(0 == ~t3_st~0); 396468#L455 assume !(0 == ~t4_st~0); 396466#L459 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6#1 := 0; 396465#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 396464#L472 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 396462#L486 assume !(0 != eval_~tmp~0#1); 396461#L576 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 396460#L394-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 396459#L586-3 assume !(0 == ~M_E~0); 396458#L586-5 assume !(0 == ~T1_E~0); 396457#L591-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 396456#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 396455#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 396454#L606-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 396453#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 396452#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 396451#L621-3 assume !(0 == ~E_3~0); 396450#L626-3 assume !(0 == ~E_4~0); 396449#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 396448#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 396446#L279-18 assume 1 == ~m_pc~0; 396445#L280-6 assume !(1 == ~M_E~0); 396444#L279-20 is_master_triggered_~__retres1~0#1 := 0; 396443#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 396442#L291-6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 396441#L720-18 assume !(0 != activate_threads_~tmp~1#1); 396440#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 396439#L298-18 assume !(1 == ~t1_pc~0); 396438#L298-20 is_transmit1_triggered_~__retres1~1#1 := 0; 396437#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 396436#L310-6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 396435#L728-18 assume !(0 != activate_threads_~tmp___0~0#1); 396434#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 396433#L317-18 assume !(1 == ~t2_pc~0); 396432#L317-20 is_transmit2_triggered_~__retres1~2#1 := 0; 396431#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 396430#L329-6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 396429#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 396428#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 396427#L336-18 assume !(1 == ~t3_pc~0); 396426#L336-20 is_transmit3_triggered_~__retres1~3#1 := 0; 396425#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 396424#L348-6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 396423#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 396422#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 396420#L355-18 assume !(1 == ~t4_pc~0); 396419#L355-20 is_transmit4_triggered_~__retres1~4#1 := 0; 396418#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 396417#L367-6 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 396416#L752-18 assume !(0 != activate_threads_~tmp___3~0#1); 396415#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 396414#L374-18 assume !(1 == ~t5_pc~0); 396413#L374-20 is_transmit5_triggered_~__retres1~5#1 := 0; 396412#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 396411#L386-6 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 396410#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 396409#L760-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 396408#L649-3 assume !(1 == ~M_E~0); 396296#L649-5 assume !(1 == ~T1_E~0); 396407#L654-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 396406#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 396405#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 396404#L669-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 396403#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 396402#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 396401#L684-3 assume !(1 == ~E_3~0); 396400#L689-3 assume !(1 == ~E_4~0); 396399#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 396398#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 396397#L439-1 assume !(0 == ~m_st~0); 396196#L443-1 assume 0 == ~t1_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 396392#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 396391#L472-1 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 396389#L919 assume 0 == start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 4;assume { :begin_inline_fire_time_events } true;~M_E~0 := 1; 396045#L786 assume { :end_inline_fire_time_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 396387#L279-21 assume 1 == ~m_pc~0; 396386#L280-7 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 396385#L290-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 396384#L291-7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 396376#L720-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 396375#L720-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 396374#L298-21 assume !(1 == ~t1_pc~0); 396373#L298-23 is_transmit1_triggered_~__retres1~1#1 := 0; 396372#L309-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 396371#L310-7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 396370#L728-21 assume !(0 != activate_threads_~tmp___0~0#1); 396369#L728-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 396368#L317-21 assume !(1 == ~t2_pc~0); 396367#L317-23 is_transmit2_triggered_~__retres1~2#1 := 0; 396366#L328-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 396365#L329-7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 396364#L736-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 396363#L736-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 396362#L336-21 assume !(1 == ~t3_pc~0); 396361#L336-23 is_transmit3_triggered_~__retres1~3#1 := 0; 396360#L347-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 396359#L348-7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 396358#L744-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 396357#L744-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 396356#L355-21 assume !(1 == ~t4_pc~0); 396354#L355-23 is_transmit4_triggered_~__retres1~4#1 := 0; 396353#L366-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 396352#L367-7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 396351#L752-21 assume !(0 != activate_threads_~tmp___3~0#1); 396350#L752-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 396349#L374-21 assume !(1 == ~t5_pc~0); 396348#L374-23 is_transmit5_triggered_~__retres1~5#1 := 0; 396347#L385-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 396346#L386-7 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 396345#L760-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 396344#L760-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_time_events } true; 396342#L793 assume !(1 == ~M_E~0); 396341#L793-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 396340#L798-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 396339#L803-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 396338#L808-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 396337#L813-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 396336#L818-1 assume 1 == ~E_1~0;~E_1~0 := 2; 396335#L823-1 assume 1 == ~E_2~0;~E_2~0 := 2; 396334#L828-1 assume !(1 == ~E_3~0); 396333#L833-1 assume !(1 == ~E_4~0); 396332#L838-1 assume 1 == ~E_5~0;~E_5~0 := 2; 396331#L843-1 assume { :end_inline_reset_time_events } true; 396190#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 396040#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 396041#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 396511#L472-2 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 396510#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 396509#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 396508#L882 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 396507#L932 assume !(0 != start_simulation_~tmp___0~1#1); 396506#L900-2 assume !false; 396504#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 396503#L561 assume !false; 392511#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 392508#L439 assume !(0 == ~m_st~0); 392509#L443 assume !(0 == ~t1_st~0); 395981#L447 assume !(0 == ~t2_st~0); 395980#L451 assume !(0 == ~t3_st~0); 395979#L455 assume !(0 == ~t4_st~0); 395978#L459 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6#1 := 0; 395977#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 395976#L472 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 392736#L486 assume !(0 != eval_~tmp~0#1); 392737#L576 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 396262#L394-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 396261#L586-3 assume 0 == ~M_E~0;~M_E~0 := 1; 396260#L586-5 assume !(0 == ~T1_E~0); 396259#L591-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 396258#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 396257#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 396256#L606-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 396255#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 396254#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 396253#L621-3 assume !(0 == ~E_3~0); 396252#L626-3 assume !(0 == ~E_4~0); 396251#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 396250#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 396248#L279-18 assume 1 == ~m_pc~0; 396246#L280-6 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 396245#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 396244#L291-6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 396242#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 396241#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 396240#L298-18 assume !(1 == ~t1_pc~0); 396239#L298-20 is_transmit1_triggered_~__retres1~1#1 := 0; 396238#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 396237#L310-6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 396236#L728-18 assume !(0 != activate_threads_~tmp___0~0#1); 396235#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 396234#L317-18 assume !(1 == ~t2_pc~0); 396233#L317-20 is_transmit2_triggered_~__retres1~2#1 := 0; 396232#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 396231#L329-6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 396230#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 396229#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 396228#L336-18 assume !(1 == ~t3_pc~0); 396227#L336-20 is_transmit3_triggered_~__retres1~3#1 := 0; 396226#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 396225#L348-6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 396224#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 396223#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 396221#L355-18 assume !(1 == ~t4_pc~0); 396220#L355-20 is_transmit4_triggered_~__retres1~4#1 := 0; 396219#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 396218#L367-6 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 396217#L752-18 assume !(0 != activate_threads_~tmp___3~0#1); 396216#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 396215#L374-18 assume !(1 == ~t5_pc~0); 396214#L374-20 is_transmit5_triggered_~__retres1~5#1 := 0; 396213#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 396212#L386-6 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 396211#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 396210#L760-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 396208#L649-3 assume !(1 == ~M_E~0); 396209#L649-5 assume !(1 == ~T1_E~0); 396276#L654-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 396275#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 396274#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 396273#L669-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 396272#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 396271#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 396270#L684-3 assume !(1 == ~E_3~0); 396269#L689-3 assume !(1 == ~E_4~0); 396268#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 396267#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 396265#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 396264#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 396263#L472-1 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 396189#L919 assume 0 == start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 4;assume { :begin_inline_fire_time_events } true;~M_E~0 := 1; 396188#L786 assume { :end_inline_fire_time_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 396186#L279-21 assume !(1 == ~m_pc~0); 396185#L279-23 is_master_triggered_~__retres1~0#1 := 0; 396184#L290-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 396183#L291-7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 396182#L720-21 assume !(0 != activate_threads_~tmp~1#1); 396181#L720-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 396180#L298-21 assume !(1 == ~t1_pc~0); 396179#L298-23 is_transmit1_triggered_~__retres1~1#1 := 0; 396178#L309-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 396177#L310-7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 396176#L728-21 assume !(0 != activate_threads_~tmp___0~0#1); 396175#L728-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 396174#L317-21 assume !(1 == ~t2_pc~0); 396173#L317-23 is_transmit2_triggered_~__retres1~2#1 := 0; 396172#L328-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 396171#L329-7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 396170#L736-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 396169#L736-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 396168#L336-21 assume !(1 == ~t3_pc~0); 396167#L336-23 is_transmit3_triggered_~__retres1~3#1 := 0; 396166#L347-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 396165#L348-7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 396164#L744-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 396163#L744-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 396162#L355-21 assume !(1 == ~t4_pc~0); 396160#L355-23 is_transmit4_triggered_~__retres1~4#1 := 0; 396159#L366-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 396158#L367-7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 396157#L752-21 assume !(0 != activate_threads_~tmp___3~0#1); 396156#L752-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 396155#L374-21 assume !(1 == ~t5_pc~0); 396154#L374-23 is_transmit5_triggered_~__retres1~5#1 := 0; 396153#L385-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 396152#L386-7 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 396151#L760-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 396150#L760-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_time_events } true; 396148#L793 assume 1 == ~M_E~0;~M_E~0 := 2; 396149#L793-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 396687#L798-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 396686#L803-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 396685#L808-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 396684#L813-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 396683#L818-1 assume 1 == ~E_1~0;~E_1~0 := 2; 396682#L823-1 assume 1 == ~E_2~0;~E_2~0 := 2; 396681#L828-1 assume !(1 == ~E_3~0); 396680#L833-1 assume !(1 == ~E_4~0); 396679#L838-1 assume 1 == ~E_5~0;~E_5~0 := 2; 396678#L843-1 assume { :end_inline_reset_time_events } true; 396677#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 396675#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 396674#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 396673#L472-2 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 396672#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 396671#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 396670#L882 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 396669#L932 assume !(0 != start_simulation_~tmp___0~1#1); 389103#L900-2 [2021-12-16 10:05:54,929 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:54,929 INFO L85 PathProgramCache]: Analyzing trace with hash -445536100, now seen corresponding path program 7 times [2021-12-16 10:05:54,929 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:54,929 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1295950028] [2021-12-16 10:05:54,929 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:54,929 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:54,935 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:05:54,935 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-16 10:05:54,939 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:05:54,945 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-16 10:05:54,945 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:54,946 INFO L85 PathProgramCache]: Analyzing trace with hash -385293559, now seen corresponding path program 1 times [2021-12-16 10:05:54,946 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:54,946 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1213210787] [2021-12-16 10:05:54,946 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:54,946 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:54,957 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:55,155 INFO L134 CoverageAnalysis]: Checked inductivity of 147 backedges. 14 proven. 0 refuted. 0 times theorem prover too weak. 133 trivial. 0 not checked. [2021-12-16 10:05:55,155 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:55,155 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1213210787] [2021-12-16 10:05:55,155 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1213210787] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:55,155 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:55,155 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-16 10:05:55,155 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [40932448] [2021-12-16 10:05:55,156 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:55,156 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:05:55,156 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:05:55,157 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-16 10:05:55,157 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-16 10:05:55,157 INFO L87 Difference]: Start difference. First operand 35025 states and 46603 transitions. cyclomatic complexity: 11594 Second operand has 5 states, 5 states have (on average 40.8) internal successors, (204), 5 states have internal predecessors, (204), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:55,423 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:05:55,424 INFO L93 Difference]: Finished difference Result 57557 states and 76204 transitions. [2021-12-16 10:05:55,429 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-16 10:05:55,430 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 57557 states and 76204 transitions. [2021-12-16 10:05:55,874 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 57085 [2021-12-16 10:05:56,040 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 57557 states to 57557 states and 76204 transitions. [2021-12-16 10:05:56,040 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 57557 [2021-12-16 10:05:56,082 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 57557 [2021-12-16 10:05:56,082 INFO L73 IsDeterministic]: Start isDeterministic. Operand 57557 states and 76204 transitions. [2021-12-16 10:05:56,118 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:05:56,119 INFO L681 BuchiCegarLoop]: Abstraction has 57557 states and 76204 transitions. [2021-12-16 10:05:56,149 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 57557 states and 76204 transitions. [2021-12-16 10:05:56,487 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 57557 to 35679. [2021-12-16 10:05:56,515 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 35679 states, 35679 states have (on average 1.3158440539252783) internal successors, (46948), 35678 states have internal predecessors, (46948), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:56,570 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 35679 states to 35679 states and 46948 transitions. [2021-12-16 10:05:56,570 INFO L704 BuchiCegarLoop]: Abstraction has 35679 states and 46948 transitions. [2021-12-16 10:05:56,570 INFO L587 BuchiCegarLoop]: Abstraction has 35679 states and 46948 transitions. [2021-12-16 10:05:56,570 INFO L425 BuchiCegarLoop]: ======== Iteration 21============ [2021-12-16 10:05:56,570 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 35679 states and 46948 transitions. [2021-12-16 10:05:56,771 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 35367 [2021-12-16 10:05:56,771 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:05:56,771 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:05:56,773 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:56,773 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:56,773 INFO L791 eck$LassoCheckResult]: Stem: 481943#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 481905#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 481892#L863 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 481889#L394 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 481764#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 481765#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 481549#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 481550#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 481887#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 481888#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 481845#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 481518#L586 assume !(0 == ~M_E~0); 481519#L586-2 assume !(0 == ~T1_E~0); 481575#L591-1 assume !(0 == ~T2_E~0); 481711#L596-1 assume !(0 == ~T3_E~0); 481712#L601-1 assume !(0 == ~T4_E~0); 481754#L606-1 assume !(0 == ~T5_E~0); 481755#L611-1 assume !(0 == ~E_1~0); 481854#L616-1 assume !(0 == ~E_2~0); 481855#L621-1 assume !(0 == ~E_3~0); 481451#L626-1 assume !(0 == ~E_4~0); 481452#L631-1 assume !(0 == ~E_5~0); 481609#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 481447#L279 assume !(1 == ~m_pc~0); 481448#L279-2 is_master_triggered_~__retres1~0#1 := 0; 481775#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 481686#L291 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 481687#L720 assume !(0 != activate_threads_~tmp~1#1); 481774#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 481616#L298 assume !(1 == ~t1_pc~0); 481407#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 481408#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 481676#L310 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 481460#L728 assume !(0 != activate_threads_~tmp___0~0#1); 481461#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 481581#L317 assume !(1 == ~t2_pc~0); 481582#L317-2 is_transmit2_triggered_~__retres1~2#1 := 0; 481798#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 481899#L329 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 481625#L736 assume !(0 != activate_threads_~tmp___1~0#1); 481626#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 481841#L336 assume !(1 == ~t3_pc~0); 481842#L336-2 is_transmit3_triggered_~__retres1~3#1 := 0; 481922#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 481736#L348 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 481737#L744 assume !(0 != activate_threads_~tmp___2~0#1); 481784#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 481849#L355 assume !(1 == ~t4_pc~0); 481708#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 481534#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 481535#L367 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 481768#L752 assume !(0 != activate_threads_~tmp___3~0#1); 481470#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 481471#L374 assume !(1 == ~t5_pc~0); 481598#L374-2 is_transmit5_triggered_~__retres1~5#1 := 0; 481599#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 481684#L386 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 481685#L760 assume !(0 != activate_threads_~tmp___4~0#1); 481739#L760-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 481740#L649 assume !(1 == ~M_E~0); 481917#L649-2 assume !(1 == ~T1_E~0); 481436#L654-1 assume !(1 == ~T2_E~0); 481437#L659-1 assume !(1 == ~T3_E~0); 481624#L664-1 assume !(1 == ~T4_E~0); 481429#L669-1 assume !(1 == ~T5_E~0); 481430#L674-1 assume !(1 == ~E_1~0); 481836#L679-1 assume !(1 == ~E_2~0); 481522#L684-1 assume !(1 == ~E_3~0); 481523#L689-1 assume !(1 == ~E_4~0); 481704#L694-1 assume !(1 == ~E_5~0); 481702#L699-1 assume { :end_inline_reset_delta_events } true; 481703#L900-2 [2021-12-16 10:05:56,774 INFO L793 eck$LassoCheckResult]: Loop: 481703#L900-2 assume !false; 483732#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 483544#L561 assume !false; 483724#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 483725#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 483715#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 483716#L472 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 483707#L486 assume 0 != eval_~tmp~0#1; 483708#L486-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 483697#L494 assume 0 != eval_~tmp_ndt_1~0#1;~m_st~0 := 1;assume { :begin_inline_master } true; 483698#L65 assume 0 == ~m_pc~0; 483957#L92 assume !false; 484350#L77 ~E_1~0 := 1;assume { :begin_inline_immediate_notify } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 484343#L279-3 assume !(1 == ~m_pc~0); 484338#L279-5 is_master_triggered_~__retres1~0#1 := 0; 484331#L290-1 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 484323#L291-1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 484316#L720-3 assume !(0 != activate_threads_~tmp~1#1); 484307#L720-5 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 484299#L298-3 assume !(1 == ~t1_pc~0); 484291#L298-5 is_transmit1_triggered_~__retres1~1#1 := 0; 484283#L309-1 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 484275#L310-1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 484267#L728-3 assume !(0 != activate_threads_~tmp___0~0#1); 484260#L728-5 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 484253#L317-3 assume !(1 == ~t2_pc~0); 484245#L317-5 is_transmit2_triggered_~__retres1~2#1 := 0; 484236#L328-1 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 484227#L329-1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 484220#L736-3 assume !(0 != activate_threads_~tmp___1~0#1); 484213#L736-5 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 484206#L336-3 assume !(1 == ~t3_pc~0); 484198#L336-5 is_transmit3_triggered_~__retres1~3#1 := 0; 484191#L347-1 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 484185#L348-1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 484178#L744-3 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 484172#L744-5 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 484164#L355-3 assume !(1 == ~t4_pc~0); 484155#L355-5 is_transmit4_triggered_~__retres1~4#1 := 0; 484147#L366-1 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 484138#L367-1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 484132#L752-3 assume !(0 != activate_threads_~tmp___3~0#1); 484126#L752-5 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 484118#L374-3 assume !(1 == ~t5_pc~0); 484111#L374-5 is_transmit5_triggered_~__retres1~5#1 := 0; 484103#L385-1 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 484095#L386-1 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 484087#L760-3 assume !(0 != activate_threads_~tmp___4~0#1); 484078#L760-5 assume { :end_inline_activate_threads } true; 483954#L777 assume { :end_inline_immediate_notify } true;~E_1~0 := 2; 483955#L69 assume !false; 483356#L85 ~m_pc~0 := 1;~m_st~0 := 2; 483357#L95 assume { :end_inline_master } true; 483332#L491 assume !(0 == ~t1_st~0); 483317#L505 assume !(0 == ~t2_st~0); 483309#L519 assume !(0 == ~t3_st~0); 483275#L533 assume !(0 == ~t4_st~0); 483261#L547 assume !(0 == ~t5_st~0); 482900#L561 assume !false; 484666#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 484665#L439 assume !(0 == ~m_st~0); 484242#L443 assume !(0 == ~t1_st~0); 484662#L447 assume !(0 == ~t2_st~0); 484663#L451 assume !(0 == ~t3_st~0); 484664#L455 assume !(0 == ~t4_st~0); 484661#L459 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6#1 := 0; 484660#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 484657#L472 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 484653#L486 assume !(0 != eval_~tmp~0#1); 484652#L576 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 484651#L394-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 484650#L586-3 assume !(0 == ~M_E~0); 484649#L586-5 assume !(0 == ~T1_E~0); 484648#L591-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 484647#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 484646#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 484645#L606-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 484644#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 484643#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 484642#L621-3 assume !(0 == ~E_3~0); 484641#L626-3 assume !(0 == ~E_4~0); 484640#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 484639#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 484637#L279-18 assume 1 == ~m_pc~0; 484636#L280-6 assume !(1 == ~M_E~0); 484635#L279-20 is_master_triggered_~__retres1~0#1 := 0; 484634#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 484633#L291-6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 484632#L720-18 assume !(0 != activate_threads_~tmp~1#1); 484630#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 484628#L298-18 assume !(1 == ~t1_pc~0); 484626#L298-20 is_transmit1_triggered_~__retres1~1#1 := 0; 484624#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 484623#L310-6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 484620#L728-18 assume !(0 != activate_threads_~tmp___0~0#1); 484617#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 484614#L317-18 assume !(1 == ~t2_pc~0); 484611#L317-20 is_transmit2_triggered_~__retres1~2#1 := 0; 484609#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 484606#L329-6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 484603#L736-18 assume !(0 != activate_threads_~tmp___1~0#1); 484600#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 484597#L336-18 assume !(1 == ~t3_pc~0); 484594#L336-20 is_transmit3_triggered_~__retres1~3#1 := 0; 484591#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 484588#L348-6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 484585#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 484582#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 484578#L355-18 assume !(1 == ~t4_pc~0); 484575#L355-20 is_transmit4_triggered_~__retres1~4#1 := 0; 484572#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 484569#L367-6 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 484565#L752-18 assume !(0 != activate_threads_~tmp___3~0#1); 484562#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 484559#L374-18 assume !(1 == ~t5_pc~0); 484556#L374-20 is_transmit5_triggered_~__retres1~5#1 := 0; 484553#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 484549#L386-6 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 484546#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 484543#L760-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 484540#L649-3 assume !(1 == ~M_E~0); 484530#L649-5 assume !(1 == ~T1_E~0); 484535#L654-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 484532#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 484528#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 484525#L669-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 484522#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 484519#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 484516#L684-3 assume !(1 == ~E_3~0); 484511#L689-3 assume !(1 == ~E_4~0); 484508#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 484505#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 484502#L439-1 assume !(0 == ~m_st~0); 484084#L443-1 assume 0 == ~t1_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 484490#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 484491#L472-1 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 484482#L919 assume 0 == start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 4;assume { :begin_inline_fire_time_events } true;~M_E~0 := 1; 484459#L786 assume { :end_inline_fire_time_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 484467#L279-21 assume 1 == ~m_pc~0; 484468#L280-7 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 484453#L290-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 484454#L291-7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 484425#L720-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 484426#L720-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 484412#L298-21 assume !(1 == ~t1_pc~0); 484413#L298-23 is_transmit1_triggered_~__retres1~1#1 := 0; 484404#L309-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 484405#L310-7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 484395#L728-21 assume !(0 != activate_threads_~tmp___0~0#1); 484396#L728-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 484384#L317-21 assume !(1 == ~t2_pc~0); 484385#L317-23 is_transmit2_triggered_~__retres1~2#1 := 0; 484374#L328-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 484375#L329-7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 484362#L736-21 assume !(0 != activate_threads_~tmp___1~0#1); 484363#L736-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 484351#L336-21 assume !(1 == ~t3_pc~0); 484352#L336-23 is_transmit3_triggered_~__retres1~3#1 := 0; 484339#L347-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 484340#L348-7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 484325#L744-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 484326#L744-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 484311#L355-21 assume !(1 == ~t4_pc~0); 484310#L355-23 is_transmit4_triggered_~__retres1~4#1 := 0; 484293#L366-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 484294#L367-7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 484277#L752-21 assume !(0 != activate_threads_~tmp___3~0#1); 484278#L752-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 484262#L374-21 assume !(1 == ~t5_pc~0); 484263#L374-23 is_transmit5_triggered_~__retres1~5#1 := 0; 484247#L385-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 484248#L386-7 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 484229#L760-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 484230#L760-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_time_events } true; 484215#L793 assume !(1 == ~M_E~0); 484216#L793-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 484200#L798-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 484201#L803-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 484187#L808-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 484188#L813-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 484174#L818-1 assume 1 == ~E_1~0;~E_1~0 := 2; 484175#L823-1 assume 1 == ~E_2~0;~E_2~0 := 2; 484157#L828-1 assume !(1 == ~E_3~0); 484158#L833-1 assume !(1 == ~E_4~0); 484141#L838-1 assume 1 == ~E_5~0;~E_5~0 := 2; 484142#L843-1 assume { :end_inline_reset_time_events } true; 483428#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 483429#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 483421#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 483422#L472-2 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 483415#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 483416#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 491012#L882 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 483407#L932 assume !(0 != start_simulation_~tmp___0~1#1); 483408#L900-2 assume !false; 483402#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 482403#L561 assume !false; 483399#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 483396#L439 assume !(0 == ~m_st~0); 483397#L443 assume !(0 == ~t1_st~0); 484383#L447 assume !(0 == ~t2_st~0); 484378#L451 assume !(0 == ~t3_st~0); 484372#L455 assume !(0 == ~t4_st~0); 484366#L459 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6#1 := 0; 484360#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 484355#L472 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 484349#L486 assume !(0 != eval_~tmp~0#1); 484342#L576 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 484337#L394-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 484330#L586-3 assume 0 == ~M_E~0;~M_E~0 := 1; 484322#L586-5 assume !(0 == ~T1_E~0); 484314#L591-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 484315#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 484297#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 484298#L606-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 484281#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 484282#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 484265#L621-3 assume !(0 == ~E_3~0); 484266#L626-3 assume !(0 == ~E_4~0); 484251#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 484252#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 484233#L279-18 assume 1 == ~m_pc~0; 484235#L280-6 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 484218#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 484219#L291-6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 484203#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 484204#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 484189#L298-18 assume !(1 == ~t1_pc~0); 484190#L298-20 is_transmit1_triggered_~__retres1~1#1 := 0; 484176#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 484177#L310-6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 484161#L728-18 assume !(0 != activate_threads_~tmp___0~0#1); 484162#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 484145#L317-18 assume !(1 == ~t2_pc~0); 484146#L317-20 is_transmit2_triggered_~__retres1~2#1 := 0; 484130#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 484131#L329-6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 484116#L736-18 assume !(0 != activate_threads_~tmp___1~0#1); 484117#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 484101#L336-18 assume !(1 == ~t3_pc~0); 484102#L336-20 is_transmit3_triggered_~__retres1~3#1 := 0; 484085#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 484086#L348-6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 483952#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 483953#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 483518#L355-18 assume !(1 == ~t4_pc~0); 483519#L355-20 is_transmit4_triggered_~__retres1~4#1 := 0; 483511#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 483512#L367-6 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 483505#L752-18 assume !(0 != activate_threads_~tmp___3~0#1); 483506#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 483499#L374-18 assume !(1 == ~t5_pc~0); 483500#L374-20 is_transmit5_triggered_~__retres1~5#1 := 0; 483494#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 483495#L386-6 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 483488#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 483489#L760-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 483481#L649-3 assume !(1 == ~M_E~0); 483483#L649-5 assume !(1 == ~T1_E~0); 483475#L654-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 483476#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 483469#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 483470#L669-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 483463#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 483464#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 483457#L684-3 assume !(1 == ~E_3~0); 483458#L689-3 assume !(1 == ~E_4~0); 483451#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 483452#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 483444#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 483445#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 483438#L472-1 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 483439#L919 assume 0 == start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 4;assume { :begin_inline_fire_time_events } true;~M_E~0 := 1; 483946#L786 assume { :end_inline_fire_time_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 483947#L279-21 assume !(1 == ~m_pc~0); 483940#L279-23 is_master_triggered_~__retres1~0#1 := 0; 483941#L290-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 483932#L291-7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 483933#L720-21 assume !(0 != activate_threads_~tmp~1#1); 483927#L720-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 483928#L298-21 assume !(1 == ~t1_pc~0); 483918#L298-23 is_transmit1_triggered_~__retres1~1#1 := 0; 483919#L309-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 483910#L310-7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 483911#L728-21 assume !(0 != activate_threads_~tmp___0~0#1); 483906#L728-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 483907#L317-21 assume !(1 == ~t2_pc~0); 483898#L317-23 is_transmit2_triggered_~__retres1~2#1 := 0; 483899#L328-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 483892#L329-7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 483893#L736-21 assume !(0 != activate_threads_~tmp___1~0#1); 483881#L736-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 483882#L336-21 assume !(1 == ~t3_pc~0); 483873#L336-23 is_transmit3_triggered_~__retres1~3#1 := 0; 483874#L347-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 483865#L348-7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 483866#L744-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 483857#L744-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 483858#L355-21 assume !(1 == ~t4_pc~0); 483848#L355-23 is_transmit4_triggered_~__retres1~4#1 := 0; 483849#L366-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 483840#L367-7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 483841#L752-21 assume !(0 != activate_threads_~tmp___3~0#1); 483832#L752-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 483833#L374-21 assume !(1 == ~t5_pc~0); 483825#L374-23 is_transmit5_triggered_~__retres1~5#1 := 0; 483826#L385-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 483817#L386-7 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 483818#L760-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 483809#L760-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_time_events } true; 483810#L793 assume 1 == ~M_E~0;~M_E~0 := 2; 483801#L793-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 483802#L798-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 483793#L803-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 483794#L808-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 483785#L813-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 483786#L818-1 assume 1 == ~E_1~0;~E_1~0 := 2; 483777#L823-1 assume 1 == ~E_2~0;~E_2~0 := 2; 483778#L828-1 assume !(1 == ~E_3~0); 483770#L833-1 assume !(1 == ~E_4~0); 483771#L838-1 assume 1 == ~E_5~0;~E_5~0 := 2; 483762#L843-1 assume { :end_inline_reset_time_events } true; 483763#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 483755#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 483756#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 483751#L472-2 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 483752#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 483745#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 483746#L882 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 483739#L932 assume !(0 != start_simulation_~tmp___0~1#1); 481703#L900-2 [2021-12-16 10:05:56,774 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:56,774 INFO L85 PathProgramCache]: Analyzing trace with hash -445536100, now seen corresponding path program 8 times [2021-12-16 10:05:56,775 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:56,775 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1624490631] [2021-12-16 10:05:56,775 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:56,775 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:56,780 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:05:56,780 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-16 10:05:56,783 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:05:56,790 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-16 10:05:56,790 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:56,790 INFO L85 PathProgramCache]: Analyzing trace with hash 1035898823, now seen corresponding path program 1 times [2021-12-16 10:05:56,790 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:56,790 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1149445653] [2021-12-16 10:05:56,791 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:56,791 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:56,799 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:56,826 INFO L134 CoverageAnalysis]: Checked inductivity of 147 backedges. 14 proven. 0 refuted. 0 times theorem prover too weak. 133 trivial. 0 not checked. [2021-12-16 10:05:56,826 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:56,826 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1149445653] [2021-12-16 10:05:56,826 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1149445653] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:56,826 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:56,827 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-16 10:05:56,827 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1222961705] [2021-12-16 10:05:56,827 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:56,827 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:05:56,827 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:05:56,828 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-16 10:05:56,828 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-16 10:05:56,828 INFO L87 Difference]: Start difference. First operand 35679 states and 46948 transitions. cyclomatic complexity: 11285 Second operand has 5 states, 5 states have (on average 40.8) internal successors, (204), 5 states have internal predecessors, (204), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:56,994 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:05:56,994 INFO L93 Difference]: Finished difference Result 42376 states and 55251 transitions. [2021-12-16 10:05:56,995 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-16 10:05:56,995 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 42376 states and 55251 transitions. [2021-12-16 10:05:57,154 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 42032 [2021-12-16 10:05:57,248 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 42376 states to 42376 states and 55251 transitions. [2021-12-16 10:05:57,249 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 42376 [2021-12-16 10:05:57,275 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 42376 [2021-12-16 10:05:57,276 INFO L73 IsDeterministic]: Start isDeterministic. Operand 42376 states and 55251 transitions. [2021-12-16 10:05:57,300 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:05:57,301 INFO L681 BuchiCegarLoop]: Abstraction has 42376 states and 55251 transitions. [2021-12-16 10:05:57,323 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 42376 states and 55251 transitions. [2021-12-16 10:05:57,730 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 42376 to 35751. [2021-12-16 10:05:57,759 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 35751 states, 35751 states have (on average 1.3011384296942743) internal successors, (46517), 35750 states have internal predecessors, (46517), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:57,816 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 35751 states to 35751 states and 46517 transitions. [2021-12-16 10:05:57,816 INFO L704 BuchiCegarLoop]: Abstraction has 35751 states and 46517 transitions. [2021-12-16 10:05:57,816 INFO L587 BuchiCegarLoop]: Abstraction has 35751 states and 46517 transitions. [2021-12-16 10:05:57,816 INFO L425 BuchiCegarLoop]: ======== Iteration 22============ [2021-12-16 10:05:57,816 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 35751 states and 46517 transitions. [2021-12-16 10:05:57,910 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 35439 [2021-12-16 10:05:57,911 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:05:57,911 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:05:57,914 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:57,914 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:57,914 INFO L791 eck$LassoCheckResult]: Stem: 560051#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 559991#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 559979#L863 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 559974#L394 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 559838#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 559839#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 559620#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 559621#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 559972#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 559973#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 559926#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 559593#L586 assume !(0 == ~M_E~0); 559594#L586-2 assume !(0 == ~T1_E~0); 559645#L591-1 assume !(0 == ~T2_E~0); 559783#L596-1 assume !(0 == ~T3_E~0); 559784#L601-1 assume !(0 == ~T4_E~0); 559826#L606-1 assume !(0 == ~T5_E~0); 559827#L611-1 assume !(0 == ~E_1~0); 559937#L616-1 assume !(0 == ~E_2~0); 559938#L621-1 assume !(0 == ~E_3~0); 559519#L626-1 assume !(0 == ~E_4~0); 559520#L631-1 assume !(0 == ~E_5~0); 559679#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 559517#L279 assume !(1 == ~m_pc~0); 559518#L279-2 is_master_triggered_~__retres1~0#1 := 0; 559852#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 559757#L291 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 559758#L720 assume !(0 != activate_threads_~tmp~1#1); 559851#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 559686#L298 assume !(1 == ~t1_pc~0); 559478#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 559479#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 559747#L310 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 559528#L728 assume !(0 != activate_threads_~tmp___0~0#1); 559529#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 559650#L317 assume !(1 == ~t2_pc~0); 559651#L317-2 is_transmit2_triggered_~__retres1~2#1 := 0; 559875#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 559986#L329 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 559700#L736 assume !(0 != activate_threads_~tmp___1~0#1); 559701#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 559922#L336 assume !(1 == ~t3_pc~0); 559923#L336-2 is_transmit3_triggered_~__retres1~3#1 := 0; 560022#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 559810#L348 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 559811#L744 assume !(0 != activate_threads_~tmp___2~0#1); 559862#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 559930#L355 assume !(1 == ~t4_pc~0); 559782#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 559607#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 559608#L367 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 559844#L752 assume !(0 != activate_threads_~tmp___3~0#1); 559542#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 559543#L374 assume !(1 == ~t5_pc~0); 559672#L374-2 is_transmit5_triggered_~__retres1~5#1 := 0; 559673#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 559755#L386 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 559756#L760 assume !(0 != activate_threads_~tmp___4~0#1); 559813#L760-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 559814#L649 assume !(1 == ~M_E~0); 560012#L649-2 assume !(1 == ~T1_E~0); 559504#L654-1 assume !(1 == ~T2_E~0); 559505#L659-1 assume !(1 == ~T3_E~0); 559693#L664-1 assume !(1 == ~T4_E~0); 559497#L669-1 assume !(1 == ~T5_E~0); 559498#L674-1 assume !(1 == ~E_1~0); 559913#L679-1 assume !(1 == ~E_2~0); 559595#L684-1 assume !(1 == ~E_3~0); 559596#L689-1 assume !(1 == ~E_4~0); 559776#L694-1 assume !(1 == ~E_5~0); 559772#L699-1 assume { :end_inline_reset_delta_events } true; 559773#L900-2 [2021-12-16 10:05:57,914 INFO L793 eck$LassoCheckResult]: Loop: 559773#L900-2 assume !false; 569990#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 562684#L561 assume !false; 569987#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 569984#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 569982#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 569980#L472 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 569978#L486 assume 0 != eval_~tmp~0#1; 569975#L486-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 569972#L494 assume 0 != eval_~tmp_ndt_1~0#1;~m_st~0 := 1;assume { :begin_inline_master } true; 569973#L65 assume 0 == ~m_pc~0; 570210#L92 assume !false; 570286#L77 ~E_1~0 := 1;assume { :begin_inline_immediate_notify } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 570285#L279-3 assume !(1 == ~m_pc~0); 570284#L279-5 is_master_triggered_~__retres1~0#1 := 0; 570281#L290-1 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 570279#L291-1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 570277#L720-3 assume !(0 != activate_threads_~tmp~1#1); 570275#L720-5 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 570273#L298-3 assume !(1 == ~t1_pc~0); 570271#L298-5 is_transmit1_triggered_~__retres1~1#1 := 0; 570269#L309-1 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 570267#L310-1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 570265#L728-3 assume !(0 != activate_threads_~tmp___0~0#1); 570263#L728-5 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 570261#L317-3 assume !(1 == ~t2_pc~0); 570259#L317-5 is_transmit2_triggered_~__retres1~2#1 := 0; 570257#L328-1 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 570255#L329-1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 570253#L736-3 assume !(0 != activate_threads_~tmp___1~0#1); 570251#L736-5 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 570249#L336-3 assume !(1 == ~t3_pc~0); 570247#L336-5 is_transmit3_triggered_~__retres1~3#1 := 0; 570245#L347-1 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 570243#L348-1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 570241#L744-3 assume !(0 != activate_threads_~tmp___2~0#1); 570239#L744-5 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 570237#L355-3 assume !(1 == ~t4_pc~0); 570234#L355-5 is_transmit4_triggered_~__retres1~4#1 := 0; 570232#L366-1 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 570231#L367-1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 570228#L752-3 assume !(0 != activate_threads_~tmp___3~0#1); 570226#L752-5 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 570224#L374-3 assume !(1 == ~t5_pc~0); 570222#L374-5 is_transmit5_triggered_~__retres1~5#1 := 0; 570220#L385-1 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 570218#L386-1 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 570216#L760-3 assume !(0 != activate_threads_~tmp___4~0#1); 570214#L760-5 assume { :end_inline_activate_threads } true; 570208#L777 assume { :end_inline_immediate_notify } true;~E_1~0 := 2; 570206#L69 assume !false; 570205#L85 ~m_pc~0 := 1;~m_st~0 := 2; 570204#L95 assume { :end_inline_master } true; 568400#L491 assume !(0 == ~t1_st~0); 570198#L505 assume !(0 == ~t2_st~0); 570195#L519 assume !(0 == ~t3_st~0); 570087#L533 assume !(0 == ~t4_st~0); 569951#L547 assume !(0 == ~t5_st~0); 569943#L561 assume !false; 569939#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 568077#L439 assume !(0 == ~m_st~0); 568075#L443 assume !(0 == ~t1_st~0); 568073#L447 assume !(0 == ~t2_st~0); 568071#L451 assume !(0 == ~t3_st~0); 568068#L455 assume !(0 == ~t4_st~0); 568065#L459 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6#1 := 0; 568063#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 568060#L472 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 568058#L486 assume !(0 != eval_~tmp~0#1); 568055#L576 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 568052#L394-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 568050#L586-3 assume !(0 == ~M_E~0); 568048#L586-5 assume !(0 == ~T1_E~0); 568046#L591-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 568041#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 568039#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 568038#L606-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 568034#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 568032#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 568030#L621-3 assume !(0 == ~E_3~0); 568028#L626-3 assume !(0 == ~E_4~0); 568025#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 568023#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 568020#L279-18 assume 1 == ~m_pc~0; 568019#L280-6 assume !(1 == ~M_E~0); 568017#L279-20 is_master_triggered_~__retres1~0#1 := 0; 568015#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 568013#L291-6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 568011#L720-18 assume !(0 != activate_threads_~tmp~1#1); 568009#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 568007#L298-18 assume !(1 == ~t1_pc~0); 568005#L298-20 is_transmit1_triggered_~__retres1~1#1 := 0; 568003#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 568001#L310-6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 567999#L728-18 assume !(0 != activate_threads_~tmp___0~0#1); 567996#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 567994#L317-18 assume !(1 == ~t2_pc~0); 567992#L317-20 is_transmit2_triggered_~__retres1~2#1 := 0; 567990#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 567988#L329-6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 567986#L736-18 assume !(0 != activate_threads_~tmp___1~0#1); 567984#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 567983#L336-18 assume !(1 == ~t3_pc~0); 567981#L336-20 is_transmit3_triggered_~__retres1~3#1 := 0; 567979#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 567977#L348-6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 567975#L744-18 assume !(0 != activate_threads_~tmp___2~0#1); 567972#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 567895#L355-18 assume !(1 == ~t4_pc~0); 567892#L355-20 is_transmit4_triggered_~__retres1~4#1 := 0; 567890#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 567888#L367-6 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 567876#L752-18 assume !(0 != activate_threads_~tmp___3~0#1); 567871#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 567870#L374-18 assume !(1 == ~t5_pc~0); 567869#L374-20 is_transmit5_triggered_~__retres1~5#1 := 0; 567868#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 567867#L386-6 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 567866#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 567865#L760-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 567864#L649-3 assume !(1 == ~M_E~0); 567625#L649-5 assume !(1 == ~T1_E~0); 567861#L654-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 567859#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 567858#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 567856#L669-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 567854#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 567852#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 567850#L684-3 assume !(1 == ~E_3~0); 567848#L689-3 assume !(1 == ~E_4~0); 567846#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 567844#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 567842#L439-1 assume !(0 == ~m_st~0); 567657#L443-1 assume 0 == ~t1_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 567832#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 567830#L472-1 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 567827#L919 assume 0 == start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 4;assume { :begin_inline_fire_time_events } true;~M_E~0 := 1; 567539#L786 assume { :end_inline_fire_time_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 567823#L279-21 assume 1 == ~m_pc~0; 567820#L280-7 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 567819#L290-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 567818#L291-7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 567693#L720-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 567691#L720-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 567689#L298-21 assume !(1 == ~t1_pc~0); 567686#L298-23 is_transmit1_triggered_~__retres1~1#1 := 0; 567684#L309-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 567682#L310-7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 567680#L728-21 assume !(0 != activate_threads_~tmp___0~0#1); 567678#L728-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 567676#L317-21 assume !(1 == ~t2_pc~0); 567674#L317-23 is_transmit2_triggered_~__retres1~2#1 := 0; 567672#L328-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 567670#L329-7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 567668#L736-21 assume !(0 != activate_threads_~tmp___1~0#1); 567666#L736-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 567664#L336-21 assume !(1 == ~t3_pc~0); 567662#L336-23 is_transmit3_triggered_~__retres1~3#1 := 0; 567661#L347-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 567660#L348-7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 567659#L744-21 assume !(0 != activate_threads_~tmp___2~0#1); 567658#L744-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 567449#L355-21 assume !(1 == ~t4_pc~0); 567445#L355-23 is_transmit4_triggered_~__retres1~4#1 := 0; 567443#L366-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 567441#L367-7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 567438#L752-21 assume !(0 != activate_threads_~tmp___3~0#1); 567436#L752-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 567434#L374-21 assume !(1 == ~t5_pc~0); 567432#L374-23 is_transmit5_triggered_~__retres1~5#1 := 0; 567429#L385-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 567427#L386-7 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 567425#L760-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 567422#L760-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_time_events } true; 567419#L793 assume !(1 == ~M_E~0); 567417#L793-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 567415#L798-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 567413#L803-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 567410#L808-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 567407#L813-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 567398#L818-1 assume 1 == ~E_1~0;~E_1~0 := 2; 567389#L823-1 assume 1 == ~E_2~0;~E_2~0 := 2; 567388#L828-1 assume !(1 == ~E_3~0); 567387#L833-1 assume !(1 == ~E_4~0); 567386#L838-1 assume 1 == ~E_5~0;~E_5~0 := 2; 567271#L843-1 assume { :end_inline_reset_time_events } true; 567269#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 567267#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 567266#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 567265#L472-2 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 567264#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 567263#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 567262#L882 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 567261#L932 assume !(0 != start_simulation_~tmp___0~1#1); 567260#L900-2 assume !false; 567258#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 567257#L561 assume !false; 567256#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 567254#L439 assume !(0 == ~m_st~0); 567255#L443 assume !(0 == ~t1_st~0); 567493#L447 assume !(0 == ~t2_st~0); 567491#L451 assume !(0 == ~t3_st~0); 567489#L455 assume !(0 == ~t4_st~0); 567486#L459 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6#1 := 0; 567484#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 567482#L472 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 567479#L486 assume !(0 != eval_~tmp~0#1); 567477#L576 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 567475#L394-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 567473#L586-3 assume 0 == ~M_E~0;~M_E~0 := 1; 567471#L586-5 assume !(0 == ~T1_E~0); 567469#L591-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 567467#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 567465#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 567463#L606-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 567461#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 567460#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 567459#L621-3 assume !(0 == ~E_3~0); 567458#L626-3 assume !(0 == ~E_4~0); 567455#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 567453#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 567450#L279-18 assume 1 == ~m_pc~0; 567446#L280-6 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 567444#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 567442#L291-6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 567439#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 567437#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 567435#L298-18 assume !(1 == ~t1_pc~0); 567433#L298-20 is_transmit1_triggered_~__retres1~1#1 := 0; 567399#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 567396#L310-6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 567360#L728-18 assume !(0 != activate_threads_~tmp___0~0#1); 567359#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 567356#L317-18 assume !(1 == ~t2_pc~0); 567354#L317-20 is_transmit2_triggered_~__retres1~2#1 := 0; 567351#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 567349#L329-6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 567347#L736-18 assume !(0 != activate_threads_~tmp___1~0#1); 567345#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 567343#L336-18 assume !(1 == ~t3_pc~0); 567341#L336-20 is_transmit3_triggered_~__retres1~3#1 := 0; 567339#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 567337#L348-6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 567334#L744-18 assume !(0 != activate_threads_~tmp___2~0#1); 567332#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 567326#L355-18 assume !(1 == ~t4_pc~0); 567324#L355-20 is_transmit4_triggered_~__retres1~4#1 := 0; 567322#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 567321#L367-6 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 567319#L752-18 assume !(0 != activate_threads_~tmp___3~0#1); 567317#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 567315#L374-18 assume !(1 == ~t5_pc~0); 567313#L374-20 is_transmit5_triggered_~__retres1~5#1 := 0; 567311#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 567309#L386-6 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 567307#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 567305#L760-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 567302#L649-3 assume !(1 == ~M_E~0); 567300#L649-5 assume !(1 == ~T1_E~0); 567299#L654-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 567296#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 567294#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 567292#L669-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 567290#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 567288#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 567286#L684-3 assume !(1 == ~E_3~0); 567284#L689-3 assume !(1 == ~E_4~0); 567282#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 567280#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 567277#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 567275#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 567274#L472-1 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 567270#L919 assume 0 == start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 4;assume { :begin_inline_fire_time_events } true;~M_E~0 := 1; 567159#L786 assume { :end_inline_fire_time_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 567152#L279-21 assume !(1 == ~m_pc~0); 567145#L279-23 is_master_triggered_~__retres1~0#1 := 0; 567139#L290-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 567133#L291-7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 567126#L720-21 assume !(0 != activate_threads_~tmp~1#1); 567122#L720-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 567115#L298-21 assume !(1 == ~t1_pc~0); 567108#L298-23 is_transmit1_triggered_~__retres1~1#1 := 0; 567102#L309-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 567096#L310-7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 567089#L728-21 assume !(0 != activate_threads_~tmp___0~0#1); 567080#L728-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 567073#L317-21 assume !(1 == ~t2_pc~0); 567067#L317-23 is_transmit2_triggered_~__retres1~2#1 := 0; 567062#L328-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 567055#L329-7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 567050#L736-21 assume !(0 != activate_threads_~tmp___1~0#1); 567045#L736-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 567038#L336-21 assume !(1 == ~t3_pc~0); 567032#L336-23 is_transmit3_triggered_~__retres1~3#1 := 0; 567026#L347-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 567020#L348-7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 567015#L744-21 assume !(0 != activate_threads_~tmp___2~0#1); 567008#L744-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 567001#L355-21 assume !(1 == ~t4_pc~0); 566993#L355-23 is_transmit4_triggered_~__retres1~4#1 := 0; 566988#L366-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 566979#L367-7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 566971#L752-21 assume !(0 != activate_threads_~tmp___3~0#1); 566962#L752-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 566953#L374-21 assume !(1 == ~t5_pc~0); 566946#L374-23 is_transmit5_triggered_~__retres1~5#1 := 0; 566941#L385-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 566934#L386-7 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 566927#L760-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 566921#L760-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_time_events } true; 566914#L793 assume 1 == ~M_E~0;~M_E~0 := 2; 566915#L793-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 570689#L798-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 570369#L803-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 570365#L808-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 570358#L813-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 570353#L818-1 assume 1 == ~E_1~0;~E_1~0 := 2; 570348#L823-1 assume 1 == ~E_2~0;~E_2~0 := 2; 570336#L828-1 assume !(1 == ~E_3~0); 570327#L833-1 assume !(1 == ~E_4~0); 570318#L838-1 assume 1 == ~E_5~0;~E_5~0 := 2; 570301#L843-1 assume { :end_inline_reset_time_events } true; 570293#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 570288#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 570091#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 570082#L472-2 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 570076#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 570075#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 570074#L882 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 570073#L932 assume !(0 != start_simulation_~tmp___0~1#1); 559773#L900-2 [2021-12-16 10:05:57,915 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:57,915 INFO L85 PathProgramCache]: Analyzing trace with hash -445536100, now seen corresponding path program 9 times [2021-12-16 10:05:57,915 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:57,915 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [58297845] [2021-12-16 10:05:57,916 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:57,916 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:57,920 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:05:57,920 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-16 10:05:57,924 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:05:57,930 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-16 10:05:57,931 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:57,931 INFO L85 PathProgramCache]: Analyzing trace with hash 74195717, now seen corresponding path program 1 times [2021-12-16 10:05:57,931 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:57,931 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [711450246] [2021-12-16 10:05:57,931 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:57,931 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:57,940 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:57,963 INFO L134 CoverageAnalysis]: Checked inductivity of 147 backedges. 34 proven. 0 refuted. 0 times theorem prover too weak. 113 trivial. 0 not checked. [2021-12-16 10:05:57,963 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:57,963 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [711450246] [2021-12-16 10:05:57,963 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [711450246] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:57,964 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:57,964 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:05:57,964 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [887573110] [2021-12-16 10:05:57,964 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:57,964 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:05:57,964 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:05:57,965 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-16 10:05:57,965 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-16 10:05:57,965 INFO L87 Difference]: Start difference. First operand 35751 states and 46517 transitions. cyclomatic complexity: 10782 Second operand has 3 states, 3 states have (on average 74.33333333333333) internal successors, (223), 3 states have internal predecessors, (223), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:58,066 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:05:58,067 INFO L93 Difference]: Finished difference Result 34959 states and 44871 transitions. [2021-12-16 10:05:58,067 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-16 10:05:58,067 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 34959 states and 44871 transitions. [2021-12-16 10:05:58,202 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 34647 [2021-12-16 10:05:58,520 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 34959 states to 34959 states and 44871 transitions. [2021-12-16 10:05:58,521 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 34959 [2021-12-16 10:05:58,540 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 34959 [2021-12-16 10:05:58,541 INFO L73 IsDeterministic]: Start isDeterministic. Operand 34959 states and 44871 transitions. [2021-12-16 10:05:58,560 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:05:58,560 INFO L681 BuchiCegarLoop]: Abstraction has 34959 states and 44871 transitions. [2021-12-16 10:05:58,579 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 34959 states and 44871 transitions. [2021-12-16 10:05:58,886 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 34959 to 34959. [2021-12-16 10:05:58,914 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 34959 states, 34959 states have (on average 1.283532137646958) internal successors, (44871), 34958 states have internal predecessors, (44871), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:58,969 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 34959 states to 34959 states and 44871 transitions. [2021-12-16 10:05:58,970 INFO L704 BuchiCegarLoop]: Abstraction has 34959 states and 44871 transitions. [2021-12-16 10:05:58,970 INFO L587 BuchiCegarLoop]: Abstraction has 34959 states and 44871 transitions. [2021-12-16 10:05:58,970 INFO L425 BuchiCegarLoop]: ======== Iteration 23============ [2021-12-16 10:05:58,970 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 34959 states and 44871 transitions. [2021-12-16 10:05:59,061 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 34647 [2021-12-16 10:05:59,063 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:05:59,064 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:05:59,081 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:59,081 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:05:59,081 INFO L791 eck$LassoCheckResult]: Stem: 630717#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 630675#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 630661#L863 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 630658#L394 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 630538#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 630539#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 630328#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 630329#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 630656#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 630657#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 630619#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 630300#L586 assume !(0 == ~M_E~0); 630301#L586-2 assume !(0 == ~T1_E~0); 630352#L591-1 assume !(0 == ~T2_E~0); 630484#L596-1 assume !(0 == ~T3_E~0); 630485#L601-1 assume !(0 == ~T4_E~0); 630527#L606-1 assume !(0 == ~T5_E~0); 630528#L611-1 assume !(0 == ~E_1~0); 630626#L616-1 assume !(0 == ~E_2~0); 630627#L621-1 assume !(0 == ~E_3~0); 630232#L626-1 assume !(0 == ~E_4~0); 630233#L631-1 assume !(0 == ~E_5~0); 630384#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 630228#L279 assume !(1 == ~m_pc~0); 630229#L279-2 is_master_triggered_~__retres1~0#1 := 0; 630550#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 630459#L291 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 630460#L720 assume !(0 != activate_threads_~tmp~1#1); 630549#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 630390#L298 assume !(1 == ~t1_pc~0); 630190#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 630191#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 630448#L310 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 630242#L728 assume !(0 != activate_threads_~tmp___0~0#1); 630243#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 630357#L317 assume !(1 == ~t2_pc~0); 630358#L317-2 is_transmit2_triggered_~__retres1~2#1 := 0; 630571#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 630668#L329 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 630398#L736 assume !(0 != activate_threads_~tmp___1~0#1); 630399#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 630614#L336 assume !(1 == ~t3_pc~0); 630615#L336-2 is_transmit3_triggered_~__retres1~3#1 := 0; 630696#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 630510#L348 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 630511#L744 assume !(0 != activate_threads_~tmp___2~0#1); 630560#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 630623#L355 assume !(1 == ~t4_pc~0); 630481#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 630314#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 630315#L367 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 630543#L752 assume !(0 != activate_threads_~tmp___3~0#1); 630253#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 630254#L374 assume !(1 == ~t5_pc~0); 630374#L374-2 is_transmit5_triggered_~__retres1~5#1 := 0; 630375#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 630457#L386 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 630458#L760 assume !(0 != activate_threads_~tmp___4~0#1); 630513#L760-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 630514#L649 assume !(1 == ~M_E~0); 630687#L649-2 assume !(1 == ~T1_E~0); 630217#L654-1 assume !(1 == ~T2_E~0); 630218#L659-1 assume !(1 == ~T3_E~0); 630397#L664-1 assume !(1 == ~T4_E~0); 630210#L669-1 assume !(1 == ~T5_E~0); 630211#L674-1 assume !(1 == ~E_1~0); 630609#L679-1 assume !(1 == ~E_2~0); 630304#L684-1 assume !(1 == ~E_3~0); 630305#L689-1 assume !(1 == ~E_4~0); 630477#L694-1 assume !(1 == ~E_5~0); 630475#L699-1 assume { :end_inline_reset_delta_events } true; 630476#L900-2 [2021-12-16 10:05:59,082 INFO L793 eck$LassoCheckResult]: Loop: 630476#L900-2 assume !false; 640238#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 640237#L561 assume !false; 640236#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 640234#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 640233#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 640232#L472 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 640231#L486 assume 0 != eval_~tmp~0#1; 640229#L486-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 640228#L494 assume 0 != eval_~tmp_ndt_1~0#1;~m_st~0 := 1;assume { :begin_inline_master } true; 640226#L65 assume 0 == ~m_pc~0; 640185#L92 assume !false; 640225#L77 ~E_1~0 := 1;assume { :begin_inline_immediate_notify } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 640224#L279-3 assume !(1 == ~m_pc~0); 640223#L279-5 is_master_triggered_~__retres1~0#1 := 0; 640222#L290-1 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 640221#L291-1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 640220#L720-3 assume !(0 != activate_threads_~tmp~1#1); 640219#L720-5 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 640218#L298-3 assume !(1 == ~t1_pc~0); 640217#L298-5 is_transmit1_triggered_~__retres1~1#1 := 0; 640216#L309-1 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 640215#L310-1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 640214#L728-3 assume !(0 != activate_threads_~tmp___0~0#1); 640213#L728-5 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 640212#L317-3 assume !(1 == ~t2_pc~0); 640211#L317-5 is_transmit2_triggered_~__retres1~2#1 := 0; 640210#L328-1 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 640209#L329-1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 640208#L736-3 assume !(0 != activate_threads_~tmp___1~0#1); 640207#L736-5 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 640206#L336-3 assume !(1 == ~t3_pc~0); 640205#L336-5 is_transmit3_triggered_~__retres1~3#1 := 0; 640204#L347-1 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 640203#L348-1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 640202#L744-3 assume !(0 != activate_threads_~tmp___2~0#1); 640201#L744-5 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 640200#L355-3 assume !(1 == ~t4_pc~0); 640198#L355-5 is_transmit4_triggered_~__retres1~4#1 := 0; 640197#L366-1 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 640196#L367-1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 640195#L752-3 assume !(0 != activate_threads_~tmp___3~0#1); 640194#L752-5 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 640193#L374-3 assume !(1 == ~t5_pc~0); 640192#L374-5 is_transmit5_triggered_~__retres1~5#1 := 0; 640191#L385-1 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 640190#L386-1 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 640189#L760-3 assume !(0 != activate_threads_~tmp___4~0#1); 640188#L760-5 assume { :end_inline_activate_threads } true; 640183#L777 assume { :end_inline_immediate_notify } true;~E_1~0 := 2; 640182#L69 assume !false; 633291#L85 ~m_pc~0 := 1;~m_st~0 := 2; 633282#L95 assume { :end_inline_master } true; 633275#L491 assume !(0 == ~t1_st~0); 633263#L505 assume !(0 == ~t2_st~0); 633251#L519 assume !(0 == ~t3_st~0); 636387#L533 assume !(0 == ~t4_st~0); 636189#L547 assume !(0 == ~t5_st~0); 636184#L561 assume !false; 636183#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 636181#L439 assume !(0 == ~m_st~0); 633311#L443 assume !(0 == ~t1_st~0); 636178#L447 assume !(0 == ~t2_st~0); 636176#L451 assume !(0 == ~t3_st~0); 636174#L455 assume !(0 == ~t4_st~0); 636171#L459 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6#1 := 0; 636169#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 636167#L472 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 636165#L486 assume !(0 != eval_~tmp~0#1); 636163#L576 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 636161#L394-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 636159#L586-3 assume !(0 == ~M_E~0); 636157#L586-5 assume !(0 == ~T1_E~0); 636155#L591-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 636153#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 636151#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 636149#L606-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 636147#L611-3 assume !(0 == ~E_1~0); 636144#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 636142#L621-3 assume !(0 == ~E_3~0); 636140#L626-3 assume !(0 == ~E_4~0); 636138#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 636136#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 636133#L279-18 assume 1 == ~m_pc~0; 636131#L280-6 assume !(1 == ~M_E~0); 636129#L279-20 is_master_triggered_~__retres1~0#1 := 0; 636127#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 636125#L291-6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 636123#L720-18 assume !(0 != activate_threads_~tmp~1#1); 636122#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 636121#L298-18 assume !(1 == ~t1_pc~0); 636119#L298-20 is_transmit1_triggered_~__retres1~1#1 := 0; 636117#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 636115#L310-6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 636114#L728-18 assume !(0 != activate_threads_~tmp___0~0#1); 636112#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 636110#L317-18 assume !(1 == ~t2_pc~0); 636108#L317-20 is_transmit2_triggered_~__retres1~2#1 := 0; 636106#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 636104#L329-6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 636102#L736-18 assume !(0 != activate_threads_~tmp___1~0#1); 636100#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 636098#L336-18 assume !(1 == ~t3_pc~0); 636096#L336-20 is_transmit3_triggered_~__retres1~3#1 := 0; 636094#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 636092#L348-6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 636090#L744-18 assume !(0 != activate_threads_~tmp___2~0#1); 636088#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 636084#L355-18 assume !(1 == ~t4_pc~0); 636082#L355-20 is_transmit4_triggered_~__retres1~4#1 := 0; 636080#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 636078#L367-6 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 636077#L752-18 assume !(0 != activate_threads_~tmp___3~0#1); 636074#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 636072#L374-18 assume !(1 == ~t5_pc~0); 636070#L374-20 is_transmit5_triggered_~__retres1~5#1 := 0; 636068#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 636066#L386-6 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 636064#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 636062#L760-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 636060#L649-3 assume !(1 == ~M_E~0); 636052#L649-5 assume !(1 == ~T1_E~0); 636057#L654-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 636055#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 636053#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 636050#L669-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 636048#L674-3 assume !(1 == ~E_1~0); 636046#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 636044#L684-3 assume !(1 == ~E_3~0); 636042#L689-3 assume !(1 == ~E_4~0); 636040#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 636038#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 636020#L439-1 assume !(0 == ~m_st~0); 633574#L443-1 assume 0 == ~t1_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 635807#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 635808#L472-1 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 634073#L919 assume 0 == start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 4;assume { :begin_inline_fire_time_events } true;~M_E~0 := 1; 634071#L786 assume { :end_inline_fire_time_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 634068#L279-21 assume 1 == ~m_pc~0; 634065#L280-7 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 634063#L290-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 634061#L291-7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 634041#L720-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 634040#L720-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 634037#L298-21 assume !(1 == ~t1_pc~0); 634035#L298-23 is_transmit1_triggered_~__retres1~1#1 := 0; 634033#L309-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 634031#L310-7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 634029#L728-21 assume !(0 != activate_threads_~tmp___0~0#1); 634027#L728-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 633716#L317-21 assume !(1 == ~t2_pc~0); 633712#L317-23 is_transmit2_triggered_~__retres1~2#1 := 0; 633708#L328-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 633704#L329-7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 633700#L736-21 assume !(0 != activate_threads_~tmp___1~0#1); 633696#L736-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 633692#L336-21 assume !(1 == ~t3_pc~0); 633688#L336-23 is_transmit3_triggered_~__retres1~3#1 := 0; 633683#L347-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 633678#L348-7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 633674#L744-21 assume !(0 != activate_threads_~tmp___2~0#1); 633669#L744-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 633666#L355-21 assume !(1 == ~t4_pc~0); 633660#L355-23 is_transmit4_triggered_~__retres1~4#1 := 0; 633656#L366-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 633653#L367-7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 633649#L752-21 assume !(0 != activate_threads_~tmp___3~0#1); 633645#L752-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 633641#L374-21 assume !(1 == ~t5_pc~0); 633636#L374-23 is_transmit5_triggered_~__retres1~5#1 := 0; 633632#L385-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 633627#L386-7 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 633622#L760-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 633618#L760-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_time_events } true; 633613#L793 assume !(1 == ~M_E~0); 633614#L793-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 634861#L798-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 634859#L803-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 634857#L808-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 634855#L813-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 634853#L818-1 assume !(1 == ~E_1~0); 634851#L823-1 assume 1 == ~E_2~0;~E_2~0 := 2; 634849#L828-1 assume !(1 == ~E_3~0); 634847#L833-1 assume !(1 == ~E_4~0); 634845#L838-1 assume 1 == ~E_5~0;~E_5~0 := 2; 634843#L843-1 assume { :end_inline_reset_time_events } true; 633672#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 634839#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 634837#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 634836#L472-2 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 634833#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 634831#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 634829#L882 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 634827#L932 assume !(0 != start_simulation_~tmp___0~1#1); 634825#L900-2 assume !false; 634798#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 634796#L561 assume !false; 634794#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 634793#L439 assume !(0 == ~m_st~0); 634023#L443 assume !(0 == ~t1_st~0); 634021#L447 assume !(0 == ~t2_st~0); 634019#L451 assume !(0 == ~t3_st~0); 634017#L455 assume !(0 == ~t4_st~0); 634013#L459 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6#1 := 0; 634012#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 634008#L472 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 634005#L486 assume !(0 != eval_~tmp~0#1); 634003#L576 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 634002#L394-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 633996#L586-3 assume 0 == ~M_E~0;~M_E~0 := 1; 633991#L586-5 assume !(0 == ~T1_E~0); 633989#L591-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 633987#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 633984#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 633982#L606-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 633980#L611-3 assume !(0 == ~E_1~0); 633979#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 633978#L621-3 assume !(0 == ~E_3~0); 633977#L626-3 assume !(0 == ~E_4~0); 633975#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 633973#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 633970#L279-18 assume 1 == ~m_pc~0; 633967#L280-6 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 633965#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 633963#L291-6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 633960#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 633958#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 633956#L298-18 assume !(1 == ~t1_pc~0); 633954#L298-20 is_transmit1_triggered_~__retres1~1#1 := 0; 633952#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 633951#L310-6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 633950#L728-18 assume !(0 != activate_threads_~tmp___0~0#1); 633949#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 633944#L317-18 assume !(1 == ~t2_pc~0); 633942#L317-20 is_transmit2_triggered_~__retres1~2#1 := 0; 633940#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 633939#L329-6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 633715#L736-18 assume !(0 != activate_threads_~tmp___1~0#1); 633711#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 633707#L336-18 assume !(1 == ~t3_pc~0); 633703#L336-20 is_transmit3_triggered_~__retres1~3#1 := 0; 633699#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 633695#L348-6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 633691#L744-18 assume !(0 != activate_threads_~tmp___2~0#1); 633687#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 633681#L355-18 assume !(1 == ~t4_pc~0); 633677#L355-20 is_transmit4_triggered_~__retres1~4#1 := 0; 633673#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 633668#L367-6 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 633664#L752-18 assume !(0 != activate_threads_~tmp___3~0#1); 633659#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 633655#L374-18 assume !(1 == ~t5_pc~0); 633652#L374-20 is_transmit5_triggered_~__retres1~5#1 := 0; 633648#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 633644#L386-6 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 633640#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 633635#L760-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 633630#L649-3 assume 1 == ~M_E~0;~M_E~0 := 2; 633626#L649-5 assume !(1 == ~T1_E~0); 633621#L654-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 633617#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 633612#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 633608#L669-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 633603#L674-3 assume !(1 == ~E_1~0); 633598#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 633594#L684-3 assume !(1 == ~E_3~0); 633590#L689-3 assume !(1 == ~E_4~0); 633586#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 633581#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 633573#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 633566#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 633558#L472-1 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 633548#L919 assume 0 == start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 4;assume { :begin_inline_fire_time_events } true;~M_E~0 := 1; 633550#L786 assume { :end_inline_fire_time_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 633662#L279-21 assume !(1 == ~m_pc~0); 633658#L279-23 is_master_triggered_~__retres1~0#1 := 0; 633654#L290-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 633651#L291-7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 633647#L720-21 assume !(0 != activate_threads_~tmp~1#1); 633643#L720-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 633639#L298-21 assume !(1 == ~t1_pc~0); 633634#L298-23 is_transmit1_triggered_~__retres1~1#1 := 0; 633629#L309-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 633625#L310-7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 633620#L728-21 assume !(0 != activate_threads_~tmp___0~0#1); 633616#L728-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 633611#L317-21 assume !(1 == ~t2_pc~0); 633607#L317-23 is_transmit2_triggered_~__retres1~2#1 := 0; 633602#L328-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 633597#L329-7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 633593#L736-21 assume !(0 != activate_threads_~tmp___1~0#1); 633589#L736-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 633584#L336-21 assume !(1 == ~t3_pc~0); 633577#L336-23 is_transmit3_triggered_~__retres1~3#1 := 0; 633569#L347-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 633562#L348-7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 633554#L744-21 assume !(0 != activate_threads_~tmp___2~0#1); 633544#L744-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 633538#L355-21 assume !(1 == ~t4_pc~0); 633534#L355-23 is_transmit4_triggered_~__retres1~4#1 := 0; 633531#L366-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 633528#L367-7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 633525#L752-21 assume !(0 != activate_threads_~tmp___3~0#1); 633522#L752-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 633519#L374-21 assume !(1 == ~t5_pc~0); 633517#L374-23 is_transmit5_triggered_~__retres1~5#1 := 0; 633514#L385-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 633511#L386-7 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 633508#L760-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 633505#L760-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_time_events } true; 633501#L793 assume 1 == ~M_E~0;~M_E~0 := 2; 633502#L793-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 633585#L798-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 633580#L803-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 633572#L808-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 633565#L813-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 633557#L818-1 assume !(1 == ~E_1~0); 633547#L823-1 assume 1 == ~E_2~0;~E_2~0 := 2; 633541#L828-1 assume !(1 == ~E_3~0); 633478#L833-1 assume !(1 == ~E_4~0); 633472#L838-1 assume 1 == ~E_5~0;~E_5~0 := 2; 633468#L843-1 assume { :end_inline_reset_time_events } true; 633465#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 633460#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 633461#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 640263#L472-2 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 640261#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 640259#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 640257#L882 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 640255#L932 assume !(0 != start_simulation_~tmp___0~1#1); 630476#L900-2 [2021-12-16 10:05:59,086 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:59,086 INFO L85 PathProgramCache]: Analyzing trace with hash -445536100, now seen corresponding path program 10 times [2021-12-16 10:05:59,086 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:59,087 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1872706269] [2021-12-16 10:05:59,087 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:59,087 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:59,092 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:05:59,107 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-16 10:05:59,115 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:05:59,122 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-16 10:05:59,132 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:05:59,133 INFO L85 PathProgramCache]: Analyzing trace with hash 52046915, now seen corresponding path program 1 times [2021-12-16 10:05:59,133 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:05:59,133 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1932443674] [2021-12-16 10:05:59,133 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:05:59,133 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:05:59,143 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:05:59,198 INFO L134 CoverageAnalysis]: Checked inductivity of 147 backedges. 68 proven. 0 refuted. 0 times theorem prover too weak. 79 trivial. 0 not checked. [2021-12-16 10:05:59,198 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:05:59,198 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1932443674] [2021-12-16 10:05:59,198 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1932443674] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:05:59,199 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:05:59,199 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-16 10:05:59,199 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1496454504] [2021-12-16 10:05:59,199 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:05:59,199 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:05:59,199 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:05:59,200 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-16 10:05:59,200 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-16 10:05:59,200 INFO L87 Difference]: Start difference. First operand 34959 states and 44871 transitions. cyclomatic complexity: 9928 Second operand has 5 states, 5 states have (on average 51.6) internal successors, (258), 5 states have internal predecessors, (258), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:05:59,663 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:05:59,663 INFO L93 Difference]: Finished difference Result 51604 states and 66568 transitions. [2021-12-16 10:05:59,663 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-16 10:05:59,664 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 51604 states and 66568 transitions. [2021-12-16 10:05:59,946 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 51132 [2021-12-16 10:06:00,148 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 51604 states to 51604 states and 66568 transitions. [2021-12-16 10:06:00,148 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 51604 [2021-12-16 10:06:00,188 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 51604 [2021-12-16 10:06:00,188 INFO L73 IsDeterministic]: Start isDeterministic. Operand 51604 states and 66568 transitions. [2021-12-16 10:06:00,228 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:06:00,228 INFO L681 BuchiCegarLoop]: Abstraction has 51604 states and 66568 transitions. [2021-12-16 10:06:00,262 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 51604 states and 66568 transitions. [2021-12-16 10:06:00,623 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 51604 to 35517. [2021-12-16 10:06:00,655 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 35517 states, 35517 states have (on average 1.2694765886758455) internal successors, (45088), 35516 states have internal predecessors, (45088), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:00,714 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 35517 states to 35517 states and 45088 transitions. [2021-12-16 10:06:00,715 INFO L704 BuchiCegarLoop]: Abstraction has 35517 states and 45088 transitions. [2021-12-16 10:06:00,715 INFO L587 BuchiCegarLoop]: Abstraction has 35517 states and 45088 transitions. [2021-12-16 10:06:00,715 INFO L425 BuchiCegarLoop]: ======== Iteration 24============ [2021-12-16 10:06:00,715 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 35517 states and 45088 transitions. [2021-12-16 10:06:00,997 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 35205 [2021-12-16 10:06:00,998 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:06:00,998 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:06:01,000 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:01,000 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:01,000 INFO L791 eck$LassoCheckResult]: Stem: 717303#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 717259#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 717247#L863 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 717244#L394 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 717120#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 717121#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 716908#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 716909#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 717242#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 717243#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 717202#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 716878#L586 assume !(0 == ~M_E~0); 716879#L586-2 assume !(0 == ~T1_E~0); 716932#L591-1 assume !(0 == ~T2_E~0); 717065#L596-1 assume !(0 == ~T3_E~0); 717066#L601-1 assume !(0 == ~T4_E~0); 717110#L606-1 assume !(0 == ~T5_E~0); 717111#L611-1 assume !(0 == ~E_1~0); 717212#L616-1 assume !(0 == ~E_2~0); 717213#L621-1 assume !(0 == ~E_3~0); 716811#L626-1 assume !(0 == ~E_4~0); 716812#L631-1 assume !(0 == ~E_5~0); 716965#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 716807#L279 assume !(1 == ~m_pc~0); 716808#L279-2 is_master_triggered_~__retres1~0#1 := 0; 717133#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 717040#L291 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 717041#L720 assume !(0 != activate_threads_~tmp~1#1); 717132#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 716971#L298 assume !(1 == ~t1_pc~0); 716769#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 716770#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 717029#L310 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 716820#L728 assume !(0 != activate_threads_~tmp___0~0#1); 716821#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 716938#L317 assume !(1 == ~t2_pc~0); 716939#L317-2 is_transmit2_triggered_~__retres1~2#1 := 0; 717155#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 717253#L329 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 716979#L736 assume !(0 != activate_threads_~tmp___1~0#1); 716980#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 717198#L336 assume !(1 == ~t3_pc~0); 717199#L336-2 is_transmit3_triggered_~__retres1~3#1 := 0; 717284#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 717091#L348 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 717092#L744 assume !(0 != activate_threads_~tmp___2~0#1); 717142#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 717207#L355 assume !(1 == ~t4_pc~0); 717062#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 716893#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 716894#L367 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 717126#L752 assume !(0 != activate_threads_~tmp___3~0#1); 716831#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 716832#L374 assume !(1 == ~t5_pc~0); 716955#L374-2 is_transmit5_triggered_~__retres1~5#1 := 0; 716956#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 717038#L386 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 717039#L760 assume !(0 != activate_threads_~tmp___4~0#1); 717094#L760-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 717095#L649 assume !(1 == ~M_E~0); 717270#L649-2 assume !(1 == ~T1_E~0); 716796#L654-1 assume !(1 == ~T2_E~0); 716797#L659-1 assume !(1 == ~T3_E~0); 716978#L664-1 assume !(1 == ~T4_E~0); 716789#L669-1 assume !(1 == ~T5_E~0); 716790#L674-1 assume !(1 == ~E_1~0); 717194#L679-1 assume !(1 == ~E_2~0); 716883#L684-1 assume !(1 == ~E_3~0); 716884#L689-1 assume !(1 == ~E_4~0); 717058#L694-1 assume !(1 == ~E_5~0); 717056#L699-1 assume { :end_inline_reset_delta_events } true; 717057#L900-2 [2021-12-16 10:06:01,001 INFO L793 eck$LassoCheckResult]: Loop: 717057#L900-2 assume !false; 722479#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 720656#L561 assume !false; 720657#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 720648#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 720649#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 720640#L472 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 720641#L486 assume 0 != eval_~tmp~0#1; 720631#L486-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 720632#L494 assume 0 != eval_~tmp_ndt_1~0#1;~m_st~0 := 1;assume { :begin_inline_master } true; 728757#L65 assume 0 == ~m_pc~0; 729137#L92 assume !false; 729175#L77 ~E_1~0 := 1;assume { :begin_inline_immediate_notify } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 729174#L279-3 assume !(1 == ~m_pc~0); 729173#L279-5 is_master_triggered_~__retres1~0#1 := 0; 729172#L290-1 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 729171#L291-1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 729170#L720-3 assume !(0 != activate_threads_~tmp~1#1); 729169#L720-5 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 729168#L298-3 assume !(1 == ~t1_pc~0); 729167#L298-5 is_transmit1_triggered_~__retres1~1#1 := 0; 729166#L309-1 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 729165#L310-1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 729164#L728-3 assume !(0 != activate_threads_~tmp___0~0#1); 729163#L728-5 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 729162#L317-3 assume !(1 == ~t2_pc~0); 729161#L317-5 is_transmit2_triggered_~__retres1~2#1 := 0; 729160#L328-1 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 729159#L329-1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 729158#L736-3 assume !(0 != activate_threads_~tmp___1~0#1); 729157#L736-5 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 729156#L336-3 assume !(1 == ~t3_pc~0); 729155#L336-5 is_transmit3_triggered_~__retres1~3#1 := 0; 729154#L347-1 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 729153#L348-1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 729152#L744-3 assume !(0 != activate_threads_~tmp___2~0#1); 729151#L744-5 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 729150#L355-3 assume !(1 == ~t4_pc~0); 729148#L355-5 is_transmit4_triggered_~__retres1~4#1 := 0; 729147#L366-1 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 729146#L367-1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 729145#L752-3 assume !(0 != activate_threads_~tmp___3~0#1); 729144#L752-5 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 729143#L374-3 assume !(1 == ~t5_pc~0); 729142#L374-5 is_transmit5_triggered_~__retres1~5#1 := 0; 729141#L385-1 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 729140#L386-1 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 729139#L760-3 assume !(0 != activate_threads_~tmp___4~0#1); 729138#L760-5 assume { :end_inline_activate_threads } true; 729135#L777 assume { :end_inline_immediate_notify } true;~E_1~0 := 2; 729134#L69 assume !false; 729133#L85 ~m_pc~0 := 1;~m_st~0 := 2; 729130#L95 assume { :end_inline_master } true; 729048#L491 assume !(0 == ~t1_st~0); 729128#L505 assume !(0 == ~t2_st~0); 729126#L519 assume !(0 == ~t3_st~0); 729076#L533 assume !(0 == ~t4_st~0); 729075#L547 assume !(0 == ~t5_st~0); 729071#L561 assume !false; 729070#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 728984#L439 assume !(0 == ~m_st~0); 728983#L443 assume !(0 == ~t1_st~0); 728982#L447 assume !(0 == ~t2_st~0); 728981#L451 assume !(0 == ~t3_st~0); 728980#L455 assume !(0 == ~t4_st~0); 728978#L459 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6#1 := 0; 728977#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 728976#L472 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 728974#L486 assume !(0 != eval_~tmp~0#1); 728973#L576 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 728972#L394-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 728971#L586-3 assume !(0 == ~M_E~0); 728970#L586-5 assume !(0 == ~T1_E~0); 728969#L591-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 728968#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 728967#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 728966#L606-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 728965#L611-3 assume !(0 == ~E_1~0); 728964#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 728963#L621-3 assume !(0 == ~E_3~0); 728962#L626-3 assume !(0 == ~E_4~0); 728961#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 728960#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 728958#L279-18 assume 1 == ~m_pc~0; 728957#L280-6 assume !(1 == ~M_E~0); 728956#L279-20 is_master_triggered_~__retres1~0#1 := 0; 728955#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 728954#L291-6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 728953#L720-18 assume !(0 != activate_threads_~tmp~1#1); 728952#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 728951#L298-18 assume !(1 == ~t1_pc~0); 728950#L298-20 is_transmit1_triggered_~__retres1~1#1 := 0; 728949#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 728948#L310-6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 728947#L728-18 assume !(0 != activate_threads_~tmp___0~0#1); 728946#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 728945#L317-18 assume !(1 == ~t2_pc~0); 728944#L317-20 is_transmit2_triggered_~__retres1~2#1 := 0; 728943#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 728942#L329-6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 728941#L736-18 assume !(0 != activate_threads_~tmp___1~0#1); 728940#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 728939#L336-18 assume !(1 == ~t3_pc~0); 728938#L336-20 is_transmit3_triggered_~__retres1~3#1 := 0; 728937#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 728936#L348-6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 728935#L744-18 assume !(0 != activate_threads_~tmp___2~0#1); 728934#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 728932#L355-18 assume !(1 == ~t4_pc~0); 728931#L355-20 is_transmit4_triggered_~__retres1~4#1 := 0; 728930#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 728929#L367-6 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 728928#L752-18 assume !(0 != activate_threads_~tmp___3~0#1); 728927#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 728926#L374-18 assume !(1 == ~t5_pc~0); 728925#L374-20 is_transmit5_triggered_~__retres1~5#1 := 0; 728924#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 728923#L386-6 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 728922#L760-18 assume !(0 != activate_threads_~tmp___4~0#1); 728921#L760-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 728920#L649-3 assume !(1 == ~M_E~0); 728917#L649-5 assume !(1 == ~T1_E~0); 728916#L654-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 728915#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 728914#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 728913#L669-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 728912#L674-3 assume !(1 == ~E_1~0); 728911#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 728910#L684-3 assume !(1 == ~E_3~0); 728909#L689-3 assume !(1 == ~E_4~0); 728908#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 728907#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 728906#L439-1 assume !(0 == ~m_st~0); 728763#L443-1 assume 0 == ~t1_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 728892#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 728891#L472-1 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 728889#L919 assume 0 == start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 4;assume { :begin_inline_fire_time_events } true;~M_E~0 := 1; 728887#L786 assume { :end_inline_fire_time_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 728885#L279-21 assume 1 == ~m_pc~0; 728883#L280-7 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 728882#L290-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 728881#L291-7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 728874#L720-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 728873#L720-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 728872#L298-21 assume !(1 == ~t1_pc~0); 728871#L298-23 is_transmit1_triggered_~__retres1~1#1 := 0; 728870#L309-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 728869#L310-7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 728868#L728-21 assume !(0 != activate_threads_~tmp___0~0#1); 728867#L728-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 728866#L317-21 assume !(1 == ~t2_pc~0); 728865#L317-23 is_transmit2_triggered_~__retres1~2#1 := 0; 728864#L328-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 728863#L329-7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 728862#L736-21 assume !(0 != activate_threads_~tmp___1~0#1); 728861#L736-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 728860#L336-21 assume !(1 == ~t3_pc~0); 728859#L336-23 is_transmit3_triggered_~__retres1~3#1 := 0; 728858#L347-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 728857#L348-7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 728856#L744-21 assume !(0 != activate_threads_~tmp___2~0#1); 721023#L744-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 721024#L355-21 assume !(1 == ~t4_pc~0); 728804#L355-23 is_transmit4_triggered_~__retres1~4#1 := 0; 728803#L366-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 728802#L367-7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 728801#L752-21 assume !(0 != activate_threads_~tmp___3~0#1); 728800#L752-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 728799#L374-21 assume !(1 == ~t5_pc~0); 728798#L374-23 is_transmit5_triggered_~__retres1~5#1 := 0; 728797#L385-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 728796#L386-7 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 728795#L760-21 assume !(0 != activate_threads_~tmp___4~0#1); 728794#L760-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_time_events } true; 728792#L793 assume !(1 == ~M_E~0); 728791#L793-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 728790#L798-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 728789#L803-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 728788#L808-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 728787#L813-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 728786#L818-1 assume !(1 == ~E_1~0); 728785#L823-1 assume 1 == ~E_2~0;~E_2~0 := 2; 728784#L828-1 assume !(1 == ~E_3~0); 728783#L833-1 assume !(1 == ~E_4~0); 728782#L838-1 assume 1 == ~E_5~0;~E_5~0 := 2; 728781#L843-1 assume { :end_inline_reset_time_events } true; 721107#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 728780#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 728779#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 728778#L472-2 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 728777#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 728776#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 728775#L882 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 728774#L932 assume !(0 != start_simulation_~tmp___0~1#1); 721428#L900-2 assume !false; 721429#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 721396#L561 assume !false; 721397#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 721376#L439 assume !(0 == ~m_st~0); 721378#L443 assume !(0 == ~t1_st~0); 721370#L447 assume !(0 == ~t2_st~0); 721371#L451 assume !(0 == ~t3_st~0); 721351#L455 assume !(0 == ~t4_st~0); 721353#L459 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6#1 := 0; 721202#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 721203#L472 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 721194#L486 assume !(0 != eval_~tmp~0#1); 721196#L576 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 721186#L394-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 721187#L586-3 assume 0 == ~M_E~0;~M_E~0 := 1; 721180#L586-5 assume !(0 == ~T1_E~0); 721181#L591-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 721176#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 721177#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 721170#L606-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 721171#L611-3 assume !(0 == ~E_1~0); 721164#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 721165#L621-3 assume !(0 == ~E_3~0); 721156#L626-3 assume !(0 == ~E_4~0); 721157#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 721148#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 721149#L279-18 assume 1 == ~m_pc~0; 721138#L280-6 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 721139#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 721130#L291-6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 721131#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 721121#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 721122#L298-18 assume !(1 == ~t1_pc~0); 721112#L298-20 is_transmit1_triggered_~__retres1~1#1 := 0; 721113#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 721104#L310-6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 721105#L728-18 assume !(0 != activate_threads_~tmp___0~0#1); 721095#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 721096#L317-18 assume !(1 == ~t2_pc~0); 721088#L317-20 is_transmit2_triggered_~__retres1~2#1 := 0; 721089#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 721078#L329-6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 721079#L736-18 assume !(0 != activate_threads_~tmp___1~0#1); 721072#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 721073#L336-18 assume !(1 == ~t3_pc~0); 721066#L336-20 is_transmit3_triggered_~__retres1~3#1 := 0; 721067#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 721060#L348-6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 721061#L744-18 assume !(0 != activate_threads_~tmp___2~0#1); 721054#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 721055#L355-18 assume !(1 == ~t4_pc~0); 721047#L355-20 is_transmit4_triggered_~__retres1~4#1 := 0; 721048#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 721041#L367-6 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 721042#L752-18 assume !(0 != activate_threads_~tmp___3~0#1); 721035#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 721036#L374-18 assume !(1 == ~t5_pc~0); 721029#L374-20 is_transmit5_triggered_~__retres1~5#1 := 0; 721030#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 721021#L386-6 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 721022#L760-18 assume !(0 != activate_threads_~tmp___4~0#1); 721014#L760-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 721015#L649-3 assume 1 == ~M_E~0;~M_E~0 := 2; 721007#L649-5 assume !(1 == ~T1_E~0); 721008#L654-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 721001#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 721002#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 720995#L669-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 720996#L674-3 assume !(1 == ~E_1~0); 720989#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 720990#L684-3 assume !(1 == ~E_3~0); 720983#L689-3 assume !(1 == ~E_4~0); 720984#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 720976#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 720977#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 720969#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 720970#L472-1 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 720951#L919 assume 0 == start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 4;assume { :begin_inline_fire_time_events } true;~M_E~0 := 1; 720953#L786 assume { :end_inline_fire_time_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 721097#L279-21 assume !(1 == ~m_pc~0); 721099#L279-23 is_master_triggered_~__retres1~0#1 := 0; 721998#L290-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 721999#L291-7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 721990#L720-21 assume !(0 != activate_threads_~tmp~1#1); 721991#L720-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 721982#L298-21 assume !(1 == ~t1_pc~0); 721983#L298-23 is_transmit1_triggered_~__retres1~1#1 := 0; 721975#L309-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 721976#L310-7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 721969#L728-21 assume !(0 != activate_threads_~tmp___0~0#1); 721970#L728-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 721963#L317-21 assume !(1 == ~t2_pc~0); 721964#L317-23 is_transmit2_triggered_~__retres1~2#1 := 0; 721957#L328-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 721958#L329-7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 721951#L736-21 assume !(0 != activate_threads_~tmp___1~0#1); 721952#L736-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 721945#L336-21 assume !(1 == ~t3_pc~0); 721946#L336-23 is_transmit3_triggered_~__retres1~3#1 := 0; 721939#L347-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 721940#L348-7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 721933#L744-21 assume !(0 != activate_threads_~tmp___2~0#1); 721934#L744-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 721928#L355-21 assume !(1 == ~t4_pc~0); 721927#L355-23 is_transmit4_triggered_~__retres1~4#1 := 0; 721919#L366-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 721920#L367-7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 721913#L752-21 assume !(0 != activate_threads_~tmp___3~0#1); 721914#L752-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 721907#L374-21 assume !(1 == ~t5_pc~0); 721908#L374-23 is_transmit5_triggered_~__retres1~5#1 := 0; 721901#L385-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 721902#L386-7 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 721895#L760-21 assume !(0 != activate_threads_~tmp___4~0#1); 721896#L760-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_time_events } true; 721889#L793 assume 1 == ~M_E~0;~M_E~0 := 2; 721890#L793-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 722566#L798-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 722567#L803-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 722558#L808-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 722559#L813-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 722550#L818-1 assume !(1 == ~E_1~0); 722551#L823-1 assume 1 == ~E_2~0;~E_2~0 := 2; 722542#L828-1 assume !(1 == ~E_3~0); 722543#L833-1 assume !(1 == ~E_4~0); 722533#L838-1 assume 1 == ~E_5~0;~E_5~0 := 2; 722534#L843-1 assume { :end_inline_reset_time_events } true; 722525#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 722526#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 722516#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 722517#L472-2 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 722505#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 722506#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 722492#L882 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 722493#L932 assume !(0 != start_simulation_~tmp___0~1#1); 717057#L900-2 [2021-12-16 10:06:01,001 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:01,002 INFO L85 PathProgramCache]: Analyzing trace with hash -445536100, now seen corresponding path program 11 times [2021-12-16 10:06:01,002 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:01,002 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1019954633] [2021-12-16 10:06:01,002 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:01,002 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:01,007 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:06:01,008 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-16 10:06:01,011 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:06:01,019 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-16 10:06:01,019 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:01,020 INFO L85 PathProgramCache]: Analyzing trace with hash -459388161, now seen corresponding path program 1 times [2021-12-16 10:06:01,020 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:01,020 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1411321263] [2021-12-16 10:06:01,020 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:01,020 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:01,031 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:06:01,053 INFO L134 CoverageAnalysis]: Checked inductivity of 147 backedges. 88 proven. 0 refuted. 0 times theorem prover too weak. 59 trivial. 0 not checked. [2021-12-16 10:06:01,054 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:06:01,054 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1411321263] [2021-12-16 10:06:01,054 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1411321263] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:06:01,054 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:06:01,054 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:06:01,054 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [553312486] [2021-12-16 10:06:01,054 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:06:01,055 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:06:01,055 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:06:01,055 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-16 10:06:01,055 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-16 10:06:01,055 INFO L87 Difference]: Start difference. First operand 35517 states and 45088 transitions. cyclomatic complexity: 9587 Second operand has 3 states, 3 states have (on average 91.33333333333333) internal successors, (274), 3 states have internal predecessors, (274), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:01,168 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:06:01,168 INFO L93 Difference]: Finished difference Result 46520 states and 58178 transitions. [2021-12-16 10:06:01,169 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-16 10:06:01,169 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 46520 states and 58178 transitions. [2021-12-16 10:06:01,371 INFO L131 ngComponentsAnalysis]: Automaton has 40 accepting balls. 44303 [2021-12-16 10:06:01,475 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 46520 states to 46520 states and 58178 transitions. [2021-12-16 10:06:01,475 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 46520 [2021-12-16 10:06:01,504 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 46520 [2021-12-16 10:06:01,505 INFO L73 IsDeterministic]: Start isDeterministic. Operand 46520 states and 58178 transitions. [2021-12-16 10:06:01,530 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:06:01,530 INFO L681 BuchiCegarLoop]: Abstraction has 46520 states and 58178 transitions. [2021-12-16 10:06:01,554 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 46520 states and 58178 transitions. [2021-12-16 10:06:01,856 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 46520 to 46520. [2021-12-16 10:06:02,191 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 46520 states, 46520 states have (on average 1.2506018916595012) internal successors, (58178), 46519 states have internal predecessors, (58178), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:02,267 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 46520 states to 46520 states and 58178 transitions. [2021-12-16 10:06:02,267 INFO L704 BuchiCegarLoop]: Abstraction has 46520 states and 58178 transitions. [2021-12-16 10:06:02,267 INFO L587 BuchiCegarLoop]: Abstraction has 46520 states and 58178 transitions. [2021-12-16 10:06:02,267 INFO L425 BuchiCegarLoop]: ======== Iteration 25============ [2021-12-16 10:06:02,267 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 46520 states and 58178 transitions. [2021-12-16 10:06:02,394 INFO L131 ngComponentsAnalysis]: Automaton has 40 accepting balls. 44303 [2021-12-16 10:06:02,394 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:06:02,394 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:06:02,396 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:02,396 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:02,396 INFO L791 eck$LassoCheckResult]: Stem: 799393#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 799337#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 799319#L863 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 799316#L394 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 799182#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 799183#L401-2 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 798956#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 798957#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 799314#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 799315#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 799266#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 798927#L586 assume !(0 == ~M_E~0); 798928#L586-2 assume !(0 == ~T1_E~0); 798981#L591-1 assume !(0 == ~T2_E~0); 799120#L596-1 assume !(0 == ~T3_E~0); 799121#L601-1 assume !(0 == ~T4_E~0); 799169#L606-1 assume !(0 == ~T5_E~0); 799170#L611-1 assume !(0 == ~E_1~0); 799275#L616-1 assume !(0 == ~E_2~0); 799276#L621-1 assume !(0 == ~E_3~0); 798854#L626-1 assume !(0 == ~E_4~0); 798855#L631-1 assume !(0 == ~E_5~0); 799016#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 798852#L279 assume !(1 == ~m_pc~0); 798853#L279-2 is_master_triggered_~__retres1~0#1 := 0; 799194#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 799093#L291 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 799094#L720 assume !(0 != activate_threads_~tmp~1#1); 799193#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 799023#L298 assume !(1 == ~t1_pc~0); 798813#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 798814#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 799082#L310 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 798864#L728 assume !(0 != activate_threads_~tmp___0~0#1); 798865#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 798986#L317 assume !(1 == ~t2_pc~0); 798987#L317-2 is_transmit2_triggered_~__retres1~2#1 := 0; 799217#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 799331#L329 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 799036#L736 assume !(0 != activate_threads_~tmp___1~0#1); 799037#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 799347#L336 assume !(1 == ~t3_pc~0); 805342#L336-2 is_transmit3_triggered_~__retres1~3#1 := 0; 805340#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 805339#L348 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 805337#L744 assume !(0 != activate_threads_~tmp___2~0#1); 805335#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 805333#L355 assume !(1 == ~t4_pc~0); 799267#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 799268#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 805145#L367 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 805143#L752 assume !(0 != activate_threads_~tmp___3~0#1); 798877#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 798878#L374 assume !(1 == ~t5_pc~0); 799008#L374-2 is_transmit5_triggered_~__retres1~5#1 := 0; 799009#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 799091#L386 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 799092#L760 assume !(0 != activate_threads_~tmp___4~0#1); 799153#L760-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 799154#L649 assume !(1 == ~M_E~0); 799355#L649-2 assume !(1 == ~T1_E~0); 798839#L654-1 assume !(1 == ~T2_E~0); 798840#L659-1 assume !(1 == ~T3_E~0); 799031#L664-1 assume !(1 == ~T4_E~0); 798832#L669-1 assume !(1 == ~T5_E~0); 798833#L674-1 assume !(1 == ~E_1~0); 799256#L679-1 assume !(1 == ~E_2~0); 798929#L684-1 assume !(1 == ~E_3~0); 798930#L689-1 assume !(1 == ~E_4~0); 799113#L694-1 assume !(1 == ~E_5~0); 799387#L699-1 assume { :end_inline_reset_delta_events } true; 804988#L900-2 [2021-12-16 10:06:02,397 INFO L793 eck$LassoCheckResult]: Loop: 804988#L900-2 assume !false; 813197#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 804858#L561 assume !false; 813196#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 813194#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 813193#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 813192#L472 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 813191#L486 assume 0 != eval_~tmp~0#1; 813189#L486-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 813188#L494 assume 0 != eval_~tmp_ndt_1~0#1;~m_st~0 := 1;assume { :begin_inline_master } true; 804834#L65 assume 0 == ~m_pc~0; 804759#L92 assume !false; 804831#L77 ~E_1~0 := 1;assume { :begin_inline_immediate_notify } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 804829#L279-3 assume !(1 == ~m_pc~0); 804827#L279-5 is_master_triggered_~__retres1~0#1 := 0; 804825#L290-1 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 804823#L291-1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 804821#L720-3 assume !(0 != activate_threads_~tmp~1#1); 804819#L720-5 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 804818#L298-3 assume !(1 == ~t1_pc~0); 804816#L298-5 is_transmit1_triggered_~__retres1~1#1 := 0; 804814#L309-1 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 804813#L310-1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 804812#L728-3 assume !(0 != activate_threads_~tmp___0~0#1); 804811#L728-5 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 804806#L317-3 assume !(1 == ~t2_pc~0); 804804#L317-5 is_transmit2_triggered_~__retres1~2#1 := 0; 804802#L328-1 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 804800#L329-1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 804798#L736-3 assume !(0 != activate_threads_~tmp___1~0#1); 804796#L736-5 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 804794#L336-3 assume !(1 == ~t3_pc~0); 804792#L336-5 is_transmit3_triggered_~__retres1~3#1 := 0; 804791#L347-1 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 804790#L348-1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 804789#L744-3 assume !(0 != activate_threads_~tmp___2~0#1); 804788#L744-5 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 804787#L355-3 assume !(1 == ~t4_pc~0); 804785#L355-5 is_transmit4_triggered_~__retres1~4#1 := 0; 804782#L366-1 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 804780#L367-1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 804778#L752-3 assume !(0 != activate_threads_~tmp___3~0#1); 804776#L752-5 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 804774#L374-3 assume !(1 == ~t5_pc~0); 804772#L374-5 is_transmit5_triggered_~__retres1~5#1 := 0; 804770#L385-1 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 804768#L386-1 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 804766#L760-3 assume !(0 != activate_threads_~tmp___4~0#1); 804764#L760-5 assume { :end_inline_activate_threads } true; 804757#L777 assume { :end_inline_immediate_notify } true;~E_1~0 := 2; 804755#L69 assume !false; 804753#L85 ~m_pc~0 := 1;~m_st~0 := 2; 804745#L95 assume { :end_inline_master } true; 804743#L491 assume !(0 == ~t1_st~0); 804741#L505 assume !(0 == ~t2_st~0); 804737#L519 assume !(0 == ~t3_st~0); 804677#L533 assume !(0 == ~t4_st~0); 804674#L547 assume !(0 == ~t5_st~0); 804668#L561 assume !false; 804665#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 804662#L439 assume !(0 == ~m_st~0); 804659#L443 assume !(0 == ~t1_st~0); 804658#L447 assume !(0 == ~t2_st~0); 804654#L451 assume !(0 == ~t3_st~0); 804651#L455 assume !(0 == ~t4_st~0); 804647#L459 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6#1 := 0; 804644#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 804641#L472 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 804637#L486 assume !(0 != eval_~tmp~0#1); 804634#L576 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 804631#L394-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 804628#L586-3 assume !(0 == ~M_E~0); 804625#L586-5 assume !(0 == ~T1_E~0); 804622#L591-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 804619#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 804617#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 804614#L606-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 804611#L611-3 assume !(0 == ~E_1~0); 804557#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 804556#L621-3 assume !(0 == ~E_3~0); 804555#L626-3 assume !(0 == ~E_4~0); 804554#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 804552#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 804549#L279-18 assume 1 == ~m_pc~0; 804548#L280-6 assume !(1 == ~M_E~0); 804547#L279-20 is_master_triggered_~__retres1~0#1 := 0; 804545#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 804542#L291-6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 804539#L720-18 assume !(0 != activate_threads_~tmp~1#1); 804536#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 804533#L298-18 assume !(1 == ~t1_pc~0); 804530#L298-20 is_transmit1_triggered_~__retres1~1#1 := 0; 804527#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 804524#L310-6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 804521#L728-18 assume !(0 != activate_threads_~tmp___0~0#1); 804518#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 804516#L317-18 assume !(1 == ~t2_pc~0); 804514#L317-20 is_transmit2_triggered_~__retres1~2#1 := 0; 804511#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 804509#L329-6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 804507#L736-18 assume !(0 != activate_threads_~tmp___1~0#1); 804503#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 804501#L336-18 assume !(1 == ~t3_pc~0); 804499#L336-20 is_transmit3_triggered_~__retres1~3#1 := 0; 804496#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 804492#L348-6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 804490#L744-18 assume !(0 != activate_threads_~tmp___2~0#1); 804488#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 804483#L355-18 assume !(1 == ~t4_pc~0); 804481#L355-20 is_transmit4_triggered_~__retres1~4#1 := 0; 804479#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 804477#L367-6 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 804476#L752-18 assume !(0 != activate_threads_~tmp___3~0#1); 804475#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 804474#L374-18 assume !(1 == ~t5_pc~0); 804473#L374-20 is_transmit5_triggered_~__retres1~5#1 := 0; 804472#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 804471#L386-6 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 804469#L760-18 assume !(0 != activate_threads_~tmp___4~0#1); 804467#L760-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 804464#L649-3 assume !(1 == ~M_E~0); 804462#L649-5 assume !(1 == ~T1_E~0); 804460#L654-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 804458#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 804456#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 804454#L669-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 804452#L674-3 assume !(1 == ~E_1~0); 804450#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 804448#L684-3 assume !(1 == ~E_3~0); 804446#L689-3 assume !(1 == ~E_4~0); 804444#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 804442#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 804440#L439-1 assume !(0 == ~m_st~0); 802063#L443-1 assume !(0 == ~t1_st~0); 804433#L447-1 assume 0 == ~t2_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 804429#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 804428#L472-1 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 802111#L919 assume 0 == start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 4;assume { :begin_inline_fire_time_events } true;~M_E~0 := 1; 802109#L786 assume { :end_inline_fire_time_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 802106#L279-21 assume 1 == ~m_pc~0; 802103#L280-7 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 802100#L290-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 802097#L291-7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 802098#L720-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 813123#L720-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 813122#L298-21 assume !(1 == ~t1_pc~0); 813121#L298-23 is_transmit1_triggered_~__retres1~1#1 := 0; 813120#L309-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 813119#L310-7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 813118#L728-21 assume !(0 != activate_threads_~tmp___0~0#1); 813117#L728-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 813116#L317-21 assume !(1 == ~t2_pc~0); 813115#L317-23 is_transmit2_triggered_~__retres1~2#1 := 0; 813114#L328-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 813113#L329-7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 813112#L736-21 assume !(0 != activate_threads_~tmp___1~0#1); 813111#L736-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 813110#L336-21 assume !(1 == ~t3_pc~0); 813109#L336-23 is_transmit3_triggered_~__retres1~3#1 := 0; 813108#L347-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 813107#L348-7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 813106#L744-21 assume !(0 != activate_threads_~tmp___2~0#1); 813105#L744-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 813104#L355-21 assume !(1 == ~t4_pc~0); 813102#L355-23 is_transmit4_triggered_~__retres1~4#1 := 0; 813101#L366-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 813100#L367-7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 813099#L752-21 assume !(0 != activate_threads_~tmp___3~0#1); 813098#L752-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 813097#L374-21 assume !(1 == ~t5_pc~0); 813096#L374-23 is_transmit5_triggered_~__retres1~5#1 := 0; 813095#L385-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 813094#L386-7 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 813093#L760-21 assume !(0 != activate_threads_~tmp___4~0#1); 813092#L760-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_time_events } true; 813090#L793 assume !(1 == ~M_E~0); 813091#L793-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 813374#L798-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 813373#L803-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 813372#L808-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 813371#L813-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 813370#L818-1 assume !(1 == ~E_1~0); 813369#L823-1 assume 1 == ~E_2~0;~E_2~0 := 2; 813368#L828-1 assume !(1 == ~E_3~0); 813367#L833-1 assume !(1 == ~E_4~0); 813366#L838-1 assume 1 == ~E_5~0;~E_5~0 := 2; 813365#L843-1 assume { :end_inline_reset_time_events } true; 813258#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 813364#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 813363#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 813362#L472-2 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 813361#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 813360#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 813359#L882 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 813358#L932 assume !(0 != start_simulation_~tmp___0~1#1); 813357#L900-2 assume !false; 813354#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 813353#L561 assume !false; 813352#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 813351#L439 assume !(0 == ~m_st~0); 813349#L443 assume !(0 == ~t1_st~0); 813348#L447 assume !(0 == ~t2_st~0); 813347#L451 assume !(0 == ~t3_st~0); 813346#L455 assume !(0 == ~t4_st~0); 813344#L459 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6#1 := 0; 813343#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 813342#L472 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 813340#L486 assume !(0 != eval_~tmp~0#1); 813339#L576 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 813338#L394-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 813337#L586-3 assume 0 == ~M_E~0;~M_E~0 := 1; 813336#L586-5 assume !(0 == ~T1_E~0); 813335#L591-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 813334#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 813333#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 813332#L606-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 813331#L611-3 assume !(0 == ~E_1~0); 813330#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 813329#L621-3 assume !(0 == ~E_3~0); 813328#L626-3 assume !(0 == ~E_4~0); 813327#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 813326#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 813324#L279-18 assume 1 == ~m_pc~0; 813323#L280-6 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 813322#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 813321#L291-6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 813320#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 813319#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 813318#L298-18 assume !(1 == ~t1_pc~0); 813317#L298-20 is_transmit1_triggered_~__retres1~1#1 := 0; 813316#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 813315#L310-6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 813314#L728-18 assume !(0 != activate_threads_~tmp___0~0#1); 813313#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 813312#L317-18 assume !(1 == ~t2_pc~0); 813311#L317-20 is_transmit2_triggered_~__retres1~2#1 := 0; 813310#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 813309#L329-6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 813308#L736-18 assume !(0 != activate_threads_~tmp___1~0#1); 813307#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 813306#L336-18 assume !(1 == ~t3_pc~0); 813305#L336-20 is_transmit3_triggered_~__retres1~3#1 := 0; 813304#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 813303#L348-6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 813302#L744-18 assume !(0 != activate_threads_~tmp___2~0#1); 813301#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 813285#L355-18 assume !(1 == ~t4_pc~0); 813284#L355-20 is_transmit4_triggered_~__retres1~4#1 := 0; 813283#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 813282#L367-6 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 813281#L752-18 assume !(0 != activate_threads_~tmp___3~0#1); 813280#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 813279#L374-18 assume !(1 == ~t5_pc~0); 813278#L374-20 is_transmit5_triggered_~__retres1~5#1 := 0; 813277#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 813276#L386-6 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 813275#L760-18 assume !(0 != activate_threads_~tmp___4~0#1); 813274#L760-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 813273#L649-3 assume !(1 == ~M_E~0); 813272#L649-5 assume !(1 == ~T1_E~0); 813271#L654-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 813270#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 813269#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 813268#L669-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 813267#L674-3 assume !(1 == ~E_1~0); 813266#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 813265#L684-3 assume !(1 == ~E_3~0); 813264#L689-3 assume !(1 == ~E_4~0); 813263#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 813262#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 813261#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 813260#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 813259#L472-1 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 813257#L919 assume 0 == start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 4;assume { :begin_inline_fire_time_events } true;~M_E~0 := 1; 813078#L786 assume { :end_inline_fire_time_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 813256#L279-21 assume !(1 == ~m_pc~0); 813255#L279-23 is_master_triggered_~__retres1~0#1 := 0; 813254#L290-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 813253#L291-7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 813252#L720-21 assume !(0 != activate_threads_~tmp~1#1); 813251#L720-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 813250#L298-21 assume !(1 == ~t1_pc~0); 813249#L298-23 is_transmit1_triggered_~__retres1~1#1 := 0; 813248#L309-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 813247#L310-7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 813246#L728-21 assume !(0 != activate_threads_~tmp___0~0#1); 813245#L728-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 813244#L317-21 assume !(1 == ~t2_pc~0); 813243#L317-23 is_transmit2_triggered_~__retres1~2#1 := 0; 813242#L328-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 813241#L329-7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 813240#L736-21 assume !(0 != activate_threads_~tmp___1~0#1); 813239#L736-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 813238#L336-21 assume !(1 == ~t3_pc~0); 813237#L336-23 is_transmit3_triggered_~__retres1~3#1 := 0; 813236#L347-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 813235#L348-7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 813234#L744-21 assume !(0 != activate_threads_~tmp___2~0#1); 813233#L744-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 813232#L355-21 assume !(1 == ~t4_pc~0); 813230#L355-23 is_transmit4_triggered_~__retres1~4#1 := 0; 813229#L366-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 813228#L367-7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 813227#L752-21 assume !(0 != activate_threads_~tmp___3~0#1); 813226#L752-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 813225#L374-21 assume !(1 == ~t5_pc~0); 813224#L374-23 is_transmit5_triggered_~__retres1~5#1 := 0; 813223#L385-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 813222#L386-7 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 813221#L760-21 assume !(0 != activate_threads_~tmp___4~0#1); 813220#L760-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_time_events } true; 813218#L793 assume 1 == ~M_E~0;~M_E~0 := 2; 813217#L793-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 813216#L798-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 813215#L803-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 813214#L808-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 813213#L813-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 813212#L818-1 assume !(1 == ~E_1~0); 813211#L823-1 assume 1 == ~E_2~0;~E_2~0 := 2; 813210#L828-1 assume !(1 == ~E_3~0); 813209#L833-1 assume !(1 == ~E_4~0); 813208#L838-1 assume 1 == ~E_5~0;~E_5~0 := 2; 813207#L843-1 assume { :end_inline_reset_time_events } true; 813206#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 813204#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 813203#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 813202#L472-2 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 813201#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 813200#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 813199#L882 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 813198#L932 assume !(0 != start_simulation_~tmp___0~1#1); 804988#L900-2 [2021-12-16 10:06:02,397 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:02,397 INFO L85 PathProgramCache]: Analyzing trace with hash -1177503526, now seen corresponding path program 1 times [2021-12-16 10:06:02,398 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:02,398 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [588946427] [2021-12-16 10:06:02,398 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:02,398 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:02,402 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:06:02,415 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:06:02,415 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:06:02,415 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [588946427] [2021-12-16 10:06:02,415 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [588946427] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:06:02,416 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:06:02,416 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:06:02,416 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [948941359] [2021-12-16 10:06:02,416 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:06:02,416 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:06:02,416 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:02,417 INFO L85 PathProgramCache]: Analyzing trace with hash 1889758451, now seen corresponding path program 1 times [2021-12-16 10:06:02,417 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:02,417 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [785525364] [2021-12-16 10:06:02,417 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:02,417 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:02,427 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:06:02,449 INFO L134 CoverageAnalysis]: Checked inductivity of 147 backedges. 88 proven. 0 refuted. 0 times theorem prover too weak. 59 trivial. 0 not checked. [2021-12-16 10:06:02,449 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:06:02,449 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [785525364] [2021-12-16 10:06:02,449 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [785525364] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:06:02,449 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:06:02,449 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:06:02,450 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1795903206] [2021-12-16 10:06:02,450 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:06:02,450 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:06:02,450 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:06:02,450 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-16 10:06:02,451 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-16 10:06:02,451 INFO L87 Difference]: Start difference. First operand 46520 states and 58178 transitions. cyclomatic complexity: 11698 Second operand has 3 states, 3 states have (on average 23.666666666666668) internal successors, (71), 3 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:02,562 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:06:02,562 INFO L93 Difference]: Finished difference Result 46454 states and 58096 transitions. [2021-12-16 10:06:02,563 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-16 10:06:02,564 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 46454 states and 58096 transitions. [2021-12-16 10:06:02,736 INFO L131 ngComponentsAnalysis]: Automaton has 40 accepting balls. 44303 [2021-12-16 10:06:02,848 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 46454 states to 46454 states and 58096 transitions. [2021-12-16 10:06:02,849 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 46454 [2021-12-16 10:06:02,883 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 46454 [2021-12-16 10:06:02,884 INFO L73 IsDeterministic]: Start isDeterministic. Operand 46454 states and 58096 transitions. [2021-12-16 10:06:02,916 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:06:02,916 INFO L681 BuchiCegarLoop]: Abstraction has 46454 states and 58096 transitions. [2021-12-16 10:06:02,946 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 46454 states and 58096 transitions. [2021-12-16 10:06:03,579 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 46454 to 46454. [2021-12-16 10:06:03,616 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 46454 states, 46454 states have (on average 1.2506135101390623) internal successors, (58096), 46453 states have internal predecessors, (58096), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:03,680 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 46454 states to 46454 states and 58096 transitions. [2021-12-16 10:06:03,680 INFO L704 BuchiCegarLoop]: Abstraction has 46454 states and 58096 transitions. [2021-12-16 10:06:03,680 INFO L587 BuchiCegarLoop]: Abstraction has 46454 states and 58096 transitions. [2021-12-16 10:06:03,680 INFO L425 BuchiCegarLoop]: ======== Iteration 26============ [2021-12-16 10:06:03,680 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 46454 states and 58096 transitions. [2021-12-16 10:06:03,798 INFO L131 ngComponentsAnalysis]: Automaton has 40 accepting balls. 44303 [2021-12-16 10:06:03,799 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:06:03,799 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:06:03,804 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:03,804 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:03,805 INFO L791 eck$LassoCheckResult]: Stem: 892350#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 892299#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 892286#L863 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 892283#L394 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 892158#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 892159#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 891934#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 891935#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 892281#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 892282#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 892240#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 891906#L586 assume !(0 == ~M_E~0); 891907#L586-2 assume !(0 == ~T1_E~0); 891959#L591-1 assume !(0 == ~T2_E~0); 892100#L596-1 assume !(0 == ~T3_E~0); 892101#L601-1 assume !(0 == ~T4_E~0); 892148#L606-1 assume !(0 == ~T5_E~0); 892149#L611-1 assume !(0 == ~E_1~0); 892247#L616-1 assume !(0 == ~E_2~0); 892248#L621-1 assume !(0 == ~E_3~0); 891834#L626-1 assume !(0 == ~E_4~0); 891835#L631-1 assume !(0 == ~E_5~0); 891995#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 891832#L279 assume !(1 == ~m_pc~0); 891833#L279-2 is_master_triggered_~__retres1~0#1 := 0; 892169#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 892073#L291 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 892074#L720 assume !(0 != activate_threads_~tmp~1#1); 892168#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 892001#L298 assume !(1 == ~t1_pc~0); 891793#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 891794#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 892061#L310 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 891844#L728 assume !(0 != activate_threads_~tmp___0~0#1); 891845#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 891964#L317 assume !(1 == ~t2_pc~0); 891965#L317-2 is_transmit2_triggered_~__retres1~2#1 := 0; 892193#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 892296#L329 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 892015#L736 assume !(0 != activate_threads_~tmp___1~0#1); 892016#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 892236#L336 assume !(1 == ~t3_pc~0); 892237#L336-2 is_transmit3_triggered_~__retres1~3#1 := 0; 892326#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 892126#L348 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 892127#L744 assume !(0 != activate_threads_~tmp___2~0#1); 892179#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 892244#L355 assume !(1 == ~t4_pc~0); 892099#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 891921#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 891922#L367 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 892162#L752 assume !(0 != activate_threads_~tmp___3~0#1); 891857#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 891858#L374 assume !(1 == ~t5_pc~0); 891987#L374-2 is_transmit5_triggered_~__retres1~5#1 := 0; 891988#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 892071#L386 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 892072#L760 assume !(0 != activate_threads_~tmp___4~0#1); 892130#L760-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 892131#L649 assume !(1 == ~M_E~0); 892313#L649-2 assume !(1 == ~T1_E~0); 891819#L654-1 assume !(1 == ~T2_E~0); 891820#L659-1 assume !(1 == ~T3_E~0); 892008#L664-1 assume !(1 == ~T4_E~0); 891811#L669-1 assume !(1 == ~T5_E~0); 891812#L674-1 assume !(1 == ~E_1~0); 892228#L679-1 assume !(1 == ~E_2~0); 891908#L684-1 assume !(1 == ~E_3~0); 891909#L689-1 assume !(1 == ~E_4~0); 892093#L694-1 assume !(1 == ~E_5~0); 892091#L699-1 assume { :end_inline_reset_delta_events } true; 892092#L900-2 assume !false; 897246#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 897247#L561 [2021-12-16 10:06:03,805 INFO L793 eck$LassoCheckResult]: Loop: 897247#L561 assume !false; 905225#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 905223#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 897235#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 897233#L472 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 897231#L486 assume 0 != eval_~tmp~0#1; 897229#L486-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 897227#L494 assume !(0 != eval_~tmp_ndt_1~0#1); 897228#L491 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 897371#L508 assume !(0 != eval_~tmp_ndt_2~0#1); 897369#L505 assume !(0 == ~t2_st~0); 895479#L519 assume !(0 == ~t3_st~0); 897252#L533 assume !(0 == ~t4_st~0); 897250#L547 assume !(0 == ~t5_st~0); 897247#L561 [2021-12-16 10:06:03,805 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:03,805 INFO L85 PathProgramCache]: Analyzing trace with hash 1336547998, now seen corresponding path program 1 times [2021-12-16 10:06:03,806 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:03,806 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1648073703] [2021-12-16 10:06:03,806 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:03,806 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:03,829 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:06:03,829 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-16 10:06:03,833 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:06:03,856 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-16 10:06:03,856 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:03,857 INFO L85 PathProgramCache]: Analyzing trace with hash 140407213, now seen corresponding path program 1 times [2021-12-16 10:06:03,857 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:03,857 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1301267679] [2021-12-16 10:06:03,857 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:03,857 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:03,859 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:06:03,859 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-16 10:06:03,860 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:06:03,862 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-16 10:06:03,862 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:03,862 INFO L85 PathProgramCache]: Analyzing trace with hash 182662538, now seen corresponding path program 1 times [2021-12-16 10:06:03,862 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:03,862 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [552560497] [2021-12-16 10:06:03,862 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:03,862 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:03,888 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:06:03,901 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:06:03,902 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:06:03,902 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [552560497] [2021-12-16 10:06:03,902 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [552560497] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:06:03,902 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:06:03,902 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:06:03,902 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2074827701] [2021-12-16 10:06:03,903 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:06:04,026 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:06:04,026 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-16 10:06:04,026 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-16 10:06:04,027 INFO L87 Difference]: Start difference. First operand 46454 states and 58096 transitions. cyclomatic complexity: 11682 Second operand has 3 states, 3 states have (on average 29.0) internal successors, (87), 3 states have internal predecessors, (87), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:04,239 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:06:04,239 INFO L93 Difference]: Finished difference Result 67501 states and 83307 transitions. [2021-12-16 10:06:04,239 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-16 10:06:04,240 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 67501 states and 83307 transitions. [2021-12-16 10:06:04,502 INFO L131 ngComponentsAnalysis]: Automaton has 44 accepting balls. 63381 [2021-12-16 10:06:05,003 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 67501 states to 67501 states and 83307 transitions. [2021-12-16 10:06:05,004 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 67501 [2021-12-16 10:06:05,037 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 67501 [2021-12-16 10:06:05,038 INFO L73 IsDeterministic]: Start isDeterministic. Operand 67501 states and 83307 transitions. [2021-12-16 10:06:05,072 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:06:05,072 INFO L681 BuchiCegarLoop]: Abstraction has 67501 states and 83307 transitions. [2021-12-16 10:06:05,097 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 67501 states and 83307 transitions. [2021-12-16 10:06:05,582 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 67501 to 65331. [2021-12-16 10:06:05,630 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 65331 states, 65331 states have (on average 1.2374217446541458) internal successors, (80842), 65330 states have internal predecessors, (80842), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:05,740 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 65331 states to 65331 states and 80842 transitions. [2021-12-16 10:06:05,741 INFO L704 BuchiCegarLoop]: Abstraction has 65331 states and 80842 transitions. [2021-12-16 10:06:05,741 INFO L587 BuchiCegarLoop]: Abstraction has 65331 states and 80842 transitions. [2021-12-16 10:06:05,741 INFO L425 BuchiCegarLoop]: ======== Iteration 27============ [2021-12-16 10:06:05,741 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 65331 states and 80842 transitions. [2021-12-16 10:06:05,937 INFO L131 ngComponentsAnalysis]: Automaton has 44 accepting balls. 61211 [2021-12-16 10:06:05,937 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:06:05,937 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:06:05,938 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:05,938 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:05,938 INFO L791 eck$LassoCheckResult]: Stem: 1006303#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 1006261#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 1006248#L863 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1006244#L394 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1006121#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 1006122#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1005895#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1005896#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1006242#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1006243#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1006202#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1005865#L586 assume !(0 == ~M_E~0); 1005866#L586-2 assume !(0 == ~T1_E~0); 1005920#L591-1 assume !(0 == ~T2_E~0); 1006058#L596-1 assume !(0 == ~T3_E~0); 1006059#L601-1 assume !(0 == ~T4_E~0); 1006110#L606-1 assume !(0 == ~T5_E~0); 1006111#L611-1 assume !(0 == ~E_1~0); 1006213#L616-1 assume !(0 == ~E_2~0); 1006214#L621-1 assume !(0 == ~E_3~0); 1005796#L626-1 assume !(0 == ~E_4~0); 1005797#L631-1 assume !(0 == ~E_5~0); 1005953#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1005792#L279 assume !(1 == ~m_pc~0); 1005793#L279-2 is_master_triggered_~__retres1~0#1 := 0; 1006132#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1006030#L291 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1006031#L720 assume !(0 != activate_threads_~tmp~1#1); 1006131#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1005959#L298 assume !(1 == ~t1_pc~0); 1005754#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1005755#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1006019#L310 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1005806#L728 assume !(0 != activate_threads_~tmp___0~0#1); 1005807#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1005925#L317 assume !(1 == ~t2_pc~0); 1005926#L317-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1006156#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1006256#L329 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1005967#L736 assume !(0 != activate_threads_~tmp___1~0#1); 1005968#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1006198#L336 assume !(1 == ~t3_pc~0); 1006199#L336-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1006285#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1006088#L348 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1006089#L744 assume !(0 != activate_threads_~tmp___2~0#1); 1006142#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1006207#L355 assume !(1 == ~t4_pc~0); 1006055#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1005881#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1005882#L367 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1006125#L752 assume !(0 != activate_threads_~tmp___3~0#1); 1005817#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1005818#L374 assume !(1 == ~t5_pc~0); 1005943#L374-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1005944#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1006028#L386 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1006029#L760 assume !(0 != activate_threads_~tmp___4~0#1); 1006091#L760-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1006092#L649 assume !(1 == ~M_E~0); 1006276#L649-2 assume !(1 == ~T1_E~0); 1005781#L654-1 assume !(1 == ~T2_E~0); 1005782#L659-1 assume !(1 == ~T3_E~0); 1005966#L664-1 assume !(1 == ~T4_E~0); 1005774#L669-1 assume !(1 == ~T5_E~0); 1005775#L674-1 assume !(1 == ~E_1~0); 1006194#L679-1 assume !(1 == ~E_2~0); 1005869#L684-1 assume !(1 == ~E_3~0); 1005870#L689-1 assume !(1 == ~E_4~0); 1006051#L694-1 assume !(1 == ~E_5~0); 1006049#L699-1 assume { :end_inline_reset_delta_events } true; 1006050#L900-2 assume !false; 1020065#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1019895#L561 [2021-12-16 10:06:05,939 INFO L793 eck$LassoCheckResult]: Loop: 1019895#L561 assume !false; 1020062#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 1020059#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 1020056#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 1020054#L472 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1020052#L486 assume 0 != eval_~tmp~0#1; 1020049#L486-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 1020045#L494 assume !(0 != eval_~tmp_ndt_1~0#1); 1020041#L491 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 1020038#L508 assume !(0 != eval_~tmp_ndt_2~0#1); 1020035#L505 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 1020032#L522 assume !(0 != eval_~tmp_ndt_3~0#1); 1020017#L519 assume !(0 == ~t3_st~0); 1020015#L533 assume !(0 == ~t4_st~0); 1019992#L547 assume !(0 == ~t5_st~0); 1019895#L561 [2021-12-16 10:06:05,939 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:05,939 INFO L85 PathProgramCache]: Analyzing trace with hash 1336547998, now seen corresponding path program 2 times [2021-12-16 10:06:05,939 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:05,939 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2089278707] [2021-12-16 10:06:05,939 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:05,940 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:05,957 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:06:05,957 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-16 10:06:05,960 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:06:05,968 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-16 10:06:05,969 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:05,969 INFO L85 PathProgramCache]: Analyzing trace with hash -111462417, now seen corresponding path program 1 times [2021-12-16 10:06:05,969 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:05,969 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [999274381] [2021-12-16 10:06:05,970 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:05,970 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:05,972 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:06:05,972 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-16 10:06:05,973 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:06:05,974 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-16 10:06:05,974 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:05,975 INFO L85 PathProgramCache]: Analyzing trace with hash 1198452658, now seen corresponding path program 1 times [2021-12-16 10:06:05,975 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:05,975 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [620217694] [2021-12-16 10:06:05,975 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:05,975 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:05,980 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:06:05,992 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:06:05,993 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:06:05,993 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [620217694] [2021-12-16 10:06:05,993 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [620217694] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:06:05,993 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:06:05,993 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:06:05,993 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2064974761] [2021-12-16 10:06:05,993 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:06:06,099 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:06:06,100 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-16 10:06:06,100 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-16 10:06:06,100 INFO L87 Difference]: Start difference. First operand 65331 states and 80842 transitions. cyclomatic complexity: 15555 Second operand has 3 states, 3 states have (on average 29.333333333333332) internal successors, (88), 3 states have internal predecessors, (88), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:06,584 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:06:06,584 INFO L93 Difference]: Finished difference Result 70203 states and 85948 transitions. [2021-12-16 10:06:06,585 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-16 10:06:06,585 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 70203 states and 85948 transitions. [2021-12-16 10:06:06,835 INFO L131 ngComponentsAnalysis]: Automaton has 46 accepting balls. 63517 [2021-12-16 10:06:06,995 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 70203 states to 70203 states and 85948 transitions. [2021-12-16 10:06:06,995 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 70203 [2021-12-16 10:06:07,037 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 70203 [2021-12-16 10:06:07,037 INFO L73 IsDeterministic]: Start isDeterministic. Operand 70203 states and 85948 transitions. [2021-12-16 10:06:07,074 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:06:07,075 INFO L681 BuchiCegarLoop]: Abstraction has 70203 states and 85948 transitions. [2021-12-16 10:06:07,111 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 70203 states and 85948 transitions. [2021-12-16 10:06:07,933 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 70203 to 70203. [2021-12-16 10:06:07,976 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 70203 states, 70203 states have (on average 1.224278164750794) internal successors, (85948), 70202 states have internal predecessors, (85948), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:08,089 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 70203 states to 70203 states and 85948 transitions. [2021-12-16 10:06:08,089 INFO L704 BuchiCegarLoop]: Abstraction has 70203 states and 85948 transitions. [2021-12-16 10:06:08,090 INFO L587 BuchiCegarLoop]: Abstraction has 70203 states and 85948 transitions. [2021-12-16 10:06:08,090 INFO L425 BuchiCegarLoop]: ======== Iteration 28============ [2021-12-16 10:06:08,090 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 70203 states and 85948 transitions. [2021-12-16 10:06:08,316 INFO L131 ngComponentsAnalysis]: Automaton has 46 accepting balls. 63517 [2021-12-16 10:06:08,316 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:06:08,317 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:06:08,317 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:08,317 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:08,318 INFO L791 eck$LassoCheckResult]: Stem: 1141873#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 1141818#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 1141802#L863 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1141799#L394 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1141662#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 1141663#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1141438#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1141439#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1141797#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1141798#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1141752#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1141406#L586 assume !(0 == ~M_E~0); 1141407#L586-2 assume !(0 == ~T1_E~0); 1141463#L591-1 assume !(0 == ~T2_E~0); 1141596#L596-1 assume !(0 == ~T3_E~0); 1141597#L601-1 assume !(0 == ~T4_E~0); 1141650#L606-1 assume !(0 == ~T5_E~0); 1141651#L611-1 assume !(0 == ~E_1~0); 1141761#L616-1 assume !(0 == ~E_2~0); 1141762#L621-1 assume !(0 == ~E_3~0); 1141339#L626-1 assume !(0 == ~E_4~0); 1141340#L631-1 assume !(0 == ~E_5~0); 1141498#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1141335#L279 assume !(1 == ~m_pc~0); 1141336#L279-2 is_master_triggered_~__retres1~0#1 := 0; 1141675#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1141571#L291 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1141572#L720 assume !(0 != activate_threads_~tmp~1#1); 1141674#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1141505#L298 assume !(1 == ~t1_pc~0); 1141296#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1141297#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1141561#L310 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1141349#L728 assume !(0 != activate_threads_~tmp___0~0#1); 1141350#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1141468#L317 assume !(1 == ~t2_pc~0); 1141469#L317-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1141700#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1141811#L329 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1141513#L736 assume !(0 != activate_threads_~tmp___1~0#1); 1141514#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1141748#L336 assume !(1 == ~t3_pc~0); 1141749#L336-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1141848#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1141631#L348 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1141632#L744 assume !(0 != activate_threads_~tmp___2~0#1); 1141686#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1141756#L355 assume !(1 == ~t4_pc~0); 1141593#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1141423#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1141424#L367 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1141666#L752 assume !(0 != activate_threads_~tmp___3~0#1); 1141359#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1141360#L374 assume !(1 == ~t5_pc~0); 1141487#L374-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1141488#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1141569#L386 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1141570#L760 assume !(0 != activate_threads_~tmp___4~0#1); 1141635#L760-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1141636#L649 assume !(1 == ~M_E~0); 1141840#L649-2 assume !(1 == ~T1_E~0); 1141323#L654-1 assume !(1 == ~T2_E~0); 1141324#L659-1 assume !(1 == ~T3_E~0); 1141512#L664-1 assume !(1 == ~T4_E~0); 1141316#L669-1 assume !(1 == ~T5_E~0); 1141317#L674-1 assume !(1 == ~E_1~0); 1141744#L679-1 assume !(1 == ~E_2~0); 1141412#L684-1 assume !(1 == ~E_3~0); 1141413#L689-1 assume !(1 == ~E_4~0); 1141589#L694-1 assume !(1 == ~E_5~0); 1141587#L699-1 assume { :end_inline_reset_delta_events } true; 1141588#L900-2 assume !false; 1153627#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1153624#L561 [2021-12-16 10:06:08,318 INFO L793 eck$LassoCheckResult]: Loop: 1153624#L561 assume !false; 1153622#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 1153617#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 1153612#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 1153613#L472 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1170161#L486 assume 0 != eval_~tmp~0#1; 1170158#L486-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 1153595#L494 assume !(0 != eval_~tmp_ndt_1~0#1); 1150317#L491 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 1150307#L508 assume !(0 != eval_~tmp_ndt_2~0#1); 1150292#L505 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 1150293#L522 assume !(0 != eval_~tmp_ndt_3~0#1); 1153647#L519 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 1153648#L536 assume !(0 != eval_~tmp_ndt_4~0#1); 1153634#L533 assume !(0 == ~t4_st~0); 1153636#L547 assume !(0 == ~t5_st~0); 1153624#L561 [2021-12-16 10:06:08,318 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:08,318 INFO L85 PathProgramCache]: Analyzing trace with hash 1336547998, now seen corresponding path program 3 times [2021-12-16 10:06:08,319 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:08,319 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1448595410] [2021-12-16 10:06:08,319 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:08,319 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:08,325 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:06:08,326 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-16 10:06:08,330 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:06:08,340 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-16 10:06:08,341 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:08,341 INFO L85 PathProgramCache]: Analyzing trace with hash 834182516, now seen corresponding path program 1 times [2021-12-16 10:06:08,341 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:08,341 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1585699819] [2021-12-16 10:06:08,341 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:08,341 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:08,344 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:06:08,344 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-16 10:06:08,345 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:06:08,346 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-16 10:06:08,346 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:08,346 INFO L85 PathProgramCache]: Analyzing trace with hash -1508123119, now seen corresponding path program 1 times [2021-12-16 10:06:08,346 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:08,346 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1700917280] [2021-12-16 10:06:08,347 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:08,347 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:08,352 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:06:08,366 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:06:08,366 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:06:08,367 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1700917280] [2021-12-16 10:06:08,367 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1700917280] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:06:08,367 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:06:08,367 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:06:08,367 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [96343092] [2021-12-16 10:06:08,367 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:06:08,501 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:06:08,502 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-16 10:06:08,502 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-16 10:06:08,502 INFO L87 Difference]: Start difference. First operand 70203 states and 85948 transitions. cyclomatic complexity: 15791 Second operand has 3 states, 3 states have (on average 29.666666666666668) internal successors, (89), 3 states have internal predecessors, (89), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:08,822 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:06:08,822 INFO L93 Difference]: Finished difference Result 110222 states and 135053 transitions. [2021-12-16 10:06:08,823 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-16 10:06:08,823 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 110222 states and 135053 transitions. [2021-12-16 10:06:09,782 INFO L131 ngComponentsAnalysis]: Automaton has 46 accepting balls. 96924 [2021-12-16 10:06:10,086 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 110222 states to 110222 states and 135053 transitions. [2021-12-16 10:06:10,086 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 110222 [2021-12-16 10:06:10,164 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 110222 [2021-12-16 10:06:10,165 INFO L73 IsDeterministic]: Start isDeterministic. Operand 110222 states and 135053 transitions. [2021-12-16 10:06:10,224 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:06:10,224 INFO L681 BuchiCegarLoop]: Abstraction has 110222 states and 135053 transitions. [2021-12-16 10:06:10,293 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 110222 states and 135053 transitions. [2021-12-16 10:06:11,425 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 110222 to 110222. [2021-12-16 10:06:11,593 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 110222 states, 110222 states have (on average 1.2252817041969843) internal successors, (135053), 110221 states have internal predecessors, (135053), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:11,810 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 110222 states to 110222 states and 135053 transitions. [2021-12-16 10:06:11,811 INFO L704 BuchiCegarLoop]: Abstraction has 110222 states and 135053 transitions. [2021-12-16 10:06:11,811 INFO L587 BuchiCegarLoop]: Abstraction has 110222 states and 135053 transitions. [2021-12-16 10:06:11,811 INFO L425 BuchiCegarLoop]: ======== Iteration 29============ [2021-12-16 10:06:11,811 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 110222 states and 135053 transitions. [2021-12-16 10:06:12,173 INFO L131 ngComponentsAnalysis]: Automaton has 46 accepting balls. 96924 [2021-12-16 10:06:12,174 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:06:12,174 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:06:12,174 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:12,174 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:12,175 INFO L791 eck$LassoCheckResult]: Stem: 1322331#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 1322265#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 1322251#L863 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1322248#L394 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1322101#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 1322102#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1321876#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1321877#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1322246#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1322247#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1322194#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1321846#L586 assume !(0 == ~M_E~0); 1321847#L586-2 assume !(0 == ~T1_E~0); 1321900#L591-1 assume !(0 == ~T2_E~0); 1322037#L596-1 assume !(0 == ~T3_E~0); 1322038#L601-1 assume !(0 == ~T4_E~0); 1322090#L606-1 assume !(0 == ~T5_E~0); 1322091#L611-1 assume !(0 == ~E_1~0); 1322203#L616-1 assume !(0 == ~E_2~0); 1322204#L621-1 assume !(0 == ~E_3~0); 1321772#L626-1 assume !(0 == ~E_4~0); 1321773#L631-1 assume !(0 == ~E_5~0); 1321936#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1321770#L279 assume !(1 == ~m_pc~0); 1321771#L279-2 is_master_triggered_~__retres1~0#1 := 0; 1322116#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1322012#L291 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1322013#L720 assume !(0 != activate_threads_~tmp~1#1); 1322115#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1321943#L298 assume !(1 == ~t1_pc~0); 1321731#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1321732#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1322002#L310 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1321782#L728 assume !(0 != activate_threads_~tmp___0~0#1); 1321783#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1321905#L317 assume !(1 == ~t2_pc~0); 1321906#L317-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1322141#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1322260#L329 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1321954#L736 assume !(0 != activate_threads_~tmp___1~0#1); 1321955#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1322190#L336 assume !(1 == ~t3_pc~0); 1322191#L336-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1322295#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1322066#L348 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1322067#L744 assume !(0 != activate_threads_~tmp___2~0#1); 1322127#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1322197#L355 assume !(1 == ~t4_pc~0); 1322036#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1321863#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1321864#L367 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1322105#L752 assume !(0 != activate_threads_~tmp___3~0#1); 1321796#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1321797#L374 assume !(1 == ~t5_pc~0); 1321924#L374-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1321925#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1322010#L386 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1322011#L760 assume !(0 != activate_threads_~tmp___4~0#1); 1322070#L760-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1322071#L649 assume !(1 == ~M_E~0); 1322288#L649-2 assume !(1 == ~T1_E~0); 1321756#L654-1 assume !(1 == ~T2_E~0); 1321757#L659-1 assume !(1 == ~T3_E~0); 1321951#L664-1 assume !(1 == ~T4_E~0); 1321749#L669-1 assume !(1 == ~T5_E~0); 1321750#L674-1 assume !(1 == ~E_1~0); 1322183#L679-1 assume !(1 == ~E_2~0); 1321848#L684-1 assume !(1 == ~E_3~0); 1321849#L689-1 assume !(1 == ~E_4~0); 1322030#L694-1 assume !(1 == ~E_5~0); 1322028#L699-1 assume { :end_inline_reset_delta_events } true; 1322029#L900-2 assume !false; 1335870#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1335871#L561 [2021-12-16 10:06:12,175 INFO L793 eck$LassoCheckResult]: Loop: 1335871#L561 assume !false; 1364424#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 1364423#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 1364422#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 1364421#L472 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1364420#L486 assume 0 != eval_~tmp~0#1; 1364419#L486-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 1364417#L494 assume !(0 != eval_~tmp_ndt_1~0#1); 1364415#L491 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 1364414#L508 assume !(0 != eval_~tmp_ndt_2~0#1); 1364413#L505 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 1364412#L522 assume !(0 != eval_~tmp_ndt_3~0#1); 1364411#L519 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 1364410#L536 assume !(0 != eval_~tmp_ndt_4~0#1); 1364409#L533 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0#1;eval_~tmp_ndt_5~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 1335969#L550 assume !(0 != eval_~tmp_ndt_5~0#1); 1364407#L547 assume !(0 == ~t5_st~0); 1335871#L561 [2021-12-16 10:06:12,175 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:12,175 INFO L85 PathProgramCache]: Analyzing trace with hash 1336547998, now seen corresponding path program 4 times [2021-12-16 10:06:12,176 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:12,176 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2105516666] [2021-12-16 10:06:12,176 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:12,176 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:12,181 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:06:12,181 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-16 10:06:12,184 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:06:12,192 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-16 10:06:12,193 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:12,193 INFO L85 PathProgramCache]: Analyzing trace with hash 89684008, now seen corresponding path program 1 times [2021-12-16 10:06:12,193 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:12,193 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1720590755] [2021-12-16 10:06:12,193 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:12,193 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:12,196 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:06:12,196 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-16 10:06:12,197 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:06:12,198 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-16 10:06:12,198 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:12,198 INFO L85 PathProgramCache]: Analyzing trace with hash 492653355, now seen corresponding path program 1 times [2021-12-16 10:06:12,199 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:12,199 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1768684678] [2021-12-16 10:06:12,199 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:12,199 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:12,204 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:06:12,216 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:06:12,216 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:06:12,217 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1768684678] [2021-12-16 10:06:12,217 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1768684678] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:06:12,217 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:06:12,217 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-16 10:06:12,217 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1648785961] [2021-12-16 10:06:12,217 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:06:12,364 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:06:12,365 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-16 10:06:12,365 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-16 10:06:12,365 INFO L87 Difference]: Start difference. First operand 110222 states and 135053 transitions. cyclomatic complexity: 24877 Second operand has 3 states, 2 states have (on average 45.0) internal successors, (90), 3 states have internal predecessors, (90), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:12,877 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:06:12,878 INFO L93 Difference]: Finished difference Result 177709 states and 216599 transitions. [2021-12-16 10:06:12,878 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-16 10:06:12,879 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 177709 states and 216599 transitions. [2021-12-16 10:06:14,196 INFO L131 ngComponentsAnalysis]: Automaton has 47 accepting balls. 152715 [2021-12-16 10:06:14,673 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 177709 states to 177709 states and 216599 transitions. [2021-12-16 10:06:14,674 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 177709 [2021-12-16 10:06:14,765 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 177709 [2021-12-16 10:06:14,766 INFO L73 IsDeterministic]: Start isDeterministic. Operand 177709 states and 216599 transitions. [2021-12-16 10:06:14,855 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:06:14,856 INFO L681 BuchiCegarLoop]: Abstraction has 177709 states and 216599 transitions. [2021-12-16 10:06:14,957 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 177709 states and 216599 transitions. [2021-12-16 10:06:17,069 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 177709 to 177709. [2021-12-16 10:06:17,228 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 177709 states, 177709 states have (on average 1.2188409140786343) internal successors, (216599), 177708 states have internal predecessors, (216599), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:17,540 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 177709 states to 177709 states and 216599 transitions. [2021-12-16 10:06:17,540 INFO L704 BuchiCegarLoop]: Abstraction has 177709 states and 216599 transitions. [2021-12-16 10:06:17,540 INFO L587 BuchiCegarLoop]: Abstraction has 177709 states and 216599 transitions. [2021-12-16 10:06:17,540 INFO L425 BuchiCegarLoop]: ======== Iteration 30============ [2021-12-16 10:06:17,540 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 177709 states and 216599 transitions. [2021-12-16 10:06:18,063 INFO L131 ngComponentsAnalysis]: Automaton has 47 accepting balls. 152715 [2021-12-16 10:06:18,064 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:06:18,064 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:06:18,064 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:18,065 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:18,065 INFO L791 eck$LassoCheckResult]: Stem: 1610267#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 1610204#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 1610190#L863 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1610187#L394 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1610048#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 1610049#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1609815#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1609816#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1610185#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1610186#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1610140#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1609784#L586 assume !(0 == ~M_E~0); 1609785#L586-2 assume !(0 == ~T1_E~0); 1609841#L591-1 assume !(0 == ~T2_E~0); 1609981#L596-1 assume !(0 == ~T3_E~0); 1609982#L601-1 assume !(0 == ~T4_E~0); 1610035#L606-1 assume !(0 == ~T5_E~0); 1610036#L611-1 assume !(0 == ~E_1~0); 1610148#L616-1 assume !(0 == ~E_2~0); 1610149#L621-1 assume !(0 == ~E_3~0); 1609711#L626-1 assume !(0 == ~E_4~0); 1609712#L631-1 assume !(0 == ~E_5~0); 1609876#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1609709#L279 assume !(1 == ~m_pc~0); 1609710#L279-2 is_master_triggered_~__retres1~0#1 := 0; 1610062#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1609955#L291 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1609956#L720 assume !(0 != activate_threads_~tmp~1#1); 1610061#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1609882#L298 assume !(1 == ~t1_pc~0); 1609670#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1609671#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1609945#L310 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1609721#L728 assume !(0 != activate_threads_~tmp___0~0#1); 1609722#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1609846#L317 assume !(1 == ~t2_pc~0); 1609847#L317-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1610087#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1610201#L329 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1609894#L736 assume !(0 != activate_threads_~tmp___1~0#1); 1609895#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1610136#L336 assume !(1 == ~t3_pc~0); 1610137#L336-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1610237#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1610013#L348 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1610014#L744 assume !(0 != activate_threads_~tmp___2~0#1); 1610073#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1610144#L355 assume !(1 == ~t4_pc~0); 1609980#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1609802#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1609803#L367 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1610053#L752 assume !(0 != activate_threads_~tmp___3~0#1); 1609735#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1609736#L374 assume !(1 == ~t5_pc~0); 1609865#L374-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1609866#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1609953#L386 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1609954#L760 assume !(0 != activate_threads_~tmp___4~0#1); 1610016#L760-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1610017#L649 assume !(1 == ~M_E~0); 1610226#L649-2 assume !(1 == ~T1_E~0); 1609695#L654-1 assume !(1 == ~T2_E~0); 1609696#L659-1 assume !(1 == ~T3_E~0); 1609891#L664-1 assume !(1 == ~T4_E~0); 1609688#L669-1 assume !(1 == ~T5_E~0); 1609689#L674-1 assume !(1 == ~E_1~0); 1610128#L679-1 assume !(1 == ~E_2~0); 1609786#L684-1 assume !(1 == ~E_3~0); 1609787#L689-1 assume !(1 == ~E_4~0); 1609974#L694-1 assume !(1 == ~E_5~0); 1609972#L699-1 assume { :end_inline_reset_delta_events } true; 1609973#L900-2 assume !false; 1650192#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1635275#L561 [2021-12-16 10:06:18,065 INFO L793 eck$LassoCheckResult]: Loop: 1635275#L561 assume !false; 1650189#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 1650186#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 1650184#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 1650182#L472 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1650179#L486 assume 0 != eval_~tmp~0#1; 1650175#L486-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 1650172#L494 assume !(0 != eval_~tmp_ndt_1~0#1); 1650173#L491 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 1651400#L508 assume !(0 != eval_~tmp_ndt_2~0#1); 1651401#L505 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 1652648#L522 assume !(0 != eval_~tmp_ndt_3~0#1); 1652649#L519 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 1663334#L536 assume !(0 != eval_~tmp_ndt_4~0#1); 1663332#L533 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0#1;eval_~tmp_ndt_5~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 1649229#L550 assume !(0 != eval_~tmp_ndt_5~0#1); 1649508#L547 assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0#1;eval_~tmp_ndt_6~0#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 1635274#L564 assume !(0 != eval_~tmp_ndt_6~0#1); 1635275#L561 [2021-12-16 10:06:18,065 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:18,065 INFO L85 PathProgramCache]: Analyzing trace with hash 1336547998, now seen corresponding path program 5 times [2021-12-16 10:06:18,066 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:18,066 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [134423223] [2021-12-16 10:06:18,066 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:18,066 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:18,071 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:06:18,071 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-16 10:06:18,075 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:06:18,082 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-16 10:06:18,083 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:18,083 INFO L85 PathProgramCache]: Analyzing trace with hash -1514762949, now seen corresponding path program 1 times [2021-12-16 10:06:18,083 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:18,083 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1184687708] [2021-12-16 10:06:18,083 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:18,084 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:18,086 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:06:18,086 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-16 10:06:18,087 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:06:18,089 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-16 10:06:18,089 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:18,089 INFO L85 PathProgramCache]: Analyzing trace with hash -1907615080, now seen corresponding path program 1 times [2021-12-16 10:06:18,089 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:18,089 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [970127863] [2021-12-16 10:06:18,089 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:18,090 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:18,094 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:06:18,095 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-16 10:06:18,099 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-16 10:06:18,109 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-16 10:06:19,386 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 16.12 10:06:19 BoogieIcfgContainer [2021-12-16 10:06:19,387 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2021-12-16 10:06:19,387 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2021-12-16 10:06:19,387 INFO L271 PluginConnector]: Initializing Witness Printer... [2021-12-16 10:06:19,387 INFO L275 PluginConnector]: Witness Printer initialized [2021-12-16 10:06:19,388 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 16.12 10:05:45" (3/4) ... [2021-12-16 10:06:19,389 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2021-12-16 10:06:19,441 INFO L141 WitnessManager]: Wrote witness to /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/witness.graphml [2021-12-16 10:06:19,441 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2021-12-16 10:06:19,442 INFO L158 Benchmark]: Toolchain (without parser) took 35771.32ms. Allocated memory was 94.4MB in the beginning and 13.0GB in the end (delta: 12.9GB). Free memory was 53.6MB in the beginning and 9.7GB in the end (delta: -9.6GB). Peak memory consumption was 3.3GB. Max. memory is 16.1GB. [2021-12-16 10:06:19,442 INFO L158 Benchmark]: CDTParser took 0.15ms. Allocated memory is still 94.4MB. Free memory is still 70.8MB. There was no memory consumed. Max. memory is 16.1GB. [2021-12-16 10:06:19,442 INFO L158 Benchmark]: CACSL2BoogieTranslator took 389.65ms. Allocated memory is still 94.4MB. Free memory was 53.3MB in the beginning and 66.9MB in the end (delta: -13.5MB). Peak memory consumption was 11.0MB. Max. memory is 16.1GB. [2021-12-16 10:06:19,442 INFO L158 Benchmark]: Boogie Procedure Inliner took 102.14ms. Allocated memory is still 94.4MB. Free memory was 66.4MB in the beginning and 62.2MB in the end (delta: 4.2MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2021-12-16 10:06:19,443 INFO L158 Benchmark]: Boogie Preprocessor took 125.32ms. Allocated memory is still 94.4MB. Free memory was 61.7MB in the beginning and 57.4MB in the end (delta: 4.3MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2021-12-16 10:06:19,443 INFO L158 Benchmark]: RCFGBuilder took 965.77ms. Allocated memory was 94.4MB in the beginning and 157.3MB in the end (delta: 62.9MB). Free memory was 57.4MB in the beginning and 94.1MB in the end (delta: -36.7MB). Peak memory consumption was 25.2MB. Max. memory is 16.1GB. [2021-12-16 10:06:19,443 INFO L158 Benchmark]: BuchiAutomizer took 34126.72ms. Allocated memory was 157.3MB in the beginning and 13.0GB in the end (delta: 12.9GB). Free memory was 94.1MB in the beginning and 9.7GB in the end (delta: -9.6GB). Peak memory consumption was 3.3GB. Max. memory is 16.1GB. [2021-12-16 10:06:19,444 INFO L158 Benchmark]: Witness Printer took 53.85ms. Allocated memory is still 13.0GB. Free memory was 9.7GB in the beginning and 9.7GB in the end (delta: 4.2MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2021-12-16 10:06:19,445 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.15ms. Allocated memory is still 94.4MB. Free memory is still 70.8MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 389.65ms. Allocated memory is still 94.4MB. Free memory was 53.3MB in the beginning and 66.9MB in the end (delta: -13.5MB). Peak memory consumption was 11.0MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 102.14ms. Allocated memory is still 94.4MB. Free memory was 66.4MB in the beginning and 62.2MB in the end (delta: 4.2MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * Boogie Preprocessor took 125.32ms. Allocated memory is still 94.4MB. Free memory was 61.7MB in the beginning and 57.4MB in the end (delta: 4.3MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * RCFGBuilder took 965.77ms. Allocated memory was 94.4MB in the beginning and 157.3MB in the end (delta: 62.9MB). Free memory was 57.4MB in the beginning and 94.1MB in the end (delta: -36.7MB). Peak memory consumption was 25.2MB. Max. memory is 16.1GB. * BuchiAutomizer took 34126.72ms. Allocated memory was 157.3MB in the beginning and 13.0GB in the end (delta: 12.9GB). Free memory was 94.1MB in the beginning and 9.7GB in the end (delta: -9.6GB). Peak memory consumption was 3.3GB. Max. memory is 16.1GB. * Witness Printer took 53.85ms. Allocated memory is still 13.0GB. Free memory was 9.7GB in the beginning and 9.7GB in the end (delta: 4.2MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 29 terminating modules (29 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.29 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 177709 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 34.0s and 30 iterations. TraceHistogramMax:3. Analysis of lassos took 4.1s. Construction of modules took 0.7s. Büchi inclusion checks took 3.9s. Highest rank in rank-based complementation 0. Minimization of det autom 29. Minimization of nondet autom 0. Automata minimization 11.8s AutomataMinimizationTime, 29 MinimizatonAttempts, 111205 StatesRemovedByMinimization, 16 NontrivialMinimizations. Non-live state removal took 9.1s Buchi closure took 0.6s. Biggest automaton had 177709 states and ocurred in iteration 29. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 30260 SdHoareTripleChecker+Valid, 1.1s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 30260 mSDsluCounter, 46710 SdHoareTripleChecker+Invalid, 0.7s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 25292 mSDsCounter, 454 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 1085 IncrementalHoareTripleChecker+Invalid, 1539 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 454 mSolverCounterUnsat, 21418 mSDtfsCounter, 1085 mSolverCounterSat, 0.3s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI11 SFLT0 conc4 concLT0 SILN0 SILU0 SILI14 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - FixpointNonTerminationResult [Line: 481]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite execution State at position 0 is {NULL=1} State at position 1 is {tmp_ndt_3=0, NULL=0, t3_st=0, NULL=1, tmp=0, t5_i=1, __retres1=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@4cec5bce=0, t2_st=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@19700c7c=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@40fa620b=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@3bd1c149=0, tmp_ndt_2=0, \result=0, t4_i=1, \result=0, E_3=2, t4_pc=0, E_5=2, E_1=2, tmp_ndt_1=0, tmp___4=0, tmp=1, \result=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@797b4216=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@7bdb386f=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@3056b229=0, m_st=0, NULL=0, t3_pc=0, tmp___3=0, __retres1=0, tmp___0=0, __retres1=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@31b5e550=0, tmp___2=0, m_pc=0, \result=0, \result=1, __retres1=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@5ef0f85a=0, \result=0, \result=0, tmp___1=0, T2_E=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@33873d2e=0, tmp_ndt_6=0, tmp=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@152ba52c=0, t1_pc=0, t5_st=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@22db3a82=0, E_2=2, tmp___0=0, E_4=2, T1_E=2, __retres1=0, M_E=2, T5_E=2, t2_i=1, __retres1=1, T4_E=2, \result=0, t3_i=1, t4_st=0, m_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@6e321348=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@c9ef9e9=0, t1_st=0, t5_pc=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@3b1cc1a7=0, __retres1=0, t2_pc=0, tmp_ndt_5=0, __retres1=0, tmp_ndt_4=0, kernel_st=1, T3_E=2, t1_i=1} - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 481]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L25] int m_pc = 0; [L26] int t1_pc = 0; [L27] int t2_pc = 0; [L28] int t3_pc = 0; [L29] int t4_pc = 0; [L30] int t5_pc = 0; [L31] int m_st ; [L32] int t1_st ; [L33] int t2_st ; [L34] int t3_st ; [L35] int t4_st ; [L36] int t5_st ; [L37] int m_i ; [L38] int t1_i ; [L39] int t2_i ; [L40] int t3_i ; [L41] int t4_i ; [L42] int t5_i ; [L43] int M_E = 2; [L44] int T1_E = 2; [L45] int T2_E = 2; [L46] int T3_E = 2; [L47] int T4_E = 2; [L48] int T5_E = 2; [L49] int E_1 = 2; [L50] int E_2 = 2; [L51] int E_3 = 2; [L52] int E_4 = 2; [L53] int E_5 = 2; [L945] int __retres1 ; [L949] CALL init_model() [L856] m_i = 1 [L857] t1_i = 1 [L858] t2_i = 1 [L859] t3_i = 1 [L860] t4_i = 1 [L861] t5_i = 1 [L949] RET init_model() [L950] CALL start_simulation() [L886] int kernel_st ; [L887] int tmp ; [L888] int tmp___0 ; [L892] kernel_st = 0 [L893] FCALL update_channels() [L894] CALL init_threads() [L401] COND TRUE m_i == 1 [L402] m_st = 0 [L406] COND TRUE t1_i == 1 [L407] t1_st = 0 [L411] COND TRUE t2_i == 1 [L412] t2_st = 0 [L416] COND TRUE t3_i == 1 [L417] t3_st = 0 [L421] COND TRUE t4_i == 1 [L422] t4_st = 0 [L426] COND TRUE t5_i == 1 [L427] t5_st = 0 [L894] RET init_threads() [L895] CALL fire_delta_events() [L586] COND FALSE !(M_E == 0) [L591] COND FALSE !(T1_E == 0) [L596] COND FALSE !(T2_E == 0) [L601] COND FALSE !(T3_E == 0) [L606] COND FALSE !(T4_E == 0) [L611] COND FALSE !(T5_E == 0) [L616] COND FALSE !(E_1 == 0) [L621] COND FALSE !(E_2 == 0) [L626] COND FALSE !(E_3 == 0) [L631] COND FALSE !(E_4 == 0) [L636] COND FALSE !(E_5 == 0) [L895] RET fire_delta_events() [L896] CALL activate_threads() [L709] int tmp ; [L710] int tmp___0 ; [L711] int tmp___1 ; [L712] int tmp___2 ; [L713] int tmp___3 ; [L714] int tmp___4 ; [L718] CALL, EXPR is_master_triggered() [L276] int __retres1 ; [L279] COND FALSE !(m_pc == 1) [L289] __retres1 = 0 [L291] return (__retres1); [L718] RET, EXPR is_master_triggered() [L718] tmp = is_master_triggered() [L720] COND FALSE !(\read(tmp)) [L726] CALL, EXPR is_transmit1_triggered() [L295] int __retres1 ; [L298] COND FALSE !(t1_pc == 1) [L308] __retres1 = 0 [L310] return (__retres1); [L726] RET, EXPR is_transmit1_triggered() [L726] tmp___0 = is_transmit1_triggered() [L728] COND FALSE !(\read(tmp___0)) [L734] CALL, EXPR is_transmit2_triggered() [L314] int __retres1 ; [L317] COND FALSE !(t2_pc == 1) [L327] __retres1 = 0 [L329] return (__retres1); [L734] RET, EXPR is_transmit2_triggered() [L734] tmp___1 = is_transmit2_triggered() [L736] COND FALSE !(\read(tmp___1)) [L742] CALL, EXPR is_transmit3_triggered() [L333] int __retres1 ; [L336] COND FALSE !(t3_pc == 1) [L346] __retres1 = 0 [L348] return (__retres1); [L742] RET, EXPR is_transmit3_triggered() [L742] tmp___2 = is_transmit3_triggered() [L744] COND FALSE !(\read(tmp___2)) [L750] CALL, EXPR is_transmit4_triggered() [L352] int __retres1 ; [L355] COND FALSE !(t4_pc == 1) [L365] __retres1 = 0 [L367] return (__retres1); [L750] RET, EXPR is_transmit4_triggered() [L750] tmp___3 = is_transmit4_triggered() [L752] COND FALSE !(\read(tmp___3)) [L758] CALL, EXPR is_transmit5_triggered() [L371] int __retres1 ; [L374] COND FALSE !(t5_pc == 1) [L384] __retres1 = 0 [L386] return (__retres1); [L758] RET, EXPR is_transmit5_triggered() [L758] tmp___4 = is_transmit5_triggered() [L760] COND FALSE !(\read(tmp___4)) [L896] RET activate_threads() [L897] CALL reset_delta_events() [L649] COND FALSE !(M_E == 1) [L654] COND FALSE !(T1_E == 1) [L659] COND FALSE !(T2_E == 1) [L664] COND FALSE !(T3_E == 1) [L669] COND FALSE !(T4_E == 1) [L674] COND FALSE !(T5_E == 1) [L679] COND FALSE !(E_1 == 1) [L684] COND FALSE !(E_2 == 1) [L689] COND FALSE !(E_3 == 1) [L694] COND FALSE !(E_4 == 1) [L699] COND FALSE !(E_5 == 1) [L897] RET reset_delta_events() [L900] COND TRUE 1 [L903] kernel_st = 1 [L904] CALL eval() [L477] int tmp ; Loop: [L481] COND TRUE 1 [L484] CALL, EXPR exists_runnable_thread() [L436] int __retres1 ; [L439] COND TRUE m_st == 0 [L440] __retres1 = 1 [L472] return (__retres1); [L484] RET, EXPR exists_runnable_thread() [L484] tmp = exists_runnable_thread() [L486] COND TRUE \read(tmp) [L491] COND TRUE m_st == 0 [L492] int tmp_ndt_1; [L493] tmp_ndt_1 = __VERIFIER_nondet_int() [L494] COND FALSE !(\read(tmp_ndt_1)) [L505] COND TRUE t1_st == 0 [L506] int tmp_ndt_2; [L507] tmp_ndt_2 = __VERIFIER_nondet_int() [L508] COND FALSE !(\read(tmp_ndt_2)) [L519] COND TRUE t2_st == 0 [L520] int tmp_ndt_3; [L521] tmp_ndt_3 = __VERIFIER_nondet_int() [L522] COND FALSE !(\read(tmp_ndt_3)) [L533] COND TRUE t3_st == 0 [L534] int tmp_ndt_4; [L535] tmp_ndt_4 = __VERIFIER_nondet_int() [L536] COND FALSE !(\read(tmp_ndt_4)) [L547] COND TRUE t4_st == 0 [L548] int tmp_ndt_5; [L549] tmp_ndt_5 = __VERIFIER_nondet_int() [L550] COND FALSE !(\read(tmp_ndt_5)) [L561] COND TRUE t5_st == 0 [L562] int tmp_ndt_6; [L563] tmp_ndt_6 = __VERIFIER_nondet_int() [L564] COND FALSE !(\read(tmp_ndt_6)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2021-12-16 10:06:19,480 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Ended with exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)