./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/transmitter.10.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version c3fed411 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/transmitter.10.cil.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash c68befe0cb772d649d152823cc17c89d77797d55cc04257d4beaaad2b518a7a0 --- Real Ultimate output --- This is Ultimate 0.2.2-tmp.no-commuhash-c3fed41 [2021-12-16 10:05:56,391 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-12-16 10:05:56,393 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-12-16 10:05:56,444 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-12-16 10:05:56,445 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-12-16 10:05:56,448 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-12-16 10:05:56,449 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-12-16 10:05:56,451 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-12-16 10:05:56,452 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-12-16 10:05:56,456 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-12-16 10:05:56,457 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-12-16 10:05:56,458 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-12-16 10:05:56,458 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-12-16 10:05:56,461 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-12-16 10:05:56,462 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-12-16 10:05:56,463 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-12-16 10:05:56,464 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-12-16 10:05:56,465 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-12-16 10:05:56,466 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-12-16 10:05:56,467 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-12-16 10:05:56,468 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-12-16 10:05:56,469 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-12-16 10:05:56,471 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-12-16 10:05:56,472 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-12-16 10:05:56,474 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-12-16 10:05:56,479 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-12-16 10:05:56,479 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-12-16 10:05:56,480 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-12-16 10:05:56,481 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-12-16 10:05:56,481 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-12-16 10:05:56,482 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-12-16 10:05:56,483 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-12-16 10:05:56,484 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-12-16 10:05:56,485 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-12-16 10:05:56,486 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-12-16 10:05:56,486 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-12-16 10:05:56,487 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-12-16 10:05:56,487 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-12-16 10:05:56,488 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-12-16 10:05:56,488 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-12-16 10:05:56,489 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-12-16 10:05:56,490 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2021-12-16 10:05:56,513 INFO L113 SettingsManager]: Loading preferences was successful [2021-12-16 10:05:56,513 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-12-16 10:05:56,513 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2021-12-16 10:05:56,514 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2021-12-16 10:05:56,515 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-12-16 10:05:56,515 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-12-16 10:05:56,515 INFO L138 SettingsManager]: * Use SBE=true [2021-12-16 10:05:56,515 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2021-12-16 10:05:56,515 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2021-12-16 10:05:56,516 INFO L138 SettingsManager]: * Use old map elimination=false [2021-12-16 10:05:56,516 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2021-12-16 10:05:56,516 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2021-12-16 10:05:56,517 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2021-12-16 10:05:56,517 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-12-16 10:05:56,517 INFO L138 SettingsManager]: * sizeof long=4 [2021-12-16 10:05:56,517 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2021-12-16 10:05:56,517 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-12-16 10:05:56,517 INFO L138 SettingsManager]: * sizeof POINTER=4 [2021-12-16 10:05:56,518 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-12-16 10:05:56,518 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2021-12-16 10:05:56,518 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2021-12-16 10:05:56,518 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2021-12-16 10:05:56,518 INFO L138 SettingsManager]: * sizeof long double=12 [2021-12-16 10:05:56,518 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-12-16 10:05:56,519 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2021-12-16 10:05:56,519 INFO L138 SettingsManager]: * Use constant arrays=true [2021-12-16 10:05:56,519 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2021-12-16 10:05:56,519 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-12-16 10:05:56,519 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-12-16 10:05:56,520 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-12-16 10:05:56,520 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-12-16 10:05:56,520 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2021-12-16 10:05:56,521 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2021-12-16 10:05:56,521 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> c68befe0cb772d649d152823cc17c89d77797d55cc04257d4beaaad2b518a7a0 [2021-12-16 10:05:56,744 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-12-16 10:05:56,763 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-12-16 10:05:56,765 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-12-16 10:05:56,766 INFO L271 PluginConnector]: Initializing CDTParser... [2021-12-16 10:05:56,766 INFO L275 PluginConnector]: CDTParser initialized [2021-12-16 10:05:56,767 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/transmitter.10.cil.c [2021-12-16 10:05:56,836 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/5bea99e6d/92b101c04b1e4181968bb7f3def0e04f/FLAGa9b4c31ba [2021-12-16 10:05:57,260 INFO L306 CDTParser]: Found 1 translation units. [2021-12-16 10:05:57,260 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.10.cil.c [2021-12-16 10:05:57,274 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/5bea99e6d/92b101c04b1e4181968bb7f3def0e04f/FLAGa9b4c31ba [2021-12-16 10:05:57,643 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/5bea99e6d/92b101c04b1e4181968bb7f3def0e04f [2021-12-16 10:05:57,645 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-12-16 10:05:57,646 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-12-16 10:05:57,648 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-12-16 10:05:57,648 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-12-16 10:05:57,651 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-12-16 10:05:57,651 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 16.12 10:05:57" (1/1) ... [2021-12-16 10:05:57,653 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@592674ca and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:05:57, skipping insertion in model container [2021-12-16 10:05:57,653 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 16.12 10:05:57" (1/1) ... [2021-12-16 10:05:57,658 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-12-16 10:05:57,691 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-12-16 10:05:57,840 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.10.cil.c[706,719] [2021-12-16 10:05:57,952 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-16 10:05:57,960 INFO L203 MainTranslator]: Completed pre-run [2021-12-16 10:05:57,969 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.10.cil.c[706,719] [2021-12-16 10:05:58,011 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-16 10:05:58,027 INFO L208 MainTranslator]: Completed translation [2021-12-16 10:05:58,027 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:05:58 WrapperNode [2021-12-16 10:05:58,027 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-12-16 10:05:58,028 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-12-16 10:05:58,028 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-12-16 10:05:58,029 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-12-16 10:05:58,034 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:05:58" (1/1) ... [2021-12-16 10:05:58,047 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:05:58" (1/1) ... [2021-12-16 10:05:58,142 INFO L137 Inliner]: procedures = 48, calls = 60, calls flagged for inlining = 55, calls inlined = 196, statements flattened = 2994 [2021-12-16 10:05:58,143 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-12-16 10:05:58,144 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-12-16 10:05:58,144 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-12-16 10:05:58,144 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-12-16 10:05:58,151 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:05:58" (1/1) ... [2021-12-16 10:05:58,151 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:05:58" (1/1) ... [2021-12-16 10:05:58,162 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:05:58" (1/1) ... [2021-12-16 10:05:58,162 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:05:58" (1/1) ... [2021-12-16 10:05:58,190 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:05:58" (1/1) ... [2021-12-16 10:05:58,216 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:05:58" (1/1) ... [2021-12-16 10:05:58,221 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:05:58" (1/1) ... [2021-12-16 10:05:58,231 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-12-16 10:05:58,232 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-12-16 10:05:58,232 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-12-16 10:05:58,233 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-12-16 10:05:58,233 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:05:58" (1/1) ... [2021-12-16 10:05:58,253 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-16 10:05:58,262 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-16 10:05:58,276 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-16 10:05:58,295 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2021-12-16 10:05:58,322 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2021-12-16 10:05:58,323 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2021-12-16 10:05:58,323 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-12-16 10:05:58,323 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-12-16 10:05:58,470 INFO L236 CfgBuilder]: Building ICFG [2021-12-16 10:05:58,484 INFO L262 CfgBuilder]: Building CFG for each procedure with an implementation [2021-12-16 10:05:59,912 INFO L277 CfgBuilder]: Performing block encoding [2021-12-16 10:05:59,937 INFO L296 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-12-16 10:05:59,941 INFO L301 CfgBuilder]: Removed 14 assume(true) statements. [2021-12-16 10:05:59,944 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 16.12 10:05:59 BoogieIcfgContainer [2021-12-16 10:05:59,944 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-12-16 10:05:59,945 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2021-12-16 10:05:59,946 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2021-12-16 10:05:59,949 INFO L275 PluginConnector]: BuchiAutomizer initialized [2021-12-16 10:05:59,949 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-16 10:05:59,949 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 16.12 10:05:57" (1/3) ... [2021-12-16 10:05:59,950 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@7bc48905 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 16.12 10:05:59, skipping insertion in model container [2021-12-16 10:05:59,951 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-16 10:05:59,951 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:05:58" (2/3) ... [2021-12-16 10:05:59,951 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@7bc48905 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 16.12 10:05:59, skipping insertion in model container [2021-12-16 10:05:59,951 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-16 10:05:59,952 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 16.12 10:05:59" (3/3) ... [2021-12-16 10:05:59,953 INFO L388 chiAutomizerObserver]: Analyzing ICFG transmitter.10.cil.c [2021-12-16 10:05:59,986 INFO L359 BuchiCegarLoop]: Interprodecural is true [2021-12-16 10:05:59,986 INFO L360 BuchiCegarLoop]: Hoare is false [2021-12-16 10:05:59,986 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2021-12-16 10:05:59,987 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2021-12-16 10:05:59,987 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2021-12-16 10:05:59,987 INFO L364 BuchiCegarLoop]: Difference is false [2021-12-16 10:05:59,987 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2021-12-16 10:05:59,987 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2021-12-16 10:06:00,028 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1285 states, 1284 states have (on average 1.5093457943925233) internal successors, (1938), 1284 states have internal predecessors, (1938), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:00,104 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1144 [2021-12-16 10:06:00,104 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:06:00,105 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:06:00,126 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:00,126 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:00,126 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2021-12-16 10:06:00,130 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1285 states, 1284 states have (on average 1.5093457943925233) internal successors, (1938), 1284 states have internal predecessors, (1938), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:00,143 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1144 [2021-12-16 10:06:00,143 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:06:00,144 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:06:00,152 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:00,152 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:00,165 INFO L791 eck$LassoCheckResult]: Stem: 617#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 1166#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 1096#L1483true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1051#L694true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1270#L701true assume !(1 == ~m_i~0);~m_st~0 := 2; 1144#L701-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 1164#L706-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 284#L711-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 132#L716-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1186#L721-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 878#L726-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 1069#L731-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 850#L736-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 924#L741-1true assume 1 == ~t9_i~0;~t9_st~0 := 0; 1224#L746-1true assume !(1 == ~t10_i~0);~t10_st~0 := 2; 159#L751-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 792#L1006true assume !(0 == ~M_E~0); 83#L1006-2true assume !(0 == ~T1_E~0); 978#L1011-1true assume !(0 == ~T2_E~0); 1017#L1016-1true assume 0 == ~T3_E~0;~T3_E~0 := 1; 1169#L1021-1true assume !(0 == ~T4_E~0); 25#L1026-1true assume !(0 == ~T5_E~0); 1237#L1031-1true assume !(0 == ~T6_E~0); 562#L1036-1true assume !(0 == ~T7_E~0); 559#L1041-1true assume !(0 == ~T8_E~0); 896#L1046-1true assume !(0 == ~T9_E~0); 178#L1051-1true assume !(0 == ~T10_E~0); 702#L1056-1true assume 0 == ~E_1~0;~E_1~0 := 1; 748#L1061-1true assume !(0 == ~E_2~0); 134#L1066-1true assume !(0 == ~E_3~0); 1061#L1071-1true assume !(0 == ~E_4~0); 680#L1076-1true assume !(0 == ~E_5~0); 88#L1081-1true assume !(0 == ~E_6~0); 271#L1086-1true assume !(0 == ~E_7~0); 1075#L1091-1true assume !(0 == ~E_8~0); 951#L1096-1true assume 0 == ~E_9~0;~E_9~0 := 1; 1170#L1101-1true assume !(0 == ~E_10~0); 308#L1106-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1086#L484true assume !(1 == ~m_pc~0); 371#L484-2true is_master_triggered_~__retres1~0#1 := 0; 495#L495true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 879#L496true activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 795#L1245true assume !(0 != activate_threads_~tmp~1#1); 1206#L1245-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 554#L503true assume 1 == ~t1_pc~0; 566#L504true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 734#L514true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 694#L515true activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 384#L1253true assume !(0 != activate_threads_~tmp___0~0#1); 40#L1253-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 900#L522true assume !(1 == ~t2_pc~0); 522#L522-2true is_transmit2_triggered_~__retres1~2#1 := 0; 141#L533true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 424#L534true activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 880#L1261true assume !(0 != activate_threads_~tmp___1~0#1); 1197#L1261-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1040#L541true assume 1 == ~t3_pc~0; 483#L542true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 825#L552true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 238#L553true activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 591#L1269true assume !(0 != activate_threads_~tmp___2~0#1); 525#L1269-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 964#L560true assume !(1 == ~t4_pc~0); 1067#L560-2true is_transmit4_triggered_~__retres1~4#1 := 0; 463#L571true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 447#L572true activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 24#L1277true assume !(0 != activate_threads_~tmp___3~0#1); 888#L1277-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 166#L579true assume 1 == ~t5_pc~0; 3#L580true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 55#L590true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 453#L591true activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1015#L1285true assume !(0 != activate_threads_~tmp___4~0#1); 1090#L1285-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1263#L598true assume 1 == ~t6_pc~0; 220#L599true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 409#L609true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1185#L610true activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 833#L1293true assume !(0 != activate_threads_~tmp___5~0#1); 598#L1293-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 548#L617true assume !(1 == ~t7_pc~0); 459#L617-2true is_transmit7_triggered_~__retres1~7#1 := 0; 1180#L628true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 372#L629true activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 902#L1301true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 327#L1301-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 595#L636true assume 1 == ~t8_pc~0; 445#L637true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 782#L647true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 309#L648true activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 605#L1309true assume !(0 != activate_threads_~tmp___7~0#1); 415#L1309-2true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 684#L655true assume !(1 == ~t9_pc~0); 761#L655-2true is_transmit9_triggered_~__retres1~9#1 := 0; 1121#L666true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 196#L667true activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1019#L1317true assume !(0 != activate_threads_~tmp___8~0#1); 618#L1317-2true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 961#L674true assume 1 == ~t10_pc~0; 78#L675true assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 1046#L685true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1203#L686true activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1284#L1325true assume !(0 != activate_threads_~tmp___9~0#1); 408#L1325-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 890#L1119true assume !(1 == ~M_E~0); 123#L1119-2true assume !(1 == ~T1_E~0); 354#L1124-1true assume !(1 == ~T2_E~0); 36#L1129-1true assume !(1 == ~T3_E~0); 533#L1134-1true assume !(1 == ~T4_E~0); 197#L1139-1true assume !(1 == ~T5_E~0); 325#L1144-1true assume 1 == ~T6_E~0;~T6_E~0 := 2; 1244#L1149-1true assume !(1 == ~T7_E~0); 120#L1154-1true assume !(1 == ~T8_E~0); 169#L1159-1true assume !(1 == ~T9_E~0); 1213#L1164-1true assume !(1 == ~T10_E~0); 426#L1169-1true assume !(1 == ~E_1~0); 347#L1174-1true assume !(1 == ~E_2~0); 227#L1179-1true assume !(1 == ~E_3~0); 162#L1184-1true assume 1 == ~E_4~0;~E_4~0 := 2; 193#L1189-1true assume !(1 == ~E_5~0); 260#L1194-1true assume !(1 == ~E_6~0); 1257#L1199-1true assume !(1 == ~E_7~0); 233#L1204-1true assume !(1 == ~E_8~0); 1119#L1209-1true assume !(1 == ~E_9~0); 615#L1214-1true assume !(1 == ~E_10~0); 1211#L1219-1true assume { :end_inline_reset_delta_events } true; 18#L1520-2true [2021-12-16 10:06:00,174 INFO L793 eck$LassoCheckResult]: Loop: 18#L1520-2true assume !false; 1267#L1521true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 164#L981true assume !true; 322#L996true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1260#L694-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 321#L1006-3true assume 0 == ~M_E~0;~M_E~0 := 1; 959#L1006-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 731#L1011-3true assume !(0 == ~T2_E~0); 968#L1016-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 777#L1021-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 464#L1026-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 1139#L1031-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 698#L1036-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 1207#L1041-3true assume 0 == ~T8_E~0;~T8_E~0 := 1; 769#L1046-3true assume 0 == ~T9_E~0;~T9_E~0 := 1; 1085#L1051-3true assume !(0 == ~T10_E~0); 699#L1056-3true assume 0 == ~E_1~0;~E_1~0 := 1; 175#L1061-3true assume 0 == ~E_2~0;~E_2~0 := 1; 177#L1066-3true assume 0 == ~E_3~0;~E_3~0 := 1; 1227#L1071-3true assume 0 == ~E_4~0;~E_4~0 := 1; 992#L1076-3true assume 0 == ~E_5~0;~E_5~0 := 1; 67#L1081-3true assume 0 == ~E_6~0;~E_6~0 := 1; 1140#L1086-3true assume 0 == ~E_7~0;~E_7~0 := 1; 91#L1091-3true assume !(0 == ~E_8~0); 1052#L1096-3true assume 0 == ~E_9~0;~E_9~0 := 1; 928#L1101-3true assume 0 == ~E_10~0;~E_10~0 := 1; 985#L1106-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 480#L484-33true assume 1 == ~m_pc~0; 1177#L485-11true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 418#L495-11true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 943#L496-11true activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 21#L1245-33true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 632#L1245-35true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 265#L503-33true assume !(1 == ~t1_pc~0); 895#L503-35true is_transmit1_triggered_~__retres1~1#1 := 0; 600#L514-11true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 530#L515-11true activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 216#L1253-33true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 645#L1253-35true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 506#L522-33true assume 1 == ~t2_pc~0; 631#L523-11true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 85#L533-11true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 608#L534-11true activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 804#L1261-33true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 521#L1261-35true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 875#L541-33true assume !(1 == ~t3_pc~0); 288#L541-35true is_transmit3_triggered_~__retres1~3#1 := 0; 20#L552-11true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 973#L553-11true activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 500#L1269-33true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 932#L1269-35true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 693#L560-33true assume !(1 == ~t4_pc~0); 988#L560-35true is_transmit4_triggered_~__retres1~4#1 := 0; 57#L571-11true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 189#L572-11true activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1074#L1277-33true assume !(0 != activate_threads_~tmp___3~0#1); 672#L1277-35true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16#L579-33true assume 1 == ~t5_pc~0; 460#L580-11true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1033#L590-11true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1047#L591-11true activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 549#L1285-33true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 569#L1285-35true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1035#L598-33true assume 1 == ~t6_pc~0; 1249#L599-11true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 278#L609-11true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 753#L610-11true activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 192#L1293-33true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 901#L1293-35true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1155#L617-33true assume 1 == ~t7_pc~0; 918#L618-11true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 776#L628-11true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1002#L629-11true activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1123#L1301-33true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 994#L1301-35true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 50#L636-33true assume !(1 == ~t8_pc~0); 1010#L636-35true is_transmit8_triggered_~__retres1~8#1 := 0; 664#L647-11true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1165#L648-11true activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1055#L1309-33true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 652#L1309-35true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1255#L655-33true assume 1 == ~t9_pc~0; 1171#L656-11true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 247#L666-11true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 487#L667-11true activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 750#L1317-33true assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1000#L1317-35true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 346#L674-33true assume !(1 == ~t10_pc~0); 1029#L674-35true is_transmit10_triggered_~__retres1~10#1 := 0; 1066#L685-11true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 202#L686-11true activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 512#L1325-33true assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1060#L1325-35true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1093#L1119-3true assume 1 == ~M_E~0;~M_E~0 := 2; 1101#L1119-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 1261#L1124-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 1150#L1129-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 214#L1134-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 497#L1139-3true assume !(1 == ~T5_E~0); 342#L1144-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 450#L1149-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 1248#L1154-3true assume 1 == ~T8_E~0;~T8_E~0 := 2; 708#L1159-3true assume 1 == ~T9_E~0;~T9_E~0 := 2; 1230#L1164-3true assume 1 == ~T10_E~0;~T10_E~0 := 2; 1005#L1169-3true assume 1 == ~E_1~0;~E_1~0 := 2; 277#L1174-3true assume 1 == ~E_2~0;~E_2~0 := 2; 1083#L1179-3true assume !(1 == ~E_3~0); 835#L1184-3true assume 1 == ~E_4~0;~E_4~0 := 2; 80#L1189-3true assume 1 == ~E_5~0;~E_5~0 := 2; 840#L1194-3true assume 1 == ~E_6~0;~E_6~0 := 2; 244#L1199-3true assume 1 == ~E_7~0;~E_7~0 := 2; 1266#L1204-3true assume 1 == ~E_8~0;~E_8~0 := 2; 438#L1209-3true assume 1 == ~E_9~0;~E_9~0 := 2; 27#L1214-3true assume 1 == ~E_10~0;~E_10~0 := 2; 937#L1219-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 607#L764-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 945#L821-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 254#L822-1true start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 306#L1539true assume !(0 == start_simulation_~tmp~3#1); 501#L1539-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 428#L764-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 863#L821-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 386#L822-2true stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 250#L1494true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 739#L1501true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 903#L1502true start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 307#L1552true assume !(0 != start_simulation_~tmp___0~1#1); 18#L1520-2true [2021-12-16 10:06:00,184 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:00,184 INFO L85 PathProgramCache]: Analyzing trace with hash 1310232617, now seen corresponding path program 1 times [2021-12-16 10:06:00,195 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:00,196 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [229050573] [2021-12-16 10:06:00,196 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:00,197 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:00,315 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:06:00,408 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:06:00,409 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:06:00,409 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [229050573] [2021-12-16 10:06:00,410 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [229050573] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:06:00,410 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:06:00,410 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:06:00,412 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [577786918] [2021-12-16 10:06:00,413 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:06:00,416 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:06:00,416 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:00,417 INFO L85 PathProgramCache]: Analyzing trace with hash 1452797615, now seen corresponding path program 1 times [2021-12-16 10:06:00,417 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:00,417 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2046485257] [2021-12-16 10:06:00,417 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:00,418 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:00,469 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:06:00,504 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:06:00,504 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:06:00,504 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2046485257] [2021-12-16 10:06:00,504 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2046485257] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:06:00,505 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:06:00,505 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-16 10:06:00,505 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1506458524] [2021-12-16 10:06:00,505 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:06:00,506 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:06:00,507 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:06:00,555 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-16 10:06:00,556 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-16 10:06:00,561 INFO L87 Difference]: Start difference. First operand has 1285 states, 1284 states have (on average 1.5093457943925233) internal successors, (1938), 1284 states have internal predecessors, (1938), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 42.0) internal successors, (126), 3 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:00,646 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:06:00,646 INFO L93 Difference]: Finished difference Result 1284 states and 1907 transitions. [2021-12-16 10:06:00,651 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-16 10:06:00,655 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1284 states and 1907 transitions. [2021-12-16 10:06:00,666 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1141 [2021-12-16 10:06:00,678 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1284 states to 1278 states and 1901 transitions. [2021-12-16 10:06:00,681 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1278 [2021-12-16 10:06:00,683 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1278 [2021-12-16 10:06:00,683 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1278 states and 1901 transitions. [2021-12-16 10:06:00,690 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:06:00,690 INFO L681 BuchiCegarLoop]: Abstraction has 1278 states and 1901 transitions. [2021-12-16 10:06:00,706 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1278 states and 1901 transitions. [2021-12-16 10:06:00,757 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1278 to 1278. [2021-12-16 10:06:00,763 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1278 states, 1278 states have (on average 1.4874804381846636) internal successors, (1901), 1277 states have internal predecessors, (1901), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:00,767 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1278 states to 1278 states and 1901 transitions. [2021-12-16 10:06:00,768 INFO L704 BuchiCegarLoop]: Abstraction has 1278 states and 1901 transitions. [2021-12-16 10:06:00,768 INFO L587 BuchiCegarLoop]: Abstraction has 1278 states and 1901 transitions. [2021-12-16 10:06:00,768 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2021-12-16 10:06:00,768 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1278 states and 1901 transitions. [2021-12-16 10:06:00,774 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1141 [2021-12-16 10:06:00,774 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:06:00,774 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:06:00,777 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:00,777 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:00,778 INFO L791 eck$LassoCheckResult]: Stem: 3560#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 3561#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 3835#L1483 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3823#L694 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3824#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 3844#L701-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3845#L706-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 3128#L711-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2846#L716-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2847#L721-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3753#L726-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 3754#L731-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 3739#L736-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 3740#L741-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 3775#L746-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 2900#L751-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2901#L1006 assume !(0 == ~M_E~0); 2749#L1006-2 assume !(0 == ~T1_E~0); 2750#L1011-1 assume !(0 == ~T2_E~0); 3797#L1016-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3812#L1021-1 assume !(0 == ~T4_E~0); 2631#L1026-1 assume !(0 == ~T5_E~0); 2632#L1031-1 assume !(0 == ~T6_E~0); 3505#L1036-1 assume !(0 == ~T7_E~0); 3501#L1041-1 assume !(0 == ~T8_E~0); 3502#L1046-1 assume !(0 == ~T9_E~0); 2931#L1051-1 assume !(0 == ~T10_E~0); 2932#L1056-1 assume 0 == ~E_1~0;~E_1~0 := 1; 3634#L1061-1 assume !(0 == ~E_2~0); 2850#L1066-1 assume !(0 == ~E_3~0); 2851#L1071-1 assume !(0 == ~E_4~0); 3613#L1076-1 assume !(0 == ~E_5~0); 2760#L1081-1 assume !(0 == ~E_6~0); 2761#L1086-1 assume !(0 == ~E_7~0); 3103#L1091-1 assume !(0 == ~E_8~0); 3790#L1096-1 assume 0 == ~E_9~0;~E_9~0 := 1; 3791#L1101-1 assume !(0 == ~E_10~0); 3165#L1106-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3166#L484 assume !(1 == ~m_pc~0); 2809#L484-2 is_master_triggered_~__retres1~0#1 := 0; 2808#L495 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3424#L496 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3708#L1245 assume !(0 != activate_threads_~tmp~1#1); 3709#L1245-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3493#L503 assume 1 == ~t1_pc~0; 3494#L504 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3511#L514 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3626#L515 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3279#L1253 assume !(0 != activate_threads_~tmp___0~0#1); 2659#L1253-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2660#L522 assume !(1 == ~t2_pc~0); 3460#L522-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2863#L533 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2864#L534 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3334#L1261 assume !(0 != activate_threads_~tmp___1~0#1); 3755#L1261-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3820#L541 assume 1 == ~t3_pc~0; 3409#L542 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3225#L552 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3040#L553 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3041#L1269 assume !(0 != activate_threads_~tmp___2~0#1); 3463#L1269-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3464#L560 assume !(1 == ~t4_pc~0); 2743#L560-2 is_transmit4_triggered_~__retres1~4#1 := 0; 2742#L571 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3368#L572 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2627#L1277 assume !(0 != activate_threads_~tmp___3~0#1); 2628#L1277-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2914#L579 assume 1 == ~t5_pc~0; 2578#L580 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2579#L590 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2687#L591 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3371#L1285 assume !(0 != activate_threads_~tmp___4~0#1); 3811#L1285-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3832#L598 assume 1 == ~t6_pc~0; 3008#L599 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 3009#L609 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3311#L610 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3731#L1293 assume !(0 != activate_threads_~tmp___5~0#1); 3542#L1293-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3484#L617 assume !(1 == ~t7_pc~0); 2981#L617-2 is_transmit7_triggered_~__retres1~7#1 := 0; 2980#L628 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3266#L629 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3267#L1301 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 3202#L1301-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3203#L636 assume 1 == ~t8_pc~0; 3365#L637 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 3366#L647 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3167#L648 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3168#L1309 assume !(0 != activate_threads_~tmp___7~0#1); 3318#L1309-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3319#L655 assume !(1 == ~t9_pc~0); 3348#L655-2 is_transmit9_triggered_~__retres1~9#1 := 0; 3349#L666 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2960#L667 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 2961#L1317 assume !(0 != activate_threads_~tmp___8~0#1); 3562#L1317-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 3563#L674 assume 1 == ~t10_pc~0; 2736#L675 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 2737#L685 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 3822#L686 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3853#L1325 assume !(0 != activate_threads_~tmp___9~0#1); 3308#L1325-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3309#L1119 assume !(1 == ~M_E~0); 2832#L1119-2 assume !(1 == ~T1_E~0); 2833#L1124-1 assume !(1 == ~T2_E~0); 2651#L1129-1 assume !(1 == ~T3_E~0); 2652#L1134-1 assume !(1 == ~T4_E~0); 2965#L1139-1 assume !(1 == ~T5_E~0); 2966#L1144-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 3198#L1149-1 assume !(1 == ~T7_E~0); 2827#L1154-1 assume !(1 == ~T8_E~0); 2828#L1159-1 assume !(1 == ~T9_E~0); 2915#L1164-1 assume !(1 == ~T10_E~0); 3337#L1169-1 assume !(1 == ~E_1~0); 3235#L1174-1 assume !(1 == ~E_2~0); 3022#L1179-1 assume !(1 == ~E_3~0); 2904#L1184-1 assume 1 == ~E_4~0;~E_4~0 := 2; 2905#L1189-1 assume !(1 == ~E_5~0); 2958#L1194-1 assume !(1 == ~E_6~0); 3081#L1199-1 assume !(1 == ~E_7~0); 3032#L1204-1 assume !(1 == ~E_8~0); 3033#L1209-1 assume !(1 == ~E_9~0); 3556#L1214-1 assume !(1 == ~E_10~0); 3557#L1219-1 assume { :end_inline_reset_delta_events } true; 2615#L1520-2 [2021-12-16 10:06:00,778 INFO L793 eck$LassoCheckResult]: Loop: 2615#L1520-2 assume !false; 2616#L1521 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2719#L981 assume !false; 2911#L832 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 3583#L764 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 2601#L821 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 3701#L822 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 3751#L836 assume !(0 != eval_~tmp~0#1); 3193#L996 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3194#L694-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3189#L1006-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3190#L1006-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3660#L1011-3 assume !(0 == ~T2_E~0); 3661#L1016-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3700#L1021-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3383#L1026-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3384#L1031-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3628#L1036-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 3629#L1041-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 3691#L1046-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 3692#L1051-3 assume !(0 == ~T10_E~0); 3630#L1056-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2928#L1061-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2929#L1066-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2930#L1071-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3801#L1076-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2713#L1081-3 assume 0 == ~E_6~0;~E_6~0 := 1; 2714#L1086-3 assume 0 == ~E_7~0;~E_7~0 := 1; 2768#L1091-3 assume !(0 == ~E_8~0); 2769#L1096-3 assume 0 == ~E_9~0;~E_9~0 := 1; 3776#L1101-3 assume 0 == ~E_10~0;~E_10~0 := 1; 3777#L1106-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3403#L484-33 assume 1 == ~m_pc~0; 3404#L485-11 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 3323#L495-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3324#L496-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2621#L1245-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2622#L1245-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3093#L503-33 assume !(1 == ~t1_pc~0); 3094#L503-35 is_transmit1_triggered_~__retres1~1#1 := 0; 3544#L514-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3473#L515-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3000#L1253-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3001#L1253-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3440#L522-33 assume 1 == ~t2_pc~0; 3441#L523-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2756#L533-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2757#L534-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3550#L1261-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3458#L1261-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3459#L541-33 assume 1 == ~t3_pc~0; 2780#L542-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2619#L552-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2620#L553-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3430#L1269-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3431#L1269-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3625#L560-33 assume 1 == ~t4_pc~0; 3330#L561-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2691#L571-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2692#L572-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2948#L1277-33 assume !(0 != activate_threads_~tmp___3~0#1); 3607#L1277-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2607#L579-33 assume 1 == ~t5_pc~0; 2608#L580-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2856#L590-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3816#L591-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3485#L1285-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 3486#L1285-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3510#L598-33 assume !(1 == ~t6_pc~0); 3283#L598-35 is_transmit6_triggered_~__retres1~6#1 := 0; 3114#L609-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3115#L610-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2955#L1293-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 2956#L1293-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3765#L617-33 assume 1 == ~t7_pc~0; 3771#L618-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 2748#L628-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3699#L629-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3806#L1301-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 3802#L1301-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2679#L636-33 assume !(1 == ~t8_pc~0); 2680#L636-35 is_transmit8_triggered_~__retres1~8#1 := 0; 3599#L647-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3600#L648-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3825#L1309-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 3588#L1309-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3589#L655-33 assume 1 == ~t9_pc~0; 3849#L656-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 3055#L666-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3056#L667-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3414#L1317-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 3678#L1317-35 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 3234#L674-33 assume 1 == ~t10_pc~0; 3109#L675-11 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 3110#L685-11 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 2971#L686-11 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 2972#L1325-33 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 3449#L1325-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3826#L1119-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3833#L1119-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3836#L1124-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3847#L1129-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2993#L1134-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2994#L1139-3 assume !(1 == ~T5_E~0); 3227#L1144-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 3228#L1149-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 3370#L1154-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 3640#L1159-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 3641#L1164-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 3807#L1169-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3112#L1174-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3113#L1179-3 assume !(1 == ~E_3~0); 3732#L1184-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2739#L1189-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2740#L1194-3 assume 1 == ~E_6~0;~E_6~0 := 2; 3053#L1199-3 assume 1 == ~E_7~0;~E_7~0 := 2; 3054#L1204-3 assume 1 == ~E_8~0;~E_8~0 := 2; 3357#L1209-3 assume 1 == ~E_9~0;~E_9~0 := 2; 2633#L1214-3 assume 1 == ~E_10~0;~E_10~0 := 2; 2634#L1219-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 3547#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 2716#L821-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 3070#L822-1 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 3071#L1539 assume !(0 == start_simulation_~tmp~3#1); 3163#L1539-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 3339#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 3146#L821-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 3278#L822-2 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 3062#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3063#L1501 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3667#L1502 start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 3164#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 2615#L1520-2 [2021-12-16 10:06:00,779 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:00,779 INFO L85 PathProgramCache]: Analyzing trace with hash -934325781, now seen corresponding path program 1 times [2021-12-16 10:06:00,779 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:00,779 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2132832996] [2021-12-16 10:06:00,780 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:00,780 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:00,800 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:06:00,856 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:06:00,856 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:06:00,856 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2132832996] [2021-12-16 10:06:00,857 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2132832996] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:06:00,857 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:06:00,857 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:06:00,857 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1134713943] [2021-12-16 10:06:00,857 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:06:00,858 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:06:00,858 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:00,859 INFO L85 PathProgramCache]: Analyzing trace with hash -1410939798, now seen corresponding path program 1 times [2021-12-16 10:06:00,859 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:00,859 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [234962889] [2021-12-16 10:06:00,859 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:00,859 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:00,902 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:06:01,008 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:06:01,008 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:06:01,009 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [234962889] [2021-12-16 10:06:01,009 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [234962889] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:06:01,009 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:06:01,009 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:06:01,009 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1171766130] [2021-12-16 10:06:01,009 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:06:01,010 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:06:01,010 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:06:01,011 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-16 10:06:01,011 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-16 10:06:01,011 INFO L87 Difference]: Start difference. First operand 1278 states and 1901 transitions. cyclomatic complexity: 624 Second operand has 3 states, 3 states have (on average 42.0) internal successors, (126), 3 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:01,039 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:06:01,040 INFO L93 Difference]: Finished difference Result 1278 states and 1900 transitions. [2021-12-16 10:06:01,040 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-16 10:06:01,041 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1278 states and 1900 transitions. [2021-12-16 10:06:01,050 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1141 [2021-12-16 10:06:01,056 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1278 states to 1278 states and 1900 transitions. [2021-12-16 10:06:01,057 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1278 [2021-12-16 10:06:01,078 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1278 [2021-12-16 10:06:01,078 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1278 states and 1900 transitions. [2021-12-16 10:06:01,081 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:06:01,082 INFO L681 BuchiCegarLoop]: Abstraction has 1278 states and 1900 transitions. [2021-12-16 10:06:01,083 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1278 states and 1900 transitions. [2021-12-16 10:06:01,096 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1278 to 1278. [2021-12-16 10:06:01,098 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1278 states, 1278 states have (on average 1.486697965571205) internal successors, (1900), 1277 states have internal predecessors, (1900), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:01,102 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1278 states to 1278 states and 1900 transitions. [2021-12-16 10:06:01,102 INFO L704 BuchiCegarLoop]: Abstraction has 1278 states and 1900 transitions. [2021-12-16 10:06:01,103 INFO L587 BuchiCegarLoop]: Abstraction has 1278 states and 1900 transitions. [2021-12-16 10:06:01,103 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2021-12-16 10:06:01,103 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1278 states and 1900 transitions. [2021-12-16 10:06:01,109 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1141 [2021-12-16 10:06:01,109 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:06:01,109 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:06:01,113 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:01,113 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:01,115 INFO L791 eck$LassoCheckResult]: Stem: 6123#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 6124#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 6398#L1483 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6386#L694 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6387#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 6407#L701-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6408#L706-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5691#L711-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 5411#L716-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 5412#L721-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 6316#L726-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 6317#L731-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 6302#L736-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 6303#L741-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 6338#L746-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 5463#L751-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5464#L1006 assume !(0 == ~M_E~0); 5315#L1006-2 assume !(0 == ~T1_E~0); 5316#L1011-1 assume !(0 == ~T2_E~0); 6360#L1016-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 6375#L1021-1 assume !(0 == ~T4_E~0); 5194#L1026-1 assume !(0 == ~T5_E~0); 5195#L1031-1 assume !(0 == ~T6_E~0); 6070#L1036-1 assume !(0 == ~T7_E~0); 6064#L1041-1 assume !(0 == ~T8_E~0); 6065#L1046-1 assume !(0 == ~T9_E~0); 5494#L1051-1 assume !(0 == ~T10_E~0); 5495#L1056-1 assume 0 == ~E_1~0;~E_1~0 := 1; 6197#L1061-1 assume !(0 == ~E_2~0); 5413#L1066-1 assume !(0 == ~E_3~0); 5414#L1071-1 assume !(0 == ~E_4~0); 6176#L1076-1 assume !(0 == ~E_5~0); 5323#L1081-1 assume !(0 == ~E_6~0); 5324#L1086-1 assume !(0 == ~E_7~0); 5667#L1091-1 assume !(0 == ~E_8~0); 6353#L1096-1 assume 0 == ~E_9~0;~E_9~0 := 1; 6354#L1101-1 assume !(0 == ~E_10~0); 5728#L1106-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5729#L484 assume !(1 == ~m_pc~0); 5372#L484-2 is_master_triggered_~__retres1~0#1 := 0; 5371#L495 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5987#L496 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6271#L1245 assume !(0 != activate_threads_~tmp~1#1); 6272#L1245-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6056#L503 assume 1 == ~t1_pc~0; 6057#L504 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 6075#L514 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6189#L515 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5842#L1253 assume !(0 != activate_threads_~tmp___0~0#1); 5224#L1253-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5225#L522 assume !(1 == ~t2_pc~0); 6023#L522-2 is_transmit2_triggered_~__retres1~2#1 := 0; 5427#L533 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5428#L534 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5897#L1261 assume !(0 != activate_threads_~tmp___1~0#1); 6318#L1261-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6383#L541 assume 1 == ~t3_pc~0; 5974#L542 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5788#L552 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5603#L553 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5604#L1269 assume !(0 != activate_threads_~tmp___2~0#1); 6030#L1269-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6031#L560 assume !(1 == ~t4_pc~0); 5306#L560-2 is_transmit4_triggered_~__retres1~4#1 := 0; 5305#L571 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5931#L572 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5190#L1277 assume !(0 != activate_threads_~tmp___3~0#1); 5191#L1277-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5477#L579 assume 1 == ~t5_pc~0; 5141#L580 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5142#L590 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5250#L591 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 5934#L1285 assume !(0 != activate_threads_~tmp___4~0#1); 6374#L1285-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6395#L598 assume 1 == ~t6_pc~0; 5573#L599 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 5574#L609 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5876#L610 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 6294#L1293 assume !(0 != activate_threads_~tmp___5~0#1); 6105#L1293-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6047#L617 assume !(1 == ~t7_pc~0); 5544#L617-2 is_transmit7_triggered_~__retres1~7#1 := 0; 5543#L628 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5829#L629 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 5830#L1301 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 5766#L1301-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 5767#L636 assume 1 == ~t8_pc~0; 5928#L637 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 5929#L647 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 5730#L648 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 5731#L1309 assume !(0 != activate_threads_~tmp___7~0#1); 5883#L1309-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 5884#L655 assume !(1 == ~t9_pc~0); 5913#L655-2 is_transmit9_triggered_~__retres1~9#1 := 0; 5914#L666 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 5523#L667 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 5524#L1317 assume !(0 != activate_threads_~tmp___8~0#1); 6125#L1317-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 6126#L674 assume 1 == ~t10_pc~0; 5299#L675 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 5300#L685 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 6385#L686 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 6416#L1325 assume !(0 != activate_threads_~tmp___9~0#1); 5871#L1325-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5872#L1119 assume !(1 == ~M_E~0); 5395#L1119-2 assume !(1 == ~T1_E~0); 5396#L1124-1 assume !(1 == ~T2_E~0); 5214#L1129-1 assume !(1 == ~T3_E~0); 5215#L1134-1 assume !(1 == ~T4_E~0); 5528#L1139-1 assume !(1 == ~T5_E~0); 5529#L1144-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 5761#L1149-1 assume !(1 == ~T7_E~0); 5390#L1154-1 assume !(1 == ~T8_E~0); 5391#L1159-1 assume !(1 == ~T9_E~0); 5478#L1164-1 assume !(1 == ~T10_E~0); 5900#L1169-1 assume !(1 == ~E_1~0); 5798#L1174-1 assume !(1 == ~E_2~0); 5587#L1179-1 assume !(1 == ~E_3~0); 5467#L1184-1 assume 1 == ~E_4~0;~E_4~0 := 2; 5468#L1189-1 assume !(1 == ~E_5~0); 5522#L1194-1 assume !(1 == ~E_6~0); 5644#L1199-1 assume !(1 == ~E_7~0); 5595#L1204-1 assume !(1 == ~E_8~0); 5596#L1209-1 assume !(1 == ~E_9~0); 6119#L1214-1 assume !(1 == ~E_10~0); 6120#L1219-1 assume { :end_inline_reset_delta_events } true; 5178#L1520-2 [2021-12-16 10:06:01,116 INFO L793 eck$LassoCheckResult]: Loop: 5178#L1520-2 assume !false; 5179#L1521 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5279#L981 assume !false; 5474#L832 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 6146#L764 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 5164#L821 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 6264#L822 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 6314#L836 assume !(0 != eval_~tmp~0#1); 5759#L996 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5760#L694-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5752#L1006-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5753#L1006-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 6223#L1011-3 assume !(0 == ~T2_E~0); 6224#L1016-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 6263#L1021-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5946#L1026-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5947#L1031-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 6191#L1036-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 6192#L1041-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 6252#L1046-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 6253#L1051-3 assume !(0 == ~T10_E~0); 6193#L1056-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5489#L1061-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5490#L1066-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5493#L1071-3 assume 0 == ~E_4~0;~E_4~0 := 1; 6364#L1076-3 assume 0 == ~E_5~0;~E_5~0 := 1; 5276#L1081-3 assume 0 == ~E_6~0;~E_6~0 := 1; 5277#L1086-3 assume 0 == ~E_7~0;~E_7~0 := 1; 5329#L1091-3 assume !(0 == ~E_8~0); 5330#L1096-3 assume 0 == ~E_9~0;~E_9~0 := 1; 6339#L1101-3 assume 0 == ~E_10~0;~E_10~0 := 1; 6340#L1106-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5966#L484-33 assume !(1 == ~m_pc~0); 5968#L484-35 is_master_triggered_~__retres1~0#1 := 0; 5886#L495-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5887#L496-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5184#L1245-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 5185#L1245-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5653#L503-33 assume !(1 == ~t1_pc~0); 5654#L503-35 is_transmit1_triggered_~__retres1~1#1 := 0; 6107#L514-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6033#L515-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5561#L1253-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5562#L1253-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6003#L522-33 assume 1 == ~t2_pc~0; 6004#L523-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5317#L533-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5318#L534-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6112#L1261-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 6021#L1261-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6022#L541-33 assume !(1 == ~t3_pc~0); 5344#L541-35 is_transmit3_triggered_~__retres1~3#1 := 0; 5182#L552-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5183#L553-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5993#L1269-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5994#L1269-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6188#L560-33 assume 1 == ~t4_pc~0; 5893#L561-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5254#L571-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5255#L572-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5513#L1277-33 assume !(0 != activate_threads_~tmp___3~0#1); 6170#L1277-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5173#L579-33 assume 1 == ~t5_pc~0; 5174#L580-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5420#L590-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6379#L591-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 6048#L1285-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 6049#L1285-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6074#L598-33 assume !(1 == ~t6_pc~0); 5851#L598-35 is_transmit6_triggered_~__retres1~6#1 := 0; 5677#L609-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5678#L610-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5518#L1293-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 5519#L1293-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6328#L617-33 assume 1 == ~t7_pc~0; 6334#L618-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 5311#L628-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 6262#L629-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 6369#L1301-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 6365#L1301-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 5242#L636-33 assume !(1 == ~t8_pc~0); 5243#L636-35 is_transmit8_triggered_~__retres1~8#1 := 0; 6162#L647-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 6163#L648-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 6388#L1309-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 6153#L1309-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 6154#L655-33 assume 1 == ~t9_pc~0; 6412#L656-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 5618#L666-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 5619#L667-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 5977#L1317-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 6241#L1317-35 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 5797#L674-33 assume 1 == ~t10_pc~0; 5672#L675-11 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 5673#L685-11 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 5534#L686-11 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 5535#L1325-33 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 6012#L1325-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6389#L1119-3 assume 1 == ~M_E~0;~M_E~0 := 2; 6396#L1119-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 6399#L1124-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 6410#L1129-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5559#L1134-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5560#L1139-3 assume !(1 == ~T5_E~0); 5790#L1144-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 5791#L1149-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 5933#L1154-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 6203#L1159-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 6204#L1164-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 6370#L1169-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5675#L1174-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5676#L1179-3 assume !(1 == ~E_3~0); 6295#L1184-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5302#L1189-3 assume 1 == ~E_5~0;~E_5~0 := 2; 5303#L1194-3 assume 1 == ~E_6~0;~E_6~0 := 2; 5616#L1199-3 assume 1 == ~E_7~0;~E_7~0 := 2; 5617#L1204-3 assume 1 == ~E_8~0;~E_8~0 := 2; 5920#L1209-3 assume 1 == ~E_9~0;~E_9~0 := 2; 5196#L1214-3 assume 1 == ~E_10~0;~E_10~0 := 2; 5197#L1219-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 6111#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 5282#L821-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 5633#L822-1 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 5634#L1539 assume !(0 == start_simulation_~tmp~3#1); 5726#L1539-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 5902#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 5709#L821-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 5841#L822-2 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 5625#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5626#L1501 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6230#L1502 start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 5727#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 5178#L1520-2 [2021-12-16 10:06:01,119 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:01,120 INFO L85 PathProgramCache]: Analyzing trace with hash 158309421, now seen corresponding path program 1 times [2021-12-16 10:06:01,120 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:01,121 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [548389776] [2021-12-16 10:06:01,121 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:01,121 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:01,146 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:06:01,179 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:06:01,180 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:06:01,180 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [548389776] [2021-12-16 10:06:01,180 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [548389776] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:06:01,181 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:06:01,181 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:06:01,181 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [47379577] [2021-12-16 10:06:01,181 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:06:01,182 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:06:01,182 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:01,182 INFO L85 PathProgramCache]: Analyzing trace with hash -103858072, now seen corresponding path program 1 times [2021-12-16 10:06:01,183 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:01,183 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [99155861] [2021-12-16 10:06:01,183 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:01,183 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:01,201 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:06:01,235 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:06:01,236 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:06:01,236 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [99155861] [2021-12-16 10:06:01,236 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [99155861] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:06:01,237 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:06:01,237 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:06:01,237 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2077773714] [2021-12-16 10:06:01,237 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:06:01,238 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:06:01,238 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:06:01,238 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-16 10:06:01,238 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-16 10:06:01,239 INFO L87 Difference]: Start difference. First operand 1278 states and 1900 transitions. cyclomatic complexity: 623 Second operand has 3 states, 3 states have (on average 42.0) internal successors, (126), 3 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:01,262 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:06:01,262 INFO L93 Difference]: Finished difference Result 1278 states and 1899 transitions. [2021-12-16 10:06:01,263 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-16 10:06:01,265 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1278 states and 1899 transitions. [2021-12-16 10:06:01,272 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1141 [2021-12-16 10:06:01,278 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1278 states to 1278 states and 1899 transitions. [2021-12-16 10:06:01,278 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1278 [2021-12-16 10:06:01,279 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1278 [2021-12-16 10:06:01,279 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1278 states and 1899 transitions. [2021-12-16 10:06:01,281 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:06:01,281 INFO L681 BuchiCegarLoop]: Abstraction has 1278 states and 1899 transitions. [2021-12-16 10:06:01,282 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1278 states and 1899 transitions. [2021-12-16 10:06:01,294 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1278 to 1278. [2021-12-16 10:06:01,296 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1278 states, 1278 states have (on average 1.4859154929577465) internal successors, (1899), 1277 states have internal predecessors, (1899), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:01,300 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1278 states to 1278 states and 1899 transitions. [2021-12-16 10:06:01,300 INFO L704 BuchiCegarLoop]: Abstraction has 1278 states and 1899 transitions. [2021-12-16 10:06:01,300 INFO L587 BuchiCegarLoop]: Abstraction has 1278 states and 1899 transitions. [2021-12-16 10:06:01,300 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2021-12-16 10:06:01,300 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1278 states and 1899 transitions. [2021-12-16 10:06:01,306 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1141 [2021-12-16 10:06:01,306 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:06:01,306 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:06:01,313 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:01,313 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:01,313 INFO L791 eck$LassoCheckResult]: Stem: 8685#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 8686#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 8961#L1483 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8949#L694 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 8950#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 8970#L701-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8971#L706-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8254#L711-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7972#L716-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 7973#L721-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 8879#L726-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 8880#L731-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 8865#L736-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 8866#L741-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 8901#L746-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 8024#L751-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8025#L1006 assume !(0 == ~M_E~0); 7875#L1006-2 assume !(0 == ~T1_E~0); 7876#L1011-1 assume !(0 == ~T2_E~0); 8923#L1016-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8938#L1021-1 assume !(0 == ~T4_E~0); 7755#L1026-1 assume !(0 == ~T5_E~0); 7756#L1031-1 assume !(0 == ~T6_E~0); 8631#L1036-1 assume !(0 == ~T7_E~0); 8627#L1041-1 assume !(0 == ~T8_E~0); 8628#L1046-1 assume !(0 == ~T9_E~0); 8057#L1051-1 assume !(0 == ~T10_E~0); 8058#L1056-1 assume 0 == ~E_1~0;~E_1~0 := 1; 8760#L1061-1 assume !(0 == ~E_2~0); 7976#L1066-1 assume !(0 == ~E_3~0); 7977#L1071-1 assume !(0 == ~E_4~0); 8739#L1076-1 assume !(0 == ~E_5~0); 7886#L1081-1 assume !(0 == ~E_6~0); 7887#L1086-1 assume !(0 == ~E_7~0); 8229#L1091-1 assume !(0 == ~E_8~0); 8915#L1096-1 assume 0 == ~E_9~0;~E_9~0 := 1; 8916#L1101-1 assume !(0 == ~E_10~0); 8291#L1106-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8292#L484 assume !(1 == ~m_pc~0); 7935#L484-2 is_master_triggered_~__retres1~0#1 := 0; 7934#L495 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8550#L496 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8834#L1245 assume !(0 != activate_threads_~tmp~1#1); 8835#L1245-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8619#L503 assume 1 == ~t1_pc~0; 8620#L504 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8636#L514 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8752#L515 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 8402#L1253 assume !(0 != activate_threads_~tmp___0~0#1); 7785#L1253-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7786#L522 assume !(1 == ~t2_pc~0); 8586#L522-2 is_transmit2_triggered_~__retres1~2#1 := 0; 7989#L533 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7990#L534 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8460#L1261 assume !(0 != activate_threads_~tmp___1~0#1); 8881#L1261-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8946#L541 assume 1 == ~t3_pc~0; 8535#L542 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 8351#L552 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8166#L553 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8167#L1269 assume !(0 != activate_threads_~tmp___2~0#1); 8589#L1269-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8590#L560 assume !(1 == ~t4_pc~0); 7867#L560-2 is_transmit4_triggered_~__retres1~4#1 := 0; 7866#L571 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8494#L572 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7753#L1277 assume !(0 != activate_threads_~tmp___3~0#1); 7754#L1277-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8038#L579 assume 1 == ~t5_pc~0; 7704#L580 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 7705#L590 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7813#L591 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8497#L1285 assume !(0 != activate_threads_~tmp___4~0#1); 8936#L1285-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8958#L598 assume 1 == ~t6_pc~0; 8134#L599 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 8135#L609 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8436#L610 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 8857#L1293 assume !(0 != activate_threads_~tmp___5~0#1); 8668#L1293-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8610#L617 assume !(1 == ~t7_pc~0); 8107#L617-2 is_transmit7_triggered_~__retres1~7#1 := 0; 8106#L628 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8392#L629 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 8393#L1301 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 8328#L1301-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 8329#L636 assume 1 == ~t8_pc~0; 8491#L637 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 8492#L647 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 8293#L648 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 8294#L1309 assume !(0 != activate_threads_~tmp___7~0#1); 8444#L1309-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 8445#L655 assume !(1 == ~t9_pc~0); 8472#L655-2 is_transmit9_triggered_~__retres1~9#1 := 0; 8473#L666 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 8086#L667 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 8087#L1317 assume !(0 != activate_threads_~tmp___8~0#1); 8687#L1317-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 8688#L674 assume 1 == ~t10_pc~0; 7862#L675 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 7863#L685 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 8948#L686 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 8979#L1325 assume !(0 != activate_threads_~tmp___9~0#1); 8434#L1325-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8435#L1119 assume !(1 == ~M_E~0); 7958#L1119-2 assume !(1 == ~T1_E~0); 7959#L1124-1 assume !(1 == ~T2_E~0); 7777#L1129-1 assume !(1 == ~T3_E~0); 7778#L1134-1 assume !(1 == ~T4_E~0); 8088#L1139-1 assume !(1 == ~T5_E~0); 8089#L1144-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 8324#L1149-1 assume !(1 == ~T7_E~0); 7953#L1154-1 assume !(1 == ~T8_E~0); 7954#L1159-1 assume !(1 == ~T9_E~0); 8041#L1164-1 assume !(1 == ~T10_E~0); 8463#L1169-1 assume !(1 == ~E_1~0); 8361#L1174-1 assume !(1 == ~E_2~0); 8148#L1179-1 assume !(1 == ~E_3~0); 8030#L1184-1 assume 1 == ~E_4~0;~E_4~0 := 2; 8031#L1189-1 assume !(1 == ~E_5~0); 8083#L1194-1 assume !(1 == ~E_6~0); 8207#L1199-1 assume !(1 == ~E_7~0); 8158#L1204-1 assume !(1 == ~E_8~0); 8159#L1209-1 assume !(1 == ~E_9~0); 8682#L1214-1 assume !(1 == ~E_10~0); 8683#L1219-1 assume { :end_inline_reset_delta_events } true; 7741#L1520-2 [2021-12-16 10:06:01,314 INFO L793 eck$LassoCheckResult]: Loop: 7741#L1520-2 assume !false; 7742#L1521 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7842#L981 assume !false; 8034#L832 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 8709#L764 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 7727#L821 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 8827#L822 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 8877#L836 assume !(0 != eval_~tmp~0#1); 8319#L996 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8320#L694-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8315#L1006-3 assume 0 == ~M_E~0;~M_E~0 := 1; 8316#L1006-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 8786#L1011-3 assume !(0 == ~T2_E~0); 8787#L1016-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8826#L1021-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 8507#L1026-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 8508#L1031-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 8754#L1036-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 8755#L1041-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 8815#L1046-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 8816#L1051-3 assume !(0 == ~T10_E~0); 8756#L1056-3 assume 0 == ~E_1~0;~E_1~0 := 1; 8052#L1061-3 assume 0 == ~E_2~0;~E_2~0 := 1; 8053#L1066-3 assume 0 == ~E_3~0;~E_3~0 := 1; 8056#L1071-3 assume 0 == ~E_4~0;~E_4~0 := 1; 8927#L1076-3 assume 0 == ~E_5~0;~E_5~0 := 1; 7839#L1081-3 assume 0 == ~E_6~0;~E_6~0 := 1; 7840#L1086-3 assume 0 == ~E_7~0;~E_7~0 := 1; 7892#L1091-3 assume !(0 == ~E_8~0); 7893#L1096-3 assume 0 == ~E_9~0;~E_9~0 := 1; 8902#L1101-3 assume 0 == ~E_10~0;~E_10~0 := 1; 8903#L1106-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8529#L484-33 assume 1 == ~m_pc~0; 8530#L485-11 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 8449#L495-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8450#L496-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 7747#L1245-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 7748#L1245-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8216#L503-33 assume !(1 == ~t1_pc~0); 8217#L503-35 is_transmit1_triggered_~__retres1~1#1 := 0; 8670#L514-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8597#L515-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 8126#L1253-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8127#L1253-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8566#L522-33 assume 1 == ~t2_pc~0; 8567#L523-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 7880#L533-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7881#L534-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8675#L1261-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 8584#L1261-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8585#L541-33 assume 1 == ~t3_pc~0; 7906#L542-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 7745#L552-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7746#L553-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8556#L1269-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 8557#L1269-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8751#L560-33 assume 1 == ~t4_pc~0; 8456#L561-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 7817#L571-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7818#L572-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8076#L1277-33 assume !(0 != activate_threads_~tmp___3~0#1); 8733#L1277-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7736#L579-33 assume 1 == ~t5_pc~0; 7737#L580-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 7983#L590-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8942#L591-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8611#L1285-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 8612#L1285-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8640#L598-33 assume 1 == ~t6_pc~0; 8944#L599-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 8240#L609-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8241#L610-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 8081#L1293-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 8082#L1293-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8891#L617-33 assume 1 == ~t7_pc~0; 8897#L618-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 7874#L628-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8825#L629-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 8932#L1301-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 8928#L1301-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 7805#L636-33 assume !(1 == ~t8_pc~0); 7806#L636-35 is_transmit8_triggered_~__retres1~8#1 := 0; 8725#L647-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 8726#L648-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 8951#L1309-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 8716#L1309-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 8717#L655-33 assume !(1 == ~t9_pc~0); 8976#L655-35 is_transmit9_triggered_~__retres1~9#1 := 0; 8183#L666-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 8184#L667-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 8540#L1317-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 8804#L1317-35 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 8360#L674-33 assume 1 == ~t10_pc~0; 8235#L675-11 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 8236#L685-11 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 8097#L686-11 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 8098#L1325-33 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 8575#L1325-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8952#L1119-3 assume 1 == ~M_E~0;~M_E~0 := 2; 8959#L1119-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8963#L1124-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 8973#L1129-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8122#L1134-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8123#L1139-3 assume !(1 == ~T5_E~0); 8353#L1144-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 8354#L1149-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 8496#L1154-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 8766#L1159-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 8767#L1164-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 8934#L1169-3 assume 1 == ~E_1~0;~E_1~0 := 2; 8238#L1174-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8239#L1179-3 assume !(1 == ~E_3~0); 8858#L1184-3 assume 1 == ~E_4~0;~E_4~0 := 2; 7868#L1189-3 assume 1 == ~E_5~0;~E_5~0 := 2; 7869#L1194-3 assume 1 == ~E_6~0;~E_6~0 := 2; 8179#L1199-3 assume 1 == ~E_7~0;~E_7~0 := 2; 8180#L1204-3 assume 1 == ~E_8~0;~E_8~0 := 2; 8483#L1209-3 assume 1 == ~E_9~0;~E_9~0 := 2; 7759#L1214-3 assume 1 == ~E_10~0;~E_10~0 := 2; 7760#L1219-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 8674#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 7845#L821-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 8196#L822-1 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 8197#L1539 assume !(0 == start_simulation_~tmp~3#1); 8289#L1539-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 8465#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 8272#L821-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 8405#L822-2 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 8188#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 8189#L1501 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8793#L1502 start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 8290#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 7741#L1520-2 [2021-12-16 10:06:01,314 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:01,315 INFO L85 PathProgramCache]: Analyzing trace with hash 1440481707, now seen corresponding path program 1 times [2021-12-16 10:06:01,315 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:01,316 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2011829869] [2021-12-16 10:06:01,316 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:01,316 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:01,339 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:06:01,373 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:06:01,374 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:06:01,374 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2011829869] [2021-12-16 10:06:01,374 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2011829869] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:06:01,375 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:06:01,375 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:06:01,377 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [953299525] [2021-12-16 10:06:01,378 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:06:01,378 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:06:01,378 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:01,379 INFO L85 PathProgramCache]: Analyzing trace with hash 871104042, now seen corresponding path program 1 times [2021-12-16 10:06:01,379 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:01,379 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [966094471] [2021-12-16 10:06:01,380 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:01,380 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:01,425 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:06:01,469 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:06:01,469 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:06:01,469 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [966094471] [2021-12-16 10:06:01,470 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [966094471] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:06:01,470 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:06:01,470 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:06:01,470 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [824028596] [2021-12-16 10:06:01,470 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:06:01,471 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:06:01,471 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:06:01,472 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-16 10:06:01,472 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-16 10:06:01,473 INFO L87 Difference]: Start difference. First operand 1278 states and 1899 transitions. cyclomatic complexity: 622 Second operand has 3 states, 3 states have (on average 42.0) internal successors, (126), 3 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:01,492 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:06:01,492 INFO L93 Difference]: Finished difference Result 1278 states and 1898 transitions. [2021-12-16 10:06:01,493 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-16 10:06:01,493 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1278 states and 1898 transitions. [2021-12-16 10:06:01,501 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1141 [2021-12-16 10:06:01,507 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1278 states to 1278 states and 1898 transitions. [2021-12-16 10:06:01,507 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1278 [2021-12-16 10:06:01,508 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1278 [2021-12-16 10:06:01,508 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1278 states and 1898 transitions. [2021-12-16 10:06:01,509 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:06:01,510 INFO L681 BuchiCegarLoop]: Abstraction has 1278 states and 1898 transitions. [2021-12-16 10:06:01,511 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1278 states and 1898 transitions. [2021-12-16 10:06:01,522 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1278 to 1278. [2021-12-16 10:06:01,524 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1278 states, 1278 states have (on average 1.4851330203442878) internal successors, (1898), 1277 states have internal predecessors, (1898), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:01,527 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1278 states to 1278 states and 1898 transitions. [2021-12-16 10:06:01,528 INFO L704 BuchiCegarLoop]: Abstraction has 1278 states and 1898 transitions. [2021-12-16 10:06:01,528 INFO L587 BuchiCegarLoop]: Abstraction has 1278 states and 1898 transitions. [2021-12-16 10:06:01,528 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2021-12-16 10:06:01,528 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1278 states and 1898 transitions. [2021-12-16 10:06:01,533 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1141 [2021-12-16 10:06:01,533 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:06:01,533 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:06:01,535 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:01,535 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:01,535 INFO L791 eck$LassoCheckResult]: Stem: 11248#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 11249#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 11524#L1483 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 11512#L694 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 11513#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 11533#L701-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 11534#L706-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10817#L711-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 10535#L716-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 10536#L721-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 11442#L726-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 11443#L731-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 11428#L736-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 11429#L741-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 11464#L746-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 10587#L751-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10588#L1006 assume !(0 == ~M_E~0); 10438#L1006-2 assume !(0 == ~T1_E~0); 10439#L1011-1 assume !(0 == ~T2_E~0); 11486#L1016-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11501#L1021-1 assume !(0 == ~T4_E~0); 10318#L1026-1 assume !(0 == ~T5_E~0); 10319#L1031-1 assume !(0 == ~T6_E~0); 11194#L1036-1 assume !(0 == ~T7_E~0); 11190#L1041-1 assume !(0 == ~T8_E~0); 11191#L1046-1 assume !(0 == ~T9_E~0); 10620#L1051-1 assume !(0 == ~T10_E~0); 10621#L1056-1 assume 0 == ~E_1~0;~E_1~0 := 1; 11323#L1061-1 assume !(0 == ~E_2~0); 10539#L1066-1 assume !(0 == ~E_3~0); 10540#L1071-1 assume !(0 == ~E_4~0); 11302#L1076-1 assume !(0 == ~E_5~0); 10449#L1081-1 assume !(0 == ~E_6~0); 10450#L1086-1 assume !(0 == ~E_7~0); 10792#L1091-1 assume !(0 == ~E_8~0); 11478#L1096-1 assume 0 == ~E_9~0;~E_9~0 := 1; 11479#L1101-1 assume !(0 == ~E_10~0); 10854#L1106-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10855#L484 assume !(1 == ~m_pc~0); 10498#L484-2 is_master_triggered_~__retres1~0#1 := 0; 10497#L495 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11113#L496 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 11397#L1245 assume !(0 != activate_threads_~tmp~1#1); 11398#L1245-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11182#L503 assume 1 == ~t1_pc~0; 11183#L504 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 11199#L514 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11315#L515 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 10965#L1253 assume !(0 != activate_threads_~tmp___0~0#1); 10348#L1253-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10349#L522 assume !(1 == ~t2_pc~0); 11149#L522-2 is_transmit2_triggered_~__retres1~2#1 := 0; 10552#L533 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10553#L534 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 11023#L1261 assume !(0 != activate_threads_~tmp___1~0#1); 11444#L1261-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11509#L541 assume 1 == ~t3_pc~0; 11098#L542 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 10914#L552 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10729#L553 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10730#L1269 assume !(0 != activate_threads_~tmp___2~0#1); 11152#L1269-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 11153#L560 assume !(1 == ~t4_pc~0); 10430#L560-2 is_transmit4_triggered_~__retres1~4#1 := 0; 10429#L571 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11057#L572 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 10316#L1277 assume !(0 != activate_threads_~tmp___3~0#1); 10317#L1277-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10601#L579 assume 1 == ~t5_pc~0; 10267#L580 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 10268#L590 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10376#L591 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 11060#L1285 assume !(0 != activate_threads_~tmp___4~0#1); 11499#L1285-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11521#L598 assume 1 == ~t6_pc~0; 10697#L599 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 10698#L609 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 10999#L610 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 11420#L1293 assume !(0 != activate_threads_~tmp___5~0#1); 11231#L1293-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 11173#L617 assume !(1 == ~t7_pc~0); 10670#L617-2 is_transmit7_triggered_~__retres1~7#1 := 0; 10669#L628 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10955#L629 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 10956#L1301 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 10891#L1301-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 10892#L636 assume 1 == ~t8_pc~0; 11054#L637 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 11055#L647 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 10856#L648 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 10857#L1309 assume !(0 != activate_threads_~tmp___7~0#1); 11007#L1309-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 11008#L655 assume !(1 == ~t9_pc~0); 11035#L655-2 is_transmit9_triggered_~__retres1~9#1 := 0; 11036#L666 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 10649#L667 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 10650#L1317 assume !(0 != activate_threads_~tmp___8~0#1); 11250#L1317-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 11251#L674 assume 1 == ~t10_pc~0; 10425#L675 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 10426#L685 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 11511#L686 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 11542#L1325 assume !(0 != activate_threads_~tmp___9~0#1); 10997#L1325-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10998#L1119 assume !(1 == ~M_E~0); 10521#L1119-2 assume !(1 == ~T1_E~0); 10522#L1124-1 assume !(1 == ~T2_E~0); 10340#L1129-1 assume !(1 == ~T3_E~0); 10341#L1134-1 assume !(1 == ~T4_E~0); 10652#L1139-1 assume !(1 == ~T5_E~0); 10653#L1144-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 10887#L1149-1 assume !(1 == ~T7_E~0); 10516#L1154-1 assume !(1 == ~T8_E~0); 10517#L1159-1 assume !(1 == ~T9_E~0); 10604#L1164-1 assume !(1 == ~T10_E~0); 11026#L1169-1 assume !(1 == ~E_1~0); 10924#L1174-1 assume !(1 == ~E_2~0); 10711#L1179-1 assume !(1 == ~E_3~0); 10593#L1184-1 assume 1 == ~E_4~0;~E_4~0 := 2; 10594#L1189-1 assume !(1 == ~E_5~0); 10646#L1194-1 assume !(1 == ~E_6~0); 10770#L1199-1 assume !(1 == ~E_7~0); 10721#L1204-1 assume !(1 == ~E_8~0); 10722#L1209-1 assume !(1 == ~E_9~0); 11245#L1214-1 assume !(1 == ~E_10~0); 11246#L1219-1 assume { :end_inline_reset_delta_events } true; 10304#L1520-2 [2021-12-16 10:06:01,536 INFO L793 eck$LassoCheckResult]: Loop: 10304#L1520-2 assume !false; 10305#L1521 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 10405#L981 assume !false; 10597#L832 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 11272#L764 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 10290#L821 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 11390#L822 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 11440#L836 assume !(0 != eval_~tmp~0#1); 10882#L996 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 10883#L694-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 10878#L1006-3 assume 0 == ~M_E~0;~M_E~0 := 1; 10879#L1006-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 11349#L1011-3 assume !(0 == ~T2_E~0); 11350#L1016-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11389#L1021-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 11070#L1026-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 11071#L1031-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 11317#L1036-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 11318#L1041-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 11378#L1046-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 11379#L1051-3 assume !(0 == ~T10_E~0); 11319#L1056-3 assume 0 == ~E_1~0;~E_1~0 := 1; 10615#L1061-3 assume 0 == ~E_2~0;~E_2~0 := 1; 10616#L1066-3 assume 0 == ~E_3~0;~E_3~0 := 1; 10619#L1071-3 assume 0 == ~E_4~0;~E_4~0 := 1; 11490#L1076-3 assume 0 == ~E_5~0;~E_5~0 := 1; 10402#L1081-3 assume 0 == ~E_6~0;~E_6~0 := 1; 10403#L1086-3 assume 0 == ~E_7~0;~E_7~0 := 1; 10455#L1091-3 assume !(0 == ~E_8~0); 10456#L1096-3 assume 0 == ~E_9~0;~E_9~0 := 1; 11465#L1101-3 assume 0 == ~E_10~0;~E_10~0 := 1; 11466#L1106-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11092#L484-33 assume 1 == ~m_pc~0; 11093#L485-11 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 11012#L495-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11013#L496-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 10310#L1245-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 10311#L1245-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10779#L503-33 assume !(1 == ~t1_pc~0); 10780#L503-35 is_transmit1_triggered_~__retres1~1#1 := 0; 11233#L514-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11160#L515-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 10689#L1253-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 10690#L1253-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11129#L522-33 assume 1 == ~t2_pc~0; 11130#L523-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 10443#L533-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10444#L534-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 11238#L1261-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 11147#L1261-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11148#L541-33 assume 1 == ~t3_pc~0; 10469#L542-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 10308#L552-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10309#L553-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 11119#L1269-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 11120#L1269-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 11314#L560-33 assume 1 == ~t4_pc~0; 11019#L561-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 10380#L571-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10381#L572-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 10639#L1277-33 assume !(0 != activate_threads_~tmp___3~0#1); 11296#L1277-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10299#L579-33 assume 1 == ~t5_pc~0; 10300#L580-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 10546#L590-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11505#L591-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 11174#L1285-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 11175#L1285-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11203#L598-33 assume !(1 == ~t6_pc~0); 10977#L598-35 is_transmit6_triggered_~__retres1~6#1 := 0; 10803#L609-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 10804#L610-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 10644#L1293-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 10645#L1293-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 11454#L617-33 assume 1 == ~t7_pc~0; 11460#L618-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 10437#L628-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 11388#L629-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 11495#L1301-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 11491#L1301-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 10368#L636-33 assume !(1 == ~t8_pc~0); 10369#L636-35 is_transmit8_triggered_~__retres1~8#1 := 0; 11288#L647-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 11289#L648-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 11514#L1309-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 11279#L1309-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 11280#L655-33 assume 1 == ~t9_pc~0; 11538#L656-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 10746#L666-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 10747#L667-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 11103#L1317-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 11367#L1317-35 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 10923#L674-33 assume !(1 == ~t10_pc~0); 10800#L674-35 is_transmit10_triggered_~__retres1~10#1 := 0; 10799#L685-11 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 10660#L686-11 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 10661#L1325-33 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 11138#L1325-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11515#L1119-3 assume 1 == ~M_E~0;~M_E~0 := 2; 11522#L1119-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 11526#L1124-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 11536#L1129-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 10685#L1134-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 10686#L1139-3 assume !(1 == ~T5_E~0); 10916#L1144-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 10917#L1149-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 11059#L1154-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 11329#L1159-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 11330#L1164-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 11497#L1169-3 assume 1 == ~E_1~0;~E_1~0 := 2; 10801#L1174-3 assume 1 == ~E_2~0;~E_2~0 := 2; 10802#L1179-3 assume !(1 == ~E_3~0); 11421#L1184-3 assume 1 == ~E_4~0;~E_4~0 := 2; 10431#L1189-3 assume 1 == ~E_5~0;~E_5~0 := 2; 10432#L1194-3 assume 1 == ~E_6~0;~E_6~0 := 2; 10742#L1199-3 assume 1 == ~E_7~0;~E_7~0 := 2; 10743#L1204-3 assume 1 == ~E_8~0;~E_8~0 := 2; 11046#L1209-3 assume 1 == ~E_9~0;~E_9~0 := 2; 10322#L1214-3 assume 1 == ~E_10~0;~E_10~0 := 2; 10323#L1219-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 11237#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 10408#L821-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 10759#L822-1 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 10760#L1539 assume !(0 == start_simulation_~tmp~3#1); 10852#L1539-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 11028#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 10835#L821-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 10968#L822-2 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 10751#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 10752#L1501 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 11356#L1502 start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 10853#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 10304#L1520-2 [2021-12-16 10:06:01,536 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:01,536 INFO L85 PathProgramCache]: Analyzing trace with hash -1012009875, now seen corresponding path program 1 times [2021-12-16 10:06:01,537 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:01,537 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1827327477] [2021-12-16 10:06:01,537 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:01,537 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:01,548 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:06:01,567 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:06:01,567 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:06:01,567 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1827327477] [2021-12-16 10:06:01,568 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1827327477] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:06:01,568 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:06:01,568 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:06:01,568 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [480398232] [2021-12-16 10:06:01,568 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:06:01,569 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:06:01,569 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:01,569 INFO L85 PathProgramCache]: Analyzing trace with hash -1010948599, now seen corresponding path program 1 times [2021-12-16 10:06:01,569 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:01,570 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2083033092] [2021-12-16 10:06:01,570 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:01,570 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:01,582 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:06:01,604 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:06:01,605 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:06:01,605 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2083033092] [2021-12-16 10:06:01,605 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2083033092] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:06:01,605 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:06:01,606 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:06:01,606 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2069256297] [2021-12-16 10:06:01,606 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:06:01,606 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:06:01,607 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:06:01,607 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-16 10:06:01,607 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-16 10:06:01,607 INFO L87 Difference]: Start difference. First operand 1278 states and 1898 transitions. cyclomatic complexity: 621 Second operand has 3 states, 3 states have (on average 42.0) internal successors, (126), 3 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:01,628 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:06:01,628 INFO L93 Difference]: Finished difference Result 1278 states and 1897 transitions. [2021-12-16 10:06:01,628 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-16 10:06:01,629 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1278 states and 1897 transitions. [2021-12-16 10:06:01,636 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1141 [2021-12-16 10:06:01,642 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1278 states to 1278 states and 1897 transitions. [2021-12-16 10:06:01,642 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1278 [2021-12-16 10:06:01,643 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1278 [2021-12-16 10:06:01,643 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1278 states and 1897 transitions. [2021-12-16 10:06:01,645 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:06:01,645 INFO L681 BuchiCegarLoop]: Abstraction has 1278 states and 1897 transitions. [2021-12-16 10:06:01,647 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1278 states and 1897 transitions. [2021-12-16 10:06:01,684 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1278 to 1278. [2021-12-16 10:06:01,686 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1278 states, 1278 states have (on average 1.4843505477308294) internal successors, (1897), 1277 states have internal predecessors, (1897), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:01,689 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1278 states to 1278 states and 1897 transitions. [2021-12-16 10:06:01,690 INFO L704 BuchiCegarLoop]: Abstraction has 1278 states and 1897 transitions. [2021-12-16 10:06:01,690 INFO L587 BuchiCegarLoop]: Abstraction has 1278 states and 1897 transitions. [2021-12-16 10:06:01,690 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2021-12-16 10:06:01,690 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1278 states and 1897 transitions. [2021-12-16 10:06:01,696 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1141 [2021-12-16 10:06:01,696 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:06:01,696 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:06:01,698 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:01,698 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:01,698 INFO L791 eck$LassoCheckResult]: Stem: 13812#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 13813#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 14087#L1483 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 14075#L694 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 14076#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 14096#L701-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 14097#L706-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 13380#L711-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 13098#L716-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 13099#L721-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 14005#L726-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 14006#L731-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 13991#L736-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 13992#L741-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 14027#L746-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 13152#L751-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 13153#L1006 assume !(0 == ~M_E~0); 13001#L1006-2 assume !(0 == ~T1_E~0); 13002#L1011-1 assume !(0 == ~T2_E~0); 14049#L1016-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 14064#L1021-1 assume !(0 == ~T4_E~0); 12883#L1026-1 assume !(0 == ~T5_E~0); 12884#L1031-1 assume !(0 == ~T6_E~0); 13757#L1036-1 assume !(0 == ~T7_E~0); 13753#L1041-1 assume !(0 == ~T8_E~0); 13754#L1046-1 assume !(0 == ~T9_E~0); 13183#L1051-1 assume !(0 == ~T10_E~0); 13184#L1056-1 assume 0 == ~E_1~0;~E_1~0 := 1; 13886#L1061-1 assume !(0 == ~E_2~0); 13102#L1066-1 assume !(0 == ~E_3~0); 13103#L1071-1 assume !(0 == ~E_4~0); 13865#L1076-1 assume !(0 == ~E_5~0); 13012#L1081-1 assume !(0 == ~E_6~0); 13013#L1086-1 assume !(0 == ~E_7~0); 13355#L1091-1 assume !(0 == ~E_8~0); 14042#L1096-1 assume 0 == ~E_9~0;~E_9~0 := 1; 14043#L1101-1 assume !(0 == ~E_10~0); 13417#L1106-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13418#L484 assume !(1 == ~m_pc~0); 13061#L484-2 is_master_triggered_~__retres1~0#1 := 0; 13060#L495 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13676#L496 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 13960#L1245 assume !(0 != activate_threads_~tmp~1#1); 13961#L1245-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13745#L503 assume 1 == ~t1_pc~0; 13746#L504 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 13763#L514 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13878#L515 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 13531#L1253 assume !(0 != activate_threads_~tmp___0~0#1); 12911#L1253-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12912#L522 assume !(1 == ~t2_pc~0); 13712#L522-2 is_transmit2_triggered_~__retres1~2#1 := 0; 13115#L533 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13116#L534 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 13586#L1261 assume !(0 != activate_threads_~tmp___1~0#1); 14007#L1261-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14072#L541 assume 1 == ~t3_pc~0; 13661#L542 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 13477#L552 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13292#L553 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 13293#L1269 assume !(0 != activate_threads_~tmp___2~0#1); 13715#L1269-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13716#L560 assume !(1 == ~t4_pc~0); 12995#L560-2 is_transmit4_triggered_~__retres1~4#1 := 0; 12994#L571 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13620#L572 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12879#L1277 assume !(0 != activate_threads_~tmp___3~0#1); 12880#L1277-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13166#L579 assume 1 == ~t5_pc~0; 12830#L580 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12831#L590 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12939#L591 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 13623#L1285 assume !(0 != activate_threads_~tmp___4~0#1); 14063#L1285-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14084#L598 assume 1 == ~t6_pc~0; 13260#L599 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 13261#L609 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 13563#L610 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 13983#L1293 assume !(0 != activate_threads_~tmp___5~0#1); 13794#L1293-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 13736#L617 assume !(1 == ~t7_pc~0); 13233#L617-2 is_transmit7_triggered_~__retres1~7#1 := 0; 13232#L628 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 13518#L629 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 13519#L1301 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 13454#L1301-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 13455#L636 assume 1 == ~t8_pc~0; 13617#L637 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 13618#L647 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 13419#L648 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 13420#L1309 assume !(0 != activate_threads_~tmp___7~0#1); 13572#L1309-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 13573#L655 assume !(1 == ~t9_pc~0); 13600#L655-2 is_transmit9_triggered_~__retres1~9#1 := 0; 13601#L666 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 13212#L667 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 13213#L1317 assume !(0 != activate_threads_~tmp___8~0#1); 13814#L1317-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 13815#L674 assume 1 == ~t10_pc~0; 12988#L675 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 12989#L685 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 14074#L686 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 14105#L1325 assume !(0 != activate_threads_~tmp___9~0#1); 13560#L1325-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13561#L1119 assume !(1 == ~M_E~0); 13084#L1119-2 assume !(1 == ~T1_E~0); 13085#L1124-1 assume !(1 == ~T2_E~0); 12903#L1129-1 assume !(1 == ~T3_E~0); 12904#L1134-1 assume !(1 == ~T4_E~0); 13217#L1139-1 assume !(1 == ~T5_E~0); 13218#L1144-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 13450#L1149-1 assume !(1 == ~T7_E~0); 13079#L1154-1 assume !(1 == ~T8_E~0); 13080#L1159-1 assume !(1 == ~T9_E~0); 13167#L1164-1 assume !(1 == ~T10_E~0); 13589#L1169-1 assume !(1 == ~E_1~0); 13487#L1174-1 assume !(1 == ~E_2~0); 13274#L1179-1 assume !(1 == ~E_3~0); 13156#L1184-1 assume 1 == ~E_4~0;~E_4~0 := 2; 13157#L1189-1 assume !(1 == ~E_5~0); 13210#L1194-1 assume !(1 == ~E_6~0); 13333#L1199-1 assume !(1 == ~E_7~0); 13284#L1204-1 assume !(1 == ~E_8~0); 13285#L1209-1 assume !(1 == ~E_9~0); 13808#L1214-1 assume !(1 == ~E_10~0); 13809#L1219-1 assume { :end_inline_reset_delta_events } true; 12867#L1520-2 [2021-12-16 10:06:01,699 INFO L793 eck$LassoCheckResult]: Loop: 12867#L1520-2 assume !false; 12868#L1521 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 12971#L981 assume !false; 13163#L832 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 13835#L764 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 12853#L821 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 13953#L822 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 14003#L836 assume !(0 != eval_~tmp~0#1); 13445#L996 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 13446#L694-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 13441#L1006-3 assume 0 == ~M_E~0;~M_E~0 := 1; 13442#L1006-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 13912#L1011-3 assume !(0 == ~T2_E~0); 13913#L1016-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 13952#L1021-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 13635#L1026-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 13636#L1031-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 13880#L1036-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 13881#L1041-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 13943#L1046-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 13944#L1051-3 assume !(0 == ~T10_E~0); 13882#L1056-3 assume 0 == ~E_1~0;~E_1~0 := 1; 13180#L1061-3 assume 0 == ~E_2~0;~E_2~0 := 1; 13181#L1066-3 assume 0 == ~E_3~0;~E_3~0 := 1; 13182#L1071-3 assume 0 == ~E_4~0;~E_4~0 := 1; 14053#L1076-3 assume 0 == ~E_5~0;~E_5~0 := 1; 12965#L1081-3 assume 0 == ~E_6~0;~E_6~0 := 1; 12966#L1086-3 assume 0 == ~E_7~0;~E_7~0 := 1; 13020#L1091-3 assume !(0 == ~E_8~0); 13021#L1096-3 assume 0 == ~E_9~0;~E_9~0 := 1; 14028#L1101-3 assume 0 == ~E_10~0;~E_10~0 := 1; 14029#L1106-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13655#L484-33 assume 1 == ~m_pc~0; 13656#L485-11 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 13575#L495-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13576#L496-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 12873#L1245-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12874#L1245-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13345#L503-33 assume !(1 == ~t1_pc~0); 13346#L503-35 is_transmit1_triggered_~__retres1~1#1 := 0; 13796#L514-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13725#L515-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 13252#L1253-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 13253#L1253-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13692#L522-33 assume 1 == ~t2_pc~0; 13693#L523-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 13008#L533-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13009#L534-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 13802#L1261-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 13710#L1261-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 13711#L541-33 assume 1 == ~t3_pc~0; 13032#L542-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 12871#L552-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12872#L553-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 13682#L1269-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 13683#L1269-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13877#L560-33 assume 1 == ~t4_pc~0; 13582#L561-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 12943#L571-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12944#L572-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 13200#L1277-33 assume !(0 != activate_threads_~tmp___3~0#1); 13859#L1277-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12859#L579-33 assume 1 == ~t5_pc~0; 12860#L580-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 13108#L590-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 14068#L591-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 13737#L1285-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 13738#L1285-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 13762#L598-33 assume 1 == ~t6_pc~0; 14069#L599-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 13366#L609-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 13367#L610-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 13207#L1293-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 13208#L1293-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 14017#L617-33 assume 1 == ~t7_pc~0; 14023#L618-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 13000#L628-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 13951#L629-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 14058#L1301-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 14054#L1301-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12931#L636-33 assume !(1 == ~t8_pc~0); 12932#L636-35 is_transmit8_triggered_~__retres1~8#1 := 0; 13851#L647-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 13852#L648-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 14077#L1309-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 13840#L1309-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 13841#L655-33 assume 1 == ~t9_pc~0; 14101#L656-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 13307#L666-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 13308#L667-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 13666#L1317-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 13930#L1317-35 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 13486#L674-33 assume 1 == ~t10_pc~0; 13361#L675-11 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 13362#L685-11 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 13223#L686-11 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 13224#L1325-33 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 13701#L1325-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14078#L1119-3 assume 1 == ~M_E~0;~M_E~0 := 2; 14085#L1119-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 14088#L1124-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 14099#L1129-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 13245#L1134-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 13246#L1139-3 assume !(1 == ~T5_E~0); 13479#L1144-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 13480#L1149-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 13622#L1154-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 13892#L1159-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 13893#L1164-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 14059#L1169-3 assume 1 == ~E_1~0;~E_1~0 := 2; 13364#L1174-3 assume 1 == ~E_2~0;~E_2~0 := 2; 13365#L1179-3 assume !(1 == ~E_3~0); 13984#L1184-3 assume 1 == ~E_4~0;~E_4~0 := 2; 12991#L1189-3 assume 1 == ~E_5~0;~E_5~0 := 2; 12992#L1194-3 assume 1 == ~E_6~0;~E_6~0 := 2; 13305#L1199-3 assume 1 == ~E_7~0;~E_7~0 := 2; 13306#L1204-3 assume 1 == ~E_8~0;~E_8~0 := 2; 13609#L1209-3 assume 1 == ~E_9~0;~E_9~0 := 2; 12885#L1214-3 assume 1 == ~E_10~0;~E_10~0 := 2; 12886#L1219-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 13799#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 12968#L821-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 13322#L822-1 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 13323#L1539 assume !(0 == start_simulation_~tmp~3#1); 13415#L1539-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 13591#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 13398#L821-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 13530#L822-2 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 13314#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 13315#L1501 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 13919#L1502 start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 13416#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 12867#L1520-2 [2021-12-16 10:06:01,699 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:01,699 INFO L85 PathProgramCache]: Analyzing trace with hash 709992811, now seen corresponding path program 1 times [2021-12-16 10:06:01,700 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:01,700 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [42001095] [2021-12-16 10:06:01,700 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:01,700 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:01,709 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:06:01,724 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:06:01,725 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:06:01,725 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [42001095] [2021-12-16 10:06:01,725 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [42001095] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:06:01,725 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:06:01,725 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:06:01,726 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [920194351] [2021-12-16 10:06:01,726 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:06:01,726 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:06:01,727 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:01,727 INFO L85 PathProgramCache]: Analyzing trace with hash -2115858485, now seen corresponding path program 1 times [2021-12-16 10:06:01,727 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:01,727 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [665923410] [2021-12-16 10:06:01,728 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:01,728 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:01,739 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:06:01,762 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:06:01,762 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:06:01,762 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [665923410] [2021-12-16 10:06:01,763 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [665923410] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:06:01,763 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:06:01,763 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:06:01,763 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1313439269] [2021-12-16 10:06:01,763 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:06:01,764 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:06:01,764 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:06:01,764 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-16 10:06:01,765 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-16 10:06:01,765 INFO L87 Difference]: Start difference. First operand 1278 states and 1897 transitions. cyclomatic complexity: 620 Second operand has 3 states, 3 states have (on average 42.0) internal successors, (126), 3 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:01,787 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:06:01,787 INFO L93 Difference]: Finished difference Result 1278 states and 1896 transitions. [2021-12-16 10:06:01,787 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-16 10:06:01,788 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1278 states and 1896 transitions. [2021-12-16 10:06:01,796 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1141 [2021-12-16 10:06:01,802 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1278 states to 1278 states and 1896 transitions. [2021-12-16 10:06:01,802 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1278 [2021-12-16 10:06:01,803 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1278 [2021-12-16 10:06:01,803 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1278 states and 1896 transitions. [2021-12-16 10:06:01,805 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:06:01,805 INFO L681 BuchiCegarLoop]: Abstraction has 1278 states and 1896 transitions. [2021-12-16 10:06:01,807 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1278 states and 1896 transitions. [2021-12-16 10:06:01,819 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1278 to 1278. [2021-12-16 10:06:01,821 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1278 states, 1278 states have (on average 1.483568075117371) internal successors, (1896), 1277 states have internal predecessors, (1896), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:01,825 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1278 states to 1278 states and 1896 transitions. [2021-12-16 10:06:01,825 INFO L704 BuchiCegarLoop]: Abstraction has 1278 states and 1896 transitions. [2021-12-16 10:06:01,825 INFO L587 BuchiCegarLoop]: Abstraction has 1278 states and 1896 transitions. [2021-12-16 10:06:01,825 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2021-12-16 10:06:01,825 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1278 states and 1896 transitions. [2021-12-16 10:06:01,830 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1141 [2021-12-16 10:06:01,831 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:06:01,831 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:06:01,833 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:01,833 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:01,833 INFO L791 eck$LassoCheckResult]: Stem: 16375#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 16376#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 16650#L1483 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 16638#L694 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 16639#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 16659#L701-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 16660#L706-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 15943#L711-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 15663#L716-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 15664#L721-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 16568#L726-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 16569#L731-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 16554#L736-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 16555#L741-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 16590#L746-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 15715#L751-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 15716#L1006 assume !(0 == ~M_E~0); 15567#L1006-2 assume !(0 == ~T1_E~0); 15568#L1011-1 assume !(0 == ~T2_E~0); 16612#L1016-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 16627#L1021-1 assume !(0 == ~T4_E~0); 15446#L1026-1 assume !(0 == ~T5_E~0); 15447#L1031-1 assume !(0 == ~T6_E~0); 16322#L1036-1 assume !(0 == ~T7_E~0); 16316#L1041-1 assume !(0 == ~T8_E~0); 16317#L1046-1 assume !(0 == ~T9_E~0); 15746#L1051-1 assume !(0 == ~T10_E~0); 15747#L1056-1 assume 0 == ~E_1~0;~E_1~0 := 1; 16449#L1061-1 assume !(0 == ~E_2~0); 15665#L1066-1 assume !(0 == ~E_3~0); 15666#L1071-1 assume !(0 == ~E_4~0); 16428#L1076-1 assume !(0 == ~E_5~0); 15575#L1081-1 assume !(0 == ~E_6~0); 15576#L1086-1 assume !(0 == ~E_7~0); 15919#L1091-1 assume !(0 == ~E_8~0); 16605#L1096-1 assume 0 == ~E_9~0;~E_9~0 := 1; 16606#L1101-1 assume !(0 == ~E_10~0); 15980#L1106-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15981#L484 assume !(1 == ~m_pc~0); 15624#L484-2 is_master_triggered_~__retres1~0#1 := 0; 15623#L495 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16239#L496 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 16523#L1245 assume !(0 != activate_threads_~tmp~1#1); 16524#L1245-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16308#L503 assume 1 == ~t1_pc~0; 16309#L504 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 16327#L514 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16441#L515 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 16094#L1253 assume !(0 != activate_threads_~tmp___0~0#1); 15476#L1253-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15477#L522 assume !(1 == ~t2_pc~0); 16275#L522-2 is_transmit2_triggered_~__retres1~2#1 := 0; 15679#L533 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 15680#L534 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 16149#L1261 assume !(0 != activate_threads_~tmp___1~0#1); 16570#L1261-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16635#L541 assume 1 == ~t3_pc~0; 16226#L542 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 16040#L552 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15855#L553 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 15856#L1269 assume !(0 != activate_threads_~tmp___2~0#1); 16282#L1269-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16283#L560 assume !(1 == ~t4_pc~0); 15558#L560-2 is_transmit4_triggered_~__retres1~4#1 := 0; 15557#L571 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 16183#L572 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 15442#L1277 assume !(0 != activate_threads_~tmp___3~0#1); 15443#L1277-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 15729#L579 assume 1 == ~t5_pc~0; 15393#L580 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 15394#L590 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15502#L591 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 16186#L1285 assume !(0 != activate_threads_~tmp___4~0#1); 16626#L1285-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 16647#L598 assume 1 == ~t6_pc~0; 15825#L599 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 15826#L609 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 16128#L610 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 16546#L1293 assume !(0 != activate_threads_~tmp___5~0#1); 16357#L1293-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 16299#L617 assume !(1 == ~t7_pc~0); 15796#L617-2 is_transmit7_triggered_~__retres1~7#1 := 0; 15795#L628 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16081#L629 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 16082#L1301 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 16018#L1301-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 16019#L636 assume 1 == ~t8_pc~0; 16180#L637 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 16181#L647 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 15982#L648 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 15983#L1309 assume !(0 != activate_threads_~tmp___7~0#1); 16135#L1309-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 16136#L655 assume !(1 == ~t9_pc~0); 16165#L655-2 is_transmit9_triggered_~__retres1~9#1 := 0; 16166#L666 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 15775#L667 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 15776#L1317 assume !(0 != activate_threads_~tmp___8~0#1); 16377#L1317-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 16378#L674 assume 1 == ~t10_pc~0; 15551#L675 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 15552#L685 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 16637#L686 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 16668#L1325 assume !(0 != activate_threads_~tmp___9~0#1); 16123#L1325-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16124#L1119 assume !(1 == ~M_E~0); 15647#L1119-2 assume !(1 == ~T1_E~0); 15648#L1124-1 assume !(1 == ~T2_E~0); 15466#L1129-1 assume !(1 == ~T3_E~0); 15467#L1134-1 assume !(1 == ~T4_E~0); 15780#L1139-1 assume !(1 == ~T5_E~0); 15781#L1144-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 16013#L1149-1 assume !(1 == ~T7_E~0); 15642#L1154-1 assume !(1 == ~T8_E~0); 15643#L1159-1 assume !(1 == ~T9_E~0); 15730#L1164-1 assume !(1 == ~T10_E~0); 16152#L1169-1 assume !(1 == ~E_1~0); 16050#L1174-1 assume !(1 == ~E_2~0); 15839#L1179-1 assume !(1 == ~E_3~0); 15719#L1184-1 assume 1 == ~E_4~0;~E_4~0 := 2; 15720#L1189-1 assume !(1 == ~E_5~0); 15774#L1194-1 assume !(1 == ~E_6~0); 15896#L1199-1 assume !(1 == ~E_7~0); 15847#L1204-1 assume !(1 == ~E_8~0); 15848#L1209-1 assume !(1 == ~E_9~0); 16371#L1214-1 assume !(1 == ~E_10~0); 16372#L1219-1 assume { :end_inline_reset_delta_events } true; 15430#L1520-2 [2021-12-16 10:06:01,834 INFO L793 eck$LassoCheckResult]: Loop: 15430#L1520-2 assume !false; 15431#L1521 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 15531#L981 assume !false; 15726#L832 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 16398#L764 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 15416#L821 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 16516#L822 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 16566#L836 assume !(0 != eval_~tmp~0#1); 16011#L996 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 16012#L694-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 16004#L1006-3 assume 0 == ~M_E~0;~M_E~0 := 1; 16005#L1006-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 16475#L1011-3 assume !(0 == ~T2_E~0); 16476#L1016-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 16515#L1021-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 16198#L1026-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 16199#L1031-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 16443#L1036-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 16444#L1041-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 16504#L1046-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 16505#L1051-3 assume !(0 == ~T10_E~0); 16445#L1056-3 assume 0 == ~E_1~0;~E_1~0 := 1; 15741#L1061-3 assume 0 == ~E_2~0;~E_2~0 := 1; 15742#L1066-3 assume 0 == ~E_3~0;~E_3~0 := 1; 15745#L1071-3 assume 0 == ~E_4~0;~E_4~0 := 1; 16616#L1076-3 assume 0 == ~E_5~0;~E_5~0 := 1; 15528#L1081-3 assume 0 == ~E_6~0;~E_6~0 := 1; 15529#L1086-3 assume 0 == ~E_7~0;~E_7~0 := 1; 15581#L1091-3 assume !(0 == ~E_8~0); 15582#L1096-3 assume 0 == ~E_9~0;~E_9~0 := 1; 16591#L1101-3 assume 0 == ~E_10~0;~E_10~0 := 1; 16592#L1106-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16218#L484-33 assume 1 == ~m_pc~0; 16219#L485-11 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 16138#L495-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16139#L496-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 15436#L1245-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 15437#L1245-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15905#L503-33 assume !(1 == ~t1_pc~0); 15906#L503-35 is_transmit1_triggered_~__retres1~1#1 := 0; 16359#L514-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16285#L515-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 15813#L1253-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 15814#L1253-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16255#L522-33 assume 1 == ~t2_pc~0; 16256#L523-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 15569#L533-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 15570#L534-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 16364#L1261-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 16273#L1261-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16274#L541-33 assume 1 == ~t3_pc~0; 15595#L542-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 15434#L552-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15435#L553-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 16245#L1269-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 16246#L1269-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16440#L560-33 assume 1 == ~t4_pc~0; 16145#L561-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 15506#L571-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 15507#L572-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 15765#L1277-33 assume !(0 != activate_threads_~tmp___3~0#1); 16422#L1277-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 15425#L579-33 assume 1 == ~t5_pc~0; 15426#L580-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 15672#L590-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 16631#L591-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 16300#L1285-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 16301#L1285-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 16326#L598-33 assume !(1 == ~t6_pc~0); 16103#L598-35 is_transmit6_triggered_~__retres1~6#1 := 0; 15929#L609-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 15930#L610-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 15770#L1293-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 15771#L1293-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 16580#L617-33 assume 1 == ~t7_pc~0; 16586#L618-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 15563#L628-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16514#L629-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 16621#L1301-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 16617#L1301-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 15494#L636-33 assume !(1 == ~t8_pc~0); 15495#L636-35 is_transmit8_triggered_~__retres1~8#1 := 0; 16414#L647-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 16415#L648-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 16640#L1309-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 16405#L1309-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 16406#L655-33 assume 1 == ~t9_pc~0; 16664#L656-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 15870#L666-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 15871#L667-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 16229#L1317-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 16493#L1317-35 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 16049#L674-33 assume 1 == ~t10_pc~0; 15924#L675-11 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 15925#L685-11 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 15786#L686-11 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 15787#L1325-33 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 16264#L1325-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16641#L1119-3 assume 1 == ~M_E~0;~M_E~0 := 2; 16648#L1119-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 16652#L1124-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 16662#L1129-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 15811#L1134-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 15812#L1139-3 assume !(1 == ~T5_E~0); 16042#L1144-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 16043#L1149-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 16185#L1154-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 16455#L1159-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 16456#L1164-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 16623#L1169-3 assume 1 == ~E_1~0;~E_1~0 := 2; 15927#L1174-3 assume 1 == ~E_2~0;~E_2~0 := 2; 15928#L1179-3 assume !(1 == ~E_3~0); 16547#L1184-3 assume 1 == ~E_4~0;~E_4~0 := 2; 15554#L1189-3 assume 1 == ~E_5~0;~E_5~0 := 2; 15555#L1194-3 assume 1 == ~E_6~0;~E_6~0 := 2; 15868#L1199-3 assume 1 == ~E_7~0;~E_7~0 := 2; 15869#L1204-3 assume 1 == ~E_8~0;~E_8~0 := 2; 16172#L1209-3 assume 1 == ~E_9~0;~E_9~0 := 2; 15448#L1214-3 assume 1 == ~E_10~0;~E_10~0 := 2; 15449#L1219-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 16363#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 15534#L821-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 15885#L822-1 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 15886#L1539 assume !(0 == start_simulation_~tmp~3#1); 15978#L1539-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 16154#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 15961#L821-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 16093#L822-2 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 15877#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 15878#L1501 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 16482#L1502 start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 15979#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 15430#L1520-2 [2021-12-16 10:06:01,834 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:01,835 INFO L85 PathProgramCache]: Analyzing trace with hash 1042635949, now seen corresponding path program 1 times [2021-12-16 10:06:01,835 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:01,835 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2132484780] [2021-12-16 10:06:01,835 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:01,835 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:01,845 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:06:01,863 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:06:01,863 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:06:01,864 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2132484780] [2021-12-16 10:06:01,864 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2132484780] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:06:01,864 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:06:01,864 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:06:01,864 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1922655278] [2021-12-16 10:06:01,864 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:06:01,865 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:06:01,865 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:01,865 INFO L85 PathProgramCache]: Analyzing trace with hash -1410939798, now seen corresponding path program 2 times [2021-12-16 10:06:01,866 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:01,866 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1141738566] [2021-12-16 10:06:01,866 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:01,866 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:01,879 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:06:01,904 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:06:01,904 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:06:01,905 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1141738566] [2021-12-16 10:06:01,905 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1141738566] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:06:01,905 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:06:01,905 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:06:01,905 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [486714374] [2021-12-16 10:06:01,905 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:06:01,906 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:06:01,906 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:06:01,906 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-16 10:06:01,907 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-16 10:06:01,907 INFO L87 Difference]: Start difference. First operand 1278 states and 1896 transitions. cyclomatic complexity: 619 Second operand has 3 states, 3 states have (on average 42.0) internal successors, (126), 3 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:01,929 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:06:01,929 INFO L93 Difference]: Finished difference Result 1278 states and 1895 transitions. [2021-12-16 10:06:01,929 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-16 10:06:01,931 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1278 states and 1895 transitions. [2021-12-16 10:06:01,939 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1141 [2021-12-16 10:06:01,945 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1278 states to 1278 states and 1895 transitions. [2021-12-16 10:06:01,945 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1278 [2021-12-16 10:06:01,946 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1278 [2021-12-16 10:06:01,946 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1278 states and 1895 transitions. [2021-12-16 10:06:01,948 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:06:01,948 INFO L681 BuchiCegarLoop]: Abstraction has 1278 states and 1895 transitions. [2021-12-16 10:06:01,950 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1278 states and 1895 transitions. [2021-12-16 10:06:01,987 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1278 to 1278. [2021-12-16 10:06:01,990 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1278 states, 1278 states have (on average 1.4827856025039123) internal successors, (1895), 1277 states have internal predecessors, (1895), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:01,994 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1278 states to 1278 states and 1895 transitions. [2021-12-16 10:06:01,994 INFO L704 BuchiCegarLoop]: Abstraction has 1278 states and 1895 transitions. [2021-12-16 10:06:01,994 INFO L587 BuchiCegarLoop]: Abstraction has 1278 states and 1895 transitions. [2021-12-16 10:06:01,994 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2021-12-16 10:06:01,995 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1278 states and 1895 transitions. [2021-12-16 10:06:02,000 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1141 [2021-12-16 10:06:02,000 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:06:02,000 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:06:02,002 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:02,002 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:02,003 INFO L791 eck$LassoCheckResult]: Stem: 18937#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 18938#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 19213#L1483 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 19201#L694 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 19202#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 19222#L701-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 19223#L706-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 18506#L711-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 18224#L716-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 18225#L721-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 19131#L726-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 19132#L731-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 19117#L736-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 19118#L741-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 19153#L746-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 18276#L751-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 18277#L1006 assume !(0 == ~M_E~0); 18127#L1006-2 assume !(0 == ~T1_E~0); 18128#L1011-1 assume !(0 == ~T2_E~0); 19175#L1016-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 19190#L1021-1 assume !(0 == ~T4_E~0); 18007#L1026-1 assume !(0 == ~T5_E~0); 18008#L1031-1 assume !(0 == ~T6_E~0); 18883#L1036-1 assume !(0 == ~T7_E~0); 18879#L1041-1 assume !(0 == ~T8_E~0); 18880#L1046-1 assume !(0 == ~T9_E~0); 18309#L1051-1 assume !(0 == ~T10_E~0); 18310#L1056-1 assume 0 == ~E_1~0;~E_1~0 := 1; 19012#L1061-1 assume !(0 == ~E_2~0); 18228#L1066-1 assume !(0 == ~E_3~0); 18229#L1071-1 assume !(0 == ~E_4~0); 18991#L1076-1 assume !(0 == ~E_5~0); 18138#L1081-1 assume !(0 == ~E_6~0); 18139#L1086-1 assume !(0 == ~E_7~0); 18481#L1091-1 assume !(0 == ~E_8~0); 19167#L1096-1 assume 0 == ~E_9~0;~E_9~0 := 1; 19168#L1101-1 assume !(0 == ~E_10~0); 18543#L1106-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 18544#L484 assume !(1 == ~m_pc~0); 18187#L484-2 is_master_triggered_~__retres1~0#1 := 0; 18186#L495 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 18802#L496 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 19086#L1245 assume !(0 != activate_threads_~tmp~1#1); 19087#L1245-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 18871#L503 assume 1 == ~t1_pc~0; 18872#L504 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 18888#L514 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19004#L515 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 18654#L1253 assume !(0 != activate_threads_~tmp___0~0#1); 18037#L1253-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18038#L522 assume !(1 == ~t2_pc~0); 18838#L522-2 is_transmit2_triggered_~__retres1~2#1 := 0; 18241#L533 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 18242#L534 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 18712#L1261 assume !(0 != activate_threads_~tmp___1~0#1); 19133#L1261-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19198#L541 assume 1 == ~t3_pc~0; 18787#L542 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 18603#L552 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18418#L553 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 18419#L1269 assume !(0 != activate_threads_~tmp___2~0#1); 18841#L1269-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 18842#L560 assume !(1 == ~t4_pc~0); 18119#L560-2 is_transmit4_triggered_~__retres1~4#1 := 0; 18118#L571 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 18746#L572 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 18005#L1277 assume !(0 != activate_threads_~tmp___3~0#1); 18006#L1277-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 18290#L579 assume 1 == ~t5_pc~0; 17956#L580 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 17957#L590 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 18065#L591 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 18749#L1285 assume !(0 != activate_threads_~tmp___4~0#1); 19188#L1285-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19210#L598 assume 1 == ~t6_pc~0; 18386#L599 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 18387#L609 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 18688#L610 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 19109#L1293 assume !(0 != activate_threads_~tmp___5~0#1); 18920#L1293-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 18862#L617 assume !(1 == ~t7_pc~0); 18359#L617-2 is_transmit7_triggered_~__retres1~7#1 := 0; 18358#L628 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 18644#L629 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 18645#L1301 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 18580#L1301-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 18581#L636 assume 1 == ~t8_pc~0; 18743#L637 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 18744#L647 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 18545#L648 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 18546#L1309 assume !(0 != activate_threads_~tmp___7~0#1); 18696#L1309-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 18697#L655 assume !(1 == ~t9_pc~0); 18724#L655-2 is_transmit9_triggered_~__retres1~9#1 := 0; 18725#L666 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 18338#L667 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 18339#L1317 assume !(0 != activate_threads_~tmp___8~0#1); 18939#L1317-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 18940#L674 assume 1 == ~t10_pc~0; 18114#L675 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 18115#L685 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 19200#L686 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 19231#L1325 assume !(0 != activate_threads_~tmp___9~0#1); 18686#L1325-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 18687#L1119 assume !(1 == ~M_E~0); 18210#L1119-2 assume !(1 == ~T1_E~0); 18211#L1124-1 assume !(1 == ~T2_E~0); 18029#L1129-1 assume !(1 == ~T3_E~0); 18030#L1134-1 assume !(1 == ~T4_E~0); 18340#L1139-1 assume !(1 == ~T5_E~0); 18341#L1144-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 18576#L1149-1 assume !(1 == ~T7_E~0); 18205#L1154-1 assume !(1 == ~T8_E~0); 18206#L1159-1 assume !(1 == ~T9_E~0); 18293#L1164-1 assume !(1 == ~T10_E~0); 18715#L1169-1 assume !(1 == ~E_1~0); 18613#L1174-1 assume !(1 == ~E_2~0); 18400#L1179-1 assume !(1 == ~E_3~0); 18282#L1184-1 assume 1 == ~E_4~0;~E_4~0 := 2; 18283#L1189-1 assume !(1 == ~E_5~0); 18335#L1194-1 assume !(1 == ~E_6~0); 18459#L1199-1 assume !(1 == ~E_7~0); 18410#L1204-1 assume !(1 == ~E_8~0); 18411#L1209-1 assume !(1 == ~E_9~0); 18934#L1214-1 assume !(1 == ~E_10~0); 18935#L1219-1 assume { :end_inline_reset_delta_events } true; 17993#L1520-2 [2021-12-16 10:06:02,003 INFO L793 eck$LassoCheckResult]: Loop: 17993#L1520-2 assume !false; 17994#L1521 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 18094#L981 assume !false; 18286#L832 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 18961#L764 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 17979#L821 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 19079#L822 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 19129#L836 assume !(0 != eval_~tmp~0#1); 18571#L996 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 18572#L694-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 18567#L1006-3 assume 0 == ~M_E~0;~M_E~0 := 1; 18568#L1006-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 19038#L1011-3 assume !(0 == ~T2_E~0); 19039#L1016-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 19078#L1021-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 18759#L1026-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 18760#L1031-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 19006#L1036-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 19007#L1041-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 19067#L1046-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 19068#L1051-3 assume !(0 == ~T10_E~0); 19008#L1056-3 assume 0 == ~E_1~0;~E_1~0 := 1; 18304#L1061-3 assume 0 == ~E_2~0;~E_2~0 := 1; 18305#L1066-3 assume 0 == ~E_3~0;~E_3~0 := 1; 18308#L1071-3 assume 0 == ~E_4~0;~E_4~0 := 1; 19179#L1076-3 assume 0 == ~E_5~0;~E_5~0 := 1; 18091#L1081-3 assume 0 == ~E_6~0;~E_6~0 := 1; 18092#L1086-3 assume 0 == ~E_7~0;~E_7~0 := 1; 18144#L1091-3 assume !(0 == ~E_8~0); 18145#L1096-3 assume 0 == ~E_9~0;~E_9~0 := 1; 19154#L1101-3 assume 0 == ~E_10~0;~E_10~0 := 1; 19155#L1106-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 18781#L484-33 assume 1 == ~m_pc~0; 18782#L485-11 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 18701#L495-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 18702#L496-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 17999#L1245-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 18000#L1245-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 18468#L503-33 assume !(1 == ~t1_pc~0); 18469#L503-35 is_transmit1_triggered_~__retres1~1#1 := 0; 18922#L514-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18849#L515-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 18378#L1253-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 18379#L1253-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18818#L522-33 assume 1 == ~t2_pc~0; 18819#L523-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 18132#L533-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 18133#L534-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 18927#L1261-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 18836#L1261-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18837#L541-33 assume 1 == ~t3_pc~0; 18158#L542-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 17997#L552-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 17998#L553-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 18808#L1269-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 18809#L1269-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19003#L560-33 assume 1 == ~t4_pc~0; 18708#L561-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 18069#L571-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 18070#L572-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 18328#L1277-33 assume !(0 != activate_threads_~tmp___3~0#1); 18985#L1277-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 17988#L579-33 assume 1 == ~t5_pc~0; 17989#L580-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 18235#L590-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19194#L591-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 18863#L1285-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 18864#L1285-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 18892#L598-33 assume !(1 == ~t6_pc~0); 18666#L598-35 is_transmit6_triggered_~__retres1~6#1 := 0; 18492#L609-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 18493#L610-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 18333#L1293-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 18334#L1293-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 19143#L617-33 assume 1 == ~t7_pc~0; 19149#L618-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 18126#L628-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19077#L629-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 19184#L1301-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 19180#L1301-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 18057#L636-33 assume !(1 == ~t8_pc~0); 18058#L636-35 is_transmit8_triggered_~__retres1~8#1 := 0; 18977#L647-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 18978#L648-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 19203#L1309-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 18968#L1309-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 18969#L655-33 assume 1 == ~t9_pc~0; 19227#L656-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 18435#L666-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 18436#L667-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 18792#L1317-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 19056#L1317-35 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 18612#L674-33 assume 1 == ~t10_pc~0; 18487#L675-11 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 18488#L685-11 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 18349#L686-11 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 18350#L1325-33 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 18827#L1325-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19204#L1119-3 assume 1 == ~M_E~0;~M_E~0 := 2; 19211#L1119-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 19215#L1124-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 19225#L1129-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 18374#L1134-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 18375#L1139-3 assume !(1 == ~T5_E~0); 18605#L1144-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 18606#L1149-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 18748#L1154-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 19018#L1159-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 19019#L1164-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 19186#L1169-3 assume 1 == ~E_1~0;~E_1~0 := 2; 18490#L1174-3 assume 1 == ~E_2~0;~E_2~0 := 2; 18491#L1179-3 assume !(1 == ~E_3~0); 19110#L1184-3 assume 1 == ~E_4~0;~E_4~0 := 2; 18120#L1189-3 assume 1 == ~E_5~0;~E_5~0 := 2; 18121#L1194-3 assume 1 == ~E_6~0;~E_6~0 := 2; 18431#L1199-3 assume 1 == ~E_7~0;~E_7~0 := 2; 18432#L1204-3 assume 1 == ~E_8~0;~E_8~0 := 2; 18735#L1209-3 assume 1 == ~E_9~0;~E_9~0 := 2; 18011#L1214-3 assume 1 == ~E_10~0;~E_10~0 := 2; 18012#L1219-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 18926#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 18097#L821-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 18448#L822-1 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 18449#L1539 assume !(0 == start_simulation_~tmp~3#1); 18541#L1539-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 18717#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 18524#L821-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 18657#L822-2 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 18440#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 18441#L1501 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 19045#L1502 start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 18542#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 17993#L1520-2 [2021-12-16 10:06:02,004 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:02,004 INFO L85 PathProgramCache]: Analyzing trace with hash -886296277, now seen corresponding path program 1 times [2021-12-16 10:06:02,004 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:02,004 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [826566951] [2021-12-16 10:06:02,004 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:02,005 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:02,015 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:06:02,031 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:06:02,031 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:06:02,031 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [826566951] [2021-12-16 10:06:02,031 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [826566951] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:06:02,032 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:06:02,032 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:06:02,032 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2038699065] [2021-12-16 10:06:02,032 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:06:02,032 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:06:02,033 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:02,033 INFO L85 PathProgramCache]: Analyzing trace with hash -1410939798, now seen corresponding path program 3 times [2021-12-16 10:06:02,033 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:02,033 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1706927074] [2021-12-16 10:06:02,034 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:02,034 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:02,046 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:06:02,066 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:06:02,066 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:06:02,066 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1706927074] [2021-12-16 10:06:02,066 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1706927074] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:06:02,067 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:06:02,067 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:06:02,067 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1594947633] [2021-12-16 10:06:02,067 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:06:02,068 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:06:02,068 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:06:02,068 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-16 10:06:02,068 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-16 10:06:02,069 INFO L87 Difference]: Start difference. First operand 1278 states and 1895 transitions. cyclomatic complexity: 618 Second operand has 3 states, 3 states have (on average 42.0) internal successors, (126), 3 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:02,091 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:06:02,091 INFO L93 Difference]: Finished difference Result 1278 states and 1894 transitions. [2021-12-16 10:06:02,091 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-16 10:06:02,092 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1278 states and 1894 transitions. [2021-12-16 10:06:02,099 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1141 [2021-12-16 10:06:02,104 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1278 states to 1278 states and 1894 transitions. [2021-12-16 10:06:02,105 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1278 [2021-12-16 10:06:02,106 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1278 [2021-12-16 10:06:02,106 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1278 states and 1894 transitions. [2021-12-16 10:06:02,108 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:06:02,108 INFO L681 BuchiCegarLoop]: Abstraction has 1278 states and 1894 transitions. [2021-12-16 10:06:02,109 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1278 states and 1894 transitions. [2021-12-16 10:06:02,123 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1278 to 1278. [2021-12-16 10:06:02,125 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1278 states, 1278 states have (on average 1.482003129890454) internal successors, (1894), 1277 states have internal predecessors, (1894), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:02,129 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1278 states to 1278 states and 1894 transitions. [2021-12-16 10:06:02,129 INFO L704 BuchiCegarLoop]: Abstraction has 1278 states and 1894 transitions. [2021-12-16 10:06:02,129 INFO L587 BuchiCegarLoop]: Abstraction has 1278 states and 1894 transitions. [2021-12-16 10:06:02,129 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2021-12-16 10:06:02,129 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1278 states and 1894 transitions. [2021-12-16 10:06:02,134 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1141 [2021-12-16 10:06:02,134 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:06:02,134 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:06:02,136 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:02,136 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:02,137 INFO L791 eck$LassoCheckResult]: Stem: 21500#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 21501#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 21776#L1483 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 21764#L694 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 21765#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 21785#L701-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 21786#L706-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 21069#L711-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 20787#L716-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 20788#L721-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 21694#L726-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 21695#L731-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 21680#L736-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 21681#L741-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 21716#L746-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 20839#L751-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 20840#L1006 assume !(0 == ~M_E~0); 20690#L1006-2 assume !(0 == ~T1_E~0); 20691#L1011-1 assume !(0 == ~T2_E~0); 21738#L1016-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 21753#L1021-1 assume !(0 == ~T4_E~0); 20570#L1026-1 assume !(0 == ~T5_E~0); 20571#L1031-1 assume !(0 == ~T6_E~0); 21446#L1036-1 assume !(0 == ~T7_E~0); 21442#L1041-1 assume !(0 == ~T8_E~0); 21443#L1046-1 assume !(0 == ~T9_E~0); 20872#L1051-1 assume !(0 == ~T10_E~0); 20873#L1056-1 assume 0 == ~E_1~0;~E_1~0 := 1; 21575#L1061-1 assume !(0 == ~E_2~0); 20791#L1066-1 assume !(0 == ~E_3~0); 20792#L1071-1 assume !(0 == ~E_4~0); 21554#L1076-1 assume !(0 == ~E_5~0); 20701#L1081-1 assume !(0 == ~E_6~0); 20702#L1086-1 assume !(0 == ~E_7~0); 21044#L1091-1 assume !(0 == ~E_8~0); 21730#L1096-1 assume 0 == ~E_9~0;~E_9~0 := 1; 21731#L1101-1 assume !(0 == ~E_10~0); 21106#L1106-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 21107#L484 assume !(1 == ~m_pc~0); 20750#L484-2 is_master_triggered_~__retres1~0#1 := 0; 20749#L495 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21365#L496 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 21649#L1245 assume !(0 != activate_threads_~tmp~1#1); 21650#L1245-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 21434#L503 assume 1 == ~t1_pc~0; 21435#L504 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 21451#L514 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 21567#L515 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 21217#L1253 assume !(0 != activate_threads_~tmp___0~0#1); 20600#L1253-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 20601#L522 assume !(1 == ~t2_pc~0); 21401#L522-2 is_transmit2_triggered_~__retres1~2#1 := 0; 20804#L533 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20805#L534 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 21275#L1261 assume !(0 != activate_threads_~tmp___1~0#1); 21696#L1261-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 21761#L541 assume 1 == ~t3_pc~0; 21350#L542 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 21166#L552 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 20981#L553 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 20982#L1269 assume !(0 != activate_threads_~tmp___2~0#1); 21404#L1269-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 21405#L560 assume !(1 == ~t4_pc~0); 20682#L560-2 is_transmit4_triggered_~__retres1~4#1 := 0; 20681#L571 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 21309#L572 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 20568#L1277 assume !(0 != activate_threads_~tmp___3~0#1); 20569#L1277-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 20855#L579 assume 1 == ~t5_pc~0; 20519#L580 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 20520#L590 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 20628#L591 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 21312#L1285 assume !(0 != activate_threads_~tmp___4~0#1); 21751#L1285-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 21773#L598 assume 1 == ~t6_pc~0; 20949#L599 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 20950#L609 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 21251#L610 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 21672#L1293 assume !(0 != activate_threads_~tmp___5~0#1); 21483#L1293-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 21425#L617 assume !(1 == ~t7_pc~0); 20922#L617-2 is_transmit7_triggered_~__retres1~7#1 := 0; 20921#L628 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 21207#L629 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 21208#L1301 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 21143#L1301-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 21144#L636 assume 1 == ~t8_pc~0; 21306#L637 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 21307#L647 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 21108#L648 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 21109#L1309 assume !(0 != activate_threads_~tmp___7~0#1); 21259#L1309-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 21260#L655 assume !(1 == ~t9_pc~0); 21287#L655-2 is_transmit9_triggered_~__retres1~9#1 := 0; 21288#L666 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 20901#L667 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 20902#L1317 assume !(0 != activate_threads_~tmp___8~0#1); 21502#L1317-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 21503#L674 assume 1 == ~t10_pc~0; 20677#L675 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 20678#L685 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 21763#L686 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 21794#L1325 assume !(0 != activate_threads_~tmp___9~0#1); 21249#L1325-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21250#L1119 assume !(1 == ~M_E~0); 20773#L1119-2 assume !(1 == ~T1_E~0); 20774#L1124-1 assume !(1 == ~T2_E~0); 20592#L1129-1 assume !(1 == ~T3_E~0); 20593#L1134-1 assume !(1 == ~T4_E~0); 20904#L1139-1 assume !(1 == ~T5_E~0); 20905#L1144-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 21139#L1149-1 assume !(1 == ~T7_E~0); 20768#L1154-1 assume !(1 == ~T8_E~0); 20769#L1159-1 assume !(1 == ~T9_E~0); 20856#L1164-1 assume !(1 == ~T10_E~0); 21278#L1169-1 assume !(1 == ~E_1~0); 21176#L1174-1 assume !(1 == ~E_2~0); 20963#L1179-1 assume !(1 == ~E_3~0); 20845#L1184-1 assume 1 == ~E_4~0;~E_4~0 := 2; 20846#L1189-1 assume !(1 == ~E_5~0); 20898#L1194-1 assume !(1 == ~E_6~0); 21022#L1199-1 assume !(1 == ~E_7~0); 20973#L1204-1 assume !(1 == ~E_8~0); 20974#L1209-1 assume !(1 == ~E_9~0); 21497#L1214-1 assume !(1 == ~E_10~0); 21498#L1219-1 assume { :end_inline_reset_delta_events } true; 20556#L1520-2 [2021-12-16 10:06:02,137 INFO L793 eck$LassoCheckResult]: Loop: 20556#L1520-2 assume !false; 20557#L1521 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 20657#L981 assume !false; 20849#L832 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 21524#L764 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 20542#L821 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 21642#L822 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 21692#L836 assume !(0 != eval_~tmp~0#1); 21134#L996 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 21135#L694-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 21130#L1006-3 assume 0 == ~M_E~0;~M_E~0 := 1; 21131#L1006-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 21601#L1011-3 assume !(0 == ~T2_E~0); 21602#L1016-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 21641#L1021-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 21322#L1026-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 21323#L1031-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 21569#L1036-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 21570#L1041-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 21630#L1046-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 21631#L1051-3 assume !(0 == ~T10_E~0); 21571#L1056-3 assume 0 == ~E_1~0;~E_1~0 := 1; 20867#L1061-3 assume 0 == ~E_2~0;~E_2~0 := 1; 20868#L1066-3 assume 0 == ~E_3~0;~E_3~0 := 1; 20871#L1071-3 assume 0 == ~E_4~0;~E_4~0 := 1; 21742#L1076-3 assume 0 == ~E_5~0;~E_5~0 := 1; 20654#L1081-3 assume 0 == ~E_6~0;~E_6~0 := 1; 20655#L1086-3 assume 0 == ~E_7~0;~E_7~0 := 1; 20707#L1091-3 assume !(0 == ~E_8~0); 20708#L1096-3 assume 0 == ~E_9~0;~E_9~0 := 1; 21717#L1101-3 assume 0 == ~E_10~0;~E_10~0 := 1; 21718#L1106-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 21344#L484-33 assume 1 == ~m_pc~0; 21345#L485-11 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 21264#L495-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21265#L496-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 20562#L1245-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 20563#L1245-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 21031#L503-33 assume !(1 == ~t1_pc~0); 21032#L503-35 is_transmit1_triggered_~__retres1~1#1 := 0; 21485#L514-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 21412#L515-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 20941#L1253-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 20942#L1253-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 21381#L522-33 assume 1 == ~t2_pc~0; 21382#L523-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 20695#L533-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20696#L534-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 21490#L1261-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 21399#L1261-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 21400#L541-33 assume 1 == ~t3_pc~0; 20721#L542-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 20560#L552-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 20561#L553-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 21371#L1269-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 21372#L1269-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 21566#L560-33 assume 1 == ~t4_pc~0; 21271#L561-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 20632#L571-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 20633#L572-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 20891#L1277-33 assume !(0 != activate_threads_~tmp___3~0#1); 21548#L1277-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 20551#L579-33 assume 1 == ~t5_pc~0; 20552#L580-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 20798#L590-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 21757#L591-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 21426#L1285-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 21427#L1285-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 21455#L598-33 assume !(1 == ~t6_pc~0); 21229#L598-35 is_transmit6_triggered_~__retres1~6#1 := 0; 21055#L609-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 21056#L610-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 20896#L1293-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 20897#L1293-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 21706#L617-33 assume 1 == ~t7_pc~0; 21712#L618-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 20689#L628-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 21640#L629-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 21747#L1301-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 21743#L1301-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 20620#L636-33 assume !(1 == ~t8_pc~0); 20621#L636-35 is_transmit8_triggered_~__retres1~8#1 := 0; 21540#L647-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 21541#L648-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 21766#L1309-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 21531#L1309-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 21532#L655-33 assume 1 == ~t9_pc~0; 21790#L656-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 20998#L666-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 20999#L667-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 21355#L1317-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 21619#L1317-35 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 21175#L674-33 assume 1 == ~t10_pc~0; 21050#L675-11 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 21051#L685-11 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 20912#L686-11 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 20913#L1325-33 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 21390#L1325-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21767#L1119-3 assume 1 == ~M_E~0;~M_E~0 := 2; 21774#L1119-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 21778#L1124-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 21788#L1129-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 20937#L1134-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 20938#L1139-3 assume !(1 == ~T5_E~0); 21168#L1144-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 21169#L1149-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 21311#L1154-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 21581#L1159-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 21582#L1164-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 21749#L1169-3 assume 1 == ~E_1~0;~E_1~0 := 2; 21053#L1174-3 assume 1 == ~E_2~0;~E_2~0 := 2; 21054#L1179-3 assume !(1 == ~E_3~0); 21673#L1184-3 assume 1 == ~E_4~0;~E_4~0 := 2; 20683#L1189-3 assume 1 == ~E_5~0;~E_5~0 := 2; 20684#L1194-3 assume 1 == ~E_6~0;~E_6~0 := 2; 20994#L1199-3 assume 1 == ~E_7~0;~E_7~0 := 2; 20995#L1204-3 assume 1 == ~E_8~0;~E_8~0 := 2; 21298#L1209-3 assume 1 == ~E_9~0;~E_9~0 := 2; 20574#L1214-3 assume 1 == ~E_10~0;~E_10~0 := 2; 20575#L1219-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 21489#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 20660#L821-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 21011#L822-1 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 21012#L1539 assume !(0 == start_simulation_~tmp~3#1); 21104#L1539-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 21280#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 21087#L821-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 21220#L822-2 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 21003#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 21004#L1501 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 21608#L1502 start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 21105#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 20556#L1520-2 [2021-12-16 10:06:02,138 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:02,138 INFO L85 PathProgramCache]: Analyzing trace with hash 1406784749, now seen corresponding path program 1 times [2021-12-16 10:06:02,138 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:02,138 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1168941240] [2021-12-16 10:06:02,138 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:02,138 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:02,147 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:06:02,161 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:06:02,161 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:06:02,162 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1168941240] [2021-12-16 10:06:02,162 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1168941240] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:06:02,162 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:06:02,162 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:06:02,162 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [434707648] [2021-12-16 10:06:02,162 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:06:02,163 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:06:02,163 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:02,163 INFO L85 PathProgramCache]: Analyzing trace with hash -1410939798, now seen corresponding path program 4 times [2021-12-16 10:06:02,163 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:02,164 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [718369816] [2021-12-16 10:06:02,164 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:02,164 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:02,175 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:06:02,195 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:06:02,195 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:06:02,195 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [718369816] [2021-12-16 10:06:02,195 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [718369816] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:06:02,196 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:06:02,196 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:06:02,196 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1164801802] [2021-12-16 10:06:02,196 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:06:02,196 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:06:02,197 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:06:02,197 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-16 10:06:02,197 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-16 10:06:02,198 INFO L87 Difference]: Start difference. First operand 1278 states and 1894 transitions. cyclomatic complexity: 617 Second operand has 3 states, 3 states have (on average 42.0) internal successors, (126), 3 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:02,218 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:06:02,218 INFO L93 Difference]: Finished difference Result 1278 states and 1893 transitions. [2021-12-16 10:06:02,218 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-16 10:06:02,219 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1278 states and 1893 transitions. [2021-12-16 10:06:02,226 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1141 [2021-12-16 10:06:02,231 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1278 states to 1278 states and 1893 transitions. [2021-12-16 10:06:02,231 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1278 [2021-12-16 10:06:02,232 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1278 [2021-12-16 10:06:02,232 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1278 states and 1893 transitions. [2021-12-16 10:06:02,234 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:06:02,234 INFO L681 BuchiCegarLoop]: Abstraction has 1278 states and 1893 transitions. [2021-12-16 10:06:02,236 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1278 states and 1893 transitions. [2021-12-16 10:06:02,249 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1278 to 1278. [2021-12-16 10:06:02,251 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1278 states, 1278 states have (on average 1.4812206572769953) internal successors, (1893), 1277 states have internal predecessors, (1893), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:02,255 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1278 states to 1278 states and 1893 transitions. [2021-12-16 10:06:02,255 INFO L704 BuchiCegarLoop]: Abstraction has 1278 states and 1893 transitions. [2021-12-16 10:06:02,255 INFO L587 BuchiCegarLoop]: Abstraction has 1278 states and 1893 transitions. [2021-12-16 10:06:02,255 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2021-12-16 10:06:02,256 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1278 states and 1893 transitions. [2021-12-16 10:06:02,260 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1141 [2021-12-16 10:06:02,260 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:06:02,260 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:06:02,262 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:02,262 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:02,262 INFO L791 eck$LassoCheckResult]: Stem: 24064#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 24065#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 24339#L1483 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 24327#L694 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 24328#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 24348#L701-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 24349#L706-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 23632#L711-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 23350#L716-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 23351#L721-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 24257#L726-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 24258#L731-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 24243#L736-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 24244#L741-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 24279#L746-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 23404#L751-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 23405#L1006 assume !(0 == ~M_E~0); 23253#L1006-2 assume !(0 == ~T1_E~0); 23254#L1011-1 assume !(0 == ~T2_E~0); 24301#L1016-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 24316#L1021-1 assume !(0 == ~T4_E~0); 23135#L1026-1 assume !(0 == ~T5_E~0); 23136#L1031-1 assume !(0 == ~T6_E~0); 24009#L1036-1 assume !(0 == ~T7_E~0); 24005#L1041-1 assume !(0 == ~T8_E~0); 24006#L1046-1 assume !(0 == ~T9_E~0); 23435#L1051-1 assume !(0 == ~T10_E~0); 23436#L1056-1 assume 0 == ~E_1~0;~E_1~0 := 1; 24138#L1061-1 assume !(0 == ~E_2~0); 23354#L1066-1 assume !(0 == ~E_3~0); 23355#L1071-1 assume !(0 == ~E_4~0); 24117#L1076-1 assume !(0 == ~E_5~0); 23264#L1081-1 assume !(0 == ~E_6~0); 23265#L1086-1 assume !(0 == ~E_7~0); 23608#L1091-1 assume !(0 == ~E_8~0); 24294#L1096-1 assume 0 == ~E_9~0;~E_9~0 := 1; 24295#L1101-1 assume !(0 == ~E_10~0); 23669#L1106-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 23670#L484 assume !(1 == ~m_pc~0); 23313#L484-2 is_master_triggered_~__retres1~0#1 := 0; 23312#L495 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 23928#L496 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 24212#L1245 assume !(0 != activate_threads_~tmp~1#1); 24213#L1245-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 23997#L503 assume 1 == ~t1_pc~0; 23998#L504 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 24015#L514 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 24130#L515 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 23783#L1253 assume !(0 != activate_threads_~tmp___0~0#1); 23163#L1253-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 23164#L522 assume !(1 == ~t2_pc~0); 23964#L522-2 is_transmit2_triggered_~__retres1~2#1 := 0; 23367#L533 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 23368#L534 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 23838#L1261 assume !(0 != activate_threads_~tmp___1~0#1); 24259#L1261-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 24324#L541 assume 1 == ~t3_pc~0; 23913#L542 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 23729#L552 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 23544#L553 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 23545#L1269 assume !(0 != activate_threads_~tmp___2~0#1); 23967#L1269-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 23968#L560 assume !(1 == ~t4_pc~0); 23247#L560-2 is_transmit4_triggered_~__retres1~4#1 := 0; 23246#L571 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 23872#L572 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 23131#L1277 assume !(0 != activate_threads_~tmp___3~0#1); 23132#L1277-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 23418#L579 assume 1 == ~t5_pc~0; 23082#L580 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 23083#L590 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 23191#L591 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 23875#L1285 assume !(0 != activate_threads_~tmp___4~0#1); 24315#L1285-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 24336#L598 assume 1 == ~t6_pc~0; 23512#L599 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 23513#L609 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 23815#L610 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 24235#L1293 assume !(0 != activate_threads_~tmp___5~0#1); 24046#L1293-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 23988#L617 assume !(1 == ~t7_pc~0); 23485#L617-2 is_transmit7_triggered_~__retres1~7#1 := 0; 23484#L628 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 23770#L629 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 23771#L1301 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 23706#L1301-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 23707#L636 assume 1 == ~t8_pc~0; 23869#L637 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 23870#L647 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 23671#L648 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 23672#L1309 assume !(0 != activate_threads_~tmp___7~0#1); 23824#L1309-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 23825#L655 assume !(1 == ~t9_pc~0); 23852#L655-2 is_transmit9_triggered_~__retres1~9#1 := 0; 23853#L666 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 23464#L667 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 23465#L1317 assume !(0 != activate_threads_~tmp___8~0#1); 24066#L1317-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 24067#L674 assume 1 == ~t10_pc~0; 23240#L675 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 23241#L685 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 24326#L686 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 24357#L1325 assume !(0 != activate_threads_~tmp___9~0#1); 23812#L1325-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 23813#L1119 assume !(1 == ~M_E~0); 23336#L1119-2 assume !(1 == ~T1_E~0); 23337#L1124-1 assume !(1 == ~T2_E~0); 23155#L1129-1 assume !(1 == ~T3_E~0); 23156#L1134-1 assume !(1 == ~T4_E~0); 23469#L1139-1 assume !(1 == ~T5_E~0); 23470#L1144-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 23702#L1149-1 assume !(1 == ~T7_E~0); 23331#L1154-1 assume !(1 == ~T8_E~0); 23332#L1159-1 assume !(1 == ~T9_E~0); 23419#L1164-1 assume !(1 == ~T10_E~0); 23841#L1169-1 assume !(1 == ~E_1~0); 23739#L1174-1 assume !(1 == ~E_2~0); 23526#L1179-1 assume !(1 == ~E_3~0); 23408#L1184-1 assume 1 == ~E_4~0;~E_4~0 := 2; 23409#L1189-1 assume !(1 == ~E_5~0); 23462#L1194-1 assume !(1 == ~E_6~0); 23585#L1199-1 assume !(1 == ~E_7~0); 23536#L1204-1 assume !(1 == ~E_8~0); 23537#L1209-1 assume !(1 == ~E_9~0); 24060#L1214-1 assume !(1 == ~E_10~0); 24061#L1219-1 assume { :end_inline_reset_delta_events } true; 23119#L1520-2 [2021-12-16 10:06:02,263 INFO L793 eck$LassoCheckResult]: Loop: 23119#L1520-2 assume !false; 23120#L1521 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 23223#L981 assume !false; 23415#L832 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 24087#L764 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 23105#L821 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 24205#L822 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 24255#L836 assume !(0 != eval_~tmp~0#1); 23697#L996 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 23698#L694-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 23693#L1006-3 assume 0 == ~M_E~0;~M_E~0 := 1; 23694#L1006-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 24164#L1011-3 assume !(0 == ~T2_E~0); 24165#L1016-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 24204#L1021-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 23887#L1026-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 23888#L1031-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 24132#L1036-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 24133#L1041-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 24195#L1046-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 24196#L1051-3 assume !(0 == ~T10_E~0); 24134#L1056-3 assume 0 == ~E_1~0;~E_1~0 := 1; 23432#L1061-3 assume 0 == ~E_2~0;~E_2~0 := 1; 23433#L1066-3 assume 0 == ~E_3~0;~E_3~0 := 1; 23434#L1071-3 assume 0 == ~E_4~0;~E_4~0 := 1; 24305#L1076-3 assume 0 == ~E_5~0;~E_5~0 := 1; 23217#L1081-3 assume 0 == ~E_6~0;~E_6~0 := 1; 23218#L1086-3 assume 0 == ~E_7~0;~E_7~0 := 1; 23272#L1091-3 assume !(0 == ~E_8~0); 23273#L1096-3 assume 0 == ~E_9~0;~E_9~0 := 1; 24280#L1101-3 assume 0 == ~E_10~0;~E_10~0 := 1; 24281#L1106-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 23907#L484-33 assume 1 == ~m_pc~0; 23908#L485-11 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 23827#L495-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 23828#L496-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 23125#L1245-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 23126#L1245-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 23597#L503-33 assume !(1 == ~t1_pc~0); 23598#L503-35 is_transmit1_triggered_~__retres1~1#1 := 0; 24048#L514-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 23977#L515-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 23504#L1253-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 23505#L1253-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 23944#L522-33 assume 1 == ~t2_pc~0; 23945#L523-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 23260#L533-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 23261#L534-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 24054#L1261-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 23962#L1261-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 23963#L541-33 assume 1 == ~t3_pc~0; 23284#L542-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 23123#L552-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 23124#L553-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 23934#L1269-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 23935#L1269-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 24129#L560-33 assume 1 == ~t4_pc~0; 23834#L561-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 23195#L571-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 23196#L572-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 23452#L1277-33 assume !(0 != activate_threads_~tmp___3~0#1); 24111#L1277-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 23111#L579-33 assume 1 == ~t5_pc~0; 23112#L580-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 23360#L590-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 24320#L591-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 23989#L1285-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 23990#L1285-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 24014#L598-33 assume 1 == ~t6_pc~0; 24321#L599-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 23618#L609-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 23619#L610-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 23459#L1293-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 23460#L1293-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 24269#L617-33 assume 1 == ~t7_pc~0; 24275#L618-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 23252#L628-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 24203#L629-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 24310#L1301-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 24306#L1301-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 23183#L636-33 assume !(1 == ~t8_pc~0); 23184#L636-35 is_transmit8_triggered_~__retres1~8#1 := 0; 24103#L647-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 24104#L648-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 24329#L1309-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 24092#L1309-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 24093#L655-33 assume 1 == ~t9_pc~0; 24353#L656-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 23559#L666-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 23560#L667-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 23918#L1317-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 24182#L1317-35 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 23738#L674-33 assume 1 == ~t10_pc~0; 23613#L675-11 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 23614#L685-11 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 23475#L686-11 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 23476#L1325-33 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 23953#L1325-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 24330#L1119-3 assume 1 == ~M_E~0;~M_E~0 := 2; 24337#L1119-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 24340#L1124-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 24351#L1129-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 23497#L1134-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 23498#L1139-3 assume !(1 == ~T5_E~0); 23731#L1144-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 23732#L1149-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 23874#L1154-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 24144#L1159-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 24145#L1164-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 24311#L1169-3 assume 1 == ~E_1~0;~E_1~0 := 2; 23616#L1174-3 assume 1 == ~E_2~0;~E_2~0 := 2; 23617#L1179-3 assume !(1 == ~E_3~0); 24236#L1184-3 assume 1 == ~E_4~0;~E_4~0 := 2; 23243#L1189-3 assume 1 == ~E_5~0;~E_5~0 := 2; 23244#L1194-3 assume 1 == ~E_6~0;~E_6~0 := 2; 23557#L1199-3 assume 1 == ~E_7~0;~E_7~0 := 2; 23558#L1204-3 assume 1 == ~E_8~0;~E_8~0 := 2; 23861#L1209-3 assume 1 == ~E_9~0;~E_9~0 := 2; 23137#L1214-3 assume 1 == ~E_10~0;~E_10~0 := 2; 23138#L1219-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 24051#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 23220#L821-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 23574#L822-1 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 23575#L1539 assume !(0 == start_simulation_~tmp~3#1); 23667#L1539-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 23843#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 23650#L821-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 23782#L822-2 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 23566#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 23567#L1501 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 24171#L1502 start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 23668#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 23119#L1520-2 [2021-12-16 10:06:02,263 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:02,264 INFO L85 PathProgramCache]: Analyzing trace with hash 935428399, now seen corresponding path program 1 times [2021-12-16 10:06:02,264 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:02,264 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [406505536] [2021-12-16 10:06:02,264 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:02,264 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:02,275 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:06:02,298 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:06:02,298 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:06:02,298 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [406505536] [2021-12-16 10:06:02,298 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [406505536] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:06:02,298 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:06:02,299 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:06:02,299 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [992051496] [2021-12-16 10:06:02,299 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:06:02,299 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:06:02,300 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:02,300 INFO L85 PathProgramCache]: Analyzing trace with hash -2115858485, now seen corresponding path program 2 times [2021-12-16 10:06:02,300 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:02,300 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [654086291] [2021-12-16 10:06:02,300 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:02,301 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:02,325 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:06:02,345 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:06:02,346 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:06:02,346 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [654086291] [2021-12-16 10:06:02,346 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [654086291] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:06:02,346 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:06:02,346 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:06:02,347 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [549516565] [2021-12-16 10:06:02,347 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:06:02,347 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:06:02,347 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:06:02,348 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-16 10:06:02,348 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-16 10:06:02,348 INFO L87 Difference]: Start difference. First operand 1278 states and 1893 transitions. cyclomatic complexity: 616 Second operand has 4 states, 4 states have (on average 31.5) internal successors, (126), 3 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:02,479 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:06:02,479 INFO L93 Difference]: Finished difference Result 2340 states and 3454 transitions. [2021-12-16 10:06:02,479 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-16 10:06:02,480 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2340 states and 3454 transitions. [2021-12-16 10:06:02,493 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2182 [2021-12-16 10:06:02,503 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2340 states to 2340 states and 3454 transitions. [2021-12-16 10:06:02,503 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2340 [2021-12-16 10:06:02,505 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2340 [2021-12-16 10:06:02,505 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2340 states and 3454 transitions. [2021-12-16 10:06:02,508 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:06:02,508 INFO L681 BuchiCegarLoop]: Abstraction has 2340 states and 3454 transitions. [2021-12-16 10:06:02,510 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2340 states and 3454 transitions. [2021-12-16 10:06:02,538 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2340 to 2340. [2021-12-16 10:06:02,542 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2340 states, 2340 states have (on average 1.4760683760683762) internal successors, (3454), 2339 states have internal predecessors, (3454), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:02,549 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2340 states to 2340 states and 3454 transitions. [2021-12-16 10:06:02,550 INFO L704 BuchiCegarLoop]: Abstraction has 2340 states and 3454 transitions. [2021-12-16 10:06:02,550 INFO L587 BuchiCegarLoop]: Abstraction has 2340 states and 3454 transitions. [2021-12-16 10:06:02,550 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2021-12-16 10:06:02,550 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2340 states and 3454 transitions. [2021-12-16 10:06:02,559 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2182 [2021-12-16 10:06:02,559 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:06:02,559 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:06:02,561 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:02,561 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:02,561 INFO L791 eck$LassoCheckResult]: Stem: 27702#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 27703#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 27999#L1483 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 27985#L694 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 27986#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 28010#L701-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 28011#L706-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 27267#L711-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 26983#L716-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 26984#L721-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 27903#L726-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 27904#L731-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 27886#L736-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 27887#L741-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 27927#L746-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 27035#L751-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 27036#L1006 assume !(0 == ~M_E~0); 26885#L1006-2 assume !(0 == ~T1_E~0); 26886#L1011-1 assume !(0 == ~T2_E~0); 27953#L1016-1 assume !(0 == ~T3_E~0); 27973#L1021-1 assume !(0 == ~T4_E~0); 26763#L1026-1 assume !(0 == ~T5_E~0); 26764#L1031-1 assume !(0 == ~T6_E~0); 27649#L1036-1 assume !(0 == ~T7_E~0); 27643#L1041-1 assume !(0 == ~T8_E~0); 27644#L1046-1 assume !(0 == ~T9_E~0); 27066#L1051-1 assume !(0 == ~T10_E~0); 27067#L1056-1 assume 0 == ~E_1~0;~E_1~0 := 1; 27776#L1061-1 assume !(0 == ~E_2~0); 26985#L1066-1 assume !(0 == ~E_3~0); 26986#L1071-1 assume !(0 == ~E_4~0); 27755#L1076-1 assume !(0 == ~E_5~0); 26893#L1081-1 assume !(0 == ~E_6~0); 26894#L1086-1 assume !(0 == ~E_7~0); 27243#L1091-1 assume !(0 == ~E_8~0); 27942#L1096-1 assume 0 == ~E_9~0;~E_9~0 := 1; 27943#L1101-1 assume !(0 == ~E_10~0); 27304#L1106-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 27305#L484 assume !(1 == ~m_pc~0); 26944#L484-2 is_master_triggered_~__retres1~0#1 := 0; 26943#L495 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 27566#L496 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 27854#L1245 assume !(0 != activate_threads_~tmp~1#1); 27855#L1245-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 27635#L503 assume 1 == ~t1_pc~0; 27636#L504 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 27656#L514 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 27768#L515 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 27419#L1253 assume !(0 != activate_threads_~tmp___0~0#1); 26794#L1253-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 26795#L522 assume !(1 == ~t2_pc~0); 27602#L522-2 is_transmit2_triggered_~__retres1~2#1 := 0; 26999#L533 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 27000#L534 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 27474#L1261 assume !(0 != activate_threads_~tmp___1~0#1); 27905#L1261-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 27982#L541 assume 1 == ~t3_pc~0; 27553#L542 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 27364#L552 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 27177#L553 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 27178#L1269 assume !(0 != activate_threads_~tmp___2~0#1); 27609#L1269-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 27610#L560 assume !(1 == ~t4_pc~0); 26876#L560-2 is_transmit4_triggered_~__retres1~4#1 := 0; 26875#L571 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 27508#L572 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 26759#L1277 assume !(0 != activate_threads_~tmp___3~0#1); 26760#L1277-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 27049#L579 assume 1 == ~t5_pc~0; 26710#L580 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 26711#L590 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 26820#L591 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 27511#L1285 assume !(0 != activate_threads_~tmp___4~0#1); 27972#L1285-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 27995#L598 assume 1 == ~t6_pc~0; 27147#L599 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 27148#L609 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 27453#L610 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 27878#L1293 assume !(0 != activate_threads_~tmp___5~0#1); 27684#L1293-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 27626#L617 assume !(1 == ~t7_pc~0); 27117#L617-2 is_transmit7_triggered_~__retres1~7#1 := 0; 27116#L628 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 27406#L629 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 27407#L1301 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 27342#L1301-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 27343#L636 assume 1 == ~t8_pc~0; 27505#L637 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 27506#L647 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 27306#L648 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 27307#L1309 assume !(0 != activate_threads_~tmp___7~0#1); 27460#L1309-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 27461#L655 assume !(1 == ~t9_pc~0); 27490#L655-2 is_transmit9_triggered_~__retres1~9#1 := 0; 27491#L666 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 27096#L667 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 27097#L1317 assume !(0 != activate_threads_~tmp___8~0#1); 27704#L1317-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 27705#L674 assume 1 == ~t10_pc~0; 26869#L675 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 26870#L685 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 27984#L686 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 28020#L1325 assume !(0 != activate_threads_~tmp___9~0#1); 27448#L1325-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 27449#L1119 assume 1 == ~M_E~0;~M_E~0 := 2; 27913#L1119-2 assume !(1 == ~T1_E~0); 28465#L1124-1 assume !(1 == ~T2_E~0); 28127#L1129-1 assume !(1 == ~T3_E~0); 26784#L1134-1 assume !(1 == ~T4_E~0); 28114#L1139-1 assume !(1 == ~T5_E~0); 28112#L1144-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 28111#L1149-1 assume !(1 == ~T7_E~0); 28109#L1154-1 assume !(1 == ~T8_E~0); 28107#L1159-1 assume !(1 == ~T9_E~0); 28105#L1164-1 assume !(1 == ~T10_E~0); 28103#L1169-1 assume !(1 == ~E_1~0); 28100#L1174-1 assume !(1 == ~E_2~0); 28098#L1179-1 assume !(1 == ~E_3~0); 28096#L1184-1 assume 1 == ~E_4~0;~E_4~0 := 2; 28094#L1189-1 assume !(1 == ~E_5~0); 28087#L1194-1 assume !(1 == ~E_6~0); 28086#L1199-1 assume !(1 == ~E_7~0); 28085#L1204-1 assume !(1 == ~E_8~0); 28076#L1209-1 assume !(1 == ~E_9~0); 28064#L1214-1 assume !(1 == ~E_10~0); 28055#L1219-1 assume { :end_inline_reset_delta_events } true; 28049#L1520-2 [2021-12-16 10:06:02,562 INFO L793 eck$LassoCheckResult]: Loop: 28049#L1520-2 assume !false; 28044#L1521 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 28042#L981 assume !false; 28041#L832 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 28032#L764 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 28029#L821 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 28028#L822 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 28027#L836 assume !(0 != eval_~tmp~0#1); 28026#L996 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 28025#L694-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 28024#L1006-3 assume 0 == ~M_E~0;~M_E~0 := 1; 27948#L1006-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 27803#L1011-3 assume !(0 == ~T2_E~0); 27804#L1016-3 assume !(0 == ~T3_E~0); 27845#L1021-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 27521#L1026-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 27522#L1031-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 27770#L1036-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 27771#L1041-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 27834#L1046-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 27835#L1051-3 assume !(0 == ~T10_E~0); 27772#L1056-3 assume 0 == ~E_1~0;~E_1~0 := 1; 27061#L1061-3 assume 0 == ~E_2~0;~E_2~0 := 1; 27062#L1066-3 assume 0 == ~E_3~0;~E_3~0 := 1; 27065#L1071-3 assume 0 == ~E_4~0;~E_4~0 := 1; 27958#L1076-3 assume 0 == ~E_5~0;~E_5~0 := 1; 26846#L1081-3 assume 0 == ~E_6~0;~E_6~0 := 1; 26847#L1086-3 assume 0 == ~E_7~0;~E_7~0 := 1; 26899#L1091-3 assume !(0 == ~E_8~0); 26900#L1096-3 assume 0 == ~E_9~0;~E_9~0 := 1; 27928#L1101-3 assume 0 == ~E_10~0;~E_10~0 := 1; 27929#L1106-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 27545#L484-33 assume 1 == ~m_pc~0; 27546#L485-11 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 27463#L495-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 27464#L496-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 26753#L1245-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 26754#L1245-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 27229#L503-33 assume !(1 == ~t1_pc~0); 27230#L503-35 is_transmit1_triggered_~__retres1~1#1 := 0; 27686#L514-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 27613#L515-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 27137#L1253-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 27138#L1253-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 27582#L522-33 assume !(1 == ~t2_pc~0); 27584#L522-35 is_transmit2_triggered_~__retres1~2#1 := 0; 26887#L533-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 26888#L534-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 27691#L1261-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 27600#L1261-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 27601#L541-33 assume 1 == ~t3_pc~0; 26913#L542-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 26751#L552-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 26752#L553-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 27572#L1269-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 27573#L1269-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 27767#L560-33 assume 1 == ~t4_pc~0; 27470#L561-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 26824#L571-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 26825#L572-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 27085#L1277-33 assume !(0 != activate_threads_~tmp___3~0#1); 27749#L1277-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 26742#L579-33 assume 1 == ~t5_pc~0; 26743#L580-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 26992#L590-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 27977#L591-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 27627#L1285-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 27628#L1285-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 27655#L598-33 assume !(1 == ~t6_pc~0); 27428#L598-35 is_transmit6_triggered_~__retres1~6#1 := 0; 27253#L609-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 27254#L610-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 27090#L1293-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 27091#L1293-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 27917#L617-33 assume !(1 == ~t7_pc~0); 26880#L617-35 is_transmit7_triggered_~__retres1~7#1 := 0; 26881#L628-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 27844#L629-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 27964#L1301-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 27960#L1301-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 26812#L636-33 assume !(1 == ~t8_pc~0); 26813#L636-35 is_transmit8_triggered_~__retres1~8#1 := 0; 27741#L647-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 27742#L648-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 27987#L1309-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 27732#L1309-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 27733#L655-33 assume 1 == ~t9_pc~0; 28016#L656-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 27194#L666-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 27195#L667-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 27556#L1317-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 27821#L1317-35 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 27373#L674-33 assume 1 == ~t10_pc~0; 27248#L675-11 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 27249#L685-11 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 28299#L686-11 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 28296#L1325-33 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 28294#L1325-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 28292#L1119-3 assume 1 == ~M_E~0;~M_E~0 := 2; 27996#L1119-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 28289#L1124-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 28287#L1129-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 28014#L1134-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 28283#L1139-3 assume !(1 == ~T5_E~0); 28281#L1144-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 28279#L1149-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 28277#L1154-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 28275#L1159-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 28272#L1164-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 28270#L1169-3 assume 1 == ~E_1~0;~E_1~0 := 2; 28268#L1174-3 assume 1 == ~E_2~0;~E_2~0 := 2; 28266#L1179-3 assume !(1 == ~E_3~0); 28264#L1184-3 assume 1 == ~E_4~0;~E_4~0 := 2; 28262#L1189-3 assume 1 == ~E_5~0;~E_5~0 := 2; 28259#L1194-3 assume 1 == ~E_6~0;~E_6~0 := 2; 28257#L1199-3 assume 1 == ~E_7~0;~E_7~0 := 2; 28255#L1204-3 assume 1 == ~E_8~0;~E_8~0 := 2; 28253#L1209-3 assume 1 == ~E_9~0;~E_9~0 := 2; 28251#L1214-3 assume 1 == ~E_10~0;~E_10~0 := 2; 28249#L1219-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 28221#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 28219#L821-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 28217#L822-1 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 28215#L1539 assume !(0 == start_simulation_~tmp~3#1); 27889#L1539-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 28120#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 28115#L821-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 28113#L822-2 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 28088#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 28077#L1501 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 28065#L1502 start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 28056#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 28049#L1520-2 [2021-12-16 10:06:02,562 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:02,562 INFO L85 PathProgramCache]: Analyzing trace with hash -1425286797, now seen corresponding path program 1 times [2021-12-16 10:06:02,562 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:02,563 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [927774564] [2021-12-16 10:06:02,563 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:02,563 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:02,573 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:06:02,591 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:06:02,591 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:06:02,591 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [927774564] [2021-12-16 10:06:02,592 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [927774564] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:06:02,592 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:06:02,592 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-16 10:06:02,592 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1956290259] [2021-12-16 10:06:02,592 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:06:02,593 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:06:02,593 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:02,593 INFO L85 PathProgramCache]: Analyzing trace with hash 1662402154, now seen corresponding path program 1 times [2021-12-16 10:06:02,593 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:02,594 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [939214335] [2021-12-16 10:06:02,594 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:02,594 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:02,604 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:06:02,629 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:06:02,629 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:06:02,630 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [939214335] [2021-12-16 10:06:02,630 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [939214335] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:06:02,630 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:06:02,630 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:06:02,630 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1834521367] [2021-12-16 10:06:02,630 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:06:02,630 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:06:02,631 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:06:02,631 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-16 10:06:02,631 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-16 10:06:02,632 INFO L87 Difference]: Start difference. First operand 2340 states and 3454 transitions. cyclomatic complexity: 1116 Second operand has 3 states, 3 states have (on average 42.0) internal successors, (126), 2 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:02,686 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:06:02,686 INFO L93 Difference]: Finished difference Result 2340 states and 3424 transitions. [2021-12-16 10:06:02,686 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-16 10:06:02,687 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2340 states and 3424 transitions. [2021-12-16 10:06:02,703 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2182 [2021-12-16 10:06:02,712 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2340 states to 2340 states and 3424 transitions. [2021-12-16 10:06:02,712 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2340 [2021-12-16 10:06:02,714 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2340 [2021-12-16 10:06:02,714 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2340 states and 3424 transitions. [2021-12-16 10:06:02,716 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:06:02,716 INFO L681 BuchiCegarLoop]: Abstraction has 2340 states and 3424 transitions. [2021-12-16 10:06:02,718 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2340 states and 3424 transitions. [2021-12-16 10:06:02,743 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2340 to 2340. [2021-12-16 10:06:02,747 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2340 states, 2340 states have (on average 1.4632478632478632) internal successors, (3424), 2339 states have internal predecessors, (3424), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:02,754 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2340 states to 2340 states and 3424 transitions. [2021-12-16 10:06:02,754 INFO L704 BuchiCegarLoop]: Abstraction has 2340 states and 3424 transitions. [2021-12-16 10:06:02,754 INFO L587 BuchiCegarLoop]: Abstraction has 2340 states and 3424 transitions. [2021-12-16 10:06:02,754 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2021-12-16 10:06:02,754 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2340 states and 3424 transitions. [2021-12-16 10:06:02,763 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2182 [2021-12-16 10:06:02,763 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:06:02,763 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:06:02,765 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:02,765 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:02,766 INFO L791 eck$LassoCheckResult]: Stem: 32385#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 32386#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 32690#L1483 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 32676#L694 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 32677#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 32704#L701-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 32705#L706-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 31949#L711-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 31666#L716-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 31667#L721-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 32587#L726-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 32588#L731-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 32572#L736-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 32573#L741-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 32613#L746-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 31718#L751-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 31719#L1006 assume !(0 == ~M_E~0); 31569#L1006-2 assume !(0 == ~T1_E~0); 31570#L1011-1 assume !(0 == ~T2_E~0); 32643#L1016-1 assume !(0 == ~T3_E~0); 32662#L1021-1 assume !(0 == ~T4_E~0); 31448#L1026-1 assume !(0 == ~T5_E~0); 31449#L1031-1 assume !(0 == ~T6_E~0); 32331#L1036-1 assume !(0 == ~T7_E~0); 32327#L1041-1 assume !(0 == ~T8_E~0); 32328#L1046-1 assume !(0 == ~T9_E~0); 31751#L1051-1 assume !(0 == ~T10_E~0); 31752#L1056-1 assume !(0 == ~E_1~0); 32462#L1061-1 assume !(0 == ~E_2~0); 31670#L1066-1 assume !(0 == ~E_3~0); 31671#L1071-1 assume !(0 == ~E_4~0); 32440#L1076-1 assume !(0 == ~E_5~0); 31580#L1081-1 assume !(0 == ~E_6~0); 31581#L1086-1 assume !(0 == ~E_7~0); 31922#L1091-1 assume !(0 == ~E_8~0); 32627#L1096-1 assume 0 == ~E_9~0;~E_9~0 := 1; 32628#L1101-1 assume !(0 == ~E_10~0); 31986#L1106-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 31987#L484 assume !(1 == ~m_pc~0); 31629#L484-2 is_master_triggered_~__retres1~0#1 := 0; 31628#L495 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 32246#L496 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 32541#L1245 assume !(0 != activate_threads_~tmp~1#1); 32542#L1245-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 32319#L503 assume !(1 == ~t1_pc~0); 32321#L503-2 is_transmit1_triggered_~__retres1~1#1 := 0; 32492#L514 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 32454#L515 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 32098#L1253 assume !(0 != activate_threads_~tmp___0~0#1); 31479#L1253-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 31480#L522 assume !(1 == ~t2_pc~0); 32283#L522-2 is_transmit2_triggered_~__retres1~2#1 := 0; 31683#L533 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 31684#L534 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 32156#L1261 assume !(0 != activate_threads_~tmp___1~0#1); 32589#L1261-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 32670#L541 assume 1 == ~t3_pc~0; 32231#L542 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 32046#L552 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 31860#L553 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 31861#L1269 assume !(0 != activate_threads_~tmp___2~0#1); 32286#L1269-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 32287#L560 assume !(1 == ~t4_pc~0); 31561#L560-2 is_transmit4_triggered_~__retres1~4#1 := 0; 31560#L571 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 32190#L572 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 31446#L1277 assume !(0 != activate_threads_~tmp___3~0#1); 31447#L1277-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 31732#L579 assume 1 == ~t5_pc~0; 31397#L580 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 31398#L590 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 31507#L591 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 32193#L1285 assume !(0 != activate_threads_~tmp___4~0#1); 32660#L1285-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 32687#L598 assume 1 == ~t6_pc~0; 31827#L599 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 31828#L609 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 32132#L610 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 32564#L1293 assume !(0 != activate_threads_~tmp___5~0#1); 32368#L1293-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 32310#L617 assume !(1 == ~t7_pc~0); 31802#L617-2 is_transmit7_triggered_~__retres1~7#1 := 0; 31801#L628 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 32087#L629 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 32088#L1301 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 32023#L1301-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 32024#L636 assume 1 == ~t8_pc~0; 32187#L637 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 32188#L647 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 31988#L648 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 31989#L1309 assume !(0 != activate_threads_~tmp___7~0#1); 32140#L1309-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 32141#L655 assume !(1 == ~t9_pc~0); 32169#L655-2 is_transmit9_triggered_~__retres1~9#1 := 0; 32170#L666 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 31781#L667 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 31782#L1317 assume !(0 != activate_threads_~tmp___8~0#1); 32387#L1317-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 32388#L674 assume 1 == ~t10_pc~0; 31556#L675 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 31557#L685 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 32674#L686 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 32716#L1325 assume !(0 != activate_threads_~tmp___9~0#1); 32130#L1325-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 32131#L1119 assume 1 == ~M_E~0;~M_E~0 := 2; 32596#L1119-2 assume !(1 == ~T1_E~0); 33538#L1124-1 assume !(1 == ~T2_E~0); 33537#L1129-1 assume !(1 == ~T3_E~0); 31471#L1134-1 assume !(1 == ~T4_E~0); 33536#L1139-1 assume !(1 == ~T5_E~0); 33535#L1144-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 33534#L1149-1 assume !(1 == ~T7_E~0); 33533#L1154-1 assume !(1 == ~T8_E~0); 33532#L1159-1 assume !(1 == ~T9_E~0); 33092#L1164-1 assume !(1 == ~T10_E~0); 32788#L1169-1 assume !(1 == ~E_1~0); 32785#L1174-1 assume !(1 == ~E_2~0); 32783#L1179-1 assume !(1 == ~E_3~0); 32782#L1184-1 assume 1 == ~E_4~0;~E_4~0 := 2; 32770#L1189-1 assume !(1 == ~E_5~0); 32768#L1194-1 assume !(1 == ~E_6~0); 32766#L1199-1 assume !(1 == ~E_7~0); 32764#L1204-1 assume !(1 == ~E_8~0); 32762#L1209-1 assume !(1 == ~E_9~0); 32760#L1214-1 assume !(1 == ~E_10~0); 32754#L1219-1 assume { :end_inline_reset_delta_events } true; 32748#L1520-2 [2021-12-16 10:06:02,766 INFO L793 eck$LassoCheckResult]: Loop: 32748#L1520-2 assume !false; 32743#L1521 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 32741#L981 assume !false; 32740#L832 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 32731#L764 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 32728#L821 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 32727#L822 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 32725#L836 assume !(0 != eval_~tmp~0#1); 32724#L996 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 32723#L694-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 32721#L1006-3 assume 0 == ~M_E~0;~M_E~0 := 1; 32722#L1006-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 33172#L1011-3 assume !(0 == ~T2_E~0); 33170#L1016-3 assume !(0 == ~T3_E~0); 33169#L1021-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 33168#L1026-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 33165#L1031-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 33163#L1036-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 33161#L1041-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 33160#L1046-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 33153#L1051-3 assume !(0 == ~T10_E~0); 33150#L1056-3 assume !(0 == ~E_1~0); 33148#L1061-3 assume 0 == ~E_2~0;~E_2~0 := 1; 33144#L1066-3 assume 0 == ~E_3~0;~E_3~0 := 1; 33143#L1071-3 assume 0 == ~E_4~0;~E_4~0 := 1; 33142#L1076-3 assume 0 == ~E_5~0;~E_5~0 := 1; 33141#L1081-3 assume 0 == ~E_6~0;~E_6~0 := 1; 33140#L1086-3 assume 0 == ~E_7~0;~E_7~0 := 1; 33139#L1091-3 assume !(0 == ~E_8~0); 33138#L1096-3 assume 0 == ~E_9~0;~E_9~0 := 1; 33137#L1101-3 assume 0 == ~E_10~0;~E_10~0 := 1; 33136#L1106-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 33135#L484-33 assume 1 == ~m_pc~0; 33133#L485-11 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 33132#L495-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 33131#L496-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 33130#L1245-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 33129#L1245-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 33127#L503-33 assume !(1 == ~t1_pc~0); 33126#L503-35 is_transmit1_triggered_~__retres1~1#1 := 0; 33125#L514-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 33124#L515-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 33123#L1253-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 33122#L1253-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 33121#L522-33 assume !(1 == ~t2_pc~0); 33120#L522-35 is_transmit2_triggered_~__retres1~2#1 := 0; 33118#L533-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 33117#L534-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 33116#L1261-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 33115#L1261-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 33114#L541-33 assume !(1 == ~t3_pc~0); 33112#L541-35 is_transmit3_triggered_~__retres1~3#1 := 0; 33111#L552-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 33110#L553-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 33109#L1269-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 33108#L1269-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 33107#L560-33 assume 1 == ~t4_pc~0; 33105#L561-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 33104#L571-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 33103#L572-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 33102#L1277-33 assume !(0 != activate_threads_~tmp___3~0#1); 33101#L1277-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 33100#L579-33 assume 1 == ~t5_pc~0; 33098#L580-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 33097#L590-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 33096#L591-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 33095#L1285-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 33094#L1285-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 33093#L598-33 assume !(1 == ~t6_pc~0); 33088#L598-35 is_transmit6_triggered_~__retres1~6#1 := 0; 33086#L609-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 33084#L610-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 33082#L1293-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 33080#L1293-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 33078#L617-33 assume 1 == ~t7_pc~0; 33074#L618-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 33072#L628-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 33070#L629-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 33068#L1301-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 32649#L1301-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 31499#L636-33 assume !(1 == ~t8_pc~0); 31500#L636-35 is_transmit8_triggered_~__retres1~8#1 := 0; 32425#L647-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 32426#L648-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 32678#L1309-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 32416#L1309-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 32417#L655-33 assume 1 == ~t9_pc~0; 32709#L656-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 31877#L666-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 31878#L667-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 32236#L1317-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 32509#L1317-35 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 32055#L674-33 assume 1 == ~t10_pc~0; 31930#L675-11 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 31931#L685-11 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 31792#L686-11 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 31793#L1325-33 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 32272#L1325-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 32680#L1119-3 assume 1 == ~M_E~0;~M_E~0 := 2; 32688#L1119-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 32692#L1124-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 32707#L1129-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 31816#L1134-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 31817#L1139-3 assume !(1 == ~T5_E~0); 33013#L1144-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 33011#L1149-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 33009#L1154-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 33006#L1159-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 33004#L1164-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 33002#L1169-3 assume !(1 == ~E_1~0); 33000#L1174-3 assume 1 == ~E_2~0;~E_2~0 := 2; 32998#L1179-3 assume !(1 == ~E_3~0); 32996#L1184-3 assume 1 == ~E_4~0;~E_4~0 := 2; 32993#L1189-3 assume 1 == ~E_5~0;~E_5~0 := 2; 32991#L1194-3 assume 1 == ~E_6~0;~E_6~0 := 2; 32989#L1199-3 assume 1 == ~E_7~0;~E_7~0 := 2; 32987#L1204-3 assume 1 == ~E_8~0;~E_8~0 := 2; 32985#L1209-3 assume 1 == ~E_9~0;~E_9~0 := 2; 32983#L1214-3 assume 1 == ~E_10~0;~E_10~0 := 2; 32980#L1219-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 32960#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 32958#L821-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 32956#L822-1 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 32954#L1539 assume !(0 == start_simulation_~tmp~3#1); 32575#L1539-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 32775#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 32769#L821-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 32767#L822-2 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 32765#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 32763#L1501 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 32761#L1502 start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 32755#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 32748#L1520-2 [2021-12-16 10:06:02,766 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:02,767 INFO L85 PathProgramCache]: Analyzing trace with hash 1915892692, now seen corresponding path program 1 times [2021-12-16 10:06:02,767 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:02,767 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2025259657] [2021-12-16 10:06:02,767 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:02,767 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:02,778 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:06:02,815 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:06:02,816 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:06:02,816 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2025259657] [2021-12-16 10:06:02,816 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2025259657] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:06:02,818 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:06:02,818 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:06:02,819 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [114606795] [2021-12-16 10:06:02,820 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:06:02,820 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:06:02,820 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:02,820 INFO L85 PathProgramCache]: Analyzing trace with hash 1661386862, now seen corresponding path program 1 times [2021-12-16 10:06:02,821 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:02,821 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [315314270] [2021-12-16 10:06:02,821 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:02,822 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:02,833 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:06:02,855 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:06:02,855 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:06:02,856 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [315314270] [2021-12-16 10:06:02,856 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [315314270] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:06:02,856 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:06:02,856 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:06:02,856 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1197426251] [2021-12-16 10:06:02,856 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:06:02,857 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:06:02,857 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:06:02,857 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-16 10:06:02,857 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-16 10:06:02,858 INFO L87 Difference]: Start difference. First operand 2340 states and 3424 transitions. cyclomatic complexity: 1086 Second operand has 4 states, 4 states have (on average 31.5) internal successors, (126), 3 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:03,035 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:06:03,035 INFO L93 Difference]: Finished difference Result 4286 states and 6258 transitions. [2021-12-16 10:06:03,036 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-16 10:06:03,037 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4286 states and 6258 transitions. [2021-12-16 10:06:03,062 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4106 [2021-12-16 10:06:03,090 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4286 states to 4286 states and 6258 transitions. [2021-12-16 10:06:03,090 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4286 [2021-12-16 10:06:03,093 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4286 [2021-12-16 10:06:03,093 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4286 states and 6258 transitions. [2021-12-16 10:06:03,099 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:06:03,099 INFO L681 BuchiCegarLoop]: Abstraction has 4286 states and 6258 transitions. [2021-12-16 10:06:03,102 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4286 states and 6258 transitions. [2021-12-16 10:06:03,154 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4286 to 4284. [2021-12-16 10:06:03,174 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4284 states, 4284 states have (on average 1.4603174603174602) internal successors, (6256), 4283 states have internal predecessors, (6256), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:03,189 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4284 states to 4284 states and 6256 transitions. [2021-12-16 10:06:03,190 INFO L704 BuchiCegarLoop]: Abstraction has 4284 states and 6256 transitions. [2021-12-16 10:06:03,190 INFO L587 BuchiCegarLoop]: Abstraction has 4284 states and 6256 transitions. [2021-12-16 10:06:03,190 INFO L425 BuchiCegarLoop]: ======== Iteration 13============ [2021-12-16 10:06:03,190 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4284 states and 6256 transitions. [2021-12-16 10:06:03,205 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4106 [2021-12-16 10:06:03,206 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:06:03,206 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:06:03,207 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:03,208 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:03,208 INFO L791 eck$LassoCheckResult]: Stem: 39045#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 39046#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 39370#L1483 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 39348#L694 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 39349#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 39390#L701-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 39391#L706-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 38591#L711-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 38305#L716-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 38306#L721-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 39262#L726-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 39263#L731-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 39246#L736-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 39247#L741-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 39287#L746-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 38357#L751-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 38358#L1006 assume !(0 == ~M_E~0); 38206#L1006-2 assume !(0 == ~T1_E~0); 38207#L1011-1 assume !(0 == ~T2_E~0); 39317#L1016-1 assume !(0 == ~T3_E~0); 39337#L1021-1 assume !(0 == ~T4_E~0); 38084#L1026-1 assume !(0 == ~T5_E~0); 38085#L1031-1 assume !(0 == ~T6_E~0); 38986#L1036-1 assume !(0 == ~T7_E~0); 38982#L1041-1 assume !(0 == ~T8_E~0); 38983#L1046-1 assume !(0 == ~T9_E~0); 38391#L1051-1 assume !(0 == ~T10_E~0); 38392#L1056-1 assume !(0 == ~E_1~0); 39128#L1061-1 assume !(0 == ~E_2~0); 38309#L1066-1 assume !(0 == ~E_3~0); 38310#L1071-1 assume !(0 == ~E_4~0); 39107#L1076-1 assume !(0 == ~E_5~0); 38217#L1081-1 assume !(0 == ~E_6~0); 38218#L1086-1 assume !(0 == ~E_7~0); 38566#L1091-1 assume !(0 == ~E_8~0); 39305#L1096-1 assume !(0 == ~E_9~0); 39306#L1101-1 assume !(0 == ~E_10~0); 38629#L1106-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 38630#L484 assume !(1 == ~m_pc~0); 38268#L484-2 is_master_triggered_~__retres1~0#1 := 0; 38267#L495 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 38899#L496 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 39211#L1245 assume !(0 != activate_threads_~tmp~1#1); 39212#L1245-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 38973#L503 assume !(1 == ~t1_pc~0); 38975#L503-2 is_transmit1_triggered_~__retres1~1#1 := 0; 39160#L514 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 39120#L515 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 38742#L1253 assume !(0 != activate_threads_~tmp___0~0#1); 38115#L1253-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 38116#L522 assume !(1 == ~t2_pc~0); 38938#L522-2 is_transmit2_triggered_~__retres1~2#1 := 0; 38322#L533 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 38323#L534 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 38801#L1261 assume !(0 != activate_threads_~tmp___1~0#1); 39264#L1261-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 39345#L541 assume 1 == ~t3_pc~0; 38882#L542 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 38690#L552 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 38500#L553 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 38501#L1269 assume !(0 != activate_threads_~tmp___2~0#1); 38941#L1269-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 38942#L560 assume !(1 == ~t4_pc~0); 38198#L560-2 is_transmit4_triggered_~__retres1~4#1 := 0; 38197#L571 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 38837#L572 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 38082#L1277 assume !(0 != activate_threads_~tmp___3~0#1); 38083#L1277-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 38371#L579 assume 1 == ~t5_pc~0; 38033#L580 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 38034#L590 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 38143#L591 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 38842#L1285 assume !(0 != activate_threads_~tmp___4~0#1); 39335#L1285-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 39363#L598 assume 1 == ~t6_pc~0; 38466#L599 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 38467#L609 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 38777#L610 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 39236#L1293 assume !(0 != activate_threads_~tmp___5~0#1); 39028#L1293-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 38963#L617 assume !(1 == ~t7_pc~0); 38441#L617-2 is_transmit7_triggered_~__retres1~7#1 := 0; 38440#L628 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 38732#L629 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 38733#L1301 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 38667#L1301-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 38668#L636 assume 1 == ~t8_pc~0; 38834#L637 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 38835#L647 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 38631#L648 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 38632#L1309 assume !(0 != activate_threads_~tmp___7~0#1); 38785#L1309-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 38786#L655 assume !(1 == ~t9_pc~0); 38814#L655-2 is_transmit9_triggered_~__retres1~9#1 := 0; 38815#L666 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 38420#L667 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 38421#L1317 assume !(0 != activate_threads_~tmp___8~0#1); 39047#L1317-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 39048#L674 assume 1 == ~t10_pc~0; 38193#L675 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 38194#L685 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 39347#L686 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 39409#L1325 assume !(0 != activate_threads_~tmp___9~0#1); 38775#L1325-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 38776#L1119 assume 1 == ~M_E~0;~M_E~0 := 2; 38291#L1119-2 assume !(1 == ~T1_E~0); 38292#L1124-1 assume !(1 == ~T2_E~0); 38705#L1129-1 assume !(1 == ~T3_E~0); 39810#L1134-1 assume !(1 == ~T4_E~0); 39547#L1139-1 assume !(1 == ~T5_E~0); 38662#L1144-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 38663#L1149-1 assume !(1 == ~T7_E~0); 38286#L1154-1 assume !(1 == ~T8_E~0); 38287#L1159-1 assume !(1 == ~T9_E~0); 39535#L1164-1 assume !(1 == ~T10_E~0); 39533#L1169-1 assume !(1 == ~E_1~0); 39531#L1174-1 assume !(1 == ~E_2~0); 39529#L1179-1 assume !(1 == ~E_3~0); 39527#L1184-1 assume 1 == ~E_4~0;~E_4~0 := 2; 39525#L1189-1 assume !(1 == ~E_5~0); 38544#L1194-1 assume !(1 == ~E_6~0); 38545#L1199-1 assume !(1 == ~E_7~0); 38490#L1204-1 assume !(1 == ~E_8~0); 38491#L1209-1 assume !(1 == ~E_9~0); 39459#L1214-1 assume !(1 == ~E_10~0); 39451#L1219-1 assume { :end_inline_reset_delta_events } true; 39445#L1520-2 [2021-12-16 10:06:03,208 INFO L793 eck$LassoCheckResult]: Loop: 39445#L1520-2 assume !false; 39440#L1521 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 39438#L981 assume !false; 39437#L832 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 39428#L764 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 39425#L821 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 39424#L822 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 39422#L836 assume !(0 != eval_~tmp~0#1); 39421#L996 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 39420#L694-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 39418#L1006-3 assume 0 == ~M_E~0;~M_E~0 := 1; 39419#L1006-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 40367#L1011-3 assume !(0 == ~T2_E~0); 39939#L1016-3 assume !(0 == ~T3_E~0); 39937#L1021-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 39935#L1026-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 39933#L1031-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 39931#L1036-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 39928#L1041-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 39926#L1046-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 39924#L1051-3 assume !(0 == ~T10_E~0); 39922#L1056-3 assume !(0 == ~E_1~0); 39920#L1061-3 assume 0 == ~E_2~0;~E_2~0 := 1; 39918#L1066-3 assume 0 == ~E_3~0;~E_3~0 := 1; 39915#L1071-3 assume 0 == ~E_4~0;~E_4~0 := 1; 39913#L1076-3 assume 0 == ~E_5~0;~E_5~0 := 1; 39911#L1081-3 assume 0 == ~E_6~0;~E_6~0 := 1; 39909#L1086-3 assume 0 == ~E_7~0;~E_7~0 := 1; 39907#L1091-3 assume !(0 == ~E_8~0); 39905#L1096-3 assume !(0 == ~E_9~0); 39904#L1101-3 assume 0 == ~E_10~0;~E_10~0 := 1; 39901#L1106-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 39899#L484-33 assume 1 == ~m_pc~0; 39896#L485-11 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 39894#L495-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 39892#L496-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 39890#L1245-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 39887#L1245-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 39883#L503-33 assume !(1 == ~t1_pc~0); 39881#L503-35 is_transmit1_triggered_~__retres1~1#1 := 0; 39879#L514-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 39878#L515-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 39874#L1253-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 39872#L1253-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 39870#L522-33 assume 1 == ~t2_pc~0; 39865#L523-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 39860#L533-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 39859#L534-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 39858#L1261-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 39857#L1261-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 39856#L541-33 assume !(1 == ~t3_pc~0); 39852#L541-35 is_transmit3_triggered_~__retres1~3#1 := 0; 39850#L552-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 39848#L553-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 39845#L1269-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 39843#L1269-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 39841#L560-33 assume 1 == ~t4_pc~0; 39838#L561-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 39836#L571-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 39835#L572-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 39831#L1277-33 assume !(0 != activate_threads_~tmp___3~0#1); 39829#L1277-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 39827#L579-33 assume 1 == ~t5_pc~0; 39821#L580-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 39816#L590-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 39815#L591-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 39814#L1285-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 39813#L1285-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 39812#L598-33 assume 1 == ~t6_pc~0; 39808#L599-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 39804#L609-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 39802#L610-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 39800#L1293-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 39798#L1293-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 39796#L617-33 assume 1 == ~t7_pc~0; 39793#L618-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 39790#L628-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 39788#L629-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 39786#L1301-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 39784#L1301-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 39782#L636-33 assume !(1 == ~t8_pc~0); 39780#L636-35 is_transmit8_triggered_~__retres1~8#1 := 0; 39776#L647-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 39774#L648-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 39772#L1309-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 39767#L1309-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 39766#L655-33 assume 1 == ~t9_pc~0; 39764#L656-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 39763#L666-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 39761#L667-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 39758#L1317-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 39756#L1317-35 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 39754#L674-33 assume !(1 == ~t10_pc~0); 39751#L674-35 is_transmit10_triggered_~__retres1~10#1 := 0; 39749#L685-11 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 39746#L686-11 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 39744#L1325-33 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 39742#L1325-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 39740#L1119-3 assume 1 == ~M_E~0;~M_E~0 := 2; 39365#L1119-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 39737#L1124-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 39735#L1129-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 39730#L1134-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 39728#L1139-3 assume !(1 == ~T5_E~0); 39726#L1144-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 39724#L1149-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 39722#L1154-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 39720#L1159-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 39717#L1164-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 39715#L1169-3 assume !(1 == ~E_1~0); 39713#L1174-3 assume 1 == ~E_2~0;~E_2~0 := 2; 39711#L1179-3 assume !(1 == ~E_3~0); 39709#L1184-3 assume 1 == ~E_4~0;~E_4~0 := 2; 39707#L1189-3 assume 1 == ~E_5~0;~E_5~0 := 2; 39704#L1194-3 assume 1 == ~E_6~0;~E_6~0 := 2; 39702#L1199-3 assume 1 == ~E_7~0;~E_7~0 := 2; 39700#L1204-3 assume 1 == ~E_8~0;~E_8~0 := 2; 39698#L1209-3 assume 1 == ~E_9~0;~E_9~0 := 2; 39695#L1214-3 assume 1 == ~E_10~0;~E_10~0 := 2; 39693#L1219-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 39593#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 39591#L821-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 39588#L822-1 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 39586#L1539 assume !(0 == start_simulation_~tmp~3#1); 39249#L1539-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 39573#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 39567#L821-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 39565#L822-2 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 39486#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 39468#L1501 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 39460#L1502 start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 39452#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 39445#L1520-2 [2021-12-16 10:06:03,209 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:03,209 INFO L85 PathProgramCache]: Analyzing trace with hash -24689322, now seen corresponding path program 1 times [2021-12-16 10:06:03,209 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:03,210 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [416927173] [2021-12-16 10:06:03,210 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:03,210 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:03,226 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:06:03,252 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:06:03,252 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:06:03,252 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [416927173] [2021-12-16 10:06:03,253 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [416927173] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:06:03,253 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:06:03,253 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:06:03,253 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1488035842] [2021-12-16 10:06:03,253 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:06:03,254 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:06:03,254 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:03,255 INFO L85 PathProgramCache]: Analyzing trace with hash -1879129007, now seen corresponding path program 1 times [2021-12-16 10:06:03,255 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:03,255 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [449689235] [2021-12-16 10:06:03,255 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:03,255 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:03,266 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:06:03,285 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:06:03,285 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:06:03,285 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [449689235] [2021-12-16 10:06:03,286 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [449689235] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:06:03,286 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:06:03,286 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:06:03,286 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [991236962] [2021-12-16 10:06:03,286 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:06:03,287 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:06:03,287 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:06:03,288 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-16 10:06:03,288 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-16 10:06:03,289 INFO L87 Difference]: Start difference. First operand 4284 states and 6256 transitions. cyclomatic complexity: 1976 Second operand has 4 states, 4 states have (on average 31.5) internal successors, (126), 3 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:03,528 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:06:03,529 INFO L93 Difference]: Finished difference Result 11645 states and 16849 transitions. [2021-12-16 10:06:03,529 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-16 10:06:03,530 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 11645 states and 16849 transitions. [2021-12-16 10:06:03,601 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 11437 [2021-12-16 10:06:03,650 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 11645 states to 11645 states and 16849 transitions. [2021-12-16 10:06:03,650 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11645 [2021-12-16 10:06:03,661 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11645 [2021-12-16 10:06:03,662 INFO L73 IsDeterministic]: Start isDeterministic. Operand 11645 states and 16849 transitions. [2021-12-16 10:06:03,681 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:06:03,681 INFO L681 BuchiCegarLoop]: Abstraction has 11645 states and 16849 transitions. [2021-12-16 10:06:03,689 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11645 states and 16849 transitions. [2021-12-16 10:06:03,854 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11645 to 11393. [2021-12-16 10:06:03,872 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 11393 states, 11393 states have (on average 1.448696568068112) internal successors, (16505), 11392 states have internal predecessors, (16505), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:03,908 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11393 states to 11393 states and 16505 transitions. [2021-12-16 10:06:03,908 INFO L704 BuchiCegarLoop]: Abstraction has 11393 states and 16505 transitions. [2021-12-16 10:06:03,908 INFO L587 BuchiCegarLoop]: Abstraction has 11393 states and 16505 transitions. [2021-12-16 10:06:03,908 INFO L425 BuchiCegarLoop]: ======== Iteration 14============ [2021-12-16 10:06:03,908 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 11393 states and 16505 transitions. [2021-12-16 10:06:03,974 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 11209 [2021-12-16 10:06:03,974 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:06:03,975 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:06:03,976 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:03,976 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:03,977 INFO L791 eck$LassoCheckResult]: Stem: 55006#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 55007#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 55420#L1483 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 55396#L694 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 55397#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 55449#L701-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 55450#L706-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 54531#L711-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 54241#L716-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 54242#L721-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 55281#L726-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 55282#L731-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 55252#L736-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 55253#L741-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 55317#L746-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 54297#L751-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 54298#L1006 assume !(0 == ~M_E~0); 54143#L1006-2 assume !(0 == ~T1_E~0); 54144#L1011-1 assume !(0 == ~T2_E~0); 55355#L1016-1 assume !(0 == ~T3_E~0); 55379#L1021-1 assume !(0 == ~T4_E~0); 54025#L1026-1 assume !(0 == ~T5_E~0); 54026#L1031-1 assume !(0 == ~T6_E~0); 54946#L1036-1 assume !(0 == ~T7_E~0); 54940#L1041-1 assume !(0 == ~T8_E~0); 54941#L1046-1 assume !(0 == ~T9_E~0); 54328#L1051-1 assume !(0 == ~T10_E~0); 54329#L1056-1 assume !(0 == ~E_1~0); 55102#L1061-1 assume !(0 == ~E_2~0); 54245#L1066-1 assume !(0 == ~E_3~0); 54246#L1071-1 assume !(0 == ~E_4~0); 55078#L1076-1 assume !(0 == ~E_5~0); 54153#L1081-1 assume !(0 == ~E_6~0); 54154#L1086-1 assume !(0 == ~E_7~0); 54506#L1091-1 assume !(0 == ~E_8~0); 55341#L1096-1 assume !(0 == ~E_9~0); 55342#L1101-1 assume !(0 == ~E_10~0); 54567#L1106-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 54568#L484 assume !(1 == ~m_pc~0); 54203#L484-2 is_master_triggered_~__retres1~0#1 := 0; 54202#L495 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 54857#L496 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 55202#L1245 assume !(0 != activate_threads_~tmp~1#1); 55203#L1245-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 54933#L503 assume !(1 == ~t1_pc~0); 54934#L503-2 is_transmit1_triggered_~__retres1~1#1 := 0; 55139#L514 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 55094#L515 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 54689#L1253 assume !(0 != activate_threads_~tmp___0~0#1); 54053#L1253-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 54054#L522 assume !(1 == ~t2_pc~0); 54896#L522-2 is_transmit2_triggered_~__retres1~2#1 := 0; 54258#L533 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 54259#L534 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 54748#L1261 assume !(0 != activate_threads_~tmp___1~0#1); 55283#L1261-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 55390#L541 assume !(1 == ~t3_pc~0); 54627#L541-2 is_transmit3_triggered_~__retres1~3#1 := 0; 54628#L552 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 54441#L553 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 54442#L1269 assume !(0 != activate_threads_~tmp___2~0#1); 54899#L1269-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 54900#L560 assume !(1 == ~t4_pc~0); 54137#L560-2 is_transmit4_triggered_~__retres1~4#1 := 0; 54136#L571 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 54786#L572 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 54021#L1277 assume !(0 != activate_threads_~tmp___3~0#1); 54022#L1277-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 54311#L579 assume 1 == ~t5_pc~0; 53972#L580 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 53973#L590 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 54081#L591 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 54791#L1285 assume !(0 != activate_threads_~tmp___4~0#1); 55378#L1285-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 55414#L598 assume 1 == ~t6_pc~0; 54406#L599 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 54407#L609 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 54726#L610 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 55238#L1293 assume !(0 != activate_threads_~tmp___5~0#1); 54987#L1293-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 54923#L617 assume !(1 == ~t7_pc~0); 54381#L617-2 is_transmit7_triggered_~__retres1~7#1 := 0; 54380#L628 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 54675#L629 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 54676#L1301 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 54604#L1301-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 54605#L636 assume 1 == ~t8_pc~0; 54783#L637 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 54784#L647 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 54569#L648 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 54570#L1309 assume !(0 != activate_threads_~tmp___7~0#1); 54731#L1309-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 54732#L655 assume !(1 == ~t9_pc~0); 54765#L655-2 is_transmit9_triggered_~__retres1~9#1 := 0; 54766#L666 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 54359#L667 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 54360#L1317 assume !(0 != activate_threads_~tmp___8~0#1); 55008#L1317-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 55009#L674 assume 1 == ~t10_pc~0; 54130#L675 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 54131#L685 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 55393#L686 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 55480#L1325 assume !(0 != activate_threads_~tmp___9~0#1); 54721#L1325-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 54722#L1119 assume 1 == ~M_E~0;~M_E~0 := 2; 54226#L1119-2 assume !(1 == ~T1_E~0); 54227#L1124-1 assume !(1 == ~T2_E~0); 54045#L1129-1 assume !(1 == ~T3_E~0); 54046#L1134-1 assume !(1 == ~T4_E~0); 54365#L1139-1 assume !(1 == ~T5_E~0); 54366#L1144-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 54600#L1149-1 assume !(1 == ~T7_E~0); 54221#L1154-1 assume !(1 == ~T8_E~0); 54222#L1159-1 assume !(1 == ~T9_E~0); 57552#L1164-1 assume !(1 == ~T10_E~0); 57550#L1169-1 assume !(1 == ~E_1~0); 57549#L1174-1 assume !(1 == ~E_2~0); 57547#L1179-1 assume !(1 == ~E_3~0); 54301#L1184-1 assume 1 == ~E_4~0;~E_4~0 := 2; 54302#L1189-1 assume !(1 == ~E_5~0); 57505#L1194-1 assume !(1 == ~E_6~0); 57503#L1199-1 assume !(1 == ~E_7~0); 54431#L1204-1 assume !(1 == ~E_8~0); 54432#L1209-1 assume !(1 == ~E_9~0); 57444#L1214-1 assume !(1 == ~E_10~0); 57429#L1219-1 assume { :end_inline_reset_delta_events } true; 57418#L1520-2 [2021-12-16 10:06:03,977 INFO L793 eck$LassoCheckResult]: Loop: 57418#L1520-2 assume !false; 57412#L1521 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 57410#L981 assume !false; 57409#L832 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 57399#L764 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 57385#L821 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 57383#L822 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 57380#L836 assume !(0 != eval_~tmp~0#1); 57376#L996 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 57375#L694-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 57373#L1006-3 assume 0 == ~M_E~0;~M_E~0 := 1; 57374#L1006-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 63399#L1011-3 assume !(0 == ~T2_E~0); 63398#L1016-3 assume !(0 == ~T3_E~0); 63397#L1021-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 63396#L1026-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 63395#L1031-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 63394#L1036-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 63393#L1041-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 63392#L1046-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 63391#L1051-3 assume !(0 == ~T10_E~0); 63390#L1056-3 assume !(0 == ~E_1~0); 63389#L1061-3 assume 0 == ~E_2~0;~E_2~0 := 1; 63388#L1066-3 assume 0 == ~E_3~0;~E_3~0 := 1; 63387#L1071-3 assume 0 == ~E_4~0;~E_4~0 := 1; 63386#L1076-3 assume 0 == ~E_5~0;~E_5~0 := 1; 63385#L1081-3 assume 0 == ~E_6~0;~E_6~0 := 1; 63384#L1086-3 assume 0 == ~E_7~0;~E_7~0 := 1; 54161#L1091-3 assume !(0 == ~E_8~0); 54162#L1096-3 assume !(0 == ~E_9~0); 55319#L1101-3 assume 0 == ~E_10~0;~E_10~0 := 1; 55320#L1106-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 54833#L484-33 assume 1 == ~m_pc~0; 54834#L485-11 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 54736#L495-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 54737#L496-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 54015#L1245-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 54016#L1245-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 54495#L503-33 assume !(1 == ~t1_pc~0); 54496#L503-35 is_transmit1_triggered_~__retres1~1#1 := 0; 63439#L514-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 63437#L515-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 63435#L1253-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 63433#L1253-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 63431#L522-33 assume 1 == ~t2_pc~0; 63427#L523-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 63425#L533-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 54994#L534-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 54995#L1261-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 54894#L1261-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 54895#L541-33 assume !(1 == ~t3_pc~0); 55276#L541-35 is_transmit3_triggered_~__retres1~3#1 := 0; 63414#L552-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 63413#L553-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 63412#L1269-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 63411#L1269-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 63410#L560-33 assume 1 == ~t4_pc~0; 63408#L561-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 63407#L571-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 63406#L572-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 63405#L1277-33 assume !(0 != activate_threads_~tmp___3~0#1); 63404#L1277-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 63403#L579-33 assume 1 == ~t5_pc~0; 63401#L580-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 63400#L590-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 55394#L591-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 55395#L1285-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 57271#L1285-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 57270#L598-33 assume !(1 == ~t6_pc~0); 57268#L598-35 is_transmit6_triggered_~__retres1~6#1 := 0; 57266#L609-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 57267#L610-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 62630#L1293-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 62628#L1293-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 62626#L617-33 assume !(1 == ~t7_pc~0); 62624#L617-35 is_transmit7_triggered_~__retres1~7#1 := 0; 62621#L628-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 62619#L629-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 62617#L1301-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 62615#L1301-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 62613#L636-33 assume !(1 == ~t8_pc~0); 62610#L636-35 is_transmit8_triggered_~__retres1~8#1 := 0; 62608#L647-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 62606#L648-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 62603#L1309-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 62601#L1309-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 62599#L655-33 assume 1 == ~t9_pc~0; 62596#L656-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 62594#L666-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 62591#L667-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 62589#L1317-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 62587#L1317-35 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 62585#L674-33 assume !(1 == ~t10_pc~0); 62574#L674-35 is_transmit10_triggered_~__retres1~10#1 := 0; 62572#L685-11 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 62570#L686-11 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 62568#L1325-33 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 62566#L1325-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 62564#L1119-3 assume 1 == ~M_E~0;~M_E~0 := 2; 57195#L1119-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 62560#L1124-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 62558#L1129-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 62555#L1134-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 62554#L1139-3 assume !(1 == ~T5_E~0); 62553#L1144-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 62552#L1149-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 62551#L1154-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 62550#L1159-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 62549#L1164-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 62548#L1169-3 assume !(1 == ~E_1~0); 62547#L1174-3 assume 1 == ~E_2~0;~E_2~0 := 2; 62546#L1179-3 assume !(1 == ~E_3~0); 62545#L1184-3 assume 1 == ~E_4~0;~E_4~0 := 2; 62544#L1189-3 assume 1 == ~E_5~0;~E_5~0 := 2; 62543#L1194-3 assume 1 == ~E_6~0;~E_6~0 := 2; 62541#L1199-3 assume 1 == ~E_7~0;~E_7~0 := 2; 61839#L1204-3 assume 1 == ~E_8~0;~E_8~0 := 2; 61831#L1209-3 assume 1 == ~E_9~0;~E_9~0 := 2; 61800#L1214-3 assume 1 == ~E_10~0;~E_10~0 := 2; 61728#L1219-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 61704#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 58173#L821-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 58171#L822-1 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 58170#L1539 assume !(0 == start_simulation_~tmp~3#1); 55255#L1539-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 57538#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 57509#L821-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 57507#L822-2 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 57483#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 57462#L1501 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 57445#L1502 start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 57430#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 57418#L1520-2 [2021-12-16 10:06:03,978 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:03,978 INFO L85 PathProgramCache]: Analyzing trace with hash 882067125, now seen corresponding path program 1 times [2021-12-16 10:06:03,978 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:03,978 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1640465288] [2021-12-16 10:06:03,978 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:03,979 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:03,989 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:06:04,010 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:06:04,010 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:06:04,010 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1640465288] [2021-12-16 10:06:04,010 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1640465288] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:06:04,011 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:06:04,011 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:06:04,011 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1946258306] [2021-12-16 10:06:04,011 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:06:04,011 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:06:04,012 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:04,012 INFO L85 PathProgramCache]: Analyzing trace with hash 1979109583, now seen corresponding path program 1 times [2021-12-16 10:06:04,012 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:04,012 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [403581482] [2021-12-16 10:06:04,012 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:04,013 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:04,022 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:06:04,042 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:06:04,042 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:06:04,042 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [403581482] [2021-12-16 10:06:04,042 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [403581482] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:06:04,043 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:06:04,043 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:06:04,043 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1983244076] [2021-12-16 10:06:04,043 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:06:04,044 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:06:04,044 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:06:04,044 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-16 10:06:04,044 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-16 10:06:04,045 INFO L87 Difference]: Start difference. First operand 11393 states and 16505 transitions. cyclomatic complexity: 5120 Second operand has 4 states, 4 states have (on average 31.5) internal successors, (126), 3 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:04,307 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:06:04,307 INFO L93 Difference]: Finished difference Result 31518 states and 45350 transitions. [2021-12-16 10:06:04,307 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-16 10:06:04,308 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 31518 states and 45350 transitions. [2021-12-16 10:06:04,487 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 31239 [2021-12-16 10:06:04,712 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 31518 states to 31518 states and 45350 transitions. [2021-12-16 10:06:04,712 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 31518 [2021-12-16 10:06:04,742 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 31518 [2021-12-16 10:06:04,742 INFO L73 IsDeterministic]: Start isDeterministic. Operand 31518 states and 45350 transitions. [2021-12-16 10:06:04,781 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:06:04,782 INFO L681 BuchiCegarLoop]: Abstraction has 31518 states and 45350 transitions. [2021-12-16 10:06:04,804 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 31518 states and 45350 transitions. [2021-12-16 10:06:05,329 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 31518 to 30922. [2021-12-16 10:06:05,381 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 30922 states, 30922 states have (on average 1.4404631007049997) internal successors, (44542), 30921 states have internal predecessors, (44542), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:05,475 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 30922 states to 30922 states and 44542 transitions. [2021-12-16 10:06:05,475 INFO L704 BuchiCegarLoop]: Abstraction has 30922 states and 44542 transitions. [2021-12-16 10:06:05,476 INFO L587 BuchiCegarLoop]: Abstraction has 30922 states and 44542 transitions. [2021-12-16 10:06:05,476 INFO L425 BuchiCegarLoop]: ======== Iteration 15============ [2021-12-16 10:06:05,476 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 30922 states and 44542 transitions. [2021-12-16 10:06:05,587 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 30723 [2021-12-16 10:06:05,587 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:06:05,587 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:06:05,589 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:05,589 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:05,590 INFO L791 eck$LassoCheckResult]: Stem: 97909#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 97910#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 98298#L1483 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 98275#L694 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 98276#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 98320#L701-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 98321#L706-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 97442#L711-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 97159#L716-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 97160#L721-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 98159#L726-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 98160#L731-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 98135#L736-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 98136#L741-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 98189#L746-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 97213#L751-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 97214#L1006 assume !(0 == ~M_E~0); 97062#L1006-2 assume !(0 == ~T1_E~0); 97063#L1011-1 assume !(0 == ~T2_E~0); 98226#L1016-1 assume !(0 == ~T3_E~0); 98252#L1021-1 assume !(0 == ~T4_E~0); 96942#L1026-1 assume !(0 == ~T5_E~0); 96943#L1031-1 assume !(0 == ~T6_E~0); 97852#L1036-1 assume !(0 == ~T7_E~0); 97845#L1041-1 assume !(0 == ~T8_E~0); 97846#L1046-1 assume !(0 == ~T9_E~0); 97245#L1051-1 assume !(0 == ~T10_E~0); 97246#L1056-1 assume !(0 == ~E_1~0); 98005#L1061-1 assume !(0 == ~E_2~0); 97161#L1066-1 assume !(0 == ~E_3~0); 97162#L1071-1 assume !(0 == ~E_4~0); 97982#L1076-1 assume !(0 == ~E_5~0); 97070#L1081-1 assume !(0 == ~E_6~0); 97071#L1086-1 assume !(0 == ~E_7~0); 97418#L1091-1 assume !(0 == ~E_8~0); 98209#L1096-1 assume !(0 == ~E_9~0); 98210#L1101-1 assume !(0 == ~E_10~0); 97483#L1106-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 97484#L484 assume !(1 == ~m_pc~0); 97119#L484-2 is_master_triggered_~__retres1~0#1 := 0; 97118#L495 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 97759#L496 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 98097#L1245 assume !(0 != activate_threads_~tmp~1#1); 98098#L1245-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 97836#L503 assume !(1 == ~t1_pc~0); 97837#L503-2 is_transmit1_triggered_~__retres1~1#1 := 0; 98045#L514 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 97997#L515 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 97601#L1253 assume !(0 != activate_threads_~tmp___0~0#1); 96972#L1253-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 96973#L522 assume !(1 == ~t2_pc~0); 97798#L522-2 is_transmit2_triggered_~__retres1~2#1 := 0; 97177#L533 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 97178#L534 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 97657#L1261 assume !(0 != activate_threads_~tmp___1~0#1); 98161#L1261-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 98270#L541 assume !(1 == ~t3_pc~0); 97543#L541-2 is_transmit3_triggered_~__retres1~3#1 := 0; 97544#L552 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 97354#L553 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 97355#L1269 assume !(0 != activate_threads_~tmp___2~0#1); 97805#L1269-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 97806#L560 assume !(1 == ~t4_pc~0); 97054#L560-2 is_transmit4_triggered_~__retres1~4#1 := 0; 97053#L571 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 97693#L572 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 96938#L1277 assume !(0 != activate_threads_~tmp___3~0#1); 96939#L1277-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 97227#L579 assume !(1 == ~t5_pc~0); 97228#L579-2 is_transmit5_triggered_~__retres1~5#1 := 0; 96998#L590 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 96999#L591 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 97699#L1285 assume !(0 != activate_threads_~tmp___4~0#1); 98251#L1285-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 98294#L598 assume 1 == ~t6_pc~0; 97323#L599 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 97324#L609 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 97636#L610 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 98126#L1293 assume !(0 != activate_threads_~tmp___5~0#1); 97890#L1293-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 97827#L617 assume !(1 == ~t7_pc~0); 97295#L617-2 is_transmit7_triggered_~__retres1~7#1 := 0; 97294#L628 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 97585#L629 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 97586#L1301 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 97522#L1301-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 97523#L636 assume 1 == ~t8_pc~0; 97690#L637 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 97691#L647 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 97485#L648 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 97486#L1309 assume !(0 != activate_threads_~tmp___7~0#1); 97643#L1309-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 97644#L655 assume !(1 == ~t9_pc~0); 97676#L655-2 is_transmit9_triggered_~__retres1~9#1 := 0; 97677#L666 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 97275#L667 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 97276#L1317 assume !(0 != activate_threads_~tmp___8~0#1); 97911#L1317-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 97912#L674 assume 1 == ~t10_pc~0; 97047#L675 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 97048#L685 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 98273#L686 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 98340#L1325 assume !(0 != activate_threads_~tmp___9~0#1); 97631#L1325-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 97632#L1119 assume 1 == ~M_E~0;~M_E~0 := 2; 97142#L1119-2 assume !(1 == ~T1_E~0); 97143#L1124-1 assume !(1 == ~T2_E~0); 96962#L1129-1 assume !(1 == ~T3_E~0); 96963#L1134-1 assume !(1 == ~T4_E~0); 118981#L1139-1 assume !(1 == ~T5_E~0); 97519#L1144-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 97520#L1149-1 assume !(1 == ~T7_E~0); 97137#L1154-1 assume !(1 == ~T8_E~0); 97138#L1159-1 assume !(1 == ~T9_E~0); 118963#L1164-1 assume !(1 == ~T10_E~0); 118961#L1169-1 assume !(1 == ~E_1~0); 118959#L1174-1 assume !(1 == ~E_2~0); 118957#L1179-1 assume !(1 == ~E_3~0); 118955#L1184-1 assume 1 == ~E_4~0;~E_4~0 := 2; 118952#L1189-1 assume !(1 == ~E_5~0); 118950#L1194-1 assume !(1 == ~E_6~0); 118948#L1199-1 assume !(1 == ~E_7~0); 118946#L1204-1 assume !(1 == ~E_8~0); 118944#L1209-1 assume !(1 == ~E_9~0); 98309#L1214-1 assume !(1 == ~E_10~0); 118940#L1219-1 assume { :end_inline_reset_delta_events } true; 118941#L1520-2 [2021-12-16 10:06:05,590 INFO L793 eck$LassoCheckResult]: Loop: 118941#L1520-2 assume !false; 122897#L1521 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 122895#L981 assume !false; 122894#L832 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 122885#L764 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 122882#L821 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 122881#L822 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 122879#L836 assume !(0 != eval_~tmp~0#1); 122880#L996 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 127066#L694-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 127064#L1006-3 assume 0 == ~M_E~0;~M_E~0 := 1; 127062#L1006-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 127061#L1011-3 assume !(0 == ~T2_E~0); 127060#L1016-3 assume !(0 == ~T3_E~0); 127059#L1021-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 127058#L1026-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 127035#L1031-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 127034#L1036-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 126893#L1041-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 126894#L1046-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 126887#L1051-3 assume !(0 == ~T10_E~0); 126888#L1056-3 assume !(0 == ~E_1~0); 126877#L1061-3 assume 0 == ~E_2~0;~E_2~0 := 1; 126878#L1066-3 assume 0 == ~E_3~0;~E_3~0 := 1; 126862#L1071-3 assume 0 == ~E_4~0;~E_4~0 := 1; 126863#L1076-3 assume 0 == ~E_5~0;~E_5~0 := 1; 126855#L1081-3 assume 0 == ~E_6~0;~E_6~0 := 1; 126856#L1086-3 assume 0 == ~E_7~0;~E_7~0 := 1; 97076#L1091-3 assume !(0 == ~E_8~0); 97077#L1096-3 assume !(0 == ~E_9~0); 127033#L1101-3 assume 0 == ~E_10~0;~E_10~0 := 1; 98232#L1106-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 97736#L484-33 assume 1 == ~m_pc~0; 97737#L485-11 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 98109#L495-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 127029#L496-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 127028#L1245-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 127027#L1245-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 97403#L503-33 assume !(1 == ~t1_pc~0); 97404#L503-35 is_transmit1_triggered_~__retres1~1#1 := 0; 98173#L514-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 97810#L515-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 97313#L1253-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 97314#L1253-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 126891#L522-33 assume 1 == ~t2_pc~0; 97921#L523-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 97922#L533-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 126841#L534-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 98103#L1261-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 97796#L1261-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 97797#L541-33 assume !(1 == ~t3_pc~0); 119217#L541-35 is_transmit3_triggered_~__retres1~3#1 := 0; 119215#L552-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 119213#L553-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 119211#L1269-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 119209#L1269-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 119207#L560-33 assume !(1 == ~t4_pc~0); 119205#L560-35 is_transmit4_triggered_~__retres1~4#1 := 0; 119202#L571-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 119199#L572-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 119197#L1277-33 assume !(0 != activate_threads_~tmp___3~0#1); 119195#L1277-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 119193#L579-33 assume !(1 == ~t5_pc~0); 119191#L579-35 is_transmit5_triggered_~__retres1~5#1 := 0; 119189#L590-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 119188#L591-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 119186#L1285-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 119184#L1285-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 119182#L598-33 assume !(1 == ~t6_pc~0); 119179#L598-35 is_transmit6_triggered_~__retres1~6#1 := 0; 119177#L609-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 119174#L610-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 119172#L1293-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 119170#L1293-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 119168#L617-33 assume 1 == ~t7_pc~0; 119165#L618-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 119163#L628-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 119161#L629-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 119159#L1301-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 119157#L1301-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 119155#L636-33 assume 1 == ~t8_pc~0; 119153#L637-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 119149#L647-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 119150#L648-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 123388#L1309-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 123386#L1309-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 123384#L655-33 assume 1 == ~t9_pc~0; 123381#L656-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 123379#L666-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 123377#L667-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 123375#L1317-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 123373#L1317-35 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 123371#L674-33 assume 1 == ~t10_pc~0; 123369#L675-11 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 123366#L685-11 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 123364#L686-11 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 123362#L1325-33 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 123360#L1325-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 123357#L1119-3 assume 1 == ~M_E~0;~M_E~0 := 2; 109998#L1119-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 123354#L1124-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 123279#L1129-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 123278#L1134-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 123277#L1139-3 assume !(1 == ~T5_E~0); 123276#L1144-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 123275#L1149-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 123274#L1154-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 123273#L1159-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 123272#L1164-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 123271#L1169-3 assume !(1 == ~E_1~0); 123270#L1174-3 assume 1 == ~E_2~0;~E_2~0 := 2; 123269#L1179-3 assume !(1 == ~E_3~0); 123268#L1184-3 assume 1 == ~E_4~0;~E_4~0 := 2; 123267#L1189-3 assume 1 == ~E_5~0;~E_5~0 := 2; 123266#L1194-3 assume 1 == ~E_6~0;~E_6~0 := 2; 123265#L1199-3 assume 1 == ~E_7~0;~E_7~0 := 2; 123264#L1204-3 assume 1 == ~E_8~0;~E_8~0 := 2; 123263#L1209-3 assume 1 == ~E_9~0;~E_9~0 := 2; 119070#L1214-3 assume 1 == ~E_10~0;~E_10~0 := 2; 123262#L1219-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 123251#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 123250#L821-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 123249#L822-1 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 123248#L1539 assume !(0 == start_simulation_~tmp~3#1); 123246#L1539-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 123239#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 123234#L821-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 123233#L822-2 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 123232#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 123231#L1501 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 123230#L1502 start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 123228#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 118941#L1520-2 [2021-12-16 10:06:05,591 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:05,591 INFO L85 PathProgramCache]: Analyzing trace with hash -259580268, now seen corresponding path program 1 times [2021-12-16 10:06:05,591 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:05,592 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [64805706] [2021-12-16 10:06:05,592 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:05,592 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:05,603 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:06:05,625 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:06:05,625 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:06:05,625 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [64805706] [2021-12-16 10:06:05,625 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [64805706] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:06:05,626 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:06:05,626 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:06:05,626 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1794856110] [2021-12-16 10:06:05,626 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:06:05,627 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:06:05,627 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:05,627 INFO L85 PathProgramCache]: Analyzing trace with hash 113241008, now seen corresponding path program 1 times [2021-12-16 10:06:05,627 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:05,627 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1264275500] [2021-12-16 10:06:05,628 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:05,628 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:05,637 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:06:05,657 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:06:05,657 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:06:05,657 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1264275500] [2021-12-16 10:06:05,657 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1264275500] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:06:05,657 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:06:05,658 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:06:05,658 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1664852472] [2021-12-16 10:06:05,658 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:06:05,658 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:06:05,659 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:06:05,659 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-16 10:06:05,659 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-16 10:06:05,659 INFO L87 Difference]: Start difference. First operand 30922 states and 44542 transitions. cyclomatic complexity: 13636 Second operand has 4 states, 4 states have (on average 31.5) internal successors, (126), 3 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:06,330 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:06:06,330 INFO L93 Difference]: Finished difference Result 86077 states and 123319 transitions. [2021-12-16 10:06:06,331 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-16 10:06:06,332 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 86077 states and 123319 transitions. [2021-12-16 10:06:06,904 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 85623 [2021-12-16 10:06:07,231 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 86077 states to 86077 states and 123319 transitions. [2021-12-16 10:06:07,232 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 86077 [2021-12-16 10:06:07,313 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 86077 [2021-12-16 10:06:07,313 INFO L73 IsDeterministic]: Start isDeterministic. Operand 86077 states and 123319 transitions. [2021-12-16 10:06:07,482 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:06:07,515 INFO L681 BuchiCegarLoop]: Abstraction has 86077 states and 123319 transitions. [2021-12-16 10:06:07,600 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 86077 states and 123319 transitions. [2021-12-16 10:06:08,824 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 86077 to 84557. [2021-12-16 10:06:08,951 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 84557 states, 84557 states have (on average 1.434192319973509) internal successors, (121271), 84556 states have internal predecessors, (121271), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:09,154 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 84557 states to 84557 states and 121271 transitions. [2021-12-16 10:06:09,154 INFO L704 BuchiCegarLoop]: Abstraction has 84557 states and 121271 transitions. [2021-12-16 10:06:09,154 INFO L587 BuchiCegarLoop]: Abstraction has 84557 states and 121271 transitions. [2021-12-16 10:06:09,154 INFO L425 BuchiCegarLoop]: ======== Iteration 16============ [2021-12-16 10:06:09,154 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 84557 states and 121271 transitions. [2021-12-16 10:06:09,572 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 84327 [2021-12-16 10:06:09,572 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:06:09,572 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:06:09,574 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:09,574 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:09,575 INFO L791 eck$LassoCheckResult]: Stem: 214919#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 214920#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 215304#L1483 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 215283#L694 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 215284#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 215324#L701-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 215325#L706-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 214449#L711-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 214167#L716-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 214168#L721-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 215176#L726-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 215177#L731-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 215152#L736-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 215153#L741-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 215201#L746-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 214221#L751-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 214222#L1006 assume !(0 == ~M_E~0); 214071#L1006-2 assume !(0 == ~T1_E~0); 214072#L1011-1 assume !(0 == ~T2_E~0); 215247#L1016-1 assume !(0 == ~T3_E~0); 215266#L1021-1 assume !(0 == ~T4_E~0); 213951#L1026-1 assume !(0 == ~T5_E~0); 213952#L1031-1 assume !(0 == ~T6_E~0); 214857#L1036-1 assume !(0 == ~T7_E~0); 214850#L1041-1 assume !(0 == ~T8_E~0); 214851#L1046-1 assume !(0 == ~T9_E~0); 214253#L1051-1 assume !(0 == ~T10_E~0); 214254#L1056-1 assume !(0 == ~E_1~0); 215014#L1061-1 assume !(0 == ~E_2~0); 214169#L1066-1 assume !(0 == ~E_3~0); 214170#L1071-1 assume !(0 == ~E_4~0); 214987#L1076-1 assume !(0 == ~E_5~0); 214079#L1081-1 assume !(0 == ~E_6~0); 214080#L1086-1 assume !(0 == ~E_7~0); 214425#L1091-1 assume !(0 == ~E_8~0); 215222#L1096-1 assume !(0 == ~E_9~0); 215223#L1101-1 assume !(0 == ~E_10~0); 214492#L1106-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 214493#L484 assume !(1 == ~m_pc~0); 214128#L484-2 is_master_triggered_~__retres1~0#1 := 0; 214127#L495 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 214767#L496 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 215104#L1245 assume !(0 != activate_threads_~tmp~1#1); 215105#L1245-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 214842#L503 assume !(1 == ~t1_pc~0); 214843#L503-2 is_transmit1_triggered_~__retres1~1#1 := 0; 215050#L514 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 215004#L515 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 214611#L1253 assume !(0 != activate_threads_~tmp___0~0#1); 213981#L1253-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 213982#L522 assume !(1 == ~t2_pc~0); 214806#L522-2 is_transmit2_triggered_~__retres1~2#1 := 0; 214186#L533 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 214187#L534 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 214668#L1261 assume !(0 != activate_threads_~tmp___1~0#1); 215178#L1261-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 215278#L541 assume !(1 == ~t3_pc~0); 214552#L541-2 is_transmit3_triggered_~__retres1~3#1 := 0; 214553#L552 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 214360#L553 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 214361#L1269 assume !(0 != activate_threads_~tmp___2~0#1); 214813#L1269-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 214814#L560 assume !(1 == ~t4_pc~0); 214062#L560-2 is_transmit4_triggered_~__retres1~4#1 := 0; 214061#L571 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 214704#L572 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 213947#L1277 assume !(0 != activate_threads_~tmp___3~0#1); 213948#L1277-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 214235#L579 assume !(1 == ~t5_pc~0); 214236#L579-2 is_transmit5_triggered_~__retres1~5#1 := 0; 214008#L590 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 214009#L591 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 214708#L1285 assume !(0 != activate_threads_~tmp___4~0#1); 215265#L1285-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 215299#L598 assume !(1 == ~t6_pc~0); 215030#L598-2 is_transmit6_triggered_~__retres1~6#1 := 0; 214646#L609 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 214647#L610 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 215139#L1293 assume !(0 != activate_threads_~tmp___5~0#1); 214895#L1293-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 214832#L617 assume !(1 == ~t7_pc~0); 214305#L617-2 is_transmit7_triggered_~__retres1~7#1 := 0; 214304#L628 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 214595#L629 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 214596#L1301 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 214531#L1301-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 214532#L636 assume 1 == ~t8_pc~0; 214701#L637 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 214702#L647 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 214494#L648 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 214495#L1309 assume !(0 != activate_threads_~tmp___7~0#1); 214654#L1309-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 214655#L655 assume !(1 == ~t9_pc~0); 214685#L655-2 is_transmit9_triggered_~__retres1~9#1 := 0; 214686#L666 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 214285#L667 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 214286#L1317 assume !(0 != activate_threads_~tmp___8~0#1); 214921#L1317-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 214922#L674 assume 1 == ~t10_pc~0; 214055#L675 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 214056#L685 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 215280#L686 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 215344#L1325 assume !(0 != activate_threads_~tmp___9~0#1); 214641#L1325-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 214642#L1119 assume 1 == ~M_E~0;~M_E~0 := 2; 214151#L1119-2 assume !(1 == ~T1_E~0); 214152#L1124-1 assume !(1 == ~T2_E~0); 213971#L1129-1 assume !(1 == ~T3_E~0); 213972#L1134-1 assume !(1 == ~T4_E~0); 214822#L1139-1 assume !(1 == ~T5_E~0); 214528#L1144-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 214529#L1149-1 assume !(1 == ~T7_E~0); 226941#L1154-1 assume !(1 == ~T8_E~0); 214237#L1159-1 assume !(1 == ~T9_E~0); 214238#L1164-1 assume !(1 == ~T10_E~0); 214671#L1169-1 assume !(1 == ~E_1~0); 214672#L1174-1 assume !(1 == ~E_2~0); 214342#L1179-1 assume !(1 == ~E_3~0); 214343#L1184-1 assume 1 == ~E_4~0;~E_4~0 := 2; 214283#L1189-1 assume !(1 == ~E_5~0); 214284#L1194-1 assume !(1 == ~E_6~0); 215367#L1199-1 assume !(1 == ~E_7~0); 215368#L1204-1 assume !(1 == ~E_8~0); 215315#L1209-1 assume !(1 == ~E_9~0); 214914#L1214-1 assume !(1 == ~E_10~0); 214915#L1219-1 assume { :end_inline_reset_delta_events } true; 226969#L1520-2 [2021-12-16 10:06:09,575 INFO L793 eck$LassoCheckResult]: Loop: 226969#L1520-2 assume !false; 293734#L1521 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 293731#L981 assume !false; 293681#L832 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 225368#L764 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 225365#L821 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 225361#L822 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 225358#L836 assume !(0 != eval_~tmp~0#1); 225359#L996 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 228280#L694-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 228276#L1006-3 assume 0 == ~M_E~0;~M_E~0 := 1; 228277#L1006-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 295140#L1011-3 assume !(0 == ~T2_E~0); 295138#L1016-3 assume !(0 == ~T3_E~0); 295136#L1021-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 295134#L1026-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 295132#L1031-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 295130#L1036-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 295128#L1041-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 295126#L1046-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 295124#L1051-3 assume !(0 == ~T10_E~0); 295122#L1056-3 assume !(0 == ~E_1~0); 295120#L1061-3 assume 0 == ~E_2~0;~E_2~0 := 1; 295118#L1066-3 assume 0 == ~E_3~0;~E_3~0 := 1; 295116#L1071-3 assume 0 == ~E_4~0;~E_4~0 := 1; 295114#L1076-3 assume 0 == ~E_5~0;~E_5~0 := 1; 295112#L1081-3 assume 0 == ~E_6~0;~E_6~0 := 1; 295110#L1086-3 assume 0 == ~E_7~0;~E_7~0 := 1; 295108#L1091-3 assume !(0 == ~E_8~0); 295106#L1096-3 assume !(0 == ~E_9~0); 295104#L1101-3 assume 0 == ~E_10~0;~E_10~0 := 1; 295102#L1106-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 295100#L484-33 assume 1 == ~m_pc~0; 295096#L485-11 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 295094#L495-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 295091#L496-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 295088#L1245-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 295086#L1245-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 295084#L503-33 assume !(1 == ~t1_pc~0); 295082#L503-35 is_transmit1_triggered_~__retres1~1#1 := 0; 295080#L514-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 295077#L515-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 295076#L1253-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 295075#L1253-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 295074#L522-33 assume 1 == ~t2_pc~0; 295072#L523-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 295071#L533-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 295068#L534-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 295067#L1261-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 295066#L1261-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 295065#L541-33 assume !(1 == ~t3_pc~0); 295064#L541-35 is_transmit3_triggered_~__retres1~3#1 := 0; 295063#L552-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 295062#L553-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 295061#L1269-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 295060#L1269-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 295059#L560-33 assume 1 == ~t4_pc~0; 295057#L561-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 295056#L571-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 295053#L572-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 295052#L1277-33 assume !(0 != activate_threads_~tmp___3~0#1); 295051#L1277-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 295050#L579-33 assume !(1 == ~t5_pc~0); 295049#L579-35 is_transmit5_triggered_~__retres1~5#1 := 0; 295048#L590-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 295047#L591-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 295046#L1285-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 295045#L1285-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 295044#L598-33 assume !(1 == ~t6_pc~0); 295043#L598-35 is_transmit6_triggered_~__retres1~6#1 := 0; 295042#L609-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 295041#L610-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 295040#L1293-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 295039#L1293-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 295038#L617-33 assume 1 == ~t7_pc~0; 295036#L618-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 295035#L628-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 295032#L629-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 295031#L1301-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 295030#L1301-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 295029#L636-33 assume 1 == ~t8_pc~0; 295028#L637-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 295026#L647-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 295025#L648-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 295023#L1309-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 295022#L1309-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 295021#L655-33 assume 1 == ~t9_pc~0; 295018#L656-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 295017#L666-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 295016#L667-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 295015#L1317-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 295014#L1317-35 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 295013#L674-33 assume 1 == ~t10_pc~0; 295012#L675-11 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 295010#L685-11 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 295009#L686-11 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 295006#L1325-33 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 295004#L1325-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 295002#L1119-3 assume 1 == ~M_E~0;~M_E~0 := 2; 227624#L1119-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 295001#L1124-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 295000#L1129-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 227616#L1134-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 294999#L1139-3 assume !(1 == ~T5_E~0); 294998#L1144-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 294997#L1149-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 294996#L1154-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 294995#L1159-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 294994#L1164-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 294993#L1169-3 assume !(1 == ~E_1~0); 294992#L1174-3 assume 1 == ~E_2~0;~E_2~0 := 2; 294991#L1179-3 assume !(1 == ~E_3~0); 294990#L1184-3 assume 1 == ~E_4~0;~E_4~0 := 2; 294989#L1189-3 assume 1 == ~E_5~0;~E_5~0 := 2; 294988#L1194-3 assume 1 == ~E_6~0;~E_6~0 := 2; 294987#L1199-3 assume 1 == ~E_7~0;~E_7~0 := 2; 294986#L1204-3 assume 1 == ~E_8~0;~E_8~0 := 2; 294985#L1209-3 assume 1 == ~E_9~0;~E_9~0 := 2; 286729#L1214-3 assume 1 == ~E_10~0;~E_10~0 := 2; 294984#L1219-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 294726#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 294724#L821-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 294722#L822-1 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 294721#L1539 assume !(0 == start_simulation_~tmp~3#1); 294719#L1539-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 293953#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 293947#L821-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 293945#L822-2 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 293943#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 293941#L1501 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 293938#L1502 start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 293936#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 226969#L1520-2 [2021-12-16 10:06:09,576 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:09,576 INFO L85 PathProgramCache]: Analyzing trace with hash -961148493, now seen corresponding path program 1 times [2021-12-16 10:06:09,576 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:09,576 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1653241776] [2021-12-16 10:06:09,576 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:09,577 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:09,588 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:06:09,614 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:06:09,615 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:06:09,615 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1653241776] [2021-12-16 10:06:09,615 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1653241776] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:06:09,615 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:06:09,615 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-16 10:06:09,615 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [380668715] [2021-12-16 10:06:09,616 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:06:09,616 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:06:09,616 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:09,617 INFO L85 PathProgramCache]: Analyzing trace with hash 34123153, now seen corresponding path program 1 times [2021-12-16 10:06:09,617 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:09,617 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [993224580] [2021-12-16 10:06:09,617 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:09,617 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:09,627 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:06:09,648 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:06:09,648 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:06:09,648 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [993224580] [2021-12-16 10:06:09,649 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [993224580] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:06:09,649 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:06:09,649 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:06:09,649 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1910300059] [2021-12-16 10:06:09,649 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:06:09,650 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:06:09,650 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:06:09,650 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-16 10:06:09,650 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-16 10:06:09,651 INFO L87 Difference]: Start difference. First operand 84557 states and 121271 transitions. cyclomatic complexity: 36746 Second operand has 5 states, 5 states have (on average 25.2) internal successors, (126), 5 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:10,791 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:06:10,792 INFO L93 Difference]: Finished difference Result 205317 states and 296636 transitions. [2021-12-16 10:06:10,792 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-16 10:06:10,793 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 205317 states and 296636 transitions. [2021-12-16 10:06:11,929 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 204802 [2021-12-16 10:06:12,903 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 205317 states to 205317 states and 296636 transitions. [2021-12-16 10:06:12,904 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 205317 [2021-12-16 10:06:13,043 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 205317 [2021-12-16 10:06:13,043 INFO L73 IsDeterministic]: Start isDeterministic. Operand 205317 states and 296636 transitions. [2021-12-16 10:06:13,185 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:06:13,186 INFO L681 BuchiCegarLoop]: Abstraction has 205317 states and 296636 transitions. [2021-12-16 10:06:13,312 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 205317 states and 296636 transitions. [2021-12-16 10:06:14,433 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 205317 to 87167. [2021-12-16 10:06:14,519 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 87167 states, 87167 states have (on average 1.4211915059598244) internal successors, (123881), 87166 states have internal predecessors, (123881), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:14,992 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 87167 states to 87167 states and 123881 transitions. [2021-12-16 10:06:14,992 INFO L704 BuchiCegarLoop]: Abstraction has 87167 states and 123881 transitions. [2021-12-16 10:06:14,992 INFO L587 BuchiCegarLoop]: Abstraction has 87167 states and 123881 transitions. [2021-12-16 10:06:14,992 INFO L425 BuchiCegarLoop]: ======== Iteration 17============ [2021-12-16 10:06:14,992 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 87167 states and 123881 transitions. [2021-12-16 10:06:15,213 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 86934 [2021-12-16 10:06:15,214 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:06:15,214 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:06:15,216 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:15,216 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:15,216 INFO L791 eck$LassoCheckResult]: Stem: 504844#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 504845#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 505270#L1483 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 505243#L694 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 505244#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 505302#L701-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 505303#L706-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 504348#L711-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 504055#L716-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 504056#L721-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 505119#L726-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 505120#L731-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 505092#L736-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 505093#L741-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 505154#L746-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 504111#L751-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 504112#L1006 assume !(0 == ~M_E~0); 503956#L1006-2 assume !(0 == ~T1_E~0); 503957#L1011-1 assume !(0 == ~T2_E~0); 505194#L1016-1 assume !(0 == ~T3_E~0); 505224#L1021-1 assume !(0 == ~T4_E~0); 503836#L1026-1 assume !(0 == ~T5_E~0); 503837#L1031-1 assume !(0 == ~T6_E~0); 504779#L1036-1 assume !(0 == ~T7_E~0); 504775#L1041-1 assume !(0 == ~T8_E~0); 504776#L1046-1 assume !(0 == ~T9_E~0); 504146#L1051-1 assume !(0 == ~T10_E~0); 504147#L1056-1 assume !(0 == ~E_1~0); 504939#L1061-1 assume !(0 == ~E_2~0); 504059#L1066-1 assume !(0 == ~E_3~0); 504060#L1071-1 assume !(0 == ~E_4~0); 504912#L1076-1 assume !(0 == ~E_5~0); 503967#L1081-1 assume !(0 == ~E_6~0); 503968#L1086-1 assume !(0 == ~E_7~0); 504321#L1091-1 assume !(0 == ~E_8~0); 505174#L1096-1 assume !(0 == ~E_9~0); 505175#L1101-1 assume !(0 == ~E_10~0); 504391#L1106-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 504392#L484 assume !(1 == ~m_pc~0); 504016#L484-2 is_master_triggered_~__retres1~0#1 := 0; 504015#L495 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 504690#L496 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 505044#L1245 assume !(0 != activate_threads_~tmp~1#1); 505045#L1245-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 504768#L503 assume !(1 == ~t1_pc~0); 504769#L503-2 is_transmit1_triggered_~__retres1~1#1 := 0; 504975#L514 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 504928#L515 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 504519#L1253 assume !(0 != activate_threads_~tmp___0~0#1); 503866#L1253-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 503867#L522 assume !(1 == ~t2_pc~0); 504730#L522-2 is_transmit2_triggered_~__retres1~2#1 := 0; 504076#L533 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 504077#L534 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 504584#L1261 assume !(0 != activate_threads_~tmp___1~0#1); 505121#L1261-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 505235#L541 assume !(1 == ~t3_pc~0); 504455#L541-2 is_transmit3_triggered_~__retres1~3#1 := 0; 504456#L552 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 504255#L553 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 504256#L1269 assume !(0 != activate_threads_~tmp___2~0#1); 504733#L1269-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 504734#L560 assume !(1 == ~t4_pc~0); 503948#L560-2 is_transmit4_triggered_~__retres1~4#1 := 0; 503947#L571 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 504621#L572 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 503834#L1277 assume !(0 != activate_threads_~tmp___3~0#1); 503835#L1277-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 504126#L579 assume !(1 == ~t5_pc~0); 504127#L579-2 is_transmit5_triggered_~__retres1~5#1 := 0; 503894#L590 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 503895#L591 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 504626#L1285 assume !(0 != activate_threads_~tmp___4~0#1); 505221#L1285-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 505265#L598 assume !(1 == ~t6_pc~0); 504952#L598-2 is_transmit6_triggered_~__retres1~6#1 := 0; 504558#L609 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 504559#L610 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 505077#L1293 assume !(0 != activate_threads_~tmp___5~0#1); 504823#L1293-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 504757#L617 assume !(1 == ~t7_pc~0); 504198#L617-2 is_transmit7_triggered_~__retres1~7#1 := 0; 504637#L628 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 505325#L629 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 505139#L1301 assume !(0 != activate_threads_~tmp___6~0#1); 504432#L1301-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 504433#L636 assume 1 == ~t8_pc~0; 504618#L637 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 504619#L647 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 504393#L648 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 504394#L1309 assume !(0 != activate_threads_~tmp___7~0#1); 504568#L1309-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 504569#L655 assume !(1 == ~t9_pc~0); 504598#L655-2 is_transmit9_triggered_~__retres1~9#1 := 0; 504599#L666 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 504178#L667 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 504179#L1317 assume !(0 != activate_threads_~tmp___8~0#1); 504846#L1317-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 504847#L674 assume 1 == ~t10_pc~0; 503943#L675 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 503944#L685 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 505238#L686 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 505334#L1325 assume !(0 != activate_threads_~tmp___9~0#1); 504556#L1325-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 504557#L1119 assume 1 == ~M_E~0;~M_E~0 := 2; 504040#L1119-2 assume !(1 == ~T1_E~0); 504041#L1124-1 assume !(1 == ~T2_E~0); 503858#L1129-1 assume !(1 == ~T3_E~0); 503859#L1134-1 assume !(1 == ~T4_E~0); 504745#L1139-1 assume !(1 == ~T5_E~0); 504427#L1144-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 504428#L1149-1 assume !(1 == ~T7_E~0); 504034#L1154-1 assume !(1 == ~T8_E~0); 504035#L1159-1 assume !(1 == ~T9_E~0); 505339#L1164-1 assume !(1 == ~T10_E~0); 505340#L1169-1 assume !(1 == ~E_1~0); 504467#L1174-1 assume !(1 == ~E_2~0); 504468#L1179-1 assume !(1 == ~E_3~0); 504117#L1184-1 assume 1 == ~E_4~0;~E_4~0 := 2; 504118#L1189-1 assume !(1 == ~E_5~0); 504298#L1194-1 assume !(1 == ~E_6~0); 504299#L1199-1 assume !(1 == ~E_7~0); 504245#L1204-1 assume !(1 == ~E_8~0); 504246#L1209-1 assume !(1 == ~E_9~0); 519537#L1214-1 assume !(1 == ~E_10~0); 519536#L1219-1 assume { :end_inline_reset_delta_events } true; 519533#L1520-2 [2021-12-16 10:06:15,217 INFO L793 eck$LassoCheckResult]: Loop: 519533#L1520-2 assume !false; 519401#L1521 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 519400#L981 assume !false; 545929#L832 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 519379#L764 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 519372#L821 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 519367#L822 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 519360#L836 assume !(0 != eval_~tmp~0#1); 519361#L996 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 520148#L694-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 520146#L1006-3 assume 0 == ~M_E~0;~M_E~0 := 1; 520145#L1006-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 520144#L1011-3 assume !(0 == ~T2_E~0); 520143#L1016-3 assume !(0 == ~T3_E~0); 520142#L1021-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 520141#L1026-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 520140#L1031-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 520139#L1036-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 520138#L1041-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 520137#L1046-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 520133#L1051-3 assume !(0 == ~T10_E~0); 519961#L1056-3 assume !(0 == ~E_1~0); 519959#L1061-3 assume 0 == ~E_2~0;~E_2~0 := 1; 519957#L1066-3 assume 0 == ~E_3~0;~E_3~0 := 1; 519954#L1071-3 assume 0 == ~E_4~0;~E_4~0 := 1; 519952#L1076-3 assume 0 == ~E_5~0;~E_5~0 := 1; 519949#L1081-3 assume 0 == ~E_6~0;~E_6~0 := 1; 519950#L1086-3 assume 0 == ~E_7~0;~E_7~0 := 1; 590079#L1091-3 assume !(0 == ~E_8~0); 590077#L1096-3 assume !(0 == ~E_9~0); 590068#L1101-3 assume 0 == ~E_10~0;~E_10~0 := 1; 590051#L1106-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 569091#L484-33 assume 1 == ~m_pc~0; 569092#L485-11 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 569086#L495-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 569087#L496-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 569082#L1245-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 569083#L1245-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 569078#L503-33 assume !(1 == ~t1_pc~0); 569079#L503-35 is_transmit1_triggered_~__retres1~1#1 := 0; 569074#L514-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 569075#L515-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 569070#L1253-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 569071#L1253-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 569065#L522-33 assume 1 == ~t2_pc~0; 569066#L523-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 569060#L533-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 569061#L534-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 569056#L1261-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 569057#L1261-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 569052#L541-33 assume !(1 == ~t3_pc~0); 569053#L541-35 is_transmit3_triggered_~__retres1~3#1 := 0; 569048#L552-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 569049#L553-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 569044#L1269-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 569045#L1269-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 569039#L560-33 assume !(1 == ~t4_pc~0); 569040#L560-35 is_transmit4_triggered_~__retres1~4#1 := 0; 569034#L571-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 569035#L572-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 569030#L1277-33 assume !(0 != activate_threads_~tmp___3~0#1); 569031#L1277-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 569026#L579-33 assume !(1 == ~t5_pc~0); 569027#L579-35 is_transmit5_triggered_~__retres1~5#1 := 0; 569023#L590-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 569024#L591-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 569019#L1285-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 569020#L1285-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 590020#L598-33 assume !(1 == ~t6_pc~0); 569015#L598-35 is_transmit6_triggered_~__retres1~6#1 := 0; 569013#L609-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 569014#L610-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 590014#L1293-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 519848#L1293-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 519849#L617-33 assume !(1 == ~t7_pc~0); 519843#L617-35 is_transmit7_triggered_~__retres1~7#1 := 0; 519844#L628-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 519835#L629-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 519836#L1301-33 assume !(0 != activate_threads_~tmp___6~0#1); 590012#L1301-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 590011#L636-33 assume !(1 == ~t8_pc~0); 590009#L636-35 is_transmit8_triggered_~__retres1~8#1 := 0; 590008#L647-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 590007#L648-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 590006#L1309-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 590005#L1309-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 590004#L655-33 assume 1 == ~t9_pc~0; 568978#L656-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 568977#L666-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 568976#L667-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 568975#L1317-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 568974#L1317-35 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 568971#L674-33 assume 1 == ~t10_pc~0; 568972#L675-11 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 589998#L685-11 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 589997#L686-11 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 589996#L1325-33 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 589995#L1325-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 589994#L1119-3 assume 1 == ~M_E~0;~M_E~0 := 2; 553321#L1119-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 589993#L1124-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 589992#L1129-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 565289#L1134-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 589991#L1139-3 assume !(1 == ~T5_E~0); 589990#L1144-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 589989#L1149-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 589988#L1154-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 589987#L1159-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 589986#L1164-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 589985#L1169-3 assume !(1 == ~E_1~0); 589984#L1174-3 assume 1 == ~E_2~0;~E_2~0 := 2; 589983#L1179-3 assume !(1 == ~E_3~0); 589982#L1184-3 assume 1 == ~E_4~0;~E_4~0 := 2; 589981#L1189-3 assume 1 == ~E_5~0;~E_5~0 := 2; 589980#L1194-3 assume 1 == ~E_6~0;~E_6~0 := 2; 589979#L1199-3 assume 1 == ~E_7~0;~E_7~0 := 2; 589978#L1204-3 assume 1 == ~E_8~0;~E_8~0 := 2; 589977#L1209-3 assume 1 == ~E_9~0;~E_9~0 := 2; 582596#L1214-3 assume 1 == ~E_10~0;~E_10~0 := 2; 589976#L1219-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 589965#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 589964#L821-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 589963#L822-1 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 589962#L1539 assume !(0 == start_simulation_~tmp~3#1); 589960#L1539-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 589951#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 589944#L821-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 589942#L822-2 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 589940#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 589938#L1501 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 589936#L1502 start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 589934#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 519533#L1520-2 [2021-12-16 10:06:15,217 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:15,217 INFO L85 PathProgramCache]: Analyzing trace with hash -713001999, now seen corresponding path program 1 times [2021-12-16 10:06:15,218 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:15,218 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [970708882] [2021-12-16 10:06:15,218 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:15,218 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:15,228 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:06:15,249 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:06:15,249 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:06:15,249 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [970708882] [2021-12-16 10:06:15,249 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [970708882] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:06:15,249 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:06:15,249 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:06:15,250 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [677454973] [2021-12-16 10:06:15,250 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:06:15,250 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:06:15,250 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:15,251 INFO L85 PathProgramCache]: Analyzing trace with hash -853955604, now seen corresponding path program 1 times [2021-12-16 10:06:15,251 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:15,251 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [124189169] [2021-12-16 10:06:15,251 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:15,251 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:15,260 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:06:15,277 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:06:15,278 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:06:15,278 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [124189169] [2021-12-16 10:06:15,278 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [124189169] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:06:15,278 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:06:15,278 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:06:15,279 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [677370898] [2021-12-16 10:06:15,279 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:06:15,279 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:06:15,279 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:06:15,280 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-16 10:06:15,280 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-16 10:06:15,280 INFO L87 Difference]: Start difference. First operand 87167 states and 123881 transitions. cyclomatic complexity: 36746 Second operand has 4 states, 4 states have (on average 31.5) internal successors, (126), 3 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:16,455 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:06:16,455 INFO L93 Difference]: Finished difference Result 248884 states and 351602 transitions. [2021-12-16 10:06:16,455 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-16 10:06:16,456 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 248884 states and 351602 transitions. [2021-12-16 10:06:17,941 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 247980 [2021-12-16 10:06:18,592 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 248884 states to 248884 states and 351602 transitions. [2021-12-16 10:06:18,592 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 248884 [2021-12-16 10:06:18,718 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 248884 [2021-12-16 10:06:18,718 INFO L73 IsDeterministic]: Start isDeterministic. Operand 248884 states and 351602 transitions. [2021-12-16 10:06:19,168 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:06:19,169 INFO L681 BuchiCegarLoop]: Abstraction has 248884 states and 351602 transitions. [2021-12-16 10:06:19,249 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 248884 states and 351602 transitions. [2021-12-16 10:06:21,284 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 248884 to 247088. [2021-12-16 10:06:21,465 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 247088 states, 247088 states have (on average 1.4135206889853007) internal successors, (349264), 247087 states have internal predecessors, (349264), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:22,577 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 247088 states to 247088 states and 349264 transitions. [2021-12-16 10:06:22,578 INFO L704 BuchiCegarLoop]: Abstraction has 247088 states and 349264 transitions. [2021-12-16 10:06:22,578 INFO L587 BuchiCegarLoop]: Abstraction has 247088 states and 349264 transitions. [2021-12-16 10:06:22,578 INFO L425 BuchiCegarLoop]: ======== Iteration 18============ [2021-12-16 10:06:22,578 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 247088 states and 349264 transitions. [2021-12-16 10:06:23,221 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 246792 [2021-12-16 10:06:23,221 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:06:23,221 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:06:23,223 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:23,223 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:23,223 INFO L791 eck$LassoCheckResult]: Stem: 840888#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 840889#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 841309#L1483 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 841286#L694 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 841287#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 841336#L701-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 841337#L706-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 840400#L711-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 840115#L716-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 840116#L721-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 841162#L726-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 841163#L731-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 841138#L736-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 841139#L741-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 841190#L746-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 840168#L751-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 840169#L1006 assume !(0 == ~M_E~0); 840016#L1006-2 assume !(0 == ~T1_E~0); 840017#L1011-1 assume !(0 == ~T2_E~0); 841239#L1016-1 assume !(0 == ~T3_E~0); 841263#L1021-1 assume !(0 == ~T4_E~0); 839897#L1026-1 assume !(0 == ~T5_E~0); 839898#L1031-1 assume !(0 == ~T6_E~0); 840822#L1036-1 assume !(0 == ~T7_E~0); 840816#L1041-1 assume !(0 == ~T8_E~0); 840817#L1046-1 assume !(0 == ~T9_E~0); 840204#L1051-1 assume !(0 == ~T10_E~0); 840205#L1056-1 assume !(0 == ~E_1~0); 840988#L1061-1 assume !(0 == ~E_2~0); 840119#L1066-1 assume !(0 == ~E_3~0); 840120#L1071-1 assume !(0 == ~E_4~0); 840959#L1076-1 assume !(0 == ~E_5~0); 840027#L1081-1 assume !(0 == ~E_6~0); 840028#L1086-1 assume !(0 == ~E_7~0); 840375#L1091-1 assume !(0 == ~E_8~0); 841216#L1096-1 assume !(0 == ~E_9~0); 841217#L1101-1 assume !(0 == ~E_10~0); 840444#L1106-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 840445#L484 assume !(1 == ~m_pc~0); 840076#L484-2 is_master_triggered_~__retres1~0#1 := 0; 840075#L495 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 840729#L496 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 841089#L1245 assume !(0 != activate_threads_~tmp~1#1); 841090#L1245-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 840809#L503 assume !(1 == ~t1_pc~0); 840810#L503-2 is_transmit1_triggered_~__retres1~1#1 := 0; 841025#L514 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 840976#L515 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 840565#L1253 assume !(0 != activate_threads_~tmp___0~0#1); 839926#L1253-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 839927#L522 assume !(1 == ~t2_pc~0); 840767#L522-2 is_transmit2_triggered_~__retres1~2#1 := 0; 840134#L533 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 840135#L534 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 840630#L1261 assume !(0 != activate_threads_~tmp___1~0#1); 841164#L1261-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 841278#L541 assume !(1 == ~t3_pc~0); 840504#L541-2 is_transmit3_triggered_~__retres1~3#1 := 0; 840505#L552 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 840310#L553 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 840311#L1269 assume !(0 != activate_threads_~tmp___2~0#1); 840770#L1269-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 840771#L560 assume !(1 == ~t4_pc~0); 840008#L560-2 is_transmit4_triggered_~__retres1~4#1 := 0; 840007#L571 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 840662#L572 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 839895#L1277 assume !(0 != activate_threads_~tmp___3~0#1); 839896#L1277-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 840182#L579 assume !(1 == ~t5_pc~0); 840183#L579-2 is_transmit5_triggered_~__retres1~5#1 := 0; 839953#L590 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 839954#L591 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 840665#L1285 assume !(0 != activate_threads_~tmp___4~0#1); 841261#L1285-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 841304#L598 assume !(1 == ~t6_pc~0); 841000#L598-2 is_transmit6_triggered_~__retres1~6#1 := 0; 840603#L609 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 840604#L610 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 841122#L1293 assume !(0 != activate_threads_~tmp___5~0#1); 840867#L1293-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 840799#L617 assume !(1 == ~t7_pc~0); 840255#L617-2 is_transmit7_triggered_~__retres1~7#1 := 0; 840675#L628 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 840550#L629 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 840551#L1301 assume !(0 != activate_threads_~tmp___6~0#1); 840482#L1301-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 840483#L636 assume !(1 == ~t8_pc~0); 840864#L636-2 is_transmit8_triggered_~__retres1~8#1 := 0; 841080#L647 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 840446#L648 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 840447#L1309 assume !(0 != activate_threads_~tmp___7~0#1); 840613#L1309-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 840614#L655 assume !(1 == ~t9_pc~0); 840643#L655-2 is_transmit9_triggered_~__retres1~9#1 := 0; 840644#L666 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 840235#L667 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 840236#L1317 assume !(0 != activate_threads_~tmp___8~0#1); 840890#L1317-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 840891#L674 assume 1 == ~t10_pc~0; 840003#L675 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 840004#L685 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 841281#L686 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 841353#L1325 assume !(0 != activate_threads_~tmp___9~0#1); 840601#L1325-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 840602#L1119 assume 1 == ~M_E~0;~M_E~0 := 2; 840100#L1119-2 assume !(1 == ~T1_E~0); 840101#L1124-1 assume !(1 == ~T2_E~0); 839918#L1129-1 assume !(1 == ~T3_E~0); 839919#L1134-1 assume !(1 == ~T4_E~0); 840237#L1139-1 assume !(1 == ~T5_E~0); 840238#L1144-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 841365#L1149-1 assume !(1 == ~T7_E~0); 841366#L1154-1 assume !(1 == ~T8_E~0); 840186#L1159-1 assume !(1 == ~T9_E~0); 840187#L1164-1 assume !(1 == ~T10_E~0); 840633#L1169-1 assume !(1 == ~E_1~0); 840634#L1174-1 assume !(1 == ~E_2~0); 840291#L1179-1 assume !(1 == ~E_3~0); 840292#L1184-1 assume 1 == ~E_4~0;~E_4~0 := 2; 840231#L1189-1 assume !(1 == ~E_5~0); 840232#L1194-1 assume !(1 == ~E_6~0); 841371#L1199-1 assume !(1 == ~E_7~0); 841372#L1204-1 assume !(1 == ~E_8~0); 841323#L1209-1 assume !(1 == ~E_9~0); 841324#L1214-1 assume !(1 == ~E_10~0); 841355#L1219-1 assume { :end_inline_reset_delta_events } true; 841356#L1520-2 [2021-12-16 10:06:23,224 INFO L793 eck$LassoCheckResult]: Loop: 841356#L1520-2 assume !false; 1065347#L1521 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1065345#L981 assume !false; 1065344#L832 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 1065335#L764 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 1065332#L821 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 1065331#L822 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1065329#L836 assume !(0 != eval_~tmp~0#1); 1065330#L996 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1065758#L694-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1065757#L1006-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1065756#L1006-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1065755#L1011-3 assume !(0 == ~T2_E~0); 1065754#L1016-3 assume !(0 == ~T3_E~0); 1065753#L1021-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1065752#L1026-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1065751#L1031-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1065750#L1036-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1065749#L1041-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1065748#L1046-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1065747#L1051-3 assume !(0 == ~T10_E~0); 1065746#L1056-3 assume !(0 == ~E_1~0); 1065745#L1061-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1065744#L1066-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1065743#L1071-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1065742#L1076-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1065741#L1081-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1065740#L1086-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1065739#L1091-3 assume !(0 == ~E_8~0); 1065738#L1096-3 assume !(0 == ~E_9~0); 1065737#L1101-3 assume 0 == ~E_10~0;~E_10~0 := 1; 1065736#L1106-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1065735#L484-33 assume 1 == ~m_pc~0; 1065733#L485-11 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1065732#L495-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1065731#L496-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1065730#L1245-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1065729#L1245-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1065728#L503-33 assume !(1 == ~t1_pc~0); 1065727#L503-35 is_transmit1_triggered_~__retres1~1#1 := 0; 1065726#L514-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1065725#L515-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1065724#L1253-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1065723#L1253-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1065722#L522-33 assume 1 == ~t2_pc~0; 1065720#L523-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1065719#L533-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1065718#L534-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1065717#L1261-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1065716#L1261-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1065715#L541-33 assume !(1 == ~t3_pc~0); 1065714#L541-35 is_transmit3_triggered_~__retres1~3#1 := 0; 1065713#L552-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1065712#L553-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1065711#L1269-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1065710#L1269-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1065709#L560-33 assume 1 == ~t4_pc~0; 1065707#L561-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1065706#L571-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1065705#L572-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1065704#L1277-33 assume !(0 != activate_threads_~tmp___3~0#1); 1065703#L1277-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1065702#L579-33 assume !(1 == ~t5_pc~0); 1065701#L579-35 is_transmit5_triggered_~__retres1~5#1 := 0; 1065700#L590-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1065699#L591-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1065698#L1285-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1065697#L1285-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1065696#L598-33 assume !(1 == ~t6_pc~0); 1065695#L598-35 is_transmit6_triggered_~__retres1~6#1 := 0; 1065694#L609-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1065693#L610-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1065692#L1293-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1065691#L1293-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1065690#L617-33 assume !(1 == ~t7_pc~0); 1065687#L617-35 is_transmit7_triggered_~__retres1~7#1 := 0; 1065686#L628-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1065685#L629-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1065684#L1301-33 assume !(0 != activate_threads_~tmp___6~0#1); 1065682#L1301-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1065681#L636-33 assume !(1 == ~t8_pc~0); 1065680#L636-35 is_transmit8_triggered_~__retres1~8#1 := 0; 1065679#L647-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1065678#L648-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1065677#L1309-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1065676#L1309-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1065675#L655-33 assume 1 == ~t9_pc~0; 1065673#L656-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1065672#L666-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1065671#L667-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1065670#L1317-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1065669#L1317-35 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1065668#L674-33 assume !(1 == ~t10_pc~0); 1065666#L674-35 is_transmit10_triggered_~__retres1~10#1 := 0; 1065665#L685-11 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1065664#L686-11 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1065663#L1325-33 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1065662#L1325-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1065661#L1119-3 assume 1 == ~M_E~0;~M_E~0 := 2; 894796#L1119-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1065660#L1124-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1065659#L1129-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1039149#L1134-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1065658#L1139-3 assume !(1 == ~T5_E~0); 1065657#L1144-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1065656#L1149-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1065655#L1154-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1065654#L1159-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1065653#L1164-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 1065652#L1169-3 assume !(1 == ~E_1~0); 1065651#L1174-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1065650#L1179-3 assume !(1 == ~E_3~0); 1065649#L1184-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1065648#L1189-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1065647#L1194-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1065646#L1199-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1065645#L1204-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1065644#L1209-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1008777#L1214-3 assume 1 == ~E_10~0;~E_10~0 := 2; 1065643#L1219-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 1065632#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 1065631#L821-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 1065630#L822-1 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 1065629#L1539 assume !(0 == start_simulation_~tmp~3#1); 1065627#L1539-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 1065620#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 1065615#L821-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 1065614#L822-2 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 1065613#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1065612#L1501 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1065611#L1502 start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 1065610#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 841356#L1520-2 [2021-12-16 10:06:23,225 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:23,225 INFO L85 PathProgramCache]: Analyzing trace with hash -313010800, now seen corresponding path program 1 times [2021-12-16 10:06:23,225 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:23,225 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1308919793] [2021-12-16 10:06:23,225 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:23,225 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:23,235 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:06:23,260 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:06:23,261 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:06:23,261 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1308919793] [2021-12-16 10:06:23,261 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1308919793] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:06:23,261 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:06:23,261 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:06:23,261 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [341581545] [2021-12-16 10:06:23,262 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:06:23,262 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:06:23,262 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:23,262 INFO L85 PathProgramCache]: Analyzing trace with hash -533082260, now seen corresponding path program 1 times [2021-12-16 10:06:23,263 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:23,263 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1763271484] [2021-12-16 10:06:23,263 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:23,263 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:23,275 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:06:23,293 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:06:23,293 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:06:23,293 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1763271484] [2021-12-16 10:06:23,294 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1763271484] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:06:23,294 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:06:23,294 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:06:23,294 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1554033239] [2021-12-16 10:06:23,294 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:06:23,295 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:06:23,295 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:06:23,296 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-16 10:06:23,296 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-16 10:06:23,296 INFO L87 Difference]: Start difference. First operand 247088 states and 349264 transitions. cyclomatic complexity: 102240 Second operand has 4 states, 4 states have (on average 31.5) internal successors, (126), 3 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:26,449 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:06:26,450 INFO L93 Difference]: Finished difference Result 729049 states and 1023207 transitions. [2021-12-16 10:06:26,450 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-16 10:06:26,450 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 729049 states and 1023207 transitions. [2021-12-16 10:06:30,470 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 726962 [2021-12-16 10:06:32,717 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 729049 states to 729049 states and 1023207 transitions. [2021-12-16 10:06:32,717 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 729049 [2021-12-16 10:06:32,995 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 729049 [2021-12-16 10:06:32,996 INFO L73 IsDeterministic]: Start isDeterministic. Operand 729049 states and 1023207 transitions. [2021-12-16 10:06:33,277 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:06:33,277 INFO L681 BuchiCegarLoop]: Abstraction has 729049 states and 1023207 transitions. [2021-12-16 10:06:33,614 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 729049 states and 1023207 transitions. [2021-12-16 10:06:40,139 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 729049 to 726737. [2021-12-16 10:06:40,766 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 726737 states, 726737 states have (on average 1.403708631870952) internal successors, (1020127), 726736 states have internal predecessors, (1020127), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)