./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/transmitter.13.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version c3fed411 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/transmitter.13.cil.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 5975f0f3825b3a6653676f33bd69d14e1e58fcf0306bfb5508ab91dc8951d6c4 --- Real Ultimate output --- This is Ultimate 0.2.2-tmp.no-commuhash-c3fed41 [2021-12-16 10:06:06,536 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-12-16 10:06:06,538 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-12-16 10:06:06,567 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-12-16 10:06:06,569 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-12-16 10:06:06,571 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-12-16 10:06:06,573 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-12-16 10:06:06,577 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-12-16 10:06:06,578 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-12-16 10:06:06,583 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-12-16 10:06:06,584 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-12-16 10:06:06,584 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-12-16 10:06:06,585 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-12-16 10:06:06,586 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-12-16 10:06:06,588 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-12-16 10:06:06,588 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-12-16 10:06:06,591 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-12-16 10:06:06,592 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-12-16 10:06:06,593 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-12-16 10:06:06,595 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-12-16 10:06:06,598 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-12-16 10:06:06,599 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-12-16 10:06:06,599 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-12-16 10:06:06,600 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-12-16 10:06:06,601 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-12-16 10:06:06,602 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-12-16 10:06:06,602 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-12-16 10:06:06,603 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-12-16 10:06:06,603 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-12-16 10:06:06,604 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-12-16 10:06:06,604 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-12-16 10:06:06,605 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-12-16 10:06:06,605 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-12-16 10:06:06,606 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-12-16 10:06:06,607 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-12-16 10:06:06,607 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-12-16 10:06:06,607 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-12-16 10:06:06,608 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-12-16 10:06:06,608 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-12-16 10:06:06,608 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-12-16 10:06:06,609 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-12-16 10:06:06,609 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2021-12-16 10:06:06,632 INFO L113 SettingsManager]: Loading preferences was successful [2021-12-16 10:06:06,633 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-12-16 10:06:06,633 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2021-12-16 10:06:06,633 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2021-12-16 10:06:06,634 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-12-16 10:06:06,634 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-12-16 10:06:06,635 INFO L138 SettingsManager]: * Use SBE=true [2021-12-16 10:06:06,635 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2021-12-16 10:06:06,635 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2021-12-16 10:06:06,635 INFO L138 SettingsManager]: * Use old map elimination=false [2021-12-16 10:06:06,636 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2021-12-16 10:06:06,636 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2021-12-16 10:06:06,636 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2021-12-16 10:06:06,636 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-12-16 10:06:06,636 INFO L138 SettingsManager]: * sizeof long=4 [2021-12-16 10:06:06,636 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2021-12-16 10:06:06,637 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-12-16 10:06:06,637 INFO L138 SettingsManager]: * sizeof POINTER=4 [2021-12-16 10:06:06,637 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-12-16 10:06:06,637 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2021-12-16 10:06:06,637 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2021-12-16 10:06:06,637 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2021-12-16 10:06:06,637 INFO L138 SettingsManager]: * sizeof long double=12 [2021-12-16 10:06:06,637 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-12-16 10:06:06,639 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2021-12-16 10:06:06,639 INFO L138 SettingsManager]: * Use constant arrays=true [2021-12-16 10:06:06,639 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2021-12-16 10:06:06,639 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-12-16 10:06:06,639 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-12-16 10:06:06,639 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-12-16 10:06:06,640 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-12-16 10:06:06,640 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2021-12-16 10:06:06,640 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2021-12-16 10:06:06,640 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 5975f0f3825b3a6653676f33bd69d14e1e58fcf0306bfb5508ab91dc8951d6c4 [2021-12-16 10:06:06,827 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-12-16 10:06:06,845 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-12-16 10:06:06,847 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-12-16 10:06:06,847 INFO L271 PluginConnector]: Initializing CDTParser... [2021-12-16 10:06:06,848 INFO L275 PluginConnector]: CDTParser initialized [2021-12-16 10:06:06,849 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/transmitter.13.cil.c [2021-12-16 10:06:06,920 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/f47b4e2d1/25b7eb506f654c308936dd98d48b7ef7/FLAG0dfdf63d4 [2021-12-16 10:06:07,280 INFO L306 CDTParser]: Found 1 translation units. [2021-12-16 10:06:07,280 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.13.cil.c [2021-12-16 10:06:07,293 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/f47b4e2d1/25b7eb506f654c308936dd98d48b7ef7/FLAG0dfdf63d4 [2021-12-16 10:06:07,677 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/f47b4e2d1/25b7eb506f654c308936dd98d48b7ef7 [2021-12-16 10:06:07,679 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-12-16 10:06:07,680 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-12-16 10:06:07,681 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-12-16 10:06:07,681 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-12-16 10:06:07,689 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-12-16 10:06:07,690 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 16.12 10:06:07" (1/1) ... [2021-12-16 10:06:07,690 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@1aa5c1a2 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:06:07, skipping insertion in model container [2021-12-16 10:06:07,690 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 16.12 10:06:07" (1/1) ... [2021-12-16 10:06:07,696 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-12-16 10:06:07,728 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-12-16 10:06:07,848 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.13.cil.c[706,719] [2021-12-16 10:06:07,949 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-16 10:06:07,962 INFO L203 MainTranslator]: Completed pre-run [2021-12-16 10:06:07,981 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.13.cil.c[706,719] [2021-12-16 10:06:08,019 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-16 10:06:08,031 INFO L208 MainTranslator]: Completed translation [2021-12-16 10:06:08,031 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:06:08 WrapperNode [2021-12-16 10:06:08,032 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-12-16 10:06:08,032 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-12-16 10:06:08,033 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-12-16 10:06:08,033 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-12-16 10:06:08,037 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:06:08" (1/1) ... [2021-12-16 10:06:08,049 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:06:08" (1/1) ... [2021-12-16 10:06:08,123 INFO L137 Inliner]: procedures = 54, calls = 69, calls flagged for inlining = 64, calls inlined = 286, statements flattened = 4413 [2021-12-16 10:06:08,123 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-12-16 10:06:08,124 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-12-16 10:06:08,124 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-12-16 10:06:08,124 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-12-16 10:06:08,130 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:06:08" (1/1) ... [2021-12-16 10:06:08,131 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:06:08" (1/1) ... [2021-12-16 10:06:08,138 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:06:08" (1/1) ... [2021-12-16 10:06:08,138 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:06:08" (1/1) ... [2021-12-16 10:06:08,168 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:06:08" (1/1) ... [2021-12-16 10:06:08,193 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:06:08" (1/1) ... [2021-12-16 10:06:08,199 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:06:08" (1/1) ... [2021-12-16 10:06:08,209 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-12-16 10:06:08,210 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-12-16 10:06:08,210 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-12-16 10:06:08,210 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-12-16 10:06:08,211 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:06:08" (1/1) ... [2021-12-16 10:06:08,215 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-16 10:06:08,231 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-16 10:06:08,251 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-16 10:06:08,293 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2021-12-16 10:06:08,293 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2021-12-16 10:06:08,293 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-12-16 10:06:08,293 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-12-16 10:06:08,280 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2021-12-16 10:06:08,438 INFO L236 CfgBuilder]: Building ICFG [2021-12-16 10:06:08,439 INFO L262 CfgBuilder]: Building CFG for each procedure with an implementation [2021-12-16 10:06:10,122 INFO L277 CfgBuilder]: Performing block encoding [2021-12-16 10:06:10,135 INFO L296 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-12-16 10:06:10,135 INFO L301 CfgBuilder]: Removed 17 assume(true) statements. [2021-12-16 10:06:10,138 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 16.12 10:06:10 BoogieIcfgContainer [2021-12-16 10:06:10,138 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-12-16 10:06:10,139 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2021-12-16 10:06:10,139 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2021-12-16 10:06:10,141 INFO L275 PluginConnector]: BuchiAutomizer initialized [2021-12-16 10:06:10,142 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-16 10:06:10,142 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 16.12 10:06:07" (1/3) ... [2021-12-16 10:06:10,143 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@6243979 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 16.12 10:06:10, skipping insertion in model container [2021-12-16 10:06:10,143 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-16 10:06:10,143 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:06:08" (2/3) ... [2021-12-16 10:06:10,144 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@6243979 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 16.12 10:06:10, skipping insertion in model container [2021-12-16 10:06:10,144 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-16 10:06:10,144 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 16.12 10:06:10" (3/3) ... [2021-12-16 10:06:10,145 INFO L388 chiAutomizerObserver]: Analyzing ICFG transmitter.13.cil.c [2021-12-16 10:06:10,173 INFO L359 BuchiCegarLoop]: Interprodecural is true [2021-12-16 10:06:10,173 INFO L360 BuchiCegarLoop]: Hoare is false [2021-12-16 10:06:10,173 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2021-12-16 10:06:10,173 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2021-12-16 10:06:10,173 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2021-12-16 10:06:10,173 INFO L364 BuchiCegarLoop]: Difference is false [2021-12-16 10:06:10,174 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2021-12-16 10:06:10,174 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2021-12-16 10:06:10,209 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1921 states, 1920 states have (on average 1.4984375) internal successors, (2877), 1920 states have internal predecessors, (2877), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:10,262 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1744 [2021-12-16 10:06:10,263 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:06:10,263 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:06:10,314 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:10,314 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:10,315 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2021-12-16 10:06:10,318 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1921 states, 1920 states have (on average 1.4984375) internal successors, (2877), 1920 states have internal predecessors, (2877), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:10,330 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1744 [2021-12-16 10:06:10,331 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:06:10,331 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:06:10,334 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:10,334 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:10,340 INFO L791 eck$LassoCheckResult]: Stem: 461#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 1834#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 352#L1855true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 201#L874true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1760#L881true assume !(1 == ~m_i~0);~m_st~0 := 2; 1073#L881-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 1411#L886-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 272#L891-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1402#L896-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 545#L901-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 439#L906-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 796#L911-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 306#L916-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 554#L921-1true assume 1 == ~t9_i~0;~t9_st~0 := 0; 684#L926-1true assume !(1 == ~t10_i~0);~t10_st~0 := 2; 804#L931-1true assume !(1 == ~t11_i~0);~t11_st~0 := 2; 834#L936-1true assume !(1 == ~t12_i~0);~t12_st~0 := 2; 921#L941-1true assume !(1 == ~t13_i~0);~t13_st~0 := 2; 313#L946-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1815#L1258true assume 0 == ~M_E~0;~M_E~0 := 1; 1400#L1258-2true assume !(0 == ~T1_E~0); 490#L1263-1true assume !(0 == ~T2_E~0); 710#L1268-1true assume !(0 == ~T3_E~0); 1366#L1273-1true assume !(0 == ~T4_E~0); 1749#L1278-1true assume !(0 == ~T5_E~0); 1153#L1283-1true assume !(0 == ~T6_E~0); 1781#L1288-1true assume !(0 == ~T7_E~0); 1569#L1293-1true assume 0 == ~T8_E~0;~T8_E~0 := 1; 1540#L1298-1true assume !(0 == ~T9_E~0); 1384#L1303-1true assume !(0 == ~T10_E~0); 215#L1308-1true assume !(0 == ~T11_E~0); 186#L1313-1true assume !(0 == ~T12_E~0); 1839#L1318-1true assume !(0 == ~T13_E~0); 189#L1323-1true assume !(0 == ~E_1~0); 277#L1328-1true assume !(0 == ~E_2~0); 1790#L1333-1true assume 0 == ~E_3~0;~E_3~0 := 1; 974#L1338-1true assume !(0 == ~E_4~0); 1113#L1343-1true assume !(0 == ~E_5~0); 1651#L1348-1true assume !(0 == ~E_6~0); 1668#L1353-1true assume !(0 == ~E_7~0); 726#L1358-1true assume !(0 == ~E_8~0); 1000#L1363-1true assume !(0 == ~E_9~0); 1062#L1368-1true assume !(0 == ~E_10~0); 105#L1373-1true assume 0 == ~E_11~0;~E_11~0 := 1; 489#L1378-1true assume !(0 == ~E_12~0); 250#L1383-1true assume !(0 == ~E_13~0); 1102#L1388-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 730#L607true assume 1 == ~m_pc~0; 1010#L608true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1109#L618true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1627#L619true activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 668#L1560true assume !(0 != activate_threads_~tmp~1#1); 1725#L1560-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 196#L626true assume !(1 == ~t1_pc~0); 1267#L626-2true is_transmit1_triggered_~__retres1~1#1 := 0; 339#L637true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 441#L638true activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1908#L1568true assume !(0 != activate_threads_~tmp___0~0#1); 147#L1568-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1337#L645true assume 1 == ~t2_pc~0; 205#L646true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1301#L656true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 584#L657true activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1900#L1576true assume !(0 != activate_threads_~tmp___1~0#1); 653#L1576-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1705#L664true assume 1 == ~t3_pc~0; 1634#L665true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 66#L675true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1127#L676true activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 417#L1584true assume !(0 != activate_threads_~tmp___2~0#1); 1420#L1584-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1628#L683true assume !(1 == ~t4_pc~0); 987#L683-2true is_transmit4_triggered_~__retres1~4#1 := 0; 786#L694true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 811#L695true activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1695#L1592true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 932#L1592-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 615#L702true assume 1 == ~t5_pc~0; 1685#L703true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 926#L713true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1344#L714true activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1392#L1600true assume !(0 != activate_threads_~tmp___4~0#1); 1238#L1600-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 90#L721true assume !(1 == ~t6_pc~0); 77#L721-2true is_transmit6_triggered_~__retres1~6#1 := 0; 161#L732true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 557#L733true activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 422#L1608true assume !(0 != activate_threads_~tmp___5~0#1); 1525#L1608-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 868#L740true assume 1 == ~t7_pc~0; 116#L741true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 21#L751true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 758#L752true activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 16#L1616true assume !(0 != activate_threads_~tmp___6~0#1); 763#L1616-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 385#L759true assume !(1 == ~t8_pc~0); 1374#L759-2true is_transmit8_triggered_~__retres1~8#1 := 0; 1844#L770true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 924#L771true activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1084#L1624true assume !(0 != activate_threads_~tmp___7~0#1); 1671#L1624-2true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1568#L778true assume 1 == ~t9_pc~0; 1342#L779true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1274#L789true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 73#L790true activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 36#L1632true assume !(0 != activate_threads_~tmp___8~0#1); 734#L1632-2true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 203#L797true assume !(1 == ~t10_pc~0); 265#L797-2true is_transmit10_triggered_~__retres1~10#1 := 0; 1307#L808true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1182#L809true activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 488#L1640true assume !(0 != activate_threads_~tmp___9~0#1); 697#L1640-2true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1391#L816true assume 1 == ~t11_pc~0; 57#L817true assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 588#L827true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 463#L828true activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 427#L1648true assume !(0 != activate_threads_~tmp___10~0#1); 1512#L1648-2true assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 803#L835true assume 1 == ~t12_pc~0; 706#L836true assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 151#L846true is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 222#L847true activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1784#L1656true assume !(0 != activate_threads_~tmp___11~0#1); 527#L1656-2true assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 1443#L854true assume !(1 == ~t13_pc~0); 307#L854-2true is_transmit13_triggered_~__retres1~13#1 := 0; 336#L865true is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 1082#L866true activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 160#L1664true assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 1231#L1664-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1791#L1401true assume !(1 == ~M_E~0); 419#L1401-2true assume !(1 == ~T1_E~0); 1241#L1406-1true assume !(1 == ~T2_E~0); 859#L1411-1true assume !(1 == ~T3_E~0); 1612#L1416-1true assume 1 == ~T4_E~0;~T4_E~0 := 2; 595#L1421-1true assume !(1 == ~T5_E~0); 305#L1426-1true assume !(1 == ~T6_E~0); 1015#L1431-1true assume !(1 == ~T7_E~0); 75#L1436-1true assume !(1 == ~T8_E~0); 746#L1441-1true assume !(1 == ~T9_E~0); 483#L1446-1true assume !(1 == ~T10_E~0); 1773#L1451-1true assume !(1 == ~T11_E~0); 1108#L1456-1true assume 1 == ~T12_E~0;~T12_E~0 := 2; 745#L1461-1true assume !(1 == ~T13_E~0); 436#L1466-1true assume !(1 == ~E_1~0); 1768#L1471-1true assume !(1 == ~E_2~0); 1083#L1476-1true assume !(1 == ~E_3~0); 1315#L1481-1true assume !(1 == ~E_4~0); 1593#L1486-1true assume !(1 == ~E_5~0); 225#L1491-1true assume !(1 == ~E_6~0); 42#L1496-1true assume 1 == ~E_7~0;~E_7~0 := 2; 757#L1501-1true assume !(1 == ~E_8~0); 481#L1506-1true assume !(1 == ~E_9~0); 1038#L1511-1true assume !(1 == ~E_10~0); 454#L1516-1true assume !(1 == ~E_11~0); 14#L1521-1true assume !(1 == ~E_12~0); 41#L1526-1true assume !(1 == ~E_13~0); 319#L1531-1true assume { :end_inline_reset_delta_events } true; 1172#L1892-2true [2021-12-16 10:06:10,342 INFO L793 eck$LassoCheckResult]: Loop: 1172#L1892-2true assume !false; 1868#L1893true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1514#L1233true assume !true; 81#L1248true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 805#L874-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1630#L1258-3true assume 0 == ~M_E~0;~M_E~0 := 1; 1899#L1258-5true assume !(0 == ~T1_E~0); 154#L1263-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 1604#L1268-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 1619#L1273-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 1906#L1278-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 1621#L1283-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 267#L1288-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 1789#L1293-3true assume 0 == ~T8_E~0;~T8_E~0 := 1; 1169#L1298-3true assume !(0 == ~T9_E~0); 1694#L1303-3true assume 0 == ~T10_E~0;~T10_E~0 := 1; 1428#L1308-3true assume 0 == ~T11_E~0;~T11_E~0 := 1; 1168#L1313-3true assume 0 == ~T12_E~0;~T12_E~0 := 1; 659#L1318-3true assume 0 == ~T13_E~0;~T13_E~0 := 1; 155#L1323-3true assume 0 == ~E_1~0;~E_1~0 := 1; 1302#L1328-3true assume 0 == ~E_2~0;~E_2~0 := 1; 1673#L1333-3true assume 0 == ~E_3~0;~E_3~0 := 1; 229#L1338-3true assume !(0 == ~E_4~0); 1056#L1343-3true assume 0 == ~E_5~0;~E_5~0 := 1; 1541#L1348-3true assume 0 == ~E_6~0;~E_6~0 := 1; 1312#L1353-3true assume 0 == ~E_7~0;~E_7~0 := 1; 1353#L1358-3true assume 0 == ~E_8~0;~E_8~0 := 1; 627#L1363-3true assume 0 == ~E_9~0;~E_9~0 := 1; 340#L1368-3true assume 0 == ~E_10~0;~E_10~0 := 1; 1885#L1373-3true assume 0 == ~E_11~0;~E_11~0 := 1; 885#L1378-3true assume !(0 == ~E_12~0); 1460#L1383-3true assume 0 == ~E_13~0;~E_13~0 := 1; 1100#L1388-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1767#L607-42true assume !(1 == ~m_pc~0); 912#L607-44true is_master_triggered_~__retres1~0#1 := 0; 510#L618-14true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1076#L619-14true activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 349#L1560-42true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 698#L1560-44true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1220#L626-42true assume 1 == ~t1_pc~0; 399#L627-14true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1472#L637-14true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 600#L638-14true activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1131#L1568-42true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 171#L1568-44true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1574#L645-42true assume !(1 == ~t2_pc~0); 1024#L645-44true is_transmit2_triggered_~__retres1~2#1 := 0; 1696#L656-14true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1253#L657-14true activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 278#L1576-42true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 24#L1576-44true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1662#L664-42true assume 1 == ~t3_pc~0; 457#L665-14true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1624#L675-14true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1475#L676-14true activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 833#L1584-42true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1016#L1584-44true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1788#L683-42true assume !(1 == ~t4_pc~0); 732#L683-44true is_transmit4_triggered_~__retres1~4#1 := 0; 841#L694-14true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1769#L695-14true activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1412#L1592-42true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1904#L1592-44true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1163#L702-42true assume !(1 == ~t5_pc~0); 395#L702-44true is_transmit5_triggered_~__retres1~5#1 := 0; 590#L713-14true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1734#L714-14true activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1288#L1600-42true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 33#L1600-44true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 114#L721-42true assume !(1 == ~t6_pc~0); 1582#L721-44true is_transmit6_triggered_~__retres1~6#1 := 0; 368#L732-14true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1620#L733-14true activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1588#L1608-42true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 470#L1608-44true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 379#L740-42true assume !(1 == ~t7_pc~0); 236#L740-44true is_transmit7_triggered_~__retres1~7#1 := 0; 561#L751-14true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 560#L752-14true activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 459#L1616-42true assume !(0 != activate_threads_~tmp___6~0#1); 651#L1616-44true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1896#L759-42true assume 1 == ~t8_pc~0; 540#L760-14true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 493#L770-14true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 674#L771-14true activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 547#L1624-42true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 617#L1624-44true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1175#L778-42true assume !(1 == ~t9_pc~0); 620#L778-44true is_transmit9_triggered_~__retres1~9#1 := 0; 809#L789-14true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1750#L790-14true activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 733#L1632-42true assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1613#L1632-44true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 781#L797-42true assume 1 == ~t10_pc~0; 239#L798-14true assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 938#L808-14true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1376#L809-14true activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1877#L1640-42true assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 810#L1640-44true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1709#L816-42true assume !(1 == ~t11_pc~0); 347#L816-44true is_transmit11_triggered_~__retres1~11#1 := 0; 1852#L827-14true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 285#L828-14true activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 486#L1648-42true assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 328#L1648-44true assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 587#L835-42true assume 1 == ~t12_pc~0; 846#L836-14true assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 1244#L846-14true is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 314#L847-14true activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1838#L1656-42true assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 1237#L1656-44true assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 950#L854-42true assume 1 == ~t13_pc~0; 1782#L855-14true assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 482#L865-14true is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 86#L866-14true activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 515#L1664-42true assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 435#L1664-44true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1855#L1401-3true assume 1 == ~M_E~0;~M_E~0 := 2; 1094#L1401-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 204#L1406-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 136#L1411-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 1680#L1416-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 465#L1421-3true assume !(1 == ~T5_E~0); 1053#L1426-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 228#L1431-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 293#L1436-3true assume 1 == ~T8_E~0;~T8_E~0 := 2; 17#L1441-3true assume 1 == ~T9_E~0;~T9_E~0 := 2; 1145#L1446-3true assume 1 == ~T10_E~0;~T10_E~0 := 2; 1136#L1451-3true assume 1 == ~T11_E~0;~T11_E~0 := 2; 521#L1456-3true assume 1 == ~T12_E~0;~T12_E~0 := 2; 309#L1461-3true assume !(1 == ~T13_E~0); 1611#L1466-3true assume 1 == ~E_1~0;~E_1~0 := 2; 1817#L1471-3true assume 1 == ~E_2~0;~E_2~0 := 2; 279#L1476-3true assume 1 == ~E_3~0;~E_3~0 := 2; 1687#L1481-3true assume 1 == ~E_4~0;~E_4~0 := 2; 514#L1486-3true assume 1 == ~E_5~0;~E_5~0 := 2; 292#L1491-3true assume 1 == ~E_6~0;~E_6~0 := 2; 1482#L1496-3true assume 1 == ~E_7~0;~E_7~0 := 2; 544#L1501-3true assume !(1 == ~E_8~0); 1595#L1506-3true assume 1 == ~E_9~0;~E_9~0 := 2; 882#L1511-3true assume 1 == ~E_10~0;~E_10~0 := 2; 875#L1516-3true assume 1 == ~E_11~0;~E_11~0 := 2; 1719#L1521-3true assume 1 == ~E_12~0;~E_12~0 := 2; 630#L1526-3true assume 1 == ~E_13~0;~E_13~0 := 2; 970#L1531-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 1843#L959-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 1881#L1031-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 761#L1032-1true start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 494#L1911true assume !(0 == start_simulation_~tmp~3#1); 1305#L1911-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 907#L959-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 1025#L1031-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 843#L1032-2true stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 107#L1866true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 520#L1873true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 224#L1874true start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 1349#L1924true assume !(0 != start_simulation_~tmp___0~1#1); 1172#L1892-2true [2021-12-16 10:06:10,347 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:10,347 INFO L85 PathProgramCache]: Analyzing trace with hash 517365666, now seen corresponding path program 1 times [2021-12-16 10:06:10,353 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:10,353 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1590447968] [2021-12-16 10:06:10,353 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:10,354 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:10,456 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:06:10,543 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:06:10,544 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:06:10,544 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1590447968] [2021-12-16 10:06:10,545 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1590447968] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:06:10,545 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:06:10,545 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:06:10,546 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1071116945] [2021-12-16 10:06:10,560 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:06:10,563 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:06:10,563 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:10,564 INFO L85 PathProgramCache]: Analyzing trace with hash -1573044070, now seen corresponding path program 1 times [2021-12-16 10:06:10,564 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:10,564 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1489469614] [2021-12-16 10:06:10,565 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:10,565 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:10,574 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:06:10,617 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:06:10,618 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:06:10,618 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1489469614] [2021-12-16 10:06:10,618 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1489469614] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:06:10,618 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:06:10,618 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-16 10:06:10,619 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [261432956] [2021-12-16 10:06:10,619 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:06:10,620 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:06:10,620 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:06:10,643 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2021-12-16 10:06:10,644 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2021-12-16 10:06:10,648 INFO L87 Difference]: Start difference. First operand has 1921 states, 1920 states have (on average 1.4984375) internal successors, (2877), 1920 states have internal predecessors, (2877), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 2 states, 2 states have (on average 78.5) internal successors, (157), 2 states have internal predecessors, (157), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:10,718 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:06:10,719 INFO L93 Difference]: Finished difference Result 1920 states and 2841 transitions. [2021-12-16 10:06:10,720 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2021-12-16 10:06:10,723 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1920 states and 2841 transitions. [2021-12-16 10:06:10,734 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2021-12-16 10:06:10,746 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1920 states to 1914 states and 2835 transitions. [2021-12-16 10:06:10,747 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1914 [2021-12-16 10:06:10,748 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1914 [2021-12-16 10:06:10,749 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1914 states and 2835 transitions. [2021-12-16 10:06:10,753 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:06:10,753 INFO L681 BuchiCegarLoop]: Abstraction has 1914 states and 2835 transitions. [2021-12-16 10:06:10,766 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1914 states and 2835 transitions. [2021-12-16 10:06:10,805 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1914 to 1914. [2021-12-16 10:06:10,808 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1914 states, 1914 states have (on average 1.4811912225705328) internal successors, (2835), 1913 states have internal predecessors, (2835), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:10,812 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1914 states to 1914 states and 2835 transitions. [2021-12-16 10:06:10,813 INFO L704 BuchiCegarLoop]: Abstraction has 1914 states and 2835 transitions. [2021-12-16 10:06:10,813 INFO L587 BuchiCegarLoop]: Abstraction has 1914 states and 2835 transitions. [2021-12-16 10:06:10,813 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2021-12-16 10:06:10,813 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1914 states and 2835 transitions. [2021-12-16 10:06:10,820 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2021-12-16 10:06:10,820 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:06:10,820 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:06:10,822 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:10,822 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:10,823 INFO L791 eck$LassoCheckResult]: Stem: 4711#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 4712#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 4531#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4247#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4248#L881 assume !(1 == ~m_i~0);~m_st~0 := 2; 5424#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5425#L886-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 4383#L891-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 4384#L896-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 4838#L901-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 4673#L906-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 4674#L911-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 4450#L916-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 4451#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 4849#L926-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 5026#L931-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 5180#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 5217#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 4461#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4462#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 5637#L1258-2 assume !(0 == ~T1_E~0); 4756#L1263-1 assume !(0 == ~T2_E~0); 4757#L1268-1 assume !(0 == ~T3_E~0); 5060#L1273-1 assume !(0 == ~T4_E~0); 5619#L1278-1 assume !(0 == ~T5_E~0); 5480#L1283-1 assume !(0 == ~T6_E~0); 5481#L1288-1 assume !(0 == ~T7_E~0); 5717#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 5705#L1298-1 assume !(0 == ~T9_E~0); 5631#L1303-1 assume !(0 == ~T10_E~0); 4276#L1308-1 assume !(0 == ~T11_E~0); 4218#L1313-1 assume !(0 == ~T12_E~0); 4219#L1318-1 assume !(0 == ~T13_E~0); 4225#L1323-1 assume !(0 == ~E_1~0); 4226#L1328-1 assume !(0 == ~E_2~0); 4393#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 5352#L1338-1 assume !(0 == ~E_4~0); 5353#L1343-1 assume !(0 == ~E_5~0); 5454#L1348-1 assume !(0 == ~E_6~0); 5740#L1353-1 assume !(0 == ~E_7~0); 5079#L1358-1 assume !(0 == ~E_8~0); 5080#L1363-1 assume !(0 == ~E_9~0); 5370#L1368-1 assume !(0 == ~E_10~0); 4055#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 4056#L1378-1 assume !(0 == ~E_12~0); 4342#L1383-1 assume !(0 == ~E_13~0); 4343#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5086#L607 assume 1 == ~m_pc~0; 5087#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 4413#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5452#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5006#L1560 assume !(0 != activate_threads_~tmp~1#1); 5007#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4238#L626 assume !(1 == ~t1_pc~0); 4239#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4507#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4508#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4677#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 4138#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4139#L645 assume 1 == ~t2_pc~0; 4255#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4212#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4889#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4890#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 4982#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4983#L664 assume 1 == ~t3_pc~0; 5739#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3979#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3980#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4638#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 4639#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5647#L683 assume !(1 == ~t4_pc~0); 5202#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 5154#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5155#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 5189#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5313#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4932#L702 assume 1 == ~t5_pc~0; 4933#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 4858#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5308#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 5606#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 5547#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4027#L721 assume !(1 == ~t6_pc~0); 4001#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 4002#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4165#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4647#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 4648#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5249#L740 assume 1 == ~t7_pc~0; 4076#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 3889#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3890#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3879#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 3880#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4583#L759 assume !(1 == ~t8_pc~0); 4584#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 4613#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 5306#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 5307#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 5438#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 5716#L778 assume 1 == ~t9_pc~0; 5603#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 4054#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3994#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 3923#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 3924#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4251#L797 assume !(1 == ~t10_pc~0); 4252#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 4370#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 5504#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 4754#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 4755#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 5044#L816 assume 1 == ~t11_pc~0; 3959#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 3960#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 4715#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 4654#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 4655#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 5179#L835 assume 1 == ~t12_pc~0; 5057#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 4123#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 4145#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 4286#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 4811#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 4812#L854 assume !(1 == ~t13_pc~0); 4452#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 4453#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 4503#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 4163#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 4164#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5543#L1401 assume !(1 == ~M_E~0); 4642#L1401-2 assume !(1 == ~T1_E~0); 4643#L1406-1 assume !(1 == ~T2_E~0); 5238#L1411-1 assume !(1 == ~T3_E~0); 5239#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4905#L1421-1 assume !(1 == ~T5_E~0); 4448#L1426-1 assume !(1 == ~T6_E~0); 4449#L1431-1 assume !(1 == ~T7_E~0); 3997#L1436-1 assume !(1 == ~T8_E~0); 3998#L1441-1 assume !(1 == ~T9_E~0); 4745#L1446-1 assume !(1 == ~T10_E~0); 4746#L1451-1 assume !(1 == ~T11_E~0); 5451#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 5105#L1461-1 assume !(1 == ~T13_E~0); 4666#L1466-1 assume !(1 == ~E_1~0); 4667#L1471-1 assume !(1 == ~E_2~0); 5436#L1476-1 assume !(1 == ~E_3~0); 5437#L1481-1 assume !(1 == ~E_4~0); 5585#L1486-1 assume !(1 == ~E_5~0); 4291#L1491-1 assume !(1 == ~E_6~0); 3931#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 3932#L1501-1 assume !(1 == ~E_8~0); 4743#L1506-1 assume !(1 == ~E_9~0); 4744#L1511-1 assume !(1 == ~E_10~0); 4700#L1516-1 assume !(1 == ~E_11~0); 3875#L1521-1 assume !(1 == ~E_12~0); 3876#L1526-1 assume !(1 == ~E_13~0); 3930#L1531-1 assume { :end_inline_reset_delta_events } true; 4473#L1892-2 [2021-12-16 10:06:10,823 INFO L793 eck$LassoCheckResult]: Loop: 4473#L1892-2 assume !false; 5496#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5694#L1233 assume !false; 5677#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 5009#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 4989#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 5147#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 3973#L1046 assume !(0 != eval_~tmp~0#1); 3975#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4009#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5181#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5738#L1258-5 assume !(0 == ~T1_E~0); 4151#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4152#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5730#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5736#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5737#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4375#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 4376#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 5493#L1298-3 assume !(0 == ~T9_E~0); 5494#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 5653#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 5492#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 4993#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 4153#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4154#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5577#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4296#L1338-3 assume !(0 == ~E_4~0); 4297#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 5409#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 5582#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 5583#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 4949#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 4509#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 4510#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 5266#L1378-3 assume !(0 == ~E_12~0); 5267#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 5448#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5449#L607-42 assume 1 == ~m_pc~0; 5062#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 4790#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4791#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4523#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4524#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5045#L626-42 assume !(1 == ~t1_pc~0); 4609#L626-44 is_transmit1_triggered_~__retres1~1#1 := 0; 4608#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4912#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4913#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4187#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4188#L645-42 assume !(1 == ~t2_pc~0); 5387#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 5388#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5553#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4394#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3901#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3902#L664-42 assume 1 == ~t3_pc~0; 4704#L665-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4429#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5680#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5215#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5216#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5381#L683-42 assume !(1 == ~t4_pc~0); 5089#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 5090#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5222#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 5642#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5643#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5487#L702-42 assume !(1 == ~t5_pc~0); 4599#L702-44 is_transmit5_triggered_~__retres1~5#1 := 0; 4600#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4896#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 5569#L1600-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 3917#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3918#L721-42 assume 1 == ~t6_pc~0; 4071#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4091#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4555#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 5722#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 4727#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4573#L740-42 assume !(1 == ~t7_pc~0); 4310#L740-44 is_transmit7_triggered_~__retres1~7#1 := 0; 4311#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4852#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4707#L1616-42 assume !(0 != activate_threads_~tmp___6~0#1); 4708#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4981#L759-42 assume 1 == ~t8_pc~0; 4830#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 4762#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4763#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 4841#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 4842#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4937#L778-42 assume 1 == ~t9_pc~0; 4774#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 4776#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 5186#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 5091#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 5092#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 5149#L797-42 assume 1 == ~t10_pc~0; 4316#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 4317#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 5318#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 5627#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 5187#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 5188#L816-42 assume 1 == ~t11_pc~0; 3865#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 3866#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 4408#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 4409#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 4488#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 4489#L835-42 assume !(1 == ~t12_pc~0); 4785#L835-44 is_transmit12_triggered_~__retres1~12#1 := 0; 4786#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 4463#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 4464#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 5546#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 5330#L854-42 assume 1 == ~t13_pc~0; 5331#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 4407#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 4017#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 4018#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 4664#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4665#L1401-3 assume 1 == ~M_E~0;~M_E~0 := 2; 5443#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4254#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4118#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4119#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4718#L1421-3 assume !(1 == ~T5_E~0); 4719#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 4294#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 4295#L1436-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 3881#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 3882#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 5471#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 4802#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 4455#L1461-3 assume !(1 == ~T13_E~0); 4456#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5733#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4395#L1476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4396#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4796#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4423#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 4424#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 4836#L1501-3 assume !(1 == ~E_8~0); 4837#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 5263#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 5253#L1516-3 assume 1 == ~E_11~0;~E_11~0 := 2; 5254#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 4953#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 4954#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 5348#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 4230#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 5123#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 4764#L1911 assume !(0 == start_simulation_~tmp~3#1); 4765#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 5287#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 4354#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 5225#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 4059#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4060#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4289#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 4290#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 4473#L1892-2 [2021-12-16 10:06:10,824 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:10,824 INFO L85 PathProgramCache]: Analyzing trace with hash 517365666, now seen corresponding path program 2 times [2021-12-16 10:06:10,824 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:10,825 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [459503840] [2021-12-16 10:06:10,825 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:10,825 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:10,839 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:06:10,872 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:06:10,873 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:06:10,873 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [459503840] [2021-12-16 10:06:10,873 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [459503840] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:06:10,873 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:06:10,874 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:06:10,874 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1305920536] [2021-12-16 10:06:10,874 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:06:10,874 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:06:10,875 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:10,875 INFO L85 PathProgramCache]: Analyzing trace with hash -423565315, now seen corresponding path program 1 times [2021-12-16 10:06:10,875 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:10,875 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1848772610] [2021-12-16 10:06:10,875 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:10,876 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:10,903 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:06:10,951 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:06:10,952 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:06:10,952 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1848772610] [2021-12-16 10:06:10,952 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1848772610] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:06:10,953 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:06:10,953 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:06:10,953 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2143868586] [2021-12-16 10:06:10,953 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:06:10,954 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:06:10,954 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:06:10,954 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-16 10:06:10,955 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-16 10:06:10,955 INFO L87 Difference]: Start difference. First operand 1914 states and 2835 transitions. cyclomatic complexity: 922 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:11,003 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:06:11,004 INFO L93 Difference]: Finished difference Result 1914 states and 2834 transitions. [2021-12-16 10:06:11,004 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-16 10:06:11,005 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1914 states and 2834 transitions. [2021-12-16 10:06:11,043 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2021-12-16 10:06:11,050 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1914 states to 1914 states and 2834 transitions. [2021-12-16 10:06:11,051 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1914 [2021-12-16 10:06:11,052 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1914 [2021-12-16 10:06:11,052 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1914 states and 2834 transitions. [2021-12-16 10:06:11,054 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:06:11,054 INFO L681 BuchiCegarLoop]: Abstraction has 1914 states and 2834 transitions. [2021-12-16 10:06:11,056 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1914 states and 2834 transitions. [2021-12-16 10:06:11,072 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1914 to 1914. [2021-12-16 10:06:11,075 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1914 states, 1914 states have (on average 1.4806687565308254) internal successors, (2834), 1913 states have internal predecessors, (2834), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:11,079 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1914 states to 1914 states and 2834 transitions. [2021-12-16 10:06:11,079 INFO L704 BuchiCegarLoop]: Abstraction has 1914 states and 2834 transitions. [2021-12-16 10:06:11,080 INFO L587 BuchiCegarLoop]: Abstraction has 1914 states and 2834 transitions. [2021-12-16 10:06:11,080 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2021-12-16 10:06:11,080 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1914 states and 2834 transitions. [2021-12-16 10:06:11,086 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2021-12-16 10:06:11,086 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:06:11,086 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:06:11,091 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:11,091 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:11,093 INFO L791 eck$LassoCheckResult]: Stem: 8546#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 8547#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 8366#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8082#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 8083#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 9259#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9260#L886-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 8218#L891-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 8219#L896-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 8673#L901-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 8508#L906-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 8509#L911-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 8285#L916-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 8286#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 8684#L926-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 8861#L931-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 9015#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 9052#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 8296#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8297#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 9472#L1258-2 assume !(0 == ~T1_E~0); 8591#L1263-1 assume !(0 == ~T2_E~0); 8592#L1268-1 assume !(0 == ~T3_E~0); 8895#L1273-1 assume !(0 == ~T4_E~0); 9454#L1278-1 assume !(0 == ~T5_E~0); 9315#L1283-1 assume !(0 == ~T6_E~0); 9316#L1288-1 assume !(0 == ~T7_E~0); 9552#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 9540#L1298-1 assume !(0 == ~T9_E~0); 9466#L1303-1 assume !(0 == ~T10_E~0); 8111#L1308-1 assume !(0 == ~T11_E~0); 8053#L1313-1 assume !(0 == ~T12_E~0); 8054#L1318-1 assume !(0 == ~T13_E~0); 8060#L1323-1 assume !(0 == ~E_1~0); 8061#L1328-1 assume !(0 == ~E_2~0); 8228#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 9187#L1338-1 assume !(0 == ~E_4~0); 9188#L1343-1 assume !(0 == ~E_5~0); 9289#L1348-1 assume !(0 == ~E_6~0); 9575#L1353-1 assume !(0 == ~E_7~0); 8914#L1358-1 assume !(0 == ~E_8~0); 8915#L1363-1 assume !(0 == ~E_9~0); 9205#L1368-1 assume !(0 == ~E_10~0); 7890#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 7891#L1378-1 assume !(0 == ~E_12~0); 8177#L1383-1 assume !(0 == ~E_13~0); 8178#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8921#L607 assume 1 == ~m_pc~0; 8922#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 8248#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9287#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8841#L1560 assume !(0 != activate_threads_~tmp~1#1); 8842#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8073#L626 assume !(1 == ~t1_pc~0); 8074#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 8342#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8343#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8512#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 7973#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7974#L645 assume 1 == ~t2_pc~0; 8090#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 8047#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8724#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8725#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 8817#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8818#L664 assume 1 == ~t3_pc~0; 9574#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 7814#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7815#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 8473#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 8474#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9482#L683 assume !(1 == ~t4_pc~0); 9037#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 8989#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8990#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 9024#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 9148#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8767#L702 assume 1 == ~t5_pc~0; 8768#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 8693#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9143#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 9441#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 9382#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7862#L721 assume !(1 == ~t6_pc~0); 7836#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 7837#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8000#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 8482#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 8483#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9084#L740 assume 1 == ~t7_pc~0; 7911#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 7724#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 7725#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 7714#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 7715#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 8418#L759 assume !(1 == ~t8_pc~0); 8419#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 8448#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 9141#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 9142#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 9273#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 9551#L778 assume 1 == ~t9_pc~0; 9438#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 7889#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 7829#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 7758#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 7759#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 8086#L797 assume !(1 == ~t10_pc~0); 8087#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 8205#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 9339#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 8589#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 8590#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 8879#L816 assume 1 == ~t11_pc~0; 7794#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 7795#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 8550#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 8489#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 8490#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 9014#L835 assume 1 == ~t12_pc~0; 8892#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 7958#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 7980#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 8121#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 8646#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 8647#L854 assume !(1 == ~t13_pc~0); 8287#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 8288#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 8338#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 7998#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 7999#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9378#L1401 assume !(1 == ~M_E~0); 8477#L1401-2 assume !(1 == ~T1_E~0); 8478#L1406-1 assume !(1 == ~T2_E~0); 9073#L1411-1 assume !(1 == ~T3_E~0); 9074#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8740#L1421-1 assume !(1 == ~T5_E~0); 8283#L1426-1 assume !(1 == ~T6_E~0); 8284#L1431-1 assume !(1 == ~T7_E~0); 7832#L1436-1 assume !(1 == ~T8_E~0); 7833#L1441-1 assume !(1 == ~T9_E~0); 8580#L1446-1 assume !(1 == ~T10_E~0); 8581#L1451-1 assume !(1 == ~T11_E~0); 9286#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 8940#L1461-1 assume !(1 == ~T13_E~0); 8501#L1466-1 assume !(1 == ~E_1~0); 8502#L1471-1 assume !(1 == ~E_2~0); 9271#L1476-1 assume !(1 == ~E_3~0); 9272#L1481-1 assume !(1 == ~E_4~0); 9420#L1486-1 assume !(1 == ~E_5~0); 8126#L1491-1 assume !(1 == ~E_6~0); 7766#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 7767#L1501-1 assume !(1 == ~E_8~0); 8578#L1506-1 assume !(1 == ~E_9~0); 8579#L1511-1 assume !(1 == ~E_10~0); 8535#L1516-1 assume !(1 == ~E_11~0); 7710#L1521-1 assume !(1 == ~E_12~0); 7711#L1526-1 assume !(1 == ~E_13~0); 7765#L1531-1 assume { :end_inline_reset_delta_events } true; 8308#L1892-2 [2021-12-16 10:06:11,094 INFO L793 eck$LassoCheckResult]: Loop: 8308#L1892-2 assume !false; 9331#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 9529#L1233 assume !false; 9512#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 8844#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 8824#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 8982#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 7808#L1046 assume !(0 != eval_~tmp~0#1); 7810#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 7844#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 9016#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 9573#L1258-5 assume !(0 == ~T1_E~0); 7986#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7987#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 9565#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 9571#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 9572#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 8210#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 8211#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 9328#L1298-3 assume !(0 == ~T9_E~0); 9329#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 9488#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 9327#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 8828#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 7988#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7989#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 9412#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 8131#L1338-3 assume !(0 == ~E_4~0); 8132#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 9244#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 9417#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 9418#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 8784#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 8344#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 8345#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 9101#L1378-3 assume !(0 == ~E_12~0); 9102#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 9283#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9284#L607-42 assume 1 == ~m_pc~0; 8897#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 8625#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8626#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8358#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8359#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8880#L626-42 assume 1 == ~t1_pc~0; 8442#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8443#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8747#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8748#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8022#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8023#L645-42 assume !(1 == ~t2_pc~0); 9222#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 9223#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9388#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8229#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 7736#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7737#L664-42 assume !(1 == ~t3_pc~0); 8263#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 8264#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9515#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9050#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9051#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9216#L683-42 assume !(1 == ~t4_pc~0); 8924#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 8925#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9057#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 9477#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 9478#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9322#L702-42 assume !(1 == ~t5_pc~0); 8434#L702-44 is_transmit5_triggered_~__retres1~5#1 := 0; 8435#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8731#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 9404#L1600-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 7752#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7753#L721-42 assume 1 == ~t6_pc~0; 7906#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 7926#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8390#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 9557#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 8562#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8408#L740-42 assume !(1 == ~t7_pc~0); 8145#L740-44 is_transmit7_triggered_~__retres1~7#1 := 0; 8146#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8687#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 8542#L1616-42 assume !(0 != activate_threads_~tmp___6~0#1); 8543#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 8816#L759-42 assume 1 == ~t8_pc~0; 8665#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 8597#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 8598#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 8676#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 8677#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 8772#L778-42 assume 1 == ~t9_pc~0; 8609#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 8611#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 9021#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 8926#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 8927#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 8984#L797-42 assume 1 == ~t10_pc~0; 8151#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 8152#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 9153#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 9462#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 9022#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 9023#L816-42 assume 1 == ~t11_pc~0; 7700#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 7701#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 8243#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 8244#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 8323#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 8324#L835-42 assume 1 == ~t12_pc~0; 8728#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 8621#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 8298#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 8299#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 9381#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 9165#L854-42 assume !(1 == ~t13_pc~0); 8241#L854-44 is_transmit13_triggered_~__retres1~13#1 := 0; 8242#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 7852#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 7853#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 8499#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8500#L1401-3 assume 1 == ~M_E~0;~M_E~0 := 2; 9278#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8089#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7953#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7954#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8553#L1421-3 assume !(1 == ~T5_E~0); 8554#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 8129#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 8130#L1436-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 7716#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 7717#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 9306#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 8637#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 8290#L1461-3 assume !(1 == ~T13_E~0); 8291#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 9568#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8230#L1476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 8231#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 8631#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 8258#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 8259#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 8671#L1501-3 assume !(1 == ~E_8~0); 8672#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 9098#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 9088#L1516-3 assume 1 == ~E_11~0;~E_11~0 := 2; 9089#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 8788#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 8789#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 9183#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 8065#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 8958#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 8599#L1911 assume !(0 == start_simulation_~tmp~3#1); 8600#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 9122#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 8189#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 9060#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 7894#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 7895#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8124#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 8125#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 8308#L1892-2 [2021-12-16 10:06:11,097 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:11,098 INFO L85 PathProgramCache]: Analyzing trace with hash -2008130016, now seen corresponding path program 1 times [2021-12-16 10:06:11,098 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:11,099 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2008709393] [2021-12-16 10:06:11,099 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:11,099 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:11,124 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:06:11,163 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:06:11,167 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:06:11,167 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2008709393] [2021-12-16 10:06:11,167 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2008709393] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:06:11,167 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:06:11,167 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:06:11,168 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1112075771] [2021-12-16 10:06:11,168 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:06:11,168 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:06:11,169 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:11,170 INFO L85 PathProgramCache]: Analyzing trace with hash 168575421, now seen corresponding path program 1 times [2021-12-16 10:06:11,170 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:11,171 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1610133973] [2021-12-16 10:06:11,171 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:11,172 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:11,192 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:06:11,249 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:06:11,249 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:06:11,249 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1610133973] [2021-12-16 10:06:11,250 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1610133973] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:06:11,250 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:06:11,250 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:06:11,250 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1062342592] [2021-12-16 10:06:11,250 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:06:11,251 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:06:11,251 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:06:11,251 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-16 10:06:11,251 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-16 10:06:11,252 INFO L87 Difference]: Start difference. First operand 1914 states and 2834 transitions. cyclomatic complexity: 921 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:11,276 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:06:11,277 INFO L93 Difference]: Finished difference Result 1914 states and 2833 transitions. [2021-12-16 10:06:11,277 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-16 10:06:11,278 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1914 states and 2833 transitions. [2021-12-16 10:06:11,288 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2021-12-16 10:06:11,295 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1914 states to 1914 states and 2833 transitions. [2021-12-16 10:06:11,295 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1914 [2021-12-16 10:06:11,296 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1914 [2021-12-16 10:06:11,296 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1914 states and 2833 transitions. [2021-12-16 10:06:11,299 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:06:11,299 INFO L681 BuchiCegarLoop]: Abstraction has 1914 states and 2833 transitions. [2021-12-16 10:06:11,301 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1914 states and 2833 transitions. [2021-12-16 10:06:11,316 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1914 to 1914. [2021-12-16 10:06:11,319 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1914 states, 1914 states have (on average 1.480146290491118) internal successors, (2833), 1913 states have internal predecessors, (2833), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:11,323 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1914 states to 1914 states and 2833 transitions. [2021-12-16 10:06:11,323 INFO L704 BuchiCegarLoop]: Abstraction has 1914 states and 2833 transitions. [2021-12-16 10:06:11,323 INFO L587 BuchiCegarLoop]: Abstraction has 1914 states and 2833 transitions. [2021-12-16 10:06:11,324 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2021-12-16 10:06:11,324 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1914 states and 2833 transitions. [2021-12-16 10:06:11,329 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2021-12-16 10:06:11,330 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:06:11,330 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:06:11,331 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:11,331 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:11,332 INFO L791 eck$LassoCheckResult]: Stem: 12381#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 12382#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 12201#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 11917#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 11918#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 13094#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 13095#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12053#L891-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 12054#L896-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 12508#L901-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 12343#L906-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 12344#L911-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 12120#L916-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 12121#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 12519#L926-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 12696#L931-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 12850#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 12887#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 12131#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12132#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 13307#L1258-2 assume !(0 == ~T1_E~0); 12426#L1263-1 assume !(0 == ~T2_E~0); 12427#L1268-1 assume !(0 == ~T3_E~0); 12730#L1273-1 assume !(0 == ~T4_E~0); 13289#L1278-1 assume !(0 == ~T5_E~0); 13150#L1283-1 assume !(0 == ~T6_E~0); 13151#L1288-1 assume !(0 == ~T7_E~0); 13387#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 13375#L1298-1 assume !(0 == ~T9_E~0); 13301#L1303-1 assume !(0 == ~T10_E~0); 11946#L1308-1 assume !(0 == ~T11_E~0); 11888#L1313-1 assume !(0 == ~T12_E~0); 11889#L1318-1 assume !(0 == ~T13_E~0); 11895#L1323-1 assume !(0 == ~E_1~0); 11896#L1328-1 assume !(0 == ~E_2~0); 12063#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 13022#L1338-1 assume !(0 == ~E_4~0); 13023#L1343-1 assume !(0 == ~E_5~0); 13124#L1348-1 assume !(0 == ~E_6~0); 13410#L1353-1 assume !(0 == ~E_7~0); 12749#L1358-1 assume !(0 == ~E_8~0); 12750#L1363-1 assume !(0 == ~E_9~0); 13040#L1368-1 assume !(0 == ~E_10~0); 11725#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 11726#L1378-1 assume !(0 == ~E_12~0); 12012#L1383-1 assume !(0 == ~E_13~0); 12013#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12756#L607 assume 1 == ~m_pc~0; 12757#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 12083#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13122#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12676#L1560 assume !(0 != activate_threads_~tmp~1#1); 12677#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11908#L626 assume !(1 == ~t1_pc~0); 11909#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 12177#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12178#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12347#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 11808#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11809#L645 assume 1 == ~t2_pc~0; 11925#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 11882#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12559#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12560#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 12652#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12653#L664 assume 1 == ~t3_pc~0; 13409#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 11649#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11650#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 12308#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 12309#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13317#L683 assume !(1 == ~t4_pc~0); 12872#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 12824#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12825#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 12859#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 12983#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12602#L702 assume 1 == ~t5_pc~0; 12603#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12528#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12978#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 13276#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 13217#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11697#L721 assume !(1 == ~t6_pc~0); 11671#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 11672#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11835#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 12317#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 12318#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12919#L740 assume 1 == ~t7_pc~0; 11746#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 11559#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 11560#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 11549#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 11550#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12253#L759 assume !(1 == ~t8_pc~0); 12254#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 12283#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12976#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 12977#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 13108#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 13386#L778 assume 1 == ~t9_pc~0; 13273#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 11724#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 11664#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 11593#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 11594#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 11921#L797 assume !(1 == ~t10_pc~0); 11922#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 12040#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 13174#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 12424#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 12425#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 12714#L816 assume 1 == ~t11_pc~0; 11629#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 11630#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 12385#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 12324#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 12325#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 12849#L835 assume 1 == ~t12_pc~0; 12727#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 11793#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 11815#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 11956#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 12481#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 12482#L854 assume !(1 == ~t13_pc~0); 12122#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 12123#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 12173#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 11833#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 11834#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13213#L1401 assume !(1 == ~M_E~0); 12312#L1401-2 assume !(1 == ~T1_E~0); 12313#L1406-1 assume !(1 == ~T2_E~0); 12908#L1411-1 assume !(1 == ~T3_E~0); 12909#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12575#L1421-1 assume !(1 == ~T5_E~0); 12118#L1426-1 assume !(1 == ~T6_E~0); 12119#L1431-1 assume !(1 == ~T7_E~0); 11667#L1436-1 assume !(1 == ~T8_E~0); 11668#L1441-1 assume !(1 == ~T9_E~0); 12415#L1446-1 assume !(1 == ~T10_E~0); 12416#L1451-1 assume !(1 == ~T11_E~0); 13121#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 12775#L1461-1 assume !(1 == ~T13_E~0); 12336#L1466-1 assume !(1 == ~E_1~0); 12337#L1471-1 assume !(1 == ~E_2~0); 13106#L1476-1 assume !(1 == ~E_3~0); 13107#L1481-1 assume !(1 == ~E_4~0); 13255#L1486-1 assume !(1 == ~E_5~0); 11961#L1491-1 assume !(1 == ~E_6~0); 11601#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 11602#L1501-1 assume !(1 == ~E_8~0); 12413#L1506-1 assume !(1 == ~E_9~0); 12414#L1511-1 assume !(1 == ~E_10~0); 12370#L1516-1 assume !(1 == ~E_11~0); 11545#L1521-1 assume !(1 == ~E_12~0); 11546#L1526-1 assume !(1 == ~E_13~0); 11600#L1531-1 assume { :end_inline_reset_delta_events } true; 12143#L1892-2 [2021-12-16 10:06:11,332 INFO L793 eck$LassoCheckResult]: Loop: 12143#L1892-2 assume !false; 13166#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 13364#L1233 assume !false; 13347#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 12679#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 12659#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 12817#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 11643#L1046 assume !(0 != eval_~tmp~0#1); 11645#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 11679#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 12851#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 13408#L1258-5 assume !(0 == ~T1_E~0); 11821#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 11822#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 13400#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 13406#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 13407#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 12045#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 12046#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 13163#L1298-3 assume !(0 == ~T9_E~0); 13164#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 13323#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 13162#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 12663#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 11823#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 11824#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 13247#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 11966#L1338-3 assume !(0 == ~E_4~0); 11967#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 13079#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 13252#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 13253#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 12619#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 12179#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 12180#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 12936#L1378-3 assume !(0 == ~E_12~0); 12937#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 13118#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13119#L607-42 assume 1 == ~m_pc~0; 12732#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 12460#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12461#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12193#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12194#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12715#L626-42 assume 1 == ~t1_pc~0; 12277#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 12278#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12582#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12583#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 11857#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11858#L645-42 assume !(1 == ~t2_pc~0); 13057#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 13058#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13223#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12064#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 11571#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11572#L664-42 assume !(1 == ~t3_pc~0); 12098#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 12099#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13350#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 12885#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 12886#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13051#L683-42 assume !(1 == ~t4_pc~0); 12759#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 12760#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12892#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 13312#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 13313#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13157#L702-42 assume 1 == ~t5_pc~0; 12645#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12270#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12566#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 13239#L1600-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 11587#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11588#L721-42 assume 1 == ~t6_pc~0; 11741#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 11761#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12225#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 13392#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 12397#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12243#L740-42 assume 1 == ~t7_pc~0; 12244#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 11981#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12522#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 12377#L1616-42 assume !(0 != activate_threads_~tmp___6~0#1); 12378#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12651#L759-42 assume 1 == ~t8_pc~0; 12500#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 12432#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12433#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 12511#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 12512#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 12607#L778-42 assume 1 == ~t9_pc~0; 12444#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 12446#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 12856#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 12761#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 12762#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 12819#L797-42 assume 1 == ~t10_pc~0; 11986#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 11987#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 12988#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 13297#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 12857#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 12858#L816-42 assume !(1 == ~t11_pc~0); 11537#L816-44 is_transmit11_triggered_~__retres1~11#1 := 0; 11536#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 12078#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 12079#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 12158#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 12159#L835-42 assume 1 == ~t12_pc~0; 12563#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 12456#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 12133#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 12134#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 13216#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 13000#L854-42 assume 1 == ~t13_pc~0; 13001#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 12077#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 11687#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 11688#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 12334#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12335#L1401-3 assume 1 == ~M_E~0;~M_E~0 := 2; 13113#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 11924#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 11788#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 11789#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12388#L1421-3 assume !(1 == ~T5_E~0); 12389#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 11964#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 11965#L1436-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 11551#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 11552#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 13141#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 12472#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 12125#L1461-3 assume !(1 == ~T13_E~0); 12126#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 13403#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 12065#L1476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 12066#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 12466#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 12093#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 12094#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 12506#L1501-3 assume !(1 == ~E_8~0); 12507#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 12933#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 12923#L1516-3 assume 1 == ~E_11~0;~E_11~0 := 2; 12924#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 12623#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 12624#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 13018#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 11900#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 12793#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 12434#L1911 assume !(0 == start_simulation_~tmp~3#1); 12435#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 12957#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 12024#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 12895#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 11729#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 11730#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 11959#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 11960#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 12143#L1892-2 [2021-12-16 10:06:11,333 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:11,334 INFO L85 PathProgramCache]: Analyzing trace with hash -602938338, now seen corresponding path program 1 times [2021-12-16 10:06:11,334 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:11,335 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1128153257] [2021-12-16 10:06:11,335 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:11,335 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:11,354 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:06:11,383 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:06:11,383 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:06:11,383 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1128153257] [2021-12-16 10:06:11,384 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1128153257] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:06:11,384 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:06:11,385 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:06:11,387 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1759963666] [2021-12-16 10:06:11,387 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:06:11,387 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:06:11,388 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:11,388 INFO L85 PathProgramCache]: Analyzing trace with hash 2046766079, now seen corresponding path program 1 times [2021-12-16 10:06:11,388 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:11,391 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [741348402] [2021-12-16 10:06:11,391 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:11,391 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:11,408 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:06:11,449 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:06:11,450 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:06:11,450 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [741348402] [2021-12-16 10:06:11,450 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [741348402] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:06:11,450 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:06:11,450 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:06:11,451 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1003193332] [2021-12-16 10:06:11,451 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:06:11,451 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:06:11,451 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:06:11,452 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-16 10:06:11,452 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-16 10:06:11,453 INFO L87 Difference]: Start difference. First operand 1914 states and 2833 transitions. cyclomatic complexity: 920 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:11,512 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:06:11,512 INFO L93 Difference]: Finished difference Result 1914 states and 2832 transitions. [2021-12-16 10:06:11,513 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-16 10:06:11,513 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1914 states and 2832 transitions. [2021-12-16 10:06:11,521 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2021-12-16 10:06:11,527 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1914 states to 1914 states and 2832 transitions. [2021-12-16 10:06:11,528 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1914 [2021-12-16 10:06:11,529 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1914 [2021-12-16 10:06:11,529 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1914 states and 2832 transitions. [2021-12-16 10:06:11,530 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:06:11,530 INFO L681 BuchiCegarLoop]: Abstraction has 1914 states and 2832 transitions. [2021-12-16 10:06:11,533 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1914 states and 2832 transitions. [2021-12-16 10:06:11,546 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1914 to 1914. [2021-12-16 10:06:11,548 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1914 states, 1914 states have (on average 1.4796238244514106) internal successors, (2832), 1913 states have internal predecessors, (2832), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:11,552 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1914 states to 1914 states and 2832 transitions. [2021-12-16 10:06:11,552 INFO L704 BuchiCegarLoop]: Abstraction has 1914 states and 2832 transitions. [2021-12-16 10:06:11,552 INFO L587 BuchiCegarLoop]: Abstraction has 1914 states and 2832 transitions. [2021-12-16 10:06:11,552 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2021-12-16 10:06:11,552 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1914 states and 2832 transitions. [2021-12-16 10:06:11,559 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2021-12-16 10:06:11,559 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:06:11,559 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:06:11,560 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:11,561 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:11,561 INFO L791 eck$LassoCheckResult]: Stem: 16216#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 16217#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 16036#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 15752#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 15753#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 16929#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 16930#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 15888#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 15889#L896-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 16343#L901-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 16178#L906-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 16179#L911-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 15955#L916-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 15956#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 16354#L926-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 16531#L931-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 16685#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 16722#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 15966#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 15967#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 17142#L1258-2 assume !(0 == ~T1_E~0); 16261#L1263-1 assume !(0 == ~T2_E~0); 16262#L1268-1 assume !(0 == ~T3_E~0); 16565#L1273-1 assume !(0 == ~T4_E~0); 17124#L1278-1 assume !(0 == ~T5_E~0); 16985#L1283-1 assume !(0 == ~T6_E~0); 16986#L1288-1 assume !(0 == ~T7_E~0); 17222#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 17210#L1298-1 assume !(0 == ~T9_E~0); 17136#L1303-1 assume !(0 == ~T10_E~0); 15781#L1308-1 assume !(0 == ~T11_E~0); 15723#L1313-1 assume !(0 == ~T12_E~0); 15724#L1318-1 assume !(0 == ~T13_E~0); 15730#L1323-1 assume !(0 == ~E_1~0); 15731#L1328-1 assume !(0 == ~E_2~0); 15898#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 16857#L1338-1 assume !(0 == ~E_4~0); 16858#L1343-1 assume !(0 == ~E_5~0); 16959#L1348-1 assume !(0 == ~E_6~0); 17245#L1353-1 assume !(0 == ~E_7~0); 16584#L1358-1 assume !(0 == ~E_8~0); 16585#L1363-1 assume !(0 == ~E_9~0); 16875#L1368-1 assume !(0 == ~E_10~0); 15560#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 15561#L1378-1 assume !(0 == ~E_12~0); 15847#L1383-1 assume !(0 == ~E_13~0); 15848#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16591#L607 assume 1 == ~m_pc~0; 16592#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 15918#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16957#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 16511#L1560 assume !(0 != activate_threads_~tmp~1#1); 16512#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15743#L626 assume !(1 == ~t1_pc~0); 15744#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 16012#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16013#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 16182#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 15643#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15644#L645 assume 1 == ~t2_pc~0; 15760#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 15717#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16394#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 16395#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 16487#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16488#L664 assume 1 == ~t3_pc~0; 17244#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 15484#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15485#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 16143#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 16144#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 17152#L683 assume !(1 == ~t4_pc~0); 16707#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 16659#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 16660#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 16694#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 16818#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16437#L702 assume 1 == ~t5_pc~0; 16438#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 16363#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 16813#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 17111#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 17052#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 15532#L721 assume !(1 == ~t6_pc~0); 15506#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 15507#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 15670#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 16152#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 16153#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 16754#L740 assume 1 == ~t7_pc~0; 15581#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 15394#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 15395#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 15384#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 15385#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 16088#L759 assume !(1 == ~t8_pc~0); 16089#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 16118#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 16811#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 16812#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 16943#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 17221#L778 assume 1 == ~t9_pc~0; 17108#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 15559#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 15499#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 15428#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 15429#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 15756#L797 assume !(1 == ~t10_pc~0); 15757#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 15875#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 17009#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 16259#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 16260#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 16549#L816 assume 1 == ~t11_pc~0; 15464#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 15465#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 16220#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 16159#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 16160#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 16684#L835 assume 1 == ~t12_pc~0; 16562#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 15628#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 15650#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 15791#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 16316#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 16317#L854 assume !(1 == ~t13_pc~0); 15957#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 15958#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 16008#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 15668#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 15669#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17048#L1401 assume !(1 == ~M_E~0); 16147#L1401-2 assume !(1 == ~T1_E~0); 16148#L1406-1 assume !(1 == ~T2_E~0); 16743#L1411-1 assume !(1 == ~T3_E~0); 16744#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 16410#L1421-1 assume !(1 == ~T5_E~0); 15953#L1426-1 assume !(1 == ~T6_E~0); 15954#L1431-1 assume !(1 == ~T7_E~0); 15502#L1436-1 assume !(1 == ~T8_E~0); 15503#L1441-1 assume !(1 == ~T9_E~0); 16250#L1446-1 assume !(1 == ~T10_E~0); 16251#L1451-1 assume !(1 == ~T11_E~0); 16956#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 16610#L1461-1 assume !(1 == ~T13_E~0); 16171#L1466-1 assume !(1 == ~E_1~0); 16172#L1471-1 assume !(1 == ~E_2~0); 16941#L1476-1 assume !(1 == ~E_3~0); 16942#L1481-1 assume !(1 == ~E_4~0); 17090#L1486-1 assume !(1 == ~E_5~0); 15796#L1491-1 assume !(1 == ~E_6~0); 15436#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 15437#L1501-1 assume !(1 == ~E_8~0); 16248#L1506-1 assume !(1 == ~E_9~0); 16249#L1511-1 assume !(1 == ~E_10~0); 16205#L1516-1 assume !(1 == ~E_11~0); 15380#L1521-1 assume !(1 == ~E_12~0); 15381#L1526-1 assume !(1 == ~E_13~0); 15435#L1531-1 assume { :end_inline_reset_delta_events } true; 15978#L1892-2 [2021-12-16 10:06:11,561 INFO L793 eck$LassoCheckResult]: Loop: 15978#L1892-2 assume !false; 17001#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 17199#L1233 assume !false; 17182#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 16514#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 16494#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 16652#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 15478#L1046 assume !(0 != eval_~tmp~0#1); 15480#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 15514#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 16686#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 17243#L1258-5 assume !(0 == ~T1_E~0); 15656#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 15657#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 17235#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 17241#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 17242#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 15880#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 15881#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 16998#L1298-3 assume !(0 == ~T9_E~0); 16999#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 17158#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 16997#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 16498#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 15658#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 15659#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 17082#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 15801#L1338-3 assume !(0 == ~E_4~0); 15802#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 16914#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 17087#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 17088#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 16454#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 16014#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 16015#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 16771#L1378-3 assume !(0 == ~E_12~0); 16772#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 16953#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16954#L607-42 assume 1 == ~m_pc~0; 16567#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 16295#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16296#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 16028#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 16029#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16550#L626-42 assume 1 == ~t1_pc~0; 16112#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 16113#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16417#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 16418#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 15692#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15693#L645-42 assume !(1 == ~t2_pc~0); 16892#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 16893#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17058#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 15899#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 15406#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15407#L664-42 assume 1 == ~t3_pc~0; 16209#L665-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 15934#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 17185#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 16720#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 16721#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16886#L683-42 assume !(1 == ~t4_pc~0); 16594#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 16595#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 16727#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 17147#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 17148#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16992#L702-42 assume 1 == ~t5_pc~0; 16480#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 16105#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 16401#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 17074#L1600-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 15422#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 15423#L721-42 assume 1 == ~t6_pc~0; 15576#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 15596#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 16060#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 17227#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 16232#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 16078#L740-42 assume !(1 == ~t7_pc~0); 15815#L740-44 is_transmit7_triggered_~__retres1~7#1 := 0; 15816#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16357#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 16212#L1616-42 assume !(0 != activate_threads_~tmp___6~0#1); 16213#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 16486#L759-42 assume !(1 == ~t8_pc~0); 16336#L759-44 is_transmit8_triggered_~__retres1~8#1 := 0; 16267#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 16268#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 16346#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 16347#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 16442#L778-42 assume 1 == ~t9_pc~0; 16279#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 16281#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 16691#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 16596#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 16597#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 16654#L797-42 assume 1 == ~t10_pc~0; 15821#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 15822#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 16823#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 17132#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 16692#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 16693#L816-42 assume 1 == ~t11_pc~0; 15370#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 15371#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 15913#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 15914#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 15993#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 15994#L835-42 assume !(1 == ~t12_pc~0); 16290#L835-44 is_transmit12_triggered_~__retres1~12#1 := 0; 16291#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 15968#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 15969#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 17051#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 16835#L854-42 assume 1 == ~t13_pc~0; 16836#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 15912#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 15522#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 15523#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 16169#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16170#L1401-3 assume 1 == ~M_E~0;~M_E~0 := 2; 16948#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 15759#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 15623#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 15624#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 16223#L1421-3 assume !(1 == ~T5_E~0); 16224#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 15799#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 15800#L1436-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 15386#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 15387#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 16976#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 16307#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 15960#L1461-3 assume !(1 == ~T13_E~0); 15961#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 17238#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 15900#L1476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 15901#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 16301#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 15928#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 15929#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 16341#L1501-3 assume !(1 == ~E_8~0); 16342#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 16768#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 16758#L1516-3 assume 1 == ~E_11~0;~E_11~0 := 2; 16759#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 16458#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 16459#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 16853#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 15735#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 16628#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 16269#L1911 assume !(0 == start_simulation_~tmp~3#1); 16270#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 16792#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 15859#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 16730#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 15564#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 15565#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 15794#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 15795#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 15978#L1892-2 [2021-12-16 10:06:11,562 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:11,562 INFO L85 PathProgramCache]: Analyzing trace with hash 1797695072, now seen corresponding path program 1 times [2021-12-16 10:06:11,562 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:11,562 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [702579135] [2021-12-16 10:06:11,562 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:11,563 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:11,571 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:06:11,588 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:06:11,588 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:06:11,588 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [702579135] [2021-12-16 10:06:11,588 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [702579135] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:06:11,589 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:06:11,589 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:06:11,589 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [248248397] [2021-12-16 10:06:11,589 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:06:11,590 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:06:11,590 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:11,590 INFO L85 PathProgramCache]: Analyzing trace with hash 259811934, now seen corresponding path program 1 times [2021-12-16 10:06:11,590 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:11,590 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1416467421] [2021-12-16 10:06:11,591 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:11,591 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:11,604 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:06:11,625 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:06:11,626 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:06:11,627 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1416467421] [2021-12-16 10:06:11,627 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1416467421] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:06:11,627 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:06:11,627 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:06:11,627 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1865701587] [2021-12-16 10:06:11,627 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:06:11,628 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:06:11,628 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:06:11,628 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-16 10:06:11,629 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-16 10:06:11,629 INFO L87 Difference]: Start difference. First operand 1914 states and 2832 transitions. cyclomatic complexity: 919 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:11,650 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:06:11,650 INFO L93 Difference]: Finished difference Result 1914 states and 2831 transitions. [2021-12-16 10:06:11,651 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-16 10:06:11,653 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1914 states and 2831 transitions. [2021-12-16 10:06:11,659 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2021-12-16 10:06:11,665 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1914 states to 1914 states and 2831 transitions. [2021-12-16 10:06:11,666 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1914 [2021-12-16 10:06:11,667 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1914 [2021-12-16 10:06:11,667 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1914 states and 2831 transitions. [2021-12-16 10:06:11,668 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:06:11,668 INFO L681 BuchiCegarLoop]: Abstraction has 1914 states and 2831 transitions. [2021-12-16 10:06:11,670 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1914 states and 2831 transitions. [2021-12-16 10:06:11,684 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1914 to 1914. [2021-12-16 10:06:11,686 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1914 states, 1914 states have (on average 1.4791013584117032) internal successors, (2831), 1913 states have internal predecessors, (2831), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:11,689 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1914 states to 1914 states and 2831 transitions. [2021-12-16 10:06:11,690 INFO L704 BuchiCegarLoop]: Abstraction has 1914 states and 2831 transitions. [2021-12-16 10:06:11,690 INFO L587 BuchiCegarLoop]: Abstraction has 1914 states and 2831 transitions. [2021-12-16 10:06:11,690 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2021-12-16 10:06:11,690 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1914 states and 2831 transitions. [2021-12-16 10:06:11,696 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2021-12-16 10:06:11,696 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:06:11,696 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:06:11,697 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:11,698 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:11,698 INFO L791 eck$LassoCheckResult]: Stem: 20051#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 20052#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 19871#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 19587#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 19588#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 20764#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 20765#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 19723#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 19724#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 20178#L901-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 20013#L906-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 20014#L911-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 19790#L916-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 19791#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 20189#L926-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 20366#L931-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 20520#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 20557#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 19801#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 19802#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 20977#L1258-2 assume !(0 == ~T1_E~0); 20096#L1263-1 assume !(0 == ~T2_E~0); 20097#L1268-1 assume !(0 == ~T3_E~0); 20400#L1273-1 assume !(0 == ~T4_E~0); 20959#L1278-1 assume !(0 == ~T5_E~0); 20820#L1283-1 assume !(0 == ~T6_E~0); 20821#L1288-1 assume !(0 == ~T7_E~0); 21057#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 21045#L1298-1 assume !(0 == ~T9_E~0); 20971#L1303-1 assume !(0 == ~T10_E~0); 19616#L1308-1 assume !(0 == ~T11_E~0); 19558#L1313-1 assume !(0 == ~T12_E~0); 19559#L1318-1 assume !(0 == ~T13_E~0); 19565#L1323-1 assume !(0 == ~E_1~0); 19566#L1328-1 assume !(0 == ~E_2~0); 19733#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 20692#L1338-1 assume !(0 == ~E_4~0); 20693#L1343-1 assume !(0 == ~E_5~0); 20794#L1348-1 assume !(0 == ~E_6~0); 21080#L1353-1 assume !(0 == ~E_7~0); 20419#L1358-1 assume !(0 == ~E_8~0); 20420#L1363-1 assume !(0 == ~E_9~0); 20710#L1368-1 assume !(0 == ~E_10~0); 19395#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 19396#L1378-1 assume !(0 == ~E_12~0); 19682#L1383-1 assume !(0 == ~E_13~0); 19683#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20426#L607 assume 1 == ~m_pc~0; 20427#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 19753#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 20792#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 20346#L1560 assume !(0 != activate_threads_~tmp~1#1); 20347#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19578#L626 assume !(1 == ~t1_pc~0); 19579#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 19847#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19848#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 20017#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 19478#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 19479#L645 assume 1 == ~t2_pc~0; 19595#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 19552#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20229#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 20230#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 20322#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 20323#L664 assume 1 == ~t3_pc~0; 21079#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 19319#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19320#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 19978#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 19979#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 20987#L683 assume !(1 == ~t4_pc~0); 20542#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 20494#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 20495#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 20529#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 20653#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 20272#L702 assume 1 == ~t5_pc~0; 20273#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 20198#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 20648#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 20946#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 20887#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19367#L721 assume !(1 == ~t6_pc~0); 19341#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 19342#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19505#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 19987#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 19988#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 20589#L740 assume 1 == ~t7_pc~0; 19416#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 19229#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19230#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 19219#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 19220#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 19923#L759 assume !(1 == ~t8_pc~0); 19924#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 19953#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 20646#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 20647#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 20778#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 21056#L778 assume 1 == ~t9_pc~0; 20943#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 19394#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 19334#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 19263#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 19264#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 19591#L797 assume !(1 == ~t10_pc~0); 19592#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 19710#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 20844#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 20094#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 20095#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 20384#L816 assume 1 == ~t11_pc~0; 19299#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 19300#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 20055#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 19994#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 19995#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 20519#L835 assume 1 == ~t12_pc~0; 20397#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 19463#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 19485#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 19626#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 20151#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 20152#L854 assume !(1 == ~t13_pc~0); 19792#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 19793#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 19843#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 19503#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 19504#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 20883#L1401 assume !(1 == ~M_E~0); 19982#L1401-2 assume !(1 == ~T1_E~0); 19983#L1406-1 assume !(1 == ~T2_E~0); 20578#L1411-1 assume !(1 == ~T3_E~0); 20579#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 20245#L1421-1 assume !(1 == ~T5_E~0); 19788#L1426-1 assume !(1 == ~T6_E~0); 19789#L1431-1 assume !(1 == ~T7_E~0); 19337#L1436-1 assume !(1 == ~T8_E~0); 19338#L1441-1 assume !(1 == ~T9_E~0); 20085#L1446-1 assume !(1 == ~T10_E~0); 20086#L1451-1 assume !(1 == ~T11_E~0); 20791#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 20445#L1461-1 assume !(1 == ~T13_E~0); 20006#L1466-1 assume !(1 == ~E_1~0); 20007#L1471-1 assume !(1 == ~E_2~0); 20776#L1476-1 assume !(1 == ~E_3~0); 20777#L1481-1 assume !(1 == ~E_4~0); 20925#L1486-1 assume !(1 == ~E_5~0); 19631#L1491-1 assume !(1 == ~E_6~0); 19271#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 19272#L1501-1 assume !(1 == ~E_8~0); 20083#L1506-1 assume !(1 == ~E_9~0); 20084#L1511-1 assume !(1 == ~E_10~0); 20040#L1516-1 assume !(1 == ~E_11~0); 19215#L1521-1 assume !(1 == ~E_12~0); 19216#L1526-1 assume !(1 == ~E_13~0); 19270#L1531-1 assume { :end_inline_reset_delta_events } true; 19813#L1892-2 [2021-12-16 10:06:11,698 INFO L793 eck$LassoCheckResult]: Loop: 19813#L1892-2 assume !false; 20836#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 21034#L1233 assume !false; 21017#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 20349#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 20329#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 20487#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 19313#L1046 assume !(0 != eval_~tmp~0#1); 19315#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 19349#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 20521#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 21078#L1258-5 assume !(0 == ~T1_E~0); 19491#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 19492#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 21070#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 21076#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 21077#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 19715#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 19716#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 20833#L1298-3 assume !(0 == ~T9_E~0); 20834#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 20993#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 20832#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 20333#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 19493#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 19494#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 20917#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 19636#L1338-3 assume !(0 == ~E_4~0); 19637#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 20749#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 20922#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 20923#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 20289#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 19849#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 19850#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 20606#L1378-3 assume !(0 == ~E_12~0); 20607#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 20788#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20789#L607-42 assume 1 == ~m_pc~0; 20402#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 20130#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 20131#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 19863#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 19864#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 20385#L626-42 assume 1 == ~t1_pc~0; 19947#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 19948#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 20252#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 20253#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 19527#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 19528#L645-42 assume !(1 == ~t2_pc~0); 20727#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 20728#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20893#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 19734#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 19241#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19242#L664-42 assume !(1 == ~t3_pc~0); 19768#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 19769#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 21020#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 20555#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 20556#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 20721#L683-42 assume !(1 == ~t4_pc~0); 20429#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 20430#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 20562#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 20982#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 20983#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 20827#L702-42 assume !(1 == ~t5_pc~0); 19939#L702-44 is_transmit5_triggered_~__retres1~5#1 := 0; 19940#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 20236#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 20909#L1600-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 19257#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19258#L721-42 assume 1 == ~t6_pc~0; 19411#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 19431#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19895#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 21062#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 20067#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 19913#L740-42 assume !(1 == ~t7_pc~0); 19650#L740-44 is_transmit7_triggered_~__retres1~7#1 := 0; 19651#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 20192#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 20047#L1616-42 assume !(0 != activate_threads_~tmp___6~0#1); 20048#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 20321#L759-42 assume 1 == ~t8_pc~0; 20170#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 20102#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 20103#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 20181#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 20182#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 20277#L778-42 assume 1 == ~t9_pc~0; 20114#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 20116#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 20526#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 20431#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 20432#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 20489#L797-42 assume 1 == ~t10_pc~0; 19656#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 19657#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 20658#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 20967#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 20527#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 20528#L816-42 assume 1 == ~t11_pc~0; 19205#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 19206#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 19748#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 19749#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 19828#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 19829#L835-42 assume 1 == ~t12_pc~0; 20233#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 20126#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 19803#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 19804#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 20886#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 20670#L854-42 assume !(1 == ~t13_pc~0); 19746#L854-44 is_transmit13_triggered_~__retres1~13#1 := 0; 19747#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 19357#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 19358#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 20004#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 20005#L1401-3 assume 1 == ~M_E~0;~M_E~0 := 2; 20783#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 19594#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 19458#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 19459#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 20058#L1421-3 assume !(1 == ~T5_E~0); 20059#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 19634#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 19635#L1436-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 19221#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 19222#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 20811#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 20142#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 19795#L1461-3 assume !(1 == ~T13_E~0); 19796#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 21073#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 19735#L1476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 19736#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 20136#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 19763#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 19764#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 20176#L1501-3 assume !(1 == ~E_8~0); 20177#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 20603#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 20593#L1516-3 assume 1 == ~E_11~0;~E_11~0 := 2; 20594#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 20293#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 20294#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 20688#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 19570#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 20463#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 20104#L1911 assume !(0 == start_simulation_~tmp~3#1); 20105#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 20627#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 19694#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 20565#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 19399#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 19400#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 19629#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 19630#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 19813#L1892-2 [2021-12-16 10:06:11,699 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:11,699 INFO L85 PathProgramCache]: Analyzing trace with hash 351114206, now seen corresponding path program 1 times [2021-12-16 10:06:11,699 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:11,700 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1703974711] [2021-12-16 10:06:11,700 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:11,700 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:11,707 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:06:11,720 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:06:11,721 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:06:11,721 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1703974711] [2021-12-16 10:06:11,721 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1703974711] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:06:11,721 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:06:11,721 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:06:11,721 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1225989679] [2021-12-16 10:06:11,722 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:06:11,722 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:06:11,722 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:11,722 INFO L85 PathProgramCache]: Analyzing trace with hash 168575421, now seen corresponding path program 2 times [2021-12-16 10:06:11,722 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:11,723 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1622085611] [2021-12-16 10:06:11,723 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:11,723 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:11,732 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:06:11,775 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:06:11,775 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:06:11,776 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1622085611] [2021-12-16 10:06:11,776 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1622085611] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:06:11,776 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:06:11,776 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:06:11,777 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [239847673] [2021-12-16 10:06:11,777 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:06:11,777 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:06:11,777 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:06:11,778 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-16 10:06:11,778 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-16 10:06:11,778 INFO L87 Difference]: Start difference. First operand 1914 states and 2831 transitions. cyclomatic complexity: 918 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:11,801 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:06:11,801 INFO L93 Difference]: Finished difference Result 1914 states and 2830 transitions. [2021-12-16 10:06:11,801 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-16 10:06:11,803 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1914 states and 2830 transitions. [2021-12-16 10:06:11,810 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2021-12-16 10:06:11,816 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1914 states to 1914 states and 2830 transitions. [2021-12-16 10:06:11,817 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1914 [2021-12-16 10:06:11,818 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1914 [2021-12-16 10:06:11,818 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1914 states and 2830 transitions. [2021-12-16 10:06:11,820 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:06:11,820 INFO L681 BuchiCegarLoop]: Abstraction has 1914 states and 2830 transitions. [2021-12-16 10:06:11,821 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1914 states and 2830 transitions. [2021-12-16 10:06:11,842 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1914 to 1914. [2021-12-16 10:06:11,845 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1914 states, 1914 states have (on average 1.4785788923719958) internal successors, (2830), 1913 states have internal predecessors, (2830), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:11,849 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1914 states to 1914 states and 2830 transitions. [2021-12-16 10:06:11,849 INFO L704 BuchiCegarLoop]: Abstraction has 1914 states and 2830 transitions. [2021-12-16 10:06:11,849 INFO L587 BuchiCegarLoop]: Abstraction has 1914 states and 2830 transitions. [2021-12-16 10:06:11,849 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2021-12-16 10:06:11,849 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1914 states and 2830 transitions. [2021-12-16 10:06:11,854 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2021-12-16 10:06:11,854 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:06:11,854 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:06:11,856 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:11,856 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:11,856 INFO L791 eck$LassoCheckResult]: Stem: 23886#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 23887#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 23706#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 23422#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 23423#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 24599#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 24600#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 23558#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 23559#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 24013#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 23848#L906-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 23849#L911-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 23625#L916-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 23626#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 24024#L926-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 24201#L931-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 24355#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 24392#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 23636#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 23637#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 24812#L1258-2 assume !(0 == ~T1_E~0); 23931#L1263-1 assume !(0 == ~T2_E~0); 23932#L1268-1 assume !(0 == ~T3_E~0); 24235#L1273-1 assume !(0 == ~T4_E~0); 24794#L1278-1 assume !(0 == ~T5_E~0); 24655#L1283-1 assume !(0 == ~T6_E~0); 24656#L1288-1 assume !(0 == ~T7_E~0); 24892#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 24880#L1298-1 assume !(0 == ~T9_E~0); 24806#L1303-1 assume !(0 == ~T10_E~0); 23451#L1308-1 assume !(0 == ~T11_E~0); 23393#L1313-1 assume !(0 == ~T12_E~0); 23394#L1318-1 assume !(0 == ~T13_E~0); 23400#L1323-1 assume !(0 == ~E_1~0); 23401#L1328-1 assume !(0 == ~E_2~0); 23568#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 24527#L1338-1 assume !(0 == ~E_4~0); 24528#L1343-1 assume !(0 == ~E_5~0); 24629#L1348-1 assume !(0 == ~E_6~0); 24915#L1353-1 assume !(0 == ~E_7~0); 24254#L1358-1 assume !(0 == ~E_8~0); 24255#L1363-1 assume !(0 == ~E_9~0); 24545#L1368-1 assume !(0 == ~E_10~0); 23230#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 23231#L1378-1 assume !(0 == ~E_12~0); 23517#L1383-1 assume !(0 == ~E_13~0); 23518#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 24261#L607 assume 1 == ~m_pc~0; 24262#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 23588#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 24627#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 24181#L1560 assume !(0 != activate_threads_~tmp~1#1); 24182#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 23413#L626 assume !(1 == ~t1_pc~0); 23414#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 23682#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 23683#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 23852#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 23313#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 23314#L645 assume 1 == ~t2_pc~0; 23430#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 23387#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 24064#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 24065#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 24157#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 24158#L664 assume 1 == ~t3_pc~0; 24914#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 23154#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 23155#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 23813#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 23814#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 24822#L683 assume !(1 == ~t4_pc~0); 24377#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 24329#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 24330#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 24364#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 24488#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 24107#L702 assume 1 == ~t5_pc~0; 24108#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 24033#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 24483#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 24781#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 24722#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 23202#L721 assume !(1 == ~t6_pc~0); 23176#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 23177#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 23340#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 23822#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 23823#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 24424#L740 assume 1 == ~t7_pc~0; 23251#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 23064#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 23065#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 23054#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 23055#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 23758#L759 assume !(1 == ~t8_pc~0); 23759#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 23788#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 24481#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 24482#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 24613#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 24891#L778 assume 1 == ~t9_pc~0; 24778#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 23229#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 23169#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 23098#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 23099#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 23426#L797 assume !(1 == ~t10_pc~0); 23427#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 23545#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 24679#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 23929#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 23930#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 24219#L816 assume 1 == ~t11_pc~0; 23134#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 23135#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 23890#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 23829#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 23830#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 24354#L835 assume 1 == ~t12_pc~0; 24232#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 23298#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 23320#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 23461#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 23986#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 23987#L854 assume !(1 == ~t13_pc~0); 23627#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 23628#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 23678#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 23338#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 23339#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 24718#L1401 assume !(1 == ~M_E~0); 23817#L1401-2 assume !(1 == ~T1_E~0); 23818#L1406-1 assume !(1 == ~T2_E~0); 24413#L1411-1 assume !(1 == ~T3_E~0); 24414#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 24080#L1421-1 assume !(1 == ~T5_E~0); 23623#L1426-1 assume !(1 == ~T6_E~0); 23624#L1431-1 assume !(1 == ~T7_E~0); 23172#L1436-1 assume !(1 == ~T8_E~0); 23173#L1441-1 assume !(1 == ~T9_E~0); 23920#L1446-1 assume !(1 == ~T10_E~0); 23921#L1451-1 assume !(1 == ~T11_E~0); 24626#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 24280#L1461-1 assume !(1 == ~T13_E~0); 23841#L1466-1 assume !(1 == ~E_1~0); 23842#L1471-1 assume !(1 == ~E_2~0); 24611#L1476-1 assume !(1 == ~E_3~0); 24612#L1481-1 assume !(1 == ~E_4~0); 24760#L1486-1 assume !(1 == ~E_5~0); 23466#L1491-1 assume !(1 == ~E_6~0); 23106#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 23107#L1501-1 assume !(1 == ~E_8~0); 23918#L1506-1 assume !(1 == ~E_9~0); 23919#L1511-1 assume !(1 == ~E_10~0); 23875#L1516-1 assume !(1 == ~E_11~0); 23050#L1521-1 assume !(1 == ~E_12~0); 23051#L1526-1 assume !(1 == ~E_13~0); 23105#L1531-1 assume { :end_inline_reset_delta_events } true; 23648#L1892-2 [2021-12-16 10:06:11,856 INFO L793 eck$LassoCheckResult]: Loop: 23648#L1892-2 assume !false; 24671#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 24869#L1233 assume !false; 24852#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 24184#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 24164#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 24322#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 23148#L1046 assume !(0 != eval_~tmp~0#1); 23150#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 23184#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 24356#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 24913#L1258-5 assume !(0 == ~T1_E~0); 23326#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 23327#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 24905#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 24911#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 24912#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 23550#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 23551#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 24668#L1298-3 assume !(0 == ~T9_E~0); 24669#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 24828#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 24667#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 24168#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 23328#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 23329#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 24752#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 23471#L1338-3 assume !(0 == ~E_4~0); 23472#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 24584#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 24757#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 24758#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 24124#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 23684#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 23685#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 24441#L1378-3 assume !(0 == ~E_12~0); 24442#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 24623#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 24624#L607-42 assume 1 == ~m_pc~0; 24237#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 23965#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 23966#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 23698#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 23699#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 24220#L626-42 assume 1 == ~t1_pc~0; 23782#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 23783#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 24087#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 24088#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 23362#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 23363#L645-42 assume !(1 == ~t2_pc~0); 24562#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 24563#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 24728#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 23569#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 23076#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 23077#L664-42 assume !(1 == ~t3_pc~0); 23603#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 23604#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 24855#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 24390#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 24391#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 24556#L683-42 assume !(1 == ~t4_pc~0); 24264#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 24265#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 24397#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 24817#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 24818#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 24662#L702-42 assume 1 == ~t5_pc~0; 24150#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 23775#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 24071#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 24744#L1600-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 23092#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 23093#L721-42 assume 1 == ~t6_pc~0; 23246#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 23266#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 23730#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 24897#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 23902#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 23748#L740-42 assume 1 == ~t7_pc~0; 23749#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 23486#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 24027#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 23882#L1616-42 assume !(0 != activate_threads_~tmp___6~0#1); 23883#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 24156#L759-42 assume 1 == ~t8_pc~0; 24005#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 23937#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 23938#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 24016#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 24017#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 24112#L778-42 assume 1 == ~t9_pc~0; 23949#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 23951#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 24361#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 24266#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 24267#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 24324#L797-42 assume 1 == ~t10_pc~0; 23491#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 23492#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 24493#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 24802#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 24362#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 24363#L816-42 assume 1 == ~t11_pc~0; 23040#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 23041#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 23583#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 23584#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 23663#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 23664#L835-42 assume 1 == ~t12_pc~0; 24068#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 23961#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 23638#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 23639#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 24721#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 24505#L854-42 assume 1 == ~t13_pc~0; 24506#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 23582#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 23192#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 23193#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 23839#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 23840#L1401-3 assume 1 == ~M_E~0;~M_E~0 := 2; 24618#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 23429#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 23293#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 23294#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 23893#L1421-3 assume !(1 == ~T5_E~0); 23894#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 23469#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 23470#L1436-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 23056#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 23057#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 24646#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 23977#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 23630#L1461-3 assume !(1 == ~T13_E~0); 23631#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 24908#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 23570#L1476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 23571#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 23971#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 23598#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 23599#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 24011#L1501-3 assume !(1 == ~E_8~0); 24012#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 24438#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 24428#L1516-3 assume 1 == ~E_11~0;~E_11~0 := 2; 24429#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 24128#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 24129#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 24523#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 23405#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 24298#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 23939#L1911 assume !(0 == start_simulation_~tmp~3#1); 23940#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 24462#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 23529#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 24400#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 23234#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 23235#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 23464#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 23465#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 23648#L1892-2 [2021-12-16 10:06:11,857 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:11,857 INFO L85 PathProgramCache]: Analyzing trace with hash 1274281632, now seen corresponding path program 1 times [2021-12-16 10:06:11,857 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:11,857 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2110533445] [2021-12-16 10:06:11,857 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:11,857 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:11,866 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:06:11,888 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:06:11,888 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:06:11,889 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2110533445] [2021-12-16 10:06:11,889 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2110533445] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:06:11,889 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:06:11,889 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:06:11,889 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [519870405] [2021-12-16 10:06:11,889 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:06:11,889 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:06:11,890 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:11,890 INFO L85 PathProgramCache]: Analyzing trace with hash -1106553824, now seen corresponding path program 1 times [2021-12-16 10:06:11,890 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:11,890 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1157021755] [2021-12-16 10:06:11,890 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:11,890 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:11,903 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:06:11,929 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:06:11,929 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:06:11,929 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1157021755] [2021-12-16 10:06:11,929 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1157021755] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:06:11,929 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:06:11,929 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:06:11,929 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [944037297] [2021-12-16 10:06:11,929 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:06:11,930 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:06:11,930 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:06:11,930 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-16 10:06:11,930 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-16 10:06:11,930 INFO L87 Difference]: Start difference. First operand 1914 states and 2830 transitions. cyclomatic complexity: 917 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:11,954 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:06:11,954 INFO L93 Difference]: Finished difference Result 1914 states and 2829 transitions. [2021-12-16 10:06:11,955 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-16 10:06:11,956 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1914 states and 2829 transitions. [2021-12-16 10:06:11,963 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2021-12-16 10:06:11,969 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1914 states to 1914 states and 2829 transitions. [2021-12-16 10:06:11,969 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1914 [2021-12-16 10:06:11,972 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1914 [2021-12-16 10:06:11,972 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1914 states and 2829 transitions. [2021-12-16 10:06:11,974 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:06:11,974 INFO L681 BuchiCegarLoop]: Abstraction has 1914 states and 2829 transitions. [2021-12-16 10:06:11,976 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1914 states and 2829 transitions. [2021-12-16 10:06:11,992 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1914 to 1914. [2021-12-16 10:06:11,995 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1914 states, 1914 states have (on average 1.4780564263322884) internal successors, (2829), 1913 states have internal predecessors, (2829), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:11,999 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1914 states to 1914 states and 2829 transitions. [2021-12-16 10:06:11,999 INFO L704 BuchiCegarLoop]: Abstraction has 1914 states and 2829 transitions. [2021-12-16 10:06:11,999 INFO L587 BuchiCegarLoop]: Abstraction has 1914 states and 2829 transitions. [2021-12-16 10:06:11,999 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2021-12-16 10:06:11,999 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1914 states and 2829 transitions. [2021-12-16 10:06:12,004 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2021-12-16 10:06:12,004 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:06:12,004 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:06:12,005 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:12,005 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:12,006 INFO L791 eck$LassoCheckResult]: Stem: 27721#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 27722#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 27541#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 27257#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 27258#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 28434#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 28435#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 27393#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 27394#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 27848#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 27683#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 27684#L911-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 27460#L916-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 27461#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 27859#L926-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 28036#L931-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 28190#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 28227#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 27471#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 27472#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 28647#L1258-2 assume !(0 == ~T1_E~0); 27766#L1263-1 assume !(0 == ~T2_E~0); 27767#L1268-1 assume !(0 == ~T3_E~0); 28070#L1273-1 assume !(0 == ~T4_E~0); 28629#L1278-1 assume !(0 == ~T5_E~0); 28490#L1283-1 assume !(0 == ~T6_E~0); 28491#L1288-1 assume !(0 == ~T7_E~0); 28727#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 28715#L1298-1 assume !(0 == ~T9_E~0); 28641#L1303-1 assume !(0 == ~T10_E~0); 27286#L1308-1 assume !(0 == ~T11_E~0); 27228#L1313-1 assume !(0 == ~T12_E~0); 27229#L1318-1 assume !(0 == ~T13_E~0); 27235#L1323-1 assume !(0 == ~E_1~0); 27236#L1328-1 assume !(0 == ~E_2~0); 27403#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 28362#L1338-1 assume !(0 == ~E_4~0); 28363#L1343-1 assume !(0 == ~E_5~0); 28464#L1348-1 assume !(0 == ~E_6~0); 28750#L1353-1 assume !(0 == ~E_7~0); 28089#L1358-1 assume !(0 == ~E_8~0); 28090#L1363-1 assume !(0 == ~E_9~0); 28380#L1368-1 assume !(0 == ~E_10~0); 27065#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 27066#L1378-1 assume !(0 == ~E_12~0); 27352#L1383-1 assume !(0 == ~E_13~0); 27353#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 28096#L607 assume 1 == ~m_pc~0; 28097#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 27423#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 28462#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 28016#L1560 assume !(0 != activate_threads_~tmp~1#1); 28017#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 27248#L626 assume !(1 == ~t1_pc~0); 27249#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 27517#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 27518#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 27687#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 27148#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 27149#L645 assume 1 == ~t2_pc~0; 27265#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 27222#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 27899#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 27900#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 27992#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 27993#L664 assume 1 == ~t3_pc~0; 28749#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 26989#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 26990#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 27648#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 27649#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 28657#L683 assume !(1 == ~t4_pc~0); 28212#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 28164#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 28165#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 28199#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 28323#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 27942#L702 assume 1 == ~t5_pc~0; 27943#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 27868#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 28318#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 28616#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 28557#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 27037#L721 assume !(1 == ~t6_pc~0); 27011#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 27012#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 27175#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 27657#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 27658#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 28259#L740 assume 1 == ~t7_pc~0; 27086#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 26899#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 26900#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 26889#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 26890#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 27593#L759 assume !(1 == ~t8_pc~0); 27594#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 27623#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 28316#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 28317#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 28448#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 28726#L778 assume 1 == ~t9_pc~0; 28613#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 27064#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 27004#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 26933#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 26934#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 27261#L797 assume !(1 == ~t10_pc~0); 27262#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 27380#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 28514#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 27764#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 27765#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 28054#L816 assume 1 == ~t11_pc~0; 26969#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 26970#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 27725#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 27664#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 27665#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 28189#L835 assume 1 == ~t12_pc~0; 28067#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 27133#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 27155#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 27296#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 27821#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 27822#L854 assume !(1 == ~t13_pc~0); 27462#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 27463#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 27513#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 27173#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 27174#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 28553#L1401 assume !(1 == ~M_E~0); 27652#L1401-2 assume !(1 == ~T1_E~0); 27653#L1406-1 assume !(1 == ~T2_E~0); 28248#L1411-1 assume !(1 == ~T3_E~0); 28249#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 27915#L1421-1 assume !(1 == ~T5_E~0); 27458#L1426-1 assume !(1 == ~T6_E~0); 27459#L1431-1 assume !(1 == ~T7_E~0); 27007#L1436-1 assume !(1 == ~T8_E~0); 27008#L1441-1 assume !(1 == ~T9_E~0); 27755#L1446-1 assume !(1 == ~T10_E~0); 27756#L1451-1 assume !(1 == ~T11_E~0); 28461#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 28115#L1461-1 assume !(1 == ~T13_E~0); 27676#L1466-1 assume !(1 == ~E_1~0); 27677#L1471-1 assume !(1 == ~E_2~0); 28446#L1476-1 assume !(1 == ~E_3~0); 28447#L1481-1 assume !(1 == ~E_4~0); 28595#L1486-1 assume !(1 == ~E_5~0); 27301#L1491-1 assume !(1 == ~E_6~0); 26941#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 26942#L1501-1 assume !(1 == ~E_8~0); 27753#L1506-1 assume !(1 == ~E_9~0); 27754#L1511-1 assume !(1 == ~E_10~0); 27710#L1516-1 assume !(1 == ~E_11~0); 26885#L1521-1 assume !(1 == ~E_12~0); 26886#L1526-1 assume !(1 == ~E_13~0); 26940#L1531-1 assume { :end_inline_reset_delta_events } true; 27483#L1892-2 [2021-12-16 10:06:12,006 INFO L793 eck$LassoCheckResult]: Loop: 27483#L1892-2 assume !false; 28506#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 28704#L1233 assume !false; 28687#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 28019#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 27999#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 28157#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 26983#L1046 assume !(0 != eval_~tmp~0#1); 26985#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 27019#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 28191#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 28748#L1258-5 assume !(0 == ~T1_E~0); 27161#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 27162#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 28740#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 28746#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 28747#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 27385#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 27386#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 28503#L1298-3 assume !(0 == ~T9_E~0); 28504#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 28663#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 28502#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 28003#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 27163#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 27164#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 28587#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 27306#L1338-3 assume !(0 == ~E_4~0); 27307#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 28419#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 28592#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 28593#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 27959#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 27519#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 27520#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 28276#L1378-3 assume !(0 == ~E_12~0); 28277#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 28458#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 28459#L607-42 assume 1 == ~m_pc~0; 28072#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 27800#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 27801#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 27533#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 27534#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 28055#L626-42 assume 1 == ~t1_pc~0; 27617#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 27618#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 27922#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 27923#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 27197#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 27198#L645-42 assume 1 == ~t2_pc~0; 28656#L646-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 28398#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 28563#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 27404#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 26911#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 26912#L664-42 assume 1 == ~t3_pc~0; 27714#L665-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 27439#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 28690#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 28225#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 28226#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 28391#L683-42 assume !(1 == ~t4_pc~0); 28099#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 28100#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 28232#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 28652#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 28653#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 28497#L702-42 assume 1 == ~t5_pc~0; 27985#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 27610#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 27906#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 28579#L1600-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 26927#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 26928#L721-42 assume 1 == ~t6_pc~0; 27081#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 27101#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 27565#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 28732#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 27737#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 27583#L740-42 assume 1 == ~t7_pc~0; 27584#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 27321#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 27862#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 27717#L1616-42 assume !(0 != activate_threads_~tmp___6~0#1); 27718#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 27991#L759-42 assume 1 == ~t8_pc~0; 27840#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 27772#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 27773#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 27851#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 27852#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 27947#L778-42 assume 1 == ~t9_pc~0; 27784#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 27786#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 28196#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 28101#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 28102#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 28159#L797-42 assume !(1 == ~t10_pc~0); 27328#L797-44 is_transmit10_triggered_~__retres1~10#1 := 0; 27327#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 28328#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 28637#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 28197#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 28198#L816-42 assume 1 == ~t11_pc~0; 26875#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 26876#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 27418#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 27419#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 27498#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 27499#L835-42 assume !(1 == ~t12_pc~0); 27795#L835-44 is_transmit12_triggered_~__retres1~12#1 := 0; 27796#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 27473#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 27474#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 28556#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 28340#L854-42 assume 1 == ~t13_pc~0; 28341#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 27417#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 27027#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 27028#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 27674#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 27675#L1401-3 assume 1 == ~M_E~0;~M_E~0 := 2; 28453#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 27264#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 27128#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 27129#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 27728#L1421-3 assume !(1 == ~T5_E~0); 27729#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 27304#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 27305#L1436-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 26891#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 26892#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 28481#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 27812#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 27465#L1461-3 assume !(1 == ~T13_E~0); 27466#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 28743#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 27405#L1476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 27406#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 27806#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 27433#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 27434#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 27846#L1501-3 assume !(1 == ~E_8~0); 27847#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 28273#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 28263#L1516-3 assume 1 == ~E_11~0;~E_11~0 := 2; 28264#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 27963#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 27964#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 28358#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 27240#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 28133#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 27774#L1911 assume !(0 == start_simulation_~tmp~3#1); 27775#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 28297#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 27364#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 28235#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 27069#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 27070#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 27299#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 27300#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 27483#L1892-2 [2021-12-16 10:06:12,007 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:12,007 INFO L85 PathProgramCache]: Analyzing trace with hash 888419230, now seen corresponding path program 1 times [2021-12-16 10:06:12,007 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:12,007 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [750762503] [2021-12-16 10:06:12,007 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:12,007 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:12,015 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:06:12,032 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:06:12,032 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:06:12,032 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [750762503] [2021-12-16 10:06:12,032 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [750762503] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:06:12,033 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:06:12,033 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:06:12,034 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [714766148] [2021-12-16 10:06:12,034 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:06:12,034 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:06:12,034 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:12,034 INFO L85 PathProgramCache]: Analyzing trace with hash 1867815776, now seen corresponding path program 1 times [2021-12-16 10:06:12,037 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:12,039 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [593657501] [2021-12-16 10:06:12,039 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:12,039 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:12,049 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:06:12,070 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:06:12,070 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:06:12,072 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [593657501] [2021-12-16 10:06:12,073 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [593657501] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:06:12,073 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:06:12,073 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:06:12,073 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [65298053] [2021-12-16 10:06:12,073 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:06:12,074 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:06:12,074 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:06:12,074 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-16 10:06:12,074 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-16 10:06:12,075 INFO L87 Difference]: Start difference. First operand 1914 states and 2829 transitions. cyclomatic complexity: 916 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:12,099 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:06:12,099 INFO L93 Difference]: Finished difference Result 1914 states and 2828 transitions. [2021-12-16 10:06:12,099 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-16 10:06:12,101 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1914 states and 2828 transitions. [2021-12-16 10:06:12,112 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2021-12-16 10:06:12,118 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1914 states to 1914 states and 2828 transitions. [2021-12-16 10:06:12,118 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1914 [2021-12-16 10:06:12,119 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1914 [2021-12-16 10:06:12,119 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1914 states and 2828 transitions. [2021-12-16 10:06:12,121 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:06:12,121 INFO L681 BuchiCegarLoop]: Abstraction has 1914 states and 2828 transitions. [2021-12-16 10:06:12,123 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1914 states and 2828 transitions. [2021-12-16 10:06:12,138 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1914 to 1914. [2021-12-16 10:06:12,140 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1914 states, 1914 states have (on average 1.477533960292581) internal successors, (2828), 1913 states have internal predecessors, (2828), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:12,143 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1914 states to 1914 states and 2828 transitions. [2021-12-16 10:06:12,144 INFO L704 BuchiCegarLoop]: Abstraction has 1914 states and 2828 transitions. [2021-12-16 10:06:12,144 INFO L587 BuchiCegarLoop]: Abstraction has 1914 states and 2828 transitions. [2021-12-16 10:06:12,144 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2021-12-16 10:06:12,144 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1914 states and 2828 transitions. [2021-12-16 10:06:12,148 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2021-12-16 10:06:12,148 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:06:12,148 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:06:12,149 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:12,149 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:12,150 INFO L791 eck$LassoCheckResult]: Stem: 31556#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 31557#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 31376#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 31092#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 31093#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 32269#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 32270#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 31228#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 31229#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 31683#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 31518#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 31519#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 31295#L916-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 31296#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 31694#L926-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 31871#L931-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 32025#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 32062#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 31306#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 31307#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 32482#L1258-2 assume !(0 == ~T1_E~0); 31601#L1263-1 assume !(0 == ~T2_E~0); 31602#L1268-1 assume !(0 == ~T3_E~0); 31905#L1273-1 assume !(0 == ~T4_E~0); 32464#L1278-1 assume !(0 == ~T5_E~0); 32325#L1283-1 assume !(0 == ~T6_E~0); 32326#L1288-1 assume !(0 == ~T7_E~0); 32562#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 32550#L1298-1 assume !(0 == ~T9_E~0); 32476#L1303-1 assume !(0 == ~T10_E~0); 31121#L1308-1 assume !(0 == ~T11_E~0); 31063#L1313-1 assume !(0 == ~T12_E~0); 31064#L1318-1 assume !(0 == ~T13_E~0); 31070#L1323-1 assume !(0 == ~E_1~0); 31071#L1328-1 assume !(0 == ~E_2~0); 31238#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 32197#L1338-1 assume !(0 == ~E_4~0); 32198#L1343-1 assume !(0 == ~E_5~0); 32299#L1348-1 assume !(0 == ~E_6~0); 32585#L1353-1 assume !(0 == ~E_7~0); 31924#L1358-1 assume !(0 == ~E_8~0); 31925#L1363-1 assume !(0 == ~E_9~0); 32215#L1368-1 assume !(0 == ~E_10~0); 30900#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 30901#L1378-1 assume !(0 == ~E_12~0); 31187#L1383-1 assume !(0 == ~E_13~0); 31188#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 31931#L607 assume 1 == ~m_pc~0; 31932#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 31258#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 32297#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 31851#L1560 assume !(0 != activate_threads_~tmp~1#1); 31852#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 31083#L626 assume !(1 == ~t1_pc~0); 31084#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 31352#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 31353#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 31522#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 30983#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 30984#L645 assume 1 == ~t2_pc~0; 31100#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 31057#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 31734#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 31735#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 31827#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 31828#L664 assume 1 == ~t3_pc~0; 32584#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 30824#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 30825#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 31483#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 31484#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 32492#L683 assume !(1 == ~t4_pc~0); 32047#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 31999#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 32000#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 32034#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 32158#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 31777#L702 assume 1 == ~t5_pc~0; 31778#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 31703#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 32153#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 32451#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 32392#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 30872#L721 assume !(1 == ~t6_pc~0); 30846#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 30847#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 31010#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 31492#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 31493#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 32094#L740 assume 1 == ~t7_pc~0; 30921#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 30734#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 30735#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 30724#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 30725#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 31428#L759 assume !(1 == ~t8_pc~0); 31429#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 31458#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 32151#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 32152#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 32283#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 32561#L778 assume 1 == ~t9_pc~0; 32448#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 30899#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 30839#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 30768#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 30769#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 31096#L797 assume !(1 == ~t10_pc~0); 31097#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 31215#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 32349#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 31599#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 31600#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 31889#L816 assume 1 == ~t11_pc~0; 30804#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 30805#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 31560#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 31499#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 31500#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 32024#L835 assume 1 == ~t12_pc~0; 31902#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 30968#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 30990#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 31131#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 31656#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 31657#L854 assume !(1 == ~t13_pc~0); 31297#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 31298#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 31348#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 31008#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 31009#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 32388#L1401 assume !(1 == ~M_E~0); 31487#L1401-2 assume !(1 == ~T1_E~0); 31488#L1406-1 assume !(1 == ~T2_E~0); 32083#L1411-1 assume !(1 == ~T3_E~0); 32084#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 31750#L1421-1 assume !(1 == ~T5_E~0); 31293#L1426-1 assume !(1 == ~T6_E~0); 31294#L1431-1 assume !(1 == ~T7_E~0); 30842#L1436-1 assume !(1 == ~T8_E~0); 30843#L1441-1 assume !(1 == ~T9_E~0); 31590#L1446-1 assume !(1 == ~T10_E~0); 31591#L1451-1 assume !(1 == ~T11_E~0); 32296#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 31950#L1461-1 assume !(1 == ~T13_E~0); 31511#L1466-1 assume !(1 == ~E_1~0); 31512#L1471-1 assume !(1 == ~E_2~0); 32281#L1476-1 assume !(1 == ~E_3~0); 32282#L1481-1 assume !(1 == ~E_4~0); 32430#L1486-1 assume !(1 == ~E_5~0); 31136#L1491-1 assume !(1 == ~E_6~0); 30776#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 30777#L1501-1 assume !(1 == ~E_8~0); 31588#L1506-1 assume !(1 == ~E_9~0); 31589#L1511-1 assume !(1 == ~E_10~0); 31545#L1516-1 assume !(1 == ~E_11~0); 30720#L1521-1 assume !(1 == ~E_12~0); 30721#L1526-1 assume !(1 == ~E_13~0); 30775#L1531-1 assume { :end_inline_reset_delta_events } true; 31318#L1892-2 [2021-12-16 10:06:12,150 INFO L793 eck$LassoCheckResult]: Loop: 31318#L1892-2 assume !false; 32341#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 32539#L1233 assume !false; 32522#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 31854#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 31834#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 31992#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 30818#L1046 assume !(0 != eval_~tmp~0#1); 30820#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 30854#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 32026#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 32583#L1258-5 assume !(0 == ~T1_E~0); 30996#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 30997#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 32575#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 32581#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 32582#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 31220#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 31221#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 32338#L1298-3 assume !(0 == ~T9_E~0); 32339#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 32498#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 32337#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 31838#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 30998#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 30999#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 32422#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 31141#L1338-3 assume !(0 == ~E_4~0); 31142#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 32254#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 32427#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 32428#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 31794#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 31354#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 31355#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 32111#L1378-3 assume !(0 == ~E_12~0); 32112#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 32293#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 32294#L607-42 assume 1 == ~m_pc~0; 31907#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 31635#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 31636#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 31368#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 31369#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 31890#L626-42 assume 1 == ~t1_pc~0; 31452#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 31453#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 31757#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 31758#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 31032#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 31033#L645-42 assume !(1 == ~t2_pc~0); 32232#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 32233#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 32398#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 31239#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 30746#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 30747#L664-42 assume !(1 == ~t3_pc~0); 31273#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 31274#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 32525#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 32060#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 32061#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 32226#L683-42 assume !(1 == ~t4_pc~0); 31934#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 31935#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 32067#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 32487#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 32488#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 32332#L702-42 assume !(1 == ~t5_pc~0); 31444#L702-44 is_transmit5_triggered_~__retres1~5#1 := 0; 31445#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 31741#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 32414#L1600-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 30762#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 30763#L721-42 assume 1 == ~t6_pc~0; 30916#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 30936#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 31400#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 32567#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 31572#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 31418#L740-42 assume !(1 == ~t7_pc~0); 31155#L740-44 is_transmit7_triggered_~__retres1~7#1 := 0; 31156#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 31697#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 31552#L1616-42 assume !(0 != activate_threads_~tmp___6~0#1); 31553#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 31826#L759-42 assume 1 == ~t8_pc~0; 31675#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 31607#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 31608#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 31686#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 31687#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 31782#L778-42 assume 1 == ~t9_pc~0; 31619#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 31621#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 32031#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 31936#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 31937#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 31994#L797-42 assume 1 == ~t10_pc~0; 31161#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 31162#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 32163#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 32472#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 32032#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 32033#L816-42 assume 1 == ~t11_pc~0; 30710#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 30711#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 31253#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 31254#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 31333#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 31334#L835-42 assume 1 == ~t12_pc~0; 31738#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 31631#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 31308#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 31309#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 32391#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 32175#L854-42 assume 1 == ~t13_pc~0; 32176#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 31252#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 30862#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 30863#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 31509#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 31510#L1401-3 assume 1 == ~M_E~0;~M_E~0 := 2; 32288#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 31099#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 30963#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 30964#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 31563#L1421-3 assume !(1 == ~T5_E~0); 31564#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 31139#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 31140#L1436-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 30726#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 30727#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 32316#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 31647#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 31300#L1461-3 assume !(1 == ~T13_E~0); 31301#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 32578#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 31240#L1476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 31241#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 31641#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 31268#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 31269#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 31681#L1501-3 assume !(1 == ~E_8~0); 31682#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 32108#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 32098#L1516-3 assume 1 == ~E_11~0;~E_11~0 := 2; 32099#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 31798#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 31799#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 32193#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 31075#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 31968#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 31609#L1911 assume !(0 == start_simulation_~tmp~3#1); 31610#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 32132#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 31199#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 32070#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 30904#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 30905#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 31134#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 31135#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 31318#L1892-2 [2021-12-16 10:06:12,150 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:12,150 INFO L85 PathProgramCache]: Analyzing trace with hash 1153066720, now seen corresponding path program 1 times [2021-12-16 10:06:12,150 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:12,150 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1326358332] [2021-12-16 10:06:12,151 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:12,151 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:12,158 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:06:12,170 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:06:12,170 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:06:12,170 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1326358332] [2021-12-16 10:06:12,170 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1326358332] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:06:12,170 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:06:12,170 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:06:12,171 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1299874244] [2021-12-16 10:06:12,171 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:06:12,171 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:06:12,171 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:12,171 INFO L85 PathProgramCache]: Analyzing trace with hash 1476580190, now seen corresponding path program 1 times [2021-12-16 10:06:12,172 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:12,172 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [930574216] [2021-12-16 10:06:12,172 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:12,172 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:12,182 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:06:12,198 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:06:12,199 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:06:12,199 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [930574216] [2021-12-16 10:06:12,199 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [930574216] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:06:12,199 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:06:12,199 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:06:12,199 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [817701056] [2021-12-16 10:06:12,199 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:06:12,199 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:06:12,199 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:06:12,200 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-16 10:06:12,200 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-16 10:06:12,200 INFO L87 Difference]: Start difference. First operand 1914 states and 2828 transitions. cyclomatic complexity: 915 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:12,220 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:06:12,220 INFO L93 Difference]: Finished difference Result 1914 states and 2827 transitions. [2021-12-16 10:06:12,220 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-16 10:06:12,221 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1914 states and 2827 transitions. [2021-12-16 10:06:12,227 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2021-12-16 10:06:12,233 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1914 states to 1914 states and 2827 transitions. [2021-12-16 10:06:12,233 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1914 [2021-12-16 10:06:12,234 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1914 [2021-12-16 10:06:12,234 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1914 states and 2827 transitions. [2021-12-16 10:06:12,236 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:06:12,236 INFO L681 BuchiCegarLoop]: Abstraction has 1914 states and 2827 transitions. [2021-12-16 10:06:12,237 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1914 states and 2827 transitions. [2021-12-16 10:06:12,258 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1914 to 1914. [2021-12-16 10:06:12,260 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1914 states, 1914 states have (on average 1.4770114942528736) internal successors, (2827), 1913 states have internal predecessors, (2827), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:12,263 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1914 states to 1914 states and 2827 transitions. [2021-12-16 10:06:12,264 INFO L704 BuchiCegarLoop]: Abstraction has 1914 states and 2827 transitions. [2021-12-16 10:06:12,264 INFO L587 BuchiCegarLoop]: Abstraction has 1914 states and 2827 transitions. [2021-12-16 10:06:12,264 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2021-12-16 10:06:12,264 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1914 states and 2827 transitions. [2021-12-16 10:06:12,268 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2021-12-16 10:06:12,268 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:06:12,268 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:06:12,270 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:12,270 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:12,270 INFO L791 eck$LassoCheckResult]: Stem: 35391#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 35392#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 35211#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 34927#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 34928#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 36104#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 36105#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 35063#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 35064#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 35522#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 35353#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 35354#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 35130#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 35131#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 35529#L926-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 35706#L931-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 35861#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 35897#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 35143#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 35144#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 36317#L1258-2 assume !(0 == ~T1_E~0); 35436#L1263-1 assume !(0 == ~T2_E~0); 35437#L1268-1 assume !(0 == ~T3_E~0); 35740#L1273-1 assume !(0 == ~T4_E~0); 36299#L1278-1 assume !(0 == ~T5_E~0); 36160#L1283-1 assume !(0 == ~T6_E~0); 36161#L1288-1 assume !(0 == ~T7_E~0); 36398#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 36385#L1298-1 assume !(0 == ~T9_E~0); 36311#L1303-1 assume !(0 == ~T10_E~0); 34956#L1308-1 assume !(0 == ~T11_E~0); 34901#L1313-1 assume !(0 == ~T12_E~0); 34902#L1318-1 assume !(0 == ~T13_E~0); 34907#L1323-1 assume !(0 == ~E_1~0); 34908#L1328-1 assume !(0 == ~E_2~0); 35073#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 36032#L1338-1 assume !(0 == ~E_4~0); 36033#L1343-1 assume !(0 == ~E_5~0); 36134#L1348-1 assume !(0 == ~E_6~0); 36420#L1353-1 assume !(0 == ~E_7~0); 35759#L1358-1 assume !(0 == ~E_8~0); 35760#L1363-1 assume !(0 == ~E_9~0); 36051#L1368-1 assume !(0 == ~E_10~0); 34735#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 34736#L1378-1 assume !(0 == ~E_12~0); 35024#L1383-1 assume !(0 == ~E_13~0); 35025#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 35766#L607 assume 1 == ~m_pc~0; 35767#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 35093#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 36132#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 35686#L1560 assume !(0 != activate_threads_~tmp~1#1); 35687#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 34918#L626 assume !(1 == ~t1_pc~0); 34919#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 35189#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 35190#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 35359#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 34821#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 34822#L645 assume 1 == ~t2_pc~0; 34935#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 34892#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 35572#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 35573#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 35662#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 35663#L664 assume 1 == ~t3_pc~0; 36419#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 34663#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 34664#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 35318#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 35319#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 36327#L683 assume !(1 == ~t4_pc~0); 35882#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 35834#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 35835#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 35869#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 35993#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 35616#L702 assume 1 == ~t5_pc~0; 35617#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 35539#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 35988#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 36287#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 36228#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 34707#L721 assume !(1 == ~t6_pc~0); 34681#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 34682#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 34845#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 35327#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 35328#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 35929#L740 assume 1 == ~t7_pc~0; 34756#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 34569#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 34570#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 34559#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 34560#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 35264#L759 assume !(1 == ~t8_pc~0); 35265#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 35293#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 35986#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 35987#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 36118#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 36396#L778 assume 1 == ~t9_pc~0; 36285#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 34734#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 34674#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 34603#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 34604#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 34932#L797 assume !(1 == ~t10_pc~0); 34933#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 35050#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 36184#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 35434#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 35435#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 35724#L816 assume 1 == ~t11_pc~0; 34639#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 34640#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 35397#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 35334#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 35335#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 35859#L835 assume 1 == ~t12_pc~0; 35737#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 34803#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 34825#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 34966#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 35491#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 35492#L854 assume !(1 == ~t13_pc~0); 35132#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 35133#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 35185#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 34843#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 34844#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 36223#L1401 assume !(1 == ~M_E~0); 35322#L1401-2 assume !(1 == ~T1_E~0); 35323#L1406-1 assume !(1 == ~T2_E~0); 35918#L1411-1 assume !(1 == ~T3_E~0); 35919#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 35585#L1421-1 assume !(1 == ~T5_E~0); 35128#L1426-1 assume !(1 == ~T6_E~0); 35129#L1431-1 assume !(1 == ~T7_E~0); 34677#L1436-1 assume !(1 == ~T8_E~0); 34678#L1441-1 assume !(1 == ~T9_E~0); 35425#L1446-1 assume !(1 == ~T10_E~0); 35426#L1451-1 assume !(1 == ~T11_E~0); 36131#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 35785#L1461-1 assume !(1 == ~T13_E~0); 35346#L1466-1 assume !(1 == ~E_1~0); 35347#L1471-1 assume !(1 == ~E_2~0); 36116#L1476-1 assume !(1 == ~E_3~0); 36117#L1481-1 assume !(1 == ~E_4~0); 36265#L1486-1 assume !(1 == ~E_5~0); 34971#L1491-1 assume !(1 == ~E_6~0); 34611#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 34612#L1501-1 assume !(1 == ~E_8~0); 35423#L1506-1 assume !(1 == ~E_9~0); 35424#L1511-1 assume !(1 == ~E_10~0); 35380#L1516-1 assume !(1 == ~E_11~0); 34555#L1521-1 assume !(1 == ~E_12~0); 34556#L1526-1 assume !(1 == ~E_13~0); 34610#L1531-1 assume { :end_inline_reset_delta_events } true; 35153#L1892-2 [2021-12-16 10:06:12,271 INFO L793 eck$LassoCheckResult]: Loop: 35153#L1892-2 assume !false; 36176#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 36374#L1233 assume !false; 36357#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 35689#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 35669#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 35827#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 34653#L1046 assume !(0 != eval_~tmp~0#1); 34655#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 34689#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 35860#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 36418#L1258-5 assume !(0 == ~T1_E~0); 34831#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 34832#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 36410#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 36416#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 36417#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 35055#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 35056#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 36173#L1298-3 assume !(0 == ~T9_E~0); 36174#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 36333#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 36172#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 35673#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 34833#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 34834#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 36257#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 34976#L1338-3 assume !(0 == ~E_4~0); 34977#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 36089#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 36262#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 36263#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 35629#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 35187#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 35188#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 35946#L1378-3 assume !(0 == ~E_12~0); 35947#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 36128#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 36129#L607-42 assume 1 == ~m_pc~0; 35742#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 35470#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 35471#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 35203#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 35204#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 35725#L626-42 assume 1 == ~t1_pc~0; 35287#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 35288#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 35592#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 35593#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 34867#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 34868#L645-42 assume !(1 == ~t2_pc~0); 36067#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 36068#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 36233#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 35074#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 34581#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 34582#L664-42 assume !(1 == ~t3_pc~0); 35108#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 35109#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 36360#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 35895#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 35896#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 36061#L683-42 assume !(1 == ~t4_pc~0); 35769#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 35770#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 35902#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 36322#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 36323#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 36167#L702-42 assume 1 == ~t5_pc~0; 35655#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 35280#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 35576#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 36249#L1600-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 34597#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 34598#L721-42 assume !(1 == ~t6_pc~0); 34752#L721-44 is_transmit6_triggered_~__retres1~6#1 := 0; 34771#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 35235#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 36402#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 35407#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 35253#L740-42 assume 1 == ~t7_pc~0; 35254#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 34991#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 35532#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 35387#L1616-42 assume !(0 != activate_threads_~tmp___6~0#1); 35388#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 35661#L759-42 assume 1 == ~t8_pc~0; 35510#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 35442#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 35443#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 35520#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 35521#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 35615#L778-42 assume 1 == ~t9_pc~0; 35454#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 35456#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 35866#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 35771#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 35772#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 35829#L797-42 assume 1 == ~t10_pc~0; 34996#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 34997#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 35998#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 36307#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 35867#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 35868#L816-42 assume 1 == ~t11_pc~0; 34545#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 34546#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 35088#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 35089#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 35168#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 35169#L835-42 assume 1 == ~t12_pc~0; 35571#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 35466#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 35141#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 35142#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 36226#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 36010#L854-42 assume 1 == ~t13_pc~0; 36011#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 35087#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 34697#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 34698#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 35344#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 35345#L1401-3 assume 1 == ~M_E~0;~M_E~0 := 2; 36123#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 34931#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 34798#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 34799#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 35398#L1421-3 assume !(1 == ~T5_E~0); 35399#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 34974#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 34975#L1436-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 34561#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 34562#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 36151#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 35482#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 35135#L1461-3 assume !(1 == ~T13_E~0); 35136#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 36413#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 35075#L1476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 35076#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 35476#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 35103#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 35104#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 35516#L1501-3 assume !(1 == ~E_8~0); 35517#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 35943#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 35933#L1516-3 assume 1 == ~E_11~0;~E_11~0 := 2; 35934#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 35633#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 35634#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 36028#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 34910#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 35803#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 35444#L1911 assume !(0 == start_simulation_~tmp~3#1); 35445#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 35967#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 35034#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 35905#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 34739#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 34740#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 34969#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 34970#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 35153#L1892-2 [2021-12-16 10:06:12,271 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:12,271 INFO L85 PathProgramCache]: Analyzing trace with hash -778058914, now seen corresponding path program 1 times [2021-12-16 10:06:12,272 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:12,272 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1665532207] [2021-12-16 10:06:12,272 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:12,272 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:12,281 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:06:12,300 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:06:12,301 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:06:12,301 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1665532207] [2021-12-16 10:06:12,301 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1665532207] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:06:12,301 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:06:12,301 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:06:12,301 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1464403694] [2021-12-16 10:06:12,301 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:06:12,302 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:06:12,303 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:12,303 INFO L85 PathProgramCache]: Analyzing trace with hash 95640511, now seen corresponding path program 1 times [2021-12-16 10:06:12,303 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:12,303 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1665416663] [2021-12-16 10:06:12,303 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:12,303 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:12,317 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:06:12,353 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:06:12,354 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:06:12,354 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1665416663] [2021-12-16 10:06:12,354 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1665416663] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:06:12,354 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:06:12,354 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:06:12,355 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1739562308] [2021-12-16 10:06:12,355 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:06:12,355 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:06:12,355 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:06:12,356 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-16 10:06:12,356 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-16 10:06:12,356 INFO L87 Difference]: Start difference. First operand 1914 states and 2827 transitions. cyclomatic complexity: 914 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:12,376 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:06:12,376 INFO L93 Difference]: Finished difference Result 1914 states and 2826 transitions. [2021-12-16 10:06:12,376 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-16 10:06:12,377 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1914 states and 2826 transitions. [2021-12-16 10:06:12,383 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2021-12-16 10:06:12,396 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1914 states to 1914 states and 2826 transitions. [2021-12-16 10:06:12,396 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1914 [2021-12-16 10:06:12,397 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1914 [2021-12-16 10:06:12,397 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1914 states and 2826 transitions. [2021-12-16 10:06:12,399 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:06:12,399 INFO L681 BuchiCegarLoop]: Abstraction has 1914 states and 2826 transitions. [2021-12-16 10:06:12,401 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1914 states and 2826 transitions. [2021-12-16 10:06:12,417 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1914 to 1914. [2021-12-16 10:06:12,430 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1914 states, 1914 states have (on average 1.4764890282131662) internal successors, (2826), 1913 states have internal predecessors, (2826), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:12,435 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1914 states to 1914 states and 2826 transitions. [2021-12-16 10:06:12,435 INFO L704 BuchiCegarLoop]: Abstraction has 1914 states and 2826 transitions. [2021-12-16 10:06:12,435 INFO L587 BuchiCegarLoop]: Abstraction has 1914 states and 2826 transitions. [2021-12-16 10:06:12,435 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2021-12-16 10:06:12,435 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1914 states and 2826 transitions. [2021-12-16 10:06:12,440 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2021-12-16 10:06:12,440 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:06:12,440 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:06:12,442 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:12,442 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:12,442 INFO L791 eck$LassoCheckResult]: Stem: 39226#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 39227#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 39046#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 38762#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 38763#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 39939#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 39940#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 38898#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 38899#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 39357#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 39188#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 39189#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 38965#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 38966#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 39364#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 39541#L931-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 39695#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 39732#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 38978#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 38979#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 40152#L1258-2 assume !(0 == ~T1_E~0); 39271#L1263-1 assume !(0 == ~T2_E~0); 39272#L1268-1 assume !(0 == ~T3_E~0); 39575#L1273-1 assume !(0 == ~T4_E~0); 40134#L1278-1 assume !(0 == ~T5_E~0); 39995#L1283-1 assume !(0 == ~T6_E~0); 39996#L1288-1 assume !(0 == ~T7_E~0); 40233#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 40220#L1298-1 assume !(0 == ~T9_E~0); 40146#L1303-1 assume !(0 == ~T10_E~0); 38791#L1308-1 assume !(0 == ~T11_E~0); 38733#L1313-1 assume !(0 == ~T12_E~0); 38734#L1318-1 assume !(0 == ~T13_E~0); 38742#L1323-1 assume !(0 == ~E_1~0); 38743#L1328-1 assume !(0 == ~E_2~0); 38908#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 39867#L1338-1 assume !(0 == ~E_4~0); 39868#L1343-1 assume !(0 == ~E_5~0); 39969#L1348-1 assume !(0 == ~E_6~0); 40255#L1353-1 assume !(0 == ~E_7~0); 39594#L1358-1 assume !(0 == ~E_8~0); 39595#L1363-1 assume !(0 == ~E_9~0); 39886#L1368-1 assume !(0 == ~E_10~0); 38570#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 38571#L1378-1 assume !(0 == ~E_12~0); 38859#L1383-1 assume !(0 == ~E_13~0); 38860#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 39601#L607 assume 1 == ~m_pc~0; 39602#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 38928#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 39967#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 39521#L1560 assume !(0 != activate_threads_~tmp~1#1); 39522#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 38753#L626 assume !(1 == ~t1_pc~0); 38754#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 39024#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 39025#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 39194#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 38655#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 38656#L645 assume 1 == ~t2_pc~0; 38770#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 38727#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 39407#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 39408#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 39497#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 39498#L664 assume 1 == ~t3_pc~0; 40254#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 38498#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 38499#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 39153#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 39154#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 40162#L683 assume !(1 == ~t4_pc~0); 39717#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 39669#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 39670#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 39704#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 39828#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 39451#L702 assume 1 == ~t5_pc~0; 39452#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 39374#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 39823#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 40122#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 40063#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 38542#L721 assume !(1 == ~t6_pc~0); 38516#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 38517#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 38680#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 39162#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 39163#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 39764#L740 assume 1 == ~t7_pc~0; 38591#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 38404#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 38405#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 38394#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 38395#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 39099#L759 assume !(1 == ~t8_pc~0); 39100#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 39128#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 39821#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 39822#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 39953#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 40231#L778 assume 1 == ~t9_pc~0; 40120#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 38569#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 38509#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 38438#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 38439#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 38767#L797 assume !(1 == ~t10_pc~0); 38768#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 38885#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 40019#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 39269#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 39270#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 39559#L816 assume 1 == ~t11_pc~0; 38474#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 38475#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 39232#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 39169#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 39170#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 39694#L835 assume 1 == ~t12_pc~0; 39572#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 38638#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 38660#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 38801#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 39326#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 39327#L854 assume !(1 == ~t13_pc~0); 38967#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 38968#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 39020#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 38678#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 38679#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 40058#L1401 assume !(1 == ~M_E~0); 39157#L1401-2 assume !(1 == ~T1_E~0); 39158#L1406-1 assume !(1 == ~T2_E~0); 39753#L1411-1 assume !(1 == ~T3_E~0); 39754#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 39420#L1421-1 assume !(1 == ~T5_E~0); 38963#L1426-1 assume !(1 == ~T6_E~0); 38964#L1431-1 assume !(1 == ~T7_E~0); 38512#L1436-1 assume !(1 == ~T8_E~0); 38513#L1441-1 assume !(1 == ~T9_E~0); 39262#L1446-1 assume !(1 == ~T10_E~0); 39263#L1451-1 assume !(1 == ~T11_E~0); 39966#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 39620#L1461-1 assume !(1 == ~T13_E~0); 39181#L1466-1 assume !(1 == ~E_1~0); 39182#L1471-1 assume !(1 == ~E_2~0); 39951#L1476-1 assume !(1 == ~E_3~0); 39952#L1481-1 assume !(1 == ~E_4~0); 40100#L1486-1 assume !(1 == ~E_5~0); 38806#L1491-1 assume !(1 == ~E_6~0); 38446#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 38447#L1501-1 assume !(1 == ~E_8~0); 39258#L1506-1 assume !(1 == ~E_9~0); 39259#L1511-1 assume !(1 == ~E_10~0); 39215#L1516-1 assume !(1 == ~E_11~0); 38392#L1521-1 assume !(1 == ~E_12~0); 38393#L1526-1 assume !(1 == ~E_13~0); 38445#L1531-1 assume { :end_inline_reset_delta_events } true; 38988#L1892-2 [2021-12-16 10:06:12,443 INFO L793 eck$LassoCheckResult]: Loop: 38988#L1892-2 assume !false; 40011#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 40209#L1233 assume !false; 40192#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 39524#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 39504#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 39662#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 38488#L1046 assume !(0 != eval_~tmp~0#1); 38490#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 38524#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 39696#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 40253#L1258-5 assume !(0 == ~T1_E~0); 38670#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 38671#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 40245#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 40251#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 40252#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 38892#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 38893#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 40008#L1298-3 assume !(0 == ~T9_E~0); 40009#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 40168#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 40007#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 39508#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 38666#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 38667#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 40092#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 38811#L1338-3 assume !(0 == ~E_4~0); 38812#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 39924#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 40097#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 40098#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 39464#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 39022#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 39023#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 39781#L1378-3 assume !(0 == ~E_12~0); 39782#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 39963#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 39964#L607-42 assume 1 == ~m_pc~0; 39577#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 39305#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 39306#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 39038#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 39039#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 39560#L626-42 assume 1 == ~t1_pc~0; 39122#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 39123#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 39427#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 39428#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 38702#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 38703#L645-42 assume 1 == ~t2_pc~0; 40161#L646-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 39903#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 40068#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 38909#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 38416#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 38417#L664-42 assume 1 == ~t3_pc~0; 39219#L665-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 38944#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 40195#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 39730#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 39731#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 39896#L683-42 assume !(1 == ~t4_pc~0); 39604#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 39605#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 39737#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 40157#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 40158#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 40002#L702-42 assume 1 == ~t5_pc~0; 39490#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 39115#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 39411#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 40084#L1600-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 38432#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 38433#L721-42 assume 1 == ~t6_pc~0; 38586#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 38606#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 39070#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 40237#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 39242#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 39088#L740-42 assume 1 == ~t7_pc~0; 39089#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 38826#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 39367#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 39222#L1616-42 assume !(0 != activate_threads_~tmp___6~0#1); 39223#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 39496#L759-42 assume 1 == ~t8_pc~0; 39345#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 39277#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 39278#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 39355#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 39356#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 39450#L778-42 assume 1 == ~t9_pc~0; 39289#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 39291#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 39700#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 39606#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 39607#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 39664#L797-42 assume !(1 == ~t10_pc~0); 38833#L797-44 is_transmit10_triggered_~__retres1~10#1 := 0; 38832#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 39833#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 40142#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 39702#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 39703#L816-42 assume 1 == ~t11_pc~0; 38380#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 38381#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 38923#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 38924#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 39003#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 39004#L835-42 assume !(1 == ~t12_pc~0); 39300#L835-44 is_transmit12_triggered_~__retres1~12#1 := 0; 39301#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 38976#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 38977#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 40061#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 39845#L854-42 assume 1 == ~t13_pc~0; 39846#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 38920#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 38532#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 38533#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 39179#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 39180#L1401-3 assume 1 == ~M_E~0;~M_E~0 := 2; 39958#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 38766#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 38633#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 38634#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 39233#L1421-3 assume !(1 == ~T5_E~0); 39234#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 38809#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 38810#L1436-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 38396#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 38397#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 39986#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 39317#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 38970#L1461-3 assume !(1 == ~T13_E~0); 38971#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 40248#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 38910#L1476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 38911#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 39311#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 38938#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 38939#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 39351#L1501-3 assume !(1 == ~E_8~0); 39352#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 39778#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 39768#L1516-3 assume 1 == ~E_11~0;~E_11~0 := 2; 39769#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 39468#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 39469#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 39863#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 38745#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 39638#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 39279#L1911 assume !(0 == start_simulation_~tmp~3#1); 39280#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 39802#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 38869#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 39740#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 38574#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 38575#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 38804#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 38805#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 38988#L1892-2 [2021-12-16 10:06:12,443 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:12,443 INFO L85 PathProgramCache]: Analyzing trace with hash 1619928924, now seen corresponding path program 1 times [2021-12-16 10:06:12,443 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:12,444 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1030779804] [2021-12-16 10:06:12,444 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:12,444 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:12,453 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:06:12,471 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:06:12,471 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:06:12,471 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1030779804] [2021-12-16 10:06:12,471 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1030779804] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:06:12,472 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:06:12,472 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:06:12,472 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1730652096] [2021-12-16 10:06:12,472 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:06:12,472 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:06:12,472 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:12,473 INFO L85 PathProgramCache]: Analyzing trace with hash 1867815776, now seen corresponding path program 2 times [2021-12-16 10:06:12,473 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:12,473 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1097623613] [2021-12-16 10:06:12,473 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:12,473 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:12,483 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:06:12,503 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:06:12,504 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:06:12,504 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1097623613] [2021-12-16 10:06:12,504 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1097623613] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:06:12,504 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:06:12,504 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:06:12,504 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1563012714] [2021-12-16 10:06:12,504 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:06:12,505 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:06:12,505 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:06:12,505 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-16 10:06:12,505 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-16 10:06:12,506 INFO L87 Difference]: Start difference. First operand 1914 states and 2826 transitions. cyclomatic complexity: 913 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:12,525 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:06:12,525 INFO L93 Difference]: Finished difference Result 1914 states and 2825 transitions. [2021-12-16 10:06:12,526 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-16 10:06:12,526 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1914 states and 2825 transitions. [2021-12-16 10:06:12,532 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2021-12-16 10:06:12,537 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1914 states to 1914 states and 2825 transitions. [2021-12-16 10:06:12,537 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1914 [2021-12-16 10:06:12,538 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1914 [2021-12-16 10:06:12,538 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1914 states and 2825 transitions. [2021-12-16 10:06:12,540 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:06:12,540 INFO L681 BuchiCegarLoop]: Abstraction has 1914 states and 2825 transitions. [2021-12-16 10:06:12,542 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1914 states and 2825 transitions. [2021-12-16 10:06:12,557 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1914 to 1914. [2021-12-16 10:06:12,560 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1914 states, 1914 states have (on average 1.4759665621734588) internal successors, (2825), 1913 states have internal predecessors, (2825), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:12,563 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1914 states to 1914 states and 2825 transitions. [2021-12-16 10:06:12,563 INFO L704 BuchiCegarLoop]: Abstraction has 1914 states and 2825 transitions. [2021-12-16 10:06:12,563 INFO L587 BuchiCegarLoop]: Abstraction has 1914 states and 2825 transitions. [2021-12-16 10:06:12,563 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2021-12-16 10:06:12,563 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1914 states and 2825 transitions. [2021-12-16 10:06:12,567 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2021-12-16 10:06:12,568 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:06:12,568 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:06:12,569 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:12,569 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:12,570 INFO L791 eck$LassoCheckResult]: Stem: 43061#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 43062#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 42881#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 42597#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 42598#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 43774#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 43775#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 42733#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 42734#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 43192#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 43023#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 43024#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 42800#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 42801#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 43199#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 43376#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 43530#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 43567#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 42813#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 42814#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 43987#L1258-2 assume !(0 == ~T1_E~0); 43106#L1263-1 assume !(0 == ~T2_E~0); 43107#L1268-1 assume !(0 == ~T3_E~0); 43410#L1273-1 assume !(0 == ~T4_E~0); 43969#L1278-1 assume !(0 == ~T5_E~0); 43830#L1283-1 assume !(0 == ~T6_E~0); 43831#L1288-1 assume !(0 == ~T7_E~0); 44068#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 44055#L1298-1 assume !(0 == ~T9_E~0); 43981#L1303-1 assume !(0 == ~T10_E~0); 42626#L1308-1 assume !(0 == ~T11_E~0); 42568#L1313-1 assume !(0 == ~T12_E~0); 42569#L1318-1 assume !(0 == ~T13_E~0); 42577#L1323-1 assume !(0 == ~E_1~0); 42578#L1328-1 assume !(0 == ~E_2~0); 42743#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 43702#L1338-1 assume !(0 == ~E_4~0); 43703#L1343-1 assume !(0 == ~E_5~0); 43804#L1348-1 assume !(0 == ~E_6~0); 44090#L1353-1 assume !(0 == ~E_7~0); 43429#L1358-1 assume !(0 == ~E_8~0); 43430#L1363-1 assume !(0 == ~E_9~0); 43720#L1368-1 assume !(0 == ~E_10~0); 42405#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 42406#L1378-1 assume !(0 == ~E_12~0); 42694#L1383-1 assume !(0 == ~E_13~0); 42695#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 43436#L607 assume 1 == ~m_pc~0; 43437#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 42763#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 43802#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 43356#L1560 assume !(0 != activate_threads_~tmp~1#1); 43357#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 42588#L626 assume !(1 == ~t1_pc~0); 42589#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 42857#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 42858#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 43029#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 42490#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 42491#L645 assume 1 == ~t2_pc~0; 42605#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 42562#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 43242#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 43243#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 43332#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 43333#L664 assume 1 == ~t3_pc~0; 44089#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 42333#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 42334#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 42988#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 42989#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 43997#L683 assume !(1 == ~t4_pc~0); 43552#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 43504#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 43505#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 43539#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 43663#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 43286#L702 assume 1 == ~t5_pc~0; 43287#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 43209#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 43658#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 43957#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 43898#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 42377#L721 assume !(1 == ~t6_pc~0); 42351#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 42352#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 42515#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 42997#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 42998#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 43599#L740 assume 1 == ~t7_pc~0; 42426#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 42239#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 42240#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 42229#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 42230#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 42934#L759 assume !(1 == ~t8_pc~0); 42935#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 42963#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 43656#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 43657#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 43788#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 44066#L778 assume 1 == ~t9_pc~0; 43953#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 42404#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 42344#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 42273#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 42274#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 42602#L797 assume !(1 == ~t10_pc~0); 42603#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 42720#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 43854#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 43104#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 43105#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 43394#L816 assume 1 == ~t11_pc~0; 42309#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 42310#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 43067#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 43004#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 43005#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 43529#L835 assume 1 == ~t12_pc~0; 43407#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 42473#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 42495#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 42636#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 43161#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 43162#L854 assume !(1 == ~t13_pc~0); 42802#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 42803#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 42853#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 42513#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 42514#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 43893#L1401 assume !(1 == ~M_E~0); 42992#L1401-2 assume !(1 == ~T1_E~0); 42993#L1406-1 assume !(1 == ~T2_E~0); 43588#L1411-1 assume !(1 == ~T3_E~0); 43589#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 43255#L1421-1 assume !(1 == ~T5_E~0); 42798#L1426-1 assume !(1 == ~T6_E~0); 42799#L1431-1 assume !(1 == ~T7_E~0); 42347#L1436-1 assume !(1 == ~T8_E~0); 42348#L1441-1 assume !(1 == ~T9_E~0); 43097#L1446-1 assume !(1 == ~T10_E~0); 43098#L1451-1 assume !(1 == ~T11_E~0); 43801#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 43455#L1461-1 assume !(1 == ~T13_E~0); 43016#L1466-1 assume !(1 == ~E_1~0); 43017#L1471-1 assume !(1 == ~E_2~0); 43786#L1476-1 assume !(1 == ~E_3~0); 43787#L1481-1 assume !(1 == ~E_4~0); 43935#L1486-1 assume !(1 == ~E_5~0); 42641#L1491-1 assume !(1 == ~E_6~0); 42281#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 42282#L1501-1 assume !(1 == ~E_8~0); 43093#L1506-1 assume !(1 == ~E_9~0); 43094#L1511-1 assume !(1 == ~E_10~0); 43050#L1516-1 assume !(1 == ~E_11~0); 42227#L1521-1 assume !(1 == ~E_12~0); 42228#L1526-1 assume !(1 == ~E_13~0); 42280#L1531-1 assume { :end_inline_reset_delta_events } true; 42823#L1892-2 [2021-12-16 10:06:12,570 INFO L793 eck$LassoCheckResult]: Loop: 42823#L1892-2 assume !false; 43846#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 44044#L1233 assume !false; 44027#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 43359#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 43339#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 43497#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 42323#L1046 assume !(0 != eval_~tmp~0#1); 42325#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 42359#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 43531#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 44088#L1258-5 assume !(0 == ~T1_E~0); 42503#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 42504#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 44080#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 44086#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 44087#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 42727#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 42728#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 43843#L1298-3 assume !(0 == ~T9_E~0); 43844#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 44003#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 43842#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 43343#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 42505#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 42506#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 43927#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 42646#L1338-3 assume !(0 == ~E_4~0); 42647#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 43759#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 43933#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 43934#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 43301#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 42859#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 42860#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 43616#L1378-3 assume !(0 == ~E_12~0); 43617#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 43798#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 43799#L607-42 assume 1 == ~m_pc~0; 43414#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 43140#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 43141#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 42873#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 42874#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 43395#L626-42 assume 1 == ~t1_pc~0; 42957#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 42958#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 43262#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 43263#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 42537#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 42538#L645-42 assume !(1 == ~t2_pc~0); 43736#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 43737#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 43903#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 42744#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 42251#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 42252#L664-42 assume !(1 == ~t3_pc~0); 42778#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 42779#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 44030#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 43565#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 43566#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 43731#L683-42 assume 1 == ~t4_pc~0; 44096#L684-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 43440#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 43571#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 43992#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 43993#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 43837#L702-42 assume !(1 == ~t5_pc~0); 42949#L702-44 is_transmit5_triggered_~__retres1~5#1 := 0; 42950#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 43246#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 43919#L1600-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 42267#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 42268#L721-42 assume 1 == ~t6_pc~0; 42421#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 42441#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 42905#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 44072#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 43077#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 42923#L740-42 assume !(1 == ~t7_pc~0); 42660#L740-44 is_transmit7_triggered_~__retres1~7#1 := 0; 42661#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 43202#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 43057#L1616-42 assume !(0 != activate_threads_~tmp___6~0#1); 43058#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 43331#L759-42 assume 1 == ~t8_pc~0; 43180#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 43112#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 43113#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 43190#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 43191#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 43285#L778-42 assume 1 == ~t9_pc~0; 43124#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 43126#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 43535#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 43441#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 43442#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 43499#L797-42 assume 1 == ~t10_pc~0; 42666#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 42667#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 43668#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 43977#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 43537#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 43538#L816-42 assume 1 == ~t11_pc~0; 42215#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 42216#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 42758#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 42759#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 42838#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 42839#L835-42 assume 1 == ~t12_pc~0; 43241#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 43135#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 42811#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 42812#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 43896#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 43680#L854-42 assume 1 == ~t13_pc~0; 43681#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 42755#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 42367#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 42368#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 43014#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 43015#L1401-3 assume 1 == ~M_E~0;~M_E~0 := 2; 43793#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 42601#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 42468#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 42469#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 43068#L1421-3 assume !(1 == ~T5_E~0); 43069#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 42644#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 42645#L1436-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 42231#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 42232#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 43821#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 43152#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 42805#L1461-3 assume !(1 == ~T13_E~0); 42806#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 44083#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 42745#L1476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 42746#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 43146#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 42773#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 42774#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 43185#L1501-3 assume !(1 == ~E_8~0); 43186#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 43613#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 43603#L1516-3 assume 1 == ~E_11~0;~E_11~0 := 2; 43604#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 43303#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 43304#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 43698#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 42580#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 43473#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 43114#L1911 assume !(0 == start_simulation_~tmp~3#1); 43115#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 43637#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 42704#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 43575#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 42409#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 42410#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 42639#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 42640#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 42823#L1892-2 [2021-12-16 10:06:12,571 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:12,571 INFO L85 PathProgramCache]: Analyzing trace with hash 1281641374, now seen corresponding path program 1 times [2021-12-16 10:06:12,571 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:12,571 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [125499360] [2021-12-16 10:06:12,571 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:12,572 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:12,579 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:06:12,591 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:06:12,591 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:06:12,591 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [125499360] [2021-12-16 10:06:12,591 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [125499360] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:06:12,592 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:06:12,592 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:06:12,592 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [944928968] [2021-12-16 10:06:12,592 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:06:12,592 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:06:12,593 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:12,593 INFO L85 PathProgramCache]: Analyzing trace with hash -1815330241, now seen corresponding path program 1 times [2021-12-16 10:06:12,593 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:12,593 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1941040940] [2021-12-16 10:06:12,593 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:12,593 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:12,601 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:06:12,618 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:06:12,618 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:06:12,618 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1941040940] [2021-12-16 10:06:12,618 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1941040940] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:06:12,619 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:06:12,619 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:06:12,619 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1275376959] [2021-12-16 10:06:12,619 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:06:12,619 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:06:12,619 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:06:12,620 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-16 10:06:12,620 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-16 10:06:12,620 INFO L87 Difference]: Start difference. First operand 1914 states and 2825 transitions. cyclomatic complexity: 912 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:12,638 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:06:12,638 INFO L93 Difference]: Finished difference Result 1914 states and 2824 transitions. [2021-12-16 10:06:12,638 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-16 10:06:12,639 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1914 states and 2824 transitions. [2021-12-16 10:06:12,644 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2021-12-16 10:06:12,648 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1914 states to 1914 states and 2824 transitions. [2021-12-16 10:06:12,648 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1914 [2021-12-16 10:06:12,649 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1914 [2021-12-16 10:06:12,650 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1914 states and 2824 transitions. [2021-12-16 10:06:12,651 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:06:12,651 INFO L681 BuchiCegarLoop]: Abstraction has 1914 states and 2824 transitions. [2021-12-16 10:06:12,653 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1914 states and 2824 transitions. [2021-12-16 10:06:12,668 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1914 to 1914. [2021-12-16 10:06:12,671 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1914 states, 1914 states have (on average 1.4754440961337514) internal successors, (2824), 1913 states have internal predecessors, (2824), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:12,674 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1914 states to 1914 states and 2824 transitions. [2021-12-16 10:06:12,674 INFO L704 BuchiCegarLoop]: Abstraction has 1914 states and 2824 transitions. [2021-12-16 10:06:12,674 INFO L587 BuchiCegarLoop]: Abstraction has 1914 states and 2824 transitions. [2021-12-16 10:06:12,674 INFO L425 BuchiCegarLoop]: ======== Iteration 13============ [2021-12-16 10:06:12,674 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1914 states and 2824 transitions. [2021-12-16 10:06:12,678 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2021-12-16 10:06:12,678 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:06:12,678 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:06:12,680 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:12,680 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:12,680 INFO L791 eck$LassoCheckResult]: Stem: 46896#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 46897#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 46716#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 46432#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 46433#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 47609#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 47610#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 46568#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 46569#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 47027#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 46858#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 46859#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 46635#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 46636#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 47034#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 47211#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 47365#L936-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 47402#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 46648#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 46649#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 47822#L1258-2 assume !(0 == ~T1_E~0); 46941#L1263-1 assume !(0 == ~T2_E~0); 46942#L1268-1 assume !(0 == ~T3_E~0); 47245#L1273-1 assume !(0 == ~T4_E~0); 47804#L1278-1 assume !(0 == ~T5_E~0); 47665#L1283-1 assume !(0 == ~T6_E~0); 47666#L1288-1 assume !(0 == ~T7_E~0); 47902#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 47890#L1298-1 assume !(0 == ~T9_E~0); 47816#L1303-1 assume !(0 == ~T10_E~0); 46461#L1308-1 assume !(0 == ~T11_E~0); 46403#L1313-1 assume !(0 == ~T12_E~0); 46404#L1318-1 assume !(0 == ~T13_E~0); 46412#L1323-1 assume !(0 == ~E_1~0); 46413#L1328-1 assume !(0 == ~E_2~0); 46578#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 47537#L1338-1 assume !(0 == ~E_4~0); 47538#L1343-1 assume !(0 == ~E_5~0); 47639#L1348-1 assume !(0 == ~E_6~0); 47925#L1353-1 assume !(0 == ~E_7~0); 47264#L1358-1 assume !(0 == ~E_8~0); 47265#L1363-1 assume !(0 == ~E_9~0); 47555#L1368-1 assume !(0 == ~E_10~0); 46240#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 46241#L1378-1 assume !(0 == ~E_12~0); 46529#L1383-1 assume !(0 == ~E_13~0); 46530#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 47271#L607 assume 1 == ~m_pc~0; 47272#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 46598#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 47637#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 47191#L1560 assume !(0 != activate_threads_~tmp~1#1); 47192#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 46423#L626 assume !(1 == ~t1_pc~0); 46424#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 46692#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 46693#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 46862#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 46325#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 46326#L645 assume 1 == ~t2_pc~0; 46440#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 46397#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 47077#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 47078#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 47167#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 47168#L664 assume 1 == ~t3_pc~0; 47924#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 46166#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 46167#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 46823#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 46824#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 47832#L683 assume !(1 == ~t4_pc~0); 47387#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 47339#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 47340#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 47374#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 47498#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 47121#L702 assume 1 == ~t5_pc~0; 47122#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 47044#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 47493#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 47792#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 47733#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 46212#L721 assume !(1 == ~t6_pc~0); 46186#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 46187#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 46350#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 46832#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 46833#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 47434#L740 assume 1 == ~t7_pc~0; 46261#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 46074#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 46075#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 46064#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 46065#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 46769#L759 assume !(1 == ~t8_pc~0); 46770#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 46798#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 47491#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 47492#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 47623#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 47901#L778 assume 1 == ~t9_pc~0; 47788#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 46239#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 46179#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 46108#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 46109#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 46437#L797 assume !(1 == ~t10_pc~0); 46438#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 46555#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 47689#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 46939#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 46940#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 47229#L816 assume 1 == ~t11_pc~0; 46144#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 46145#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 46902#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 46839#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 46840#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 47364#L835 assume 1 == ~t12_pc~0; 47242#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 46308#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 46330#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 46471#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 46996#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 46997#L854 assume !(1 == ~t13_pc~0); 46637#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 46638#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 46688#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 46348#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 46349#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 47728#L1401 assume !(1 == ~M_E~0); 46827#L1401-2 assume !(1 == ~T1_E~0); 46828#L1406-1 assume !(1 == ~T2_E~0); 47423#L1411-1 assume !(1 == ~T3_E~0); 47424#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 47090#L1421-1 assume !(1 == ~T5_E~0); 46633#L1426-1 assume !(1 == ~T6_E~0); 46634#L1431-1 assume !(1 == ~T7_E~0); 46182#L1436-1 assume !(1 == ~T8_E~0); 46183#L1441-1 assume !(1 == ~T9_E~0); 46932#L1446-1 assume !(1 == ~T10_E~0); 46933#L1451-1 assume !(1 == ~T11_E~0); 47636#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 47290#L1461-1 assume !(1 == ~T13_E~0); 46851#L1466-1 assume !(1 == ~E_1~0); 46852#L1471-1 assume !(1 == ~E_2~0); 47621#L1476-1 assume !(1 == ~E_3~0); 47622#L1481-1 assume !(1 == ~E_4~0); 47770#L1486-1 assume !(1 == ~E_5~0); 46476#L1491-1 assume !(1 == ~E_6~0); 46116#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 46117#L1501-1 assume !(1 == ~E_8~0); 46928#L1506-1 assume !(1 == ~E_9~0); 46929#L1511-1 assume !(1 == ~E_10~0); 46885#L1516-1 assume !(1 == ~E_11~0); 46062#L1521-1 assume !(1 == ~E_12~0); 46063#L1526-1 assume !(1 == ~E_13~0); 46115#L1531-1 assume { :end_inline_reset_delta_events } true; 46658#L1892-2 [2021-12-16 10:06:12,680 INFO L793 eck$LassoCheckResult]: Loop: 46658#L1892-2 assume !false; 47681#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 47879#L1233 assume !false; 47862#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 47194#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 47174#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 47332#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 46158#L1046 assume !(0 != eval_~tmp~0#1); 46160#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 46194#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 47366#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 47923#L1258-5 assume !(0 == ~T1_E~0); 46338#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 46339#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 47915#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 47921#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 47922#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 46562#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 46563#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 47678#L1298-3 assume !(0 == ~T9_E~0); 47679#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 47838#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 47677#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 47178#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 46340#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 46341#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 47762#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 46481#L1338-3 assume !(0 == ~E_4~0); 46482#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 47594#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 47768#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 47769#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 47136#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 46694#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 46695#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 47451#L1378-3 assume !(0 == ~E_12~0); 47452#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 47633#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 47634#L607-42 assume 1 == ~m_pc~0; 47249#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 46975#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 46976#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 46708#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 46709#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 47233#L626-42 assume 1 == ~t1_pc~0; 46795#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 46796#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 47097#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 47098#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 46372#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 46373#L645-42 assume !(1 == ~t2_pc~0); 47572#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 47573#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 47738#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 46579#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 46086#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 46087#L664-42 assume !(1 == ~t3_pc~0); 46610#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 46611#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 47865#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 47400#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 47401#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 47566#L683-42 assume !(1 == ~t4_pc~0); 47273#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 47274#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 47406#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 47827#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 47828#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 47672#L702-42 assume 1 == ~t5_pc~0; 47160#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 46784#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 47081#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 47754#L1600-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 46100#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 46101#L721-42 assume 1 == ~t6_pc~0; 46256#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 46276#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 46740#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 47907#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 46912#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 46758#L740-42 assume 1 == ~t7_pc~0; 46759#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 46496#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 47037#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 46892#L1616-42 assume !(0 != activate_threads_~tmp___6~0#1); 46893#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 47166#L759-42 assume 1 == ~t8_pc~0; 47015#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 46947#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 46948#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 47025#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 47026#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 47120#L778-42 assume !(1 == ~t9_pc~0); 46960#L778-44 is_transmit9_triggered_~__retres1~9#1 := 0; 46961#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 47370#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 47275#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 47276#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 47334#L797-42 assume 1 == ~t10_pc~0; 46501#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 46502#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 47503#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 47812#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 47372#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 47373#L816-42 assume 1 == ~t11_pc~0; 46050#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 46051#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 46593#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 46594#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 46673#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 46674#L835-42 assume 1 == ~t12_pc~0; 47076#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 46968#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 46646#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 46647#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 47731#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 47515#L854-42 assume 1 == ~t13_pc~0; 47516#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 46590#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 46202#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 46203#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 46849#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 46850#L1401-3 assume 1 == ~M_E~0;~M_E~0 := 2; 47628#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 46436#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 46303#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 46304#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 46903#L1421-3 assume !(1 == ~T5_E~0); 46904#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 46479#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 46480#L1436-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 46066#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 46067#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 47656#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 46987#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 46640#L1461-3 assume !(1 == ~T13_E~0); 46641#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 47918#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 46580#L1476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 46581#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 46981#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 46608#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 46609#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 47020#L1501-3 assume !(1 == ~E_8~0); 47021#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 47448#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 47438#L1516-3 assume 1 == ~E_11~0;~E_11~0 := 2; 47439#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 47138#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 47139#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 47533#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 46415#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 47308#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 46949#L1911 assume !(0 == start_simulation_~tmp~3#1); 46950#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 47472#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 46539#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 47410#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 46244#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 46245#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 46474#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 46475#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 46658#L1892-2 [2021-12-16 10:06:12,681 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:12,681 INFO L85 PathProgramCache]: Analyzing trace with hash 855086876, now seen corresponding path program 1 times [2021-12-16 10:06:12,681 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:12,681 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [205356374] [2021-12-16 10:06:12,681 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:12,682 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:12,689 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:06:12,700 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:06:12,701 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:06:12,701 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [205356374] [2021-12-16 10:06:12,701 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [205356374] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:06:12,701 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:06:12,701 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:06:12,701 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1184679867] [2021-12-16 10:06:12,701 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:06:12,702 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:06:12,702 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:12,702 INFO L85 PathProgramCache]: Analyzing trace with hash -199797377, now seen corresponding path program 1 times [2021-12-16 10:06:12,702 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:12,702 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1253266929] [2021-12-16 10:06:12,702 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:12,703 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:12,710 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:06:12,726 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:06:12,727 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:06:12,727 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1253266929] [2021-12-16 10:06:12,727 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1253266929] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:06:12,727 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:06:12,727 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:06:12,727 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1268405303] [2021-12-16 10:06:12,727 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:06:12,728 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:06:12,728 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:06:12,728 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-16 10:06:12,728 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-16 10:06:12,728 INFO L87 Difference]: Start difference. First operand 1914 states and 2824 transitions. cyclomatic complexity: 911 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:12,746 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:06:12,747 INFO L93 Difference]: Finished difference Result 1914 states and 2823 transitions. [2021-12-16 10:06:12,747 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-16 10:06:12,747 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1914 states and 2823 transitions. [2021-12-16 10:06:12,753 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2021-12-16 10:06:12,757 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1914 states to 1914 states and 2823 transitions. [2021-12-16 10:06:12,757 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1914 [2021-12-16 10:06:12,758 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1914 [2021-12-16 10:06:12,758 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1914 states and 2823 transitions. [2021-12-16 10:06:12,760 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:06:12,760 INFO L681 BuchiCegarLoop]: Abstraction has 1914 states and 2823 transitions. [2021-12-16 10:06:12,762 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1914 states and 2823 transitions. [2021-12-16 10:06:12,778 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1914 to 1914. [2021-12-16 10:06:12,780 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1914 states, 1914 states have (on average 1.474921630094044) internal successors, (2823), 1913 states have internal predecessors, (2823), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:12,783 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1914 states to 1914 states and 2823 transitions. [2021-12-16 10:06:12,783 INFO L704 BuchiCegarLoop]: Abstraction has 1914 states and 2823 transitions. [2021-12-16 10:06:12,783 INFO L587 BuchiCegarLoop]: Abstraction has 1914 states and 2823 transitions. [2021-12-16 10:06:12,783 INFO L425 BuchiCegarLoop]: ======== Iteration 14============ [2021-12-16 10:06:12,783 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1914 states and 2823 transitions. [2021-12-16 10:06:12,787 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2021-12-16 10:06:12,787 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:06:12,787 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:06:12,789 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:12,789 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:12,789 INFO L791 eck$LassoCheckResult]: Stem: 50731#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 50732#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 50551#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 50267#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 50268#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 51444#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 51445#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 50403#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 50404#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 50860#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 50693#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 50694#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 50470#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 50471#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 50869#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 51046#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 51200#L936-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 51237#L941-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 50483#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 50484#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 51657#L1258-2 assume !(0 == ~T1_E~0); 50776#L1263-1 assume !(0 == ~T2_E~0); 50777#L1268-1 assume !(0 == ~T3_E~0); 51080#L1273-1 assume !(0 == ~T4_E~0); 51639#L1278-1 assume !(0 == ~T5_E~0); 51500#L1283-1 assume !(0 == ~T6_E~0); 51501#L1288-1 assume !(0 == ~T7_E~0); 51737#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 51725#L1298-1 assume !(0 == ~T9_E~0); 51651#L1303-1 assume !(0 == ~T10_E~0); 50296#L1308-1 assume !(0 == ~T11_E~0); 50238#L1313-1 assume !(0 == ~T12_E~0); 50239#L1318-1 assume !(0 == ~T13_E~0); 50247#L1323-1 assume !(0 == ~E_1~0); 50248#L1328-1 assume !(0 == ~E_2~0); 50413#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 51372#L1338-1 assume !(0 == ~E_4~0); 51373#L1343-1 assume !(0 == ~E_5~0); 51474#L1348-1 assume !(0 == ~E_6~0); 51760#L1353-1 assume !(0 == ~E_7~0); 51099#L1358-1 assume !(0 == ~E_8~0); 51100#L1363-1 assume !(0 == ~E_9~0); 51390#L1368-1 assume !(0 == ~E_10~0); 50075#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 50076#L1378-1 assume !(0 == ~E_12~0); 50364#L1383-1 assume !(0 == ~E_13~0); 50365#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 51106#L607 assume 1 == ~m_pc~0; 51107#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 50433#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 51472#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 51026#L1560 assume !(0 != activate_threads_~tmp~1#1); 51027#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 50258#L626 assume !(1 == ~t1_pc~0); 50259#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 50527#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 50528#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 50697#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 50158#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 50159#L645 assume 1 == ~t2_pc~0; 50275#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 50232#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 50912#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 50913#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 51002#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 51003#L664 assume 1 == ~t3_pc~0; 51759#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 49999#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 50000#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 50658#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 50659#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 51667#L683 assume !(1 == ~t4_pc~0); 51222#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 51174#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 51175#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 51209#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 51333#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 50956#L702 assume 1 == ~t5_pc~0; 50957#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 50879#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 51328#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 51627#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 51568#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 50047#L721 assume !(1 == ~t6_pc~0); 50021#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 50022#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 50185#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 50667#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 50668#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 51269#L740 assume 1 == ~t7_pc~0; 50096#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 49909#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 49910#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 49899#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 49900#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 50604#L759 assume !(1 == ~t8_pc~0); 50605#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 50633#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 51326#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 51327#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 51458#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 51736#L778 assume 1 == ~t9_pc~0; 51623#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 50074#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 50014#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 49943#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 49944#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 50272#L797 assume !(1 == ~t10_pc~0); 50273#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 50390#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 51524#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 50774#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 50775#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 51064#L816 assume 1 == ~t11_pc~0; 49979#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 49980#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 50737#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 50674#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 50675#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 51199#L835 assume 1 == ~t12_pc~0; 51077#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 50143#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 50165#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 50306#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 50831#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 50832#L854 assume !(1 == ~t13_pc~0); 50472#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 50473#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 50523#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 50183#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 50184#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 51563#L1401 assume !(1 == ~M_E~0); 50662#L1401-2 assume !(1 == ~T1_E~0); 50663#L1406-1 assume !(1 == ~T2_E~0); 51258#L1411-1 assume !(1 == ~T3_E~0); 51259#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 50925#L1421-1 assume !(1 == ~T5_E~0); 50468#L1426-1 assume !(1 == ~T6_E~0); 50469#L1431-1 assume !(1 == ~T7_E~0); 50017#L1436-1 assume !(1 == ~T8_E~0); 50018#L1441-1 assume !(1 == ~T9_E~0); 50767#L1446-1 assume !(1 == ~T10_E~0); 50768#L1451-1 assume !(1 == ~T11_E~0); 51471#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 51125#L1461-1 assume !(1 == ~T13_E~0); 50686#L1466-1 assume !(1 == ~E_1~0); 50687#L1471-1 assume !(1 == ~E_2~0); 51456#L1476-1 assume !(1 == ~E_3~0); 51457#L1481-1 assume !(1 == ~E_4~0); 51605#L1486-1 assume !(1 == ~E_5~0); 50311#L1491-1 assume !(1 == ~E_6~0); 49951#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 49952#L1501-1 assume !(1 == ~E_8~0); 50763#L1506-1 assume !(1 == ~E_9~0); 50764#L1511-1 assume !(1 == ~E_10~0); 50720#L1516-1 assume !(1 == ~E_11~0); 49895#L1521-1 assume !(1 == ~E_12~0); 49896#L1526-1 assume !(1 == ~E_13~0); 49950#L1531-1 assume { :end_inline_reset_delta_events } true; 50493#L1892-2 [2021-12-16 10:06:12,789 INFO L793 eck$LassoCheckResult]: Loop: 50493#L1892-2 assume !false; 51516#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 51714#L1233 assume !false; 51697#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 51029#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 51009#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 51167#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 49993#L1046 assume !(0 != eval_~tmp~0#1); 49995#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 50029#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 51201#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 51758#L1258-5 assume !(0 == ~T1_E~0); 50171#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 50172#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 51750#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 51756#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 51757#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 50397#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 50398#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 51513#L1298-3 assume !(0 == ~T9_E~0); 51514#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 51673#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 51512#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 51013#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 50173#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 50174#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 51597#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 50316#L1338-3 assume !(0 == ~E_4~0); 50317#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 51429#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 51603#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 51604#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 50971#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 50529#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 50530#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 51286#L1378-3 assume !(0 == ~E_12~0); 51287#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 51468#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 51469#L607-42 assume 1 == ~m_pc~0; 51084#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 50810#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 50811#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 50543#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 50544#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 51068#L626-42 assume 1 == ~t1_pc~0; 50630#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 50631#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 50932#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 50933#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 50207#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 50208#L645-42 assume 1 == ~t2_pc~0; 51666#L646-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 51408#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 51573#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 50414#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 49921#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 49922#L664-42 assume !(1 == ~t3_pc~0); 50449#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 50450#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 51700#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 51235#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 51236#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 51401#L683-42 assume 1 == ~t4_pc~0; 51766#L684-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 51112#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 51242#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 51662#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 51663#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 51510#L702-42 assume 1 == ~t5_pc~0; 50998#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 50620#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 50918#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 51589#L1600-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 49935#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 49936#L721-42 assume 1 == ~t6_pc~0; 50090#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 50111#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 50575#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 51742#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 50747#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 50591#L740-42 assume 1 == ~t7_pc~0; 50592#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 50328#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 50872#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 50727#L1616-42 assume !(0 != activate_threads_~tmp___6~0#1); 50728#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 51001#L759-42 assume 1 == ~t8_pc~0; 50850#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 50782#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 50783#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 50858#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 50859#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 50955#L778-42 assume 1 == ~t9_pc~0; 50794#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 50796#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 51204#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 51108#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 51109#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 51169#L797-42 assume 1 == ~t10_pc~0; 50336#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 50337#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 51338#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 51647#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 51207#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 51208#L816-42 assume 1 == ~t11_pc~0; 49885#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 49886#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 50428#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 50429#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 50508#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 50509#L835-42 assume !(1 == ~t12_pc~0); 50802#L835-44 is_transmit12_triggered_~__retres1~12#1 := 0; 50803#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 50481#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 50482#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 51566#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 51350#L854-42 assume 1 == ~t13_pc~0; 51351#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 50425#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 50037#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 50038#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 50684#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 50685#L1401-3 assume 1 == ~M_E~0;~M_E~0 := 2; 51463#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 50271#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 50138#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 50139#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 50738#L1421-3 assume !(1 == ~T5_E~0); 50739#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 50314#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 50315#L1436-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 49901#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 49902#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 51491#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 50822#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 50475#L1461-3 assume !(1 == ~T13_E~0); 50476#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 51753#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 50415#L1476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 50416#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 50816#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 50443#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 50444#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 50855#L1501-3 assume !(1 == ~E_8~0); 50856#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 51283#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 51272#L1516-3 assume 1 == ~E_11~0;~E_11~0 := 2; 51273#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 50973#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 50974#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 51368#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 50250#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 51143#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 50784#L1911 assume !(0 == start_simulation_~tmp~3#1); 50785#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 51307#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 50374#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 51245#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 50079#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 50080#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 50309#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 50310#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 50493#L1892-2 [2021-12-16 10:06:12,790 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:12,790 INFO L85 PathProgramCache]: Analyzing trace with hash 1395516382, now seen corresponding path program 1 times [2021-12-16 10:06:12,790 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:12,790 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1364937439] [2021-12-16 10:06:12,790 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:12,791 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:12,799 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:06:12,828 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:06:12,829 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:06:12,829 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1364937439] [2021-12-16 10:06:12,829 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1364937439] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:06:12,829 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:06:12,829 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-16 10:06:12,829 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1717329195] [2021-12-16 10:06:12,830 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:06:12,830 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:06:12,830 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:12,830 INFO L85 PathProgramCache]: Analyzing trace with hash -1807690879, now seen corresponding path program 1 times [2021-12-16 10:06:12,830 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:12,831 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1380002221] [2021-12-16 10:06:12,831 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:12,831 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:12,839 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:06:12,855 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:06:12,855 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:06:12,856 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1380002221] [2021-12-16 10:06:12,856 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1380002221] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:06:12,856 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:06:12,856 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:06:12,856 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [671973327] [2021-12-16 10:06:12,856 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:06:12,857 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:06:12,857 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:06:12,857 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-16 10:06:12,857 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-16 10:06:12,857 INFO L87 Difference]: Start difference. First operand 1914 states and 2823 transitions. cyclomatic complexity: 910 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 2 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:12,942 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:06:12,943 INFO L93 Difference]: Finished difference Result 3555 states and 5213 transitions. [2021-12-16 10:06:12,943 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-16 10:06:12,943 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3555 states and 5213 transitions. [2021-12-16 10:06:12,953 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3382 [2021-12-16 10:06:12,959 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3555 states to 3555 states and 5213 transitions. [2021-12-16 10:06:12,960 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3555 [2021-12-16 10:06:12,962 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3555 [2021-12-16 10:06:12,962 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3555 states and 5213 transitions. [2021-12-16 10:06:12,965 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:06:12,965 INFO L681 BuchiCegarLoop]: Abstraction has 3555 states and 5213 transitions. [2021-12-16 10:06:12,967 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3555 states and 5213 transitions. [2021-12-16 10:06:13,002 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3555 to 3555. [2021-12-16 10:06:13,006 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3555 states, 3555 states have (on average 1.4663853727144867) internal successors, (5213), 3554 states have internal predecessors, (5213), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:13,012 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3555 states to 3555 states and 5213 transitions. [2021-12-16 10:06:13,012 INFO L704 BuchiCegarLoop]: Abstraction has 3555 states and 5213 transitions. [2021-12-16 10:06:13,013 INFO L587 BuchiCegarLoop]: Abstraction has 3555 states and 5213 transitions. [2021-12-16 10:06:13,013 INFO L425 BuchiCegarLoop]: ======== Iteration 15============ [2021-12-16 10:06:13,013 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3555 states and 5213 transitions. [2021-12-16 10:06:13,020 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3382 [2021-12-16 10:06:13,020 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:06:13,020 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:06:13,022 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:13,022 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:13,022 INFO L791 eck$LassoCheckResult]: Stem: 56211#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 56212#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 56030#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 55745#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 55746#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 56929#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 56930#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 55882#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 55883#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 56338#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 56173#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 56174#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 55949#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 55950#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 56349#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 56530#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 56682#L936-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 56719#L941-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 55960#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 55961#L1258 assume !(0 == ~M_E~0); 57166#L1258-2 assume !(0 == ~T1_E~0); 56256#L1263-1 assume !(0 == ~T2_E~0); 56257#L1268-1 assume !(0 == ~T3_E~0); 56564#L1273-1 assume !(0 == ~T4_E~0); 57145#L1278-1 assume !(0 == ~T5_E~0); 56987#L1283-1 assume !(0 == ~T6_E~0); 56988#L1288-1 assume !(0 == ~T7_E~0); 57269#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 57255#L1298-1 assume !(0 == ~T9_E~0); 57160#L1303-1 assume !(0 == ~T10_E~0); 55775#L1308-1 assume !(0 == ~T11_E~0); 55716#L1313-1 assume !(0 == ~T12_E~0); 55717#L1318-1 assume !(0 == ~T13_E~0); 55723#L1323-1 assume !(0 == ~E_1~0); 55724#L1328-1 assume !(0 == ~E_2~0); 55892#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 56856#L1338-1 assume !(0 == ~E_4~0); 56857#L1343-1 assume !(0 == ~E_5~0); 56960#L1348-1 assume !(0 == ~E_6~0); 57302#L1353-1 assume !(0 == ~E_7~0); 56583#L1358-1 assume !(0 == ~E_8~0); 56584#L1363-1 assume !(0 == ~E_9~0); 56875#L1368-1 assume !(0 == ~E_10~0); 55552#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 55553#L1378-1 assume !(0 == ~E_12~0); 55841#L1383-1 assume !(0 == ~E_13~0); 55842#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 56589#L607 assume !(1 == ~m_pc~0); 55911#L607-2 is_master_triggered_~__retres1~0#1 := 0; 55912#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 56958#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 56509#L1560 assume !(0 != activate_threads_~tmp~1#1); 56510#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 55736#L626 assume !(1 == ~t1_pc~0); 55737#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 56006#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 56007#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 56177#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 55635#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 55636#L645 assume 1 == ~t2_pc~0; 55753#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 55710#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 56389#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 56390#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 56484#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 56485#L664 assume 1 == ~t3_pc~0; 57299#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 55475#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 55476#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 56138#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 56139#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 57177#L683 assume !(1 == ~t4_pc~0); 56704#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 56656#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 56657#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 56691#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 56817#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 56432#L702 assume 1 == ~t5_pc~0; 56433#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 56358#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 56812#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 57130#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 57062#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 55524#L721 assume !(1 == ~t6_pc~0); 55497#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 55498#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 55662#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 56147#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 56148#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 56752#L740 assume 1 == ~t7_pc~0; 55573#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 55385#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 55386#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 55375#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 55376#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 56083#L759 assume !(1 == ~t8_pc~0); 56084#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 56113#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 56810#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 56811#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 56943#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 57268#L778 assume 1 == ~t9_pc~0; 57127#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 55551#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 55490#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 55419#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 55420#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 55749#L797 assume !(1 == ~t10_pc~0); 55750#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 55869#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 57015#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 56254#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 56255#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 56548#L816 assume 1 == ~t11_pc~0; 55455#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 55456#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 56215#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 56154#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 56155#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 56681#L835 assume 1 == ~t12_pc~0; 56561#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 55620#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 55642#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 55785#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 56311#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 56312#L854 assume !(1 == ~t13_pc~0); 55951#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 55952#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 56002#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 55660#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 55661#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 57057#L1401 assume !(1 == ~M_E~0); 56142#L1401-2 assume !(1 == ~T1_E~0); 56143#L1406-1 assume !(1 == ~T2_E~0); 56741#L1411-1 assume !(1 == ~T3_E~0); 56742#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 56405#L1421-1 assume !(1 == ~T5_E~0); 55947#L1426-1 assume !(1 == ~T6_E~0); 55948#L1431-1 assume !(1 == ~T7_E~0); 55493#L1436-1 assume !(1 == ~T8_E~0); 55494#L1441-1 assume !(1 == ~T9_E~0); 56245#L1446-1 assume !(1 == ~T10_E~0); 56246#L1451-1 assume !(1 == ~T11_E~0); 56957#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 56607#L1461-1 assume !(1 == ~T13_E~0); 56166#L1466-1 assume !(1 == ~E_1~0); 56167#L1471-1 assume !(1 == ~E_2~0); 56941#L1476-1 assume !(1 == ~E_3~0); 56942#L1481-1 assume !(1 == ~E_4~0); 57107#L1486-1 assume !(1 == ~E_5~0); 55790#L1491-1 assume !(1 == ~E_6~0); 55427#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 55428#L1501-1 assume !(1 == ~E_8~0); 56243#L1506-1 assume !(1 == ~E_9~0); 56244#L1511-1 assume !(1 == ~E_10~0); 56200#L1516-1 assume !(1 == ~E_11~0); 55371#L1521-1 assume !(1 == ~E_12~0); 55372#L1526-1 assume !(1 == ~E_13~0); 55426#L1531-1 assume { :end_inline_reset_delta_events } true; 55972#L1892-2 [2021-12-16 10:06:13,023 INFO L793 eck$LassoCheckResult]: Loop: 55972#L1892-2 assume !false; 57358#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 57240#L1233 assume !false; 57241#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 56512#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 56491#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 56649#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 55469#L1046 assume !(0 != eval_~tmp~0#1); 55471#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 58740#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 58739#L1258-3 assume !(0 == ~M_E~0); 58738#L1258-5 assume !(0 == ~T1_E~0); 58737#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 58736#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 58735#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 58734#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 58733#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 58732#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 58731#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 58730#L1298-3 assume !(0 == ~T9_E~0); 58729#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 58728#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 58727#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 58726#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 58725#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 58724#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 58442#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 58441#L1338-3 assume !(0 == ~E_4~0); 58413#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 58412#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 58410#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 58408#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 58405#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 58403#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 58401#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 58399#L1378-3 assume !(0 == ~E_12~0); 58397#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 58395#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 58392#L607-42 assume !(1 == ~m_pc~0); 58389#L607-44 is_master_triggered_~__retres1~0#1 := 0; 58387#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 58385#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 58383#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 58381#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 58378#L626-42 assume 1 == ~t1_pc~0; 58375#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 58373#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 58372#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 58371#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 58370#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 58369#L645-42 assume 1 == ~t2_pc~0; 58368#L646-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 58366#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 58365#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 58364#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 58363#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 58362#L664-42 assume 1 == ~t3_pc~0; 58360#L665-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 58359#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 58358#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 58357#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 58356#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 58355#L683-42 assume !(1 == ~t4_pc~0); 58350#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 58348#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 58345#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 58343#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 58341#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 58339#L702-42 assume 1 == ~t5_pc~0; 58336#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 58334#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 58333#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 58332#L1600-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 58286#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 58285#L721-42 assume !(1 == ~t6_pc~0); 58282#L721-44 is_transmit6_triggered_~__retres1~6#1 := 0; 58280#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 58277#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 58275#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 58263#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 58260#L740-42 assume 1 == ~t7_pc~0; 58257#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 58255#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 58253#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 58251#L1616-42 assume !(0 != activate_threads_~tmp___6~0#1); 58250#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 58249#L759-42 assume 1 == ~t8_pc~0; 58247#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 58246#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 56517#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 56341#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 56342#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 56437#L778-42 assume 1 == ~t9_pc~0; 56274#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 56276#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 56688#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 56594#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 56595#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 58233#L797-42 assume 1 == ~t10_pc~0; 58230#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 58228#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 58225#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 58224#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 58223#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 58222#L816-42 assume !(1 == ~t11_pc~0); 58220#L816-44 is_transmit11_triggered_~__retres1~11#1 := 0; 58219#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 58218#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 58216#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 58214#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 57883#L835-42 assume 1 == ~t12_pc~0; 57881#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 57065#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 55962#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 55963#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 57061#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 56834#L854-42 assume !(1 == ~t13_pc~0); 55905#L854-44 is_transmit13_triggered_~__retres1~13#1 := 0; 55906#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 55514#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 55515#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 56164#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 56165#L1401-3 assume !(1 == ~M_E~0); 56948#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 55752#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 55615#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 55616#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 56218#L1421-3 assume !(1 == ~T5_E~0); 56219#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 55793#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 55794#L1436-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 55377#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 55378#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 56978#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 56302#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 55954#L1461-3 assume !(1 == ~T13_E~0); 55955#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 57852#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 57851#L1476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 57850#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 57849#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 57848#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 57220#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 56336#L1501-3 assume !(1 == ~E_8~0); 56337#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 57846#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 57845#L1516-3 assume 1 == ~E_11~0;~E_11~0 := 2; 57844#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 57843#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 57842#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 57735#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 57728#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 57726#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 57724#L1911 assume !(0 == start_simulation_~tmp~3#1); 57098#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 56791#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 55853#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 56727#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 55556#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 55557#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 55788#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 55789#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 55972#L1892-2 [2021-12-16 10:06:13,023 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:13,023 INFO L85 PathProgramCache]: Analyzing trace with hash -1486214853, now seen corresponding path program 1 times [2021-12-16 10:06:13,023 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:13,024 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [568776783] [2021-12-16 10:06:13,024 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:13,024 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:13,032 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:06:13,048 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:06:13,048 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:06:13,048 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [568776783] [2021-12-16 10:06:13,049 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [568776783] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:06:13,049 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:06:13,049 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:06:13,049 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1043288826] [2021-12-16 10:06:13,049 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:06:13,049 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:06:13,050 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:13,050 INFO L85 PathProgramCache]: Analyzing trace with hash -1550267110, now seen corresponding path program 1 times [2021-12-16 10:06:13,050 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:13,050 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2015648106] [2021-12-16 10:06:13,050 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:13,050 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:13,059 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:06:13,075 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:06:13,076 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:06:13,076 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2015648106] [2021-12-16 10:06:13,076 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2015648106] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:06:13,076 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:06:13,076 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:06:13,077 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1682994153] [2021-12-16 10:06:13,077 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:06:13,077 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:06:13,077 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:06:13,078 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-16 10:06:13,078 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-16 10:06:13,078 INFO L87 Difference]: Start difference. First operand 3555 states and 5213 transitions. cyclomatic complexity: 1659 Second operand has 4 states, 4 states have (on average 39.75) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:13,183 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:06:13,184 INFO L93 Difference]: Finished difference Result 5188 states and 7586 transitions. [2021-12-16 10:06:13,184 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-16 10:06:13,184 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5188 states and 7586 transitions. [2021-12-16 10:06:13,198 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4996 [2021-12-16 10:06:13,208 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5188 states to 5188 states and 7586 transitions. [2021-12-16 10:06:13,208 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5188 [2021-12-16 10:06:13,211 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5188 [2021-12-16 10:06:13,211 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5188 states and 7586 transitions. [2021-12-16 10:06:13,216 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:06:13,216 INFO L681 BuchiCegarLoop]: Abstraction has 5188 states and 7586 transitions. [2021-12-16 10:06:13,220 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5188 states and 7586 transitions. [2021-12-16 10:06:13,258 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5188 to 3555. [2021-12-16 10:06:13,263 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3555 states, 3555 states have (on average 1.4655414908579465) internal successors, (5210), 3554 states have internal predecessors, (5210), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:13,268 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3555 states to 3555 states and 5210 transitions. [2021-12-16 10:06:13,268 INFO L704 BuchiCegarLoop]: Abstraction has 3555 states and 5210 transitions. [2021-12-16 10:06:13,269 INFO L587 BuchiCegarLoop]: Abstraction has 3555 states and 5210 transitions. [2021-12-16 10:06:13,269 INFO L425 BuchiCegarLoop]: ======== Iteration 16============ [2021-12-16 10:06:13,269 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3555 states and 5210 transitions. [2021-12-16 10:06:13,275 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3382 [2021-12-16 10:06:13,275 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:06:13,275 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:06:13,277 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:13,277 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:13,277 INFO L791 eck$LassoCheckResult]: Stem: 64960#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 64961#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 64780#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 64495#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 64496#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 65673#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 65674#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 64632#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 64633#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 65087#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 64922#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 64923#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 64699#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 64700#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 65098#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 65275#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 65427#L936-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 65464#L941-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 64710#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 64711#L1258 assume !(0 == ~M_E~0); 65887#L1258-2 assume !(0 == ~T1_E~0); 65005#L1263-1 assume !(0 == ~T2_E~0); 65006#L1268-1 assume !(0 == ~T3_E~0); 65309#L1273-1 assume !(0 == ~T4_E~0); 65869#L1278-1 assume !(0 == ~T5_E~0); 65729#L1283-1 assume !(0 == ~T6_E~0); 65730#L1288-1 assume !(0 == ~T7_E~0); 65967#L1293-1 assume !(0 == ~T8_E~0); 65955#L1298-1 assume !(0 == ~T9_E~0); 65881#L1303-1 assume !(0 == ~T10_E~0); 64524#L1308-1 assume !(0 == ~T11_E~0); 64466#L1313-1 assume !(0 == ~T12_E~0); 64467#L1318-1 assume !(0 == ~T13_E~0); 64473#L1323-1 assume !(0 == ~E_1~0); 64474#L1328-1 assume !(0 == ~E_2~0); 64642#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 65600#L1338-1 assume !(0 == ~E_4~0); 65601#L1343-1 assume !(0 == ~E_5~0); 65703#L1348-1 assume !(0 == ~E_6~0); 65990#L1353-1 assume !(0 == ~E_7~0); 65328#L1358-1 assume !(0 == ~E_8~0); 65329#L1363-1 assume !(0 == ~E_9~0); 65618#L1368-1 assume !(0 == ~E_10~0); 64303#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 64304#L1378-1 assume !(0 == ~E_12~0); 64591#L1383-1 assume !(0 == ~E_13~0); 64592#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 65334#L607 assume !(1 == ~m_pc~0); 64661#L607-2 is_master_triggered_~__retres1~0#1 := 0; 64662#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 65701#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 65255#L1560 assume !(0 != activate_threads_~tmp~1#1); 65256#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 64486#L626 assume !(1 == ~t1_pc~0); 64487#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 64756#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 64757#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 64926#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 64386#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 64387#L645 assume 1 == ~t2_pc~0; 64503#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 64460#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 65138#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 65139#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 65231#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 65232#L664 assume 1 == ~t3_pc~0; 65989#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 64228#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 64229#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 64887#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 64888#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 65897#L683 assume !(1 == ~t4_pc~0); 65449#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 65401#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 65402#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 65436#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 65561#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 65181#L702 assume 1 == ~t5_pc~0; 65182#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 65107#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 65556#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 65856#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 65797#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 64275#L721 assume !(1 == ~t6_pc~0); 64250#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 64251#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 64413#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 64896#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 64897#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 65497#L740 assume 1 == ~t7_pc~0; 64324#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 64138#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 64139#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 64128#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 64129#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 64832#L759 assume !(1 == ~t8_pc~0); 64833#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 64862#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 65554#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 65555#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 65687#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 65966#L778 assume 1 == ~t9_pc~0; 65853#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 64302#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 64243#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 64172#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 64173#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 64499#L797 assume !(1 == ~t10_pc~0); 64500#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 64619#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 65753#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 65003#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 65004#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 65293#L816 assume 1 == ~t11_pc~0; 64208#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 64209#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 64964#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 64903#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 64904#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 65426#L835 assume 1 == ~t12_pc~0; 65306#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 64371#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 64393#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 64534#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 65060#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 65061#L854 assume !(1 == ~t13_pc~0); 64701#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 64702#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 64752#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 64411#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 64412#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 65792#L1401 assume !(1 == ~M_E~0); 64891#L1401-2 assume !(1 == ~T1_E~0); 64892#L1406-1 assume !(1 == ~T2_E~0); 65486#L1411-1 assume !(1 == ~T3_E~0); 65487#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 65154#L1421-1 assume !(1 == ~T5_E~0); 64697#L1426-1 assume !(1 == ~T6_E~0); 64698#L1431-1 assume !(1 == ~T7_E~0); 64246#L1436-1 assume !(1 == ~T8_E~0); 64247#L1441-1 assume !(1 == ~T9_E~0); 64994#L1446-1 assume !(1 == ~T10_E~0); 64995#L1451-1 assume !(1 == ~T11_E~0); 65700#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 65352#L1461-1 assume !(1 == ~T13_E~0); 64915#L1466-1 assume !(1 == ~E_1~0); 64916#L1471-1 assume !(1 == ~E_2~0); 65685#L1476-1 assume !(1 == ~E_3~0); 65686#L1481-1 assume !(1 == ~E_4~0); 65835#L1486-1 assume !(1 == ~E_5~0); 64539#L1491-1 assume !(1 == ~E_6~0); 64180#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 64181#L1501-1 assume !(1 == ~E_8~0); 64992#L1506-1 assume !(1 == ~E_9~0); 64993#L1511-1 assume !(1 == ~E_10~0); 64949#L1516-1 assume !(1 == ~E_11~0); 64124#L1521-1 assume !(1 == ~E_12~0); 64125#L1526-1 assume !(1 == ~E_13~0); 64179#L1531-1 assume { :end_inline_reset_delta_events } true; 64722#L1892-2 [2021-12-16 10:06:13,277 INFO L793 eck$LassoCheckResult]: Loop: 64722#L1892-2 assume !false; 65745#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 65944#L1233 assume !false; 65927#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 65258#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 65238#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 65394#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 64222#L1046 assume !(0 != eval_~tmp~0#1); 64224#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 64258#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 65428#L1258-3 assume !(0 == ~M_E~0); 65988#L1258-5 assume !(0 == ~T1_E~0); 64399#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 64400#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 65980#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 65986#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 65987#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 64624#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 64625#L1293-3 assume !(0 == ~T8_E~0); 65742#L1298-3 assume !(0 == ~T9_E~0); 65743#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 65903#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 65741#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 65242#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 64401#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 64402#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 65827#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 64544#L1338-3 assume !(0 == ~E_4~0); 64545#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 65658#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 65832#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 65833#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 65198#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 64758#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 64759#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 65515#L1378-3 assume !(0 == ~E_12~0); 65516#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 65697#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 65698#L607-42 assume !(1 == ~m_pc~0); 65312#L607-44 is_master_triggered_~__retres1~0#1 := 0; 65039#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 65040#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 64772#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 64773#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 65294#L626-42 assume 1 == ~t1_pc~0; 64856#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 64857#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 65161#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 65162#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 64435#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 64436#L645-42 assume !(1 == ~t2_pc~0); 65635#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 65636#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 65803#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 64643#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 64150#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 64151#L664-42 assume !(1 == ~t3_pc~0); 64677#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 64678#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 65930#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 65462#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 65463#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 65629#L683-42 assume !(1 == ~t4_pc~0); 65337#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 65338#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 65469#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 65892#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 65893#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 65736#L702-42 assume !(1 == ~t5_pc~0); 64848#L702-44 is_transmit5_triggered_~__retres1~5#1 := 0; 64849#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 65145#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 65819#L1600-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 64166#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 64167#L721-42 assume !(1 == ~t6_pc~0); 64320#L721-44 is_transmit6_triggered_~__retres1~6#1 := 0; 64339#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 64804#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 65972#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 64976#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 64822#L740-42 assume 1 == ~t7_pc~0; 64823#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 64560#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 65101#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 64956#L1616-42 assume !(0 != activate_threads_~tmp___6~0#1); 64957#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 65230#L759-42 assume 1 == ~t8_pc~0; 65079#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 65011#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 65012#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 65090#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 65091#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 65186#L778-42 assume !(1 == ~t9_pc~0); 65024#L778-44 is_transmit9_triggered_~__retres1~9#1 := 0; 65025#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 65433#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 65339#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 65340#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 65396#L797-42 assume 1 == ~t10_pc~0; 64565#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 64566#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 65566#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 65877#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 65434#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 65435#L816-42 assume 1 == ~t11_pc~0; 64114#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 64115#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 64657#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 64658#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 64737#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 64738#L835-42 assume 1 == ~t12_pc~0; 65142#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 65035#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 64712#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 64713#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 65796#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 65578#L854-42 assume 1 == ~t13_pc~0; 65579#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 64656#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 64266#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 64267#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 64913#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 64914#L1401-3 assume !(1 == ~M_E~0); 65692#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 64502#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 64366#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 64367#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 64967#L1421-3 assume !(1 == ~T5_E~0); 64968#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 64542#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 64543#L1436-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 64130#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 64131#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 65720#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 65051#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 64704#L1461-3 assume !(1 == ~T13_E~0); 64705#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 65983#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 64644#L1476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 64645#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 65045#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 64672#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 64673#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 65085#L1501-3 assume !(1 == ~E_8~0); 65086#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 65512#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 65502#L1516-3 assume 1 == ~E_11~0;~E_11~0 := 2; 65503#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 65202#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 65203#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 65596#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 64478#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 65370#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 65013#L1911 assume !(0 == start_simulation_~tmp~3#1); 65014#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 65535#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 64603#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 65472#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 64307#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 64308#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 64537#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 64538#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 64722#L1892-2 [2021-12-16 10:06:13,278 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:13,278 INFO L85 PathProgramCache]: Analyzing trace with hash -1197395463, now seen corresponding path program 1 times [2021-12-16 10:06:13,278 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:13,278 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1928815219] [2021-12-16 10:06:13,278 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:13,279 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:13,286 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:06:13,302 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:06:13,302 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:06:13,302 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1928815219] [2021-12-16 10:06:13,302 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1928815219] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:06:13,303 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:06:13,303 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:06:13,303 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [368210712] [2021-12-16 10:06:13,303 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:06:13,303 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:06:13,303 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:13,304 INFO L85 PathProgramCache]: Analyzing trace with hash -553594666, now seen corresponding path program 1 times [2021-12-16 10:06:13,304 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:13,304 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [370134050] [2021-12-16 10:06:13,304 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:13,304 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:13,312 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:06:13,330 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:06:13,331 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:06:13,331 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [370134050] [2021-12-16 10:06:13,331 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [370134050] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:06:13,331 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:06:13,331 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:06:13,331 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [697892289] [2021-12-16 10:06:13,332 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:06:13,332 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:06:13,332 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:06:13,332 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-16 10:06:13,332 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-16 10:06:13,333 INFO L87 Difference]: Start difference. First operand 3555 states and 5210 transitions. cyclomatic complexity: 1656 Second operand has 4 states, 4 states have (on average 39.75) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:13,499 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:06:13,500 INFO L93 Difference]: Finished difference Result 5081 states and 7426 transitions. [2021-12-16 10:06:13,500 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-16 10:06:13,500 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5081 states and 7426 transitions. [2021-12-16 10:06:13,515 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4896 [2021-12-16 10:06:13,526 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5081 states to 5081 states and 7426 transitions. [2021-12-16 10:06:13,527 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5081 [2021-12-16 10:06:13,530 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5081 [2021-12-16 10:06:13,530 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5081 states and 7426 transitions. [2021-12-16 10:06:13,535 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:06:13,536 INFO L681 BuchiCegarLoop]: Abstraction has 5081 states and 7426 transitions. [2021-12-16 10:06:13,539 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5081 states and 7426 transitions. [2021-12-16 10:06:13,572 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5081 to 3555. [2021-12-16 10:06:13,576 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3555 states, 3555 states have (on average 1.4646976090014066) internal successors, (5207), 3554 states have internal predecessors, (5207), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:13,582 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3555 states to 3555 states and 5207 transitions. [2021-12-16 10:06:13,582 INFO L704 BuchiCegarLoop]: Abstraction has 3555 states and 5207 transitions. [2021-12-16 10:06:13,582 INFO L587 BuchiCegarLoop]: Abstraction has 3555 states and 5207 transitions. [2021-12-16 10:06:13,582 INFO L425 BuchiCegarLoop]: ======== Iteration 17============ [2021-12-16 10:06:13,582 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3555 states and 5207 transitions. [2021-12-16 10:06:13,588 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3382 [2021-12-16 10:06:13,589 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:06:13,589 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:06:13,590 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:13,590 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:13,591 INFO L791 eck$LassoCheckResult]: Stem: 73608#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 73609#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 73427#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 73141#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 73142#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 74327#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 74328#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 73278#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 73279#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 73735#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 73570#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 73571#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 73345#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 73346#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 73746#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 73926#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 74078#L936-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 74115#L941-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 73356#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 73357#L1258 assume !(0 == ~M_E~0); 74549#L1258-2 assume !(0 == ~T1_E~0); 73653#L1263-1 assume !(0 == ~T2_E~0); 73654#L1268-1 assume !(0 == ~T3_E~0); 73960#L1273-1 assume !(0 == ~T4_E~0); 74530#L1278-1 assume !(0 == ~T5_E~0); 74384#L1283-1 assume !(0 == ~T6_E~0); 74385#L1288-1 assume !(0 == ~T7_E~0); 74629#L1293-1 assume !(0 == ~T8_E~0); 74617#L1298-1 assume !(0 == ~T9_E~0); 74543#L1303-1 assume !(0 == ~T10_E~0); 73170#L1308-1 assume !(0 == ~T11_E~0); 73112#L1313-1 assume !(0 == ~T12_E~0); 73113#L1318-1 assume !(0 == ~T13_E~0); 73119#L1323-1 assume !(0 == ~E_1~0); 73120#L1328-1 assume !(0 == ~E_2~0); 73288#L1333-1 assume !(0 == ~E_3~0); 74253#L1338-1 assume !(0 == ~E_4~0); 74254#L1343-1 assume !(0 == ~E_5~0); 74357#L1348-1 assume !(0 == ~E_6~0); 74654#L1353-1 assume !(0 == ~E_7~0); 73979#L1358-1 assume !(0 == ~E_8~0); 73980#L1363-1 assume !(0 == ~E_9~0); 74271#L1368-1 assume !(0 == ~E_10~0); 72949#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 72950#L1378-1 assume !(0 == ~E_12~0); 73237#L1383-1 assume !(0 == ~E_13~0); 73238#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 73985#L607 assume !(1 == ~m_pc~0); 73307#L607-2 is_master_triggered_~__retres1~0#1 := 0; 73308#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 74355#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 73904#L1560 assume !(0 != activate_threads_~tmp~1#1); 73905#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 73132#L626 assume !(1 == ~t1_pc~0); 73133#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 73403#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 73404#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 73574#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 73032#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 73033#L645 assume 1 == ~t2_pc~0; 73149#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 73106#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 73786#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 73787#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 73880#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 73881#L664 assume 1 == ~t3_pc~0; 74652#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 72874#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 72875#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 73535#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 73536#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 74559#L683 assume !(1 == ~t4_pc~0); 74100#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 74052#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 74053#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 74087#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 74213#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 73829#L702 assume 1 == ~t5_pc~0; 73830#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 73755#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 74208#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 74515#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 74453#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 72921#L721 assume !(1 == ~t6_pc~0); 72896#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 72897#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 73059#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 73544#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 73545#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 74148#L740 assume 1 == ~t7_pc~0; 72970#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 72784#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 72785#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 72774#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 72775#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 73480#L759 assume !(1 == ~t8_pc~0); 73481#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 73510#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 74206#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 74207#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 74341#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 74628#L778 assume 1 == ~t9_pc~0; 74512#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 72948#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 72889#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 72818#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 72819#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 73145#L797 assume !(1 == ~t10_pc~0); 73146#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 73265#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 74409#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 73651#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 73652#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 73944#L816 assume 1 == ~t11_pc~0; 72854#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 72855#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 73612#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 73551#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 73552#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 74077#L835 assume 1 == ~t12_pc~0; 73957#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 73017#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 73039#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 73180#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 73708#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 73709#L854 assume !(1 == ~t13_pc~0); 73347#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 73348#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 73399#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 73057#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 73058#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 74448#L1401 assume !(1 == ~M_E~0); 73539#L1401-2 assume !(1 == ~T1_E~0); 73540#L1406-1 assume !(1 == ~T2_E~0); 74137#L1411-1 assume !(1 == ~T3_E~0); 74138#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 73802#L1421-1 assume !(1 == ~T5_E~0); 73343#L1426-1 assume !(1 == ~T6_E~0); 73344#L1431-1 assume !(1 == ~T7_E~0); 72892#L1436-1 assume !(1 == ~T8_E~0); 72893#L1441-1 assume !(1 == ~T9_E~0); 73642#L1446-1 assume !(1 == ~T10_E~0); 73643#L1451-1 assume !(1 == ~T11_E~0); 74354#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 74003#L1461-1 assume !(1 == ~T13_E~0); 73563#L1466-1 assume !(1 == ~E_1~0); 73564#L1471-1 assume !(1 == ~E_2~0); 74339#L1476-1 assume !(1 == ~E_3~0); 74340#L1481-1 assume !(1 == ~E_4~0); 74494#L1486-1 assume !(1 == ~E_5~0); 73185#L1491-1 assume !(1 == ~E_6~0); 72826#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 72827#L1501-1 assume !(1 == ~E_8~0); 73640#L1506-1 assume !(1 == ~E_9~0); 73641#L1511-1 assume !(1 == ~E_10~0); 73597#L1516-1 assume !(1 == ~E_11~0); 72770#L1521-1 assume !(1 == ~E_12~0); 72771#L1526-1 assume !(1 == ~E_13~0); 72825#L1531-1 assume { :end_inline_reset_delta_events } true; 73368#L1892-2 [2021-12-16 10:06:13,591 INFO L793 eck$LassoCheckResult]: Loop: 73368#L1892-2 assume !false; 74400#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 74606#L1233 assume !false; 74589#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 73907#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 73887#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 74045#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 72868#L1046 assume !(0 != eval_~tmp~0#1); 72870#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 72904#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 74079#L1258-3 assume !(0 == ~M_E~0); 74651#L1258-5 assume !(0 == ~T1_E~0); 73045#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 73046#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 74642#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 74649#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 74650#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 73270#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 73271#L1293-3 assume !(0 == ~T8_E~0); 74397#L1298-3 assume !(0 == ~T9_E~0); 74398#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 74565#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 74396#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 73891#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 73047#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 73048#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 74486#L1333-3 assume !(0 == ~E_3~0); 73190#L1338-3 assume !(0 == ~E_4~0); 73191#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 74312#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 74491#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 74492#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 73846#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 73405#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 73406#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 74167#L1378-3 assume !(0 == ~E_12~0); 74168#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 74351#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 74352#L607-42 assume !(1 == ~m_pc~0); 73963#L607-44 is_master_triggered_~__retres1~0#1 := 0; 73687#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 73688#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 73419#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 73420#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 73945#L626-42 assume 1 == ~t1_pc~0; 73504#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 73505#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 73809#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 73810#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 73081#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 73082#L645-42 assume !(1 == ~t2_pc~0); 74289#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 74290#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 74461#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 73289#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 72796#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 72797#L664-42 assume 1 == ~t3_pc~0; 73601#L665-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 73324#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 74592#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 74113#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 74114#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 76149#L683-42 assume !(1 == ~t4_pc~0); 76147#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 76146#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 76145#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 76144#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 76143#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 76142#L702-42 assume !(1 == ~t5_pc~0); 76141#L702-44 is_transmit5_triggered_~__retres1~5#1 := 0; 76139#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 76138#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 76137#L1600-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 76136#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 76135#L721-42 assume !(1 == ~t6_pc~0); 76133#L721-44 is_transmit6_triggered_~__retres1~6#1 := 0; 76132#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 76131#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 76130#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 76129#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 76128#L740-42 assume !(1 == ~t7_pc~0); 76127#L740-44 is_transmit7_triggered_~__retres1~7#1 := 0; 76125#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 76124#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 76123#L1616-42 assume !(0 != activate_threads_~tmp___6~0#1); 76122#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 76121#L759-42 assume 1 == ~t8_pc~0; 76119#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 76118#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 76117#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 76116#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 76115#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 74403#L778-42 assume 1 == ~t9_pc~0; 73671#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 73673#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 74084#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 73990#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 73991#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 74047#L797-42 assume 1 == ~t10_pc~0; 73211#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 73212#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 74218#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 74538#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 74085#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 74086#L816-42 assume 1 == ~t11_pc~0; 72760#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 72761#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 73303#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 73304#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 73384#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 73385#L835-42 assume !(1 == ~t12_pc~0); 73682#L835-44 is_transmit12_triggered_~__retres1~12#1 := 0; 73683#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 73358#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 73359#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 74452#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 74230#L854-42 assume !(1 == ~t13_pc~0); 73301#L854-44 is_transmit13_triggered_~__retres1~13#1 := 0; 73302#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 72912#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 72913#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 73561#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 73562#L1401-3 assume !(1 == ~M_E~0); 74346#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 73148#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 73012#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 73013#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 73615#L1421-3 assume !(1 == ~T5_E~0); 73616#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 73188#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 73189#L1436-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 72776#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 72777#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 74375#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 73699#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 73350#L1461-3 assume !(1 == ~T13_E~0); 73351#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 74645#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 73290#L1476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 73291#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 73693#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 73318#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 73319#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 73733#L1501-3 assume !(1 == ~E_8~0); 73734#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 74164#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 74154#L1516-3 assume 1 == ~E_11~0;~E_11~0 := 2; 74155#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 73850#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 73851#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 74249#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 73124#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 74021#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 73661#L1911 assume !(0 == start_simulation_~tmp~3#1); 73662#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 74187#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 73249#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 74123#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 72953#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 72954#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 73183#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 73184#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 73368#L1892-2 [2021-12-16 10:06:13,591 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:13,592 INFO L85 PathProgramCache]: Analyzing trace with hash -250357577, now seen corresponding path program 1 times [2021-12-16 10:06:13,592 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:13,592 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [620007793] [2021-12-16 10:06:13,592 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:13,592 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:13,599 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:06:13,617 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:06:13,617 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:06:13,617 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [620007793] [2021-12-16 10:06:13,618 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [620007793] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:06:13,618 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:06:13,618 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:06:13,618 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [755559219] [2021-12-16 10:06:13,618 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:06:13,618 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:06:13,619 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:13,619 INFO L85 PathProgramCache]: Analyzing trace with hash -1063219277, now seen corresponding path program 1 times [2021-12-16 10:06:13,619 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:13,619 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1324207820] [2021-12-16 10:06:13,619 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:13,619 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:13,627 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:06:13,643 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:06:13,644 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:06:13,644 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1324207820] [2021-12-16 10:06:13,644 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1324207820] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:06:13,644 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:06:13,644 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:06:13,644 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [574086686] [2021-12-16 10:06:13,644 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:06:13,645 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:06:13,645 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:06:13,645 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-16 10:06:13,645 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-16 10:06:13,646 INFO L87 Difference]: Start difference. First operand 3555 states and 5207 transitions. cyclomatic complexity: 1653 Second operand has 4 states, 4 states have (on average 39.75) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:13,797 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:06:13,798 INFO L93 Difference]: Finished difference Result 5073 states and 7406 transitions. [2021-12-16 10:06:13,798 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-16 10:06:13,798 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5073 states and 7406 transitions. [2021-12-16 10:06:13,815 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4896 [2021-12-16 10:06:13,827 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5073 states to 5073 states and 7406 transitions. [2021-12-16 10:06:13,827 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5073 [2021-12-16 10:06:13,831 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5073 [2021-12-16 10:06:13,832 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5073 states and 7406 transitions. [2021-12-16 10:06:13,837 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:06:13,837 INFO L681 BuchiCegarLoop]: Abstraction has 5073 states and 7406 transitions. [2021-12-16 10:06:13,841 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5073 states and 7406 transitions. [2021-12-16 10:06:13,875 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5073 to 3555. [2021-12-16 10:06:13,879 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3555 states, 3555 states have (on average 1.4638537271448664) internal successors, (5204), 3554 states have internal predecessors, (5204), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:13,885 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3555 states to 3555 states and 5204 transitions. [2021-12-16 10:06:13,886 INFO L704 BuchiCegarLoop]: Abstraction has 3555 states and 5204 transitions. [2021-12-16 10:06:13,886 INFO L587 BuchiCegarLoop]: Abstraction has 3555 states and 5204 transitions. [2021-12-16 10:06:13,886 INFO L425 BuchiCegarLoop]: ======== Iteration 18============ [2021-12-16 10:06:13,886 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3555 states and 5204 transitions. [2021-12-16 10:06:13,893 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3382 [2021-12-16 10:06:13,893 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:06:13,893 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:06:13,895 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:13,895 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:13,895 INFO L791 eck$LassoCheckResult]: Stem: 82245#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 82246#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 82065#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 81779#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 81780#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 82965#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 82966#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 81916#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 81917#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 82372#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 82207#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 82208#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 81983#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 81984#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 82383#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 82563#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 82715#L936-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 82752#L941-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 81994#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 81995#L1258 assume !(0 == ~M_E~0); 83191#L1258-2 assume !(0 == ~T1_E~0); 82290#L1263-1 assume !(0 == ~T2_E~0); 82291#L1268-1 assume !(0 == ~T3_E~0); 82597#L1273-1 assume !(0 == ~T4_E~0); 83173#L1278-1 assume !(0 == ~T5_E~0); 83026#L1283-1 assume !(0 == ~T6_E~0); 83027#L1288-1 assume !(0 == ~T7_E~0); 83277#L1293-1 assume !(0 == ~T8_E~0); 83264#L1298-1 assume !(0 == ~T9_E~0); 83185#L1303-1 assume !(0 == ~T10_E~0); 81808#L1308-1 assume !(0 == ~T11_E~0); 81750#L1313-1 assume !(0 == ~T12_E~0); 81751#L1318-1 assume !(0 == ~T13_E~0); 81757#L1323-1 assume !(0 == ~E_1~0); 81758#L1328-1 assume !(0 == ~E_2~0); 81926#L1333-1 assume !(0 == ~E_3~0); 82891#L1338-1 assume !(0 == ~E_4~0); 82892#L1343-1 assume !(0 == ~E_5~0); 82998#L1348-1 assume !(0 == ~E_6~0); 83301#L1353-1 assume !(0 == ~E_7~0); 82616#L1358-1 assume !(0 == ~E_8~0); 82617#L1363-1 assume !(0 == ~E_9~0); 82909#L1368-1 assume !(0 == ~E_10~0); 81587#L1373-1 assume !(0 == ~E_11~0); 81588#L1378-1 assume !(0 == ~E_12~0); 81875#L1383-1 assume !(0 == ~E_13~0); 81876#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 82622#L607 assume !(1 == ~m_pc~0); 81945#L607-2 is_master_triggered_~__retres1~0#1 := 0; 81946#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 82996#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 82543#L1560 assume !(0 != activate_threads_~tmp~1#1); 82544#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 81770#L626 assume !(1 == ~t1_pc~0); 81771#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 82041#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 82042#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 82211#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 81670#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 81671#L645 assume 1 == ~t2_pc~0; 81787#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 81744#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 82423#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 82424#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 82519#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 82520#L664 assume 1 == ~t3_pc~0; 83300#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 81512#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 81513#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 82172#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 82173#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 83201#L683 assume !(1 == ~t4_pc~0); 82737#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 82689#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 82690#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 82724#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 82851#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 82468#L702 assume 1 == ~t5_pc~0; 82469#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 82392#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 82846#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 83159#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 83096#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 81559#L721 assume !(1 == ~t6_pc~0); 81534#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 81535#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 81697#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 82181#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 82182#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 82785#L740 assume 1 == ~t7_pc~0; 81608#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 81422#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 81423#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 81412#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 81413#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 82117#L759 assume !(1 == ~t8_pc~0); 82118#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 82147#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 82844#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 82845#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 82979#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 83276#L778 assume 1 == ~t9_pc~0; 83156#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 81586#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 81527#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 81456#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 81457#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 81783#L797 assume !(1 == ~t10_pc~0); 81784#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 81903#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 83052#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 82288#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 82289#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 82581#L816 assume 1 == ~t11_pc~0; 81492#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 81493#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 82249#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 82188#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 82189#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 82714#L835 assume 1 == ~t12_pc~0; 82594#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 81655#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 81677#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 81818#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 82345#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 82346#L854 assume !(1 == ~t13_pc~0); 81985#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 81986#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 82037#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 81695#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 81696#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 83091#L1401 assume !(1 == ~M_E~0); 82176#L1401-2 assume !(1 == ~T1_E~0); 82177#L1406-1 assume !(1 == ~T2_E~0); 82774#L1411-1 assume !(1 == ~T3_E~0); 82775#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 82441#L1421-1 assume !(1 == ~T5_E~0); 81981#L1426-1 assume !(1 == ~T6_E~0); 81982#L1431-1 assume !(1 == ~T7_E~0); 81530#L1436-1 assume !(1 == ~T8_E~0); 81531#L1441-1 assume !(1 == ~T9_E~0); 82279#L1446-1 assume !(1 == ~T10_E~0); 82280#L1451-1 assume !(1 == ~T11_E~0); 82995#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 82641#L1461-1 assume !(1 == ~T13_E~0); 82200#L1466-1 assume !(1 == ~E_1~0); 82201#L1471-1 assume !(1 == ~E_2~0); 82977#L1476-1 assume !(1 == ~E_3~0); 82978#L1481-1 assume !(1 == ~E_4~0); 83137#L1486-1 assume !(1 == ~E_5~0); 81823#L1491-1 assume !(1 == ~E_6~0); 81464#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 81465#L1501-1 assume !(1 == ~E_8~0); 82277#L1506-1 assume !(1 == ~E_9~0); 82278#L1511-1 assume !(1 == ~E_10~0); 82234#L1516-1 assume !(1 == ~E_11~0); 81408#L1521-1 assume !(1 == ~E_12~0); 81409#L1526-1 assume !(1 == ~E_13~0); 81463#L1531-1 assume { :end_inline_reset_delta_events } true; 82006#L1892-2 [2021-12-16 10:06:13,896 INFO L793 eck$LassoCheckResult]: Loop: 82006#L1892-2 assume !false; 83044#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 83251#L1233 assume !false; 83232#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 82546#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 82526#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 82682#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 81506#L1046 assume !(0 != eval_~tmp~0#1); 81508#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 81542#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 82716#L1258-3 assume !(0 == ~M_E~0); 83299#L1258-5 assume !(0 == ~T1_E~0); 81683#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 81684#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 83291#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 83297#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 83298#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 81908#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 81909#L1293-3 assume !(0 == ~T8_E~0); 83041#L1298-3 assume !(0 == ~T9_E~0); 83042#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 83208#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 83040#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 82530#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 81685#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 81686#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 83128#L1333-3 assume !(0 == ~E_3~0); 81828#L1338-3 assume !(0 == ~E_4~0); 81829#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 82950#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 83133#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 83134#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 82485#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 82043#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 82044#L1373-3 assume !(0 == ~E_11~0); 82804#L1378-3 assume !(0 == ~E_12~0); 82805#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 82991#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 82992#L607-42 assume !(1 == ~m_pc~0); 82600#L607-44 is_master_triggered_~__retres1~0#1 := 0; 82324#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 82325#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 82057#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 82058#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 82582#L626-42 assume 1 == ~t1_pc~0; 82141#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 82142#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 82448#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 82449#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 81719#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 81720#L645-42 assume 1 == ~t2_pc~0; 83200#L646-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 82927#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 83103#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 81927#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 81434#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 81435#L664-42 assume !(1 == ~t3_pc~0); 81961#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 81962#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 83235#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 82750#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 82751#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 82920#L683-42 assume !(1 == ~t4_pc~0); 82625#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 82626#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 82757#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 83196#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 83197#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 83033#L702-42 assume 1 == ~t5_pc~0; 82512#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 82134#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 82432#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 83120#L1600-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 81450#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 81451#L721-42 assume 1 == ~t6_pc~0; 81603#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 81623#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 82089#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 83283#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 82261#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 82107#L740-42 assume !(1 == ~t7_pc~0); 81843#L740-44 is_transmit7_triggered_~__retres1~7#1 := 0; 81844#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 82386#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 82241#L1616-42 assume !(0 != activate_threads_~tmp___6~0#1); 82242#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 82518#L759-42 assume !(1 == ~t8_pc~0); 82365#L759-44 is_transmit8_triggered_~__retres1~8#1 := 0; 82296#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 82297#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 82375#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 82376#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 82473#L778-42 assume !(1 == ~t9_pc~0); 82309#L778-44 is_transmit9_triggered_~__retres1~9#1 := 0; 82310#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 82721#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 82627#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 82628#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 82684#L797-42 assume 1 == ~t10_pc~0; 81849#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 81850#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 82856#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 83181#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 82722#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 82723#L816-42 assume 1 == ~t11_pc~0; 81398#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 81399#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 81941#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 81942#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 82022#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 82023#L835-42 assume 1 == ~t12_pc~0; 82429#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 82320#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 81996#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 81997#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 83095#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 82869#L854-42 assume !(1 == ~t13_pc~0); 81939#L854-44 is_transmit13_triggered_~__retres1~13#1 := 0; 81940#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 81550#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 81551#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 82198#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 82199#L1401-3 assume !(1 == ~M_E~0); 82984#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 81786#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 81650#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 81651#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 82252#L1421-3 assume !(1 == ~T5_E~0); 82253#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 81826#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 81827#L1436-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 81414#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 81415#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 84790#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 84789#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 84788#L1461-3 assume !(1 == ~T13_E~0); 84787#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 84786#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 84785#L1476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 84784#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 82330#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 81956#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 81957#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 82370#L1501-3 assume !(1 == ~E_8~0); 82371#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 82801#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 82790#L1516-3 assume 1 == ~E_11~0;~E_11~0 := 2; 82791#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 82489#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 82490#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 82887#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 81762#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 82658#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 82298#L1911 assume !(0 == start_simulation_~tmp~3#1); 82299#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 82824#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 81887#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 82760#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 81591#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 81592#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 81821#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 81822#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 82006#L1892-2 [2021-12-16 10:06:13,896 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:13,896 INFO L85 PathProgramCache]: Analyzing trace with hash -583000715, now seen corresponding path program 1 times [2021-12-16 10:06:13,896 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:13,896 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [733040944] [2021-12-16 10:06:13,897 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:13,897 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:13,904 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:06:13,921 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:06:13,921 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:06:13,921 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [733040944] [2021-12-16 10:06:13,921 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [733040944] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:06:13,921 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:06:13,921 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:06:13,922 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1382725731] [2021-12-16 10:06:13,922 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:06:13,922 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:06:13,922 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:13,922 INFO L85 PathProgramCache]: Analyzing trace with hash -2117041390, now seen corresponding path program 1 times [2021-12-16 10:06:13,923 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:13,923 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [824631331] [2021-12-16 10:06:13,923 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:13,923 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:13,931 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:06:13,946 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:06:13,947 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:06:13,947 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [824631331] [2021-12-16 10:06:13,947 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [824631331] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:06:13,947 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:06:13,947 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:06:13,947 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2110230613] [2021-12-16 10:06:13,947 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:06:13,948 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:06:13,948 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:06:13,948 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-16 10:06:13,948 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-16 10:06:13,948 INFO L87 Difference]: Start difference. First operand 3555 states and 5204 transitions. cyclomatic complexity: 1650 Second operand has 4 states, 4 states have (on average 39.75) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:14,219 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:06:14,220 INFO L93 Difference]: Finished difference Result 9800 states and 14218 transitions. [2021-12-16 10:06:14,220 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-16 10:06:14,220 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9800 states and 14218 transitions. [2021-12-16 10:06:14,255 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 9613 [2021-12-16 10:06:14,275 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9800 states to 9800 states and 14218 transitions. [2021-12-16 10:06:14,276 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9800 [2021-12-16 10:06:14,281 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9800 [2021-12-16 10:06:14,281 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9800 states and 14218 transitions. [2021-12-16 10:06:14,289 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:06:14,289 INFO L681 BuchiCegarLoop]: Abstraction has 9800 states and 14218 transitions. [2021-12-16 10:06:14,292 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9800 states and 14218 transitions. [2021-12-16 10:06:14,358 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9800 to 9618. [2021-12-16 10:06:14,368 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 9618 states, 9618 states have (on average 1.4520690372218756) internal successors, (13966), 9617 states have internal predecessors, (13966), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:14,382 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9618 states to 9618 states and 13966 transitions. [2021-12-16 10:06:14,382 INFO L704 BuchiCegarLoop]: Abstraction has 9618 states and 13966 transitions. [2021-12-16 10:06:14,382 INFO L587 BuchiCegarLoop]: Abstraction has 9618 states and 13966 transitions. [2021-12-16 10:06:14,382 INFO L425 BuchiCegarLoop]: ======== Iteration 19============ [2021-12-16 10:06:14,382 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 9618 states and 13966 transitions. [2021-12-16 10:06:14,402 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 9443 [2021-12-16 10:06:14,402 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:06:14,402 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:06:14,403 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:14,403 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:14,404 INFO L791 eck$LassoCheckResult]: Stem: 95611#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 95612#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 95431#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 95143#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 95144#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 96369#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 96370#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 95280#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 95281#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 95740#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 95574#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 95575#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 95347#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 95348#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 95751#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 95934#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 96094#L936-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 96134#L941-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 95360#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 95361#L1258 assume !(0 == ~M_E~0); 96611#L1258-2 assume !(0 == ~T1_E~0); 95656#L1263-1 assume !(0 == ~T2_E~0); 95657#L1268-1 assume !(0 == ~T3_E~0); 95970#L1273-1 assume !(0 == ~T4_E~0); 96591#L1278-1 assume !(0 == ~T5_E~0); 96428#L1283-1 assume !(0 == ~T6_E~0); 96429#L1288-1 assume !(0 == ~T7_E~0); 96720#L1293-1 assume !(0 == ~T8_E~0); 96703#L1298-1 assume !(0 == ~T9_E~0); 96605#L1303-1 assume !(0 == ~T10_E~0); 95172#L1308-1 assume !(0 == ~T11_E~0); 95115#L1313-1 assume !(0 == ~T12_E~0); 95116#L1318-1 assume !(0 == ~T13_E~0); 95122#L1323-1 assume !(0 == ~E_1~0); 95123#L1328-1 assume !(0 == ~E_2~0); 95290#L1333-1 assume !(0 == ~E_3~0); 96281#L1338-1 assume !(0 == ~E_4~0); 96282#L1343-1 assume !(0 == ~E_5~0); 96402#L1348-1 assume !(0 == ~E_6~0); 96755#L1353-1 assume !(0 == ~E_7~0); 95991#L1358-1 assume !(0 == ~E_8~0); 95992#L1363-1 assume !(0 == ~E_9~0); 96307#L1368-1 assume !(0 == ~E_10~0); 94953#L1373-1 assume !(0 == ~E_11~0); 94954#L1378-1 assume !(0 == ~E_12~0); 95239#L1383-1 assume !(0 == ~E_13~0); 95240#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 95998#L607 assume !(1 == ~m_pc~0); 95309#L607-2 is_master_triggered_~__retres1~0#1 := 0; 95310#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 96398#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 95911#L1560 assume !(0 != activate_threads_~tmp~1#1); 95912#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 95135#L626 assume !(1 == ~t1_pc~0); 95136#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 95407#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 95408#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 95578#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 95035#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 95036#L645 assume !(1 == ~t2_pc~0); 95108#L645-2 is_transmit2_triggered_~__retres1~2#1 := 0; 95109#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 95793#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 95794#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 95887#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 95888#L664 assume 1 == ~t3_pc~0; 96753#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 94877#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 94878#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 95540#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 95541#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 96628#L683 assume !(1 == ~t4_pc~0); 96118#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 96067#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 96068#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 96104#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 96237#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 95836#L702 assume 1 == ~t5_pc~0; 95837#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 95760#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 96232#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 96575#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 96507#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 94925#L721 assume !(1 == ~t6_pc~0); 94899#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 94900#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 95062#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 95549#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 95550#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 96171#L740 assume 1 == ~t7_pc~0; 94974#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 94787#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 94788#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 94777#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 94778#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 95483#L759 assume !(1 == ~t8_pc~0); 95484#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 95512#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 96230#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 96231#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 96382#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 96719#L778 assume 1 == ~t9_pc~0; 96573#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 94952#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 94892#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 94821#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 94822#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 95147#L797 assume !(1 == ~t10_pc~0); 95148#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 95267#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 96456#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 95654#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 95655#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 95954#L816 assume 1 == ~t11_pc~0; 94857#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 94858#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 95615#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 95556#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 95557#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 96093#L835 assume 1 == ~t12_pc~0; 95967#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 95020#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 95042#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 95182#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 95712#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 95713#L854 assume !(1 == ~t13_pc~0); 95349#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 95350#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 95403#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 95060#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 95061#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 96502#L1401 assume !(1 == ~M_E~0); 95544#L1401-2 assume !(1 == ~T1_E~0); 95545#L1406-1 assume !(1 == ~T2_E~0); 96160#L1411-1 assume !(1 == ~T3_E~0); 96161#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 95809#L1421-1 assume !(1 == ~T5_E~0); 95345#L1426-1 assume !(1 == ~T6_E~0); 95346#L1431-1 assume !(1 == ~T7_E~0); 94895#L1436-1 assume !(1 == ~T8_E~0); 94896#L1441-1 assume !(1 == ~T9_E~0); 95645#L1446-1 assume !(1 == ~T10_E~0); 95646#L1451-1 assume !(1 == ~T11_E~0); 96397#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 96016#L1461-1 assume !(1 == ~T13_E~0); 95568#L1466-1 assume !(1 == ~E_1~0); 95569#L1471-1 assume !(1 == ~E_2~0); 96380#L1476-1 assume !(1 == ~E_3~0); 96381#L1481-1 assume !(1 == ~E_4~0); 96552#L1486-1 assume !(1 == ~E_5~0); 95187#L1491-1 assume !(1 == ~E_6~0); 94829#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 94830#L1501-1 assume !(1 == ~E_8~0); 95643#L1506-1 assume !(1 == ~E_9~0); 95644#L1511-1 assume !(1 == ~E_10~0); 95600#L1516-1 assume !(1 == ~E_11~0); 94773#L1521-1 assume !(1 == ~E_12~0); 94774#L1526-1 assume !(1 == ~E_13~0); 94828#L1531-1 assume { :end_inline_reset_delta_events } true; 95372#L1892-2 [2021-12-16 10:06:14,404 INFO L793 eck$LassoCheckResult]: Loop: 95372#L1892-2 assume !false; 103206#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 103205#L1233 assume !false; 103201#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 102927#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 102925#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 102923#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 102921#L1046 assume !(0 != eval_~tmp~0#1); 94907#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 94908#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 96095#L1258-3 assume !(0 == ~M_E~0); 96752#L1258-5 assume !(0 == ~T1_E~0); 95048#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 95049#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 96740#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 103818#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 103817#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 103816#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 103815#L1293-3 assume !(0 == ~T8_E~0); 103814#L1298-3 assume !(0 == ~T9_E~0); 103813#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 103812#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 103811#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 103810#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 103809#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 103808#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 96759#L1333-3 assume !(0 == ~E_3~0); 95192#L1338-3 assume !(0 == ~E_4~0); 95193#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 96350#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 96549#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 96550#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 95853#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 95409#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 95410#L1373-3 assume !(0 == ~E_11~0); 96189#L1378-3 assume !(0 == ~E_12~0); 96190#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 96394#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 96395#L607-42 assume !(1 == ~m_pc~0); 95974#L607-44 is_master_triggered_~__retres1~0#1 := 0; 95691#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 95692#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 95423#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 95424#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 95955#L626-42 assume !(1 == ~t1_pc~0); 95529#L626-44 is_transmit1_triggered_~__retres1~1#1 := 0; 95530#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 95816#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 95817#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 95084#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 95085#L645-42 assume !(1 == ~t2_pc~0); 96327#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 96328#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 96516#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 95291#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 94799#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 94800#L664-42 assume 1 == ~t3_pc~0; 95604#L665-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 95326#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 96672#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 96132#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 96133#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 96318#L683-42 assume !(1 == ~t4_pc~0); 96001#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 96002#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 96140#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 96619#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 96620#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 96438#L702-42 assume 1 == ~t5_pc~0; 95878#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 95500#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 95800#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 96535#L1600-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 94815#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 94816#L721-42 assume 1 == ~t6_pc~0; 94969#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 94988#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 95454#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 96731#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 95627#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 95473#L740-42 assume 1 == ~t7_pc~0; 95474#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 95208#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 95754#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 95607#L1616-42 assume !(0 != activate_threads_~tmp___6~0#1); 95608#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 95886#L759-42 assume 1 == ~t8_pc~0; 95731#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 95662#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 95663#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 95741#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 95742#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 95841#L778-42 assume 1 == ~t9_pc~0; 95675#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 95677#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 96101#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 96003#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 96004#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 96060#L797-42 assume 1 == ~t10_pc~0; 95213#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 95214#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 96242#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 96599#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 96102#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 96103#L816-42 assume 1 == ~t11_pc~0; 94763#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 94764#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 95305#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 95306#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 95388#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 95389#L835-42 assume 1 == ~t12_pc~0; 95797#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 95687#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 95362#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 95363#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 96506#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 96257#L854-42 assume 1 == ~t13_pc~0; 96258#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 95304#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 94916#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 94917#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 95566#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 95567#L1401-3 assume !(1 == ~M_E~0); 96803#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 103619#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 103617#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 103615#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 103613#L1421-3 assume !(1 == ~T5_E~0); 103611#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 103609#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 103607#L1436-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 103605#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 103603#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 103601#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 103598#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 103596#L1461-3 assume !(1 == ~T13_E~0); 103594#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 103592#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 103590#L1476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 103588#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 103585#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 103583#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 103581#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 103579#L1501-3 assume !(1 == ~E_8~0); 103577#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 103575#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 103572#L1516-3 assume 1 == ~E_11~0;~E_11~0 := 2; 103570#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 103568#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 103566#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 103282#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 103276#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 103274#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 103272#L1911 assume !(0 == start_simulation_~tmp~3#1); 103268#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 103266#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 103242#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 103233#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 103221#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 103220#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 103219#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 103217#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 95372#L1892-2 [2021-12-16 10:06:14,404 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:14,405 INFO L85 PathProgramCache]: Analyzing trace with hash -1586057580, now seen corresponding path program 1 times [2021-12-16 10:06:14,405 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:14,405 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1319442908] [2021-12-16 10:06:14,405 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:14,405 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:14,414 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:06:14,431 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:06:14,431 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:06:14,431 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1319442908] [2021-12-16 10:06:14,431 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1319442908] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:06:14,431 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:06:14,431 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:06:14,431 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1338206369] [2021-12-16 10:06:14,432 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:06:14,432 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:06:14,433 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:14,434 INFO L85 PathProgramCache]: Analyzing trace with hash -6033803, now seen corresponding path program 1 times [2021-12-16 10:06:14,434 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:14,434 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1688881880] [2021-12-16 10:06:14,434 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:14,434 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:14,442 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:06:14,459 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:06:14,459 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:06:14,459 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1688881880] [2021-12-16 10:06:14,459 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1688881880] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:06:14,460 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:06:14,460 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:06:14,460 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [515596147] [2021-12-16 10:06:14,460 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:06:14,461 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:06:14,461 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:06:14,461 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-16 10:06:14,461 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-16 10:06:14,461 INFO L87 Difference]: Start difference. First operand 9618 states and 13966 transitions. cyclomatic complexity: 4350 Second operand has 4 states, 4 states have (on average 39.75) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:14,694 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:06:14,694 INFO L93 Difference]: Finished difference Result 27171 states and 39183 transitions. [2021-12-16 10:06:14,695 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-16 10:06:14,696 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 27171 states and 39183 transitions. [2021-12-16 10:06:14,937 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 26949 [2021-12-16 10:06:14,999 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 27171 states to 27171 states and 39183 transitions. [2021-12-16 10:06:14,999 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 27171 [2021-12-16 10:06:15,019 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 27171 [2021-12-16 10:06:15,020 INFO L73 IsDeterministic]: Start isDeterministic. Operand 27171 states and 39183 transitions. [2021-12-16 10:06:15,040 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:06:15,040 INFO L681 BuchiCegarLoop]: Abstraction has 27171 states and 39183 transitions. [2021-12-16 10:06:15,054 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 27171 states and 39183 transitions. [2021-12-16 10:06:15,306 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 27171 to 26663. [2021-12-16 10:06:15,335 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 26663 states, 26663 states have (on average 1.4431609346285115) internal successors, (38479), 26662 states have internal predecessors, (38479), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:15,465 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 26663 states to 26663 states and 38479 transitions. [2021-12-16 10:06:15,465 INFO L704 BuchiCegarLoop]: Abstraction has 26663 states and 38479 transitions. [2021-12-16 10:06:15,465 INFO L587 BuchiCegarLoop]: Abstraction has 26663 states and 38479 transitions. [2021-12-16 10:06:15,465 INFO L425 BuchiCegarLoop]: ======== Iteration 20============ [2021-12-16 10:06:15,465 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 26663 states and 38479 transitions. [2021-12-16 10:06:15,539 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 26481 [2021-12-16 10:06:15,539 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:06:15,539 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:06:15,541 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:15,541 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:15,541 INFO L791 eck$LassoCheckResult]: Stem: 132413#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 132414#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 132228#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 131941#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 131942#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 133179#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 133180#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 132077#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 132078#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 132544#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 132375#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 132376#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 132144#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 132145#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 132556#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 132736#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 132898#L936-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 132937#L941-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 132159#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 132160#L1258 assume !(0 == ~M_E~0); 133438#L1258-2 assume !(0 == ~T1_E~0); 132458#L1263-1 assume !(0 == ~T2_E~0); 132459#L1268-1 assume !(0 == ~T3_E~0); 132772#L1273-1 assume !(0 == ~T4_E~0); 133417#L1278-1 assume !(0 == ~T5_E~0); 133243#L1283-1 assume !(0 == ~T6_E~0); 133244#L1288-1 assume !(0 == ~T7_E~0); 133559#L1293-1 assume !(0 == ~T8_E~0); 133541#L1298-1 assume !(0 == ~T9_E~0); 133431#L1303-1 assume !(0 == ~T10_E~0); 131969#L1308-1 assume !(0 == ~T11_E~0); 131913#L1313-1 assume !(0 == ~T12_E~0); 131914#L1318-1 assume !(0 == ~T13_E~0); 131920#L1323-1 assume !(0 == ~E_1~0); 131921#L1328-1 assume !(0 == ~E_2~0); 132087#L1333-1 assume !(0 == ~E_3~0); 133088#L1338-1 assume !(0 == ~E_4~0); 133089#L1343-1 assume !(0 == ~E_5~0); 133214#L1348-1 assume !(0 == ~E_6~0); 133600#L1353-1 assume !(0 == ~E_7~0); 132791#L1358-1 assume !(0 == ~E_8~0); 132792#L1363-1 assume !(0 == ~E_9~0); 133116#L1368-1 assume !(0 == ~E_10~0); 131751#L1373-1 assume !(0 == ~E_11~0); 131752#L1378-1 assume !(0 == ~E_12~0); 132036#L1383-1 assume !(0 == ~E_13~0); 132037#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 132799#L607 assume !(1 == ~m_pc~0); 132106#L607-2 is_master_triggered_~__retres1~0#1 := 0; 132107#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 133208#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 132715#L1560 assume !(0 != activate_threads_~tmp~1#1); 132716#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 131933#L626 assume !(1 == ~t1_pc~0); 131934#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 132204#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 132205#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 132379#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 131833#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 131834#L645 assume !(1 == ~t2_pc~0); 131906#L645-2 is_transmit2_triggered_~__retres1~2#1 := 0; 131907#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 132597#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 132598#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 132691#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 132692#L664 assume !(1 == ~t3_pc~0); 133140#L664-2 is_transmit3_triggered_~__retres1~3#1 := 0; 131675#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 131676#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 132341#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 132342#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 133457#L683 assume !(1 == ~t4_pc~0); 132922#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 132871#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 132872#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 132907#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 133041#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 132640#L702 assume 1 == ~t5_pc~0; 132641#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 132565#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 133036#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 133399#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 133326#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 131723#L721 assume !(1 == ~t6_pc~0); 131697#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 131698#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 131860#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 132350#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 132351#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 132975#L740 assume 1 == ~t7_pc~0; 131772#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 131586#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 131587#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 131576#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 131577#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 132283#L759 assume !(1 == ~t8_pc~0); 132284#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 132312#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 133034#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 133035#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 133193#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 133558#L778 assume 1 == ~t9_pc~0; 133397#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 131750#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 131690#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 131619#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 131620#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 131946#L797 assume !(1 == ~t10_pc~0); 131947#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 132064#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 133269#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 132456#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 132457#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 132756#L816 assume 1 == ~t11_pc~0; 131655#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 131656#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 132417#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 132357#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 132358#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 132897#L835 assume 1 == ~t12_pc~0; 132769#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 131818#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 131840#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 131980#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 132516#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 132517#L854 assume !(1 == ~t13_pc~0); 132146#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 132147#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 132200#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 131858#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 131859#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 133318#L1401 assume !(1 == ~M_E~0); 132345#L1401-2 assume !(1 == ~T1_E~0); 132346#L1406-1 assume !(1 == ~T2_E~0); 132965#L1411-1 assume !(1 == ~T3_E~0); 132966#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 132612#L1421-1 assume !(1 == ~T5_E~0); 132142#L1426-1 assume !(1 == ~T6_E~0); 132143#L1431-1 assume !(1 == ~T7_E~0); 131693#L1436-1 assume !(1 == ~T8_E~0); 131694#L1441-1 assume !(1 == ~T9_E~0); 132447#L1446-1 assume !(1 == ~T10_E~0); 132448#L1451-1 assume !(1 == ~T11_E~0); 133207#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 132818#L1461-1 assume !(1 == ~T13_E~0); 132369#L1466-1 assume !(1 == ~E_1~0); 132370#L1471-1 assume !(1 == ~E_2~0); 133191#L1476-1 assume !(1 == ~E_3~0); 133192#L1481-1 assume !(1 == ~E_4~0); 133377#L1486-1 assume !(1 == ~E_5~0); 131985#L1491-1 assume !(1 == ~E_6~0); 131627#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 131628#L1501-1 assume !(1 == ~E_8~0); 132445#L1506-1 assume !(1 == ~E_9~0); 132446#L1511-1 assume !(1 == ~E_10~0); 132401#L1516-1 assume !(1 == ~E_11~0); 131572#L1521-1 assume !(1 == ~E_12~0); 131573#L1526-1 assume !(1 == ~E_13~0); 131626#L1531-1 assume { :end_inline_reset_delta_events } true; 132169#L1892-2 [2021-12-16 10:06:15,541 INFO L793 eck$LassoCheckResult]: Loop: 132169#L1892-2 assume !false; 154770#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 154768#L1233 assume !false; 133496#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 132718#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 132698#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 133629#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 153768#L1046 assume !(0 != eval_~tmp~0#1); 131705#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 131706#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 132899#L1258-3 assume !(0 == ~M_E~0); 133597#L1258-5 assume !(0 == ~T1_E~0); 131846#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 131847#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 133584#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 133595#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 133596#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 132069#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 132070#L1293-3 assume !(0 == ~T8_E~0); 133257#L1298-3 assume !(0 == ~T9_E~0); 133258#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 133464#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 133256#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 132702#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 131848#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 131849#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 133369#L1333-3 assume !(0 == ~E_3~0); 131990#L1338-3 assume !(0 == ~E_4~0); 131991#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 133160#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 133374#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 133375#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 132657#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 132206#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 132207#L1373-3 assume !(0 == ~E_11~0); 132993#L1378-3 assume !(0 == ~E_12~0); 132994#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 133204#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 133205#L607-42 assume !(1 == ~m_pc~0); 132775#L607-44 is_master_triggered_~__retres1~0#1 := 0; 132494#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 132495#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 132220#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 132221#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 132757#L626-42 assume !(1 == ~t1_pc~0); 132330#L626-44 is_transmit1_triggered_~__retres1~1#1 := 0; 132331#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 132619#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 132620#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 131882#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 131883#L645-42 assume !(1 == ~t2_pc~0); 133136#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 133137#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 133337#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 132088#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 131598#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 131599#L664-42 assume !(1 == ~t3_pc~0); 132122#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 132123#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 133501#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 132935#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 132936#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 133127#L683-42 assume !(1 == ~t4_pc~0); 132802#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 132803#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 132944#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 133447#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 133448#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 157458#L702-42 assume 1 == ~t5_pc~0; 157456#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 157455#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 157454#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 157453#L1600-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 157452#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 157451#L721-42 assume !(1 == ~t6_pc~0); 157448#L721-44 is_transmit6_triggered_~__retres1~6#1 := 0; 157447#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 157446#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 157445#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 157444#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 157443#L740-42 assume !(1 == ~t7_pc~0); 157442#L740-44 is_transmit7_triggered_~__retres1~7#1 := 0; 157440#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 157439#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 157438#L1616-42 assume !(0 != activate_threads_~tmp___6~0#1); 157437#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 157436#L759-42 assume 1 == ~t8_pc~0; 157434#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 157407#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 157406#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 132545#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 132546#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 132645#L778-42 assume !(1 == ~t9_pc~0); 132478#L778-44 is_transmit9_triggered_~__retres1~9#1 := 0; 132479#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 132904#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 132804#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 132805#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 132864#L797-42 assume 1 == ~t10_pc~0; 132010#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 132011#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 133048#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 133425#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 132905#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 132906#L816-42 assume 1 == ~t11_pc~0; 131562#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 131563#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 132102#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 132103#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 132185#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 132186#L835-42 assume !(1 == ~t12_pc~0); 132483#L835-44 is_transmit12_triggered_~__retres1~12#1 := 0; 132484#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 132157#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 132158#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 133325#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 133062#L854-42 assume 1 == ~t13_pc~0; 133063#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 156978#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 155524#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 155522#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 155520#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 155518#L1401-3 assume !(1 == ~M_E~0); 155514#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 155512#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 155510#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 155508#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 155506#L1421-3 assume !(1 == ~T5_E~0); 155504#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 155502#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 155500#L1436-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 155498#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 155496#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 155494#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 155492#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 155490#L1461-3 assume !(1 == ~T13_E~0); 155488#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 155486#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 155484#L1476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 155482#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 155480#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 155478#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 155476#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 155474#L1501-3 assume !(1 == ~E_8~0); 155472#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 155471#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 155470#L1516-3 assume 1 == ~E_11~0;~E_11~0 := 2; 155469#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 155466#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 155464#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 155264#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 155258#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 155256#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 155244#L1911 assume !(0 == start_simulation_~tmp~3#1); 155235#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 155162#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 155144#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 155137#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 155132#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 155129#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 155125#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 155121#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 132169#L1892-2 [2021-12-16 10:06:15,541 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:15,542 INFO L85 PathProgramCache]: Analyzing trace with hash -1313062157, now seen corresponding path program 1 times [2021-12-16 10:06:15,542 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:15,542 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2119319930] [2021-12-16 10:06:15,542 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:15,542 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:15,550 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:06:15,572 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:06:15,572 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:06:15,572 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2119319930] [2021-12-16 10:06:15,572 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2119319930] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:06:15,572 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:06:15,572 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-16 10:06:15,572 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1800205641] [2021-12-16 10:06:15,572 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:06:15,573 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:06:15,573 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:15,573 INFO L85 PathProgramCache]: Analyzing trace with hash -262157488, now seen corresponding path program 1 times [2021-12-16 10:06:15,573 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:15,573 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [811510328] [2021-12-16 10:06:15,573 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:15,573 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:15,581 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:06:15,596 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:06:15,596 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:06:15,596 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [811510328] [2021-12-16 10:06:15,597 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [811510328] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:06:15,597 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:06:15,597 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:06:15,597 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2085580929] [2021-12-16 10:06:15,597 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:06:15,597 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:06:15,597 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:06:15,597 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-16 10:06:15,597 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-16 10:06:15,598 INFO L87 Difference]: Start difference. First operand 26663 states and 38479 transitions. cyclomatic complexity: 11820 Second operand has 5 states, 5 states have (on average 31.8) internal successors, (159), 5 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:16,030 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:06:16,030 INFO L93 Difference]: Finished difference Result 71848 states and 104075 transitions. [2021-12-16 10:06:16,031 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-16 10:06:16,031 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 71848 states and 104075 transitions. [2021-12-16 10:06:16,525 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 71455 [2021-12-16 10:06:16,826 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 71848 states to 71848 states and 104075 transitions. [2021-12-16 10:06:16,827 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 71848 [2021-12-16 10:06:16,858 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 71848 [2021-12-16 10:06:16,859 INFO L73 IsDeterministic]: Start isDeterministic. Operand 71848 states and 104075 transitions. [2021-12-16 10:06:16,906 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:06:16,906 INFO L681 BuchiCegarLoop]: Abstraction has 71848 states and 104075 transitions. [2021-12-16 10:06:16,934 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 71848 states and 104075 transitions. [2021-12-16 10:06:17,249 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 71848 to 27347. [2021-12-16 10:06:17,277 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 27347 states, 27347 states have (on average 1.432076644604527) internal successors, (39163), 27346 states have internal predecessors, (39163), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:17,317 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 27347 states to 27347 states and 39163 transitions. [2021-12-16 10:06:17,317 INFO L704 BuchiCegarLoop]: Abstraction has 27347 states and 39163 transitions. [2021-12-16 10:06:17,317 INFO L587 BuchiCegarLoop]: Abstraction has 27347 states and 39163 transitions. [2021-12-16 10:06:17,317 INFO L425 BuchiCegarLoop]: ======== Iteration 21============ [2021-12-16 10:06:17,317 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 27347 states and 39163 transitions. [2021-12-16 10:06:17,390 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 27162 [2021-12-16 10:06:17,391 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:06:17,391 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:06:17,392 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:17,392 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:17,392 INFO L791 eck$LassoCheckResult]: Stem: 230938#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 230939#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 230756#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 230464#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 230465#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 231739#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 231740#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 230604#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 230605#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 231074#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 230899#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 230900#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 230671#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 230672#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 231085#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 231277#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 231449#L936-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 231491#L941-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 230684#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 230685#L1258 assume !(0 == ~M_E~0); 232036#L1258-2 assume !(0 == ~T1_E~0); 230983#L1263-1 assume !(0 == ~T2_E~0); 230984#L1268-1 assume !(0 == ~T3_E~0); 231316#L1273-1 assume !(0 == ~T4_E~0); 232013#L1278-1 assume !(0 == ~T5_E~0); 231808#L1283-1 assume !(0 == ~T6_E~0); 231809#L1288-1 assume !(0 == ~T7_E~0); 232162#L1293-1 assume !(0 == ~T8_E~0); 232145#L1298-1 assume !(0 == ~T9_E~0); 232026#L1303-1 assume !(0 == ~T10_E~0); 230492#L1308-1 assume !(0 == ~T11_E~0); 230436#L1313-1 assume !(0 == ~T12_E~0); 230437#L1318-1 assume !(0 == ~T13_E~0); 230443#L1323-1 assume !(0 == ~E_1~0); 230444#L1328-1 assume !(0 == ~E_2~0); 230614#L1333-1 assume !(0 == ~E_3~0); 231646#L1338-1 assume !(0 == ~E_4~0); 231647#L1343-1 assume !(0 == ~E_5~0); 231779#L1348-1 assume !(0 == ~E_6~0); 232206#L1353-1 assume !(0 == ~E_7~0); 231335#L1358-1 assume !(0 == ~E_8~0); 231336#L1363-1 assume !(0 == ~E_9~0); 231674#L1368-1 assume !(0 == ~E_10~0); 230274#L1373-1 assume !(0 == ~E_11~0); 230275#L1378-1 assume !(0 == ~E_12~0); 230560#L1383-1 assume !(0 == ~E_13~0); 230561#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 231343#L607 assume !(1 == ~m_pc~0); 230633#L607-2 is_master_triggered_~__retres1~0#1 := 0; 230634#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 231774#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 231254#L1560 assume !(0 != activate_threads_~tmp~1#1); 231255#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 230456#L626 assume !(1 == ~t1_pc~0); 230457#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 230732#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 230733#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 230903#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 230356#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 230357#L645 assume !(1 == ~t2_pc~0); 230429#L645-2 is_transmit2_triggered_~__retres1~2#1 := 0; 230430#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 231127#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 231128#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 231229#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 231230#L664 assume !(1 == ~t3_pc~0); 231700#L664-2 is_transmit3_triggered_~__retres1~3#1 := 0; 230199#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 230200#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 230864#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 230865#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 232053#L683 assume !(1 == ~t4_pc~0); 231475#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 231423#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 231424#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 232220#L1592 assume !(0 != activate_threads_~tmp___3~0#1); 231597#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 231174#L702 assume 1 == ~t5_pc~0; 231175#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 231094#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 231592#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 231994#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 231910#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 230246#L721 assume !(1 == ~t6_pc~0); 230221#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 230222#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 230383#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 230873#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 230874#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 231529#L740 assume 1 == ~t7_pc~0; 230295#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 230110#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 230111#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 230100#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 230101#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 230807#L759 assume !(1 == ~t8_pc~0); 230808#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 230836#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 231590#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 231591#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 231754#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 232161#L778 assume 1 == ~t9_pc~0; 231991#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 230273#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 230214#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 230143#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 230144#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 230468#L797 assume !(1 == ~t10_pc~0); 230469#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 230591#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 231835#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 230981#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 230982#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 231298#L816 assume 1 == ~t11_pc~0; 230179#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 230180#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 230942#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 230880#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 230881#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 231448#L835 assume 1 == ~t12_pc~0; 231312#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 230341#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 230363#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 230503#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 231044#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 231045#L854 assume !(1 == ~t13_pc~0); 230673#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 230674#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 230727#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 230381#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 230382#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 231900#L1401 assume !(1 == ~M_E~0); 230868#L1401-2 assume !(1 == ~T1_E~0); 230869#L1406-1 assume !(1 == ~T2_E~0); 231519#L1411-1 assume !(1 == ~T3_E~0); 231520#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 231143#L1421-1 assume !(1 == ~T5_E~0); 230669#L1426-1 assume !(1 == ~T6_E~0); 230670#L1431-1 assume !(1 == ~T7_E~0); 230217#L1436-1 assume !(1 == ~T8_E~0); 230218#L1441-1 assume !(1 == ~T9_E~0); 230972#L1446-1 assume !(1 == ~T10_E~0); 230973#L1451-1 assume !(1 == ~T11_E~0); 231773#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 231365#L1461-1 assume !(1 == ~T13_E~0); 230893#L1466-1 assume !(1 == ~E_1~0); 230894#L1471-1 assume !(1 == ~E_2~0); 231752#L1476-1 assume !(1 == ~E_3~0); 231753#L1481-1 assume !(1 == ~E_4~0); 231967#L1486-1 assume !(1 == ~E_5~0); 230508#L1491-1 assume !(1 == ~E_6~0); 230151#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 230152#L1501-1 assume !(1 == ~E_8~0); 230970#L1506-1 assume !(1 == ~E_9~0); 230971#L1511-1 assume !(1 == ~E_10~0); 230926#L1516-1 assume !(1 == ~E_11~0); 230096#L1521-1 assume !(1 == ~E_12~0); 230097#L1526-1 assume !(1 == ~E_13~0); 230150#L1531-1 assume { :end_inline_reset_delta_events } true; 230696#L1892-2 [2021-12-16 10:06:17,393 INFO L793 eck$LassoCheckResult]: Loop: 230696#L1892-2 assume !false; 250725#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 250724#L1233 assume !false; 250723#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 250642#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 250624#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 250616#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 250611#L1046 assume !(0 != eval_~tmp~0#1); 250612#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 252336#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 252333#L1258-3 assume !(0 == ~M_E~0); 252331#L1258-5 assume !(0 == ~T1_E~0); 251605#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 251603#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 251601#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 251598#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 251596#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 251594#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 251484#L1293-3 assume !(0 == ~T8_E~0); 251481#L1298-3 assume !(0 == ~T9_E~0); 251479#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 251477#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 251475#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 251473#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 251471#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 251468#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 251466#L1333-3 assume !(0 == ~E_3~0); 251464#L1338-3 assume !(0 == ~E_4~0); 251462#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 251460#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 251458#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 251455#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 251453#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 251451#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 251449#L1373-3 assume !(0 == ~E_11~0); 251447#L1378-3 assume !(0 == ~E_12~0); 251445#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 251442#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 251441#L607-42 assume !(1 == ~m_pc~0); 251439#L607-44 is_master_triggered_~__retres1~0#1 := 0; 251438#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 251437#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 251436#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 251435#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 251434#L626-42 assume !(1 == ~t1_pc~0); 251433#L626-44 is_transmit1_triggered_~__retres1~1#1 := 0; 251432#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 251431#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 251430#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 251429#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 251428#L645-42 assume !(1 == ~t2_pc~0); 251427#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 251426#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 251425#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 251424#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 251423#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 251422#L664-42 assume !(1 == ~t3_pc~0); 251421#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 251420#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 251419#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 251418#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 251417#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 251416#L683-42 assume !(1 == ~t4_pc~0); 251415#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 251413#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 251411#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 251409#L1592-42 assume !(0 != activate_threads_~tmp___3~0#1); 251407#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 251406#L702-42 assume 1 == ~t5_pc~0; 251403#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 251401#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 251399#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 251397#L1600-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 251395#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 251393#L721-42 assume 1 == ~t6_pc~0; 251391#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 251388#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 251386#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 251384#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 251382#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 251380#L740-42 assume !(1 == ~t7_pc~0); 251378#L740-44 is_transmit7_triggered_~__retres1~7#1 := 0; 251375#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 251373#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 251371#L1616-42 assume !(0 != activate_threads_~tmp___6~0#1); 251369#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 251367#L759-42 assume !(1 == ~t8_pc~0); 251365#L759-44 is_transmit8_triggered_~__retres1~8#1 := 0; 251362#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 250976#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 250974#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 250972#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 250969#L778-42 assume 1 == ~t9_pc~0; 250967#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 250964#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 250962#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 250960#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 250958#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 250955#L797-42 assume !(1 == ~t10_pc~0); 250953#L797-44 is_transmit10_triggered_~__retres1~10#1 := 0; 250950#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 250948#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 250946#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 250944#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 250941#L816-42 assume 1 == ~t11_pc~0; 250939#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 250936#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 250934#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 250932#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 250930#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 250927#L835-42 assume !(1 == ~t12_pc~0); 250925#L835-44 is_transmit12_triggered_~__retres1~12#1 := 0; 250922#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 250920#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 250918#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 250916#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 250915#L854-42 assume 1 == ~t13_pc~0; 250912#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 250909#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 250907#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 250905#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 250903#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 250901#L1401-3 assume !(1 == ~M_E~0); 250898#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 250895#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 250893#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 250891#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 250889#L1421-3 assume !(1 == ~T5_E~0); 250887#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 250885#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 250882#L1436-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 250880#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 250878#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 250876#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 250821#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 250810#L1461-3 assume !(1 == ~T13_E~0); 250802#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 250795#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 250789#L1476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 250786#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 250785#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 250784#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 250783#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 250782#L1501-3 assume !(1 == ~E_8~0); 250781#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 250780#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 250779#L1516-3 assume 1 == ~E_11~0;~E_11~0 := 2; 250778#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 250777#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 250776#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 250765#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 250759#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 250757#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 250755#L1911 assume !(0 == start_simulation_~tmp~3#1); 250753#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 250752#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 250738#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 250737#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 250736#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 250735#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 250734#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 250732#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 230696#L1892-2 [2021-12-16 10:06:17,393 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:17,393 INFO L85 PathProgramCache]: Analyzing trace with hash 1102774193, now seen corresponding path program 1 times [2021-12-16 10:06:17,393 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:17,393 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1259506608] [2021-12-16 10:06:17,393 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:17,393 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:17,402 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:06:17,422 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:06:17,422 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:06:17,422 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1259506608] [2021-12-16 10:06:17,422 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1259506608] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:06:17,422 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:06:17,422 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:06:17,422 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [605324367] [2021-12-16 10:06:17,422 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:06:17,423 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:06:17,423 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:17,423 INFO L85 PathProgramCache]: Analyzing trace with hash 1651164366, now seen corresponding path program 1 times [2021-12-16 10:06:17,423 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:17,423 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1164389325] [2021-12-16 10:06:17,423 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:17,423 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:17,433 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:06:17,448 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:06:17,448 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:06:17,448 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1164389325] [2021-12-16 10:06:17,448 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1164389325] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:06:17,448 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:06:17,448 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:06:17,448 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1173581559] [2021-12-16 10:06:17,448 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:06:17,448 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:06:17,449 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:06:17,449 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-16 10:06:17,449 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-16 10:06:17,449 INFO L87 Difference]: Start difference. First operand 27347 states and 39163 transitions. cyclomatic complexity: 11820 Second operand has 4 states, 4 states have (on average 39.75) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:17,966 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:06:17,966 INFO L93 Difference]: Finished difference Result 77808 states and 110810 transitions. [2021-12-16 10:06:17,966 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-16 10:06:17,967 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 77808 states and 110810 transitions. [2021-12-16 10:06:18,463 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 77496 [2021-12-16 10:06:18,808 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 77808 states to 77808 states and 110810 transitions. [2021-12-16 10:06:18,809 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 77808 [2021-12-16 10:06:18,850 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 77808 [2021-12-16 10:06:18,851 INFO L73 IsDeterministic]: Start isDeterministic. Operand 77808 states and 110810 transitions. [2021-12-16 10:06:18,915 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:06:18,915 INFO L681 BuchiCegarLoop]: Abstraction has 77808 states and 110810 transitions. [2021-12-16 10:06:18,954 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 77808 states and 110810 transitions. [2021-12-16 10:06:19,563 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 77808 to 76544. [2021-12-16 10:06:19,626 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 76544 states, 76544 states have (on average 1.4248798076923077) internal successors, (109066), 76543 states have internal predecessors, (109066), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:19,755 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 76544 states to 76544 states and 109066 transitions. [2021-12-16 10:06:19,755 INFO L704 BuchiCegarLoop]: Abstraction has 76544 states and 109066 transitions. [2021-12-16 10:06:19,755 INFO L587 BuchiCegarLoop]: Abstraction has 76544 states and 109066 transitions. [2021-12-16 10:06:19,755 INFO L425 BuchiCegarLoop]: ======== Iteration 22============ [2021-12-16 10:06:19,755 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 76544 states and 109066 transitions. [2021-12-16 10:06:19,992 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 76344 [2021-12-16 10:06:19,992 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:06:19,992 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:06:19,994 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:19,994 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:19,994 INFO L791 eck$LassoCheckResult]: Stem: 336102#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 336103#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 335915#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 335630#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 335631#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 336933#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 336934#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 335766#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 335767#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 336247#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 336061#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 336062#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 335834#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 335835#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 336254#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 336455#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 336629#L936-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 336671#L941-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 335847#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 335848#L1258 assume !(0 == ~M_E~0); 337235#L1258-2 assume !(0 == ~T1_E~0); 336154#L1263-1 assume !(0 == ~T2_E~0); 336155#L1268-1 assume !(0 == ~T3_E~0); 336495#L1273-1 assume !(0 == ~T4_E~0); 337210#L1278-1 assume !(0 == ~T5_E~0); 337006#L1283-1 assume !(0 == ~T6_E~0); 337007#L1288-1 assume !(0 == ~T7_E~0); 337355#L1293-1 assume !(0 == ~T8_E~0); 337334#L1298-1 assume !(0 == ~T9_E~0); 337228#L1303-1 assume !(0 == ~T10_E~0); 335658#L1308-1 assume !(0 == ~T11_E~0); 335605#L1313-1 assume !(0 == ~T12_E~0); 335606#L1318-1 assume !(0 == ~T13_E~0); 335611#L1323-1 assume !(0 == ~E_1~0); 335612#L1328-1 assume !(0 == ~E_2~0); 335776#L1333-1 assume !(0 == ~E_3~0); 336831#L1338-1 assume !(0 == ~E_4~0); 336832#L1343-1 assume !(0 == ~E_5~0); 336973#L1348-1 assume !(0 == ~E_6~0); 337409#L1353-1 assume !(0 == ~E_7~0); 336516#L1358-1 assume !(0 == ~E_8~0); 336517#L1363-1 assume !(0 == ~E_9~0); 336860#L1368-1 assume !(0 == ~E_10~0); 335438#L1373-1 assume !(0 == ~E_11~0); 335439#L1378-1 assume !(0 == ~E_12~0); 335727#L1383-1 assume !(0 == ~E_13~0); 335728#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 336524#L607 assume !(1 == ~m_pc~0); 335795#L607-2 is_master_triggered_~__retres1~0#1 := 0; 335796#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 336968#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 336430#L1560 assume !(0 != activate_threads_~tmp~1#1); 336431#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 335622#L626 assume !(1 == ~t1_pc~0); 335623#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 335893#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 335894#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 336067#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 335525#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 335526#L645 assume !(1 == ~t2_pc~0); 335595#L645-2 is_transmit2_triggered_~__retres1~2#1 := 0; 335596#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 336303#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 336304#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 336403#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 336404#L664 assume !(1 == ~t3_pc~0); 336891#L664-2 is_transmit3_triggered_~__retres1~3#1 := 0; 335366#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 335367#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 336027#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 336028#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 337251#L683 assume !(1 == ~t4_pc~0); 336655#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 336600#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 336601#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 337425#L1592 assume !(0 != activate_threads_~tmp___3~0#1); 336779#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 336351#L702 assume !(1 == ~t5_pc~0); 336266#L702-2 is_transmit5_triggered_~__retres1~5#1 := 0; 336267#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 336774#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 337191#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 337100#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 335410#L721 assume !(1 == ~t6_pc~0); 335384#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 335385#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 335549#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 336036#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 336037#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 336708#L740 assume 1 == ~t7_pc~0; 335459#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 335275#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 335276#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 335265#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 335266#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 335969#L759 assume !(1 == ~t8_pc~0); 335970#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 336000#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 336772#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 336773#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 336948#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 337353#L778 assume 1 == ~t9_pc~0; 337189#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 335437#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 335377#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 335306#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 335307#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 335636#L797 assume !(1 == ~t10_pc~0); 335637#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 335753#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 337040#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 336152#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 336153#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 336477#L816 assume 1 == ~t11_pc~0; 335342#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 335343#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 336108#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 336043#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 336044#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 336626#L835 assume 1 == ~t12_pc~0; 336492#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 335507#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 335529#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 335669#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 336212#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 336213#L854 assume !(1 == ~t13_pc~0); 335836#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 335837#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 335888#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 335547#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 335548#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 337093#L1401 assume !(1 == ~M_E~0); 336031#L1401-2 assume !(1 == ~T1_E~0); 336032#L1406-1 assume !(1 == ~T2_E~0); 336698#L1411-1 assume !(1 == ~T3_E~0); 336699#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 336317#L1421-1 assume !(1 == ~T5_E~0); 335832#L1426-1 assume !(1 == ~T6_E~0); 335833#L1431-1 assume !(1 == ~T7_E~0); 335380#L1436-1 assume !(1 == ~T8_E~0); 335381#L1441-1 assume !(1 == ~T9_E~0); 336143#L1446-1 assume !(1 == ~T10_E~0); 336144#L1451-1 assume !(1 == ~T11_E~0); 336967#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 336545#L1461-1 assume !(1 == ~T13_E~0); 336055#L1466-1 assume !(1 == ~E_1~0); 336056#L1471-1 assume !(1 == ~E_2~0); 336946#L1476-1 assume !(1 == ~E_3~0); 336947#L1481-1 assume !(1 == ~E_4~0); 337165#L1486-1 assume !(1 == ~E_5~0); 335676#L1491-1 assume !(1 == ~E_6~0); 335314#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 335315#L1501-1 assume !(1 == ~E_8~0); 336137#L1506-1 assume !(1 == ~E_9~0); 336138#L1511-1 assume !(1 == ~E_10~0); 336089#L1516-1 assume !(1 == ~E_11~0); 335263#L1521-1 assume !(1 == ~E_12~0); 335264#L1526-1 assume !(1 == ~E_13~0); 335313#L1531-1 assume { :end_inline_reset_delta_events } true; 335858#L1892-2 [2021-12-16 10:06:19,995 INFO L793 eck$LassoCheckResult]: Loop: 335858#L1892-2 assume !false; 406446#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 406445#L1233 assume !false; 406444#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 406415#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 406414#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 406413#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 406411#L1046 assume !(0 != eval_~tmp~0#1); 406410#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 406409#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 406408#L1258-3 assume !(0 == ~M_E~0); 406407#L1258-5 assume !(0 == ~T1_E~0); 406406#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 406405#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 406404#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 406403#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 406402#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 406401#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 406400#L1293-3 assume !(0 == ~T8_E~0); 406399#L1298-3 assume !(0 == ~T9_E~0); 406398#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 406397#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 406396#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 406395#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 406394#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 406393#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 406392#L1333-3 assume !(0 == ~E_3~0); 406391#L1338-3 assume !(0 == ~E_4~0); 406390#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 406389#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 406388#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 406387#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 406386#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 406385#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 406384#L1373-3 assume !(0 == ~E_11~0); 406383#L1378-3 assume !(0 == ~E_12~0); 406382#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 406381#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 406380#L607-42 assume !(1 == ~m_pc~0); 406378#L607-44 is_master_triggered_~__retres1~0#1 := 0; 406377#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 406376#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 406375#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 406374#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 406373#L626-42 assume !(1 == ~t1_pc~0); 406372#L626-44 is_transmit1_triggered_~__retres1~1#1 := 0; 406371#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 406370#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 406369#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 406368#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 406367#L645-42 assume !(1 == ~t2_pc~0); 406366#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 406365#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 406364#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 406363#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 406362#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 406361#L664-42 assume !(1 == ~t3_pc~0); 406360#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 406359#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 406358#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 406357#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 406356#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 406353#L683-42 assume 1 == ~t4_pc~0; 406354#L684-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 406355#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 407613#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 406348#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 406347#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 406346#L702-42 assume !(1 == ~t5_pc~0); 406345#L702-44 is_transmit5_triggered_~__retres1~5#1 := 0; 406344#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 406343#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 406342#L1600-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 406341#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 406340#L721-42 assume !(1 == ~t6_pc~0); 406338#L721-44 is_transmit6_triggered_~__retres1~6#1 := 0; 406337#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 406336#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 406335#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 406334#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 406333#L740-42 assume !(1 == ~t7_pc~0); 406332#L740-44 is_transmit7_triggered_~__retres1~7#1 := 0; 406330#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 406329#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 406328#L1616-42 assume !(0 != activate_threads_~tmp___6~0#1); 406327#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 406326#L759-42 assume 1 == ~t8_pc~0; 406324#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 406323#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 406322#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 406321#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 406320#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 406319#L778-42 assume 1 == ~t9_pc~0; 406318#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 406316#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 406315#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 406314#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 406313#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 406312#L797-42 assume 1 == ~t10_pc~0; 406310#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 406309#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 406308#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 406307#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 406306#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 406305#L816-42 assume 1 == ~t11_pc~0; 406304#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 406302#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 406301#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 406300#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 406299#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 406298#L835-42 assume 1 == ~t12_pc~0; 406296#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 406295#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 406294#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 406293#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 406292#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 406291#L854-42 assume 1 == ~t13_pc~0; 406290#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 406288#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 406287#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 406286#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 406285#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 406284#L1401-3 assume !(1 == ~M_E~0); 405990#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 406283#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 406282#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 406281#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 406280#L1421-3 assume !(1 == ~T5_E~0); 406279#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 406278#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 406277#L1436-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 406276#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 406275#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 406274#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 406273#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 406272#L1461-3 assume !(1 == ~T13_E~0); 406271#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 406270#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 406269#L1476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 406268#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 406267#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 406266#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 406265#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 406264#L1501-3 assume !(1 == ~E_8~0); 406263#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 406262#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 406261#L1516-3 assume 1 == ~E_11~0;~E_11~0 := 2; 406260#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 406259#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 406258#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 406248#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 406243#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 406242#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 406240#L1911 assume !(0 == start_simulation_~tmp~3#1); 406241#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 407586#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 407572#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 407571#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 407570#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 407569#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 407568#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 407567#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 335858#L1892-2 [2021-12-16 10:06:19,995 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:19,995 INFO L85 PathProgramCache]: Analyzing trace with hash -882054512, now seen corresponding path program 1 times [2021-12-16 10:06:19,995 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:19,996 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1553580252] [2021-12-16 10:06:19,996 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:19,996 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:20,204 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:06:20,242 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:06:20,242 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:06:20,242 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1553580252] [2021-12-16 10:06:20,242 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1553580252] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:06:20,242 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:06:20,242 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:06:20,242 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1678693693] [2021-12-16 10:06:20,243 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:06:20,243 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:06:20,243 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:20,243 INFO L85 PathProgramCache]: Analyzing trace with hash 808706578, now seen corresponding path program 1 times [2021-12-16 10:06:20,243 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:20,243 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [250600910] [2021-12-16 10:06:20,244 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:20,244 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:20,251 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:06:20,266 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:06:20,266 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:06:20,266 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [250600910] [2021-12-16 10:06:20,267 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [250600910] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:06:20,267 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:06:20,267 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:06:20,267 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1983476441] [2021-12-16 10:06:20,267 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:06:20,267 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:06:20,268 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:06:20,268 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-16 10:06:20,268 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-16 10:06:20,268 INFO L87 Difference]: Start difference. First operand 76544 states and 109066 transitions. cyclomatic complexity: 32530 Second operand has 4 states, 4 states have (on average 39.75) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:21,322 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:06:21,322 INFO L93 Difference]: Finished difference Result 217973 states and 309105 transitions. [2021-12-16 10:06:21,322 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-16 10:06:21,323 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 217973 states and 309105 transitions. [2021-12-16 10:06:22,481 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 217438 [2021-12-16 10:06:23,177 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 217973 states to 217973 states and 309105 transitions. [2021-12-16 10:06:23,178 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 217973 [2021-12-16 10:06:23,273 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 217973 [2021-12-16 10:06:23,273 INFO L73 IsDeterministic]: Start isDeterministic. Operand 217973 states and 309105 transitions. [2021-12-16 10:06:23,375 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:06:23,375 INFO L681 BuchiCegarLoop]: Abstraction has 217973 states and 309105 transitions. [2021-12-16 10:06:23,467 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 217973 states and 309105 transitions. [2021-12-16 10:06:25,245 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 217973 to 214969. [2021-12-16 10:06:25,403 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 214969 states, 214969 states have (on average 1.4187766608208625) internal successors, (304993), 214968 states have internal predecessors, (304993), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:25,837 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 214969 states to 214969 states and 304993 transitions. [2021-12-16 10:06:25,837 INFO L704 BuchiCegarLoop]: Abstraction has 214969 states and 304993 transitions. [2021-12-16 10:06:25,837 INFO L587 BuchiCegarLoop]: Abstraction has 214969 states and 304993 transitions. [2021-12-16 10:06:25,838 INFO L425 BuchiCegarLoop]: ======== Iteration 23============ [2021-12-16 10:06:25,838 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 214969 states and 304993 transitions. [2021-12-16 10:06:26,828 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 214738 [2021-12-16 10:06:26,828 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:06:26,828 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:06:26,829 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:26,830 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:26,830 INFO L791 eck$LassoCheckResult]: Stem: 630626#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 630627#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 630440#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 630151#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 630152#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 631427#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 631428#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 630288#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 630289#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 630760#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 630589#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 630590#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 630356#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 630357#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 630767#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 630959#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 631129#L936-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 631170#L941-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 630369#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 630370#L1258 assume !(0 == ~M_E~0); 631741#L1258-2 assume !(0 == ~T1_E~0); 630671#L1263-1 assume !(0 == ~T2_E~0); 630672#L1268-1 assume !(0 == ~T3_E~0); 630998#L1273-1 assume !(0 == ~T4_E~0); 631713#L1278-1 assume !(0 == ~T5_E~0); 631509#L1283-1 assume !(0 == ~T6_E~0); 631510#L1288-1 assume !(0 == ~T7_E~0); 631868#L1293-1 assume !(0 == ~T8_E~0); 631841#L1298-1 assume !(0 == ~T9_E~0); 631730#L1303-1 assume !(0 == ~T10_E~0); 630178#L1308-1 assume !(0 == ~T11_E~0); 630126#L1313-1 assume !(0 == ~T12_E~0); 630127#L1318-1 assume !(0 == ~T13_E~0); 630132#L1323-1 assume !(0 == ~E_1~0); 630133#L1328-1 assume !(0 == ~E_2~0); 630299#L1333-1 assume !(0 == ~E_3~0); 631330#L1338-1 assume !(0 == ~E_4~0); 631331#L1343-1 assume !(0 == ~E_5~0); 631466#L1348-1 assume !(0 == ~E_6~0); 631918#L1353-1 assume !(0 == ~E_7~0); 631019#L1358-1 assume !(0 == ~E_8~0); 631020#L1363-1 assume !(0 == ~E_9~0); 631360#L1368-1 assume !(0 == ~E_10~0); 629964#L1373-1 assume !(0 == ~E_11~0); 629965#L1378-1 assume !(0 == ~E_12~0); 630246#L1383-1 assume !(0 == ~E_13~0); 630247#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 631027#L607 assume !(1 == ~m_pc~0); 630318#L607-2 is_master_triggered_~__retres1~0#1 := 0; 630319#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 631460#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 630934#L1560 assume !(0 != activate_threads_~tmp~1#1); 630935#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 630143#L626 assume !(1 == ~t1_pc~0); 630144#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 630417#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 630418#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 630595#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 630046#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 630047#L645 assume !(1 == ~t2_pc~0); 630116#L645-2 is_transmit2_triggered_~__retres1~2#1 := 0; 630117#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 630812#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 630813#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 630909#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 630910#L664 assume !(1 == ~t3_pc~0); 631385#L664-2 is_transmit3_triggered_~__retres1~3#1 := 0; 629893#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 629894#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 630553#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 630554#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 631757#L683 assume !(1 == ~t4_pc~0); 631154#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 631101#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 631102#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 631944#L1592 assume !(0 != activate_threads_~tmp___3~0#1); 631278#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 630858#L702 assume !(1 == ~t5_pc~0); 630776#L702-2 is_transmit5_triggered_~__retres1~5#1 := 0; 630777#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 631273#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 631694#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 631602#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 629937#L721 assume !(1 == ~t6_pc~0); 629911#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 629912#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 630070#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 630562#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 630563#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 631207#L740 assume !(1 == ~t7_pc~0); 631208#L740-2 is_transmit7_triggered_~__retres1~7#1 := 0; 629802#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 629803#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 629792#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 629793#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 630493#L759 assume !(1 == ~t8_pc~0); 630494#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 630523#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 631271#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 631272#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 631442#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 631865#L778 assume 1 == ~t9_pc~0; 631692#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 629963#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 629904#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 629833#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 629834#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 630156#L797 assume !(1 == ~t10_pc~0); 630157#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 630275#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 631541#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 630669#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 630670#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 630981#L816 assume 1 == ~t11_pc~0; 629869#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 629870#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 630632#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 630569#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 630570#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 631127#L835 assume 1 == ~t12_pc~0; 630995#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 630028#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 630050#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 630189#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 630728#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 630729#L854 assume !(1 == ~t13_pc~0); 630358#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 630359#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 630412#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 630068#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 630069#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 631594#L1401 assume !(1 == ~M_E~0); 630557#L1401-2 assume !(1 == ~T1_E~0); 630558#L1406-1 assume !(1 == ~T2_E~0); 631195#L1411-1 assume !(1 == ~T3_E~0); 631196#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 630825#L1421-1 assume !(1 == ~T5_E~0); 630354#L1426-1 assume !(1 == ~T6_E~0); 630355#L1431-1 assume !(1 == ~T7_E~0); 629907#L1436-1 assume !(1 == ~T8_E~0); 629908#L1441-1 assume !(1 == ~T9_E~0); 630662#L1446-1 assume !(1 == ~T10_E~0); 630663#L1451-1 assume !(1 == ~T11_E~0); 631459#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 631048#L1461-1 assume !(1 == ~T13_E~0); 630583#L1466-1 assume !(1 == ~E_1~0); 630584#L1471-1 assume !(1 == ~E_2~0); 631440#L1476-1 assume !(1 == ~E_3~0); 631441#L1481-1 assume !(1 == ~E_4~0); 631667#L1486-1 assume !(1 == ~E_5~0); 630196#L1491-1 assume !(1 == ~E_6~0); 629841#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 629842#L1501-1 assume !(1 == ~E_8~0); 630658#L1506-1 assume !(1 == ~E_9~0); 630659#L1511-1 assume !(1 == ~E_10~0); 630614#L1516-1 assume !(1 == ~E_11~0); 629790#L1521-1 assume !(1 == ~E_12~0); 629791#L1526-1 assume !(1 == ~E_13~0); 629840#L1531-1 assume { :end_inline_reset_delta_events } true; 630381#L1892-2 [2021-12-16 10:06:26,831 INFO L793 eck$LassoCheckResult]: Loop: 630381#L1892-2 assume !false; 789495#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 789493#L1233 assume !false; 789491#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 789443#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 789441#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 789440#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 789437#L1046 assume !(0 != eval_~tmp~0#1); 789438#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 790837#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 790835#L1258-3 assume !(0 == ~M_E~0); 790833#L1258-5 assume !(0 == ~T1_E~0); 790831#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 790828#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 790826#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 790824#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 790822#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 790820#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 790818#L1293-3 assume !(0 == ~T8_E~0); 790816#L1298-3 assume !(0 == ~T9_E~0); 790814#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 790812#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 790809#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 790807#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 790805#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 790803#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 790801#L1333-3 assume !(0 == ~E_3~0); 790799#L1338-3 assume !(0 == ~E_4~0); 790797#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 790795#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 790793#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 790791#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 790789#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 790787#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 790784#L1373-3 assume !(0 == ~E_11~0); 790782#L1378-3 assume !(0 == ~E_12~0); 790780#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 790778#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 790776#L607-42 assume !(1 == ~m_pc~0); 790773#L607-44 is_master_triggered_~__retres1~0#1 := 0; 790770#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 790768#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 790766#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 790764#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 790762#L626-42 assume !(1 == ~t1_pc~0); 790760#L626-44 is_transmit1_triggered_~__retres1~1#1 := 0; 790757#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 790755#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 790753#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 790751#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 790749#L645-42 assume !(1 == ~t2_pc~0); 790747#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 790744#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 790742#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 790740#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 790738#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 790736#L664-42 assume !(1 == ~t3_pc~0); 790734#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 790731#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 790729#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 790727#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 790725#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 790720#L683-42 assume !(1 == ~t4_pc~0); 790717#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 790714#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 790715#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 790709#L1592-42 assume !(0 != activate_threads_~tmp___3~0#1); 790706#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 790705#L702-42 assume !(1 == ~t5_pc~0); 790704#L702-44 is_transmit5_triggered_~__retres1~5#1 := 0; 790703#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 790702#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 790700#L1600-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 790699#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 790698#L721-42 assume !(1 == ~t6_pc~0); 790696#L721-44 is_transmit6_triggered_~__retres1~6#1 := 0; 790695#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 790694#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 790693#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 790692#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 790691#L740-42 assume !(1 == ~t7_pc~0); 790690#L740-44 is_transmit7_triggered_~__retres1~7#1 := 0; 790689#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 790688#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 790686#L1616-42 assume !(0 != activate_threads_~tmp___6~0#1); 790683#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 790681#L759-42 assume 1 == ~t8_pc~0; 790678#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 790676#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 790674#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 790672#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 790670#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 790668#L778-42 assume !(1 == ~t9_pc~0); 790665#L778-44 is_transmit9_triggered_~__retres1~9#1 := 0; 790663#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 790661#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 790659#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 790657#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 790655#L797-42 assume 1 == ~t10_pc~0; 790652#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 790650#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 790648#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 790646#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 790644#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 790642#L816-42 assume !(1 == ~t11_pc~0); 790639#L816-44 is_transmit11_triggered_~__retres1~11#1 := 0; 790637#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 790635#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 790633#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 790629#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 790627#L835-42 assume 1 == ~t12_pc~0; 790624#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 790622#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 790619#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 790617#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 790615#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 790613#L854-42 assume !(1 == ~t13_pc~0); 790610#L854-44 is_transmit13_triggered_~__retres1~13#1 := 0; 790608#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 790606#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 790604#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 790602#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 790599#L1401-3 assume !(1 == ~M_E~0); 790595#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 790593#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 790591#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 790589#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 790587#L1421-3 assume !(1 == ~T5_E~0); 790585#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 790583#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 790581#L1436-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 790579#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 790577#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 790575#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 790572#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 790570#L1461-3 assume !(1 == ~T13_E~0); 790568#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 790566#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 790564#L1476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 790562#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 790559#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 790557#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 790555#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 790553#L1501-3 assume !(1 == ~E_8~0); 790551#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 790549#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 790546#L1516-3 assume 1 == ~E_11~0;~E_11~0 := 2; 790544#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 790542#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 790539#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 790540#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 790503#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 790504#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 790496#L1911 assume !(0 == start_simulation_~tmp~3#1); 790497#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 790488#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 790473#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 790471#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 790470#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 790469#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 790468#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 790466#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 630381#L1892-2 [2021-12-16 10:06:26,832 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:26,832 INFO L85 PathProgramCache]: Analyzing trace with hash 24701935, now seen corresponding path program 1 times [2021-12-16 10:06:26,833 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:26,833 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [106362252] [2021-12-16 10:06:26,833 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:26,833 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:26,844 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:06:26,864 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:06:26,864 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:06:26,864 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [106362252] [2021-12-16 10:06:26,864 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [106362252] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:06:26,865 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:06:26,865 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:06:26,865 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1351150290] [2021-12-16 10:06:26,865 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:06:26,865 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:06:26,865 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:26,866 INFO L85 PathProgramCache]: Analyzing trace with hash 1500990092, now seen corresponding path program 1 times [2021-12-16 10:06:26,866 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:26,866 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [205843238] [2021-12-16 10:06:26,866 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:26,866 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:26,873 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:06:26,889 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:06:26,889 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:06:26,889 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [205843238] [2021-12-16 10:06:26,890 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [205843238] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:06:26,890 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:06:26,890 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:06:26,890 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1884347845] [2021-12-16 10:06:26,890 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:06:26,890 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:06:26,890 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:06:26,891 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-16 10:06:26,891 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-16 10:06:26,891 INFO L87 Difference]: Start difference. First operand 214969 states and 304993 transitions. cyclomatic complexity: 90040 Second operand has 4 states, 4 states have (on average 39.75) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:29,595 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:06:29,595 INFO L93 Difference]: Finished difference Result 610682 states and 862832 transitions. [2021-12-16 10:06:29,595 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-16 10:06:29,596 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 610682 states and 862832 transitions. [2021-12-16 10:06:32,473 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 609556 [2021-12-16 10:06:34,225 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 610682 states to 610682 states and 862832 transitions. [2021-12-16 10:06:34,226 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 610682 [2021-12-16 10:06:34,578 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 610682 [2021-12-16 10:06:34,590 INFO L73 IsDeterministic]: Start isDeterministic. Operand 610682 states and 862832 transitions. [2021-12-16 10:06:34,873 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:06:34,873 INFO L681 BuchiCegarLoop]: Abstraction has 610682 states and 862832 transitions. [2021-12-16 10:06:35,539 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 610682 states and 862832 transitions. [2021-12-16 10:06:40,705 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 610682 to 604018. [2021-12-16 10:06:41,309 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 604018 states, 604018 states have (on average 1.4136002569459851) internal successors, (853840), 604017 states have internal predecessors, (853840), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:42,859 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 604018 states to 604018 states and 853840 transitions. [2021-12-16 10:06:42,860 INFO L704 BuchiCegarLoop]: Abstraction has 604018 states and 853840 transitions. [2021-12-16 10:06:42,860 INFO L587 BuchiCegarLoop]: Abstraction has 604018 states and 853840 transitions. [2021-12-16 10:06:42,860 INFO L425 BuchiCegarLoop]: ======== Iteration 24============ [2021-12-16 10:06:42,860 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 604018 states and 853840 transitions. [2021-12-16 10:06:44,930 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 603724 [2021-12-16 10:06:44,930 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:06:44,930 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:06:44,934 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:44,935 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:44,935 INFO L791 eck$LassoCheckResult]: Stem: 1456297#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 1456298#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 1456107#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1455814#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1455815#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 1457130#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1457131#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1455951#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1455952#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1456436#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1456258#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1456259#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1456020#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1456021#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1456443#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 1456643#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 1456819#L936-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 1456858#L941-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 1456035#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1456036#L1258 assume !(0 == ~M_E~0); 1457459#L1258-2 assume !(0 == ~T1_E~0); 1456343#L1263-1 assume !(0 == ~T2_E~0); 1456344#L1268-1 assume !(0 == ~T3_E~0); 1456686#L1273-1 assume !(0 == ~T4_E~0); 1457431#L1278-1 assume !(0 == ~T5_E~0); 1457218#L1283-1 assume !(0 == ~T6_E~0); 1457219#L1288-1 assume !(0 == ~T7_E~0); 1457596#L1293-1 assume !(0 == ~T8_E~0); 1457573#L1298-1 assume !(0 == ~T9_E~0); 1457447#L1303-1 assume !(0 == ~T10_E~0); 1455841#L1308-1 assume !(0 == ~T11_E~0); 1455789#L1313-1 assume !(0 == ~T12_E~0); 1455790#L1318-1 assume !(0 == ~T13_E~0); 1455795#L1323-1 assume !(0 == ~E_1~0); 1455796#L1328-1 assume !(0 == ~E_2~0); 1455962#L1333-1 assume !(0 == ~E_3~0); 1457023#L1338-1 assume !(0 == ~E_4~0); 1457024#L1343-1 assume !(0 == ~E_5~0); 1457176#L1348-1 assume !(0 == ~E_6~0); 1457653#L1353-1 assume !(0 == ~E_7~0); 1456706#L1358-1 assume !(0 == ~E_8~0); 1456707#L1363-1 assume !(0 == ~E_9~0); 1457052#L1368-1 assume !(0 == ~E_10~0); 1455626#L1373-1 assume !(0 == ~E_11~0); 1455627#L1378-1 assume !(0 == ~E_12~0); 1455910#L1383-1 assume !(0 == ~E_13~0); 1455911#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1456713#L607 assume !(1 == ~m_pc~0); 1455983#L607-2 is_master_triggered_~__retres1~0#1 := 0; 1455984#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1457170#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1456619#L1560 assume !(0 != activate_threads_~tmp~1#1); 1456620#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1455806#L626 assume !(1 == ~t1_pc~0); 1455807#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1456084#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1456085#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1456264#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 1455708#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1455709#L645 assume !(1 == ~t2_pc~0); 1455779#L645-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1455780#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1456491#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1456492#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 1456594#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1456595#L664 assume !(1 == ~t3_pc~0); 1457083#L664-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1455554#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1455555#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1456222#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 1456223#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1457475#L683 assume !(1 == ~t4_pc~0); 1456843#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1456792#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1456793#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1457671#L1592 assume !(0 != activate_threads_~tmp___3~0#1); 1456972#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1456535#L702 assume !(1 == ~t5_pc~0); 1456454#L702-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1456455#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1456964#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1457416#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 1457321#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1455599#L721 assume !(1 == ~t6_pc~0); 1455572#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1455573#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1455732#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1456232#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 1456233#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1456895#L740 assume !(1 == ~t7_pc~0); 1456896#L740-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1455463#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1455464#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1455453#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 1455454#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1456160#L759 assume !(1 == ~t8_pc~0); 1456161#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1456190#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1456961#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1456962#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 1457146#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1457594#L778 assume !(1 == ~t9_pc~0); 1455624#L778-2 is_transmit9_triggered_~__retres1~9#1 := 0; 1455625#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1455565#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1455494#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 1455495#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1455819#L797 assume !(1 == ~t10_pc~0); 1455820#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 1455938#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1457256#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1456341#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 1456342#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1456668#L816 assume 1 == ~t11_pc~0; 1455530#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 1455531#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1456303#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1456239#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 1456240#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1456817#L835 assume 1 == ~t12_pc~0; 1456682#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 1455690#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1455712#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1455854#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 1456401#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 1456402#L854 assume !(1 == ~t13_pc~0); 1456022#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 1456023#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 1456080#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1455730#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 1455731#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1457314#L1401 assume !(1 == ~M_E~0); 1456226#L1401-2 assume !(1 == ~T1_E~0); 1456227#L1406-1 assume !(1 == ~T2_E~0); 1456883#L1411-1 assume !(1 == ~T3_E~0); 1456884#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1456504#L1421-1 assume !(1 == ~T5_E~0); 1456018#L1426-1 assume !(1 == ~T6_E~0); 1456019#L1431-1 assume !(1 == ~T7_E~0); 1455568#L1436-1 assume !(1 == ~T8_E~0); 1455569#L1441-1 assume !(1 == ~T9_E~0); 1456334#L1446-1 assume !(1 == ~T10_E~0); 1456335#L1451-1 assume !(1 == ~T11_E~0); 1457169#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 1456735#L1461-1 assume !(1 == ~T13_E~0); 1456252#L1466-1 assume !(1 == ~E_1~0); 1456253#L1471-1 assume !(1 == ~E_2~0); 1457144#L1476-1 assume !(1 == ~E_3~0); 1457145#L1481-1 assume !(1 == ~E_4~0); 1457384#L1486-1 assume !(1 == ~E_5~0); 1455861#L1491-1 assume !(1 == ~E_6~0); 1455502#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 1455503#L1501-1 assume !(1 == ~E_8~0); 1456330#L1506-1 assume !(1 == ~E_9~0); 1456331#L1511-1 assume !(1 == ~E_10~0); 1456285#L1516-1 assume !(1 == ~E_11~0); 1455451#L1521-1 assume !(1 == ~E_12~0); 1455452#L1526-1 assume !(1 == ~E_13~0); 1455501#L1531-1 assume { :end_inline_reset_delta_events } true; 1456047#L1892-2 [2021-12-16 10:06:44,935 INFO L793 eck$LassoCheckResult]: Loop: 1456047#L1892-2 assume !false; 1975773#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1975772#L1233 assume !false; 1975771#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 1975757#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 1975756#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 1975755#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1975753#L1046 assume !(0 != eval_~tmp~0#1); 1975754#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1976496#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1976495#L1258-3 assume !(0 == ~M_E~0); 1976494#L1258-5 assume !(0 == ~T1_E~0); 1976493#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1976492#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1976491#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1976490#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1976489#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1976488#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1976487#L1293-3 assume !(0 == ~T8_E~0); 1976486#L1298-3 assume !(0 == ~T9_E~0); 1976485#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 1976484#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 1976483#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 1976482#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 1976481#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1976480#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1976479#L1333-3 assume !(0 == ~E_3~0); 1976478#L1338-3 assume !(0 == ~E_4~0); 1976477#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1976476#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1976475#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1976474#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1976473#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 1976472#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 1976471#L1373-3 assume !(0 == ~E_11~0); 1976470#L1378-3 assume !(0 == ~E_12~0); 1976469#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 1976468#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1976467#L607-42 assume !(1 == ~m_pc~0); 1976465#L607-44 is_master_triggered_~__retres1~0#1 := 0; 1976464#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1976463#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1976462#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1976461#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1976460#L626-42 assume !(1 == ~t1_pc~0); 1976459#L626-44 is_transmit1_triggered_~__retres1~1#1 := 0; 1976458#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1976457#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1976456#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1976455#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1976454#L645-42 assume !(1 == ~t2_pc~0); 1976453#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 1976452#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1976451#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1976450#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1976449#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1976448#L664-42 assume !(1 == ~t3_pc~0); 1976447#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 1976446#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1976445#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1976444#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1976443#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1976440#L683-42 assume 1 == ~t4_pc~0; 1976441#L684-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1976442#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1976497#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1976435#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1976434#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1976433#L702-42 assume !(1 == ~t5_pc~0); 1976432#L702-44 is_transmit5_triggered_~__retres1~5#1 := 0; 1976431#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1976430#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1976429#L1600-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1976428#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1976427#L721-42 assume 1 == ~t6_pc~0; 1976426#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1976424#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1976423#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1976422#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1976421#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1976420#L740-42 assume !(1 == ~t7_pc~0); 1976419#L740-44 is_transmit7_triggered_~__retres1~7#1 := 0; 1976418#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1976417#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1976416#L1616-42 assume !(0 != activate_threads_~tmp___6~0#1); 1976415#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1976414#L759-42 assume 1 == ~t8_pc~0; 1976412#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 1976411#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1976410#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1976409#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1976408#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1976407#L778-42 assume !(1 == ~t9_pc~0); 1976406#L778-44 is_transmit9_triggered_~__retres1~9#1 := 0; 1976405#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1976404#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1976403#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1976402#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1976401#L797-42 assume 1 == ~t10_pc~0; 1976399#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 1976398#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1976397#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1976396#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1976395#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1976394#L816-42 assume !(1 == ~t11_pc~0); 1976392#L816-44 is_transmit11_triggered_~__retres1~11#1 := 0; 1976391#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1976390#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1976389#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 1976388#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1976387#L835-42 assume !(1 == ~t12_pc~0); 1976386#L835-44 is_transmit12_triggered_~__retres1~12#1 := 0; 1976384#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1976383#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1976382#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 1976381#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 1976380#L854-42 assume !(1 == ~t13_pc~0); 1976378#L854-44 is_transmit13_triggered_~__retres1~13#1 := 0; 1976377#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 1976376#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1976375#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 1976374#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1976373#L1401-3 assume !(1 == ~M_E~0); 1976370#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1976369#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1976368#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1976367#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1976366#L1421-3 assume !(1 == ~T5_E~0); 1976365#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1976364#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1976363#L1436-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1976362#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1976361#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 1976360#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 1976359#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 1976358#L1461-3 assume !(1 == ~T13_E~0); 1976357#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1976356#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1976355#L1476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1976354#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1976353#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1976352#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1976351#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1976350#L1501-3 assume !(1 == ~E_8~0); 1976349#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1976348#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 1976347#L1516-3 assume 1 == ~E_11~0;~E_11~0 := 2; 1976346#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 1976345#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 1976344#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 1976334#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 1976329#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 1976328#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 1976326#L1911 assume !(0 == start_simulation_~tmp~3#1); 1976324#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 1976323#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 1976309#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 1976308#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 1976307#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1976306#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1976305#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 1976304#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 1456047#L1892-2 [2021-12-16 10:06:44,936 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:44,936 INFO L85 PathProgramCache]: Analyzing trace with hash -1116945458, now seen corresponding path program 1 times [2021-12-16 10:06:44,936 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:44,937 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1288030571] [2021-12-16 10:06:44,937 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:44,937 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:44,958 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:06:45,005 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:06:45,005 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:06:45,005 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1288030571] [2021-12-16 10:06:45,005 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1288030571] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:06:45,005 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:06:45,005 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:06:45,005 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [857842535] [2021-12-16 10:06:45,005 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:06:45,006 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:06:45,006 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:45,006 INFO L85 PathProgramCache]: Analyzing trace with hash 1657015599, now seen corresponding path program 1 times [2021-12-16 10:06:45,006 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:45,006 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1546283935] [2021-12-16 10:06:45,006 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:45,006 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:45,013 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:06:45,027 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:06:45,027 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:06:45,027 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1546283935] [2021-12-16 10:06:45,027 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1546283935] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:06:45,027 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:06:45,027 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:06:45,028 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [519841097] [2021-12-16 10:06:45,028 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:06:45,028 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:06:45,028 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:06:45,028 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-16 10:06:45,029 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-16 10:06:45,029 INFO L87 Difference]: Start difference. First operand 604018 states and 853840 transitions. cyclomatic complexity: 249854 Second operand has 4 states, 4 states have (on average 39.75) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)