./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/transmitter.16.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version c3fed411 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/transmitter.16.cil.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 45519c8273c53879cf6a170ed74d5bc0be814b1f3243ce6c30d1d3efe9a3cf32 --- Real Ultimate output --- This is Ultimate 0.2.2-tmp.no-commuhash-c3fed41 [2021-12-16 10:06:12,391 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-12-16 10:06:12,398 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-12-16 10:06:12,439 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-12-16 10:06:12,439 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-12-16 10:06:12,440 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-12-16 10:06:12,441 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-12-16 10:06:12,442 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-12-16 10:06:12,445 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-12-16 10:06:12,450 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-12-16 10:06:12,450 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-12-16 10:06:12,453 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-12-16 10:06:12,454 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-12-16 10:06:12,456 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-12-16 10:06:12,458 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-12-16 10:06:12,462 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-12-16 10:06:12,463 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-12-16 10:06:12,463 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-12-16 10:06:12,466 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-12-16 10:06:12,469 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-12-16 10:06:12,470 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-12-16 10:06:12,471 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-12-16 10:06:12,472 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-12-16 10:06:12,473 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-12-16 10:06:12,476 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-12-16 10:06:12,476 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-12-16 10:06:12,476 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-12-16 10:06:12,477 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-12-16 10:06:12,477 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-12-16 10:06:12,477 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-12-16 10:06:12,478 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-12-16 10:06:12,478 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-12-16 10:06:12,479 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-12-16 10:06:12,479 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-12-16 10:06:12,480 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-12-16 10:06:12,480 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-12-16 10:06:12,480 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-12-16 10:06:12,481 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-12-16 10:06:12,481 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-12-16 10:06:12,481 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-12-16 10:06:12,482 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-12-16 10:06:12,482 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2021-12-16 10:06:12,505 INFO L113 SettingsManager]: Loading preferences was successful [2021-12-16 10:06:12,510 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-12-16 10:06:12,510 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2021-12-16 10:06:12,510 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2021-12-16 10:06:12,511 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-12-16 10:06:12,512 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-12-16 10:06:12,512 INFO L138 SettingsManager]: * Use SBE=true [2021-12-16 10:06:12,512 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2021-12-16 10:06:12,512 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2021-12-16 10:06:12,512 INFO L138 SettingsManager]: * Use old map elimination=false [2021-12-16 10:06:12,513 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2021-12-16 10:06:12,513 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2021-12-16 10:06:12,513 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2021-12-16 10:06:12,513 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-12-16 10:06:12,513 INFO L138 SettingsManager]: * sizeof long=4 [2021-12-16 10:06:12,514 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2021-12-16 10:06:12,514 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-12-16 10:06:12,514 INFO L138 SettingsManager]: * sizeof POINTER=4 [2021-12-16 10:06:12,514 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-12-16 10:06:12,514 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2021-12-16 10:06:12,514 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2021-12-16 10:06:12,514 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2021-12-16 10:06:12,515 INFO L138 SettingsManager]: * sizeof long double=12 [2021-12-16 10:06:12,515 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-12-16 10:06:12,516 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2021-12-16 10:06:12,516 INFO L138 SettingsManager]: * Use constant arrays=true [2021-12-16 10:06:12,516 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2021-12-16 10:06:12,516 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-12-16 10:06:12,516 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-12-16 10:06:12,516 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-12-16 10:06:12,517 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-12-16 10:06:12,517 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2021-12-16 10:06:12,517 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2021-12-16 10:06:12,518 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 45519c8273c53879cf6a170ed74d5bc0be814b1f3243ce6c30d1d3efe9a3cf32 [2021-12-16 10:06:12,695 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-12-16 10:06:12,708 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-12-16 10:06:12,710 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-12-16 10:06:12,710 INFO L271 PluginConnector]: Initializing CDTParser... [2021-12-16 10:06:12,711 INFO L275 PluginConnector]: CDTParser initialized [2021-12-16 10:06:12,711 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/transmitter.16.cil.c [2021-12-16 10:06:12,750 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/adb3d42ed/5b3870523afb441d9e8e973182ca7d4b/FLAGf116499b6 [2021-12-16 10:06:13,104 INFO L306 CDTParser]: Found 1 translation units. [2021-12-16 10:06:13,105 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.16.cil.c [2021-12-16 10:06:13,118 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/adb3d42ed/5b3870523afb441d9e8e973182ca7d4b/FLAGf116499b6 [2021-12-16 10:06:13,495 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/adb3d42ed/5b3870523afb441d9e8e973182ca7d4b [2021-12-16 10:06:13,496 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-12-16 10:06:13,499 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-12-16 10:06:13,501 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-12-16 10:06:13,501 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-12-16 10:06:13,503 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-12-16 10:06:13,504 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 16.12 10:06:13" (1/1) ... [2021-12-16 10:06:13,505 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@4167db34 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:06:13, skipping insertion in model container [2021-12-16 10:06:13,505 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 16.12 10:06:13" (1/1) ... [2021-12-16 10:06:13,509 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-12-16 10:06:13,545 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-12-16 10:06:13,666 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.16.cil.c[706,719] [2021-12-16 10:06:13,759 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-16 10:06:13,766 INFO L203 MainTranslator]: Completed pre-run [2021-12-16 10:06:13,775 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.16.cil.c[706,719] [2021-12-16 10:06:13,853 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-16 10:06:13,868 INFO L208 MainTranslator]: Completed translation [2021-12-16 10:06:13,868 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:06:13 WrapperNode [2021-12-16 10:06:13,869 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-12-16 10:06:13,870 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-12-16 10:06:13,870 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-12-16 10:06:13,870 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-12-16 10:06:13,874 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:06:13" (1/1) ... [2021-12-16 10:06:13,885 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:06:13" (1/1) ... [2021-12-16 10:06:13,971 INFO L137 Inliner]: procedures = 56, calls = 71, calls flagged for inlining = 66, calls inlined = 303, statements flattened = 4715 [2021-12-16 10:06:13,971 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-12-16 10:06:13,972 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-12-16 10:06:13,972 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-12-16 10:06:13,972 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-12-16 10:06:13,978 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:06:13" (1/1) ... [2021-12-16 10:06:13,978 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:06:13" (1/1) ... [2021-12-16 10:06:13,988 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:06:13" (1/1) ... [2021-12-16 10:06:13,989 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:06:13" (1/1) ... [2021-12-16 10:06:14,047 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:06:13" (1/1) ... [2021-12-16 10:06:14,074 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:06:13" (1/1) ... [2021-12-16 10:06:14,079 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:06:13" (1/1) ... [2021-12-16 10:06:14,090 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-12-16 10:06:14,091 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-12-16 10:06:14,091 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-12-16 10:06:14,091 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-12-16 10:06:14,092 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:06:13" (1/1) ... [2021-12-16 10:06:14,097 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-16 10:06:14,105 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-16 10:06:14,127 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-16 10:06:14,150 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2021-12-16 10:06:14,156 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2021-12-16 10:06:14,156 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2021-12-16 10:06:14,156 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-12-16 10:06:14,156 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-12-16 10:06:14,293 INFO L236 CfgBuilder]: Building ICFG [2021-12-16 10:06:14,294 INFO L262 CfgBuilder]: Building CFG for each procedure with an implementation [2021-12-16 10:06:15,872 INFO L277 CfgBuilder]: Performing block encoding [2021-12-16 10:06:15,903 INFO L296 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-12-16 10:06:15,903 INFO L301 CfgBuilder]: Removed 18 assume(true) statements. [2021-12-16 10:06:15,907 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 16.12 10:06:15 BoogieIcfgContainer [2021-12-16 10:06:15,908 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-12-16 10:06:15,910 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2021-12-16 10:06:15,910 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2021-12-16 10:06:15,912 INFO L275 PluginConnector]: BuchiAutomizer initialized [2021-12-16 10:06:15,913 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-16 10:06:15,913 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 16.12 10:06:13" (1/3) ... [2021-12-16 10:06:15,914 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@6a26b21 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 16.12 10:06:15, skipping insertion in model container [2021-12-16 10:06:15,914 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-16 10:06:15,914 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 16.12 10:06:13" (2/3) ... [2021-12-16 10:06:15,914 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@6a26b21 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 16.12 10:06:15, skipping insertion in model container [2021-12-16 10:06:15,914 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-16 10:06:15,915 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 16.12 10:06:15" (3/3) ... [2021-12-16 10:06:15,916 INFO L388 chiAutomizerObserver]: Analyzing ICFG transmitter.16.cil.c [2021-12-16 10:06:15,944 INFO L359 BuchiCegarLoop]: Interprodecural is true [2021-12-16 10:06:15,944 INFO L360 BuchiCegarLoop]: Hoare is false [2021-12-16 10:06:15,944 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2021-12-16 10:06:15,944 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2021-12-16 10:06:15,945 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2021-12-16 10:06:15,945 INFO L364 BuchiCegarLoop]: Difference is false [2021-12-16 10:06:15,945 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2021-12-16 10:06:15,945 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2021-12-16 10:06:15,980 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 2053 states, 2052 states have (on average 1.4995126705653021) internal successors, (3077), 2052 states have internal predecessors, (3077), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:16,057 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1864 [2021-12-16 10:06:16,057 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:06:16,057 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:06:16,077 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:16,078 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:16,078 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2021-12-16 10:06:16,082 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 2053 states, 2052 states have (on average 1.4995126705653021) internal successors, (3077), 2052 states have internal predecessors, (3077), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:16,098 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1864 [2021-12-16 10:06:16,098 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:06:16,098 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:06:16,105 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:16,105 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:16,120 INFO L791 eck$LassoCheckResult]: Stem: 490#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 1963#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 967#L1980true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 327#L932true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1919#L939true assume !(1 == ~m_i~0);~m_st~0 := 2; 471#L939-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 1669#L944-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 311#L949-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1324#L954-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1969#L959-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 680#L964-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 1176#L969-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 1779#L974-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 615#L979-1true assume 1 == ~t9_i~0;~t9_st~0 := 0; 952#L984-1true assume !(1 == ~t10_i~0);~t10_st~0 := 2; 257#L989-1true assume !(1 == ~t11_i~0);~t11_st~0 := 2; 449#L994-1true assume !(1 == ~t12_i~0);~t12_st~0 := 2; 1206#L999-1true assume !(1 == ~t13_i~0);~t13_st~0 := 2; 580#L1004-1true assume !(1 == ~t14_i~0);~t14_st~0 := 2; 48#L1009-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 127#L1342true assume !(0 == ~M_E~0); 429#L1342-2true assume !(0 == ~T1_E~0); 1614#L1347-1true assume !(0 == ~T2_E~0); 1304#L1352-1true assume !(0 == ~T3_E~0); 1073#L1357-1true assume !(0 == ~T4_E~0); 445#L1362-1true assume !(0 == ~T5_E~0); 1387#L1367-1true assume !(0 == ~T6_E~0); 215#L1372-1true assume 0 == ~T7_E~0;~T7_E~0 := 1; 568#L1377-1true assume !(0 == ~T8_E~0); 401#L1382-1true assume !(0 == ~T9_E~0); 946#L1387-1true assume !(0 == ~T10_E~0); 1525#L1392-1true assume !(0 == ~T11_E~0); 420#L1397-1true assume !(0 == ~T12_E~0); 1682#L1402-1true assume !(0 == ~T13_E~0); 224#L1407-1true assume !(0 == ~T14_E~0); 1860#L1412-1true assume 0 == ~E_1~0;~E_1~0 := 1; 1201#L1417-1true assume !(0 == ~E_2~0); 2053#L1422-1true assume !(0 == ~E_3~0); 1681#L1427-1true assume !(0 == ~E_4~0); 331#L1432-1true assume !(0 == ~E_5~0); 1532#L1437-1true assume !(0 == ~E_6~0); 1118#L1442-1true assume !(0 == ~E_7~0); 1459#L1447-1true assume !(0 == ~E_8~0); 942#L1452-1true assume 0 == ~E_9~0;~E_9~0 := 1; 113#L1457-1true assume !(0 == ~E_10~0); 1154#L1462-1true assume !(0 == ~E_11~0); 1857#L1467-1true assume !(0 == ~E_12~0); 1172#L1472-1true assume !(0 == ~E_13~0); 1360#L1477-1true assume !(0 == ~E_14~0); 894#L1482-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 210#L646true assume 1 == ~m_pc~0; 624#L647true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 632#L657true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 663#L658true activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 258#L1666true assume !(0 != activate_threads_~tmp~1#1); 1984#L1666-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1747#L665true assume !(1 == ~t1_pc~0); 541#L665-2true is_transmit1_triggered_~__retres1~1#1 := 0; 1200#L676true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 262#L677true activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1708#L1674true assume !(0 != activate_threads_~tmp___0~0#1); 779#L1674-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 890#L684true assume 1 == ~t2_pc~0; 1868#L685true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 881#L695true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1693#L696true activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1308#L1682true assume !(0 != activate_threads_~tmp___1~0#1); 1813#L1682-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1789#L703true assume !(1 == ~t3_pc~0); 342#L703-2true is_transmit3_triggered_~__retres1~3#1 := 0; 1403#L714true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 771#L715true activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 35#L1690true assume !(0 != activate_threads_~tmp___2~0#1); 274#L1690-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1322#L722true assume 1 == ~t4_pc~0; 752#L723true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 603#L733true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1105#L734true activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1623#L1698true assume !(0 != activate_threads_~tmp___3~0#1); 649#L1698-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 128#L741true assume 1 == ~t5_pc~0; 288#L742true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 806#L752true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 374#L753true activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 860#L1706true assume !(0 != activate_threads_~tmp___4~0#1); 1385#L1706-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 430#L760true assume !(1 == ~t6_pc~0); 739#L760-2true is_transmit6_triggered_~__retres1~6#1 := 0; 986#L771true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 259#L772true activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1660#L1714true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 719#L1714-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1402#L779true assume 1 == ~t7_pc~0; 148#L780true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 76#L790true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 281#L791true activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1377#L1722true assume !(0 != activate_threads_~tmp___6~0#1); 295#L1722-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1691#L798true assume !(1 == ~t8_pc~0); 1935#L798-2true is_transmit8_triggered_~__retres1~8#1 := 0; 1262#L809true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 149#L810true activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1749#L1730true assume !(0 != activate_threads_~tmp___7~0#1); 1907#L1730-2true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 66#L817true assume 1 == ~t9_pc~0; 828#L818true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 495#L828true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 899#L829true activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1862#L1738true assume !(0 != activate_threads_~tmp___8~0#1); 265#L1738-2true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 773#L836true assume !(1 == ~t10_pc~0); 276#L836-2true is_transmit10_triggered_~__retres1~10#1 := 0; 238#L847true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1563#L848true activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 377#L1746true assume !(0 != activate_threads_~tmp___9~0#1); 1276#L1746-2true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1277#L855true assume 1 == ~t11_pc~0; 630#L856true assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 1147#L866true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1245#L867true activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 939#L1754true assume !(0 != activate_threads_~tmp___10~0#1); 784#L1754-2true assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 208#L874true assume !(1 == ~t12_pc~0); 1641#L874-2true is_transmit12_triggered_~__retres1~12#1 := 0; 300#L885true is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 378#L886true activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1987#L1762true assume !(0 != activate_threads_~tmp___11~0#1); 52#L1762-2true assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 1861#L893true assume 1 == ~t13_pc~0; 1545#L894true assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 400#L904true is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 1386#L905true activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 1560#L1770true assume !(0 != activate_threads_~tmp___12~0#1); 1396#L1770-2true assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 1767#L912true assume 1 == ~t14_pc~0; 1123#L913true assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 2023#L923true is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 209#L924true activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 174#L1778true assume !(0 != activate_threads_~tmp___13~0#1); 643#L1778-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1342#L1495true assume 1 == ~M_E~0;~M_E~0 := 2; 1001#L1495-2true assume !(1 == ~T1_E~0); 1674#L1500-1true assume !(1 == ~T2_E~0); 716#L1505-1true assume !(1 == ~T3_E~0); 1914#L1510-1true assume !(1 == ~T4_E~0); 759#L1515-1true assume !(1 == ~T5_E~0); 1727#L1520-1true assume !(1 == ~T6_E~0); 1394#L1525-1true assume !(1 == ~T7_E~0); 1031#L1530-1true assume 1 == ~T8_E~0;~T8_E~0 := 2; 263#L1535-1true assume !(1 == ~T9_E~0); 1837#L1540-1true assume !(1 == ~T10_E~0); 17#L1545-1true assume !(1 == ~T11_E~0); 1973#L1550-1true assume !(1 == ~T12_E~0); 132#L1555-1true assume !(1 == ~T13_E~0); 289#L1560-1true assume !(1 == ~T14_E~0); 1706#L1565-1true assume !(1 == ~E_1~0); 1928#L1570-1true assume 1 == ~E_2~0;~E_2~0 := 2; 913#L1575-1true assume !(1 == ~E_3~0); 446#L1580-1true assume !(1 == ~E_4~0); 774#L1585-1true assume !(1 == ~E_5~0); 1045#L1590-1true assume !(1 == ~E_6~0); 468#L1595-1true assume !(1 == ~E_7~0); 1895#L1600-1true assume !(1 == ~E_8~0); 723#L1605-1true assume !(1 == ~E_9~0); 1649#L1610-1true assume 1 == ~E_10~0;~E_10~0 := 2; 1240#L1615-1true assume !(1 == ~E_11~0); 365#L1620-1true assume !(1 == ~E_12~0); 1103#L1625-1true assume !(1 == ~E_13~0); 943#L1630-1true assume !(1 == ~E_14~0); 467#L1635-1true assume { :end_inline_reset_delta_events } true; 431#L2017-2true [2021-12-16 10:06:16,126 INFO L793 eck$LassoCheckResult]: Loop: 431#L2017-2true assume !false; 50#L2018true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 882#L1316true assume !true; 1267#L1332true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 502#L932-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 629#L1342-3true assume 0 == ~M_E~0;~M_E~0 := 1; 1078#L1342-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 1167#L1347-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 751#L1352-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 1355#L1357-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 2038#L1362-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 1880#L1367-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 1847#L1372-3true assume !(0 == ~T7_E~0); 42#L1377-3true assume 0 == ~T8_E~0;~T8_E~0 := 1; 491#L1382-3true assume 0 == ~T9_E~0;~T9_E~0 := 1; 388#L1387-3true assume 0 == ~T10_E~0;~T10_E~0 := 1; 1124#L1392-3true assume 0 == ~T11_E~0;~T11_E~0 := 1; 1948#L1397-3true assume 0 == ~T12_E~0;~T12_E~0 := 1; 1666#L1402-3true assume 0 == ~T13_E~0;~T13_E~0 := 1; 708#L1407-3true assume 0 == ~T14_E~0;~T14_E~0 := 1; 188#L1412-3true assume !(0 == ~E_1~0); 1397#L1417-3true assume 0 == ~E_2~0;~E_2~0 := 1; 654#L1422-3true assume 0 == ~E_3~0;~E_3~0 := 1; 1347#L1427-3true assume 0 == ~E_4~0;~E_4~0 := 1; 1534#L1432-3true assume 0 == ~E_5~0;~E_5~0 := 1; 976#L1437-3true assume 0 == ~E_6~0;~E_6~0 := 1; 720#L1442-3true assume 0 == ~E_7~0;~E_7~0 := 1; 1000#L1447-3true assume 0 == ~E_8~0;~E_8~0 := 1; 73#L1452-3true assume !(0 == ~E_9~0); 1999#L1457-3true assume 0 == ~E_10~0;~E_10~0 := 1; 1258#L1462-3true assume 0 == ~E_11~0;~E_11~0 := 1; 1689#L1467-3true assume 0 == ~E_12~0;~E_12~0 := 1; 1048#L1472-3true assume 0 == ~E_13~0;~E_13~0 := 1; 1714#L1477-3true assume 0 == ~E_14~0;~E_14~0 := 1; 187#L1482-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 523#L646-42true assume 1 == ~m_pc~0; 1978#L647-14true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1306#L657-14true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1676#L658-14true activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1619#L1666-42true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1711#L1666-44true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1216#L665-42true assume !(1 == ~t1_pc~0); 1456#L665-44true is_transmit1_triggered_~__retres1~1#1 := 0; 1538#L676-14true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1463#L677-14true activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 277#L1674-42true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1883#L1674-44true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1879#L684-42true assume !(1 == ~t2_pc~0); 1793#L684-44true is_transmit2_triggered_~__retres1~2#1 := 0; 1893#L695-14true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1808#L696-14true activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 678#L1682-42true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 766#L1682-44true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1741#L703-42true assume 1 == ~t3_pc~0; 950#L704-14true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1851#L714-14true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 434#L715-14true activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1630#L1690-42true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1052#L1690-44true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 698#L722-42true assume 1 == ~t4_pc~0; 1091#L723-14true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1719#L733-14true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 464#L734-14true activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 357#L1698-42true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1920#L1698-44true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1730#L741-42true assume 1 == ~t5_pc~0; 1548#L742-14true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 606#L752-14true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1965#L753-14true activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1898#L1706-42true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 536#L1706-44true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 636#L760-42true assume 1 == ~t6_pc~0; 1763#L761-14true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 730#L771-14true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1114#L772-14true activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1638#L1714-42true assume !(0 != activate_threads_~tmp___5~0#1); 506#L1714-44true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1315#L779-42true assume 1 == ~t7_pc~0; 1242#L780-14true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1870#L790-14true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 319#L791-14true activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1701#L1722-42true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 237#L1722-44true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 500#L798-42true assume 1 == ~t8_pc~0; 1924#L799-14true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 1432#L809-14true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1330#L810-14true activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 747#L1730-42true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 150#L1730-44true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1370#L817-42true assume !(1 == ~t9_pc~0); 1149#L817-44true is_transmit9_triggered_~__retres1~9#1 := 0; 303#L828-14true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 372#L829-14true activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1186#L1738-42true assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 974#L1738-44true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1515#L836-42true assume !(1 == ~t10_pc~0); 1817#L836-44true is_transmit10_triggered_~__retres1~10#1 := 0; 326#L847-14true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1842#L848-14true activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1553#L1746-42true assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1697#L1746-44true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 2046#L855-42true assume 1 == ~t11_pc~0; 1722#L856-14true assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 92#L866-14true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 503#L867-14true activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1169#L1754-42true assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 2048#L1754-44true assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 418#L874-42true assume 1 == ~t12_pc~0; 575#L875-14true assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 1487#L885-14true is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 51#L886-14true activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 892#L1762-42true assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 171#L1762-44true assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 1982#L893-42true assume 1 == ~t13_pc~0; 1007#L894-14true assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 1836#L904-14true is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 808#L905-14true activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 728#L1770-42true assume !(0 != activate_threads_~tmp___12~0#1); 375#L1770-44true assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 1849#L912-42true assume !(1 == ~t14_pc~0); 981#L912-44true is_transmit14_triggered_~__retres1~14#1 := 0; 27#L923-14true is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 1089#L924-14true activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 1219#L1778-42true assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 233#L1778-44true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 611#L1495-3true assume !(1 == ~M_E~0); 966#L1495-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 1574#L1500-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 1070#L1505-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 360#L1510-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 343#L1515-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 783#L1520-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 997#L1525-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 1580#L1530-3true assume !(1 == ~T8_E~0); 254#L1535-3true assume 1 == ~T9_E~0;~T9_E~0 := 2; 275#L1540-3true assume 1 == ~T10_E~0;~T10_E~0 := 2; 1289#L1545-3true assume 1 == ~T11_E~0;~T11_E~0 := 2; 1533#L1550-3true assume 1 == ~T12_E~0;~T12_E~0 := 2; 1513#L1555-3true assume 1 == ~T13_E~0;~T13_E~0 := 2; 516#L1560-3true assume 1 == ~T14_E~0;~T14_E~0 := 2; 1025#L1565-3true assume 1 == ~E_1~0;~E_1~0 := 2; 1874#L1570-3true assume !(1 == ~E_2~0); 970#L1575-3true assume 1 == ~E_3~0;~E_3~0 := 2; 1421#L1580-3true assume 1 == ~E_4~0;~E_4~0 := 2; 1522#L1585-3true assume 1 == ~E_5~0;~E_5~0 := 2; 1759#L1590-3true assume 1 == ~E_6~0;~E_6~0 := 2; 1663#L1595-3true assume 1 == ~E_7~0;~E_7~0 := 2; 803#L1600-3true assume 1 == ~E_8~0;~E_8~0 := 2; 1309#L1605-3true assume 1 == ~E_9~0;~E_9~0 := 2; 1398#L1610-3true assume !(1 == ~E_10~0); 366#L1615-3true assume 1 == ~E_11~0;~E_11~0 := 2; 1912#L1620-3true assume 1 == ~E_12~0;~E_12~0 := 2; 776#L1625-3true assume 1 == ~E_13~0;~E_13~0 := 2; 2041#L1630-3true assume 1 == ~E_14~0;~E_14~0 := 2; 700#L1635-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 336#L1022-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 539#L1100-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 1967#L1101-1true start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 999#L2036true assume !(0 == start_simulation_~tmp~3#1); 1175#L2036-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 1631#L1022-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 1422#L1100-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 1927#L1101-2true stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 733#L1991true assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 1734#L1998true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1704#L1999true start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 1807#L2049true assume !(0 != start_simulation_~tmp___0~1#1); 431#L2017-2true [2021-12-16 10:06:16,132 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:16,132 INFO L85 PathProgramCache]: Analyzing trace with hash -1440429276, now seen corresponding path program 1 times [2021-12-16 10:06:16,139 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:16,139 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [357312872] [2021-12-16 10:06:16,140 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:16,140 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:16,215 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:06:16,317 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:06:16,318 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:06:16,318 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [357312872] [2021-12-16 10:06:16,319 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [357312872] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:06:16,319 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:06:16,319 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:06:16,321 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [745370370] [2021-12-16 10:06:16,321 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:06:16,324 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:06:16,324 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:16,325 INFO L85 PathProgramCache]: Analyzing trace with hash 1941229649, now seen corresponding path program 1 times [2021-12-16 10:06:16,325 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:16,325 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [52031264] [2021-12-16 10:06:16,325 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:16,325 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:16,337 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:06:16,364 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:06:16,364 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:06:16,364 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [52031264] [2021-12-16 10:06:16,364 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [52031264] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:06:16,364 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:06:16,365 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-16 10:06:16,365 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [380403693] [2021-12-16 10:06:16,365 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:06:16,366 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:06:16,367 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:06:16,414 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2021-12-16 10:06:16,415 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2021-12-16 10:06:16,420 INFO L87 Difference]: Start difference. First operand has 2053 states, 2052 states have (on average 1.4995126705653021) internal successors, (3077), 2052 states have internal predecessors, (3077), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 2 states, 2 states have (on average 83.5) internal successors, (167), 2 states have internal predecessors, (167), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:16,536 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:06:16,536 INFO L93 Difference]: Finished difference Result 2052 states and 3039 transitions. [2021-12-16 10:06:16,537 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2021-12-16 10:06:16,540 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2052 states and 3039 transitions. [2021-12-16 10:06:16,555 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2021-12-16 10:06:16,570 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2052 states to 2047 states and 3034 transitions. [2021-12-16 10:06:16,571 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2047 [2021-12-16 10:06:16,573 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2047 [2021-12-16 10:06:16,573 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2047 states and 3034 transitions. [2021-12-16 10:06:16,583 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:06:16,583 INFO L681 BuchiCegarLoop]: Abstraction has 2047 states and 3034 transitions. [2021-12-16 10:06:16,597 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2047 states and 3034 transitions. [2021-12-16 10:06:16,636 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2047 to 2047. [2021-12-16 10:06:16,640 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2047 states, 2047 states have (on average 1.4821690278456277) internal successors, (3034), 2046 states have internal predecessors, (3034), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:16,645 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2047 states to 2047 states and 3034 transitions. [2021-12-16 10:06:16,646 INFO L704 BuchiCegarLoop]: Abstraction has 2047 states and 3034 transitions. [2021-12-16 10:06:16,646 INFO L587 BuchiCegarLoop]: Abstraction has 2047 states and 3034 transitions. [2021-12-16 10:06:16,646 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2021-12-16 10:06:16,646 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2047 states and 3034 transitions. [2021-12-16 10:06:16,658 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2021-12-16 10:06:16,658 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:06:16,658 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:06:16,664 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:16,664 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:16,665 INFO L791 eck$LassoCheckResult]: Stem: 5040#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 5041#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 5643#L1980 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4760#L932 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4761#L939 assume !(1 == ~m_i~0);~m_st~0 := 2; 5006#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5007#L944-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 4734#L949-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 4735#L954-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 5958#L959-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 5310#L964-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 5311#L969-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 5828#L974-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 5220#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 5221#L984-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 4641#L989-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 4642#L994-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 4973#L999-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 5171#L1004-1 assume !(1 == ~t14_i~0);~t14_st~0 := 2; 4218#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4219#L1342 assume !(0 == ~M_E~0); 4384#L1342-2 assume !(0 == ~T1_E~0); 4940#L1347-1 assume !(0 == ~T2_E~0); 5941#L1352-1 assume !(0 == ~T3_E~0); 5737#L1357-1 assume !(0 == ~T4_E~0); 4965#L1362-1 assume !(0 == ~T5_E~0); 4966#L1367-1 assume !(0 == ~T6_E~0); 4563#L1372-1 assume 0 == ~T7_E~0;~T7_E~0 := 1; 4564#L1377-1 assume !(0 == ~T8_E~0); 4894#L1382-1 assume !(0 == ~T9_E~0); 4895#L1387-1 assume !(0 == ~T10_E~0); 5622#L1392-1 assume !(0 == ~T11_E~0); 4926#L1397-1 assume !(0 == ~T12_E~0); 4927#L1402-1 assume !(0 == ~T13_E~0); 4579#L1407-1 assume !(0 == ~T14_E~0); 4580#L1412-1 assume 0 == ~E_1~0;~E_1~0 := 1; 5858#L1417-1 assume !(0 == ~E_2~0); 5859#L1422-1 assume !(0 == ~E_3~0); 6100#L1427-1 assume !(0 == ~E_4~0); 4767#L1432-1 assume !(0 == ~E_5~0); 4768#L1437-1 assume !(0 == ~E_6~0); 5776#L1442-1 assume !(0 == ~E_7~0); 5777#L1447-1 assume !(0 == ~E_8~0); 5619#L1452-1 assume 0 == ~E_9~0;~E_9~0 := 1; 4354#L1457-1 assume !(0 == ~E_10~0); 4355#L1462-1 assume !(0 == ~E_11~0); 5811#L1467-1 assume !(0 == ~E_12~0); 5823#L1472-1 assume !(0 == ~E_13~0); 5824#L1477-1 assume !(0 == ~E_14~0); 5566#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4553#L646 assume 1 == ~m_pc~0; 4554#L647 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 5230#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5245#L658 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4643#L1666 assume !(0 != activate_threads_~tmp~1#1); 4644#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6121#L665 assume !(1 == ~t1_pc~0); 5119#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 5120#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4652#L677 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4653#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 5443#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5444#L684 assume 1 == ~t2_pc~0; 5561#L685 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5485#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5550#L696 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5945#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 5946#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6134#L703 assume !(1 == ~t3_pc~0); 4789#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 4790#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5436#L715 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4188#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 4189#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4674#L722 assume 1 == ~t4_pc~0; 5412#L723 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4855#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5200#L734 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 5760#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 5267#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4385#L741 assume 1 == ~t5_pc~0; 4386#L742 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 4696#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4850#L753 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4851#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 5530#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4941#L760 assume !(1 == ~t6_pc~0); 4788#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 4787#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4645#L772 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4646#L1714 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 5367#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5368#L779 assume 1 == ~t7_pc~0; 4430#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 4276#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4277#L791 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 4685#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 4708#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4709#L798 assume !(1 == ~t8_pc~0); 5990#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 5913#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4432#L810 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 4433#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 6123#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4253#L817 assume 1 == ~t9_pc~0; 4254#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 5048#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 5049#L829 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 5571#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 4659#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4660#L836 assume !(1 == ~t10_pc~0); 4676#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 4607#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 4608#L848 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 4856#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 4857#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 5923#L855 assume 1 == ~t11_pc~0; 5241#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 5242#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 5806#L867 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 5615#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 5450#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 4549#L874 assume !(1 == ~t12_pc~0); 4550#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 4717#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 4718#L886 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 4858#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 4226#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 4227#L893 assume 1 == ~t13_pc~0; 6057#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 4582#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 4893#L905 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 5984#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 5992#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 5993#L912 assume 1 == ~t14_pc~0; 5783#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 5784#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 4552#L924 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 4484#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 4485#L1778-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5260#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 5676#L1495-2 assume !(1 == ~T1_E~0); 5677#L1500-1 assume !(1 == ~T2_E~0); 5363#L1505-1 assume !(1 == ~T3_E~0); 5364#L1510-1 assume !(1 == ~T4_E~0); 5421#L1515-1 assume !(1 == ~T5_E~0); 5422#L1520-1 assume !(1 == ~T6_E~0); 5991#L1525-1 assume !(1 == ~T7_E~0); 5701#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 4654#L1535-1 assume !(1 == ~T9_E~0); 4655#L1540-1 assume !(1 == ~T10_E~0); 4147#L1545-1 assume !(1 == ~T11_E~0); 4148#L1550-1 assume !(1 == ~T12_E~0); 4396#L1555-1 assume !(1 == ~T13_E~0); 4397#L1560-1 assume !(1 == ~T14_E~0); 4697#L1565-1 assume !(1 == ~E_1~0); 6110#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 5588#L1575-1 assume !(1 == ~E_3~0); 4967#L1580-1 assume !(1 == ~E_4~0); 4968#L1585-1 assume !(1 == ~E_5~0); 5438#L1590-1 assume !(1 == ~E_6~0); 5002#L1595-1 assume !(1 == ~E_7~0); 5003#L1600-1 assume !(1 == ~E_8~0); 5375#L1605-1 assume !(1 == ~E_9~0); 5376#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 5893#L1615-1 assume !(1 == ~E_11~0); 4832#L1620-1 assume !(1 == ~E_12~0); 4833#L1625-1 assume !(1 == ~E_13~0); 5620#L1630-1 assume !(1 == ~E_14~0); 5001#L1635-1 assume { :end_inline_reset_delta_events } true; 4942#L2017-2 [2021-12-16 10:06:16,666 INFO L793 eck$LassoCheckResult]: Loop: 4942#L2017-2 assume !false; 4222#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4223#L1316 assume !false; 5551#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 5613#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 4160#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 4302#L1101 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 4303#L1115 assume !(0 != eval_~tmp~0#1); 5636#L1332 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5057#L932-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5058#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5240#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5741#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5410#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5411#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5973#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 6148#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 6143#L1372-3 assume !(0 == ~T7_E~0); 4204#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 4205#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 4874#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 4875#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 5786#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 6096#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 5354#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 4510#L1412-3 assume !(0 == ~E_1~0); 4511#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5275#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5276#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 5970#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 5657#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 5369#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 5370#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 4270#L1452-3 assume !(0 == ~E_9~0); 4271#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 5909#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 5910#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 5714#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 5715#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 4508#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4509#L646-42 assume 1 == ~m_pc~0; 5094#L647-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 5942#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5943#L658-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 6081#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 6082#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5874#L665-42 assume 1 == ~t1_pc~0; 5835#L666-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5837#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6023#L677-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4677#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4678#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6147#L684-42 assume 1 == ~t2_pc~0; 5526#L685-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5527#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6137#L696-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5306#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5307#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5429#L703-42 assume 1 == ~t3_pc~0; 5627#L704-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5628#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4946#L715-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4947#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5721#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5341#L722-42 assume 1 == ~t4_pc~0; 5342#L723-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5752#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4995#L734-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4822#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4823#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6117#L741-42 assume !(1 == ~t5_pc~0); 5734#L741-44 is_transmit5_triggered_~__retres1~5#1 := 0; 5204#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5205#L753-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 6150#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 5112#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5113#L760-42 assume 1 == ~t6_pc~0; 5248#L761-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 5382#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5383#L772-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 5771#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 5064#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5065#L779-42 assume !(1 == ~t7_pc~0); 5841#L779-44 is_transmit7_triggered_~__retres1~7#1 := 0; 5842#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4749#L791-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 4750#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 4605#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4606#L798-42 assume 1 == ~t8_pc~0; 5056#L799-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 4217#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 5960#L810-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 5406#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 4436#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4437#L817-42 assume 1 == ~t9_pc~0; 5210#L818-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 4720#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4721#L829-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 4847#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 5652#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 5653#L836-42 assume 1 == ~t10_pc~0; 5745#L837-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 4758#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 4759#L848-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 6060#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 6061#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 6102#L855-42 assume 1 == ~t11_pc~0; 6115#L856-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 4309#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 4310#L867-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 5059#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 5822#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 4923#L874-42 assume 1 == ~t12_pc~0; 4924#L875-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 5163#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 4224#L886-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 4225#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 4478#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 4479#L893-42 assume 1 == ~t13_pc~0; 5681#L894-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 5463#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 5478#L905-14 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 5380#L1770-42 assume !(0 != activate_threads_~tmp___12~0#1); 4852#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 4853#L912-42 assume 1 == ~t14_pc~0; 6097#L913-14 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 4170#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 4171#L924-14 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 5751#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 4598#L1778-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4599#L1495-3 assume !(1 == ~M_E~0); 5214#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5642#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5735#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4828#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4791#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4792#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 5449#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 5672#L1530-3 assume !(1 == ~T8_E~0); 4637#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 4638#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 4675#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 5932#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 6041#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 5081#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 5082#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5697#L1570-3 assume !(1 == ~E_2~0); 5648#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5649#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 6004#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 6048#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 6094#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 5471#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 5472#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 5947#L1610-3 assume !(1 == ~E_10~0); 4834#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 4835#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 5439#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 5440#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 5344#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 4775#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 4380#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 5118#L1101-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 5674#L2036 assume !(0 == start_simulation_~tmp~3#1); 5675#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 5827#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 4987#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 6005#L1101-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 5387#L1991 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 5388#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6108#L1999 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 6109#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 4942#L2017-2 [2021-12-16 10:06:16,669 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:16,669 INFO L85 PathProgramCache]: Analyzing trace with hash -1440429276, now seen corresponding path program 2 times [2021-12-16 10:06:16,669 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:16,670 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1097896723] [2021-12-16 10:06:16,670 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:16,670 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:16,707 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:06:16,743 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:06:16,745 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:06:16,745 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1097896723] [2021-12-16 10:06:16,745 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1097896723] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:06:16,745 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:06:16,745 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:06:16,745 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1281381147] [2021-12-16 10:06:16,746 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:06:16,747 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:06:16,748 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:16,748 INFO L85 PathProgramCache]: Analyzing trace with hash 1105916303, now seen corresponding path program 1 times [2021-12-16 10:06:16,749 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:16,749 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2109030646] [2021-12-16 10:06:16,749 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:16,749 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:16,790 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:06:16,875 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:06:16,875 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:06:16,876 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2109030646] [2021-12-16 10:06:16,876 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2109030646] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:06:16,876 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:06:16,876 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:06:16,876 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [810717008] [2021-12-16 10:06:16,876 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:06:16,876 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:06:16,877 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:06:16,877 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-16 10:06:16,877 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-16 10:06:16,877 INFO L87 Difference]: Start difference. First operand 2047 states and 3034 transitions. cyclomatic complexity: 988 Second operand has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:16,927 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:06:16,927 INFO L93 Difference]: Finished difference Result 2047 states and 3033 transitions. [2021-12-16 10:06:16,928 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-16 10:06:16,928 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2047 states and 3033 transitions. [2021-12-16 10:06:16,938 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2021-12-16 10:06:16,946 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2047 states to 2047 states and 3033 transitions. [2021-12-16 10:06:16,946 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2047 [2021-12-16 10:06:16,948 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2047 [2021-12-16 10:06:16,948 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2047 states and 3033 transitions. [2021-12-16 10:06:16,950 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:06:16,950 INFO L681 BuchiCegarLoop]: Abstraction has 2047 states and 3033 transitions. [2021-12-16 10:06:16,952 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2047 states and 3033 transitions. [2021-12-16 10:06:17,002 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2047 to 2047. [2021-12-16 10:06:17,005 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2047 states, 2047 states have (on average 1.4816805080605764) internal successors, (3033), 2046 states have internal predecessors, (3033), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:17,010 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2047 states to 2047 states and 3033 transitions. [2021-12-16 10:06:17,011 INFO L704 BuchiCegarLoop]: Abstraction has 2047 states and 3033 transitions. [2021-12-16 10:06:17,011 INFO L587 BuchiCegarLoop]: Abstraction has 2047 states and 3033 transitions. [2021-12-16 10:06:17,011 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2021-12-16 10:06:17,011 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2047 states and 3033 transitions. [2021-12-16 10:06:17,018 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2021-12-16 10:06:17,018 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:06:17,018 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:06:17,020 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:17,020 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:17,020 INFO L791 eck$LassoCheckResult]: Stem: 9141#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 9142#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 9744#L1980 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8861#L932 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 8862#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 9107#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9108#L944-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 8835#L949-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 8836#L954-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 10059#L959-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 9411#L964-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 9412#L969-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 9929#L974-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 9321#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 9322#L984-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 8742#L989-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 8743#L994-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 9074#L999-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 9272#L1004-1 assume !(1 == ~t14_i~0);~t14_st~0 := 2; 8319#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8320#L1342 assume !(0 == ~M_E~0); 8485#L1342-2 assume !(0 == ~T1_E~0); 9041#L1347-1 assume !(0 == ~T2_E~0); 10042#L1352-1 assume !(0 == ~T3_E~0); 9838#L1357-1 assume !(0 == ~T4_E~0); 9066#L1362-1 assume !(0 == ~T5_E~0); 9067#L1367-1 assume !(0 == ~T6_E~0); 8664#L1372-1 assume 0 == ~T7_E~0;~T7_E~0 := 1; 8665#L1377-1 assume !(0 == ~T8_E~0); 8995#L1382-1 assume !(0 == ~T9_E~0); 8996#L1387-1 assume !(0 == ~T10_E~0); 9723#L1392-1 assume !(0 == ~T11_E~0); 9027#L1397-1 assume !(0 == ~T12_E~0); 9028#L1402-1 assume !(0 == ~T13_E~0); 8680#L1407-1 assume !(0 == ~T14_E~0); 8681#L1412-1 assume 0 == ~E_1~0;~E_1~0 := 1; 9959#L1417-1 assume !(0 == ~E_2~0); 9960#L1422-1 assume !(0 == ~E_3~0); 10201#L1427-1 assume !(0 == ~E_4~0); 8868#L1432-1 assume !(0 == ~E_5~0); 8869#L1437-1 assume !(0 == ~E_6~0); 9877#L1442-1 assume !(0 == ~E_7~0); 9878#L1447-1 assume !(0 == ~E_8~0); 9720#L1452-1 assume 0 == ~E_9~0;~E_9~0 := 1; 8455#L1457-1 assume !(0 == ~E_10~0); 8456#L1462-1 assume !(0 == ~E_11~0); 9912#L1467-1 assume !(0 == ~E_12~0); 9924#L1472-1 assume !(0 == ~E_13~0); 9925#L1477-1 assume !(0 == ~E_14~0); 9667#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8654#L646 assume 1 == ~m_pc~0; 8655#L647 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 9331#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9346#L658 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8744#L1666 assume !(0 != activate_threads_~tmp~1#1); 8745#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10222#L665 assume !(1 == ~t1_pc~0); 9220#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 9221#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8753#L677 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8754#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 9544#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9545#L684 assume 1 == ~t2_pc~0; 9662#L685 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 9586#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9651#L696 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 10046#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 10047#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10235#L703 assume !(1 == ~t3_pc~0); 8890#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 8891#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9537#L715 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 8289#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 8290#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8775#L722 assume 1 == ~t4_pc~0; 9513#L723 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 8956#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9301#L734 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 9861#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 9368#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8486#L741 assume 1 == ~t5_pc~0; 8487#L742 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 8797#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8951#L753 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 8952#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 9631#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9042#L760 assume !(1 == ~t6_pc~0); 8889#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 8888#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8746#L772 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 8747#L1714 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 9468#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9469#L779 assume 1 == ~t7_pc~0; 8531#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 8377#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8378#L791 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 8786#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 8809#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 8810#L798 assume !(1 == ~t8_pc~0); 10091#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 10014#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 8533#L810 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 8534#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 10224#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 8354#L817 assume 1 == ~t9_pc~0; 8355#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 9149#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 9150#L829 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 9672#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 8760#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 8761#L836 assume !(1 == ~t10_pc~0); 8777#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 8708#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 8709#L848 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 8957#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 8958#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 10024#L855 assume 1 == ~t11_pc~0; 9342#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 9343#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 9907#L867 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 9716#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 9551#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 8650#L874 assume !(1 == ~t12_pc~0); 8651#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 8818#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 8819#L886 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 8959#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 8327#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 8328#L893 assume 1 == ~t13_pc~0; 10158#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 8683#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 8994#L905 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 10085#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 10093#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 10094#L912 assume 1 == ~t14_pc~0; 9884#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 9885#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 8653#L924 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 8585#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 8586#L1778-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9361#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 9777#L1495-2 assume !(1 == ~T1_E~0); 9778#L1500-1 assume !(1 == ~T2_E~0); 9464#L1505-1 assume !(1 == ~T3_E~0); 9465#L1510-1 assume !(1 == ~T4_E~0); 9522#L1515-1 assume !(1 == ~T5_E~0); 9523#L1520-1 assume !(1 == ~T6_E~0); 10092#L1525-1 assume !(1 == ~T7_E~0); 9802#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 8755#L1535-1 assume !(1 == ~T9_E~0); 8756#L1540-1 assume !(1 == ~T10_E~0); 8248#L1545-1 assume !(1 == ~T11_E~0); 8249#L1550-1 assume !(1 == ~T12_E~0); 8497#L1555-1 assume !(1 == ~T13_E~0); 8498#L1560-1 assume !(1 == ~T14_E~0); 8798#L1565-1 assume !(1 == ~E_1~0); 10211#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 9689#L1575-1 assume !(1 == ~E_3~0); 9068#L1580-1 assume !(1 == ~E_4~0); 9069#L1585-1 assume !(1 == ~E_5~0); 9539#L1590-1 assume !(1 == ~E_6~0); 9103#L1595-1 assume !(1 == ~E_7~0); 9104#L1600-1 assume !(1 == ~E_8~0); 9476#L1605-1 assume !(1 == ~E_9~0); 9477#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 9994#L1615-1 assume !(1 == ~E_11~0); 8933#L1620-1 assume !(1 == ~E_12~0); 8934#L1625-1 assume !(1 == ~E_13~0); 9721#L1630-1 assume !(1 == ~E_14~0); 9102#L1635-1 assume { :end_inline_reset_delta_events } true; 9043#L2017-2 [2021-12-16 10:06:17,021 INFO L793 eck$LassoCheckResult]: Loop: 9043#L2017-2 assume !false; 8323#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 8324#L1316 assume !false; 9652#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 9714#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 8261#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 8403#L1101 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 8404#L1115 assume !(0 != eval_~tmp~0#1); 9737#L1332 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 9158#L932-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 9159#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 9341#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 9842#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 9511#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 9512#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 10074#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 10249#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 10244#L1372-3 assume !(0 == ~T7_E~0); 8305#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 8306#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 8975#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 8976#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 9887#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 10197#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 9455#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 8611#L1412-3 assume !(0 == ~E_1~0); 8612#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 9376#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 9377#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 10071#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 9758#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 9470#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 9471#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 8371#L1452-3 assume !(0 == ~E_9~0); 8372#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 10010#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 10011#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 9815#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 9816#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 8609#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8610#L646-42 assume 1 == ~m_pc~0; 9195#L647-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 10043#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10044#L658-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 10182#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 10183#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9975#L665-42 assume 1 == ~t1_pc~0; 9936#L666-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 9938#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10124#L677-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8778#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8779#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10248#L684-42 assume 1 == ~t2_pc~0; 9627#L685-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 9628#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10238#L696-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9407#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 9408#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9530#L703-42 assume 1 == ~t3_pc~0; 9728#L704-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 9729#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9047#L715-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 9048#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9822#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9442#L722-42 assume 1 == ~t4_pc~0; 9443#L723-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 9853#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9096#L734-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 8923#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 8924#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10218#L741-42 assume 1 == ~t5_pc~0; 10160#L742-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 9305#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9306#L753-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 10251#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 9213#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9214#L760-42 assume !(1 == ~t6_pc~0); 9348#L760-44 is_transmit6_triggered_~__retres1~6#1 := 0; 9483#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9484#L772-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 9872#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 9165#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9166#L779-42 assume !(1 == ~t7_pc~0); 9942#L779-44 is_transmit7_triggered_~__retres1~7#1 := 0; 9943#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8850#L791-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 8851#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 8706#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 8707#L798-42 assume 1 == ~t8_pc~0; 9157#L799-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 8318#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 10061#L810-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 9507#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 8537#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 8538#L817-42 assume !(1 == ~t9_pc~0); 9312#L817-44 is_transmit9_triggered_~__retres1~9#1 := 0; 8821#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 8822#L829-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 8948#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 9753#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 9754#L836-42 assume 1 == ~t10_pc~0; 9846#L837-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 8859#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 8860#L848-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 10161#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 10162#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 10203#L855-42 assume 1 == ~t11_pc~0; 10216#L856-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 8410#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 8411#L867-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 9160#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 9923#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 9024#L874-42 assume 1 == ~t12_pc~0; 9025#L875-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 9264#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 8325#L886-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 8326#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 8579#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 8580#L893-42 assume 1 == ~t13_pc~0; 9782#L894-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 9564#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 9579#L905-14 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 9481#L1770-42 assume !(0 != activate_threads_~tmp___12~0#1); 8953#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 8954#L912-42 assume !(1 == ~t14_pc~0); 9763#L912-44 is_transmit14_triggered_~__retres1~14#1 := 0; 8271#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 8272#L924-14 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 9852#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 8699#L1778-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8700#L1495-3 assume !(1 == ~M_E~0); 9315#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9743#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9836#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8929#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8892#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 8893#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 9550#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 9773#L1530-3 assume !(1 == ~T8_E~0); 8738#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 8739#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 8776#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 10033#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 10142#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 9182#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 9183#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 9798#L1570-3 assume !(1 == ~E_2~0); 9749#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 9750#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 10105#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 10149#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 10195#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 9572#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 9573#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 10048#L1610-3 assume !(1 == ~E_10~0); 8935#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 8936#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 9540#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 9541#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 9445#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 8876#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 8481#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 9219#L1101-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 9775#L2036 assume !(0 == start_simulation_~tmp~3#1); 9776#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 9928#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 9088#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 10106#L1101-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 9488#L1991 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 9489#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 10209#L1999 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 10210#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 9043#L2017-2 [2021-12-16 10:06:17,023 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:17,023 INFO L85 PathProgramCache]: Analyzing trace with hash -1949208090, now seen corresponding path program 1 times [2021-12-16 10:06:17,023 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:17,024 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [30103708] [2021-12-16 10:06:17,024 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:17,024 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:17,042 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:06:17,072 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:06:17,072 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:06:17,073 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [30103708] [2021-12-16 10:06:17,073 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [30103708] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:06:17,073 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:06:17,073 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:06:17,074 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2020731678] [2021-12-16 10:06:17,074 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:06:17,074 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:06:17,074 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:17,075 INFO L85 PathProgramCache]: Analyzing trace with hash -812799539, now seen corresponding path program 1 times [2021-12-16 10:06:17,075 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:17,075 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [647481754] [2021-12-16 10:06:17,075 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:17,076 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:17,101 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:06:17,140 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:06:17,141 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:06:17,141 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [647481754] [2021-12-16 10:06:17,141 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [647481754] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:06:17,141 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:06:17,141 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:06:17,142 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [883513191] [2021-12-16 10:06:17,142 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:06:17,142 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:06:17,142 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:06:17,143 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-16 10:06:17,143 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-16 10:06:17,143 INFO L87 Difference]: Start difference. First operand 2047 states and 3033 transitions. cyclomatic complexity: 987 Second operand has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:17,169 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:06:17,170 INFO L93 Difference]: Finished difference Result 2047 states and 3032 transitions. [2021-12-16 10:06:17,170 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-16 10:06:17,171 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2047 states and 3032 transitions. [2021-12-16 10:06:17,180 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2021-12-16 10:06:17,187 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2047 states to 2047 states and 3032 transitions. [2021-12-16 10:06:17,188 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2047 [2021-12-16 10:06:17,189 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2047 [2021-12-16 10:06:17,189 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2047 states and 3032 transitions. [2021-12-16 10:06:17,191 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:06:17,192 INFO L681 BuchiCegarLoop]: Abstraction has 2047 states and 3032 transitions. [2021-12-16 10:06:17,193 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2047 states and 3032 transitions. [2021-12-16 10:06:17,208 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2047 to 2047. [2021-12-16 10:06:17,211 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2047 states, 2047 states have (on average 1.4811919882755251) internal successors, (3032), 2046 states have internal predecessors, (3032), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:17,216 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2047 states to 2047 states and 3032 transitions. [2021-12-16 10:06:17,216 INFO L704 BuchiCegarLoop]: Abstraction has 2047 states and 3032 transitions. [2021-12-16 10:06:17,216 INFO L587 BuchiCegarLoop]: Abstraction has 2047 states and 3032 transitions. [2021-12-16 10:06:17,216 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2021-12-16 10:06:17,216 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2047 states and 3032 transitions. [2021-12-16 10:06:17,223 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2021-12-16 10:06:17,223 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:06:17,224 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:06:17,225 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:17,225 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:17,226 INFO L791 eck$LassoCheckResult]: Stem: 13242#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 13243#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 13845#L1980 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 12962#L932 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12963#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 13208#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 13209#L944-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12936#L949-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 12937#L954-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 14160#L959-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 13512#L964-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 13513#L969-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 14030#L974-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 13422#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 13423#L984-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 12843#L989-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 12844#L994-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 13175#L999-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 13373#L1004-1 assume !(1 == ~t14_i~0);~t14_st~0 := 2; 12420#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12421#L1342 assume !(0 == ~M_E~0); 12586#L1342-2 assume !(0 == ~T1_E~0); 13142#L1347-1 assume !(0 == ~T2_E~0); 14143#L1352-1 assume !(0 == ~T3_E~0); 13939#L1357-1 assume !(0 == ~T4_E~0); 13167#L1362-1 assume !(0 == ~T5_E~0); 13168#L1367-1 assume !(0 == ~T6_E~0); 12765#L1372-1 assume 0 == ~T7_E~0;~T7_E~0 := 1; 12766#L1377-1 assume !(0 == ~T8_E~0); 13096#L1382-1 assume !(0 == ~T9_E~0); 13097#L1387-1 assume !(0 == ~T10_E~0); 13824#L1392-1 assume !(0 == ~T11_E~0); 13128#L1397-1 assume !(0 == ~T12_E~0); 13129#L1402-1 assume !(0 == ~T13_E~0); 12781#L1407-1 assume !(0 == ~T14_E~0); 12782#L1412-1 assume 0 == ~E_1~0;~E_1~0 := 1; 14060#L1417-1 assume !(0 == ~E_2~0); 14061#L1422-1 assume !(0 == ~E_3~0); 14302#L1427-1 assume !(0 == ~E_4~0); 12969#L1432-1 assume !(0 == ~E_5~0); 12970#L1437-1 assume !(0 == ~E_6~0); 13978#L1442-1 assume !(0 == ~E_7~0); 13979#L1447-1 assume !(0 == ~E_8~0); 13821#L1452-1 assume 0 == ~E_9~0;~E_9~0 := 1; 12556#L1457-1 assume !(0 == ~E_10~0); 12557#L1462-1 assume !(0 == ~E_11~0); 14013#L1467-1 assume !(0 == ~E_12~0); 14025#L1472-1 assume !(0 == ~E_13~0); 14026#L1477-1 assume !(0 == ~E_14~0); 13768#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12755#L646 assume 1 == ~m_pc~0; 12756#L647 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 13432#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13447#L658 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12845#L1666 assume !(0 != activate_threads_~tmp~1#1); 12846#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14323#L665 assume !(1 == ~t1_pc~0); 13321#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 13322#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12854#L677 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12855#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 13645#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13646#L684 assume 1 == ~t2_pc~0; 13763#L685 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 13687#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13752#L696 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 14147#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 14148#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14336#L703 assume !(1 == ~t3_pc~0); 12991#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 12992#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13638#L715 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 12390#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 12391#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12876#L722 assume 1 == ~t4_pc~0; 13614#L723 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 13057#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13402#L734 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 13962#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 13469#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12587#L741 assume 1 == ~t5_pc~0; 12588#L742 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12898#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13052#L753 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 13053#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 13732#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 13143#L760 assume !(1 == ~t6_pc~0); 12990#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 12989#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12847#L772 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 12848#L1714 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 13569#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 13570#L779 assume 1 == ~t7_pc~0; 12632#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 12478#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12479#L791 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 12887#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 12910#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12911#L798 assume !(1 == ~t8_pc~0); 14192#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 14115#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12634#L810 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 12635#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 14325#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 12455#L817 assume 1 == ~t9_pc~0; 12456#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 13250#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 13251#L829 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 13773#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 12861#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 12862#L836 assume !(1 == ~t10_pc~0); 12878#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 12809#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 12810#L848 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 13058#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 13059#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 14125#L855 assume 1 == ~t11_pc~0; 13443#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 13444#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 14008#L867 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 13817#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 13652#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 12751#L874 assume !(1 == ~t12_pc~0); 12752#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 12919#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 12920#L886 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 13060#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 12428#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 12429#L893 assume 1 == ~t13_pc~0; 14259#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 12784#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 13095#L905 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 14186#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 14194#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 14195#L912 assume 1 == ~t14_pc~0; 13985#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 13986#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 12754#L924 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 12686#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 12687#L1778-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13462#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 13878#L1495-2 assume !(1 == ~T1_E~0); 13879#L1500-1 assume !(1 == ~T2_E~0); 13565#L1505-1 assume !(1 == ~T3_E~0); 13566#L1510-1 assume !(1 == ~T4_E~0); 13623#L1515-1 assume !(1 == ~T5_E~0); 13624#L1520-1 assume !(1 == ~T6_E~0); 14193#L1525-1 assume !(1 == ~T7_E~0); 13903#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 12856#L1535-1 assume !(1 == ~T9_E~0); 12857#L1540-1 assume !(1 == ~T10_E~0); 12349#L1545-1 assume !(1 == ~T11_E~0); 12350#L1550-1 assume !(1 == ~T12_E~0); 12598#L1555-1 assume !(1 == ~T13_E~0); 12599#L1560-1 assume !(1 == ~T14_E~0); 12899#L1565-1 assume !(1 == ~E_1~0); 14312#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 13790#L1575-1 assume !(1 == ~E_3~0); 13169#L1580-1 assume !(1 == ~E_4~0); 13170#L1585-1 assume !(1 == ~E_5~0); 13640#L1590-1 assume !(1 == ~E_6~0); 13204#L1595-1 assume !(1 == ~E_7~0); 13205#L1600-1 assume !(1 == ~E_8~0); 13577#L1605-1 assume !(1 == ~E_9~0); 13578#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 14095#L1615-1 assume !(1 == ~E_11~0); 13034#L1620-1 assume !(1 == ~E_12~0); 13035#L1625-1 assume !(1 == ~E_13~0); 13822#L1630-1 assume !(1 == ~E_14~0); 13203#L1635-1 assume { :end_inline_reset_delta_events } true; 13144#L2017-2 [2021-12-16 10:06:17,226 INFO L793 eck$LassoCheckResult]: Loop: 13144#L2017-2 assume !false; 12424#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 12425#L1316 assume !false; 13753#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 13815#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 12362#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 12504#L1101 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 12505#L1115 assume !(0 != eval_~tmp~0#1); 13838#L1332 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 13259#L932-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 13260#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 13442#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 13943#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 13612#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 13613#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 14175#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 14350#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 14345#L1372-3 assume !(0 == ~T7_E~0); 12406#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 12407#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 13076#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 13077#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 13988#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 14298#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 13556#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 12712#L1412-3 assume !(0 == ~E_1~0); 12713#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 13477#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 13478#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 14172#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 13859#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 13571#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 13572#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 12472#L1452-3 assume !(0 == ~E_9~0); 12473#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 14111#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 14112#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 13916#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 13917#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 12710#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12711#L646-42 assume 1 == ~m_pc~0; 13296#L647-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 14144#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14145#L658-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 14283#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 14284#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14076#L665-42 assume 1 == ~t1_pc~0; 14037#L666-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 14039#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14225#L677-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12879#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 12880#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14349#L684-42 assume 1 == ~t2_pc~0; 13728#L685-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 13729#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14339#L696-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 13508#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 13509#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 13631#L703-42 assume 1 == ~t3_pc~0; 13829#L704-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 13830#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13148#L715-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 13149#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 13923#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13543#L722-42 assume 1 == ~t4_pc~0; 13544#L723-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 13954#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13197#L734-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 13024#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 13025#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14319#L741-42 assume !(1 == ~t5_pc~0); 13936#L741-44 is_transmit5_triggered_~__retres1~5#1 := 0; 13406#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13407#L753-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 14352#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 13314#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 13315#L760-42 assume !(1 == ~t6_pc~0); 13449#L760-44 is_transmit6_triggered_~__retres1~6#1 := 0; 13584#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 13585#L772-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 13973#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 13266#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 13267#L779-42 assume 1 == ~t7_pc~0; 14096#L780-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 14044#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12951#L791-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 12952#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 12807#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12808#L798-42 assume !(1 == ~t8_pc~0); 12418#L798-44 is_transmit8_triggered_~__retres1~8#1 := 0; 12419#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 14162#L810-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 13608#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 12638#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 12639#L817-42 assume 1 == ~t9_pc~0; 13412#L818-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 12922#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 12923#L829-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 13049#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 13854#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 13855#L836-42 assume 1 == ~t10_pc~0; 13947#L837-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 12960#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 12961#L848-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 14262#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 14263#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 14304#L855-42 assume 1 == ~t11_pc~0; 14317#L856-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 12511#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 12512#L867-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 13261#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 14024#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 13125#L874-42 assume 1 == ~t12_pc~0; 13126#L875-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 13365#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 12426#L886-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 12427#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 12680#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 12681#L893-42 assume !(1 == ~t13_pc~0); 13664#L893-44 is_transmit13_triggered_~__retres1~13#1 := 0; 13665#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 13680#L905-14 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 13582#L1770-42 assume !(0 != activate_threads_~tmp___12~0#1); 13054#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 13055#L912-42 assume !(1 == ~t14_pc~0); 13864#L912-44 is_transmit14_triggered_~__retres1~14#1 := 0; 12372#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 12373#L924-14 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 13953#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 12800#L1778-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12801#L1495-3 assume !(1 == ~M_E~0); 13416#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 13844#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 13937#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 13030#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12993#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 12994#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 13651#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 13874#L1530-3 assume !(1 == ~T8_E~0); 12839#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 12840#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 12877#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 14134#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 14243#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 13283#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 13284#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 13899#L1570-3 assume !(1 == ~E_2~0); 13850#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 13851#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 14206#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 14250#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 14296#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 13673#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 13674#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 14149#L1610-3 assume !(1 == ~E_10~0); 13036#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 13037#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 13641#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 13642#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 13546#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 12977#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 12582#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 13320#L1101-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 13876#L2036 assume !(0 == start_simulation_~tmp~3#1); 13877#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 14029#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 13189#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 14207#L1101-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 13589#L1991 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 13590#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 14310#L1999 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 14311#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 13144#L2017-2 [2021-12-16 10:06:17,227 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:17,227 INFO L85 PathProgramCache]: Analyzing trace with hash -224599768, now seen corresponding path program 1 times [2021-12-16 10:06:17,228 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:17,228 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1820529718] [2021-12-16 10:06:17,228 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:17,229 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:17,263 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:06:17,281 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:06:17,282 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:06:17,282 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1820529718] [2021-12-16 10:06:17,283 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1820529718] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:06:17,283 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:06:17,283 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:06:17,285 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1197276117] [2021-12-16 10:06:17,285 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:06:17,286 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:06:17,286 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:17,286 INFO L85 PathProgramCache]: Analyzing trace with hash -1715277972, now seen corresponding path program 1 times [2021-12-16 10:06:17,287 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:17,290 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [624162077] [2021-12-16 10:06:17,290 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:17,290 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:17,307 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:06:17,328 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:06:17,329 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:06:17,329 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [624162077] [2021-12-16 10:06:17,330 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [624162077] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:06:17,330 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:06:17,331 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:06:17,331 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1894965618] [2021-12-16 10:06:17,331 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:06:17,331 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:06:17,331 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:06:17,332 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-16 10:06:17,332 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-16 10:06:17,333 INFO L87 Difference]: Start difference. First operand 2047 states and 3032 transitions. cyclomatic complexity: 986 Second operand has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:17,357 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:06:17,357 INFO L93 Difference]: Finished difference Result 2047 states and 3031 transitions. [2021-12-16 10:06:17,358 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-16 10:06:17,358 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2047 states and 3031 transitions. [2021-12-16 10:06:17,368 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2021-12-16 10:06:17,375 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2047 states to 2047 states and 3031 transitions. [2021-12-16 10:06:17,375 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2047 [2021-12-16 10:06:17,376 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2047 [2021-12-16 10:06:17,376 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2047 states and 3031 transitions. [2021-12-16 10:06:17,378 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:06:17,378 INFO L681 BuchiCegarLoop]: Abstraction has 2047 states and 3031 transitions. [2021-12-16 10:06:17,380 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2047 states and 3031 transitions. [2021-12-16 10:06:17,394 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2047 to 2047. [2021-12-16 10:06:17,397 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2047 states, 2047 states have (on average 1.4807034684904739) internal successors, (3031), 2046 states have internal predecessors, (3031), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:17,402 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2047 states to 2047 states and 3031 transitions. [2021-12-16 10:06:17,403 INFO L704 BuchiCegarLoop]: Abstraction has 2047 states and 3031 transitions. [2021-12-16 10:06:17,403 INFO L587 BuchiCegarLoop]: Abstraction has 2047 states and 3031 transitions. [2021-12-16 10:06:17,403 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2021-12-16 10:06:17,403 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2047 states and 3031 transitions. [2021-12-16 10:06:17,409 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2021-12-16 10:06:17,409 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:06:17,409 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:06:17,410 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:17,410 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:17,411 INFO L791 eck$LassoCheckResult]: Stem: 17343#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 17344#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 17946#L1980 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 17063#L932 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 17064#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 17309#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 17310#L944-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 17037#L949-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 17038#L954-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 18261#L959-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 17613#L964-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 17614#L969-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 18131#L974-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 17523#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 17524#L984-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 16944#L989-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 16945#L994-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 17276#L999-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 17474#L1004-1 assume !(1 == ~t14_i~0);~t14_st~0 := 2; 16521#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 16522#L1342 assume !(0 == ~M_E~0); 16687#L1342-2 assume !(0 == ~T1_E~0); 17243#L1347-1 assume !(0 == ~T2_E~0); 18244#L1352-1 assume !(0 == ~T3_E~0); 18040#L1357-1 assume !(0 == ~T4_E~0); 17268#L1362-1 assume !(0 == ~T5_E~0); 17269#L1367-1 assume !(0 == ~T6_E~0); 16866#L1372-1 assume 0 == ~T7_E~0;~T7_E~0 := 1; 16867#L1377-1 assume !(0 == ~T8_E~0); 17197#L1382-1 assume !(0 == ~T9_E~0); 17198#L1387-1 assume !(0 == ~T10_E~0); 17925#L1392-1 assume !(0 == ~T11_E~0); 17229#L1397-1 assume !(0 == ~T12_E~0); 17230#L1402-1 assume !(0 == ~T13_E~0); 16882#L1407-1 assume !(0 == ~T14_E~0); 16883#L1412-1 assume 0 == ~E_1~0;~E_1~0 := 1; 18161#L1417-1 assume !(0 == ~E_2~0); 18162#L1422-1 assume !(0 == ~E_3~0); 18403#L1427-1 assume !(0 == ~E_4~0); 17070#L1432-1 assume !(0 == ~E_5~0); 17071#L1437-1 assume !(0 == ~E_6~0); 18079#L1442-1 assume !(0 == ~E_7~0); 18080#L1447-1 assume !(0 == ~E_8~0); 17922#L1452-1 assume 0 == ~E_9~0;~E_9~0 := 1; 16657#L1457-1 assume !(0 == ~E_10~0); 16658#L1462-1 assume !(0 == ~E_11~0); 18114#L1467-1 assume !(0 == ~E_12~0); 18126#L1472-1 assume !(0 == ~E_13~0); 18127#L1477-1 assume !(0 == ~E_14~0); 17869#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16856#L646 assume 1 == ~m_pc~0; 16857#L647 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 17533#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 17548#L658 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 16946#L1666 assume !(0 != activate_threads_~tmp~1#1); 16947#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 18424#L665 assume !(1 == ~t1_pc~0); 17422#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 17423#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16955#L677 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 16956#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 17746#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 17747#L684 assume 1 == ~t2_pc~0; 17864#L685 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 17788#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17853#L696 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 18248#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 18249#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18437#L703 assume !(1 == ~t3_pc~0); 17092#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 17093#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 17739#L715 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 16491#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 16492#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16977#L722 assume 1 == ~t4_pc~0; 17715#L723 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 17158#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 17503#L734 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 18063#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 17570#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16688#L741 assume 1 == ~t5_pc~0; 16689#L742 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 16999#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 17153#L753 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 17154#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 17833#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 17244#L760 assume !(1 == ~t6_pc~0); 17091#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 17090#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 16948#L772 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 16949#L1714 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 17670#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 17671#L779 assume 1 == ~t7_pc~0; 16733#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 16579#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16580#L791 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 16988#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 17011#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 17012#L798 assume !(1 == ~t8_pc~0); 18293#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 18216#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 16735#L810 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 16736#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 18426#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 16556#L817 assume 1 == ~t9_pc~0; 16557#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 17351#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 17352#L829 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 17874#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 16962#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 16963#L836 assume !(1 == ~t10_pc~0); 16979#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 16910#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 16911#L848 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 17159#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 17160#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 18226#L855 assume 1 == ~t11_pc~0; 17544#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 17545#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 18109#L867 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 17918#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 17753#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 16852#L874 assume !(1 == ~t12_pc~0); 16853#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 17020#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 17021#L886 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 17161#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 16529#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 16530#L893 assume 1 == ~t13_pc~0; 18360#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 16885#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 17196#L905 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 18287#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 18295#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 18296#L912 assume 1 == ~t14_pc~0; 18086#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 18087#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 16855#L924 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 16787#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 16788#L1778-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17563#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 17979#L1495-2 assume !(1 == ~T1_E~0); 17980#L1500-1 assume !(1 == ~T2_E~0); 17666#L1505-1 assume !(1 == ~T3_E~0); 17667#L1510-1 assume !(1 == ~T4_E~0); 17724#L1515-1 assume !(1 == ~T5_E~0); 17725#L1520-1 assume !(1 == ~T6_E~0); 18294#L1525-1 assume !(1 == ~T7_E~0); 18004#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 16957#L1535-1 assume !(1 == ~T9_E~0); 16958#L1540-1 assume !(1 == ~T10_E~0); 16450#L1545-1 assume !(1 == ~T11_E~0); 16451#L1550-1 assume !(1 == ~T12_E~0); 16699#L1555-1 assume !(1 == ~T13_E~0); 16700#L1560-1 assume !(1 == ~T14_E~0); 17000#L1565-1 assume !(1 == ~E_1~0); 18413#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 17891#L1575-1 assume !(1 == ~E_3~0); 17270#L1580-1 assume !(1 == ~E_4~0); 17271#L1585-1 assume !(1 == ~E_5~0); 17741#L1590-1 assume !(1 == ~E_6~0); 17305#L1595-1 assume !(1 == ~E_7~0); 17306#L1600-1 assume !(1 == ~E_8~0); 17678#L1605-1 assume !(1 == ~E_9~0); 17679#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 18196#L1615-1 assume !(1 == ~E_11~0); 17135#L1620-1 assume !(1 == ~E_12~0); 17136#L1625-1 assume !(1 == ~E_13~0); 17923#L1630-1 assume !(1 == ~E_14~0); 17304#L1635-1 assume { :end_inline_reset_delta_events } true; 17245#L2017-2 [2021-12-16 10:06:17,411 INFO L793 eck$LassoCheckResult]: Loop: 17245#L2017-2 assume !false; 16525#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 16526#L1316 assume !false; 17854#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 17916#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 16463#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 16605#L1101 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 16606#L1115 assume !(0 != eval_~tmp~0#1); 17939#L1332 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 17360#L932-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 17361#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 17543#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 18044#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 17713#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 17714#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 18276#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 18451#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 18446#L1372-3 assume !(0 == ~T7_E~0); 16507#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 16508#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 17177#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 17178#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 18089#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 18399#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 17657#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 16813#L1412-3 assume !(0 == ~E_1~0); 16814#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 17578#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 17579#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 18273#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 17960#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 17672#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 17673#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 16573#L1452-3 assume !(0 == ~E_9~0); 16574#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 18212#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 18213#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 18017#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 18018#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 16811#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16812#L646-42 assume 1 == ~m_pc~0; 17397#L647-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 18245#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 18246#L658-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 18384#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 18385#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 18177#L665-42 assume 1 == ~t1_pc~0; 18138#L666-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 18140#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18326#L677-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 16980#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 16981#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18450#L684-42 assume 1 == ~t2_pc~0; 17829#L685-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 17830#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 18440#L696-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 17609#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 17610#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 17732#L703-42 assume 1 == ~t3_pc~0; 17930#L704-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 17931#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 17249#L715-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 17250#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 18024#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 17644#L722-42 assume 1 == ~t4_pc~0; 17645#L723-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 18055#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 17298#L734-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 17125#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 17126#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 18420#L741-42 assume !(1 == ~t5_pc~0); 18037#L741-44 is_transmit5_triggered_~__retres1~5#1 := 0; 17507#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 17508#L753-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 18453#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 17415#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 17416#L760-42 assume !(1 == ~t6_pc~0); 17550#L760-44 is_transmit6_triggered_~__retres1~6#1 := 0; 17685#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 17686#L772-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 18074#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 17367#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 17368#L779-42 assume !(1 == ~t7_pc~0); 18144#L779-44 is_transmit7_triggered_~__retres1~7#1 := 0; 18145#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 17052#L791-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 17053#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 16908#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 16909#L798-42 assume !(1 == ~t8_pc~0); 16519#L798-44 is_transmit8_triggered_~__retres1~8#1 := 0; 16520#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 18263#L810-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 17709#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 16739#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 16740#L817-42 assume 1 == ~t9_pc~0; 17513#L818-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 17023#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 17024#L829-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 17150#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 17955#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 17956#L836-42 assume 1 == ~t10_pc~0; 18048#L837-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 17061#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 17062#L848-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 18363#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 18364#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 18405#L855-42 assume 1 == ~t11_pc~0; 18418#L856-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 16612#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 16613#L867-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 17362#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 18125#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 17226#L874-42 assume 1 == ~t12_pc~0; 17227#L875-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 17466#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 16527#L886-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 16528#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 16781#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 16782#L893-42 assume 1 == ~t13_pc~0; 17984#L894-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 17766#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 17781#L905-14 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 17683#L1770-42 assume !(0 != activate_threads_~tmp___12~0#1); 17155#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 17156#L912-42 assume 1 == ~t14_pc~0; 18400#L913-14 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 16473#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 16474#L924-14 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 18054#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 16901#L1778-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16902#L1495-3 assume !(1 == ~M_E~0); 17517#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 17945#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 18038#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 17131#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 17094#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 17095#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 17752#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 17975#L1530-3 assume !(1 == ~T8_E~0); 16940#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 16941#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 16978#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 18235#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 18344#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 17384#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 17385#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 18000#L1570-3 assume !(1 == ~E_2~0); 17951#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 17952#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 18307#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 18351#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 18397#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 17774#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 17775#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 18250#L1610-3 assume !(1 == ~E_10~0); 17137#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 17138#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 17742#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 17743#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 17647#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 17078#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 16683#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 17421#L1101-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 17977#L2036 assume !(0 == start_simulation_~tmp~3#1); 17978#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 18130#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 17290#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 18308#L1101-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 17690#L1991 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 17691#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 18411#L1999 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 18412#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 17245#L2017-2 [2021-12-16 10:06:17,412 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:17,412 INFO L85 PathProgramCache]: Analyzing trace with hash -723156570, now seen corresponding path program 1 times [2021-12-16 10:06:17,412 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:17,412 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [577251849] [2021-12-16 10:06:17,412 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:17,413 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:17,420 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:06:17,437 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:06:17,437 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:06:17,437 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [577251849] [2021-12-16 10:06:17,437 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [577251849] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:06:17,437 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:06:17,438 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:06:17,438 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2098302128] [2021-12-16 10:06:17,438 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:06:17,438 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:06:17,438 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:17,439 INFO L85 PathProgramCache]: Analyzing trace with hash 1006606669, now seen corresponding path program 1 times [2021-12-16 10:06:17,439 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:17,439 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1932125428] [2021-12-16 10:06:17,439 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:17,439 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:17,449 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:06:17,493 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:06:17,493 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:06:17,494 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1932125428] [2021-12-16 10:06:17,494 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1932125428] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:06:17,494 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:06:17,494 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:06:17,494 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [519068644] [2021-12-16 10:06:17,494 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:06:17,495 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:06:17,495 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:06:17,495 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-16 10:06:17,495 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-16 10:06:17,496 INFO L87 Difference]: Start difference. First operand 2047 states and 3031 transitions. cyclomatic complexity: 985 Second operand has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:17,520 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:06:17,520 INFO L93 Difference]: Finished difference Result 2047 states and 3030 transitions. [2021-12-16 10:06:17,521 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-16 10:06:17,523 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2047 states and 3030 transitions. [2021-12-16 10:06:17,530 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2021-12-16 10:06:17,537 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2047 states to 2047 states and 3030 transitions. [2021-12-16 10:06:17,537 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2047 [2021-12-16 10:06:17,538 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2047 [2021-12-16 10:06:17,538 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2047 states and 3030 transitions. [2021-12-16 10:06:17,540 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:06:17,541 INFO L681 BuchiCegarLoop]: Abstraction has 2047 states and 3030 transitions. [2021-12-16 10:06:17,543 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2047 states and 3030 transitions. [2021-12-16 10:06:17,559 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2047 to 2047. [2021-12-16 10:06:17,561 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2047 states, 2047 states have (on average 1.4802149487054226) internal successors, (3030), 2046 states have internal predecessors, (3030), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:17,566 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2047 states to 2047 states and 3030 transitions. [2021-12-16 10:06:17,566 INFO L704 BuchiCegarLoop]: Abstraction has 2047 states and 3030 transitions. [2021-12-16 10:06:17,566 INFO L587 BuchiCegarLoop]: Abstraction has 2047 states and 3030 transitions. [2021-12-16 10:06:17,566 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2021-12-16 10:06:17,566 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2047 states and 3030 transitions. [2021-12-16 10:06:17,572 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2021-12-16 10:06:17,572 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:06:17,572 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:06:17,574 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:17,574 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:17,575 INFO L791 eck$LassoCheckResult]: Stem: 21444#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 21445#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 22047#L1980 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 21164#L932 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 21165#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 21410#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 21411#L944-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 21138#L949-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 21139#L954-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 22362#L959-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 21714#L964-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 21715#L969-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 22232#L974-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 21624#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 21625#L984-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 21045#L989-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 21046#L994-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 21377#L999-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 21575#L1004-1 assume !(1 == ~t14_i~0);~t14_st~0 := 2; 20622#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 20623#L1342 assume !(0 == ~M_E~0); 20788#L1342-2 assume !(0 == ~T1_E~0); 21344#L1347-1 assume !(0 == ~T2_E~0); 22345#L1352-1 assume !(0 == ~T3_E~0); 22141#L1357-1 assume !(0 == ~T4_E~0); 21369#L1362-1 assume !(0 == ~T5_E~0); 21370#L1367-1 assume !(0 == ~T6_E~0); 20967#L1372-1 assume 0 == ~T7_E~0;~T7_E~0 := 1; 20968#L1377-1 assume !(0 == ~T8_E~0); 21298#L1382-1 assume !(0 == ~T9_E~0); 21299#L1387-1 assume !(0 == ~T10_E~0); 22026#L1392-1 assume !(0 == ~T11_E~0); 21330#L1397-1 assume !(0 == ~T12_E~0); 21331#L1402-1 assume !(0 == ~T13_E~0); 20983#L1407-1 assume !(0 == ~T14_E~0); 20984#L1412-1 assume 0 == ~E_1~0;~E_1~0 := 1; 22262#L1417-1 assume !(0 == ~E_2~0); 22263#L1422-1 assume !(0 == ~E_3~0); 22504#L1427-1 assume !(0 == ~E_4~0); 21171#L1432-1 assume !(0 == ~E_5~0); 21172#L1437-1 assume !(0 == ~E_6~0); 22180#L1442-1 assume !(0 == ~E_7~0); 22181#L1447-1 assume !(0 == ~E_8~0); 22023#L1452-1 assume 0 == ~E_9~0;~E_9~0 := 1; 20758#L1457-1 assume !(0 == ~E_10~0); 20759#L1462-1 assume !(0 == ~E_11~0); 22215#L1467-1 assume !(0 == ~E_12~0); 22227#L1472-1 assume !(0 == ~E_13~0); 22228#L1477-1 assume !(0 == ~E_14~0); 21970#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20957#L646 assume 1 == ~m_pc~0; 20958#L647 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 21634#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21649#L658 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 21047#L1666 assume !(0 != activate_threads_~tmp~1#1); 21048#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 22525#L665 assume !(1 == ~t1_pc~0); 21523#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 21524#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 21056#L677 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 21057#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 21847#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 21848#L684 assume 1 == ~t2_pc~0; 21965#L685 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 21889#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 21954#L696 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 22349#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 22350#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22538#L703 assume !(1 == ~t3_pc~0); 21193#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 21194#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 21840#L715 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 20592#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 20593#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 21078#L722 assume 1 == ~t4_pc~0; 21816#L723 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 21259#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 21604#L734 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 22164#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 21671#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 20789#L741 assume 1 == ~t5_pc~0; 20790#L742 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 21100#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 21254#L753 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 21255#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 21934#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 21345#L760 assume !(1 == ~t6_pc~0); 21192#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 21191#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 21049#L772 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 21050#L1714 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 21771#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 21772#L779 assume 1 == ~t7_pc~0; 20834#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 20680#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 20681#L791 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 21089#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 21112#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 21113#L798 assume !(1 == ~t8_pc~0); 22394#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 22317#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 20836#L810 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 20837#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 22527#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 20657#L817 assume 1 == ~t9_pc~0; 20658#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 21452#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 21453#L829 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 21975#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 21063#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 21064#L836 assume !(1 == ~t10_pc~0); 21080#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 21011#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 21012#L848 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 21260#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 21261#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 22327#L855 assume 1 == ~t11_pc~0; 21645#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 21646#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 22210#L867 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 22019#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 21854#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 20953#L874 assume !(1 == ~t12_pc~0); 20954#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 21121#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 21122#L886 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 21262#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 20630#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 20631#L893 assume 1 == ~t13_pc~0; 22461#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 20986#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 21297#L905 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 22388#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 22396#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 22397#L912 assume 1 == ~t14_pc~0; 22187#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 22188#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 20956#L924 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 20888#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 20889#L1778-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21664#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 22080#L1495-2 assume !(1 == ~T1_E~0); 22081#L1500-1 assume !(1 == ~T2_E~0); 21767#L1505-1 assume !(1 == ~T3_E~0); 21768#L1510-1 assume !(1 == ~T4_E~0); 21825#L1515-1 assume !(1 == ~T5_E~0); 21826#L1520-1 assume !(1 == ~T6_E~0); 22395#L1525-1 assume !(1 == ~T7_E~0); 22105#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 21058#L1535-1 assume !(1 == ~T9_E~0); 21059#L1540-1 assume !(1 == ~T10_E~0); 20551#L1545-1 assume !(1 == ~T11_E~0); 20552#L1550-1 assume !(1 == ~T12_E~0); 20800#L1555-1 assume !(1 == ~T13_E~0); 20801#L1560-1 assume !(1 == ~T14_E~0); 21101#L1565-1 assume !(1 == ~E_1~0); 22514#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 21992#L1575-1 assume !(1 == ~E_3~0); 21371#L1580-1 assume !(1 == ~E_4~0); 21372#L1585-1 assume !(1 == ~E_5~0); 21842#L1590-1 assume !(1 == ~E_6~0); 21406#L1595-1 assume !(1 == ~E_7~0); 21407#L1600-1 assume !(1 == ~E_8~0); 21779#L1605-1 assume !(1 == ~E_9~0); 21780#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 22297#L1615-1 assume !(1 == ~E_11~0); 21236#L1620-1 assume !(1 == ~E_12~0); 21237#L1625-1 assume !(1 == ~E_13~0); 22024#L1630-1 assume !(1 == ~E_14~0); 21405#L1635-1 assume { :end_inline_reset_delta_events } true; 21346#L2017-2 [2021-12-16 10:06:17,575 INFO L793 eck$LassoCheckResult]: Loop: 21346#L2017-2 assume !false; 20626#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 20627#L1316 assume !false; 21955#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 22017#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 20564#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 20706#L1101 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 20707#L1115 assume !(0 != eval_~tmp~0#1); 22040#L1332 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 21461#L932-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 21462#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 21644#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 22145#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 21814#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 21815#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 22377#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 22552#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 22547#L1372-3 assume !(0 == ~T7_E~0); 20608#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 20609#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 21278#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 21279#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 22190#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 22500#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 21758#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 20914#L1412-3 assume !(0 == ~E_1~0); 20915#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 21679#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 21680#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 22374#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 22061#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 21773#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 21774#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 20674#L1452-3 assume !(0 == ~E_9~0); 20675#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 22313#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 22314#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 22118#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 22119#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 20912#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20913#L646-42 assume 1 == ~m_pc~0; 21498#L647-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 22346#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 22347#L658-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 22485#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 22486#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 22278#L665-42 assume !(1 == ~t1_pc~0); 22240#L665-44 is_transmit1_triggered_~__retres1~1#1 := 0; 22241#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22427#L677-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 21081#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 21082#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22551#L684-42 assume 1 == ~t2_pc~0; 21930#L685-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 21931#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 22541#L696-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 21710#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 21711#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 21833#L703-42 assume !(1 == ~t3_pc~0); 22033#L703-44 is_transmit3_triggered_~__retres1~3#1 := 0; 22032#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 21350#L715-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 21351#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 22125#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 21745#L722-42 assume 1 == ~t4_pc~0; 21746#L723-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 22156#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 21399#L734-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 21226#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 21227#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 22521#L741-42 assume !(1 == ~t5_pc~0); 22138#L741-44 is_transmit5_triggered_~__retres1~5#1 := 0; 21608#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 21609#L753-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 22554#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 21516#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 21517#L760-42 assume !(1 == ~t6_pc~0); 21651#L760-44 is_transmit6_triggered_~__retres1~6#1 := 0; 21786#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 21787#L772-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 22175#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 21468#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 21469#L779-42 assume !(1 == ~t7_pc~0); 22245#L779-44 is_transmit7_triggered_~__retres1~7#1 := 0; 22246#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 21153#L791-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 21154#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 21009#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 21010#L798-42 assume 1 == ~t8_pc~0; 21460#L799-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 20621#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 22364#L810-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 21810#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 20840#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 20841#L817-42 assume 1 == ~t9_pc~0; 21614#L818-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 21124#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 21125#L829-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 21251#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 22056#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 22057#L836-42 assume 1 == ~t10_pc~0; 22149#L837-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 21162#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 21163#L848-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 22464#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 22465#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 22506#L855-42 assume 1 == ~t11_pc~0; 22519#L856-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 20713#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 20714#L867-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 21463#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 22226#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 21327#L874-42 assume 1 == ~t12_pc~0; 21328#L875-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 21567#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 20628#L886-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 20629#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 20882#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 20883#L893-42 assume 1 == ~t13_pc~0; 22085#L894-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 21867#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 21882#L905-14 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 21784#L1770-42 assume !(0 != activate_threads_~tmp___12~0#1); 21256#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 21257#L912-42 assume !(1 == ~t14_pc~0); 22066#L912-44 is_transmit14_triggered_~__retres1~14#1 := 0; 20574#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 20575#L924-14 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 22155#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 21002#L1778-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21003#L1495-3 assume !(1 == ~M_E~0); 21618#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 22046#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 22139#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 21232#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 21195#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 21196#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 21853#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 22076#L1530-3 assume !(1 == ~T8_E~0); 21041#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 21042#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 21079#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 22336#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 22445#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 21485#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 21486#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 22101#L1570-3 assume !(1 == ~E_2~0); 22052#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 22053#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 22408#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 22452#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 22498#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 21875#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 21876#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 22351#L1610-3 assume !(1 == ~E_10~0); 21238#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 21239#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 21843#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 21844#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 21748#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 21179#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 20784#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 21522#L1101-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 22078#L2036 assume !(0 == start_simulation_~tmp~3#1); 22079#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 22231#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 21391#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 22409#L1101-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 21791#L1991 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 21792#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 22512#L1999 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 22513#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 21346#L2017-2 [2021-12-16 10:06:17,576 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:17,576 INFO L85 PathProgramCache]: Analyzing trace with hash -1293428376, now seen corresponding path program 1 times [2021-12-16 10:06:17,576 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:17,577 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1727964345] [2021-12-16 10:06:17,577 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:17,577 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:17,588 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:06:17,601 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:06:17,602 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:06:17,602 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1727964345] [2021-12-16 10:06:17,602 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1727964345] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:06:17,602 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:06:17,602 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:06:17,602 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1931733247] [2021-12-16 10:06:17,603 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:06:17,604 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:06:17,606 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:17,606 INFO L85 PathProgramCache]: Analyzing trace with hash 721372171, now seen corresponding path program 1 times [2021-12-16 10:06:17,606 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:17,609 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1804039259] [2021-12-16 10:06:17,609 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:17,609 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:17,619 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:06:17,640 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:06:17,640 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:06:17,642 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1804039259] [2021-12-16 10:06:17,642 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1804039259] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:06:17,642 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:06:17,642 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:06:17,642 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2068304017] [2021-12-16 10:06:17,642 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:06:17,643 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:06:17,643 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:06:17,644 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-16 10:06:17,644 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-16 10:06:17,644 INFO L87 Difference]: Start difference. First operand 2047 states and 3030 transitions. cyclomatic complexity: 984 Second operand has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:17,669 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:06:17,669 INFO L93 Difference]: Finished difference Result 2047 states and 3029 transitions. [2021-12-16 10:06:17,670 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-16 10:06:17,671 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2047 states and 3029 transitions. [2021-12-16 10:06:17,678 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2021-12-16 10:06:17,685 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2047 states to 2047 states and 3029 transitions. [2021-12-16 10:06:17,686 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2047 [2021-12-16 10:06:17,688 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2047 [2021-12-16 10:06:17,688 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2047 states and 3029 transitions. [2021-12-16 10:06:17,690 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:06:17,690 INFO L681 BuchiCegarLoop]: Abstraction has 2047 states and 3029 transitions. [2021-12-16 10:06:17,692 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2047 states and 3029 transitions. [2021-12-16 10:06:17,715 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2047 to 2047. [2021-12-16 10:06:17,718 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2047 states, 2047 states have (on average 1.4797264289203713) internal successors, (3029), 2046 states have internal predecessors, (3029), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:17,723 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2047 states to 2047 states and 3029 transitions. [2021-12-16 10:06:17,723 INFO L704 BuchiCegarLoop]: Abstraction has 2047 states and 3029 transitions. [2021-12-16 10:06:17,723 INFO L587 BuchiCegarLoop]: Abstraction has 2047 states and 3029 transitions. [2021-12-16 10:06:17,724 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2021-12-16 10:06:17,724 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2047 states and 3029 transitions. [2021-12-16 10:06:17,728 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2021-12-16 10:06:17,729 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:06:17,729 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:06:17,730 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:17,730 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:17,731 INFO L791 eck$LassoCheckResult]: Stem: 25545#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 25546#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 26148#L1980 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 25265#L932 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 25266#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 25511#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 25512#L944-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 25239#L949-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 25240#L954-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 26463#L959-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 25815#L964-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 25816#L969-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 26333#L974-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 25725#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 25726#L984-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 25146#L989-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 25147#L994-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 25478#L999-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 25676#L1004-1 assume !(1 == ~t14_i~0);~t14_st~0 := 2; 24723#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 24724#L1342 assume !(0 == ~M_E~0); 24889#L1342-2 assume !(0 == ~T1_E~0); 25445#L1347-1 assume !(0 == ~T2_E~0); 26446#L1352-1 assume !(0 == ~T3_E~0); 26242#L1357-1 assume !(0 == ~T4_E~0); 25470#L1362-1 assume !(0 == ~T5_E~0); 25471#L1367-1 assume !(0 == ~T6_E~0); 25068#L1372-1 assume 0 == ~T7_E~0;~T7_E~0 := 1; 25069#L1377-1 assume !(0 == ~T8_E~0); 25399#L1382-1 assume !(0 == ~T9_E~0); 25400#L1387-1 assume !(0 == ~T10_E~0); 26127#L1392-1 assume !(0 == ~T11_E~0); 25431#L1397-1 assume !(0 == ~T12_E~0); 25432#L1402-1 assume !(0 == ~T13_E~0); 25084#L1407-1 assume !(0 == ~T14_E~0); 25085#L1412-1 assume 0 == ~E_1~0;~E_1~0 := 1; 26363#L1417-1 assume !(0 == ~E_2~0); 26364#L1422-1 assume !(0 == ~E_3~0); 26605#L1427-1 assume !(0 == ~E_4~0); 25272#L1432-1 assume !(0 == ~E_5~0); 25273#L1437-1 assume !(0 == ~E_6~0); 26281#L1442-1 assume !(0 == ~E_7~0); 26282#L1447-1 assume !(0 == ~E_8~0); 26124#L1452-1 assume 0 == ~E_9~0;~E_9~0 := 1; 24859#L1457-1 assume !(0 == ~E_10~0); 24860#L1462-1 assume !(0 == ~E_11~0); 26316#L1467-1 assume !(0 == ~E_12~0); 26328#L1472-1 assume !(0 == ~E_13~0); 26329#L1477-1 assume !(0 == ~E_14~0); 26071#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 25058#L646 assume 1 == ~m_pc~0; 25059#L647 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 25735#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 25750#L658 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 25148#L1666 assume !(0 != activate_threads_~tmp~1#1); 25149#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26626#L665 assume !(1 == ~t1_pc~0); 25624#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 25625#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 25157#L677 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 25158#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 25948#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 25949#L684 assume 1 == ~t2_pc~0; 26066#L685 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 25990#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 26055#L696 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 26450#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 26451#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 26639#L703 assume !(1 == ~t3_pc~0); 25294#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 25295#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 25941#L715 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 24693#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 24694#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 25179#L722 assume 1 == ~t4_pc~0; 25917#L723 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 25360#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 25705#L734 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 26265#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 25772#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 24890#L741 assume 1 == ~t5_pc~0; 24891#L742 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 25201#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 25355#L753 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 25356#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 26035#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 25446#L760 assume !(1 == ~t6_pc~0); 25293#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 25292#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 25150#L772 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 25151#L1714 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 25872#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 25873#L779 assume 1 == ~t7_pc~0; 24935#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 24781#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 24782#L791 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 25190#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 25213#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 25214#L798 assume !(1 == ~t8_pc~0); 26495#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 26418#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 24937#L810 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 24938#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 26628#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 24758#L817 assume 1 == ~t9_pc~0; 24759#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 25553#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 25554#L829 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 26076#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 25164#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 25165#L836 assume !(1 == ~t10_pc~0); 25181#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 25112#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 25113#L848 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 25361#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 25362#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 26428#L855 assume 1 == ~t11_pc~0; 25746#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 25747#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 26311#L867 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 26120#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 25955#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 25054#L874 assume !(1 == ~t12_pc~0); 25055#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 25222#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 25223#L886 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 25363#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 24731#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 24732#L893 assume 1 == ~t13_pc~0; 26562#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 25087#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 25398#L905 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 26489#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 26497#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 26498#L912 assume 1 == ~t14_pc~0; 26288#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 26289#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 25057#L924 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 24989#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 24990#L1778-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 25765#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 26181#L1495-2 assume !(1 == ~T1_E~0); 26182#L1500-1 assume !(1 == ~T2_E~0); 25868#L1505-1 assume !(1 == ~T3_E~0); 25869#L1510-1 assume !(1 == ~T4_E~0); 25926#L1515-1 assume !(1 == ~T5_E~0); 25927#L1520-1 assume !(1 == ~T6_E~0); 26496#L1525-1 assume !(1 == ~T7_E~0); 26206#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 25159#L1535-1 assume !(1 == ~T9_E~0); 25160#L1540-1 assume !(1 == ~T10_E~0); 24652#L1545-1 assume !(1 == ~T11_E~0); 24653#L1550-1 assume !(1 == ~T12_E~0); 24901#L1555-1 assume !(1 == ~T13_E~0); 24902#L1560-1 assume !(1 == ~T14_E~0); 25202#L1565-1 assume !(1 == ~E_1~0); 26615#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 26093#L1575-1 assume !(1 == ~E_3~0); 25472#L1580-1 assume !(1 == ~E_4~0); 25473#L1585-1 assume !(1 == ~E_5~0); 25943#L1590-1 assume !(1 == ~E_6~0); 25507#L1595-1 assume !(1 == ~E_7~0); 25508#L1600-1 assume !(1 == ~E_8~0); 25880#L1605-1 assume !(1 == ~E_9~0); 25881#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 26398#L1615-1 assume !(1 == ~E_11~0); 25337#L1620-1 assume !(1 == ~E_12~0); 25338#L1625-1 assume !(1 == ~E_13~0); 26125#L1630-1 assume !(1 == ~E_14~0); 25506#L1635-1 assume { :end_inline_reset_delta_events } true; 25447#L2017-2 [2021-12-16 10:06:17,731 INFO L793 eck$LassoCheckResult]: Loop: 25447#L2017-2 assume !false; 24727#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 24728#L1316 assume !false; 26056#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 26118#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 24665#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 24807#L1101 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 24808#L1115 assume !(0 != eval_~tmp~0#1); 26141#L1332 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 25562#L932-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 25563#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 25745#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 26246#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 25915#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 25916#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 26478#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 26653#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 26648#L1372-3 assume !(0 == ~T7_E~0); 24709#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 24710#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 25379#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 25380#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 26291#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 26601#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 25859#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 25015#L1412-3 assume !(0 == ~E_1~0); 25016#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 25780#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 25781#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 26475#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 26162#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 25874#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 25875#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 24775#L1452-3 assume !(0 == ~E_9~0); 24776#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 26414#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 26415#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 26219#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 26220#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 25013#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 25014#L646-42 assume !(1 == ~m_pc~0); 25600#L646-44 is_master_triggered_~__retres1~0#1 := 0; 26447#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 26448#L658-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 26586#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 26587#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26379#L665-42 assume 1 == ~t1_pc~0; 26340#L666-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 26342#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 26528#L677-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 25182#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 25183#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 26652#L684-42 assume !(1 == ~t2_pc~0); 26033#L684-44 is_transmit2_triggered_~__retres1~2#1 := 0; 26032#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 26642#L696-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 25811#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 25812#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 25934#L703-42 assume 1 == ~t3_pc~0; 26132#L704-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 26133#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 25451#L715-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 25452#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 26226#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 25846#L722-42 assume 1 == ~t4_pc~0; 25847#L723-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 26257#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 25500#L734-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 25327#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 25328#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 26622#L741-42 assume 1 == ~t5_pc~0; 26564#L742-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 25709#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 25710#L753-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 26655#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 25617#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 25618#L760-42 assume !(1 == ~t6_pc~0); 25752#L760-44 is_transmit6_triggered_~__retres1~6#1 := 0; 25887#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 25888#L772-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 26276#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 25569#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 25570#L779-42 assume !(1 == ~t7_pc~0); 26346#L779-44 is_transmit7_triggered_~__retres1~7#1 := 0; 26347#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 25256#L791-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 25257#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 25110#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 25111#L798-42 assume !(1 == ~t8_pc~0); 24721#L798-44 is_transmit8_triggered_~__retres1~8#1 := 0; 24722#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 26465#L810-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 25911#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 24941#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 24942#L817-42 assume 1 == ~t9_pc~0; 25715#L818-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 25225#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 25226#L829-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 25352#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 26157#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 26158#L836-42 assume 1 == ~t10_pc~0; 26250#L837-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 25263#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 25264#L848-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 26565#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 26566#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 26607#L855-42 assume 1 == ~t11_pc~0; 26620#L856-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 24814#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 24815#L867-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 25564#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 26327#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 25428#L874-42 assume 1 == ~t12_pc~0; 25429#L875-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 25668#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 24729#L886-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 24730#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 24983#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 24984#L893-42 assume 1 == ~t13_pc~0; 26186#L894-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 25968#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 25983#L905-14 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 25885#L1770-42 assume !(0 != activate_threads_~tmp___12~0#1); 25357#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 25358#L912-42 assume !(1 == ~t14_pc~0); 26167#L912-44 is_transmit14_triggered_~__retres1~14#1 := 0; 24675#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 24676#L924-14 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 26256#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 25103#L1778-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 25104#L1495-3 assume !(1 == ~M_E~0); 25719#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 26147#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 26240#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 25333#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 25296#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 25297#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 25954#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 26177#L1530-3 assume !(1 == ~T8_E~0); 25142#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 25143#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 25180#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 26437#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 26546#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 25586#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 25587#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 26202#L1570-3 assume !(1 == ~E_2~0); 26153#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 26154#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 26509#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 26553#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 26599#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 25976#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 25977#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 26452#L1610-3 assume !(1 == ~E_10~0); 25339#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 25340#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 25944#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 25945#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 25849#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 25280#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 24885#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 25623#L1101-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 26179#L2036 assume !(0 == start_simulation_~tmp~3#1); 26180#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 26332#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 25492#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 26510#L1101-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 25892#L1991 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 25893#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 26613#L1999 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 26614#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 25447#L2017-2 [2021-12-16 10:06:17,732 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:17,732 INFO L85 PathProgramCache]: Analyzing trace with hash 1597669734, now seen corresponding path program 1 times [2021-12-16 10:06:17,733 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:17,733 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [903362335] [2021-12-16 10:06:17,733 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:17,733 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:17,747 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:06:17,764 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:06:17,765 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:06:17,765 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [903362335] [2021-12-16 10:06:17,765 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [903362335] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:06:17,765 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:06:17,765 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:06:17,765 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [525527171] [2021-12-16 10:06:17,766 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:06:17,766 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:06:17,766 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:17,766 INFO L85 PathProgramCache]: Analyzing trace with hash -1842591925, now seen corresponding path program 1 times [2021-12-16 10:06:17,766 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:17,767 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [875818945] [2021-12-16 10:06:17,767 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:17,767 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:17,789 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:06:17,809 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:06:17,809 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:06:17,809 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [875818945] [2021-12-16 10:06:17,810 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [875818945] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:06:17,810 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:06:17,810 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:06:17,810 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [166392698] [2021-12-16 10:06:17,810 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:06:17,811 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:06:17,811 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:06:17,811 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-16 10:06:17,811 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-16 10:06:17,811 INFO L87 Difference]: Start difference. First operand 2047 states and 3029 transitions. cyclomatic complexity: 983 Second operand has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:17,835 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:06:17,835 INFO L93 Difference]: Finished difference Result 2047 states and 3028 transitions. [2021-12-16 10:06:17,835 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-16 10:06:17,836 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2047 states and 3028 transitions. [2021-12-16 10:06:17,844 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2021-12-16 10:06:17,851 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2047 states to 2047 states and 3028 transitions. [2021-12-16 10:06:17,851 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2047 [2021-12-16 10:06:17,852 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2047 [2021-12-16 10:06:17,852 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2047 states and 3028 transitions. [2021-12-16 10:06:17,854 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:06:17,854 INFO L681 BuchiCegarLoop]: Abstraction has 2047 states and 3028 transitions. [2021-12-16 10:06:17,856 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2047 states and 3028 transitions. [2021-12-16 10:06:17,869 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2047 to 2047. [2021-12-16 10:06:17,871 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2047 states, 2047 states have (on average 1.47923790913532) internal successors, (3028), 2046 states have internal predecessors, (3028), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:17,876 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2047 states to 2047 states and 3028 transitions. [2021-12-16 10:06:17,876 INFO L704 BuchiCegarLoop]: Abstraction has 2047 states and 3028 transitions. [2021-12-16 10:06:17,876 INFO L587 BuchiCegarLoop]: Abstraction has 2047 states and 3028 transitions. [2021-12-16 10:06:17,876 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2021-12-16 10:06:17,876 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2047 states and 3028 transitions. [2021-12-16 10:06:17,881 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2021-12-16 10:06:17,881 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:06:17,881 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:06:17,883 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:17,884 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:17,884 INFO L791 eck$LassoCheckResult]: Stem: 29646#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 29647#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 30249#L1980 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 29366#L932 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 29367#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 29612#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 29613#L944-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 29340#L949-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 29341#L954-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 30564#L959-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 29916#L964-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 29917#L969-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 30434#L974-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 29826#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 29827#L984-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 29247#L989-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 29248#L994-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 29579#L999-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 29777#L1004-1 assume !(1 == ~t14_i~0);~t14_st~0 := 2; 28824#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 28825#L1342 assume !(0 == ~M_E~0); 28990#L1342-2 assume !(0 == ~T1_E~0); 29546#L1347-1 assume !(0 == ~T2_E~0); 30547#L1352-1 assume !(0 == ~T3_E~0); 30343#L1357-1 assume !(0 == ~T4_E~0); 29571#L1362-1 assume !(0 == ~T5_E~0); 29572#L1367-1 assume !(0 == ~T6_E~0); 29169#L1372-1 assume 0 == ~T7_E~0;~T7_E~0 := 1; 29170#L1377-1 assume !(0 == ~T8_E~0); 29500#L1382-1 assume !(0 == ~T9_E~0); 29501#L1387-1 assume !(0 == ~T10_E~0); 30228#L1392-1 assume !(0 == ~T11_E~0); 29532#L1397-1 assume !(0 == ~T12_E~0); 29533#L1402-1 assume !(0 == ~T13_E~0); 29185#L1407-1 assume !(0 == ~T14_E~0); 29186#L1412-1 assume 0 == ~E_1~0;~E_1~0 := 1; 30464#L1417-1 assume !(0 == ~E_2~0); 30465#L1422-1 assume !(0 == ~E_3~0); 30706#L1427-1 assume !(0 == ~E_4~0); 29373#L1432-1 assume !(0 == ~E_5~0); 29374#L1437-1 assume !(0 == ~E_6~0); 30382#L1442-1 assume !(0 == ~E_7~0); 30383#L1447-1 assume !(0 == ~E_8~0); 30225#L1452-1 assume 0 == ~E_9~0;~E_9~0 := 1; 28960#L1457-1 assume !(0 == ~E_10~0); 28961#L1462-1 assume !(0 == ~E_11~0); 30417#L1467-1 assume !(0 == ~E_12~0); 30429#L1472-1 assume !(0 == ~E_13~0); 30430#L1477-1 assume !(0 == ~E_14~0); 30172#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 29159#L646 assume 1 == ~m_pc~0; 29160#L647 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 29836#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 29851#L658 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 29249#L1666 assume !(0 != activate_threads_~tmp~1#1); 29250#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 30727#L665 assume !(1 == ~t1_pc~0); 29725#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 29726#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 29258#L677 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 29259#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 30049#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 30050#L684 assume 1 == ~t2_pc~0; 30167#L685 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 30091#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 30156#L696 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 30551#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 30552#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 30740#L703 assume !(1 == ~t3_pc~0); 29395#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 29396#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 30042#L715 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 28794#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 28795#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 29280#L722 assume 1 == ~t4_pc~0; 30018#L723 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 29461#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 29806#L734 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 30366#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 29873#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 28991#L741 assume 1 == ~t5_pc~0; 28992#L742 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 29302#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 29456#L753 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 29457#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 30136#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 29547#L760 assume !(1 == ~t6_pc~0); 29394#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 29393#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 29251#L772 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 29252#L1714 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 29973#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 29974#L779 assume 1 == ~t7_pc~0; 29036#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 28882#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 28883#L791 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 29291#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 29314#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 29315#L798 assume !(1 == ~t8_pc~0); 30596#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 30519#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 29038#L810 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 29039#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 30729#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 28859#L817 assume 1 == ~t9_pc~0; 28860#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 29654#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 29655#L829 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 30177#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 29265#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 29266#L836 assume !(1 == ~t10_pc~0); 29282#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 29213#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 29214#L848 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 29462#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 29463#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 30529#L855 assume 1 == ~t11_pc~0; 29847#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 29848#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 30412#L867 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 30221#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 30056#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 29155#L874 assume !(1 == ~t12_pc~0); 29156#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 29323#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 29324#L886 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 29464#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 28832#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 28833#L893 assume 1 == ~t13_pc~0; 30663#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 29188#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 29499#L905 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 30590#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 30598#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 30599#L912 assume 1 == ~t14_pc~0; 30389#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 30390#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 29158#L924 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 29090#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 29091#L1778-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 29866#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 30282#L1495-2 assume !(1 == ~T1_E~0); 30283#L1500-1 assume !(1 == ~T2_E~0); 29969#L1505-1 assume !(1 == ~T3_E~0); 29970#L1510-1 assume !(1 == ~T4_E~0); 30027#L1515-1 assume !(1 == ~T5_E~0); 30028#L1520-1 assume !(1 == ~T6_E~0); 30597#L1525-1 assume !(1 == ~T7_E~0); 30307#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 29260#L1535-1 assume !(1 == ~T9_E~0); 29261#L1540-1 assume !(1 == ~T10_E~0); 28753#L1545-1 assume !(1 == ~T11_E~0); 28754#L1550-1 assume !(1 == ~T12_E~0); 29002#L1555-1 assume !(1 == ~T13_E~0); 29003#L1560-1 assume !(1 == ~T14_E~0); 29303#L1565-1 assume !(1 == ~E_1~0); 30716#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 30194#L1575-1 assume !(1 == ~E_3~0); 29573#L1580-1 assume !(1 == ~E_4~0); 29574#L1585-1 assume !(1 == ~E_5~0); 30044#L1590-1 assume !(1 == ~E_6~0); 29608#L1595-1 assume !(1 == ~E_7~0); 29609#L1600-1 assume !(1 == ~E_8~0); 29981#L1605-1 assume !(1 == ~E_9~0); 29982#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 30499#L1615-1 assume !(1 == ~E_11~0); 29438#L1620-1 assume !(1 == ~E_12~0); 29439#L1625-1 assume !(1 == ~E_13~0); 30226#L1630-1 assume !(1 == ~E_14~0); 29607#L1635-1 assume { :end_inline_reset_delta_events } true; 29548#L2017-2 [2021-12-16 10:06:17,885 INFO L793 eck$LassoCheckResult]: Loop: 29548#L2017-2 assume !false; 28828#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 28829#L1316 assume !false; 30157#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 30219#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 28766#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 28908#L1101 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 28909#L1115 assume !(0 != eval_~tmp~0#1); 30242#L1332 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 29663#L932-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 29664#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 29846#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 30347#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 30016#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 30017#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 30579#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 30754#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 30749#L1372-3 assume !(0 == ~T7_E~0); 28810#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 28811#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 29480#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 29481#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 30392#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 30702#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 29960#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 29116#L1412-3 assume !(0 == ~E_1~0); 29117#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 29881#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 29882#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 30576#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 30263#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 29975#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 29976#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 28876#L1452-3 assume !(0 == ~E_9~0); 28877#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 30515#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 30516#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 30320#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 30321#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 29114#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 29115#L646-42 assume 1 == ~m_pc~0; 29700#L647-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 30548#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 30549#L658-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 30687#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 30688#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 30480#L665-42 assume 1 == ~t1_pc~0; 30441#L666-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 30443#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 30629#L677-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 29283#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 29284#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 30753#L684-42 assume 1 == ~t2_pc~0; 30132#L685-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 30133#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 30743#L696-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 29912#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 29913#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 30035#L703-42 assume 1 == ~t3_pc~0; 30233#L704-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 30234#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 29552#L715-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 29553#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 30327#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 29947#L722-42 assume 1 == ~t4_pc~0; 29948#L723-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 30358#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 29601#L734-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 29428#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 29429#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 30723#L741-42 assume !(1 == ~t5_pc~0); 30340#L741-44 is_transmit5_triggered_~__retres1~5#1 := 0; 29810#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 29811#L753-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 30756#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 29718#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 29719#L760-42 assume !(1 == ~t6_pc~0); 29853#L760-44 is_transmit6_triggered_~__retres1~6#1 := 0; 29988#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 29989#L772-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 30377#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 29670#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 29671#L779-42 assume 1 == ~t7_pc~0; 30500#L780-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 30448#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 29357#L791-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 29358#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 29211#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 29212#L798-42 assume !(1 == ~t8_pc~0); 28822#L798-44 is_transmit8_triggered_~__retres1~8#1 := 0; 28823#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 30566#L810-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 30012#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 29042#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 29043#L817-42 assume 1 == ~t9_pc~0; 29816#L818-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 29326#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 29327#L829-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 29453#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 30258#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 30259#L836-42 assume !(1 == ~t10_pc~0); 30352#L836-44 is_transmit10_triggered_~__retres1~10#1 := 0; 29364#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 29365#L848-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 30666#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 30667#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 30708#L855-42 assume 1 == ~t11_pc~0; 30721#L856-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 28915#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 28916#L867-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 29665#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 30428#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 29529#L874-42 assume 1 == ~t12_pc~0; 29530#L875-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 29769#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 28830#L886-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 28831#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 29084#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 29085#L893-42 assume 1 == ~t13_pc~0; 30288#L894-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 30069#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 30084#L905-14 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 29986#L1770-42 assume !(0 != activate_threads_~tmp___12~0#1); 29458#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 29459#L912-42 assume !(1 == ~t14_pc~0); 30268#L912-44 is_transmit14_triggered_~__retres1~14#1 := 0; 28776#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 28777#L924-14 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 30357#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 29204#L1778-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 29205#L1495-3 assume !(1 == ~M_E~0); 29820#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 30248#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 30341#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 29434#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 29397#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 29398#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 30055#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 30278#L1530-3 assume !(1 == ~T8_E~0); 29243#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 29244#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 29281#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 30538#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 30647#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 29687#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 29688#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 30303#L1570-3 assume !(1 == ~E_2~0); 30254#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 30255#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 30610#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 30654#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 30700#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 30077#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 30078#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 30553#L1610-3 assume !(1 == ~E_10~0); 29440#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 29441#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 30045#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 30046#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 29950#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 29381#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 28986#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 29724#L1101-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 30280#L2036 assume !(0 == start_simulation_~tmp~3#1); 30281#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 30433#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 29593#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 30611#L1101-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 29993#L1991 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 29994#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 30714#L1999 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 30715#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 29548#L2017-2 [2021-12-16 10:06:17,885 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:17,885 INFO L85 PathProgramCache]: Analyzing trace with hash -1911299672, now seen corresponding path program 1 times [2021-12-16 10:06:17,886 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:17,886 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1386490338] [2021-12-16 10:06:17,886 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:17,886 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:17,893 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:06:17,905 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:06:17,905 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:06:17,905 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1386490338] [2021-12-16 10:06:17,905 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1386490338] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:06:17,905 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:06:17,906 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:06:17,906 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1188883660] [2021-12-16 10:06:17,906 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:06:17,906 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:06:17,906 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:17,907 INFO L85 PathProgramCache]: Analyzing trace with hash 1991472556, now seen corresponding path program 1 times [2021-12-16 10:06:17,907 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:17,907 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [508405033] [2021-12-16 10:06:17,907 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:17,907 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:17,916 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:06:17,932 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:06:17,933 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:06:17,933 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [508405033] [2021-12-16 10:06:17,933 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [508405033] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:06:17,933 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:06:17,933 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:06:17,933 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1768417145] [2021-12-16 10:06:17,933 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:06:17,934 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:06:17,934 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:06:17,934 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-16 10:06:17,934 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-16 10:06:17,934 INFO L87 Difference]: Start difference. First operand 2047 states and 3028 transitions. cyclomatic complexity: 982 Second operand has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:17,954 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:06:17,954 INFO L93 Difference]: Finished difference Result 2047 states and 3027 transitions. [2021-12-16 10:06:17,954 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-16 10:06:17,955 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2047 states and 3027 transitions. [2021-12-16 10:06:17,961 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2021-12-16 10:06:17,967 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2047 states to 2047 states and 3027 transitions. [2021-12-16 10:06:17,967 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2047 [2021-12-16 10:06:17,968 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2047 [2021-12-16 10:06:17,968 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2047 states and 3027 transitions. [2021-12-16 10:06:17,970 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:06:17,970 INFO L681 BuchiCegarLoop]: Abstraction has 2047 states and 3027 transitions. [2021-12-16 10:06:17,971 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2047 states and 3027 transitions. [2021-12-16 10:06:17,984 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2047 to 2047. [2021-12-16 10:06:17,987 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2047 states, 2047 states have (on average 1.4787493893502688) internal successors, (3027), 2046 states have internal predecessors, (3027), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:17,990 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2047 states to 2047 states and 3027 transitions. [2021-12-16 10:06:17,990 INFO L704 BuchiCegarLoop]: Abstraction has 2047 states and 3027 transitions. [2021-12-16 10:06:17,990 INFO L587 BuchiCegarLoop]: Abstraction has 2047 states and 3027 transitions. [2021-12-16 10:06:17,990 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2021-12-16 10:06:17,990 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2047 states and 3027 transitions. [2021-12-16 10:06:17,995 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2021-12-16 10:06:17,995 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:06:17,995 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:06:17,997 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:17,997 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:17,998 INFO L791 eck$LassoCheckResult]: Stem: 33747#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 33748#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 34350#L1980 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 33467#L932 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 33468#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 33713#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 33714#L944-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 33441#L949-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 33442#L954-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 34665#L959-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 34017#L964-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 34018#L969-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 34535#L974-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 33927#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 33928#L984-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 33348#L989-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 33349#L994-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 33680#L999-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 33878#L1004-1 assume !(1 == ~t14_i~0);~t14_st~0 := 2; 32925#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 32926#L1342 assume !(0 == ~M_E~0); 33091#L1342-2 assume !(0 == ~T1_E~0); 33647#L1347-1 assume !(0 == ~T2_E~0); 34648#L1352-1 assume !(0 == ~T3_E~0); 34444#L1357-1 assume !(0 == ~T4_E~0); 33672#L1362-1 assume !(0 == ~T5_E~0); 33673#L1367-1 assume !(0 == ~T6_E~0); 33270#L1372-1 assume 0 == ~T7_E~0;~T7_E~0 := 1; 33271#L1377-1 assume !(0 == ~T8_E~0); 33601#L1382-1 assume !(0 == ~T9_E~0); 33602#L1387-1 assume !(0 == ~T10_E~0); 34329#L1392-1 assume !(0 == ~T11_E~0); 33633#L1397-1 assume !(0 == ~T12_E~0); 33634#L1402-1 assume !(0 == ~T13_E~0); 33286#L1407-1 assume !(0 == ~T14_E~0); 33287#L1412-1 assume 0 == ~E_1~0;~E_1~0 := 1; 34565#L1417-1 assume !(0 == ~E_2~0); 34566#L1422-1 assume !(0 == ~E_3~0); 34807#L1427-1 assume !(0 == ~E_4~0); 33474#L1432-1 assume !(0 == ~E_5~0); 33475#L1437-1 assume !(0 == ~E_6~0); 34483#L1442-1 assume !(0 == ~E_7~0); 34484#L1447-1 assume !(0 == ~E_8~0); 34326#L1452-1 assume 0 == ~E_9~0;~E_9~0 := 1; 33061#L1457-1 assume !(0 == ~E_10~0); 33062#L1462-1 assume !(0 == ~E_11~0); 34518#L1467-1 assume !(0 == ~E_12~0); 34530#L1472-1 assume !(0 == ~E_13~0); 34531#L1477-1 assume !(0 == ~E_14~0); 34273#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 33260#L646 assume 1 == ~m_pc~0; 33261#L647 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 33937#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 33952#L658 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 33350#L1666 assume !(0 != activate_threads_~tmp~1#1); 33351#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 34828#L665 assume !(1 == ~t1_pc~0); 33826#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 33827#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 33359#L677 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 33360#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 34150#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 34151#L684 assume 1 == ~t2_pc~0; 34268#L685 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 34192#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 34257#L696 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 34652#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 34653#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 34841#L703 assume !(1 == ~t3_pc~0); 33496#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 33497#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 34143#L715 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 32895#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 32896#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 33381#L722 assume 1 == ~t4_pc~0; 34119#L723 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 33562#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 33907#L734 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 34467#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 33974#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 33092#L741 assume 1 == ~t5_pc~0; 33093#L742 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 33403#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 33557#L753 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 33558#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 34237#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 33648#L760 assume !(1 == ~t6_pc~0); 33495#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 33494#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 33352#L772 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 33353#L1714 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 34074#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 34075#L779 assume 1 == ~t7_pc~0; 33137#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 32983#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 32984#L791 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 33392#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 33415#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 33416#L798 assume !(1 == ~t8_pc~0); 34697#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 34620#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 33139#L810 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 33140#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 34830#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 32960#L817 assume 1 == ~t9_pc~0; 32961#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 33755#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 33756#L829 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 34278#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 33366#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 33367#L836 assume !(1 == ~t10_pc~0); 33383#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 33314#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 33315#L848 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 33563#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 33564#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 34630#L855 assume 1 == ~t11_pc~0; 33948#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 33949#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 34513#L867 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 34322#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 34157#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 33256#L874 assume !(1 == ~t12_pc~0); 33257#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 33424#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 33425#L886 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 33565#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 32933#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 32934#L893 assume 1 == ~t13_pc~0; 34764#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 33289#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 33600#L905 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 34691#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 34699#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 34700#L912 assume 1 == ~t14_pc~0; 34490#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 34491#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 33259#L924 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 33191#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 33192#L1778-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 33967#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 34383#L1495-2 assume !(1 == ~T1_E~0); 34384#L1500-1 assume !(1 == ~T2_E~0); 34070#L1505-1 assume !(1 == ~T3_E~0); 34071#L1510-1 assume !(1 == ~T4_E~0); 34128#L1515-1 assume !(1 == ~T5_E~0); 34129#L1520-1 assume !(1 == ~T6_E~0); 34698#L1525-1 assume !(1 == ~T7_E~0); 34408#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 33361#L1535-1 assume !(1 == ~T9_E~0); 33362#L1540-1 assume !(1 == ~T10_E~0); 32854#L1545-1 assume !(1 == ~T11_E~0); 32855#L1550-1 assume !(1 == ~T12_E~0); 33103#L1555-1 assume !(1 == ~T13_E~0); 33104#L1560-1 assume !(1 == ~T14_E~0); 33404#L1565-1 assume !(1 == ~E_1~0); 34817#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 34295#L1575-1 assume !(1 == ~E_3~0); 33674#L1580-1 assume !(1 == ~E_4~0); 33675#L1585-1 assume !(1 == ~E_5~0); 34145#L1590-1 assume !(1 == ~E_6~0); 33709#L1595-1 assume !(1 == ~E_7~0); 33710#L1600-1 assume !(1 == ~E_8~0); 34082#L1605-1 assume !(1 == ~E_9~0); 34083#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 34600#L1615-1 assume !(1 == ~E_11~0); 33539#L1620-1 assume !(1 == ~E_12~0); 33540#L1625-1 assume !(1 == ~E_13~0); 34327#L1630-1 assume !(1 == ~E_14~0); 33708#L1635-1 assume { :end_inline_reset_delta_events } true; 33649#L2017-2 [2021-12-16 10:06:17,998 INFO L793 eck$LassoCheckResult]: Loop: 33649#L2017-2 assume !false; 32929#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 32930#L1316 assume !false; 34258#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 34320#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 32867#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 33009#L1101 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 33010#L1115 assume !(0 != eval_~tmp~0#1); 34343#L1332 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 33764#L932-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 33765#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 33947#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 34448#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 34117#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 34118#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 34680#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 34855#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 34850#L1372-3 assume !(0 == ~T7_E~0); 32911#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 32912#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 33581#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 33582#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 34493#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 34803#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 34061#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 33217#L1412-3 assume !(0 == ~E_1~0); 33218#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 33982#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 33983#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 34677#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 34364#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 34076#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 34077#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 32977#L1452-3 assume !(0 == ~E_9~0); 32978#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 34616#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 34617#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 34421#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 34422#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 33215#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 33216#L646-42 assume 1 == ~m_pc~0; 33801#L647-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 34649#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 34650#L658-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 34788#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 34789#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 34581#L665-42 assume 1 == ~t1_pc~0; 34542#L666-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 34544#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 34730#L677-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 33384#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 33385#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 34854#L684-42 assume 1 == ~t2_pc~0; 34233#L685-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 34234#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 34844#L696-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 34013#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 34014#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 34136#L703-42 assume !(1 == ~t3_pc~0); 34336#L703-44 is_transmit3_triggered_~__retres1~3#1 := 0; 34335#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 33653#L715-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 33654#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 34428#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 34048#L722-42 assume 1 == ~t4_pc~0; 34049#L723-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 34459#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 33702#L734-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 33529#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 33530#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 34824#L741-42 assume !(1 == ~t5_pc~0); 34441#L741-44 is_transmit5_triggered_~__retres1~5#1 := 0; 33911#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 33912#L753-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 34857#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 33819#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 33820#L760-42 assume !(1 == ~t6_pc~0); 33954#L760-44 is_transmit6_triggered_~__retres1~6#1 := 0; 34089#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 34090#L772-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 34478#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 33771#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 33772#L779-42 assume !(1 == ~t7_pc~0); 34548#L779-44 is_transmit7_triggered_~__retres1~7#1 := 0; 34549#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 33458#L791-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 33459#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 33312#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 33313#L798-42 assume 1 == ~t8_pc~0; 33763#L799-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 32924#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 34667#L810-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 34113#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 33143#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 33144#L817-42 assume 1 == ~t9_pc~0; 33917#L818-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 33427#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 33428#L829-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 33554#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 34359#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 34360#L836-42 assume 1 == ~t10_pc~0; 34452#L837-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 33465#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 33466#L848-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 34767#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 34768#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 34809#L855-42 assume 1 == ~t11_pc~0; 34822#L856-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 33016#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 33017#L867-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 33766#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 34529#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 33630#L874-42 assume !(1 == ~t12_pc~0); 33632#L874-44 is_transmit12_triggered_~__retres1~12#1 := 0; 33873#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 32931#L886-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 32932#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 33185#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 33186#L893-42 assume 1 == ~t13_pc~0; 34389#L894-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 34170#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 34185#L905-14 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 34087#L1770-42 assume !(0 != activate_threads_~tmp___12~0#1); 33559#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 33560#L912-42 assume !(1 == ~t14_pc~0); 34369#L912-44 is_transmit14_triggered_~__retres1~14#1 := 0; 32877#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 32878#L924-14 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 34458#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 33305#L1778-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 33306#L1495-3 assume !(1 == ~M_E~0); 33921#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 34349#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 34442#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 33535#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 33498#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 33499#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 34156#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 34379#L1530-3 assume !(1 == ~T8_E~0); 33344#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 33345#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 33382#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 34639#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 34748#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 33788#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 33789#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 34404#L1570-3 assume !(1 == ~E_2~0); 34355#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 34356#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 34711#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 34755#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 34801#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 34178#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 34179#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 34654#L1610-3 assume !(1 == ~E_10~0); 33541#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 33542#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 34146#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 34147#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 34051#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 33482#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 33087#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 33825#L1101-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 34381#L2036 assume !(0 == start_simulation_~tmp~3#1); 34382#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 34534#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 33694#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 34712#L1101-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 34094#L1991 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 34095#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 34815#L1999 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 34816#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 33649#L2017-2 [2021-12-16 10:06:17,999 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:17,999 INFO L85 PathProgramCache]: Analyzing trace with hash 1716285734, now seen corresponding path program 1 times [2021-12-16 10:06:17,999 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:17,999 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1817299069] [2021-12-16 10:06:17,999 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:17,999 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:18,007 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:06:18,019 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:06:18,019 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:06:18,019 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1817299069] [2021-12-16 10:06:18,020 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1817299069] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:06:18,020 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:06:18,020 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:06:18,020 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1088111567] [2021-12-16 10:06:18,020 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:06:18,020 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:06:18,021 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:18,021 INFO L85 PathProgramCache]: Analyzing trace with hash -1856485429, now seen corresponding path program 1 times [2021-12-16 10:06:18,021 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:18,021 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [758828811] [2021-12-16 10:06:18,021 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:18,022 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:18,031 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:06:18,047 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:06:18,047 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:06:18,048 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [758828811] [2021-12-16 10:06:18,048 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [758828811] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:06:18,048 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:06:18,048 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:06:18,048 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1763098534] [2021-12-16 10:06:18,048 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:06:18,049 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:06:18,049 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:06:18,049 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-16 10:06:18,049 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-16 10:06:18,049 INFO L87 Difference]: Start difference. First operand 2047 states and 3027 transitions. cyclomatic complexity: 981 Second operand has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:18,068 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:06:18,069 INFO L93 Difference]: Finished difference Result 2047 states and 3026 transitions. [2021-12-16 10:06:18,069 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-16 10:06:18,069 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2047 states and 3026 transitions. [2021-12-16 10:06:18,075 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2021-12-16 10:06:18,081 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2047 states to 2047 states and 3026 transitions. [2021-12-16 10:06:18,081 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2047 [2021-12-16 10:06:18,082 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2047 [2021-12-16 10:06:18,082 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2047 states and 3026 transitions. [2021-12-16 10:06:18,084 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:06:18,084 INFO L681 BuchiCegarLoop]: Abstraction has 2047 states and 3026 transitions. [2021-12-16 10:06:18,086 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2047 states and 3026 transitions. [2021-12-16 10:06:18,099 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2047 to 2047. [2021-12-16 10:06:18,101 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2047 states, 2047 states have (on average 1.4782608695652173) internal successors, (3026), 2046 states have internal predecessors, (3026), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:18,104 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2047 states to 2047 states and 3026 transitions. [2021-12-16 10:06:18,105 INFO L704 BuchiCegarLoop]: Abstraction has 2047 states and 3026 transitions. [2021-12-16 10:06:18,106 INFO L587 BuchiCegarLoop]: Abstraction has 2047 states and 3026 transitions. [2021-12-16 10:06:18,106 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2021-12-16 10:06:18,106 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2047 states and 3026 transitions. [2021-12-16 10:06:18,110 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2021-12-16 10:06:18,110 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:06:18,110 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:06:18,112 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:18,112 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:18,112 INFO L791 eck$LassoCheckResult]: Stem: 37848#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 37849#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 38451#L1980 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 37568#L932 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 37569#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 37814#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 37815#L944-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 37542#L949-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 37543#L954-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 38766#L959-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 38118#L964-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 38119#L969-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 38636#L974-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 38028#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 38029#L984-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 37449#L989-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 37450#L994-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 37781#L999-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 37979#L1004-1 assume !(1 == ~t14_i~0);~t14_st~0 := 2; 37026#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 37027#L1342 assume !(0 == ~M_E~0); 37192#L1342-2 assume !(0 == ~T1_E~0); 37748#L1347-1 assume !(0 == ~T2_E~0); 38749#L1352-1 assume !(0 == ~T3_E~0); 38545#L1357-1 assume !(0 == ~T4_E~0); 37773#L1362-1 assume !(0 == ~T5_E~0); 37774#L1367-1 assume !(0 == ~T6_E~0); 37371#L1372-1 assume 0 == ~T7_E~0;~T7_E~0 := 1; 37372#L1377-1 assume !(0 == ~T8_E~0); 37702#L1382-1 assume !(0 == ~T9_E~0); 37703#L1387-1 assume !(0 == ~T10_E~0); 38430#L1392-1 assume !(0 == ~T11_E~0); 37734#L1397-1 assume !(0 == ~T12_E~0); 37735#L1402-1 assume !(0 == ~T13_E~0); 37387#L1407-1 assume !(0 == ~T14_E~0); 37388#L1412-1 assume 0 == ~E_1~0;~E_1~0 := 1; 38666#L1417-1 assume !(0 == ~E_2~0); 38667#L1422-1 assume !(0 == ~E_3~0); 38908#L1427-1 assume !(0 == ~E_4~0); 37575#L1432-1 assume !(0 == ~E_5~0); 37576#L1437-1 assume !(0 == ~E_6~0); 38584#L1442-1 assume !(0 == ~E_7~0); 38585#L1447-1 assume !(0 == ~E_8~0); 38427#L1452-1 assume 0 == ~E_9~0;~E_9~0 := 1; 37162#L1457-1 assume !(0 == ~E_10~0); 37163#L1462-1 assume !(0 == ~E_11~0); 38619#L1467-1 assume !(0 == ~E_12~0); 38631#L1472-1 assume !(0 == ~E_13~0); 38632#L1477-1 assume !(0 == ~E_14~0); 38374#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 37361#L646 assume 1 == ~m_pc~0; 37362#L647 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 38038#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 38053#L658 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 37451#L1666 assume !(0 != activate_threads_~tmp~1#1); 37452#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 38929#L665 assume !(1 == ~t1_pc~0); 37927#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 37928#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 37460#L677 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 37461#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 38251#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 38252#L684 assume 1 == ~t2_pc~0; 38369#L685 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 38293#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 38358#L696 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 38753#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 38754#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 38942#L703 assume !(1 == ~t3_pc~0); 37597#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 37598#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 38244#L715 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 36996#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 36997#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 37482#L722 assume 1 == ~t4_pc~0; 38220#L723 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 37663#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 38008#L734 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 38568#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 38075#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 37193#L741 assume 1 == ~t5_pc~0; 37194#L742 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 37504#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 37658#L753 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 37659#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 38338#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 37749#L760 assume !(1 == ~t6_pc~0); 37596#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 37595#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 37453#L772 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 37454#L1714 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 38175#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 38176#L779 assume 1 == ~t7_pc~0; 37238#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 37084#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 37085#L791 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 37493#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 37516#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 37517#L798 assume !(1 == ~t8_pc~0); 38798#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 38721#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 37240#L810 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 37241#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 38931#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 37061#L817 assume 1 == ~t9_pc~0; 37062#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 37856#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 37857#L829 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 38379#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 37467#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 37468#L836 assume !(1 == ~t10_pc~0); 37484#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 37415#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 37416#L848 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 37664#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 37665#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 38731#L855 assume 1 == ~t11_pc~0; 38049#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 38050#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 38614#L867 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 38423#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 38258#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 37357#L874 assume !(1 == ~t12_pc~0); 37358#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 37525#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 37526#L886 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 37666#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 37034#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 37035#L893 assume 1 == ~t13_pc~0; 38865#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 37390#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 37701#L905 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 38792#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 38800#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 38801#L912 assume 1 == ~t14_pc~0; 38591#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 38592#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 37360#L924 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 37292#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 37293#L1778-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 38068#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 38484#L1495-2 assume !(1 == ~T1_E~0); 38485#L1500-1 assume !(1 == ~T2_E~0); 38171#L1505-1 assume !(1 == ~T3_E~0); 38172#L1510-1 assume !(1 == ~T4_E~0); 38229#L1515-1 assume !(1 == ~T5_E~0); 38230#L1520-1 assume !(1 == ~T6_E~0); 38799#L1525-1 assume !(1 == ~T7_E~0); 38509#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 37462#L1535-1 assume !(1 == ~T9_E~0); 37463#L1540-1 assume !(1 == ~T10_E~0); 36955#L1545-1 assume !(1 == ~T11_E~0); 36956#L1550-1 assume !(1 == ~T12_E~0); 37204#L1555-1 assume !(1 == ~T13_E~0); 37205#L1560-1 assume !(1 == ~T14_E~0); 37505#L1565-1 assume !(1 == ~E_1~0); 38918#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 38396#L1575-1 assume !(1 == ~E_3~0); 37775#L1580-1 assume !(1 == ~E_4~0); 37776#L1585-1 assume !(1 == ~E_5~0); 38246#L1590-1 assume !(1 == ~E_6~0); 37810#L1595-1 assume !(1 == ~E_7~0); 37811#L1600-1 assume !(1 == ~E_8~0); 38183#L1605-1 assume !(1 == ~E_9~0); 38184#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 38701#L1615-1 assume !(1 == ~E_11~0); 37640#L1620-1 assume !(1 == ~E_12~0); 37641#L1625-1 assume !(1 == ~E_13~0); 38428#L1630-1 assume !(1 == ~E_14~0); 37809#L1635-1 assume { :end_inline_reset_delta_events } true; 37750#L2017-2 [2021-12-16 10:06:18,113 INFO L793 eck$LassoCheckResult]: Loop: 37750#L2017-2 assume !false; 37030#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 37031#L1316 assume !false; 38359#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 38421#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 36968#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 37110#L1101 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 37111#L1115 assume !(0 != eval_~tmp~0#1); 38444#L1332 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 37865#L932-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 37866#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 38048#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 38549#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 38218#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 38219#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 38781#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 38956#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 38951#L1372-3 assume !(0 == ~T7_E~0); 37012#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 37013#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 37682#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 37683#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 38594#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 38904#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 38162#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 37318#L1412-3 assume !(0 == ~E_1~0); 37319#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 38083#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 38084#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 38778#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 38465#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 38177#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 38178#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 37078#L1452-3 assume !(0 == ~E_9~0); 37079#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 38717#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 38718#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 38522#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 38523#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 37316#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 37317#L646-42 assume 1 == ~m_pc~0; 37902#L647-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 38750#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 38751#L658-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 38889#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 38890#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 38682#L665-42 assume 1 == ~t1_pc~0; 38643#L666-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 38645#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 38831#L677-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 37485#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 37486#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 38955#L684-42 assume !(1 == ~t2_pc~0); 38336#L684-44 is_transmit2_triggered_~__retres1~2#1 := 0; 38335#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 38945#L696-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 38114#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 38115#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 38237#L703-42 assume 1 == ~t3_pc~0; 38435#L704-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 38436#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 37754#L715-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 37755#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 38529#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 38149#L722-42 assume 1 == ~t4_pc~0; 38150#L723-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 38560#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 37803#L734-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 37630#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 37631#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 38925#L741-42 assume 1 == ~t5_pc~0; 38867#L742-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 38012#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 38013#L753-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 38958#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 37920#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 37921#L760-42 assume !(1 == ~t6_pc~0); 38055#L760-44 is_transmit6_triggered_~__retres1~6#1 := 0; 38190#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 38191#L772-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 38579#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 37872#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 37873#L779-42 assume !(1 == ~t7_pc~0); 38649#L779-44 is_transmit7_triggered_~__retres1~7#1 := 0; 38650#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 37559#L791-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 37560#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 37413#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 37414#L798-42 assume !(1 == ~t8_pc~0); 37024#L798-44 is_transmit8_triggered_~__retres1~8#1 := 0; 37025#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 38768#L810-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 38214#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 37244#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 37245#L817-42 assume 1 == ~t9_pc~0; 38018#L818-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 37528#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 37529#L829-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 37655#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 38460#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 38461#L836-42 assume 1 == ~t10_pc~0; 38553#L837-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 37566#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 37567#L848-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 38868#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 38869#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 38910#L855-42 assume 1 == ~t11_pc~0; 38923#L856-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 37117#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 37118#L867-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 37867#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 38630#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 37731#L874-42 assume 1 == ~t12_pc~0; 37732#L875-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 37974#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 37032#L886-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 37033#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 37286#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 37287#L893-42 assume 1 == ~t13_pc~0; 38490#L894-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 38271#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 38286#L905-14 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 38188#L1770-42 assume !(0 != activate_threads_~tmp___12~0#1); 37660#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 37661#L912-42 assume !(1 == ~t14_pc~0); 38470#L912-44 is_transmit14_triggered_~__retres1~14#1 := 0; 36978#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 36979#L924-14 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 38559#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 37406#L1778-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 37407#L1495-3 assume !(1 == ~M_E~0); 38022#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 38450#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 38543#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 37636#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 37599#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 37600#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 38257#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 38480#L1530-3 assume !(1 == ~T8_E~0); 37445#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 37446#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 37483#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 38740#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 38849#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 37889#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 37890#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 38505#L1570-3 assume !(1 == ~E_2~0); 38456#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 38457#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 38812#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 38856#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 38902#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 38279#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 38280#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 38755#L1610-3 assume !(1 == ~E_10~0); 37642#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 37643#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 38247#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 38248#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 38152#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 37583#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 37188#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 37926#L1101-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 38482#L2036 assume !(0 == start_simulation_~tmp~3#1); 38483#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 38635#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 37795#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 38813#L1101-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 38195#L1991 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 38196#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 38916#L1999 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 38917#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 37750#L2017-2 [2021-12-16 10:06:18,113 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:18,113 INFO L85 PathProgramCache]: Analyzing trace with hash -383452696, now seen corresponding path program 1 times [2021-12-16 10:06:18,113 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:18,114 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1566377811] [2021-12-16 10:06:18,114 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:18,114 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:18,123 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:06:18,136 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:06:18,136 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:06:18,136 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1566377811] [2021-12-16 10:06:18,137 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1566377811] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:06:18,137 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:06:18,137 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:06:18,137 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [475728906] [2021-12-16 10:06:18,137 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:06:18,138 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:06:18,138 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:18,138 INFO L85 PathProgramCache]: Analyzing trace with hash -1218842068, now seen corresponding path program 1 times [2021-12-16 10:06:18,139 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:18,139 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [600672284] [2021-12-16 10:06:18,139 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:18,139 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:18,148 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:06:18,165 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:06:18,165 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:06:18,165 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [600672284] [2021-12-16 10:06:18,165 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [600672284] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:06:18,165 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:06:18,166 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:06:18,166 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [420772252] [2021-12-16 10:06:18,166 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:06:18,166 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:06:18,166 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:06:18,167 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-16 10:06:18,167 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-16 10:06:18,167 INFO L87 Difference]: Start difference. First operand 2047 states and 3026 transitions. cyclomatic complexity: 980 Second operand has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:18,199 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:06:18,199 INFO L93 Difference]: Finished difference Result 2047 states and 3025 transitions. [2021-12-16 10:06:18,200 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-16 10:06:18,200 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2047 states and 3025 transitions. [2021-12-16 10:06:18,205 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2021-12-16 10:06:18,209 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2047 states to 2047 states and 3025 transitions. [2021-12-16 10:06:18,209 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2047 [2021-12-16 10:06:18,210 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2047 [2021-12-16 10:06:18,210 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2047 states and 3025 transitions. [2021-12-16 10:06:18,212 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:06:18,212 INFO L681 BuchiCegarLoop]: Abstraction has 2047 states and 3025 transitions. [2021-12-16 10:06:18,214 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2047 states and 3025 transitions. [2021-12-16 10:06:18,227 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2047 to 2047. [2021-12-16 10:06:18,229 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2047 states, 2047 states have (on average 1.477772349780166) internal successors, (3025), 2046 states have internal predecessors, (3025), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:18,232 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2047 states to 2047 states and 3025 transitions. [2021-12-16 10:06:18,232 INFO L704 BuchiCegarLoop]: Abstraction has 2047 states and 3025 transitions. [2021-12-16 10:06:18,232 INFO L587 BuchiCegarLoop]: Abstraction has 2047 states and 3025 transitions. [2021-12-16 10:06:18,232 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2021-12-16 10:06:18,233 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2047 states and 3025 transitions. [2021-12-16 10:06:18,236 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2021-12-16 10:06:18,236 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:06:18,237 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:06:18,238 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:18,238 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:18,238 INFO L791 eck$LassoCheckResult]: Stem: 41949#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 41950#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 42552#L1980 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 41669#L932 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 41670#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 41915#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 41916#L944-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 41643#L949-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 41644#L954-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 42867#L959-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 42219#L964-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 42220#L969-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 42737#L974-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 42129#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 42130#L984-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 41550#L989-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 41551#L994-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 41882#L999-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 42080#L1004-1 assume !(1 == ~t14_i~0);~t14_st~0 := 2; 41127#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 41128#L1342 assume !(0 == ~M_E~0); 41293#L1342-2 assume !(0 == ~T1_E~0); 41849#L1347-1 assume !(0 == ~T2_E~0); 42850#L1352-1 assume !(0 == ~T3_E~0); 42646#L1357-1 assume !(0 == ~T4_E~0); 41874#L1362-1 assume !(0 == ~T5_E~0); 41875#L1367-1 assume !(0 == ~T6_E~0); 41472#L1372-1 assume 0 == ~T7_E~0;~T7_E~0 := 1; 41473#L1377-1 assume !(0 == ~T8_E~0); 41803#L1382-1 assume !(0 == ~T9_E~0); 41804#L1387-1 assume !(0 == ~T10_E~0); 42531#L1392-1 assume !(0 == ~T11_E~0); 41835#L1397-1 assume !(0 == ~T12_E~0); 41836#L1402-1 assume !(0 == ~T13_E~0); 41488#L1407-1 assume !(0 == ~T14_E~0); 41489#L1412-1 assume 0 == ~E_1~0;~E_1~0 := 1; 42767#L1417-1 assume !(0 == ~E_2~0); 42768#L1422-1 assume !(0 == ~E_3~0); 43009#L1427-1 assume !(0 == ~E_4~0); 41676#L1432-1 assume !(0 == ~E_5~0); 41677#L1437-1 assume !(0 == ~E_6~0); 42685#L1442-1 assume !(0 == ~E_7~0); 42686#L1447-1 assume !(0 == ~E_8~0); 42528#L1452-1 assume 0 == ~E_9~0;~E_9~0 := 1; 41263#L1457-1 assume !(0 == ~E_10~0); 41264#L1462-1 assume !(0 == ~E_11~0); 42720#L1467-1 assume !(0 == ~E_12~0); 42732#L1472-1 assume !(0 == ~E_13~0); 42733#L1477-1 assume !(0 == ~E_14~0); 42475#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 41462#L646 assume 1 == ~m_pc~0; 41463#L647 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 42139#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 42154#L658 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 41552#L1666 assume !(0 != activate_threads_~tmp~1#1); 41553#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 43030#L665 assume !(1 == ~t1_pc~0); 42028#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 42029#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 41561#L677 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 41562#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 42352#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 42353#L684 assume 1 == ~t2_pc~0; 42470#L685 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 42394#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 42459#L696 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 42854#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 42855#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 43043#L703 assume !(1 == ~t3_pc~0); 41698#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 41699#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 42345#L715 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 41097#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 41098#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 41583#L722 assume 1 == ~t4_pc~0; 42321#L723 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 41764#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 42109#L734 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 42669#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 42176#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 41294#L741 assume 1 == ~t5_pc~0; 41295#L742 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 41605#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 41759#L753 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 41760#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 42439#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 41850#L760 assume !(1 == ~t6_pc~0); 41697#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 41696#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 41554#L772 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 41555#L1714 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 42276#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 42277#L779 assume 1 == ~t7_pc~0; 41339#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 41185#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 41186#L791 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 41594#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 41617#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 41618#L798 assume !(1 == ~t8_pc~0); 42899#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 42822#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 41341#L810 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 41342#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 43032#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 41162#L817 assume 1 == ~t9_pc~0; 41163#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 41957#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 41958#L829 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 42480#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 41568#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 41569#L836 assume !(1 == ~t10_pc~0); 41585#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 41516#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 41517#L848 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 41765#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 41766#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 42832#L855 assume 1 == ~t11_pc~0; 42150#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 42151#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 42715#L867 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 42524#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 42359#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 41458#L874 assume !(1 == ~t12_pc~0); 41459#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 41626#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 41627#L886 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 41767#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 41135#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 41136#L893 assume 1 == ~t13_pc~0; 42966#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 41491#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 41802#L905 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 42893#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 42901#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 42902#L912 assume 1 == ~t14_pc~0; 42692#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 42693#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 41461#L924 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 41393#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 41394#L1778-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 42169#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 42585#L1495-2 assume !(1 == ~T1_E~0); 42586#L1500-1 assume !(1 == ~T2_E~0); 42272#L1505-1 assume !(1 == ~T3_E~0); 42273#L1510-1 assume !(1 == ~T4_E~0); 42330#L1515-1 assume !(1 == ~T5_E~0); 42331#L1520-1 assume !(1 == ~T6_E~0); 42900#L1525-1 assume !(1 == ~T7_E~0); 42610#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 41563#L1535-1 assume !(1 == ~T9_E~0); 41564#L1540-1 assume !(1 == ~T10_E~0); 41056#L1545-1 assume !(1 == ~T11_E~0); 41057#L1550-1 assume !(1 == ~T12_E~0); 41305#L1555-1 assume !(1 == ~T13_E~0); 41306#L1560-1 assume !(1 == ~T14_E~0); 41606#L1565-1 assume !(1 == ~E_1~0); 43019#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 42497#L1575-1 assume !(1 == ~E_3~0); 41876#L1580-1 assume !(1 == ~E_4~0); 41877#L1585-1 assume !(1 == ~E_5~0); 42347#L1590-1 assume !(1 == ~E_6~0); 41911#L1595-1 assume !(1 == ~E_7~0); 41912#L1600-1 assume !(1 == ~E_8~0); 42284#L1605-1 assume !(1 == ~E_9~0); 42285#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 42802#L1615-1 assume !(1 == ~E_11~0); 41741#L1620-1 assume !(1 == ~E_12~0); 41742#L1625-1 assume !(1 == ~E_13~0); 42529#L1630-1 assume !(1 == ~E_14~0); 41910#L1635-1 assume { :end_inline_reset_delta_events } true; 41851#L2017-2 [2021-12-16 10:06:18,239 INFO L793 eck$LassoCheckResult]: Loop: 41851#L2017-2 assume !false; 41131#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 41132#L1316 assume !false; 42460#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 42522#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 41069#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 41211#L1101 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 41212#L1115 assume !(0 != eval_~tmp~0#1); 42545#L1332 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 41966#L932-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 41967#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 42149#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 42650#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 42319#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 42320#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 42882#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 43057#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 43052#L1372-3 assume !(0 == ~T7_E~0); 41113#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 41114#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 41783#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 41784#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 42695#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 43005#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 42263#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 41419#L1412-3 assume !(0 == ~E_1~0); 41420#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 42184#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 42185#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 42879#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 42566#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 42278#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 42279#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 41179#L1452-3 assume !(0 == ~E_9~0); 41180#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 42818#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 42819#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 42623#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 42624#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 41417#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 41418#L646-42 assume 1 == ~m_pc~0; 42003#L647-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 42851#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 42852#L658-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 42990#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 42991#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 42783#L665-42 assume 1 == ~t1_pc~0; 42744#L666-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 42746#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 42932#L677-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 41586#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 41587#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 43056#L684-42 assume 1 == ~t2_pc~0; 42435#L685-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 42436#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 43046#L696-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 42215#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 42216#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 42338#L703-42 assume 1 == ~t3_pc~0; 42536#L704-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 42537#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 41855#L715-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 41856#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 42630#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 42250#L722-42 assume 1 == ~t4_pc~0; 42251#L723-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 42661#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 41904#L734-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 41731#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 41732#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 43026#L741-42 assume !(1 == ~t5_pc~0); 42643#L741-44 is_transmit5_triggered_~__retres1~5#1 := 0; 42113#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 42114#L753-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 43059#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 42021#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 42022#L760-42 assume !(1 == ~t6_pc~0); 42156#L760-44 is_transmit6_triggered_~__retres1~6#1 := 0; 42291#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 42292#L772-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 42680#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 41973#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 41974#L779-42 assume 1 == ~t7_pc~0; 42803#L780-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 42751#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 41660#L791-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 41661#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 41514#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 41515#L798-42 assume !(1 == ~t8_pc~0); 41125#L798-44 is_transmit8_triggered_~__retres1~8#1 := 0; 41126#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 42869#L810-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 42315#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 41345#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 41346#L817-42 assume 1 == ~t9_pc~0; 42119#L818-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 41629#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 41630#L829-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 41756#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 42561#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 42562#L836-42 assume 1 == ~t10_pc~0; 42654#L837-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 41667#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 41668#L848-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 42969#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 42970#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 43011#L855-42 assume 1 == ~t11_pc~0; 43024#L856-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 41218#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 41219#L867-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 41968#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 42731#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 41832#L874-42 assume 1 == ~t12_pc~0; 41833#L875-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 42075#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 41133#L886-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 41134#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 41387#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 41388#L893-42 assume !(1 == ~t13_pc~0); 42371#L893-44 is_transmit13_triggered_~__retres1~13#1 := 0; 42372#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 42387#L905-14 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 42289#L1770-42 assume !(0 != activate_threads_~tmp___12~0#1); 41761#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 41762#L912-42 assume !(1 == ~t14_pc~0); 42571#L912-44 is_transmit14_triggered_~__retres1~14#1 := 0; 41079#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 41080#L924-14 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 42660#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 41507#L1778-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 41508#L1495-3 assume !(1 == ~M_E~0); 42123#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 42551#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 42644#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 41737#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 41700#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 41701#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 42358#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 42581#L1530-3 assume !(1 == ~T8_E~0); 41546#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 41547#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 41584#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 42841#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 42950#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 41990#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 41991#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 42606#L1570-3 assume !(1 == ~E_2~0); 42557#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 42558#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 42913#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 42958#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 43003#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 42380#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 42381#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 42856#L1610-3 assume !(1 == ~E_10~0); 41743#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 41744#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 42348#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 42349#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 42253#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 41684#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 41289#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 42027#L1101-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 42583#L2036 assume !(0 == start_simulation_~tmp~3#1); 42584#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 42736#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 41896#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 42914#L1101-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 42296#L1991 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 42297#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 43017#L1999 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 43018#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 41851#L2017-2 [2021-12-16 10:06:18,239 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:18,240 INFO L85 PathProgramCache]: Analyzing trace with hash -1364407510, now seen corresponding path program 1 times [2021-12-16 10:06:18,240 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:18,240 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [170059733] [2021-12-16 10:06:18,240 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:18,240 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:18,248 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:06:18,263 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:06:18,263 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:06:18,263 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [170059733] [2021-12-16 10:06:18,263 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [170059733] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:06:18,264 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:06:18,264 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:06:18,264 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1203093315] [2021-12-16 10:06:18,264 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:06:18,264 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:06:18,264 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:18,265 INFO L85 PathProgramCache]: Analyzing trace with hash -1715277972, now seen corresponding path program 2 times [2021-12-16 10:06:18,265 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:18,265 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [641951553] [2021-12-16 10:06:18,265 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:18,265 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:18,274 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:06:18,298 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:06:18,298 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:06:18,298 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [641951553] [2021-12-16 10:06:18,299 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [641951553] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:06:18,299 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:06:18,299 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:06:18,299 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [19344304] [2021-12-16 10:06:18,299 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:06:18,299 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:06:18,299 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:06:18,300 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-16 10:06:18,300 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-16 10:06:18,301 INFO L87 Difference]: Start difference. First operand 2047 states and 3025 transitions. cyclomatic complexity: 979 Second operand has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:18,318 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:06:18,319 INFO L93 Difference]: Finished difference Result 2047 states and 3024 transitions. [2021-12-16 10:06:18,319 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-16 10:06:18,320 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2047 states and 3024 transitions. [2021-12-16 10:06:18,325 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2021-12-16 10:06:18,331 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2047 states to 2047 states and 3024 transitions. [2021-12-16 10:06:18,332 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2047 [2021-12-16 10:06:18,333 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2047 [2021-12-16 10:06:18,333 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2047 states and 3024 transitions. [2021-12-16 10:06:18,334 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:06:18,335 INFO L681 BuchiCegarLoop]: Abstraction has 2047 states and 3024 transitions. [2021-12-16 10:06:18,336 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2047 states and 3024 transitions. [2021-12-16 10:06:18,349 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2047 to 2047. [2021-12-16 10:06:18,351 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2047 states, 2047 states have (on average 1.4772838299951148) internal successors, (3024), 2046 states have internal predecessors, (3024), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:18,354 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2047 states to 2047 states and 3024 transitions. [2021-12-16 10:06:18,354 INFO L704 BuchiCegarLoop]: Abstraction has 2047 states and 3024 transitions. [2021-12-16 10:06:18,354 INFO L587 BuchiCegarLoop]: Abstraction has 2047 states and 3024 transitions. [2021-12-16 10:06:18,354 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2021-12-16 10:06:18,354 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2047 states and 3024 transitions. [2021-12-16 10:06:18,358 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2021-12-16 10:06:18,358 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:06:18,358 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:06:18,359 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:18,359 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:18,360 INFO L791 eck$LassoCheckResult]: Stem: 46050#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 46051#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 46653#L1980 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 45770#L932 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 45771#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 46016#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 46017#L944-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 45744#L949-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 45745#L954-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 46968#L959-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 46320#L964-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 46321#L969-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 46838#L974-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 46230#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 46231#L984-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 45651#L989-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 45652#L994-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 45983#L999-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 46181#L1004-1 assume !(1 == ~t14_i~0);~t14_st~0 := 2; 45228#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 45229#L1342 assume !(0 == ~M_E~0); 45394#L1342-2 assume !(0 == ~T1_E~0); 45950#L1347-1 assume !(0 == ~T2_E~0); 46951#L1352-1 assume !(0 == ~T3_E~0); 46747#L1357-1 assume !(0 == ~T4_E~0); 45975#L1362-1 assume !(0 == ~T5_E~0); 45976#L1367-1 assume !(0 == ~T6_E~0); 45573#L1372-1 assume 0 == ~T7_E~0;~T7_E~0 := 1; 45574#L1377-1 assume !(0 == ~T8_E~0); 45904#L1382-1 assume !(0 == ~T9_E~0); 45905#L1387-1 assume !(0 == ~T10_E~0); 46632#L1392-1 assume !(0 == ~T11_E~0); 45936#L1397-1 assume !(0 == ~T12_E~0); 45937#L1402-1 assume !(0 == ~T13_E~0); 45589#L1407-1 assume !(0 == ~T14_E~0); 45590#L1412-1 assume 0 == ~E_1~0;~E_1~0 := 1; 46868#L1417-1 assume !(0 == ~E_2~0); 46869#L1422-1 assume !(0 == ~E_3~0); 47110#L1427-1 assume !(0 == ~E_4~0); 45777#L1432-1 assume !(0 == ~E_5~0); 45778#L1437-1 assume !(0 == ~E_6~0); 46786#L1442-1 assume !(0 == ~E_7~0); 46787#L1447-1 assume !(0 == ~E_8~0); 46629#L1452-1 assume 0 == ~E_9~0;~E_9~0 := 1; 45364#L1457-1 assume !(0 == ~E_10~0); 45365#L1462-1 assume !(0 == ~E_11~0); 46821#L1467-1 assume !(0 == ~E_12~0); 46833#L1472-1 assume !(0 == ~E_13~0); 46834#L1477-1 assume !(0 == ~E_14~0); 46576#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 45563#L646 assume 1 == ~m_pc~0; 45564#L647 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 46240#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 46255#L658 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 45653#L1666 assume !(0 != activate_threads_~tmp~1#1); 45654#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 47131#L665 assume !(1 == ~t1_pc~0); 46129#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 46130#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 45662#L677 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 45663#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 46453#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 46454#L684 assume 1 == ~t2_pc~0; 46571#L685 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 46495#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 46560#L696 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 46955#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 46956#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 47144#L703 assume !(1 == ~t3_pc~0); 45799#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 45800#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 46446#L715 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 45198#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 45199#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 45684#L722 assume 1 == ~t4_pc~0; 46422#L723 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 45865#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 46210#L734 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 46770#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 46277#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 45395#L741 assume 1 == ~t5_pc~0; 45396#L742 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 45706#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 45860#L753 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 45861#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 46540#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 45951#L760 assume !(1 == ~t6_pc~0); 45798#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 45797#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 45655#L772 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 45656#L1714 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 46377#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 46378#L779 assume 1 == ~t7_pc~0; 45440#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 45286#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 45287#L791 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 45695#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 45718#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 45719#L798 assume !(1 == ~t8_pc~0); 47000#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 46923#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 45442#L810 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 45443#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 47133#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 45263#L817 assume 1 == ~t9_pc~0; 45264#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 46058#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 46059#L829 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 46581#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 45669#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 45670#L836 assume !(1 == ~t10_pc~0); 45686#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 45617#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 45618#L848 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 45866#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 45867#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 46933#L855 assume 1 == ~t11_pc~0; 46251#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 46252#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 46816#L867 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 46625#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 46460#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 45559#L874 assume !(1 == ~t12_pc~0); 45560#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 45727#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 45728#L886 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 45868#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 45236#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 45237#L893 assume 1 == ~t13_pc~0; 47067#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 45592#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 45903#L905 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 46994#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 47002#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 47003#L912 assume 1 == ~t14_pc~0; 46793#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 46794#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 45562#L924 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 45494#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 45495#L1778-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 46270#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 46686#L1495-2 assume !(1 == ~T1_E~0); 46687#L1500-1 assume !(1 == ~T2_E~0); 46373#L1505-1 assume !(1 == ~T3_E~0); 46374#L1510-1 assume !(1 == ~T4_E~0); 46431#L1515-1 assume !(1 == ~T5_E~0); 46432#L1520-1 assume !(1 == ~T6_E~0); 47001#L1525-1 assume !(1 == ~T7_E~0); 46711#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 45664#L1535-1 assume !(1 == ~T9_E~0); 45665#L1540-1 assume !(1 == ~T10_E~0); 45157#L1545-1 assume !(1 == ~T11_E~0); 45158#L1550-1 assume !(1 == ~T12_E~0); 45406#L1555-1 assume !(1 == ~T13_E~0); 45407#L1560-1 assume !(1 == ~T14_E~0); 45707#L1565-1 assume !(1 == ~E_1~0); 47120#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 46598#L1575-1 assume !(1 == ~E_3~0); 45977#L1580-1 assume !(1 == ~E_4~0); 45978#L1585-1 assume !(1 == ~E_5~0); 46448#L1590-1 assume !(1 == ~E_6~0); 46012#L1595-1 assume !(1 == ~E_7~0); 46013#L1600-1 assume !(1 == ~E_8~0); 46385#L1605-1 assume !(1 == ~E_9~0); 46386#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 46903#L1615-1 assume !(1 == ~E_11~0); 45842#L1620-1 assume !(1 == ~E_12~0); 45843#L1625-1 assume !(1 == ~E_13~0); 46630#L1630-1 assume !(1 == ~E_14~0); 46011#L1635-1 assume { :end_inline_reset_delta_events } true; 45952#L2017-2 [2021-12-16 10:06:18,360 INFO L793 eck$LassoCheckResult]: Loop: 45952#L2017-2 assume !false; 45232#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 45233#L1316 assume !false; 46561#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 46623#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 45170#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 45312#L1101 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 45313#L1115 assume !(0 != eval_~tmp~0#1); 46646#L1332 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 46067#L932-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 46068#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 46250#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 46751#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 46420#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 46421#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 46983#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 47158#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 47153#L1372-3 assume !(0 == ~T7_E~0); 45214#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 45215#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 45884#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 45885#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 46796#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 47106#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 46364#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 45520#L1412-3 assume !(0 == ~E_1~0); 45521#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 46285#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 46286#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 46980#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 46667#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 46379#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 46380#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 45280#L1452-3 assume !(0 == ~E_9~0); 45281#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 46919#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 46920#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 46724#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 46725#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 45518#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 45519#L646-42 assume 1 == ~m_pc~0; 46104#L647-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 46952#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 46953#L658-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 47091#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 47092#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 46884#L665-42 assume 1 == ~t1_pc~0; 46845#L666-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 46847#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 47033#L677-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 45687#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 45688#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 47157#L684-42 assume 1 == ~t2_pc~0; 46536#L685-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 46537#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 47147#L696-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 46316#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 46317#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 46439#L703-42 assume 1 == ~t3_pc~0; 46637#L704-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 46638#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 45956#L715-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 45957#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 46731#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 46351#L722-42 assume 1 == ~t4_pc~0; 46352#L723-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 46762#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 46005#L734-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 45832#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 45833#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 47127#L741-42 assume !(1 == ~t5_pc~0); 46744#L741-44 is_transmit5_triggered_~__retres1~5#1 := 0; 46214#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 46215#L753-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 47160#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 46122#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 46123#L760-42 assume !(1 == ~t6_pc~0); 46257#L760-44 is_transmit6_triggered_~__retres1~6#1 := 0; 46392#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 46393#L772-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 46781#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 46074#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 46075#L779-42 assume !(1 == ~t7_pc~0); 46851#L779-44 is_transmit7_triggered_~__retres1~7#1 := 0; 46852#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 45761#L791-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 45762#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 45615#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 45616#L798-42 assume 1 == ~t8_pc~0; 46066#L799-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 45227#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 46970#L810-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 46416#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 45446#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 45447#L817-42 assume 1 == ~t9_pc~0; 46220#L818-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 45730#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 45731#L829-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 45857#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 46662#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 46663#L836-42 assume 1 == ~t10_pc~0; 46755#L837-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 45768#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 45769#L848-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 47070#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 47071#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 47112#L855-42 assume 1 == ~t11_pc~0; 47125#L856-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 45319#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 45320#L867-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 46069#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 46832#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 45933#L874-42 assume 1 == ~t12_pc~0; 45934#L875-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 46176#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 45234#L886-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 45235#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 45488#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 45489#L893-42 assume 1 == ~t13_pc~0; 46692#L894-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 46473#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 46488#L905-14 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 46390#L1770-42 assume !(0 != activate_threads_~tmp___12~0#1); 45862#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 45863#L912-42 assume !(1 == ~t14_pc~0); 46672#L912-44 is_transmit14_triggered_~__retres1~14#1 := 0; 45180#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 45181#L924-14 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 46761#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 45608#L1778-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 45609#L1495-3 assume !(1 == ~M_E~0); 46224#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 46652#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 46745#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 45838#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 45801#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 45802#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 46459#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 46682#L1530-3 assume !(1 == ~T8_E~0); 45647#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 45648#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 45685#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 46942#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 47051#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 46091#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 46092#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 46707#L1570-3 assume !(1 == ~E_2~0); 46658#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 46659#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 47014#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 47059#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 47104#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 46481#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 46482#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 46957#L1610-3 assume !(1 == ~E_10~0); 45844#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 45845#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 46449#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 46450#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 46354#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 45785#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 45390#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 46128#L1101-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 46684#L2036 assume !(0 == start_simulation_~tmp~3#1); 46685#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 46837#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 45997#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 47015#L1101-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 46397#L1991 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 46398#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 47118#L1999 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 47119#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 45952#L2017-2 [2021-12-16 10:06:18,361 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:18,361 INFO L85 PathProgramCache]: Analyzing trace with hash 405064104, now seen corresponding path program 1 times [2021-12-16 10:06:18,362 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:18,362 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1722636737] [2021-12-16 10:06:18,362 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:18,362 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:18,370 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:06:18,382 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:06:18,383 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:06:18,383 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1722636737] [2021-12-16 10:06:18,383 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1722636737] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:06:18,384 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:06:18,384 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:06:18,385 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [258822155] [2021-12-16 10:06:18,386 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:06:18,386 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:06:18,386 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:18,386 INFO L85 PathProgramCache]: Analyzing trace with hash -1400619827, now seen corresponding path program 1 times [2021-12-16 10:06:18,386 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:18,386 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1289049124] [2021-12-16 10:06:18,387 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:18,387 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:18,398 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:06:18,415 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:06:18,415 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:06:18,415 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1289049124] [2021-12-16 10:06:18,415 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1289049124] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:06:18,415 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:06:18,415 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:06:18,416 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [443646975] [2021-12-16 10:06:18,416 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:06:18,416 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:06:18,416 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:06:18,416 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-16 10:06:18,417 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-16 10:06:18,417 INFO L87 Difference]: Start difference. First operand 2047 states and 3024 transitions. cyclomatic complexity: 978 Second operand has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:18,435 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:06:18,435 INFO L93 Difference]: Finished difference Result 2047 states and 3023 transitions. [2021-12-16 10:06:18,436 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-16 10:06:18,436 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2047 states and 3023 transitions. [2021-12-16 10:06:18,441 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2021-12-16 10:06:18,452 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2047 states to 2047 states and 3023 transitions. [2021-12-16 10:06:18,452 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2047 [2021-12-16 10:06:18,453 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2047 [2021-12-16 10:06:18,453 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2047 states and 3023 transitions. [2021-12-16 10:06:18,455 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:06:18,455 INFO L681 BuchiCegarLoop]: Abstraction has 2047 states and 3023 transitions. [2021-12-16 10:06:18,456 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2047 states and 3023 transitions. [2021-12-16 10:06:18,470 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2047 to 2047. [2021-12-16 10:06:18,472 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2047 states, 2047 states have (on average 1.4767953102100635) internal successors, (3023), 2046 states have internal predecessors, (3023), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:18,474 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2047 states to 2047 states and 3023 transitions. [2021-12-16 10:06:18,474 INFO L704 BuchiCegarLoop]: Abstraction has 2047 states and 3023 transitions. [2021-12-16 10:06:18,474 INFO L587 BuchiCegarLoop]: Abstraction has 2047 states and 3023 transitions. [2021-12-16 10:06:18,474 INFO L425 BuchiCegarLoop]: ======== Iteration 13============ [2021-12-16 10:06:18,475 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2047 states and 3023 transitions. [2021-12-16 10:06:18,478 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2021-12-16 10:06:18,478 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:06:18,478 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:06:18,480 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:18,480 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:18,480 INFO L791 eck$LassoCheckResult]: Stem: 50151#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 50152#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 50754#L1980 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 49871#L932 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 49872#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 50117#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 50118#L944-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 49845#L949-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 49846#L954-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 51069#L959-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 50421#L964-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 50422#L969-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 50939#L974-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 50331#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 50332#L984-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 49752#L989-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 49753#L994-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 50084#L999-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 50282#L1004-1 assume !(1 == ~t14_i~0);~t14_st~0 := 2; 49329#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 49330#L1342 assume !(0 == ~M_E~0); 49495#L1342-2 assume !(0 == ~T1_E~0); 50051#L1347-1 assume !(0 == ~T2_E~0); 51052#L1352-1 assume !(0 == ~T3_E~0); 50848#L1357-1 assume !(0 == ~T4_E~0); 50076#L1362-1 assume !(0 == ~T5_E~0); 50077#L1367-1 assume !(0 == ~T6_E~0); 49674#L1372-1 assume 0 == ~T7_E~0;~T7_E~0 := 1; 49675#L1377-1 assume !(0 == ~T8_E~0); 50005#L1382-1 assume !(0 == ~T9_E~0); 50006#L1387-1 assume !(0 == ~T10_E~0); 50733#L1392-1 assume !(0 == ~T11_E~0); 50037#L1397-1 assume !(0 == ~T12_E~0); 50038#L1402-1 assume !(0 == ~T13_E~0); 49690#L1407-1 assume !(0 == ~T14_E~0); 49691#L1412-1 assume 0 == ~E_1~0;~E_1~0 := 1; 50969#L1417-1 assume !(0 == ~E_2~0); 50970#L1422-1 assume !(0 == ~E_3~0); 51211#L1427-1 assume !(0 == ~E_4~0); 49878#L1432-1 assume !(0 == ~E_5~0); 49879#L1437-1 assume !(0 == ~E_6~0); 50887#L1442-1 assume !(0 == ~E_7~0); 50888#L1447-1 assume !(0 == ~E_8~0); 50730#L1452-1 assume 0 == ~E_9~0;~E_9~0 := 1; 49465#L1457-1 assume !(0 == ~E_10~0); 49466#L1462-1 assume !(0 == ~E_11~0); 50922#L1467-1 assume !(0 == ~E_12~0); 50934#L1472-1 assume !(0 == ~E_13~0); 50935#L1477-1 assume !(0 == ~E_14~0); 50677#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 49664#L646 assume 1 == ~m_pc~0; 49665#L647 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 50341#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 50356#L658 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 49754#L1666 assume !(0 != activate_threads_~tmp~1#1); 49755#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 51232#L665 assume !(1 == ~t1_pc~0); 50230#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 50231#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 49763#L677 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 49764#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 50554#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 50555#L684 assume 1 == ~t2_pc~0; 50672#L685 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 50596#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 50661#L696 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 51056#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 51057#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 51245#L703 assume !(1 == ~t3_pc~0); 49900#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 49901#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 50547#L715 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 49299#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 49300#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 49785#L722 assume 1 == ~t4_pc~0; 50523#L723 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 49966#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 50311#L734 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 50871#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 50378#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 49496#L741 assume 1 == ~t5_pc~0; 49497#L742 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 49807#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 49961#L753 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 49962#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 50641#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 50052#L760 assume !(1 == ~t6_pc~0); 49899#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 49898#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 49756#L772 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 49757#L1714 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 50478#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 50479#L779 assume 1 == ~t7_pc~0; 49541#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 49387#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 49388#L791 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 49796#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 49819#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 49820#L798 assume !(1 == ~t8_pc~0); 51101#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 51024#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 49543#L810 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 49544#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 51234#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 49364#L817 assume 1 == ~t9_pc~0; 49365#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 50159#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 50160#L829 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 50682#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 49770#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 49771#L836 assume !(1 == ~t10_pc~0); 49787#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 49718#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 49719#L848 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 49967#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 49968#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 51034#L855 assume 1 == ~t11_pc~0; 50352#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 50353#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 50917#L867 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 50726#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 50561#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 49660#L874 assume !(1 == ~t12_pc~0); 49661#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 49828#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 49829#L886 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 49969#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 49337#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 49338#L893 assume 1 == ~t13_pc~0; 51168#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 49693#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 50004#L905 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 51095#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 51103#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 51104#L912 assume 1 == ~t14_pc~0; 50894#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 50895#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 49663#L924 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 49595#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 49596#L1778-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 50371#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 50787#L1495-2 assume !(1 == ~T1_E~0); 50788#L1500-1 assume !(1 == ~T2_E~0); 50474#L1505-1 assume !(1 == ~T3_E~0); 50475#L1510-1 assume !(1 == ~T4_E~0); 50532#L1515-1 assume !(1 == ~T5_E~0); 50533#L1520-1 assume !(1 == ~T6_E~0); 51102#L1525-1 assume !(1 == ~T7_E~0); 50812#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 49765#L1535-1 assume !(1 == ~T9_E~0); 49766#L1540-1 assume !(1 == ~T10_E~0); 49258#L1545-1 assume !(1 == ~T11_E~0); 49259#L1550-1 assume !(1 == ~T12_E~0); 49507#L1555-1 assume !(1 == ~T13_E~0); 49508#L1560-1 assume !(1 == ~T14_E~0); 49808#L1565-1 assume !(1 == ~E_1~0); 51221#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 50699#L1575-1 assume !(1 == ~E_3~0); 50078#L1580-1 assume !(1 == ~E_4~0); 50079#L1585-1 assume !(1 == ~E_5~0); 50549#L1590-1 assume !(1 == ~E_6~0); 50113#L1595-1 assume !(1 == ~E_7~0); 50114#L1600-1 assume !(1 == ~E_8~0); 50486#L1605-1 assume !(1 == ~E_9~0); 50487#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 51004#L1615-1 assume !(1 == ~E_11~0); 49943#L1620-1 assume !(1 == ~E_12~0); 49944#L1625-1 assume !(1 == ~E_13~0); 50731#L1630-1 assume !(1 == ~E_14~0); 50112#L1635-1 assume { :end_inline_reset_delta_events } true; 50053#L2017-2 [2021-12-16 10:06:18,480 INFO L793 eck$LassoCheckResult]: Loop: 50053#L2017-2 assume !false; 49333#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 49334#L1316 assume !false; 50662#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 50724#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 49271#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 49413#L1101 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 49414#L1115 assume !(0 != eval_~tmp~0#1); 50747#L1332 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 50168#L932-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 50169#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 50351#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 50852#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 50521#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 50522#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 51084#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 51259#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 51254#L1372-3 assume !(0 == ~T7_E~0); 49315#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 49316#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 49985#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 49986#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 50897#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 51207#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 50465#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 49621#L1412-3 assume !(0 == ~E_1~0); 49622#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 50386#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 50387#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 51081#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 50768#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 50480#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 50481#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 49381#L1452-3 assume !(0 == ~E_9~0); 49382#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 51020#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 51021#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 50825#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 50826#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 49619#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 49620#L646-42 assume 1 == ~m_pc~0; 50205#L647-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 51053#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 51054#L658-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 51192#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 51193#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 50985#L665-42 assume 1 == ~t1_pc~0; 50946#L666-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 50948#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 51134#L677-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 49788#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 49789#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 51258#L684-42 assume 1 == ~t2_pc~0; 50637#L685-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 50638#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 51248#L696-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 50417#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 50418#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 50540#L703-42 assume 1 == ~t3_pc~0; 50738#L704-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 50739#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 50057#L715-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 50058#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 50832#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 50452#L722-42 assume 1 == ~t4_pc~0; 50453#L723-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 50863#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 50106#L734-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 49933#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 49934#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 51228#L741-42 assume 1 == ~t5_pc~0; 51170#L742-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 50315#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 50316#L753-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 51261#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 50223#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 50224#L760-42 assume !(1 == ~t6_pc~0); 50358#L760-44 is_transmit6_triggered_~__retres1~6#1 := 0; 50493#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 50494#L772-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 50882#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 50175#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 50176#L779-42 assume !(1 == ~t7_pc~0); 50952#L779-44 is_transmit7_triggered_~__retres1~7#1 := 0; 50953#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 49862#L791-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 49863#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 49716#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 49717#L798-42 assume 1 == ~t8_pc~0; 50167#L799-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 49328#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 51071#L810-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 50517#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 49547#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 49548#L817-42 assume 1 == ~t9_pc~0; 50323#L818-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 49831#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 49832#L829-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 49958#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 50763#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 50764#L836-42 assume 1 == ~t10_pc~0; 50856#L837-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 49869#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 49870#L848-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 51171#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 51172#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 51213#L855-42 assume 1 == ~t11_pc~0; 51226#L856-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 49420#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 49421#L867-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 50170#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 50933#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 50034#L874-42 assume 1 == ~t12_pc~0; 50035#L875-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 50277#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 49335#L886-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 49336#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 49589#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 49590#L893-42 assume 1 == ~t13_pc~0; 50793#L894-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 50574#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 50589#L905-14 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 50491#L1770-42 assume !(0 != activate_threads_~tmp___12~0#1); 49963#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 49964#L912-42 assume !(1 == ~t14_pc~0); 50773#L912-44 is_transmit14_triggered_~__retres1~14#1 := 0; 49281#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 49282#L924-14 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 50862#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 49709#L1778-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 49710#L1495-3 assume !(1 == ~M_E~0); 50325#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 50753#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 50846#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 49939#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 49902#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 49903#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 50560#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 50783#L1530-3 assume !(1 == ~T8_E~0); 49748#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 49749#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 49786#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 51043#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 51152#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 50192#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 50193#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 50808#L1570-3 assume !(1 == ~E_2~0); 50759#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 50760#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 51115#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 51160#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 51205#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 50582#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 50583#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 51058#L1610-3 assume !(1 == ~E_10~0); 49945#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 49946#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 50550#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 50551#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 50455#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 49886#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 49491#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 50229#L1101-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 50785#L2036 assume !(0 == start_simulation_~tmp~3#1); 50786#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 50938#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 50098#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 51116#L1101-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 50498#L1991 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 50499#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 51219#L1999 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 51220#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 50053#L2017-2 [2021-12-16 10:06:18,481 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:18,481 INFO L85 PathProgramCache]: Analyzing trace with hash 1016333162, now seen corresponding path program 1 times [2021-12-16 10:06:18,481 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:18,481 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1733133942] [2021-12-16 10:06:18,481 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:18,481 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:18,491 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:06:18,503 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:06:18,503 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:06:18,503 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1733133942] [2021-12-16 10:06:18,503 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1733133942] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:06:18,503 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:06:18,504 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:06:18,504 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [902747668] [2021-12-16 10:06:18,504 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:06:18,505 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:06:18,505 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:18,505 INFO L85 PathProgramCache]: Analyzing trace with hash 464353134, now seen corresponding path program 1 times [2021-12-16 10:06:18,505 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:18,505 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [58659499] [2021-12-16 10:06:18,505 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:18,506 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:18,517 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:06:18,535 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:06:18,535 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:06:18,535 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [58659499] [2021-12-16 10:06:18,535 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [58659499] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:06:18,535 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:06:18,535 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:06:18,535 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1667416398] [2021-12-16 10:06:18,536 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:06:18,536 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:06:18,536 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:06:18,536 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-16 10:06:18,537 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-16 10:06:18,537 INFO L87 Difference]: Start difference. First operand 2047 states and 3023 transitions. cyclomatic complexity: 977 Second operand has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:18,555 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:06:18,555 INFO L93 Difference]: Finished difference Result 2047 states and 3022 transitions. [2021-12-16 10:06:18,555 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-16 10:06:18,556 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2047 states and 3022 transitions. [2021-12-16 10:06:18,561 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2021-12-16 10:06:18,567 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2047 states to 2047 states and 3022 transitions. [2021-12-16 10:06:18,567 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2047 [2021-12-16 10:06:18,568 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2047 [2021-12-16 10:06:18,568 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2047 states and 3022 transitions. [2021-12-16 10:06:18,570 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:06:18,570 INFO L681 BuchiCegarLoop]: Abstraction has 2047 states and 3022 transitions. [2021-12-16 10:06:18,572 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2047 states and 3022 transitions. [2021-12-16 10:06:18,609 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2047 to 2047. [2021-12-16 10:06:18,611 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2047 states, 2047 states have (on average 1.4763067904250122) internal successors, (3022), 2046 states have internal predecessors, (3022), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:18,614 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2047 states to 2047 states and 3022 transitions. [2021-12-16 10:06:18,614 INFO L704 BuchiCegarLoop]: Abstraction has 2047 states and 3022 transitions. [2021-12-16 10:06:18,614 INFO L587 BuchiCegarLoop]: Abstraction has 2047 states and 3022 transitions. [2021-12-16 10:06:18,614 INFO L425 BuchiCegarLoop]: ======== Iteration 14============ [2021-12-16 10:06:18,614 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2047 states and 3022 transitions. [2021-12-16 10:06:18,618 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2021-12-16 10:06:18,618 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:06:18,618 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:06:18,619 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:18,619 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:18,620 INFO L791 eck$LassoCheckResult]: Stem: 54252#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 54253#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 54855#L1980 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 53972#L932 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 53973#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 54218#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 54219#L944-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 53946#L949-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 53947#L954-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 55170#L959-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 54522#L964-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 54523#L969-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 55040#L974-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 54432#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 54433#L984-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 53853#L989-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 53854#L994-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 54185#L999-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 54383#L1004-1 assume !(1 == ~t14_i~0);~t14_st~0 := 2; 53430#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 53431#L1342 assume !(0 == ~M_E~0); 53596#L1342-2 assume !(0 == ~T1_E~0); 54152#L1347-1 assume !(0 == ~T2_E~0); 55153#L1352-1 assume !(0 == ~T3_E~0); 54949#L1357-1 assume !(0 == ~T4_E~0); 54177#L1362-1 assume !(0 == ~T5_E~0); 54178#L1367-1 assume !(0 == ~T6_E~0); 53775#L1372-1 assume 0 == ~T7_E~0;~T7_E~0 := 1; 53776#L1377-1 assume !(0 == ~T8_E~0); 54106#L1382-1 assume !(0 == ~T9_E~0); 54107#L1387-1 assume !(0 == ~T10_E~0); 54834#L1392-1 assume !(0 == ~T11_E~0); 54138#L1397-1 assume !(0 == ~T12_E~0); 54139#L1402-1 assume !(0 == ~T13_E~0); 53791#L1407-1 assume !(0 == ~T14_E~0); 53792#L1412-1 assume 0 == ~E_1~0;~E_1~0 := 1; 55070#L1417-1 assume !(0 == ~E_2~0); 55071#L1422-1 assume !(0 == ~E_3~0); 55312#L1427-1 assume !(0 == ~E_4~0); 53979#L1432-1 assume !(0 == ~E_5~0); 53980#L1437-1 assume !(0 == ~E_6~0); 54988#L1442-1 assume !(0 == ~E_7~0); 54989#L1447-1 assume !(0 == ~E_8~0); 54831#L1452-1 assume 0 == ~E_9~0;~E_9~0 := 1; 53566#L1457-1 assume !(0 == ~E_10~0); 53567#L1462-1 assume !(0 == ~E_11~0); 55023#L1467-1 assume !(0 == ~E_12~0); 55035#L1472-1 assume !(0 == ~E_13~0); 55036#L1477-1 assume !(0 == ~E_14~0); 54778#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 53765#L646 assume 1 == ~m_pc~0; 53766#L647 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 54442#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 54457#L658 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 53855#L1666 assume !(0 != activate_threads_~tmp~1#1); 53856#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 55333#L665 assume !(1 == ~t1_pc~0); 54331#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 54332#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 53864#L677 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 53865#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 54655#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 54656#L684 assume 1 == ~t2_pc~0; 54773#L685 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 54697#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 54762#L696 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 55157#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 55158#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 55346#L703 assume !(1 == ~t3_pc~0); 54001#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 54002#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 54648#L715 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 53400#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 53401#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 53886#L722 assume 1 == ~t4_pc~0; 54624#L723 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 54067#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 54412#L734 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 54972#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 54479#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 53597#L741 assume 1 == ~t5_pc~0; 53598#L742 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 53908#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 54062#L753 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 54063#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 54742#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 54153#L760 assume !(1 == ~t6_pc~0); 54000#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 53999#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 53857#L772 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 53858#L1714 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 54579#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 54580#L779 assume 1 == ~t7_pc~0; 53642#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 53488#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 53489#L791 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 53897#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 53920#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 53921#L798 assume !(1 == ~t8_pc~0); 55202#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 55125#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 53644#L810 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 53645#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 55335#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 53465#L817 assume 1 == ~t9_pc~0; 53466#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 54260#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 54261#L829 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 54783#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 53871#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 53872#L836 assume !(1 == ~t10_pc~0); 53888#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 53819#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 53820#L848 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 54068#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 54069#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 55135#L855 assume 1 == ~t11_pc~0; 54453#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 54454#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 55018#L867 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 54827#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 54662#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 53761#L874 assume !(1 == ~t12_pc~0); 53762#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 53929#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 53930#L886 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 54070#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 53438#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 53439#L893 assume 1 == ~t13_pc~0; 55269#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 53794#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 54105#L905 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 55196#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 55204#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 55205#L912 assume 1 == ~t14_pc~0; 54995#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 54996#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 53764#L924 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 53696#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 53697#L1778-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 54472#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 54888#L1495-2 assume !(1 == ~T1_E~0); 54889#L1500-1 assume !(1 == ~T2_E~0); 54575#L1505-1 assume !(1 == ~T3_E~0); 54576#L1510-1 assume !(1 == ~T4_E~0); 54633#L1515-1 assume !(1 == ~T5_E~0); 54634#L1520-1 assume !(1 == ~T6_E~0); 55203#L1525-1 assume !(1 == ~T7_E~0); 54913#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 53866#L1535-1 assume !(1 == ~T9_E~0); 53867#L1540-1 assume !(1 == ~T10_E~0); 53359#L1545-1 assume !(1 == ~T11_E~0); 53360#L1550-1 assume !(1 == ~T12_E~0); 53608#L1555-1 assume !(1 == ~T13_E~0); 53609#L1560-1 assume !(1 == ~T14_E~0); 53909#L1565-1 assume !(1 == ~E_1~0); 55322#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 54800#L1575-1 assume !(1 == ~E_3~0); 54179#L1580-1 assume !(1 == ~E_4~0); 54180#L1585-1 assume !(1 == ~E_5~0); 54650#L1590-1 assume !(1 == ~E_6~0); 54214#L1595-1 assume !(1 == ~E_7~0); 54215#L1600-1 assume !(1 == ~E_8~0); 54587#L1605-1 assume !(1 == ~E_9~0); 54588#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 55105#L1615-1 assume !(1 == ~E_11~0); 54044#L1620-1 assume !(1 == ~E_12~0); 54045#L1625-1 assume !(1 == ~E_13~0); 54832#L1630-1 assume !(1 == ~E_14~0); 54213#L1635-1 assume { :end_inline_reset_delta_events } true; 54154#L2017-2 [2021-12-16 10:06:18,620 INFO L793 eck$LassoCheckResult]: Loop: 54154#L2017-2 assume !false; 53434#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 53435#L1316 assume !false; 54763#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 54825#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 53372#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 53514#L1101 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 53515#L1115 assume !(0 != eval_~tmp~0#1); 54848#L1332 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 54269#L932-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 54270#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 54452#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 54953#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 54622#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 54623#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 55185#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 55360#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 55355#L1372-3 assume !(0 == ~T7_E~0); 53416#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 53417#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 54086#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 54087#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 54998#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 55308#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 54566#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 53722#L1412-3 assume !(0 == ~E_1~0); 53723#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 54487#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 54488#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 55182#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 54869#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 54581#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 54582#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 53482#L1452-3 assume !(0 == ~E_9~0); 53483#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 55121#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 55122#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 54926#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 54927#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 53720#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 53721#L646-42 assume 1 == ~m_pc~0; 54306#L647-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 55154#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 55155#L658-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 55293#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 55294#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 55086#L665-42 assume 1 == ~t1_pc~0; 55047#L666-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 55049#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 55235#L677-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 53889#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 53890#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 55359#L684-42 assume 1 == ~t2_pc~0; 54738#L685-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 54739#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 55349#L696-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 54518#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 54519#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 54641#L703-42 assume 1 == ~t3_pc~0; 54839#L704-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 54840#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 54158#L715-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 54159#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 54933#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 54553#L722-42 assume 1 == ~t4_pc~0; 54554#L723-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 54964#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 54207#L734-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 54034#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 54035#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 55329#L741-42 assume !(1 == ~t5_pc~0); 54946#L741-44 is_transmit5_triggered_~__retres1~5#1 := 0; 54416#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 54417#L753-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 55362#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 54324#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 54325#L760-42 assume !(1 == ~t6_pc~0); 54459#L760-44 is_transmit6_triggered_~__retres1~6#1 := 0; 54594#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 54595#L772-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 54983#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 54276#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 54277#L779-42 assume 1 == ~t7_pc~0; 55106#L780-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 55054#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 53963#L791-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 53964#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 53817#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 53818#L798-42 assume !(1 == ~t8_pc~0); 53428#L798-44 is_transmit8_triggered_~__retres1~8#1 := 0; 53429#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 55172#L810-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 54618#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 53648#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 53649#L817-42 assume 1 == ~t9_pc~0; 54424#L818-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 53932#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 53933#L829-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 54059#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 54864#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 54865#L836-42 assume 1 == ~t10_pc~0; 54957#L837-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 53970#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 53971#L848-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 55272#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 55273#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 55314#L855-42 assume !(1 == ~t11_pc~0); 55328#L855-44 is_transmit11_triggered_~__retres1~11#1 := 0; 53521#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 53522#L867-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 54271#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 55034#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 54135#L874-42 assume 1 == ~t12_pc~0; 54136#L875-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 54378#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 53436#L886-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 53437#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 53690#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 53691#L893-42 assume !(1 == ~t13_pc~0); 54674#L893-44 is_transmit13_triggered_~__retres1~13#1 := 0; 54675#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 54690#L905-14 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 54592#L1770-42 assume !(0 != activate_threads_~tmp___12~0#1); 54064#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 54065#L912-42 assume !(1 == ~t14_pc~0); 54874#L912-44 is_transmit14_triggered_~__retres1~14#1 := 0; 53382#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 53383#L924-14 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 54963#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 53810#L1778-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 53811#L1495-3 assume !(1 == ~M_E~0); 54426#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 54854#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 54947#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 54040#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 54003#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 54004#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 54661#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 54884#L1530-3 assume !(1 == ~T8_E~0); 53849#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 53850#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 53887#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 55144#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 55253#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 54293#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 54294#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 54909#L1570-3 assume !(1 == ~E_2~0); 54860#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 54861#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 55216#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 55261#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 55306#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 54683#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 54684#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 55159#L1610-3 assume !(1 == ~E_10~0); 54046#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 54047#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 54651#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 54652#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 54556#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 53987#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 53592#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 54330#L1101-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 54886#L2036 assume !(0 == start_simulation_~tmp~3#1); 54887#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 55039#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 54199#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 55217#L1101-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 54599#L1991 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 54600#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 55320#L1999 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 55321#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 54154#L2017-2 [2021-12-16 10:06:18,621 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:18,622 INFO L85 PathProgramCache]: Analyzing trace with hash -1873442456, now seen corresponding path program 1 times [2021-12-16 10:06:18,622 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:18,622 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1469124745] [2021-12-16 10:06:18,622 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:18,622 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:18,630 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:06:18,643 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:06:18,643 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:06:18,643 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1469124745] [2021-12-16 10:06:18,643 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1469124745] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:06:18,644 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:06:18,644 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:06:18,644 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [928904256] [2021-12-16 10:06:18,644 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:06:18,645 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:06:18,646 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:18,646 INFO L85 PathProgramCache]: Analyzing trace with hash 1401714763, now seen corresponding path program 1 times [2021-12-16 10:06:18,646 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:18,646 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [727239005] [2021-12-16 10:06:18,646 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:18,647 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:18,657 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:06:18,673 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:06:18,673 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:06:18,673 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [727239005] [2021-12-16 10:06:18,674 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [727239005] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:06:18,674 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:06:18,674 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:06:18,674 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [848273166] [2021-12-16 10:06:18,674 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:06:18,674 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:06:18,675 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:06:18,675 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-16 10:06:18,675 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-16 10:06:18,675 INFO L87 Difference]: Start difference. First operand 2047 states and 3022 transitions. cyclomatic complexity: 976 Second operand has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:18,693 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:06:18,693 INFO L93 Difference]: Finished difference Result 2047 states and 3021 transitions. [2021-12-16 10:06:18,694 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-16 10:06:18,694 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2047 states and 3021 transitions. [2021-12-16 10:06:18,699 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2021-12-16 10:06:18,702 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2047 states to 2047 states and 3021 transitions. [2021-12-16 10:06:18,702 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2047 [2021-12-16 10:06:18,703 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2047 [2021-12-16 10:06:18,703 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2047 states and 3021 transitions. [2021-12-16 10:06:18,705 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:06:18,705 INFO L681 BuchiCegarLoop]: Abstraction has 2047 states and 3021 transitions. [2021-12-16 10:06:18,707 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2047 states and 3021 transitions. [2021-12-16 10:06:18,720 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2047 to 2047. [2021-12-16 10:06:18,721 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2047 states, 2047 states have (on average 1.475818270639961) internal successors, (3021), 2046 states have internal predecessors, (3021), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:18,724 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2047 states to 2047 states and 3021 transitions. [2021-12-16 10:06:18,724 INFO L704 BuchiCegarLoop]: Abstraction has 2047 states and 3021 transitions. [2021-12-16 10:06:18,724 INFO L587 BuchiCegarLoop]: Abstraction has 2047 states and 3021 transitions. [2021-12-16 10:06:18,724 INFO L425 BuchiCegarLoop]: ======== Iteration 15============ [2021-12-16 10:06:18,724 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2047 states and 3021 transitions. [2021-12-16 10:06:18,729 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2021-12-16 10:06:18,729 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:06:18,729 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:06:18,730 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:18,730 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:18,731 INFO L791 eck$LassoCheckResult]: Stem: 58353#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 58354#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 58956#L1980 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 58073#L932 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 58074#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 58319#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 58320#L944-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 58047#L949-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 58048#L954-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 59271#L959-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 58623#L964-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 58624#L969-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 59141#L974-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 58533#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 58534#L984-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 57954#L989-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 57955#L994-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 58286#L999-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 58484#L1004-1 assume 1 == ~t14_i~0;~t14_st~0 := 0; 57531#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 57532#L1342 assume !(0 == ~M_E~0); 57697#L1342-2 assume !(0 == ~T1_E~0); 58253#L1347-1 assume !(0 == ~T2_E~0); 59254#L1352-1 assume !(0 == ~T3_E~0); 59050#L1357-1 assume !(0 == ~T4_E~0); 58278#L1362-1 assume !(0 == ~T5_E~0); 58279#L1367-1 assume !(0 == ~T6_E~0); 57876#L1372-1 assume 0 == ~T7_E~0;~T7_E~0 := 1; 57877#L1377-1 assume !(0 == ~T8_E~0); 58207#L1382-1 assume !(0 == ~T9_E~0); 58208#L1387-1 assume !(0 == ~T10_E~0); 58935#L1392-1 assume !(0 == ~T11_E~0); 58239#L1397-1 assume !(0 == ~T12_E~0); 58240#L1402-1 assume !(0 == ~T13_E~0); 57892#L1407-1 assume !(0 == ~T14_E~0); 57893#L1412-1 assume 0 == ~E_1~0;~E_1~0 := 1; 59171#L1417-1 assume !(0 == ~E_2~0); 59172#L1422-1 assume !(0 == ~E_3~0); 59413#L1427-1 assume !(0 == ~E_4~0); 58080#L1432-1 assume !(0 == ~E_5~0); 58081#L1437-1 assume !(0 == ~E_6~0); 59089#L1442-1 assume !(0 == ~E_7~0); 59090#L1447-1 assume !(0 == ~E_8~0); 58932#L1452-1 assume 0 == ~E_9~0;~E_9~0 := 1; 57667#L1457-1 assume !(0 == ~E_10~0); 57668#L1462-1 assume !(0 == ~E_11~0); 59124#L1467-1 assume !(0 == ~E_12~0); 59136#L1472-1 assume !(0 == ~E_13~0); 59137#L1477-1 assume !(0 == ~E_14~0); 58879#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 57868#L646 assume 1 == ~m_pc~0; 57869#L647 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 58543#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 58558#L658 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 57956#L1666 assume !(0 != activate_threads_~tmp~1#1); 57957#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 59434#L665 assume !(1 == ~t1_pc~0); 58432#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 58433#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 57965#L677 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 57966#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 58756#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 58757#L684 assume 1 == ~t2_pc~0; 58874#L685 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 58798#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 58863#L696 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 59258#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 59259#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 59447#L703 assume !(1 == ~t3_pc~0); 58102#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 58103#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 58749#L715 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 57501#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 57502#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 57987#L722 assume 1 == ~t4_pc~0; 58725#L723 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 58168#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 58513#L734 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 59073#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 58580#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 57698#L741 assume 1 == ~t5_pc~0; 57699#L742 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 58009#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 58163#L753 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 58164#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 58843#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 58254#L760 assume !(1 == ~t6_pc~0); 58101#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 58100#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 57958#L772 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 57959#L1714 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 58680#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 58681#L779 assume 1 == ~t7_pc~0; 57743#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 57589#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 57590#L791 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 57998#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 58021#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 58022#L798 assume !(1 == ~t8_pc~0); 59303#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 59226#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 57745#L810 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 57746#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 59436#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 57566#L817 assume 1 == ~t9_pc~0; 57567#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 58361#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 58362#L829 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 58884#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 57972#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 57973#L836 assume !(1 == ~t10_pc~0); 57989#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 57920#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 57921#L848 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 58169#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 58170#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 59236#L855 assume 1 == ~t11_pc~0; 58554#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 58555#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 59119#L867 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 58928#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 58763#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 57862#L874 assume !(1 == ~t12_pc~0); 57863#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 58030#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 58031#L886 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 58171#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 57539#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 57540#L893 assume 1 == ~t13_pc~0; 59370#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 57895#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 58206#L905 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 59297#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 59305#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 59306#L912 assume 1 == ~t14_pc~0; 59096#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 59097#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 57865#L924 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 57797#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 57798#L1778-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 58573#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 58989#L1495-2 assume !(1 == ~T1_E~0); 58990#L1500-1 assume !(1 == ~T2_E~0); 58676#L1505-1 assume !(1 == ~T3_E~0); 58677#L1510-1 assume !(1 == ~T4_E~0); 58734#L1515-1 assume !(1 == ~T5_E~0); 58735#L1520-1 assume !(1 == ~T6_E~0); 59304#L1525-1 assume !(1 == ~T7_E~0); 59014#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 57967#L1535-1 assume !(1 == ~T9_E~0); 57968#L1540-1 assume !(1 == ~T10_E~0); 57460#L1545-1 assume !(1 == ~T11_E~0); 57461#L1550-1 assume !(1 == ~T12_E~0); 57709#L1555-1 assume !(1 == ~T13_E~0); 57710#L1560-1 assume !(1 == ~T14_E~0); 58010#L1565-1 assume !(1 == ~E_1~0); 59423#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 58901#L1575-1 assume !(1 == ~E_3~0); 58280#L1580-1 assume !(1 == ~E_4~0); 58281#L1585-1 assume !(1 == ~E_5~0); 58751#L1590-1 assume !(1 == ~E_6~0); 58315#L1595-1 assume !(1 == ~E_7~0); 58316#L1600-1 assume !(1 == ~E_8~0); 58688#L1605-1 assume !(1 == ~E_9~0); 58689#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 59206#L1615-1 assume !(1 == ~E_11~0); 58145#L1620-1 assume !(1 == ~E_12~0); 58146#L1625-1 assume !(1 == ~E_13~0); 58933#L1630-1 assume !(1 == ~E_14~0); 58314#L1635-1 assume { :end_inline_reset_delta_events } true; 58255#L2017-2 [2021-12-16 10:06:18,731 INFO L793 eck$LassoCheckResult]: Loop: 58255#L2017-2 assume !false; 57535#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 57536#L1316 assume !false; 58864#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 58926#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 57473#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 57615#L1101 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 57616#L1115 assume !(0 != eval_~tmp~0#1); 58949#L1332 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 58370#L932-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 58371#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 58553#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 59054#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 58723#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 58724#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 59286#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 59461#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 59456#L1372-3 assume !(0 == ~T7_E~0); 57517#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 57518#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 58187#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 58188#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 59099#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 59409#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 58667#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 57823#L1412-3 assume !(0 == ~E_1~0); 57824#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 58588#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 58589#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 59283#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 58970#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 58682#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 58683#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 57583#L1452-3 assume !(0 == ~E_9~0); 57584#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 59222#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 59223#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 59027#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 59028#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 57821#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 57822#L646-42 assume 1 == ~m_pc~0; 58407#L647-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 59255#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 59256#L658-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 59394#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 59395#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 59187#L665-42 assume 1 == ~t1_pc~0; 59148#L666-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 59150#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 59336#L677-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 57990#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 57991#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 59460#L684-42 assume 1 == ~t2_pc~0; 58839#L685-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 58840#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 59450#L696-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 58619#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 58620#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 58742#L703-42 assume 1 == ~t3_pc~0; 58940#L704-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 58941#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 58259#L715-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 58260#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 59034#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 58654#L722-42 assume !(1 == ~t4_pc~0); 58656#L722-44 is_transmit4_triggered_~__retres1~4#1 := 0; 59065#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 58308#L734-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 58135#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 58136#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 59430#L741-42 assume !(1 == ~t5_pc~0); 59047#L741-44 is_transmit5_triggered_~__retres1~5#1 := 0; 58517#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 58518#L753-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 59463#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 58425#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 58426#L760-42 assume !(1 == ~t6_pc~0); 58560#L760-44 is_transmit6_triggered_~__retres1~6#1 := 0; 58695#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 58696#L772-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 59084#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 58377#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 58378#L779-42 assume !(1 == ~t7_pc~0); 59154#L779-44 is_transmit7_triggered_~__retres1~7#1 := 0; 59155#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 58064#L791-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 58065#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 57918#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 57919#L798-42 assume 1 == ~t8_pc~0; 58369#L799-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 57530#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 59273#L810-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 58719#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 57749#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 57750#L817-42 assume 1 == ~t9_pc~0; 58525#L818-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 58033#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 58034#L829-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 58160#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 58965#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 58966#L836-42 assume 1 == ~t10_pc~0; 59058#L837-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 58071#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 58072#L848-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 59373#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 59374#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 59415#L855-42 assume 1 == ~t11_pc~0; 59428#L856-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 57622#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 57623#L867-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 58372#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 59135#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 58236#L874-42 assume 1 == ~t12_pc~0; 58237#L875-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 58479#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 57537#L886-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 57538#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 57791#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 57792#L893-42 assume 1 == ~t13_pc~0; 58995#L894-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 58776#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 58791#L905-14 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 58693#L1770-42 assume !(0 != activate_threads_~tmp___12~0#1); 58165#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 58166#L912-42 assume 1 == ~t14_pc~0; 59410#L913-14 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 57483#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 57484#L924-14 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 59064#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 57911#L1778-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 57912#L1495-3 assume !(1 == ~M_E~0); 58527#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 58955#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 59048#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 58141#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 58104#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 58105#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 58762#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 58985#L1530-3 assume !(1 == ~T8_E~0); 57950#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 57951#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 57988#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 59245#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 59354#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 58394#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 58395#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 59010#L1570-3 assume !(1 == ~E_2~0); 58961#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 58962#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 59317#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 59362#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 59407#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 58784#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 58785#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 59260#L1610-3 assume !(1 == ~E_10~0); 58147#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 58148#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 58752#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 58753#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 58657#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 58088#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 57693#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 58431#L1101-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 58987#L2036 assume !(0 == start_simulation_~tmp~3#1); 58988#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 59140#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 58300#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 59318#L1101-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 58700#L1991 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 58701#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 59421#L1999 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 59422#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 58255#L2017-2 [2021-12-16 10:06:18,731 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:18,732 INFO L85 PathProgramCache]: Analyzing trace with hash 527190954, now seen corresponding path program 1 times [2021-12-16 10:06:18,732 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:18,732 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1511741408] [2021-12-16 10:06:18,732 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:18,732 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:18,741 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:06:18,757 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:06:18,758 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:06:18,758 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1511741408] [2021-12-16 10:06:18,758 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1511741408] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:06:18,758 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:06:18,758 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:06:18,758 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [303866158] [2021-12-16 10:06:18,758 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:06:18,759 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:06:18,759 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:18,759 INFO L85 PathProgramCache]: Analyzing trace with hash 1014754381, now seen corresponding path program 1 times [2021-12-16 10:06:18,759 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:18,759 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1182154164] [2021-12-16 10:06:18,759 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:18,760 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:18,768 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:06:18,783 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:06:18,783 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:06:18,783 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1182154164] [2021-12-16 10:06:18,784 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1182154164] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:06:18,784 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:06:18,784 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:06:18,784 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [608832443] [2021-12-16 10:06:18,784 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:06:18,784 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:06:18,784 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:06:18,785 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-16 10:06:18,785 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-16 10:06:18,785 INFO L87 Difference]: Start difference. First operand 2047 states and 3021 transitions. cyclomatic complexity: 975 Second operand has 4 states, 4 states have (on average 42.5) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:18,901 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:06:18,901 INFO L93 Difference]: Finished difference Result 3802 states and 5594 transitions. [2021-12-16 10:06:18,902 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-16 10:06:18,902 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3802 states and 5594 transitions. [2021-12-16 10:06:18,911 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3588 [2021-12-16 10:06:18,917 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3802 states to 3802 states and 5594 transitions. [2021-12-16 10:06:18,917 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3802 [2021-12-16 10:06:18,919 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3802 [2021-12-16 10:06:18,919 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3802 states and 5594 transitions. [2021-12-16 10:06:18,922 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:06:18,922 INFO L681 BuchiCegarLoop]: Abstraction has 3802 states and 5594 transitions. [2021-12-16 10:06:18,924 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3802 states and 5594 transitions. [2021-12-16 10:06:18,952 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3802 to 3802. [2021-12-16 10:06:18,955 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3802 states, 3802 states have (on average 1.4713308784850079) internal successors, (5594), 3801 states have internal predecessors, (5594), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:18,961 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3802 states to 3802 states and 5594 transitions. [2021-12-16 10:06:18,961 INFO L704 BuchiCegarLoop]: Abstraction has 3802 states and 5594 transitions. [2021-12-16 10:06:18,961 INFO L587 BuchiCegarLoop]: Abstraction has 3802 states and 5594 transitions. [2021-12-16 10:06:18,962 INFO L425 BuchiCegarLoop]: ======== Iteration 16============ [2021-12-16 10:06:18,962 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3802 states and 5594 transitions. [2021-12-16 10:06:18,967 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3588 [2021-12-16 10:06:18,968 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:06:18,968 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:06:18,969 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:18,969 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:18,969 INFO L791 eck$LassoCheckResult]: Stem: 64214#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 64215#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 64820#L1980 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 63934#L932 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 63935#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 64180#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 64181#L944-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 63908#L949-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 63909#L954-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 65160#L959-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 64485#L964-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 64486#L969-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 65018#L974-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 64394#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 64395#L984-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 63815#L989-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 63816#L994-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 64147#L999-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 64345#L1004-1 assume 1 == ~t14_i~0;~t14_st~0 := 0; 63390#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 63391#L1342 assume !(0 == ~M_E~0); 63556#L1342-2 assume !(0 == ~T1_E~0); 64114#L1347-1 assume !(0 == ~T2_E~0); 65141#L1352-1 assume !(0 == ~T3_E~0); 64919#L1357-1 assume !(0 == ~T4_E~0); 64139#L1362-1 assume !(0 == ~T5_E~0); 64140#L1367-1 assume !(0 == ~T6_E~0); 63737#L1372-1 assume !(0 == ~T7_E~0); 63738#L1377-1 assume !(0 == ~T8_E~0); 64068#L1382-1 assume !(0 == ~T9_E~0); 64069#L1387-1 assume !(0 == ~T10_E~0); 64799#L1392-1 assume !(0 == ~T11_E~0); 64100#L1397-1 assume !(0 == ~T12_E~0); 64101#L1402-1 assume !(0 == ~T13_E~0); 63753#L1407-1 assume !(0 == ~T14_E~0); 63754#L1412-1 assume 0 == ~E_1~0;~E_1~0 := 1; 65049#L1417-1 assume !(0 == ~E_2~0); 65050#L1422-1 assume !(0 == ~E_3~0); 65342#L1427-1 assume !(0 == ~E_4~0); 63941#L1432-1 assume !(0 == ~E_5~0); 63942#L1437-1 assume !(0 == ~E_6~0); 64961#L1442-1 assume !(0 == ~E_7~0); 64962#L1447-1 assume !(0 == ~E_8~0); 64796#L1452-1 assume 0 == ~E_9~0;~E_9~0 := 1; 63526#L1457-1 assume !(0 == ~E_10~0); 63527#L1462-1 assume !(0 == ~E_11~0); 64998#L1467-1 assume !(0 == ~E_12~0); 65013#L1472-1 assume !(0 == ~E_13~0); 65014#L1477-1 assume !(0 == ~E_14~0); 64743#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 63727#L646 assume 1 == ~m_pc~0; 63728#L647 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 64404#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 64419#L658 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 63817#L1666 assume !(0 != activate_threads_~tmp~1#1); 63818#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 65375#L665 assume !(1 == ~t1_pc~0); 64293#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 64294#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 63826#L677 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 63827#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 64619#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 64620#L684 assume 1 == ~t2_pc~0; 64738#L685 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 64661#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 64727#L696 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 65145#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 65146#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 65390#L703 assume !(1 == ~t3_pc~0); 63963#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 63964#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 64612#L715 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 63360#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 63361#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 63848#L722 assume 1 == ~t4_pc~0; 64587#L723 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 64029#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 64374#L734 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 64945#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 64442#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 63557#L741 assume 1 == ~t5_pc~0; 63558#L742 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 63870#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 64024#L753 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 64025#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 64706#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 64115#L760 assume !(1 == ~t6_pc~0); 63962#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 63961#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 63819#L772 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 63820#L1714 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 64542#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 64543#L779 assume 1 == ~t7_pc~0; 63602#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 63448#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 63449#L791 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 63859#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 63882#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 63883#L798 assume !(1 == ~t8_pc~0); 65201#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 65107#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 63604#L810 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 63605#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 65377#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 63425#L817 assume 1 == ~t9_pc~0; 63426#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 64222#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 64223#L829 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 64748#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 63833#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 63834#L836 assume !(1 == ~t10_pc~0); 63850#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 63781#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 63782#L848 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 64030#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 64031#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 65121#L855 assume 1 == ~t11_pc~0; 64415#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 64416#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 64993#L867 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 64792#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 64626#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 63723#L874 assume !(1 == ~t12_pc~0); 63724#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 63891#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 63892#L886 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 64032#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 63398#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 63399#L893 assume 1 == ~t13_pc~0; 65284#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 63756#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 64067#L905 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 65195#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 65204#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 65205#L912 assume 1 == ~t14_pc~0; 64968#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 64969#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 63726#L924 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 63656#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 63657#L1778-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 64435#L1495 assume !(1 == ~M_E~0); 64854#L1495-2 assume !(1 == ~T1_E~0); 64855#L1500-1 assume !(1 == ~T2_E~0); 64538#L1505-1 assume !(1 == ~T3_E~0); 64539#L1510-1 assume !(1 == ~T4_E~0); 64597#L1515-1 assume !(1 == ~T5_E~0); 64598#L1520-1 assume !(1 == ~T6_E~0); 65202#L1525-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 65203#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 66479#L1535-1 assume !(1 == ~T9_E~0); 66477#L1540-1 assume !(1 == ~T10_E~0); 66475#L1545-1 assume !(1 == ~T11_E~0); 66473#L1550-1 assume !(1 == ~T12_E~0); 66472#L1555-1 assume !(1 == ~T13_E~0); 66471#L1560-1 assume !(1 == ~T14_E~0); 66470#L1565-1 assume !(1 == ~E_1~0); 65703#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 65702#L1575-1 assume !(1 == ~E_3~0); 65699#L1580-1 assume !(1 == ~E_4~0); 65697#L1585-1 assume !(1 == ~E_5~0); 65529#L1590-1 assume !(1 == ~E_6~0); 65528#L1595-1 assume !(1 == ~E_7~0); 65526#L1600-1 assume !(1 == ~E_8~0); 65524#L1605-1 assume !(1 == ~E_9~0); 65522#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 65520#L1615-1 assume !(1 == ~E_11~0); 65518#L1620-1 assume !(1 == ~E_12~0); 64944#L1625-1 assume !(1 == ~E_13~0); 64797#L1630-1 assume !(1 == ~E_14~0); 64175#L1635-1 assume { :end_inline_reset_delta_events } true; 64116#L2017-2 [2021-12-16 10:06:18,969 INFO L793 eck$LassoCheckResult]: Loop: 64116#L2017-2 assume !false; 63394#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 63395#L1316 assume !false; 64728#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 64790#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 63332#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 63474#L1101 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 63475#L1115 assume !(0 != eval_~tmp~0#1); 64813#L1332 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 65435#L932-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 65434#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 64923#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 64924#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 64585#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 64586#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 65179#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 65409#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 65403#L1372-3 assume !(0 == ~T7_E~0); 63376#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 63377#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 64048#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 64049#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 64971#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 65338#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 64529#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 63684#L1412-3 assume !(0 == ~E_1~0); 63685#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 64450#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 64451#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 65175#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 64834#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 64544#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 64545#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 63442#L1452-3 assume !(0 == ~E_9~0); 63443#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 65103#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 65104#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 64894#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 64895#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 63682#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 63683#L646-42 assume 1 == ~m_pc~0; 64268#L647-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 65142#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 65143#L658-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 65316#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 65317#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 65065#L665-42 assume 1 == ~t1_pc~0; 65025#L666-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 65027#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 65245#L677-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 63851#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 63852#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 65408#L684-42 assume !(1 == ~t2_pc~0); 64704#L684-44 is_transmit2_triggered_~__retres1~2#1 := 0; 64703#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 65394#L696-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 64481#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 64482#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 64605#L703-42 assume 1 == ~t3_pc~0; 64804#L704-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 64805#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 64120#L715-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 64121#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 64901#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 64516#L722-42 assume 1 == ~t4_pc~0; 64517#L723-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 64936#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 64169#L734-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 63996#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 63997#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 65365#L741-42 assume !(1 == ~t5_pc~0); 64914#L741-44 is_transmit5_triggered_~__retres1~5#1 := 0; 64378#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 64379#L753-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 65413#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 64286#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 64287#L760-42 assume !(1 == ~t6_pc~0); 64421#L760-44 is_transmit6_triggered_~__retres1~6#1 := 0; 64557#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 64558#L772-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 64956#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 64238#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 64239#L779-42 assume 1 == ~t7_pc~0; 65088#L780-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 65033#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 63923#L791-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 63924#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 63779#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 63780#L798-42 assume 1 == ~t8_pc~0; 64230#L799-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 63389#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 65162#L810-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 64581#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 63608#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 63609#L817-42 assume 1 == ~t9_pc~0; 64384#L818-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 63894#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 63895#L829-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 64021#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 64829#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 64830#L836-42 assume 1 == ~t10_pc~0; 64928#L837-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 63932#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 63933#L848-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 65289#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 65290#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 65345#L855-42 assume 1 == ~t11_pc~0; 65362#L856-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 63481#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 63482#L867-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 64233#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 65012#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 64097#L874-42 assume 1 == ~t12_pc~0; 64098#L875-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 64337#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 63396#L886-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 63397#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 63650#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 63651#L893-42 assume 1 == ~t13_pc~0; 64859#L894-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 64639#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 64654#L905-14 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 64555#L1770-42 assume !(0 != activate_threads_~tmp___12~0#1); 64026#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 64027#L912-42 assume !(1 == ~t14_pc~0); 64839#L912-44 is_transmit14_triggered_~__retres1~14#1 := 0; 63342#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 63343#L924-14 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 64935#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 63772#L1778-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 63773#L1495-3 assume !(1 == ~M_E~0); 64388#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 64819#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 64916#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 64001#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 63965#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 63966#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 64625#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 64850#L1530-3 assume !(1 == ~T8_E~0); 63811#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 63812#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 63849#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 65131#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 65266#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 64255#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 64256#L1565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 64875#L1570-3 assume !(1 == ~E_2~0); 64825#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 64826#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 65221#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 65275#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 65336#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 64647#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 64648#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 65147#L1610-3 assume !(1 == ~E_10~0); 64008#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 64009#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 64615#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 64616#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 64519#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 63949#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 63552#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 64292#L1101-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 64852#L2036 assume !(0 == start_simulation_~tmp~3#1); 64853#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 65017#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 65222#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 65223#L1101-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 64562#L1991 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 64563#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 65352#L1999 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 65353#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 64116#L2017-2 [2021-12-16 10:06:18,970 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:18,970 INFO L85 PathProgramCache]: Analyzing trace with hash -1513151256, now seen corresponding path program 1 times [2021-12-16 10:06:18,970 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:18,970 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1313230093] [2021-12-16 10:06:18,970 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:18,970 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:18,979 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:06:19,009 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:06:19,010 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:06:19,010 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1313230093] [2021-12-16 10:06:19,010 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1313230093] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:06:19,010 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:06:19,010 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-16 10:06:19,010 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2053327190] [2021-12-16 10:06:19,010 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:06:19,011 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:06:19,011 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:19,011 INFO L85 PathProgramCache]: Analyzing trace with hash 1703505037, now seen corresponding path program 1 times [2021-12-16 10:06:19,011 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:19,011 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [796220008] [2021-12-16 10:06:19,012 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:19,012 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:19,021 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:06:19,038 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:06:19,038 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:06:19,039 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [796220008] [2021-12-16 10:06:19,039 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [796220008] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:06:19,039 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:06:19,039 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:06:19,039 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1240422304] [2021-12-16 10:06:19,039 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:06:19,039 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:06:19,040 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:06:19,040 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-16 10:06:19,040 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-16 10:06:19,040 INFO L87 Difference]: Start difference. First operand 3802 states and 5594 transitions. cyclomatic complexity: 1794 Second operand has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 2 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:19,092 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:06:19,092 INFO L93 Difference]: Finished difference Result 3802 states and 5558 transitions. [2021-12-16 10:06:19,093 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-16 10:06:19,093 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3802 states and 5558 transitions. [2021-12-16 10:06:19,104 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3588 [2021-12-16 10:06:19,111 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3802 states to 3802 states and 5558 transitions. [2021-12-16 10:06:19,111 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3802 [2021-12-16 10:06:19,113 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3802 [2021-12-16 10:06:19,113 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3802 states and 5558 transitions. [2021-12-16 10:06:19,116 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:06:19,116 INFO L681 BuchiCegarLoop]: Abstraction has 3802 states and 5558 transitions. [2021-12-16 10:06:19,119 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3802 states and 5558 transitions. [2021-12-16 10:06:19,158 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3802 to 3802. [2021-12-16 10:06:19,162 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3802 states, 3802 states have (on average 1.4618621778011573) internal successors, (5558), 3801 states have internal predecessors, (5558), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:19,169 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3802 states to 3802 states and 5558 transitions. [2021-12-16 10:06:19,169 INFO L704 BuchiCegarLoop]: Abstraction has 3802 states and 5558 transitions. [2021-12-16 10:06:19,170 INFO L587 BuchiCegarLoop]: Abstraction has 3802 states and 5558 transitions. [2021-12-16 10:06:19,170 INFO L425 BuchiCegarLoop]: ======== Iteration 17============ [2021-12-16 10:06:19,170 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3802 states and 5558 transitions. [2021-12-16 10:06:19,177 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3588 [2021-12-16 10:06:19,177 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:06:19,178 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:06:19,179 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:19,179 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:19,180 INFO L791 eck$LassoCheckResult]: Stem: 71827#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 71828#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 72442#L1980 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 71547#L932 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 71548#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 71793#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 71794#L944-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 71520#L949-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 71521#L954-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 72797#L959-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 72101#L964-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 72102#L969-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 72644#L974-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 72009#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 72010#L984-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 71425#L989-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 71426#L994-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 71760#L999-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 71960#L1004-1 assume 1 == ~t14_i~0;~t14_st~0 := 0; 71001#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 71002#L1342 assume !(0 == ~M_E~0); 71166#L1342-2 assume !(0 == ~T1_E~0); 71727#L1347-1 assume !(0 == ~T2_E~0); 72773#L1352-1 assume !(0 == ~T3_E~0); 72540#L1357-1 assume !(0 == ~T4_E~0); 71753#L1362-1 assume !(0 == ~T5_E~0); 71754#L1367-1 assume !(0 == ~T6_E~0); 71347#L1372-1 assume !(0 == ~T7_E~0); 71348#L1377-1 assume !(0 == ~T8_E~0); 71681#L1382-1 assume !(0 == ~T9_E~0); 71682#L1387-1 assume !(0 == ~T10_E~0); 72421#L1392-1 assume !(0 == ~T11_E~0); 71713#L1397-1 assume !(0 == ~T12_E~0); 71714#L1402-1 assume !(0 == ~T13_E~0); 71363#L1407-1 assume !(0 == ~T14_E~0); 71364#L1412-1 assume !(0 == ~E_1~0); 72675#L1417-1 assume !(0 == ~E_2~0); 72676#L1422-1 assume !(0 == ~E_3~0); 72994#L1427-1 assume !(0 == ~E_4~0); 71554#L1432-1 assume !(0 == ~E_5~0); 71555#L1437-1 assume !(0 == ~E_6~0); 72583#L1442-1 assume !(0 == ~E_7~0); 72584#L1447-1 assume !(0 == ~E_8~0); 72418#L1452-1 assume 0 == ~E_9~0;~E_9~0 := 1; 71136#L1457-1 assume !(0 == ~E_10~0); 71137#L1462-1 assume !(0 == ~E_11~0); 72624#L1467-1 assume !(0 == ~E_12~0); 72639#L1472-1 assume !(0 == ~E_13~0); 72640#L1477-1 assume !(0 == ~E_14~0); 72365#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 71337#L646 assume 1 == ~m_pc~0; 71338#L647 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 72019#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 72034#L658 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 71427#L1666 assume !(0 != activate_threads_~tmp~1#1); 71428#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 73028#L665 assume !(1 == ~t1_pc~0); 71908#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 71909#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 71436#L677 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 71437#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 72235#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 72236#L684 assume 1 == ~t2_pc~0; 72360#L685 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 72277#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 72349#L696 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 72777#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 72778#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 73044#L703 assume !(1 == ~t3_pc~0); 71576#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 71577#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 72228#L715 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 70971#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 70972#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 71458#L722 assume 1 == ~t4_pc~0; 72203#L723 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 71642#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 71989#L734 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 72567#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 72058#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 71167#L741 assume 1 == ~t5_pc~0; 71168#L742 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 71480#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 71637#L753 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 71638#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 72329#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 71728#L760 assume !(1 == ~t6_pc~0); 71575#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 71574#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 71429#L772 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 71430#L1714 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 72158#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 72159#L779 assume 1 == ~t7_pc~0; 71212#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 71058#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 71059#L791 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 71469#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 71492#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 71493#L798 assume !(1 == ~t8_pc~0); 72841#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 72734#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 71214#L810 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 71215#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 73030#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 71036#L817 assume 1 == ~t9_pc~0; 71037#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 71835#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 71836#L829 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 72370#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 71443#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 71444#L836 assume !(1 == ~t10_pc~0); 71460#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 71391#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 71392#L848 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 71643#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 71644#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 72747#L855 assume 1 == ~t11_pc~0; 72030#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 72031#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 72619#L867 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 72414#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 72242#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 71333#L874 assume !(1 == ~t12_pc~0); 71334#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 71503#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 71504#L886 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 71645#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 71009#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 71010#L893 assume 1 == ~t13_pc~0; 72930#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 71366#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 71680#L905 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 72835#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 72843#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 72844#L912 assume 1 == ~t14_pc~0; 72591#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 72592#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 71336#L924 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 71266#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 71267#L1778-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 72050#L1495 assume !(1 == ~M_E~0); 72807#L1495-2 assume !(1 == ~T1_E~0); 74558#L1500-1 assume !(1 == ~T2_E~0); 74557#L1505-1 assume !(1 == ~T3_E~0); 74556#L1510-1 assume !(1 == ~T4_E~0); 74555#L1515-1 assume !(1 == ~T5_E~0); 74554#L1520-1 assume !(1 == ~T6_E~0); 74553#L1525-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 72503#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 71438#L1535-1 assume !(1 == ~T9_E~0); 71439#L1540-1 assume !(1 == ~T10_E~0); 70930#L1545-1 assume !(1 == ~T11_E~0); 70931#L1550-1 assume !(1 == ~T12_E~0); 71178#L1555-1 assume !(1 == ~T13_E~0); 71179#L1560-1 assume !(1 == ~T14_E~0); 71481#L1565-1 assume !(1 == ~E_1~0); 73362#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 73361#L1575-1 assume !(1 == ~E_3~0); 73358#L1580-1 assume !(1 == ~E_4~0); 73356#L1585-1 assume !(1 == ~E_5~0); 73188#L1590-1 assume !(1 == ~E_6~0); 73187#L1595-1 assume !(1 == ~E_7~0); 73185#L1600-1 assume !(1 == ~E_8~0); 73183#L1605-1 assume !(1 == ~E_9~0); 73181#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 73179#L1615-1 assume !(1 == ~E_11~0); 73177#L1620-1 assume !(1 == ~E_12~0); 72566#L1625-1 assume !(1 == ~E_13~0); 72419#L1630-1 assume !(1 == ~E_14~0); 71788#L1635-1 assume { :end_inline_reset_delta_events } true; 71729#L2017-2 [2021-12-16 10:06:19,180 INFO L793 eck$LassoCheckResult]: Loop: 71729#L2017-2 assume !false; 71005#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 71006#L1316 assume !false; 72350#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 72412#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 70943#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 71084#L1101 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 71085#L1115 assume !(0 != eval_~tmp~0#1); 72435#L1332 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 73095#L932-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 73094#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 72544#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 72545#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 72201#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 72202#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 72818#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 73063#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 73056#L1372-3 assume !(0 == ~T7_E~0); 70987#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 70988#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 71661#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 71662#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 72594#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 73076#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 74609#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 74607#L1412-3 assume !(0 == ~E_1~0); 74604#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 74603#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 74602#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 74601#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 74600#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 72160#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 72161#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 71052#L1452-3 assume !(0 == ~E_9~0); 71053#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 72730#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 72731#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 72516#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 72517#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 71292#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 71293#L646-42 assume !(1 == ~m_pc~0); 71883#L646-44 is_master_triggered_~__retres1~0#1 := 0; 72774#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 72775#L658-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 72966#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 72967#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 72691#L665-42 assume !(1 == ~t1_pc~0); 72652#L665-44 is_transmit1_triggered_~__retres1~1#1 := 0; 72883#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 72887#L677-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 72888#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 74406#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 74405#L684-42 assume 1 == ~t2_pc~0; 74403#L685-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 74402#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 74401#L696-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 74400#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 74399#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 74398#L703-42 assume 1 == ~t3_pc~0; 74397#L704-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 74395#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 74394#L715-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 74393#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 74392#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 74391#L722-42 assume 1 == ~t4_pc~0; 74389#L723-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 74388#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 74387#L734-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 74386#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 74385#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 74384#L741-42 assume 1 == ~t5_pc~0; 74383#L742-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 74381#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 74380#L753-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 74379#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 74378#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 74377#L760-42 assume 1 == ~t6_pc~0; 74375#L761-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 74374#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 74373#L772-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 74372#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 74371#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 74370#L779-42 assume !(1 == ~t7_pc~0); 72658#L779-44 is_transmit7_triggered_~__retres1~7#1 := 0; 72659#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 71535#L791-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 71536#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 71389#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 71390#L798-42 assume 1 == ~t8_pc~0; 71843#L799-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 71000#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 72799#L810-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 72197#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 71218#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 71219#L817-42 assume !(1 == ~t9_pc~0); 72000#L817-44 is_transmit9_triggered_~__retres1~9#1 := 0; 71506#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 71507#L829-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 71634#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 72451#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 72452#L836-42 assume 1 == ~t10_pc~0; 72549#L837-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 71545#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 71546#L848-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 72933#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 72934#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 72997#L855-42 assume 1 == ~t11_pc~0; 73015#L856-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 71091#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 71092#L867-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 71846#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 72638#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 71710#L874-42 assume !(1 == ~t12_pc~0); 71712#L874-44 is_transmit12_triggered_~__retres1~12#1 := 0; 71952#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 71007#L886-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 71008#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 71260#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 71261#L893-42 assume 1 == ~t13_pc~0; 72482#L894-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 72255#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 72270#L905-14 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 72171#L1770-42 assume !(0 != activate_threads_~tmp___12~0#1); 71639#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 71640#L912-42 assume 1 == ~t14_pc~0; 72991#L913-14 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 70953#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 70954#L924-14 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 72556#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 71382#L1778-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 71383#L1495-3 assume !(1 == ~M_E~0); 72003#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 72441#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 72538#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 71614#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 71578#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 71579#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 72241#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 72473#L1530-3 assume !(1 == ~T8_E~0); 71421#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 71422#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 71459#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 72759#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 72910#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 71869#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 71870#L1565-3 assume !(1 == ~E_1~0); 72497#L1570-3 assume !(1 == ~E_2~0); 72447#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 72448#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 74244#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 74242#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 74240#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 74238#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 72779#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 72780#L1610-3 assume !(1 == ~E_10~0); 71621#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 71622#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 72231#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 72232#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 72134#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 71562#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 71162#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 71907#L1101-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 72475#L2036 assume !(0 == start_simulation_~tmp~3#1); 72476#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 72643#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 72862#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 72863#L1101-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 72178#L1991 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 72179#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 73004#L1999 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 73005#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 71729#L2017-2 [2021-12-16 10:06:19,181 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:19,181 INFO L85 PathProgramCache]: Analyzing trace with hash -114197654, now seen corresponding path program 1 times [2021-12-16 10:06:19,181 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:19,181 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [448534075] [2021-12-16 10:06:19,181 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:19,181 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:19,190 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:06:19,208 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:06:19,208 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:06:19,208 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [448534075] [2021-12-16 10:06:19,208 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [448534075] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:06:19,208 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:06:19,209 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:06:19,209 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1249038071] [2021-12-16 10:06:19,209 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:06:19,209 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:06:19,209 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:19,210 INFO L85 PathProgramCache]: Analyzing trace with hash 1758103982, now seen corresponding path program 1 times [2021-12-16 10:06:19,210 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:19,210 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1783945347] [2021-12-16 10:06:19,210 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:19,210 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:19,220 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:06:19,237 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:06:19,238 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:06:19,238 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1783945347] [2021-12-16 10:06:19,238 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1783945347] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:06:19,238 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:06:19,238 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:06:19,238 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [732604417] [2021-12-16 10:06:19,238 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:06:19,239 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:06:19,239 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:06:19,239 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-16 10:06:19,239 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-16 10:06:19,239 INFO L87 Difference]: Start difference. First operand 3802 states and 5558 transitions. cyclomatic complexity: 1758 Second operand has 4 states, 4 states have (on average 42.5) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:19,409 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:06:19,410 INFO L93 Difference]: Finished difference Result 7070 states and 10314 transitions. [2021-12-16 10:06:19,410 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-16 10:06:19,410 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7070 states and 10314 transitions. [2021-12-16 10:06:19,431 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 6826 [2021-12-16 10:06:19,446 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7070 states to 7070 states and 10314 transitions. [2021-12-16 10:06:19,446 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7070 [2021-12-16 10:06:19,450 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7070 [2021-12-16 10:06:19,450 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7070 states and 10314 transitions. [2021-12-16 10:06:19,455 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:06:19,455 INFO L681 BuchiCegarLoop]: Abstraction has 7070 states and 10314 transitions. [2021-12-16 10:06:19,459 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7070 states and 10314 transitions. [2021-12-16 10:06:19,513 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7070 to 7068. [2021-12-16 10:06:19,519 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7068 states, 7068 states have (on average 1.4589700056593096) internal successors, (10312), 7067 states have internal predecessors, (10312), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:19,529 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7068 states to 7068 states and 10312 transitions. [2021-12-16 10:06:19,530 INFO L704 BuchiCegarLoop]: Abstraction has 7068 states and 10312 transitions. [2021-12-16 10:06:19,530 INFO L587 BuchiCegarLoop]: Abstraction has 7068 states and 10312 transitions. [2021-12-16 10:06:19,530 INFO L425 BuchiCegarLoop]: ======== Iteration 18============ [2021-12-16 10:06:19,530 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7068 states and 10312 transitions. [2021-12-16 10:06:19,540 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 6826 [2021-12-16 10:06:19,540 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:06:19,540 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:06:19,542 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:19,542 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:19,542 INFO L791 eck$LassoCheckResult]: Stem: 82706#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 82707#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 83320#L1980 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 82424#L932 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 82425#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 82672#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 82673#L944-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 82398#L949-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 82399#L954-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 83648#L959-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 82979#L964-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 82980#L969-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 83514#L974-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 82888#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 82889#L984-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 82305#L989-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 82306#L994-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 82639#L999-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 82838#L1004-1 assume 1 == ~t14_i~0;~t14_st~0 := 0; 81883#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 81884#L1342 assume !(0 == ~M_E~0); 82048#L1342-2 assume !(0 == ~T1_E~0); 82607#L1347-1 assume !(0 == ~T2_E~0); 83631#L1352-1 assume !(0 == ~T3_E~0); 83419#L1357-1 assume !(0 == ~T4_E~0); 82632#L1362-1 assume !(0 == ~T5_E~0); 82633#L1367-1 assume !(0 == ~T6_E~0); 82227#L1372-1 assume !(0 == ~T7_E~0); 82228#L1377-1 assume !(0 == ~T8_E~0); 82561#L1382-1 assume !(0 == ~T9_E~0); 82562#L1387-1 assume !(0 == ~T10_E~0); 83299#L1392-1 assume !(0 == ~T11_E~0); 82593#L1397-1 assume !(0 == ~T12_E~0); 82594#L1402-1 assume !(0 == ~T13_E~0); 82243#L1407-1 assume !(0 == ~T14_E~0); 82244#L1412-1 assume !(0 == ~E_1~0); 83544#L1417-1 assume !(0 == ~E_2~0); 83545#L1422-1 assume !(0 == ~E_3~0); 83803#L1427-1 assume !(0 == ~E_4~0); 82431#L1432-1 assume !(0 == ~E_5~0); 82432#L1437-1 assume !(0 == ~E_6~0); 83458#L1442-1 assume !(0 == ~E_7~0); 83459#L1447-1 assume !(0 == ~E_8~0); 83296#L1452-1 assume !(0 == ~E_9~0); 82018#L1457-1 assume !(0 == ~E_10~0); 82019#L1462-1 assume !(0 == ~E_11~0); 83497#L1467-1 assume !(0 == ~E_12~0); 83509#L1472-1 assume !(0 == ~E_13~0); 83510#L1477-1 assume !(0 == ~E_14~0); 83241#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 82217#L646 assume 1 == ~m_pc~0; 82218#L647 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 82898#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 82913#L658 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 82307#L1666 assume !(0 != activate_threads_~tmp~1#1); 82308#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 83834#L665 assume !(1 == ~t1_pc~0); 82786#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 82787#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 82316#L677 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 82317#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 83114#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 83115#L684 assume 1 == ~t2_pc~0; 83236#L685 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 83159#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 83225#L696 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 83635#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 83636#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 83849#L703 assume !(1 == ~t3_pc~0); 82453#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 82454#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 83106#L715 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 81853#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 81854#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 82338#L722 assume 1 == ~t4_pc~0; 83082#L723 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 82522#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 82867#L734 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 83442#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 82936#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 82049#L741 assume 1 == ~t5_pc~0; 82050#L742 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 82360#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 82517#L753 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 82518#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 83205#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 82608#L760 assume !(1 == ~t6_pc~0); 82452#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 82451#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 82309#L772 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 82310#L1714 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 83036#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 83037#L779 assume 1 == ~t7_pc~0; 82094#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 81940#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 81941#L791 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 82349#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 82372#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 82373#L798 assume !(1 == ~t8_pc~0); 83684#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 83602#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 82096#L810 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 82097#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 83836#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 81918#L817 assume 1 == ~t9_pc~0; 81919#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 82714#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 82715#L829 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 83247#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 82323#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 82324#L836 assume !(1 == ~t10_pc~0); 82340#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 82271#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 82272#L848 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 82523#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 82524#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 83612#L855 assume 1 == ~t11_pc~0; 82909#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 82910#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 83492#L867 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 83292#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 83122#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 82213#L874 assume !(1 == ~t12_pc~0); 82214#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 82381#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 82382#L886 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 82525#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 81891#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 81892#L893 assume 1 == ~t13_pc~0; 83758#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 82246#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 82560#L905 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 83678#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 83686#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 83687#L912 assume 1 == ~t14_pc~0; 83466#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 83467#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 82216#L924 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 82148#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 82149#L1778-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 82929#L1495 assume !(1 == ~M_E~0); 83354#L1495-2 assume !(1 == ~T1_E~0); 83355#L1500-1 assume !(1 == ~T2_E~0); 83032#L1505-1 assume !(1 == ~T3_E~0); 83033#L1510-1 assume !(1 == ~T4_E~0); 83091#L1515-1 assume !(1 == ~T5_E~0); 83092#L1520-1 assume !(1 == ~T6_E~0); 84147#L1525-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 84148#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 82318#L1535-1 assume !(1 == ~T9_E~0); 82319#L1540-1 assume !(1 == ~T10_E~0); 84114#L1545-1 assume !(1 == ~T11_E~0); 84112#L1550-1 assume !(1 == ~T12_E~0); 84096#L1555-1 assume !(1 == ~T13_E~0); 84094#L1560-1 assume !(1 == ~T14_E~0); 84092#L1565-1 assume !(1 == ~E_1~0); 84090#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 83264#L1575-1 assume !(1 == ~E_3~0); 83265#L1580-1 assume !(1 == ~E_4~0); 84019#L1585-1 assume !(1 == ~E_5~0); 84017#L1590-1 assume !(1 == ~E_6~0); 84015#L1595-1 assume !(1 == ~E_7~0); 84014#L1600-1 assume !(1 == ~E_8~0); 83980#L1605-1 assume 1 == ~E_9~0;~E_9~0 := 2; 83971#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 83970#L1615-1 assume !(1 == ~E_11~0); 83956#L1620-1 assume !(1 == ~E_12~0); 83947#L1625-1 assume !(1 == ~E_13~0); 83939#L1630-1 assume !(1 == ~E_14~0); 83931#L1635-1 assume { :end_inline_reset_delta_events } true; 83924#L2017-2 [2021-12-16 10:06:19,543 INFO L793 eck$LassoCheckResult]: Loop: 83924#L2017-2 assume !false; 83921#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 83917#L1316 assume !false; 83916#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 83911#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 83900#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 83899#L1101 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 83897#L1115 assume !(0 != eval_~tmp~0#1); 83896#L1332 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 83895#L932-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 83893#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 83894#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 86454#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 86447#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 86440#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 86434#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 86427#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 86420#L1372-3 assume !(0 == ~T7_E~0); 86408#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 86403#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 86397#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 86394#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 86391#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 85804#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 85788#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 85786#L1412-3 assume !(0 == ~E_1~0); 85737#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 85730#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 83663#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 83664#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 83334#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 83038#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 83039#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 81934#L1452-3 assume !(0 == ~E_9~0); 81935#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 83598#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 83599#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 83395#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 83396#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 82172#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 82173#L646-42 assume !(1 == ~m_pc~0); 82761#L646-44 is_master_triggered_~__retres1~0#1 := 0; 83632#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 83633#L658-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 83784#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 83785#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 83817#L665-42 assume !(1 == ~t1_pc~0); 85549#L665-44 is_transmit1_triggered_~__retres1~1#1 := 0; 85547#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 83721#L677-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 82341#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 82342#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 83865#L684-42 assume 1 == ~t2_pc~0; 83201#L685-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 83202#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 83852#L696-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 82975#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 82976#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 83099#L703-42 assume 1 == ~t3_pc~0; 83304#L704-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 83305#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 82613#L715-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 82614#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 83402#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 83009#L722-42 assume !(1 == ~t4_pc~0); 83011#L722-44 is_transmit4_triggered_~__retres1~4#1 := 0; 83434#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 82661#L734-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 82486#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 82487#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 83826#L741-42 assume 1 == ~t5_pc~0; 83827#L742-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 85351#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 85349#L753-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 85319#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 85316#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 85313#L760-42 assume !(1 == ~t6_pc~0); 85311#L760-44 is_transmit6_triggered_~__retres1~6#1 := 0; 85309#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 85306#L772-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 85304#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 85302#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 85300#L779-42 assume 1 == ~t7_pc~0; 85297#L780-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 85220#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 85218#L791-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 85216#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 85214#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 85213#L798-42 assume !(1 == ~t8_pc~0); 85145#L798-44 is_transmit8_triggered_~__retres1~8#1 := 0; 85046#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 85044#L810-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 84979#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 84976#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 84974#L817-42 assume 1 == ~t9_pc~0; 84905#L818-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 84903#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 84901#L829-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 84899#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 84897#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 84895#L836-42 assume !(1 == ~t10_pc~0); 84891#L836-44 is_transmit10_triggered_~__retres1~10#1 := 0; 84890#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 84826#L848-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 84823#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 84821#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 84819#L855-42 assume !(1 == ~t11_pc~0); 84817#L855-44 is_transmit11_triggered_~__retres1~11#1 := 0; 84814#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 84812#L867-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 84757#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 84755#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 84753#L874-42 assume 1 == ~t12_pc~0; 84751#L875-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 84748#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 84747#L886-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 84746#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 84635#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 84632#L893-42 assume !(1 == ~t13_pc~0); 84629#L893-44 is_transmit13_triggered_~__retres1~13#1 := 0; 84626#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 84624#L905-14 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 84529#L1770-42 assume !(0 != activate_threads_~tmp___12~0#1); 84527#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 84525#L912-42 assume 1 == ~t14_pc~0; 84521#L913-14 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 84429#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 84427#L924-14 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 84425#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 84423#L1778-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 84421#L1495-3 assume !(1 == ~M_E~0); 82882#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 84418#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 84417#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 84416#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 84414#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 84412#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 84410#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 84407#L1530-3 assume !(1 == ~T8_E~0); 84406#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 84405#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 84327#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 84325#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 84323#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 84321#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 84319#L1565-3 assume !(1 == ~E_1~0); 84252#L1570-3 assume !(1 == ~E_2~0); 84251#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 84249#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 84247#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 84245#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 84243#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 84215#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 84209#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 84202#L1610-3 assume !(1 == ~E_10~0); 84196#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 84192#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 84190#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 84188#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 84186#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 84111#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 84095#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 84093#L1101-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 84091#L2036 assume !(0 == start_simulation_~tmp~3#1); 83832#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 83991#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 83975#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 83969#L1101-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 83955#L1991 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 83946#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 83938#L1999 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 83930#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 83924#L2017-2 [2021-12-16 10:06:19,543 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:19,543 INFO L85 PathProgramCache]: Analyzing trace with hash 1971256682, now seen corresponding path program 1 times [2021-12-16 10:06:19,543 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:19,543 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1684026791] [2021-12-16 10:06:19,543 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:19,543 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:19,551 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:06:19,574 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:06:19,574 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:06:19,574 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1684026791] [2021-12-16 10:06:19,574 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1684026791] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:06:19,574 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:06:19,574 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-16 10:06:19,574 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [886570222] [2021-12-16 10:06:19,574 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:06:19,575 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:06:19,575 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:19,575 INFO L85 PathProgramCache]: Analyzing trace with hash -1422436597, now seen corresponding path program 1 times [2021-12-16 10:06:19,575 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:19,575 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [883922971] [2021-12-16 10:06:19,575 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:19,576 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:19,583 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:06:19,597 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:06:19,597 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:06:19,597 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [883922971] [2021-12-16 10:06:19,597 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [883922971] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:06:19,597 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:06:19,597 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:06:19,598 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [266108165] [2021-12-16 10:06:19,598 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:06:19,598 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:06:19,598 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:06:19,598 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-16 10:06:19,598 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-16 10:06:19,599 INFO L87 Difference]: Start difference. First operand 7068 states and 10312 transitions. cyclomatic complexity: 3248 Second operand has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 2 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:19,738 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:06:19,738 INFO L93 Difference]: Finished difference Result 13834 states and 20055 transitions. [2021-12-16 10:06:19,738 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-16 10:06:19,739 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 13834 states and 20055 transitions. [2021-12-16 10:06:19,781 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 13585 [2021-12-16 10:06:19,809 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 13834 states to 13834 states and 20055 transitions. [2021-12-16 10:06:19,809 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13834 [2021-12-16 10:06:19,816 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13834 [2021-12-16 10:06:19,816 INFO L73 IsDeterministic]: Start isDeterministic. Operand 13834 states and 20055 transitions. [2021-12-16 10:06:19,825 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:06:19,825 INFO L681 BuchiCegarLoop]: Abstraction has 13834 states and 20055 transitions. [2021-12-16 10:06:19,829 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13834 states and 20055 transitions. [2021-12-16 10:06:19,938 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13834 to 13410. [2021-12-16 10:06:19,950 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 13410 states, 13410 states have (on average 1.4510812826249069) internal successors, (19459), 13409 states have internal predecessors, (19459), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:19,969 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13410 states to 13410 states and 19459 transitions. [2021-12-16 10:06:19,969 INFO L704 BuchiCegarLoop]: Abstraction has 13410 states and 19459 transitions. [2021-12-16 10:06:19,969 INFO L587 BuchiCegarLoop]: Abstraction has 13410 states and 19459 transitions. [2021-12-16 10:06:19,969 INFO L425 BuchiCegarLoop]: ======== Iteration 19============ [2021-12-16 10:06:19,970 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 13410 states and 19459 transitions. [2021-12-16 10:06:19,998 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 13161 [2021-12-16 10:06:19,998 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:06:19,998 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:06:19,999 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:19,999 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:20,000 INFO L791 eck$LassoCheckResult]: Stem: 103634#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 103635#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 104309#L1980 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 103344#L932 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 103345#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 103600#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 103601#L944-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 103314#L949-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 103315#L954-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 104699#L959-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 103925#L964-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 103926#L969-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 104545#L974-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 103830#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 103831#L984-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 103218#L989-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 103219#L994-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 103563#L999-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 103776#L1004-1 assume 1 == ~t14_i~0;~t14_st~0 := 0; 102792#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 102793#L1342 assume !(0 == ~M_E~0); 102957#L1342-2 assume !(0 == ~T1_E~0); 103531#L1347-1 assume !(0 == ~T2_E~0); 104680#L1352-1 assume !(0 == ~T3_E~0); 104422#L1357-1 assume !(0 == ~T4_E~0); 103556#L1362-1 assume !(0 == ~T5_E~0); 103557#L1367-1 assume !(0 == ~T6_E~0); 103137#L1372-1 assume !(0 == ~T7_E~0); 103138#L1377-1 assume !(0 == ~T8_E~0); 103483#L1382-1 assume !(0 == ~T9_E~0); 103484#L1387-1 assume !(0 == ~T10_E~0); 104287#L1392-1 assume !(0 == ~T11_E~0); 103517#L1397-1 assume !(0 == ~T12_E~0); 103518#L1402-1 assume !(0 == ~T13_E~0); 103153#L1407-1 assume !(0 == ~T14_E~0); 103154#L1412-1 assume !(0 == ~E_1~0); 104575#L1417-1 assume !(0 == ~E_2~0); 104576#L1422-1 assume !(0 == ~E_3~0); 104936#L1427-1 assume !(0 == ~E_4~0); 103350#L1432-1 assume !(0 == ~E_5~0); 103351#L1437-1 assume !(0 == ~E_6~0); 104478#L1442-1 assume !(0 == ~E_7~0); 104479#L1447-1 assume !(0 == ~E_8~0); 104282#L1452-1 assume !(0 == ~E_9~0); 102927#L1457-1 assume !(0 == ~E_10~0); 102928#L1462-1 assume !(0 == ~E_11~0); 104527#L1467-1 assume !(0 == ~E_12~0); 104540#L1472-1 assume !(0 == ~E_13~0); 104541#L1477-1 assume !(0 == ~E_14~0); 104216#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 103128#L646 assume !(1 == ~m_pc~0); 103129#L646-2 is_master_triggered_~__retres1~0#1 := 0; 103859#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 103860#L658 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 103220#L1666 assume !(0 != activate_threads_~tmp~1#1); 103221#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 104981#L665 assume !(1 == ~t1_pc~0); 103720#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 103721#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 103227#L677 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 103228#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 104068#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 104069#L684 assume 1 == ~t2_pc~0; 104213#L685 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 104117#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 104198#L696 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 104684#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 104685#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 105009#L703 assume !(1 == ~t3_pc~0); 103372#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 103373#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 104061#L715 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 102762#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 102763#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 103250#L722 assume 1 == ~t4_pc~0; 104036#L723 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 103444#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 103808#L734 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 104460#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 103883#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 102958#L741 assume 1 == ~t5_pc~0; 102959#L742 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 103272#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 103441#L753 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 103442#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 104172#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 103532#L760 assume !(1 == ~t6_pc~0); 103371#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 103370#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 103222#L772 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 103223#L1714 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 103984#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 103985#L779 assume 1 == ~t7_pc~0; 103002#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 102849#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 102850#L791 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 103261#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 103285#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 103286#L798 assume !(1 == ~t8_pc~0); 104751#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 104644#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 103004#L810 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 103005#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 104983#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 102827#L817 assume 1 == ~t9_pc~0; 102828#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 103642#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 103643#L829 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 104222#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 103234#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 103235#L836 assume !(1 == ~t10_pc~0); 103252#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 103181#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 103182#L848 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 103445#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 103446#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 104658#L855 assume 1 == ~t11_pc~0; 103854#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 103855#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 104516#L867 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 104278#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 104077#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 103122#L874 assume !(1 == ~t12_pc~0); 103123#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 103296#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 103297#L886 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 103447#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 102802#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 102803#L893 assume 1 == ~t13_pc~0; 104857#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 103156#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 103482#L905 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 104745#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 104754#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 104755#L912 assume 1 == ~t14_pc~0; 104488#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 104489#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 103125#L924 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 103055#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 103056#L1778-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 103877#L1495 assume !(1 == ~M_E~0); 104709#L1495-2 assume !(1 == ~T1_E~0); 104931#L1500-1 assume !(1 == ~T2_E~0); 104932#L1505-1 assume !(1 == ~T3_E~0); 106580#L1510-1 assume !(1 == ~T4_E~0); 106579#L1515-1 assume !(1 == ~T5_E~0); 104969#L1520-1 assume !(1 == ~T6_E~0); 104970#L1525-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 104377#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 103229#L1535-1 assume !(1 == ~T9_E~0); 103230#L1540-1 assume !(1 == ~T10_E~0); 106368#L1545-1 assume !(1 == ~T11_E~0); 106367#L1550-1 assume !(1 == ~T12_E~0); 102968#L1555-1 assume !(1 == ~T13_E~0); 102969#L1560-1 assume !(1 == ~T14_E~0); 103275#L1565-1 assume !(1 == ~E_1~0); 104952#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 104242#L1575-1 assume !(1 == ~E_3~0); 104243#L1580-1 assume !(1 == ~E_4~0); 106297#L1585-1 assume !(1 == ~E_5~0); 106295#L1590-1 assume !(1 == ~E_6~0); 106293#L1595-1 assume !(1 == ~E_7~0); 106291#L1600-1 assume !(1 == ~E_8~0); 106287#L1605-1 assume 1 == ~E_9~0;~E_9~0 := 2; 106243#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 106211#L1615-1 assume !(1 == ~E_11~0); 106193#L1620-1 assume !(1 == ~E_12~0); 106189#L1625-1 assume !(1 == ~E_13~0); 106187#L1630-1 assume !(1 == ~E_14~0); 106171#L1635-1 assume { :end_inline_reset_delta_events } true; 106165#L2017-2 [2021-12-16 10:06:20,000 INFO L793 eck$LassoCheckResult]: Loop: 106165#L2017-2 assume !false; 106152#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 106142#L1316 assume !false; 106140#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 106128#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 106102#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 106100#L1101 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 106096#L1115 assume !(0 != eval_~tmp~0#1); 106098#L1332 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 109979#L932-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 109978#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 109977#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 109975#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 109973#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 109971#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 109969#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 109967#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 109965#L1372-3 assume !(0 == ~T7_E~0); 109962#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 109960#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 109958#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 109956#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 109954#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 109952#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 109950#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 109441#L1412-3 assume !(0 == ~E_1~0); 109046#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 109044#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 109041#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 109039#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 109037#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 109035#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 109033#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 109031#L1452-3 assume !(0 == ~E_9~0); 109029#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 109028#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 109025#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 109023#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 109021#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 109019#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 109017#L646-42 assume !(1 == ~m_pc~0); 109015#L646-44 is_master_triggered_~__retres1~0#1 := 0; 109012#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 109010#L658-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 109008#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 109006#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 108689#L665-42 assume !(1 == ~t1_pc~0); 108686#L665-44 is_transmit1_triggered_~__retres1~1#1 := 0; 108684#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 108682#L677-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 108680#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 108309#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 108306#L684-42 assume !(1 == ~t2_pc~0); 108303#L684-44 is_transmit2_triggered_~__retres1~2#1 := 0; 107917#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 107914#L696-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 107912#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 107910#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 107909#L703-42 assume 1 == ~t3_pc~0; 107907#L704-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 107904#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 107902#L715-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 107900#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 107897#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 107895#L722-42 assume !(1 == ~t4_pc~0); 107893#L722-44 is_transmit4_triggered_~__retres1~4#1 := 0; 107890#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 107888#L734-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 107886#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 107883#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 107881#L741-42 assume !(1 == ~t5_pc~0); 107843#L741-44 is_transmit5_triggered_~__retres1~5#1 := 0; 107841#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 107839#L753-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 107837#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 107835#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 107832#L760-42 assume 1 == ~t6_pc~0; 107829#L761-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 107827#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 107482#L772-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 107480#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 107478#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 107476#L779-42 assume 1 == ~t7_pc~0; 107473#L780-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 107471#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 107468#L791-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 107466#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 107464#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 107462#L798-42 assume !(1 == ~t8_pc~0); 107459#L798-44 is_transmit8_triggered_~__retres1~8#1 := 0; 107457#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 107454#L810-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 107452#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 107450#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 107448#L817-42 assume 1 == ~t9_pc~0; 107441#L818-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 107439#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 107436#L829-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 107205#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 107203#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 107201#L836-42 assume 1 == ~t10_pc~0; 107199#L837-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 107196#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 107193#L848-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 107191#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 107189#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 107187#L855-42 assume !(1 == ~t11_pc~0); 107185#L855-44 is_transmit11_triggered_~__retres1~11#1 := 0; 107182#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 107181#L867-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 107180#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 107179#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 107178#L874-42 assume 1 == ~t12_pc~0; 107177#L875-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 107174#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 107172#L886-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 107170#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 107168#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 107167#L893-42 assume !(1 == ~t13_pc~0); 107008#L893-44 is_transmit13_triggered_~__retres1~13#1 := 0; 107004#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 107002#L905-14 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 107000#L1770-42 assume !(0 != activate_threads_~tmp___12~0#1); 106998#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 106996#L912-42 assume 1 == ~t14_pc~0; 106993#L913-14 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 106991#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 106989#L924-14 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 106987#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 106857#L1778-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 106743#L1495-3 assume !(1 == ~M_E~0); 106741#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 106739#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 106737#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 106735#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 106733#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 106731#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 106729#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 106726#L1530-3 assume !(1 == ~T8_E~0); 106724#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 106722#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 106632#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 106630#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 106628#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 106626#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 106624#L1565-3 assume !(1 == ~E_1~0); 106622#L1570-3 assume !(1 == ~E_2~0); 106620#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 106618#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 106616#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 106614#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 106612#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 106610#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 106608#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 106604#L1610-3 assume !(1 == ~E_10~0); 106514#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 106512#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 106509#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 106507#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 106505#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 106427#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 106411#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 106409#L1101-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 106408#L2036 assume !(0 == start_simulation_~tmp~3#1); 104979#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 106268#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 106227#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 106225#L1101-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 106207#L1991 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 106205#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 106186#L1999 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 106170#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 106165#L2017-2 [2021-12-16 10:06:20,000 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:20,001 INFO L85 PathProgramCache]: Analyzing trace with hash 742967561, now seen corresponding path program 1 times [2021-12-16 10:06:20,001 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:20,001 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [171599438] [2021-12-16 10:06:20,001 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:20,001 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:20,010 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:06:20,026 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:06:20,026 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:06:20,026 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [171599438] [2021-12-16 10:06:20,026 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [171599438] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:06:20,026 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:06:20,026 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:06:20,027 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [618843787] [2021-12-16 10:06:20,027 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:06:20,027 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:06:20,027 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:20,027 INFO L85 PathProgramCache]: Analyzing trace with hash -90912309, now seen corresponding path program 1 times [2021-12-16 10:06:20,028 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:20,028 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [681652345] [2021-12-16 10:06:20,028 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:20,028 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:20,036 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:06:20,050 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:06:20,051 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:06:20,051 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [681652345] [2021-12-16 10:06:20,051 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [681652345] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:06:20,051 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:06:20,051 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:06:20,051 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1227378883] [2021-12-16 10:06:20,051 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:06:20,052 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:06:20,052 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:06:20,052 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-16 10:06:20,052 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-16 10:06:20,052 INFO L87 Difference]: Start difference. First operand 13410 states and 19459 transitions. cyclomatic complexity: 6057 Second operand has 4 states, 4 states have (on average 42.5) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:20,350 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:06:20,350 INFO L93 Difference]: Finished difference Result 37608 states and 54224 transitions. [2021-12-16 10:06:20,351 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-16 10:06:20,351 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 37608 states and 54224 transitions. [2021-12-16 10:06:20,488 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 37273 [2021-12-16 10:06:20,590 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 37608 states to 37608 states and 54224 transitions. [2021-12-16 10:06:20,590 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 37608 [2021-12-16 10:06:20,613 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 37608 [2021-12-16 10:06:20,613 INFO L73 IsDeterministic]: Start isDeterministic. Operand 37608 states and 54224 transitions. [2021-12-16 10:06:20,642 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:06:20,642 INFO L681 BuchiCegarLoop]: Abstraction has 37608 states and 54224 transitions. [2021-12-16 10:06:20,660 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 37608 states and 54224 transitions. [2021-12-16 10:06:21,009 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 37608 to 36824. [2021-12-16 10:06:21,046 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 36824 states, 36824 states have (on average 1.4429719747990442) internal successors, (53136), 36823 states have internal predecessors, (53136), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:21,230 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 36824 states to 36824 states and 53136 transitions. [2021-12-16 10:06:21,231 INFO L704 BuchiCegarLoop]: Abstraction has 36824 states and 53136 transitions. [2021-12-16 10:06:21,231 INFO L587 BuchiCegarLoop]: Abstraction has 36824 states and 53136 transitions. [2021-12-16 10:06:21,231 INFO L425 BuchiCegarLoop]: ======== Iteration 20============ [2021-12-16 10:06:21,231 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 36824 states and 53136 transitions. [2021-12-16 10:06:21,318 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 36537 [2021-12-16 10:06:21,318 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:06:21,318 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:06:21,320 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:21,320 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:21,320 INFO L791 eck$LassoCheckResult]: Stem: 154652#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 154653#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 155309#L1980 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 154363#L932 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 154364#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 154618#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 154619#L944-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 154337#L949-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 154338#L954-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 155684#L959-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 154938#L964-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 154939#L969-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 155539#L974-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 154845#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 154846#L984-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 154241#L989-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 154242#L994-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 154582#L999-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 154792#L1004-1 assume 1 == ~t14_i~0;~t14_st~0 := 0; 153820#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 153821#L1342 assume !(0 == ~M_E~0); 153984#L1342-2 assume !(0 == ~T1_E~0); 154548#L1347-1 assume !(0 == ~T2_E~0); 155667#L1352-1 assume !(0 == ~T3_E~0); 155427#L1357-1 assume !(0 == ~T4_E~0); 154574#L1362-1 assume !(0 == ~T5_E~0); 154575#L1367-1 assume !(0 == ~T6_E~0); 154162#L1372-1 assume !(0 == ~T7_E~0); 154163#L1377-1 assume !(0 == ~T8_E~0); 154498#L1382-1 assume !(0 == ~T9_E~0); 154499#L1387-1 assume !(0 == ~T10_E~0); 155285#L1392-1 assume !(0 == ~T11_E~0); 154535#L1397-1 assume !(0 == ~T12_E~0); 154536#L1402-1 assume !(0 == ~T13_E~0); 154177#L1407-1 assume !(0 == ~T14_E~0); 154178#L1412-1 assume !(0 == ~E_1~0); 155574#L1417-1 assume !(0 == ~E_2~0); 155575#L1422-1 assume !(0 == ~E_3~0); 155906#L1427-1 assume !(0 == ~E_4~0); 154369#L1432-1 assume !(0 == ~E_5~0); 154370#L1437-1 assume !(0 == ~E_6~0); 155472#L1442-1 assume !(0 == ~E_7~0); 155473#L1447-1 assume !(0 == ~E_8~0); 155280#L1452-1 assume !(0 == ~E_9~0); 153956#L1457-1 assume !(0 == ~E_10~0); 153957#L1462-1 assume !(0 == ~E_11~0); 155517#L1467-1 assume !(0 == ~E_12~0); 155533#L1472-1 assume !(0 == ~E_13~0); 155534#L1477-1 assume !(0 == ~E_14~0); 155215#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 154155#L646 assume !(1 == ~m_pc~0); 154156#L646-2 is_master_triggered_~__retres1~0#1 := 0; 154872#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 154873#L658 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 154243#L1666 assume !(0 != activate_threads_~tmp~1#1); 154244#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 155949#L665 assume !(1 == ~t1_pc~0); 154735#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 154736#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 154250#L677 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 154251#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 155082#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 155083#L684 assume !(1 == ~t2_pc~0); 155125#L684-2 is_transmit2_triggered_~__retres1~2#1 := 0; 155126#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 155200#L696 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 155671#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 155672#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 155975#L703 assume !(1 == ~t3_pc~0); 154391#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 154392#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 155071#L715 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 153790#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 153791#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 154272#L722 assume 1 == ~t4_pc~0; 155047#L723 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 154458#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 154824#L734 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 155456#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 154896#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 153985#L741 assume 1 == ~t5_pc~0; 153986#L742 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 154294#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 154455#L753 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 154456#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 155177#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 154549#L760 assume !(1 == ~t6_pc~0); 154390#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 154389#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 154245#L772 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 154246#L1714 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 154998#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 154999#L779 assume 1 == ~t7_pc~0; 154029#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 153877#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 153878#L791 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 154283#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 154306#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 154307#L798 assume !(1 == ~t8_pc~0); 155736#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 155629#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 154031#L810 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 154032#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 155950#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 153855#L817 assume 1 == ~t9_pc~0; 153856#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 154660#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 154661#L829 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 155223#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 154257#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 154258#L836 assume !(1 == ~t10_pc~0); 154274#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 154205#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 154206#L848 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 154459#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 154460#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 155641#L855 assume 1 == ~t11_pc~0; 154868#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 154869#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 155510#L867 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 155276#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 155088#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 154147#L874 assume !(1 == ~t12_pc~0); 154148#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 154315#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 154316#L886 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 154461#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 153828#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 153829#L893 assume 1 == ~t13_pc~0; 155842#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 154180#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 154497#L905 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 155729#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 155738#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 155739#L912 assume 1 == ~t14_pc~0; 155480#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 155481#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 154150#L924 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 154082#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 154083#L1778-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 154890#L1495 assume !(1 == ~M_E~0); 155698#L1495-2 assume !(1 == ~T1_E~0); 155901#L1500-1 assume !(1 == ~T2_E~0); 155902#L1505-1 assume !(1 == ~T3_E~0); 156037#L1510-1 assume !(1 == ~T4_E~0); 156038#L1515-1 assume !(1 == ~T5_E~0); 155933#L1520-1 assume !(1 == ~T6_E~0); 155934#L1525-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 177845#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 180870#L1535-1 assume !(1 == ~T9_E~0); 180868#L1540-1 assume !(1 == ~T10_E~0); 180866#L1545-1 assume !(1 == ~T11_E~0); 180864#L1550-1 assume !(1 == ~T12_E~0); 180861#L1555-1 assume !(1 == ~T13_E~0); 180859#L1560-1 assume !(1 == ~T14_E~0); 180857#L1565-1 assume !(1 == ~E_1~0); 180855#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 180853#L1575-1 assume !(1 == ~E_3~0); 180851#L1580-1 assume !(1 == ~E_4~0); 180848#L1585-1 assume !(1 == ~E_5~0); 155388#L1590-1 assume !(1 == ~E_6~0); 154612#L1595-1 assume !(1 == ~E_7~0); 154613#L1600-1 assume !(1 == ~E_8~0); 155007#L1605-1 assume 1 == ~E_9~0;~E_9~0 := 2; 155008#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 175423#L1615-1 assume !(1 == ~E_11~0); 175419#L1620-1 assume !(1 == ~E_12~0); 175417#L1625-1 assume !(1 == ~E_13~0); 175381#L1630-1 assume !(1 == ~E_14~0); 175366#L1635-1 assume { :end_inline_reset_delta_events } true; 175356#L2017-2 [2021-12-16 10:06:21,321 INFO L793 eck$LassoCheckResult]: Loop: 175356#L2017-2 assume !false; 175350#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 175344#L1316 assume !false; 175342#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 175223#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 175207#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 175202#L1101 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 175195#L1115 assume !(0 != eval_~tmp~0#1); 175196#L1332 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 176558#L932-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 176556#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 176553#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 176551#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 176549#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 176547#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 176545#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 176543#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 176540#L1372-3 assume !(0 == ~T7_E~0); 176538#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 176536#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 176534#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 176532#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 176530#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 176527#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 176525#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 176523#L1412-3 assume !(0 == ~E_1~0); 176521#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 176519#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 176517#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 176514#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 176512#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 176510#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 176508#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 176506#L1452-3 assume !(0 == ~E_9~0); 176504#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 176501#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 176499#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 176497#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 176495#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 176493#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 176491#L646-42 assume !(1 == ~m_pc~0); 176488#L646-44 is_master_triggered_~__retres1~0#1 := 0; 176486#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 176484#L658-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 176482#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 176480#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 176478#L665-42 assume !(1 == ~t1_pc~0); 176476#L665-44 is_transmit1_triggered_~__retres1~1#1 := 0; 176474#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 176472#L677-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 176470#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 176468#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 176466#L684-42 assume !(1 == ~t2_pc~0); 176465#L684-44 is_transmit2_triggered_~__retres1~2#1 := 0; 176464#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 176463#L696-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 176462#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 176461#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 176460#L703-42 assume !(1 == ~t3_pc~0); 176458#L703-44 is_transmit3_triggered_~__retres1~3#1 := 0; 176457#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 176456#L715-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 176455#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 176454#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 176453#L722-42 assume 1 == ~t4_pc~0; 176451#L723-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 176450#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 176449#L734-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 176448#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 176447#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 176446#L741-42 assume !(1 == ~t5_pc~0); 176444#L741-44 is_transmit5_triggered_~__retres1~5#1 := 0; 176443#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 176442#L753-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 176441#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 176439#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 176437#L760-42 assume 1 == ~t6_pc~0; 176434#L761-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 176432#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 176430#L772-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 176428#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 176426#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 176424#L779-42 assume !(1 == ~t7_pc~0); 176422#L779-44 is_transmit7_triggered_~__retres1~7#1 := 0; 176419#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 176417#L791-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 176415#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 176413#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 176411#L798-42 assume !(1 == ~t8_pc~0); 176408#L798-44 is_transmit8_triggered_~__retres1~8#1 := 0; 176406#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 176404#L810-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 176402#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 176400#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 176397#L817-42 assume 1 == ~t9_pc~0; 176394#L818-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 176392#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 176390#L829-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 176388#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 176386#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 176383#L836-42 assume !(1 == ~t10_pc~0); 176380#L836-44 is_transmit10_triggered_~__retres1~10#1 := 0; 176378#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 176376#L848-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 176374#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 176372#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 176369#L855-42 assume 1 == ~t11_pc~0; 176366#L856-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 176364#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 176362#L867-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 176360#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 176358#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 176355#L874-42 assume !(1 == ~t12_pc~0); 176352#L874-44 is_transmit12_triggered_~__retres1~12#1 := 0; 176350#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 176348#L886-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 176346#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 176344#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 176341#L893-42 assume 1 == ~t13_pc~0; 176338#L894-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 176336#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 176334#L905-14 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 176332#L1770-42 assume !(0 != activate_threads_~tmp___12~0#1); 176330#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 176327#L912-42 assume 1 == ~t14_pc~0; 176324#L913-14 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 176322#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 176320#L924-14 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 176318#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 176316#L1778-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 176238#L1495-3 assume !(1 == ~M_E~0); 176236#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 176234#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 176232#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 176230#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 176227#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 176225#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 176223#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 176219#L1530-3 assume !(1 == ~T8_E~0); 176217#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 176215#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 176212#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 176210#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 176208#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 176206#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 176204#L1565-3 assume !(1 == ~E_1~0); 176202#L1570-3 assume !(1 == ~E_2~0); 176199#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 176197#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 176195#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 176193#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 176191#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 176189#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 176186#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 176182#L1610-3 assume !(1 == ~E_10~0); 176180#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 176178#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 176176#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 176174#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 176171#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 176168#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 176152#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 176150#L1101-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 176148#L2036 assume !(0 == start_simulation_~tmp~3#1); 176144#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 176110#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 176107#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 175416#L1101-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 175380#L1991 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 175379#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 175378#L1999 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 175365#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 175356#L2017-2 [2021-12-16 10:06:21,321 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:21,321 INFO L85 PathProgramCache]: Analyzing trace with hash 296209192, now seen corresponding path program 1 times [2021-12-16 10:06:21,321 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:21,321 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1573044624] [2021-12-16 10:06:21,322 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:21,322 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:21,330 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:06:21,348 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:06:21,348 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:06:21,348 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1573044624] [2021-12-16 10:06:21,349 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1573044624] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:06:21,349 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:06:21,349 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:06:21,349 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1374074414] [2021-12-16 10:06:21,350 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:06:21,351 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:06:21,351 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:21,351 INFO L85 PathProgramCache]: Analyzing trace with hash 452291562, now seen corresponding path program 1 times [2021-12-16 10:06:21,351 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:21,351 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1815760734] [2021-12-16 10:06:21,351 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:21,352 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:21,359 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:06:21,374 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:06:21,375 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:06:21,375 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1815760734] [2021-12-16 10:06:21,375 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1815760734] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:06:21,375 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:06:21,375 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:06:21,375 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [386751594] [2021-12-16 10:06:21,375 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:06:21,376 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:06:21,376 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:06:21,376 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-16 10:06:21,376 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-16 10:06:21,377 INFO L87 Difference]: Start difference. First operand 36824 states and 53136 transitions. cyclomatic complexity: 16328 Second operand has 4 states, 4 states have (on average 42.5) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:21,890 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:06:21,890 INFO L93 Difference]: Finished difference Result 104297 states and 149735 transitions. [2021-12-16 10:06:21,891 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-16 10:06:21,891 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 104297 states and 149735 transitions. [2021-12-16 10:06:22,540 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 103739 [2021-12-16 10:06:22,917 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 104297 states to 104297 states and 149735 transitions. [2021-12-16 10:06:22,917 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 104297 [2021-12-16 10:06:23,029 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 104297 [2021-12-16 10:06:23,029 INFO L73 IsDeterministic]: Start isDeterministic. Operand 104297 states and 149735 transitions. [2021-12-16 10:06:23,132 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:06:23,132 INFO L681 BuchiCegarLoop]: Abstraction has 104297 states and 149735 transitions. [2021-12-16 10:06:23,176 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 104297 states and 149735 transitions. [2021-12-16 10:06:24,297 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 104297 to 102249. [2021-12-16 10:06:24,393 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 102249 states, 102249 states have (on average 1.4367182075130318) internal successors, (146903), 102248 states have internal predecessors, (146903), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:24,569 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 102249 states to 102249 states and 146903 transitions. [2021-12-16 10:06:24,569 INFO L704 BuchiCegarLoop]: Abstraction has 102249 states and 146903 transitions. [2021-12-16 10:06:24,569 INFO L587 BuchiCegarLoop]: Abstraction has 102249 states and 146903 transitions. [2021-12-16 10:06:24,569 INFO L425 BuchiCegarLoop]: ======== Iteration 21============ [2021-12-16 10:06:24,569 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 102249 states and 146903 transitions. [2021-12-16 10:06:24,988 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 101867 [2021-12-16 10:06:24,988 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:06:24,988 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:06:24,989 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:24,989 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:24,990 INFO L791 eck$LassoCheckResult]: Stem: 295771#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 295772#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 296435#L1980 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 295488#L932 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 295489#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 295737#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 295738#L944-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 295461#L949-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 295462#L954-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 296830#L959-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 296057#L964-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 296058#L969-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 296675#L974-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 295961#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 295962#L984-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 295368#L989-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 295369#L994-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 295700#L999-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 295910#L1004-1 assume 1 == ~t14_i~0;~t14_st~0 := 0; 294951#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 294952#L1342 assume !(0 == ~M_E~0); 295115#L1342-2 assume !(0 == ~T1_E~0); 295668#L1347-1 assume !(0 == ~T2_E~0); 296810#L1352-1 assume !(0 == ~T3_E~0); 296560#L1357-1 assume !(0 == ~T4_E~0); 295693#L1362-1 assume !(0 == ~T5_E~0); 295694#L1367-1 assume !(0 == ~T6_E~0); 295291#L1372-1 assume !(0 == ~T7_E~0); 295292#L1377-1 assume !(0 == ~T8_E~0); 295622#L1382-1 assume !(0 == ~T9_E~0); 295623#L1387-1 assume !(0 == ~T10_E~0); 296415#L1392-1 assume !(0 == ~T11_E~0); 295656#L1397-1 assume !(0 == ~T12_E~0); 295657#L1402-1 assume !(0 == ~T13_E~0); 295306#L1407-1 assume !(0 == ~T14_E~0); 295307#L1412-1 assume !(0 == ~E_1~0); 296709#L1417-1 assume !(0 == ~E_2~0); 296710#L1422-1 assume !(0 == ~E_3~0); 297078#L1427-1 assume !(0 == ~E_4~0); 295494#L1432-1 assume !(0 == ~E_5~0); 295495#L1437-1 assume !(0 == ~E_6~0); 296613#L1442-1 assume !(0 == ~E_7~0); 296614#L1447-1 assume !(0 == ~E_8~0); 296409#L1452-1 assume !(0 == ~E_9~0); 295085#L1457-1 assume !(0 == ~E_10~0); 295086#L1462-1 assume !(0 == ~E_11~0); 296654#L1467-1 assume !(0 == ~E_12~0); 296669#L1472-1 assume !(0 == ~E_13~0); 296670#L1477-1 assume !(0 == ~E_14~0); 296342#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 295283#L646 assume !(1 == ~m_pc~0); 295284#L646-2 is_master_triggered_~__retres1~0#1 := 0; 295987#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 295988#L658 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 295370#L1666 assume !(0 != activate_threads_~tmp~1#1); 295371#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 297118#L665 assume !(1 == ~t1_pc~0); 295854#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 295855#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 295379#L677 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 295380#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 296200#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 296201#L684 assume !(1 == ~t2_pc~0); 296250#L684-2 is_transmit2_triggered_~__retres1~2#1 := 0; 296251#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 296326#L696 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 296816#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 296817#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 297146#L703 assume !(1 == ~t3_pc~0); 295515#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 295516#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 296193#L715 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 294921#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 294922#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 295400#L722 assume !(1 == ~t4_pc~0); 295582#L722-2 is_transmit4_triggered_~__retres1~4#1 := 0; 295583#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 295940#L734 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 296594#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 296013#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 295116#L741 assume 1 == ~t5_pc~0; 295117#L742 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 295422#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 295580#L753 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 295581#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 296301#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 295669#L760 assume !(1 == ~t6_pc~0); 295514#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 295513#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 295372#L772 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 295373#L1714 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 296122#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 296123#L779 assume 1 == ~t7_pc~0; 295159#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 295008#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 295009#L791 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 295411#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 295434#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 295435#L798 assume !(1 == ~t8_pc~0); 296885#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 296771#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 295161#L810 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 295162#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 297119#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 294986#L817 assume 1 == ~t9_pc~0; 294987#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 295779#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 295780#L829 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 296350#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 295385#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 295386#L836 assume !(1 == ~t10_pc~0); 295402#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 295335#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 295336#L848 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 295584#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 295585#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 296786#L855 assume 1 == ~t11_pc~0; 295982#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 295983#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 296649#L867 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 296405#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 296207#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 295277#L874 assume !(1 == ~t12_pc~0); 295278#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 295443#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 295444#L886 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 295586#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 294959#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 294960#L893 assume 1 == ~t13_pc~0; 296997#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 295309#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 295621#L905 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 296878#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 296888#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 296889#L912 assume 1 == ~t14_pc~0; 296621#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 296622#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 295280#L924 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 295212#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 295213#L1778-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 296007#L1495 assume !(1 == ~M_E~0); 296848#L1495-2 assume !(1 == ~T1_E~0); 299754#L1500-1 assume !(1 == ~T2_E~0); 296116#L1505-1 assume !(1 == ~T3_E~0); 296117#L1510-1 assume !(1 == ~T4_E~0); 296179#L1515-1 assume !(1 == ~T5_E~0); 296180#L1520-1 assume !(1 == ~T6_E~0); 296886#L1525-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 296504#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 296505#L1535-1 assume !(1 == ~T9_E~0); 299689#L1540-1 assume !(1 == ~T10_E~0); 299687#L1545-1 assume !(1 == ~T11_E~0); 297230#L1550-1 assume !(1 == ~T12_E~0); 295126#L1555-1 assume !(1 == ~T13_E~0); 295127#L1560-1 assume !(1 == ~T14_E~0); 295423#L1565-1 assume !(1 == ~E_1~0); 297092#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 299629#L1575-1 assume !(1 == ~E_3~0); 299627#L1580-1 assume !(1 == ~E_4~0); 299625#L1585-1 assume !(1 == ~E_5~0); 299440#L1590-1 assume !(1 == ~E_6~0); 299438#L1595-1 assume !(1 == ~E_7~0); 299436#L1600-1 assume !(1 == ~E_8~0); 299434#L1605-1 assume 1 == ~E_9~0;~E_9~0 := 2; 299358#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 299350#L1615-1 assume !(1 == ~E_11~0); 299339#L1620-1 assume !(1 == ~E_12~0); 299277#L1625-1 assume !(1 == ~E_13~0); 299275#L1630-1 assume !(1 == ~E_14~0); 299204#L1635-1 assume { :end_inline_reset_delta_events } true; 299203#L2017-2 [2021-12-16 10:06:24,990 INFO L793 eck$LassoCheckResult]: Loop: 299203#L2017-2 assume !false; 299193#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 299190#L1316 assume !false; 299185#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 299186#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 299167#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 299168#L1101 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 299162#L1115 assume !(0 != eval_~tmp~0#1); 299164#L1332 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 356698#L932-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 356697#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 356696#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 356695#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 356694#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 356693#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 356692#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 356691#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 356690#L1372-3 assume !(0 == ~T7_E~0); 356689#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 356688#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 356687#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 356686#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 356685#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 356684#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 356683#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 356682#L1412-3 assume !(0 == ~E_1~0); 356681#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 356680#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 356679#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 356678#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 356677#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 356676#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 356675#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 356674#L1452-3 assume !(0 == ~E_9~0); 356673#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 356672#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 356671#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 356670#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 356669#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 356668#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 356667#L646-42 assume !(1 == ~m_pc~0); 356666#L646-44 is_master_triggered_~__retres1~0#1 := 0; 356665#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 356664#L658-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 356663#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 356662#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 356661#L665-42 assume !(1 == ~t1_pc~0); 356660#L665-44 is_transmit1_triggered_~__retres1~1#1 := 0; 356659#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 356658#L677-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 356657#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 356656#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 356655#L684-42 assume !(1 == ~t2_pc~0); 356654#L684-44 is_transmit2_triggered_~__retres1~2#1 := 0; 356653#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 356652#L696-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 356651#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 356650#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 356649#L703-42 assume !(1 == ~t3_pc~0); 356647#L703-44 is_transmit3_triggered_~__retres1~3#1 := 0; 356646#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 356645#L715-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 356644#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 356643#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 356642#L722-42 assume !(1 == ~t4_pc~0); 356641#L722-44 is_transmit4_triggered_~__retres1~4#1 := 0; 356640#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 356639#L734-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 356638#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 356637#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 356636#L741-42 assume 1 == ~t5_pc~0; 356635#L742-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 356633#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 356632#L753-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 356631#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 356630#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 356629#L760-42 assume !(1 == ~t6_pc~0); 356628#L760-44 is_transmit6_triggered_~__retres1~6#1 := 0; 356626#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 356625#L772-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 356624#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 356623#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 356622#L779-42 assume !(1 == ~t7_pc~0); 356621#L779-44 is_transmit7_triggered_~__retres1~7#1 := 0; 356619#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 356618#L791-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 356617#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 356616#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 356615#L798-42 assume !(1 == ~t8_pc~0); 356613#L798-44 is_transmit8_triggered_~__retres1~8#1 := 0; 356612#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 356611#L810-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 356610#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 356609#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 356608#L817-42 assume !(1 == ~t9_pc~0); 356607#L817-44 is_transmit9_triggered_~__retres1~9#1 := 0; 356605#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 356604#L829-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 356603#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 356602#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 356601#L836-42 assume !(1 == ~t10_pc~0); 356599#L836-44 is_transmit10_triggered_~__retres1~10#1 := 0; 356598#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 356597#L848-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 356596#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 356595#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 356594#L855-42 assume !(1 == ~t11_pc~0); 356593#L855-44 is_transmit11_triggered_~__retres1~11#1 := 0; 356591#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 356590#L867-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 356589#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 356588#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 356587#L874-42 assume !(1 == ~t12_pc~0); 356585#L874-44 is_transmit12_triggered_~__retres1~12#1 := 0; 356584#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 356583#L886-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 356582#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 356581#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 356580#L893-42 assume !(1 == ~t13_pc~0); 356579#L893-44 is_transmit13_triggered_~__retres1~13#1 := 0; 356577#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 356576#L905-14 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 356575#L1770-42 assume !(0 != activate_threads_~tmp___12~0#1); 356574#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 356573#L912-42 assume !(1 == ~t14_pc~0); 356572#L912-44 is_transmit14_triggered_~__retres1~14#1 := 0; 356570#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 356569#L924-14 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 356568#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 356567#L1778-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 356566#L1495-3 assume !(1 == ~M_E~0); 354450#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 356565#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 356564#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 356563#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 356562#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 356561#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 356560#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 300617#L1530-3 assume !(1 == ~T8_E~0); 356559#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 356558#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 356557#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 356556#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 356555#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 356554#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 356553#L1565-3 assume !(1 == ~E_1~0); 356552#L1570-3 assume !(1 == ~E_2~0); 356551#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 356550#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 356549#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 356548#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 356547#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 356546#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 356545#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 355402#L1610-3 assume !(1 == ~E_10~0); 356544#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 356543#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 356542#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 356541#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 356540#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 356539#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 356524#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 356523#L1101-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 356522#L2036 assume !(0 == start_simulation_~tmp~3#1); 300543#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 300544#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 356390#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 356389#L1101-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 356388#L1991 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 356387#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 356386#L1999 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 299202#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 299203#L2017-2 [2021-12-16 10:06:24,990 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:24,991 INFO L85 PathProgramCache]: Analyzing trace with hash 651805639, now seen corresponding path program 1 times [2021-12-16 10:06:24,991 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:24,991 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [336478923] [2021-12-16 10:06:24,991 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:24,992 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:24,999 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:06:25,017 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:06:25,018 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:06:25,018 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [336478923] [2021-12-16 10:06:25,018 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [336478923] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:06:25,018 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:06:25,018 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:06:25,018 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1203750397] [2021-12-16 10:06:25,019 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:06:25,019 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:06:25,019 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:25,019 INFO L85 PathProgramCache]: Analyzing trace with hash 1306611333, now seen corresponding path program 1 times [2021-12-16 10:06:25,019 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:25,019 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1838296384] [2021-12-16 10:06:25,020 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:25,020 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:25,027 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:06:25,041 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:06:25,042 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:06:25,042 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1838296384] [2021-12-16 10:06:25,042 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1838296384] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:06:25,042 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:06:25,042 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:06:25,042 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [549824471] [2021-12-16 10:06:25,042 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:06:25,042 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:06:25,043 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:06:25,043 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-16 10:06:25,043 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-16 10:06:25,043 INFO L87 Difference]: Start difference. First operand 102249 states and 146903 transitions. cyclomatic complexity: 44686 Second operand has 4 states, 4 states have (on average 42.5) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:26,160 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:06:26,161 INFO L93 Difference]: Finished difference Result 290834 states and 416042 transitions. [2021-12-16 10:06:26,161 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-16 10:06:26,161 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 290834 states and 416042 transitions. [2021-12-16 10:06:27,424 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 289717 [2021-12-16 10:06:28,196 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 290834 states to 290834 states and 416042 transitions. [2021-12-16 10:06:28,196 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 290834 [2021-12-16 10:06:28,346 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 290834 [2021-12-16 10:06:28,346 INFO L73 IsDeterministic]: Start isDeterministic. Operand 290834 states and 416042 transitions. [2021-12-16 10:06:28,505 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:06:28,505 INFO L681 BuchiCegarLoop]: Abstraction has 290834 states and 416042 transitions. [2021-12-16 10:06:28,642 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 290834 states and 416042 transitions. [2021-12-16 10:06:30,862 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 290834 to 285226. [2021-12-16 10:06:31,116 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 285226 states, 285226 states have (on average 1.4314894154109372) internal successors, (408298), 285225 states have internal predecessors, (408298), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:32,052 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 285226 states to 285226 states and 408298 transitions. [2021-12-16 10:06:32,053 INFO L704 BuchiCegarLoop]: Abstraction has 285226 states and 408298 transitions. [2021-12-16 10:06:32,053 INFO L587 BuchiCegarLoop]: Abstraction has 285226 states and 408298 transitions. [2021-12-16 10:06:32,053 INFO L425 BuchiCegarLoop]: ======== Iteration 22============ [2021-12-16 10:06:32,053 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 285226 states and 408298 transitions. [2021-12-16 10:06:33,191 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 284605 [2021-12-16 10:06:33,192 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:06:33,192 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:06:33,193 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:33,193 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:33,193 INFO L791 eck$LassoCheckResult]: Stem: 688868#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 688869#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 689529#L1980 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 688576#L932 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 688577#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 688837#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 688838#L944-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 688551#L949-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 688552#L954-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 689933#L959-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 689159#L964-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 689160#L969-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 689764#L974-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 689062#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 689063#L984-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 688456#L989-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 688457#L994-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 688798#L999-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 689011#L1004-1 assume 1 == ~t14_i~0;~t14_st~0 := 0; 688044#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 688045#L1342 assume !(0 == ~M_E~0); 688207#L1342-2 assume !(0 == ~T1_E~0); 688763#L1347-1 assume !(0 == ~T2_E~0); 689915#L1352-1 assume !(0 == ~T3_E~0); 689645#L1357-1 assume !(0 == ~T4_E~0); 688789#L1362-1 assume !(0 == ~T5_E~0); 688790#L1367-1 assume !(0 == ~T6_E~0); 688381#L1372-1 assume !(0 == ~T7_E~0); 688382#L1377-1 assume !(0 == ~T8_E~0); 688714#L1382-1 assume !(0 == ~T9_E~0); 688715#L1387-1 assume !(0 == ~T10_E~0); 689506#L1392-1 assume !(0 == ~T11_E~0); 688751#L1397-1 assume !(0 == ~T12_E~0); 688752#L1402-1 assume !(0 == ~T13_E~0); 688396#L1407-1 assume !(0 == ~T14_E~0); 688397#L1412-1 assume !(0 == ~E_1~0); 689804#L1417-1 assume !(0 == ~E_2~0); 689805#L1422-1 assume !(0 == ~E_3~0); 690185#L1427-1 assume !(0 == ~E_4~0); 688582#L1432-1 assume !(0 == ~E_5~0); 688583#L1437-1 assume !(0 == ~E_6~0); 689700#L1442-1 assume !(0 == ~E_7~0); 689701#L1447-1 assume !(0 == ~E_8~0); 689500#L1452-1 assume !(0 == ~E_9~0); 688179#L1457-1 assume !(0 == ~E_10~0); 688180#L1462-1 assume !(0 == ~E_11~0); 689741#L1467-1 assume !(0 == ~E_12~0); 689758#L1472-1 assume !(0 == ~E_13~0); 689759#L1477-1 assume !(0 == ~E_14~0); 689438#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 688375#L646 assume !(1 == ~m_pc~0); 688376#L646-2 is_master_triggered_~__retres1~0#1 := 0; 689090#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 689091#L658 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 688458#L1666 assume !(0 != activate_threads_~tmp~1#1); 688459#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 690233#L665 assume !(1 == ~t1_pc~0); 688953#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 688954#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 688467#L677 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 688468#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 689301#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 689302#L684 assume !(1 == ~t2_pc~0); 689345#L684-2 is_transmit2_triggered_~__retres1~2#1 := 0; 689346#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 689423#L696 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 689919#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 689920#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 690253#L703 assume !(1 == ~t3_pc~0); 688605#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 688606#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 689292#L715 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 688014#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 688015#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 688488#L722 assume !(1 == ~t4_pc~0); 688672#L722-2 is_transmit4_triggered_~__retres1~4#1 := 0; 688673#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 689041#L734 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 689683#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 689115#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 688208#L741 assume !(1 == ~t5_pc~0); 688209#L741-2 is_transmit5_triggered_~__retres1~5#1 := 0; 689336#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 688670#L753 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 688671#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 689394#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 688764#L760 assume !(1 == ~t6_pc~0); 688604#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 688603#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 688460#L772 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 688461#L1714 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 689221#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 689222#L779 assume 1 == ~t7_pc~0; 688251#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 688101#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 688102#L791 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 688499#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 688522#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 688523#L798 assume !(1 == ~t8_pc~0); 689983#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 689871#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 688253#L810 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 688254#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 690234#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 688079#L817 assume 1 == ~t9_pc~0; 688080#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 688876#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 688877#L829 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 689444#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 688473#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 688474#L836 assume !(1 == ~t10_pc~0); 688490#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 688423#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 688424#L848 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 688674#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 688675#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 689884#L855 assume 1 == ~t11_pc~0; 689086#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 689087#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 689736#L867 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 689496#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 689308#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 688367#L874 assume !(1 == ~t12_pc~0); 688368#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 688531#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 688532#L886 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 688676#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 688052#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 688053#L893 assume 1 == ~t13_pc~0; 690097#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 688399#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 688713#L905 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 689977#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 689986#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 689987#L912 assume 1 == ~t14_pc~0; 689708#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 689709#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 688370#L924 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 688303#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 688304#L1778-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 689108#L1495 assume !(1 == ~M_E~0); 689947#L1495-2 assume !(1 == ~T1_E~0); 690179#L1500-1 assume !(1 == ~T2_E~0); 690180#L1505-1 assume !(1 == ~T3_E~0); 690312#L1510-1 assume !(1 == ~T4_E~0); 690313#L1515-1 assume !(1 == ~T5_E~0); 690221#L1520-1 assume !(1 == ~T6_E~0); 690222#L1525-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 689598#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 689599#L1535-1 assume !(1 == ~T9_E~0); 690280#L1540-1 assume !(1 == ~T10_E~0); 690281#L1545-1 assume !(1 == ~T11_E~0); 690340#L1550-1 assume !(1 == ~T12_E~0); 690341#L1555-1 assume !(1 == ~T13_E~0); 688512#L1560-1 assume !(1 == ~T14_E~0); 688513#L1565-1 assume !(1 == ~E_1~0); 690323#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 690324#L1575-1 assume !(1 == ~E_3~0); 688793#L1580-1 assume !(1 == ~E_4~0); 688794#L1585-1 assume !(1 == ~E_5~0); 689612#L1590-1 assume !(1 == ~E_6~0); 689613#L1595-1 assume !(1 == ~E_7~0); 690304#L1600-1 assume !(1 == ~E_8~0); 690305#L1605-1 assume 1 == ~E_9~0;~E_9~0 := 2; 689231#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 689848#L1615-1 assume !(1 == ~E_11~0); 689849#L1620-1 assume !(1 == ~E_12~0); 689680#L1625-1 assume !(1 == ~E_13~0); 689681#L1630-1 assume !(1 == ~E_14~0); 688829#L1635-1 assume { :end_inline_reset_delta_events } true; 688830#L2017-2 [2021-12-16 10:06:33,194 INFO L793 eck$LassoCheckResult]: Loop: 688830#L2017-2 assume !false; 955938#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 955927#L1316 assume !false; 955924#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 955724#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 955708#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 898605#L1101 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 898606#L1115 assume !(0 != eval_~tmp~0#1); 951534#L1332 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 956659#L932-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 956657#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 956655#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 956653#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 956651#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 956649#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 956647#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 956645#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 956643#L1372-3 assume !(0 == ~T7_E~0); 956641#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 956639#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 956637#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 956635#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 956633#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 956631#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 956629#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 956627#L1412-3 assume !(0 == ~E_1~0); 956625#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 956622#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 956620#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 956618#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 956616#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 956614#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 956612#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 956610#L1452-3 assume !(0 == ~E_9~0); 956608#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 956606#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 956604#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 956602#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 956600#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 956598#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 956596#L646-42 assume !(1 == ~m_pc~0); 956594#L646-44 is_master_triggered_~__retres1~0#1 := 0; 956592#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 956590#L658-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 956588#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 956585#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 956583#L665-42 assume !(1 == ~t1_pc~0); 956581#L665-44 is_transmit1_triggered_~__retres1~1#1 := 0; 956579#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 956577#L677-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 956575#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 956572#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 956570#L684-42 assume !(1 == ~t2_pc~0); 956568#L684-44 is_transmit2_triggered_~__retres1~2#1 := 0; 956566#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 956564#L696-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 956562#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 956559#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 956557#L703-42 assume !(1 == ~t3_pc~0); 956554#L703-44 is_transmit3_triggered_~__retres1~3#1 := 0; 956552#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 956550#L715-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 956548#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 956545#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 956543#L722-42 assume !(1 == ~t4_pc~0); 956541#L722-44 is_transmit4_triggered_~__retres1~4#1 := 0; 956539#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 956537#L734-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 956535#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 956532#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 956530#L741-42 assume !(1 == ~t5_pc~0); 956528#L741-44 is_transmit5_triggered_~__retres1~5#1 := 0; 956526#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 956524#L753-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 956522#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 956519#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 956517#L760-42 assume 1 == ~t6_pc~0; 956514#L761-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 956512#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 956510#L772-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 956508#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 956505#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 956503#L779-42 assume 1 == ~t7_pc~0; 956500#L780-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 956498#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 956496#L791-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 956494#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 956491#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 956489#L798-42 assume !(1 == ~t8_pc~0); 956486#L798-44 is_transmit8_triggered_~__retres1~8#1 := 0; 956484#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 956482#L810-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 956480#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 956477#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 956475#L817-42 assume 1 == ~t9_pc~0; 956472#L818-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 956470#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 956468#L829-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 956466#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 956464#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 956462#L836-42 assume 1 == ~t10_pc~0; 956460#L837-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 956457#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 956455#L848-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 956453#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 956451#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 956449#L855-42 assume 1 == ~t11_pc~0; 956446#L856-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 956444#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 956442#L867-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 956440#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 956438#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 956436#L874-42 assume 1 == ~t12_pc~0; 956434#L875-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 956431#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 956429#L886-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 956427#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 956425#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 956423#L893-42 assume 1 == ~t13_pc~0; 956420#L894-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 956418#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 956416#L905-14 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 956414#L1770-42 assume !(0 != activate_threads_~tmp___12~0#1); 956412#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 956410#L912-42 assume !(1 == ~t14_pc~0); 956408#L912-44 is_transmit14_triggered_~__retres1~14#1 := 0; 956405#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 956404#L924-14 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 956403#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 956402#L1778-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 956401#L1495-3 assume !(1 == ~M_E~0); 837409#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 956400#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 956399#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 956398#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 956397#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 956396#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 956395#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 860753#L1530-3 assume !(1 == ~T8_E~0); 956394#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 956393#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 956392#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 956391#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 956389#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 956387#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 956385#L1565-3 assume !(1 == ~E_1~0); 956383#L1570-3 assume !(1 == ~E_2~0); 956381#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 956379#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 956376#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 956374#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 956372#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 956370#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 956368#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 881557#L1610-3 assume !(1 == ~E_10~0); 956365#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 956364#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 956362#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 956360#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 956358#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 956353#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 956337#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 956335#L1101-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 956333#L2036 assume !(0 == start_simulation_~tmp~3#1); 956330#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 956107#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 956105#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 956103#L1101-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 956101#L1991 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 956100#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 956099#L1999 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 955999#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 688830#L2017-2 [2021-12-16 10:06:33,194 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:33,194 INFO L85 PathProgramCache]: Analyzing trace with hash 614358950, now seen corresponding path program 1 times [2021-12-16 10:06:33,194 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:33,194 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [406695112] [2021-12-16 10:06:33,194 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:33,194 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:33,202 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:06:33,221 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:06:33,221 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:06:33,221 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [406695112] [2021-12-16 10:06:33,221 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [406695112] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:06:33,221 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:06:33,222 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-16 10:06:33,222 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2015864380] [2021-12-16 10:06:33,222 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:06:33,222 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:06:33,222 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:33,222 INFO L85 PathProgramCache]: Analyzing trace with hash -427252981, now seen corresponding path program 1 times [2021-12-16 10:06:33,223 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:33,223 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [558996369] [2021-12-16 10:06:33,223 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:33,223 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:33,230 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:06:33,244 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:06:33,244 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:06:33,244 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [558996369] [2021-12-16 10:06:33,244 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [558996369] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:06:33,244 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:06:33,244 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:06:33,245 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [341653321] [2021-12-16 10:06:33,245 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:06:33,245 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:06:33,245 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:06:33,245 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-16 10:06:33,245 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-16 10:06:33,246 INFO L87 Difference]: Start difference. First operand 285226 states and 408298 transitions. cyclomatic complexity: 123136 Second operand has 5 states, 5 states have (on average 34.0) internal successors, (170), 5 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:35,604 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:06:35,604 INFO L93 Difference]: Finished difference Result 746200 states and 1075370 transitions. [2021-12-16 10:06:35,606 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-16 10:06:35,606 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 746200 states and 1075370 transitions. [2021-12-16 10:06:39,185 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 744520 [2021-12-16 10:06:41,222 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 746200 states to 746200 states and 1075370 transitions. [2021-12-16 10:06:41,222 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 746200 [2021-12-16 10:06:41,480 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 746200 [2021-12-16 10:06:41,480 INFO L73 IsDeterministic]: Start isDeterministic. Operand 746200 states and 1075370 transitions. [2021-12-16 10:06:41,750 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-16 10:06:41,751 INFO L681 BuchiCegarLoop]: Abstraction has 746200 states and 1075370 transitions. [2021-12-16 10:06:42,048 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 746200 states and 1075370 transitions. [2021-12-16 10:06:45,883 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 746200 to 292063. [2021-12-16 10:06:46,076 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 292063 states, 292063 states have (on average 1.4213885360350336) internal successors, (415135), 292062 states have internal predecessors, (415135), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:46,588 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 292063 states to 292063 states and 415135 transitions. [2021-12-16 10:06:46,588 INFO L704 BuchiCegarLoop]: Abstraction has 292063 states and 415135 transitions. [2021-12-16 10:06:46,588 INFO L587 BuchiCegarLoop]: Abstraction has 292063 states and 415135 transitions. [2021-12-16 10:06:46,588 INFO L425 BuchiCegarLoop]: ======== Iteration 23============ [2021-12-16 10:06:46,588 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 292063 states and 415135 transitions. [2021-12-16 10:06:47,748 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 291439 [2021-12-16 10:06:47,748 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-16 10:06:47,748 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-16 10:06:47,750 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:47,750 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-16 10:06:47,750 INFO L791 eck$LassoCheckResult]: Stem: 1720303#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 1720304#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 1720954#L1980 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1720018#L932 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1720019#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 1720270#L939-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1720271#L944-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1719993#L949-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1719994#L954-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1721342#L959-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1720589#L964-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1720590#L969-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1721186#L974-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1720494#L979-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1720495#L984-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 1719900#L989-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 1719901#L994-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 1720234#L999-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 1720442#L1004-1 assume 1 == ~t14_i~0;~t14_st~0 := 0; 1719483#L1009-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1719484#L1342 assume !(0 == ~M_E~0); 1719647#L1342-2 assume !(0 == ~T1_E~0); 1720200#L1347-1 assume !(0 == ~T2_E~0); 1721324#L1352-1 assume !(0 == ~T3_E~0); 1721070#L1357-1 assume !(0 == ~T4_E~0); 1720226#L1362-1 assume !(0 == ~T5_E~0); 1720227#L1367-1 assume !(0 == ~T6_E~0); 1719822#L1372-1 assume !(0 == ~T7_E~0); 1719823#L1377-1 assume !(0 == ~T8_E~0); 1720152#L1382-1 assume !(0 == ~T9_E~0); 1720153#L1387-1 assume !(0 == ~T10_E~0); 1720932#L1392-1 assume !(0 == ~T11_E~0); 1720188#L1397-1 assume !(0 == ~T12_E~0); 1720189#L1402-1 assume !(0 == ~T13_E~0); 1719837#L1407-1 assume !(0 == ~T14_E~0); 1719838#L1412-1 assume !(0 == ~E_1~0); 1721221#L1417-1 assume !(0 == ~E_2~0); 1721222#L1422-1 assume !(0 == ~E_3~0); 1721572#L1427-1 assume !(0 == ~E_4~0); 1720024#L1432-1 assume !(0 == ~E_5~0); 1720025#L1437-1 assume !(0 == ~E_6~0); 1721123#L1442-1 assume !(0 == ~E_7~0); 1721124#L1447-1 assume !(0 == ~E_8~0); 1720927#L1452-1 assume !(0 == ~E_9~0); 1719618#L1457-1 assume !(0 == ~E_10~0); 1719619#L1462-1 assume !(0 == ~E_11~0); 1721163#L1467-1 assume !(0 == ~E_12~0); 1721180#L1472-1 assume !(0 == ~E_13~0); 1721181#L1477-1 assume !(0 == ~E_14~0); 1720867#L1482-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1719816#L646 assume !(1 == ~m_pc~0); 1719817#L646-2 is_master_triggered_~__retres1~0#1 := 0; 1720520#L657 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1720521#L658 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1719902#L1666 assume !(0 != activate_threads_~tmp~1#1); 1719903#L1666-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1721607#L665 assume !(1 == ~t1_pc~0); 1720384#L665-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1720385#L676 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1719909#L677 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1719910#L1674 assume !(0 != activate_threads_~tmp___0~0#1); 1720728#L1674-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1720729#L684 assume !(1 == ~t2_pc~0); 1720778#L684-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1720779#L695 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1720851#L696 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1721330#L1682 assume !(0 != activate_threads_~tmp___1~0#1); 1721331#L1682-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1721628#L703 assume !(1 == ~t3_pc~0); 1720046#L703-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1720047#L714 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1720718#L715 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1719453#L1690 assume !(0 != activate_threads_~tmp___2~0#1); 1719454#L1690-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1719930#L722 assume !(1 == ~t4_pc~0); 1720111#L722-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1720112#L733 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1720473#L734 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1721105#L1698 assume !(0 != activate_threads_~tmp___3~0#1); 1720547#L1698-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1719648#L741 assume !(1 == ~t5_pc~0); 1719649#L741-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1720768#L752 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1720109#L753 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1720110#L1706 assume !(0 != activate_threads_~tmp___4~0#1); 1720827#L1706-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1720201#L760 assume !(1 == ~t6_pc~0); 1720045#L760-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1720679#L771 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1720981#L772 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1721564#L1714 assume !(0 != activate_threads_~tmp___5~0#1); 1720649#L1714-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1720650#L779 assume 1 == ~t7_pc~0; 1719691#L780 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1719540#L790 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1719541#L791 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1719941#L1722 assume !(0 != activate_threads_~tmp___6~0#1); 1719964#L1722-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1719965#L798 assume !(1 == ~t8_pc~0); 1721390#L798-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1721290#L809 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1719693#L810 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1719694#L1730 assume !(0 != activate_threads_~tmp___7~0#1); 1721608#L1730-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1719518#L817 assume 1 == ~t9_pc~0; 1719519#L818 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1720311#L828 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1720312#L829 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1720872#L1738 assume !(0 != activate_threads_~tmp___8~0#1); 1719915#L1738-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1719916#L836 assume !(1 == ~t10_pc~0); 1719932#L836-2 is_transmit10_triggered_~__retres1~10#1 := 0; 1719864#L847 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1719865#L848 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1720113#L1746 assume !(0 != activate_threads_~tmp___9~0#1); 1720114#L1746-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1721304#L855 assume 1 == ~t11_pc~0; 1720516#L856 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 1720517#L866 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1721158#L867 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1720923#L1754 assume !(0 != activate_threads_~tmp___10~0#1); 1720736#L1754-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1719808#L874 assume !(1 == ~t12_pc~0); 1719809#L874-2 is_transmit12_triggered_~__retres1~12#1 := 0; 1719973#L885 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1719974#L886 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1720115#L1762 assume !(0 != activate_threads_~tmp___11~0#1); 1719493#L1762-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 1719494#L893 assume 1 == ~t13_pc~0; 1721490#L894 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 1719840#L904 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 1720151#L905 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 1721384#L1770 assume !(0 != activate_threads_~tmp___12~0#1); 1721393#L1770-2 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 1721394#L912 assume 1 == ~t14_pc~0; 1721131#L913 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 1721132#L923 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 1719811#L924 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 1719744#L1778 assume !(0 != activate_threads_~tmp___13~0#1); 1719745#L1778-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1720540#L1495 assume !(1 == ~M_E~0); 1721353#L1495-2 assume !(1 == ~T1_E~0); 1804506#L1500-1 assume !(1 == ~T2_E~0); 1804505#L1505-1 assume !(1 == ~T3_E~0); 1804504#L1510-1 assume !(1 == ~T4_E~0); 1804503#L1515-1 assume !(1 == ~T5_E~0); 1804502#L1520-1 assume !(1 == ~T6_E~0); 1804500#L1525-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1804501#L1530-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1837054#L1535-1 assume !(1 == ~T9_E~0); 1837052#L1540-1 assume !(1 == ~T10_E~0); 1837051#L1545-1 assume !(1 == ~T11_E~0); 1837050#L1550-1 assume !(1 == ~T12_E~0); 1837019#L1555-1 assume !(1 == ~T13_E~0); 1837016#L1560-1 assume !(1 == ~T14_E~0); 1836148#L1565-1 assume !(1 == ~E_1~0); 1836147#L1570-1 assume 1 == ~E_2~0;~E_2~0 := 2; 1836146#L1575-1 assume !(1 == ~E_3~0); 1836145#L1580-1 assume !(1 == ~E_4~0); 1836129#L1585-1 assume !(1 == ~E_5~0); 1836127#L1590-1 assume !(1 == ~E_6~0); 1836125#L1595-1 assume !(1 == ~E_7~0); 1836123#L1600-1 assume !(1 == ~E_8~0); 1836121#L1605-1 assume 1 == ~E_9~0;~E_9~0 := 2; 1720659#L1610-1 assume 1 == ~E_10~0;~E_10~0 := 2; 1721269#L1615-1 assume !(1 == ~E_11~0); 1720089#L1620-1 assume !(1 == ~E_12~0); 1720090#L1625-1 assume !(1 == ~E_13~0); 1720928#L1630-1 assume !(1 == ~E_14~0); 1720262#L1635-1 assume { :end_inline_reset_delta_events } true; 1720263#L2017-2 [2021-12-16 10:06:47,750 INFO L793 eck$LassoCheckResult]: Loop: 1720263#L2017-2 assume !false; 1848731#L2018 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1848723#L1316 assume !false; 1845523#L1111 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 1845485#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 1845473#L1100 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 1845471#L1101 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1845469#L1115 assume !(0 != eval_~tmp~0#1); 1845470#L1332 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1850404#L932-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1850401#L1342-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1850398#L1342-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1850394#L1347-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1850391#L1352-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1850388#L1357-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1850385#L1362-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1850382#L1367-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1850335#L1372-3 assume !(0 == ~T7_E~0); 1850330#L1377-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1850326#L1382-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1850276#L1387-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 1850271#L1392-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 1850266#L1397-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 1850260#L1402-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 1850254#L1407-3 assume 0 == ~T14_E~0;~T14_E~0 := 1; 1850249#L1412-3 assume !(0 == ~E_1~0); 1850243#L1417-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1850238#L1422-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1850233#L1427-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1850227#L1432-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1850221#L1437-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1850216#L1442-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1850210#L1447-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1850205#L1452-3 assume !(0 == ~E_9~0); 1850200#L1457-3 assume 0 == ~E_10~0;~E_10~0 := 1; 1850194#L1462-3 assume 0 == ~E_11~0;~E_11~0 := 1; 1850188#L1467-3 assume 0 == ~E_12~0;~E_12~0 := 1; 1850184#L1472-3 assume 0 == ~E_13~0;~E_13~0 := 1; 1850135#L1477-3 assume 0 == ~E_14~0;~E_14~0 := 1; 1850131#L1482-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1850130#L646-42 assume !(1 == ~m_pc~0); 1850129#L646-44 is_master_triggered_~__retres1~0#1 := 0; 1850128#L657-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1850127#L658-14 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1850126#L1666-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1850125#L1666-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1850124#L665-42 assume !(1 == ~t1_pc~0); 1850123#L665-44 is_transmit1_triggered_~__retres1~1#1 := 0; 1850122#L676-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1850121#L677-14 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1850120#L1674-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1850119#L1674-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1850118#L684-42 assume !(1 == ~t2_pc~0); 1850117#L684-44 is_transmit2_triggered_~__retres1~2#1 := 0; 1850116#L695-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1850115#L696-14 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1850114#L1682-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1850113#L1682-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1850112#L703-42 assume !(1 == ~t3_pc~0); 1850110#L703-44 is_transmit3_triggered_~__retres1~3#1 := 0; 1850109#L714-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1850108#L715-14 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1850107#L1690-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1850106#L1690-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1850105#L722-42 assume !(1 == ~t4_pc~0); 1850104#L722-44 is_transmit4_triggered_~__retres1~4#1 := 0; 1850103#L733-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1850102#L734-14 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1850101#L1698-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1850100#L1698-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1850099#L741-42 assume !(1 == ~t5_pc~0); 1850098#L741-44 is_transmit5_triggered_~__retres1~5#1 := 0; 1850097#L752-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1850096#L753-14 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1850095#L1706-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1850094#L1706-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1850093#L760-42 assume 1 == ~t6_pc~0; 1850092#L761-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1850090#L771-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1850088#L772-14 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1850086#L1714-42 assume !(0 != activate_threads_~tmp___5~0#1); 1850081#L1714-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1850075#L779-42 assume 1 == ~t7_pc~0; 1850069#L780-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1850065#L790-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1850061#L791-14 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1850057#L1722-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1850053#L1722-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1850047#L798-42 assume !(1 == ~t8_pc~0); 1850041#L798-44 is_transmit8_triggered_~__retres1~8#1 := 0; 1850037#L809-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1849987#L810-14 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1849982#L1730-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1849977#L1730-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1849969#L817-42 assume 1 == ~t9_pc~0; 1849962#L818-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1849957#L828-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1849952#L829-14 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1849947#L1738-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1849942#L1738-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1849932#L836-42 assume !(1 == ~t10_pc~0); 1849926#L836-44 is_transmit10_triggered_~__retres1~10#1 := 0; 1849921#L847-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1849917#L848-14 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1849868#L1746-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1849864#L1746-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1849858#L855-42 assume 1 == ~t11_pc~0; 1849852#L856-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 1849848#L866-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1849845#L867-14 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1849842#L1754-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 1849794#L1754-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1849745#L874-42 assume 1 == ~t12_pc~0; 1849740#L875-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 1849734#L885-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1849683#L886-14 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1849678#L1762-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 1849674#L1762-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 1849669#L893-42 assume 1 == ~t13_pc~0; 1849618#L894-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 1849612#L904-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 1849606#L905-14 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 1849600#L1770-42 assume !(0 != activate_threads_~tmp___12~0#1); 1849595#L1770-44 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 1849589#L912-42 assume 1 == ~t14_pc~0; 1849583#L913-14 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 1849577#L923-14 is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 1849571#L924-14 activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 1849565#L1778-42 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 1849560#L1778-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1849554#L1495-3 assume !(1 == ~M_E~0); 1806402#L1495-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1849544#L1500-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1849538#L1505-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1849532#L1510-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1849527#L1515-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1849521#L1520-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1849516#L1525-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1843946#L1530-3 assume !(1 == ~T8_E~0); 1849505#L1535-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1849499#L1540-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 1849494#L1545-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 1849488#L1550-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 1849483#L1555-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 1849477#L1560-3 assume 1 == ~T14_E~0;~T14_E~0 := 2; 1849471#L1565-3 assume !(1 == ~E_1~0); 1849465#L1570-3 assume !(1 == ~E_2~0); 1849460#L1575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1849454#L1580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1849449#L1585-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1849443#L1590-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1849437#L1595-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1849431#L1600-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1849426#L1605-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1836441#L1610-3 assume !(1 == ~E_10~0); 1849416#L1615-3 assume 1 == ~E_11~0;~E_11~0 := 2; 1849410#L1620-3 assume 1 == ~E_12~0;~E_12~0 := 2; 1849404#L1625-3 assume 1 == ~E_13~0;~E_13~0 := 2; 1849398#L1630-3 assume 1 == ~E_14~0;~E_14~0 := 2; 1849393#L1635-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 1849119#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 1849097#L1100-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 1849089#L1101-1 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 1849080#L2036 assume !(0 == start_simulation_~tmp~3#1); 1849070#L2036-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 1848789#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 1848778#L1100-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 1848771#L1101-2 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 1848753#L1991 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 1848752#L1998 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1848751#L1999 start_simulation_#t~ret37#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 1848749#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 1720263#L2017-2 [2021-12-16 10:06:47,751 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:47,751 INFO L85 PathProgramCache]: Analyzing trace with hash -528143516, now seen corresponding path program 1 times [2021-12-16 10:06:47,752 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:47,755 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1575290158] [2021-12-16 10:06:47,755 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:47,755 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:47,762 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:06:47,777 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:06:47,777 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:06:47,777 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1575290158] [2021-12-16 10:06:47,778 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1575290158] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:06:47,778 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:06:47,778 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:06:47,778 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1235151897] [2021-12-16 10:06:47,778 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:06:47,778 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-16 10:06:47,778 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-16 10:06:47,779 INFO L85 PathProgramCache]: Analyzing trace with hash 1949464075, now seen corresponding path program 1 times [2021-12-16 10:06:47,779 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-16 10:06:47,779 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [537407640] [2021-12-16 10:06:47,779 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-16 10:06:47,779 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-16 10:06:47,786 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-16 10:06:47,799 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-16 10:06:47,800 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-16 10:06:47,800 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [537407640] [2021-12-16 10:06:47,800 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [537407640] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-16 10:06:47,800 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-16 10:06:47,800 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-16 10:06:47,800 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1033435159] [2021-12-16 10:06:47,800 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-16 10:06:47,800 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-16 10:06:47,801 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-16 10:06:47,801 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-16 10:06:47,801 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-16 10:06:47,801 INFO L87 Difference]: Start difference. First operand 292063 states and 415135 transitions. cyclomatic complexity: 123136 Second operand has 4 states, 4 states have (on average 42.5) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-16 10:06:50,954 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-16 10:06:50,955 INFO L93 Difference]: Finished difference Result 829360 states and 1174666 transitions. [2021-12-16 10:06:50,975 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-16 10:06:50,976 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 829360 states and 1174666 transitions.